ISPLSI5512VA-100LQ208 [LATTICE]
In-System Programmable 3.3V SuperWIDE⑩ High Density PLD; 在系统可编程3.3V SuperWIDE⑩高密度PLD
| 型号： | ISPLSI5512VA-100LQ208 |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | In-System Programmable 3.3V SuperWIDE⑩ High Density PLD |
| 文件： | 总26页 (文件大小：331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispLSI 5512VA
In-System Programmable
3.3V SuperWIDE™ High Density PLD
— Superior Quality of Results
Features
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
• SuperWIDE HIGH-DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 24000 PLD Gates / 512 Macrocells
— Up to 288 I/O Pins
Functional Block Diagram
— 512 Registers
Input Bus
Input Bus
Input Bus
Input Bus
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for
Optimum Performance
Boundary
Scan
Interface
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package
Options
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 110 MHz Maximum Operating Frequency
— tpd = 8.5 ns Propagation Delay
— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,
tsu3 (CLK2/3) = 3.5ns
Global Routing Pool
(GRP)
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
Input Bus
Input Bus
Input Bus
Input Bus
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
ispLSI 5000V Description
The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with Single-
Level Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
— Slew and Skew Programmable I/O (SASPI/O™)
Supports Programmable Bus Hold, Pull-up, Open
Drain and Slew and Skew Rate Options
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are pro-
vided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and five extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
in both true and complement form for every product term.
— Six Global Output Enable Terms, Two Global OE
Pins and One Product Term OE per Macrocell
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
5512va_04
1
Specifications ispLSI 5512VA
Functional Block Diagram
Figure 1. ispLSI 5512VA Functional Block Diagram (388 BGA Option)
Input Bus
Input Bus
Input Bus
Input Bus
TDI
Boundary
Scan
Interface
TDO
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
VCCIO
1
I/O 0 / TOE
I/O 1
I/O 215
I/O 214
I/O 213
I/O 212
I/O 2
I/O 3
I/O 14
I/O 15
I/O 16
I/O 17
I/O 201
I/O 200
I/O 199
I/O 198
I/O 18
I/O 19
I/O 20
I/O 21
I/O 197/CLK3
I/O 196
I/O 195
I/O 194
I/O 32
I/O 33
I/O 34
I/O 35
I/O 183
I/O 182
I/O 181
I/O 180
Global Routing Pool
(GRP)
I/O 179/CLK2
I/O 178
I/O 36
I/O 37
I/O 38
I/O 39
I/O 177
I/O 176
I/O 165
I/O 164
I/O 163
I/O 162
I/O 50
I/O 51
I/O 52
I/O 53
I/O 161
I/O 160
I/O 159
I/O 158
I/O 54
I/O 55
I/O 56
I/O 57
I/O 147
I/O 146
I/O 145
I/O 144
I/O 68
I/O 69
I/O 70
I/O 71
Generic
Generic
Generic
Generic
Logic Block
Logic Block
Logic Block
Logic Block
Input Bus
Input Bus
Input Bus
Input Bus
GSET/GRST
1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is
determined by the package type used – see table below.
Package Type
388 BGA
272 BGA
Multiplexed Signals
I/O 197 / CLK3
I/O 131 / CLK 3
I/O 98 / CLK 3
I/O 179 / CLK2
I/O 119 / CLK2
I/O 89 / CLK2
I/O 0 / TOE
I/O 0 / TOE
I/O 0 / TOE
208 PQFP
2
Specifications ispLSI 5512VA
4mAandsink8mAin3.3Vmode. Theoutputdrivershave
a separate VCCIO reference input which is independent
ofthemainVCCsupplyforthedevice.Thisfeatureallows
the output drivers to drive either 3.3V or 2.5V output
levels while the device logic and the output current drive
is always powered from 3.3V. The output drivers also
provide individually programmable edge rates and open
drain capability. A programmable pullup resistor is pro-
vided to tie off unused inputs and a programmable
bus-hold latch is available to hold tristate outputs in their
last valid state until the bus is driven again by some
device.
ispLSI 5000V Description (Continued)
The 160 product terms are grouped in 32 sets of five and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be by-
passed for functions of five product terms or less. The
five extra product terms are used for shared GLB con-
trols, set, reset, clock, clock enable and output enable.
The32registeredmacrocellsintheGLBaredrivenbythe
32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. The macrocells each have two
outputs, which can be fed back through the Global
Routing Pool. This dual output capability from the
macrocell allows efficient use of the hardware resources.
One output can be a registered function for example,
while the other output can be an unrelated combinatorial
function. AdirectregisterinputfromtheI/Opadfacilitates
efficient use of this feature to construct high-speed input
registers.
The ispLSI 5000V Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface. Boundary Scan test is also
supported through the same interface.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
Macrocell registers can be clocked from one of several
global or product term clocks available on the device. A
global and product term clock enable is also provided,
eliminating the need to gate the clock to the macrocell
registers. Reset and preset for the macrocell register is
provided from both global and product term signals. The
macrocell register can be programmed to operate as a D-
type register, a D-type latch or a T-type flip flop.
ispLSI 5000V Family Members
The ispLSI 5000V Family ranges from 256 macrocells to
512 macrocells and operates from a 3.3V power supply.
All family members will be available with multiple pack-
age options. The ispLSI 5000V Family device matrix
showingthevariousbondoutoptionsisshowninthetable
below.
The 32 outputs from the GLB can drive both the Global
RoutingPoolandthedeviceI/Ocells.TheGlobalRouting
Pool contains one line from each macrocell output and
one line from each I/O pin.
Theinterconnectstructure(GRP)isverysimilartoLattice's
existing ispLSI 1000, 2000 and 3000 families, but with an
enhanced interconnect structure for optimal pin locking
and logic routing. This eliminates the need for registered
I/O cells or an Output Routing Pool.
The input buffer threshold has programmable TTL/3.3V/
2.5V compatible levels. The output driver can source
Table 1. ispLSI 5000VA Family
Package Type
Device
GLBs
8
Macrocells 208 fpBGA
208 PQFP
144 I/O
272 BGA
192 I/O
192 I/O
192 I/O
388 BGA
—
ispLSI 5256VA
ispLSI 5384VA
ispLSI 5512VA
256
384
512
144 I/O
144 I/O
—
12
144 I/O
288 I/O
288 I/O
16
144 I/O
3
Specifications ispLSI 5512VA
Figure 2. ispLSI 5512VA Block Diagram (288 I/O Version)
18
18
18
I/O
18
I/O
32
32
32
32
Q
D
D
D
D
D
D
D
D
Q
Generic
Logic
Block
(GLB)
18
18
18
18
32
32
32
32
32
32
32
32
18
18
18
18
160
160
Global
Routing
Pool
5
PT
160
PT
160
PT
5
PT
5
5
5
5
160
160
5
5
5
5
68
(GRP)
68
68
68
68
18
32
18
32
Buffers/Pins
18
I/O
18
I/O
CLK2
32
32
Q
Q
160
160
5
PT
160
PT
160
PT
5
PT
160
160
68
18
32
18
32
18
I/O
18
I/O
CLK3
32
32
Q
Q
160
160
5
PT
160
PT
160
PT
5
PT
160
160
68
18
32
18
32
18
I/O
18
I/O
32
32
Q
Q
800
160
160
5
PT
160
PT
160
PT
5
PT
160
160
68
18
32
18
32
18
I/O
18
I/O
TOE
32
32
Q
D
D
Q
18
32
32
18
160
160
5
PT
160
PT
160
PT
5
PT
CLK0
CLK1
5
160
160
5
GOE0
GOE1
68
5512_384
68
SET/RESET
4
Specifications ispLSI 5512VA
Figure 3. ispLSI 5000V Generic Logic Block (GLB)
From Global Routing Pool
0
1
2
6667
Global PTOE Bus
PTSA
PT 0
PT 1
PT 2
PT 3
PT 4
Macrocell 0
From PTSA
PTSA bypass
To I/O Pad
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
To GRP
Global PTOE 0 ... 5
6
PT 9
PT 8
PT 7
PT 6
PT 5
Macrocell 1
From PTSA
PTSA bypass
To I/O Pad
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
To GRP
Global PTOE 0 ... 5
6
PT 79
PT 78
PT 77
PT 76
PT 75
Macrocell 15
From PTSA
PTSA bypass
To I/O Pad
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
Shared PT Clock 1
Shared PT (P)reset 1
To GRP
Global PTOE 0 ... 5
6
PT 159
PT 158
PT 157
PT 156
PT 155
Macrocell 31
From PTSA
PTSA bypass
To I/O Pad
PTOE
PT Clock
PT Reset
PT Preset
Shared PT Clock 0
Shared PT (P)reset 0
PT 160
PT 161
PT 162
PT 163
Shared PT Clock 1
Shared PT (P)reset 1
To GRP
Global PTOE 0 ... 5
6
PT 164
GLB_5K
Programmable
AND Array
5
Specifications ispLSI 5512VA
Figure 4. ispLSI 5000V Macrocell
VCCIO
VCC
VCCIO
Global PTOE 0
Global PTOE 1
Global PTOE 2
Global PTOE 3
Global PTOE 4
Global PTOE 5
PTOE
GOE0
GOE1
TOE
PTSA bypass
I/O Pad
Delay
D
Q
PTSA
D/T
Slew Open
rate drain
Shared PT Clock 0
Shared PT Clock 1
2.5V/3.3V
Output
Clk En
PT Clock
PT Reset
To GRP
R/L
P
CLK0
CLK1
CLK2
CLK3
Clk
R
D
D
Q
Q
SET/RESET
D/T
Clk En
Clk
Register/
Latch
Shared PT (P)reset 0
Shared PT (P)reset 1
PT Preset
Programmable
Speed/Power
Option
R
P
6
Specifications ispLSI 5512VA
speed. The clock inversion is available on the remaining
CLK1 - CLK3 signals. By sharing the pins with the I/O
pins, CLK2 and CLK3 can not only be inverted but also is
available for logic implementation through GRP signal
routing. Figure 5 shows these different clock distribution
options.
Global Clock Distribution
The ispLSI 5000V Family has four dedicated clock input
pins: CLK0 - CLK3. CLK0 input is used as the dedicated
master clock that has the lowest internal clock skew with
no clock inversion to maintain the fastest internal clock
Figure 5. ispLSI 5000V Global Clock Structure
CLK 0
CLK 1
CLK0
CLK1
IO/CLK 2
To GRP
CLK2
CLK3
IO/CLK 3
To GRP
GSET/GRST
SET/RESET
7
Specifications ispLSI 5512VA
Figure 6. Boundary Scan Register Circuit for I/O Pins
HIGHZ
EXTEST
SCANIN
(from previous
cell)
TOE
BSCAN
Registers
BSCAN
Latches
Normal
Function
0
OE
D
D
D
Q
Q
Q
D
Q
1
EXTEST
PROG_MODE
Normal
0
Function
I/O Pin
D
Q
1
SCANOUT
(to next cell)
Shift DR
Clock DR
Update DR
Reset
Figure 7. Boundary Scan Register Circuit for Input-Only Pins
Input Pin
SCANIN
(from previous
cell)
SCANOUT
(to next cell)
D
Q
Shift DR
Clock DR
8
Specifications ispLSI 5512VA
Figure 8. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
T
T
bth
btsu
T
T
T
btcp
btch
btcl
TCK
TDO
T
T
T
btoz
btvo
btco
Valid Data
Valid Data
T
T
btcpsu
btcph
Data to be
captured
Data Captured
T
T
T
btuoz
btuov
btuco
Data to be
driven out
Valid Data
Valid Data
SYMBOL
PARAMETER
MIN
MAX UNITS
t
125
62.5
62.5
25
25
50
–
–
ns
ns
btcp
btch
TCK [BSCAN test] clock pulse width
TCK [BSCAN test] pulse width high
TCK [BSCAN test] pulse width low
TCK [BSCAN test] setup time
t
t
–
–
ns
btcl
t
t
t
t
t
t
t
t
t
t
t
–
ns
btsu
bth
–
ns
TCK [BSCAN test] hold time
–
mV/ns
ns
rf
TCK [BSCAN test] rise and fall time
TAP controller falling edge of clock to valid output
25
25
25
–
btco
btoz
btvo
btcpsu
btcph
btuco
btuoz
btuov
–
ns
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
–
ns
25
25
–
ns
–
ns
BSCAN test Capture register hold time
50
50
50
ns
BSCAN test Update reg, falling edge of clock to valid output
–
ns
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
–
ns
9
Specifications ispLSI 5512VA
1, 2
Absolute Maximum Ratings
Supply Voltage V .................................. -0.5 to +5.4V
cc
Input Voltage Applied............................... -0.5 to +5.6V
Tri-Stated Output Voltage Applied........... -0.5 to +5.6V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (T ) with Power Applied ... 150°C
J
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Condition
SYMBOL
PARAMETER
Supply Voltage
I/O Reference Voltage
MIN.
3.00
3.00
2.3
MAX.
3.60
3.60
3.60
UNITS
T
T
= 0°C to +70°C
Commercial
Industrial
V
V
V
A
A
V
V
CC
CCIO
= -40°C to +85°C
Table 2 - 0005/5000
Capacitance (TA=25°C,f=1.0 MHz)
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
CC= 3.3V, VI/O = 2.0V
CC= 3.3V, VCK = 2.0V
CC= 3.3V, VG = 2.0V
10
pf
V
I/O Capacitance
C1
C2
C3
10
10
pf
pf
V
Clock Capacitance
V
Global Input Capacitance
Table 2 - 0006/5384
Erase Reprogram Specification
PARAMETER
MINIMUM
MAXIMUM
UNITS
Cycles
ispLSI Erase/Reprogram Cycles
10000
–
Table 2-0008/3320
10
Specifications ispLSI 5512VA
Switching Test Conditions
Figure 9. Test Load
Input Pulse Levels
GND to VCCIO
min
Input Rise and Fall Time
Input Timing Reference Levels
Ouput Timing Reference Levels
Output Load
≤ 1.5ns 10% to 90%
V
CCIO
1.5V
1.5V
R
1
2
See figure
Device
Output
Test
Point
Table 2 - 0003/5384
3-state levels are measured 0.5V from steady-state
active level.
R
C *
L
Output Load Conditions (See Figure 8)
*
C includes Test Fixture and Probe Capacitance.
L
3.3V
R2
316Ω 348Ω 511Ω 475Ω 35pF
2.5V
0213D
TEST CONDITION
R1
R1
R2
CL
A
Active High
Active Low
∞
348Ω
∞
475Ω 35pF
35pF
475Ω 5pF
B
316Ω
∞
511Ω
∞
Active High to Z
at VOH-0.5V
∞
348Ω
∞
C
D
Active Low to Z
at VOL+0.5V
316Ω
∞
∞
511Ω
∞
∞
5pF
Slow Slew
∞
∞
35pF
Table 2 - 0004A/5384
DC Electrical Characteristics for 3.3V Range1
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
MIN.
3.0
-0.3
2.0
–
TYP. MAX. UNITS
I/O Reference Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–
–
–
–
–
3.6
0.8
5.25
0.4
–
V
V
V
V
V
V
V
V
V
V
CCIO
IL
VOH ≤ VOUT or VOUT ≤ VOL (max)
VOH ≤ VOUT or VOUT ≤ VOL (max)
IOL = 8 mA
IH
OL
OH
IOH = -4 mA
2.4
Table 2-0007/5512VA
1. I/O voltage configuration must be set to VCC.
11
Specifications ispLSI 5512VA
DC Electrical Characteristics for 2.5V Range1
Over Recommended Operating Conditions
PARAMETER CONDITION
I/O Reference Voltage
SYMBOL
MIN.
2.3
TYP. MAX. UNITS
–
–
–
2.7
0.7
V
V
V
V
V
V
CCIO
IL
Input Low Voltage
Input High Voltage
-0.3
1.7
VOH(min) ≤ VOUT or VOUT ≤ VOL(max)
VOH(min) ≤ VOUT or VOUT ≤ VOL(max)
VCCIO=min, VIN=VIH or VIL, IOL= 100µA
5.25
IH
–
–
–
–
–
–
0.2
0.7
–
V
V
V
Output Low Voltage
Output High Voltage
VOL
VCCIO=min, VIN=VIH or VIL, IOL= 2mA
VCCIO=min, VIN=VIH or VIL, IOH= -100µA
VCCIO=min, VIN=VIH or VIL, IOH= -2mA
2.1
1.7
V
OH
–
V
2.5V/5512VA
1. I/O voltage configuration must be set to VCCIO.
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL
PARAMETER
CONDITION
0V ≤ VIN≤ VIL(Max.)
(VCCIO-0.2)V ≤ VIN ≤ VCCIO
CCIO ≤ VIN ≤ 5.25V
0V ≤ VIN ≤ VIL
MIN.
–
TYP. MAX. UNITS
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
–
–
–
–
–
–
–
–
–
–
-10
10
µA
µA
µA
µA
µA
µA
µA
µA
V
I
I
IL
–
IH
V
–
50
PU1
I/O Active Pullup Current
–
-150
–
I
I
I
I
I
I
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
40
-40
–
V
IN = VIL(max)
IN = VIH(min)
BHL
–
V
BHH
BHLO
BHLH
BHT
0V ≤ VIN ≤ VCCIO
0V ≤ VIN ≤ VCCIO
550
-550
VIH
45
–
VIL
–
Current Needed for VCCIO Pin
All I/Os Pulled-up, (Total I/Os * IPUmax
)
mA
I
VCCIO
DC Char_5512VA
1. Pullup is capable of pulling to a minimum voltage of VOH under no-load conditions.
12
Specifications ispLSI 5512VA
External Switching Characteristics
Over Recommended Operating Conditions
TEST3
COND.
-110
-100
-70
DESCRIPTION 4,5
UNITS
PARAM.
#
MIN. MAX. MIN. MAX. MIN. MAX.
6
A
A
1 Data Prop. Delay, 5PT Bypass
—
—
110
91
143
6
8.5
10
—
—
—
—
4
—
—
100
69
125
8
10
13
—
—
—
—
5.5
—
—
—
—
—
70
45
83
12
—
0
15
19
—
—
—
—
8
ns
ns
t
t
f
f
f
t
t
t
t
t
pd1
6
2 Data Propagation Delay
pd2
A
3 Clock Frequency with Internal Feedback1
4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1)
5 Clock Frequency, Max Toggle2
MHz
MHz
MHz
ns
max
—
—
—
A
max (Ext.)
max (Tog.)
su1
6 GLB Reg. Setup Time before Clk, 5PT bypass
7 GLB Reg. Clock to Output Delay
6
—
0
—
0
ns
co1
—
—
—
8 GLB Reg. Hold Time after Clock, 5PT bypass
9 GLB Reg. Setup Time before Clock
10 GLB Reg. Hold Time after Clock
—
—
—
—
—
—
ns
h1
7
9
14
0
ns
su2
h2
0
0
ns
GLB Reg. Setup Time before Clock, Input Reg.
Path (CLK0/1)
—
—
—
—
11
4.5
3.5
0
—
—
—
—
6
5
0
0
—
—
—
—
9
7
0
0
—
—
—
—
ns
ns
ns
ns
tsu3 (CLK0/1)
tsu3 (CLK2/3)
th3 (CLK0/1)
th3 (CLK2/3)
GLB Reg. Setup Time before Clock, Input Reg.
Path (CLK2/3)
12
GLB Reg. Hold Time after Clock, Input Reg. Path
(CLK0/1)
13
GLB Reg. Hold Time after Clock, Input Reg. Path
(CLK2/3)
14
0
A
15 Ext. Reset Pin to Output Delay
16 Ext. Reset Pulse Duration
—
7.5
—
17
—
—
9
20
—
12
24
8
—
14
—
—
—
6
30
—
18
30
12
—
—
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
r1
—
rw1
B/C 17 Local Product Term Output Enable/Disable
B/C 18 Global Product Term Output Enable/Disable
B/C 19 Global OE Input to Output Enable/Disable
10
20
6.5
—
—
—
—
4
ptoe/dis
gptoe/dis
goe/dis
wh
—
—
—
—
20 Ext. Sync. Clock Pulse Duration, High
21 Ext. Sync. Clock Pulse Duration, Low
3.5
3.5
—
—
—
4
6
wl
1. Standard 32-bit counter using GRP feedback.
2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
3. Reference Switching Test Conditions section.
4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, and CLK0.
5. Timing parameters measured using normal active output driver.
6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
Timing Ext.5512VA/4.0.eps
13
Specifications ispLSI 5512VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-110
-100
-70
2
PARAM
#
DESCRIPTION
MIN MAX MIN MAX MIN MAX UNIT
I/O Buffer
tidcom
tidreg
todcom
todreg
todz
22
23
24
25
26
27
28
29
30
Input Pad and Buffer, Combinatorial Input
Input Pad and Buffer, Registered Input
Output Pad and Buffer, Combinatorial Output
Output Pad and Buffer, Registered Output
Output Buffer Enable/Disable
–
–
–
–
–
–
–
–
–
0.7
4.7
2.4
1.0
1.7
0
–
–
–
–
–
–
–
–
–
0.9
6.6
1.7
2.8
1.7
0
–
–
–
–
–
–
–
–
–
1.4
9.7
2.6
4.6
2.6
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tslf
Slew Rate Adder, Fast Slew
tsls
Slew Rate Adder, Slow Slew
8.5
0.5
9.5
10
15
1
tslfd
Programmable Delay Adder, Fast Slew
Programmable Delay Adder, Slow Slew
0.7
10.7
tslsd
16
GLB/Macrocell Delay Register
tmbp
31
32
33
34
35
36
37
38
39
Macrocell Register/Latch Bypass
–
–
0
1
–
–
0
1.4
1
–
–
0
2
1
–
–
–
–
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
tmlat
Macrocell Latch Delay
tmco
Macrocell Register/Latch Clock to Output
Macrocell Register/Latch Setup Time
Macrocell Register/Latch Hold Time
Macrocell Register/Latch CLKEN Setup Time
Macrocell Register/Latch CLKEN Hold Time
Macrocell Register/Latch Set/Reset Time
Toggle Flip-Flop Feedback
–
1.8
–
–
–
tmsu
1
1.1
3.9
1.4
1.4
–
–
1.7
5.3
2
tmh
2.5
1
–
–
tmsuce
tmhce
tmrst
–
–
1
–
–
2
–
1.8
1
1.4
1.3
–
tftog
–
–
–
AND Array
tandhs
tandlp
PTSA
40
41
AND Array, High Speed Mode
AND Array, Low Power Mode
–
–
3
5
–
–
4
–
–
6
ns
ns
6.6
10
t5ptcom
t5ptreg
t5ptxcom
t5pxtreg
tptsacom
tptsareg
42
43
44
45
46
47
5 Product Term Bypass, Combinatorial
5 Product Term Bypass, Registered
5 Product Term XOR, Combinatorial
5 Product Term XOR, Registered
–
–
–
–
–
–
0.7
1
–
–
–
–
–
–
1.4
1.7
3.6
2.2
4.1
2.7
–
–
–
–
–
–
2
2.3
5
ns
ns
ns
ns
ns
ns
2.5
2.3
3
3.3
6
Product Term Sharing Array, Combinatorial
Product Term Sharing Array, Registered
2
4.3
PTSA Controls
tpck
48
49
50
51
Product Term Clock Delay
–
–
–
–
–
–
–
–
–
0.5
1
–
–
–
–
–
–
–
–
–
0.7
1.4
1.4
0.7
2.4
3.4
2
–
–
–
–
–
–
–
–
–
1
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
tpcken
tscken
tsck
Product Term CLKEN Delay
Shared Product Term CLKEN Delay
Shared Product Term Clock Delay
Product Term Sharing Array CLKEN Delay
Shared Product Term Set/Reset Delay
Product Term Set/Reset Delay
1
2
0.5
2.0
2.5
1.5
2.9
13.1
1
tptsacken 52
4
tsrst
tprst
tpoe
tgpoe
53
54
55
56
5
3
Product Term Output Enable/Disable
Global PT Output Enable/Disable
3.4
15.4
5
17
1. Internal Timing Parameters are not tested and are for reference only.
Refer to Timing Model in this data sheet for further details.
Timing Rev 4.0
14
Specifications ispLSI 5512VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-110
-100
-70
2
PARAM
GRP
#
DESCRIPTION
MIN MAX MIN MAX MIN MAX UNIT
tgrpi
57
58
GRP Delay from I/O Pad
GRP Delay from Macrocell
–
–
1.5
1.2
–
–
2
–
–
3
ns
ns
tgrpm
1.2
1.2
Global Control Delays
tgclk01
tgclk23
tgclken0
tgclken1
tgrst
59
60
61
62
63
64
65
Global Clock 0 or 1 Delay
Global Clock 2 or 3 Delay
Global CLKEN 0 Delay
Global CLKEN 1 Delay
Global Set/Reset Delay
Global OE Delay
–
–
–
–
–
–
–
1.2
2.2
1.7
2.7
14.2
4.8
4.7
–
–
–
–
–
–
–
1.7
2.7
2.4
3.4
15.8
6.3
6.2
–
–
–
–
–
–
–
2.4
4.4
3.4
5.4
23.4
9.4
9.4
ns
ns
ns
ns
ns
ns
ns
tgoe
ttoe
Test OE Delay
1. Internal Timing Parameters are not tested and are for reference only.
Refer to Timing Model in this data sheet for further details.
Timing Rev 4.0
ispLSI 5512VA Timing Model
Output
Buffer
Input
Buffer
GRP
GLB/Macrocell
I/O
Pad
I/O
Pad
Buffer Delays
Slew
t
t
t
#20
#56
#28
#27
grpm
slsd
slfd
t
t
t
#22
#23
#24
t
odcom
odreg
odz
idcom
t
#37
ftog
t
#55 grpi
#25
#26
t
t
t
PTSA
Register
slf
sls
idreg
#21
OUTPUT
INPUT
t
t
t
t
t
t
#40
#44
#42
#41
#45
#43
5ptcom
ptsacom
5ptxcom
5ptxreg
ptsareg
5ptreg
t
t
t
#29
#30
#32
mbp
mlat
msu
AND Array
#38
t
t
#33
mh
#31
#35
#34
mco
t
andhs
t
t
mhce
msuce
t
andlp
Dedicated
Input Buffers
t
#36
mrst
#39
PT Controls
t
t
t
t
t
t
t
#57
#58
#59
#60
#61
#62
#63
t
gclk0
#49
sck
t
#46 pck
gclk123
gclken0
Input
Pad
t
#50 ptsacken
tpcken
tscken
gclken1
grst
#47
#48
goe
toe
t
#51
srst
t
#52 prst
t
t
#53
#54
poe
gpoe
15
Specifications ispLSI 5512VA
Power Consumption
Power consumption in the ispLSI 5512VA device de- setting operates product terms at their normal full power
pends on two primary factors: the speed at which the consumption. For portions of the logic that can tolerate
device is operating and the number of product terms longer propagation delays, selecting the slower “low-
used. The product terms have a fuse-selectable speed/ power” setting will significantly reduce the power
power tradeoff setting. Each group of four product terms dissipation for these product terms. Figure 10 shows the
has a single speed/power tradeoff control fuse that acts relationship between power and operating speed.
on the complete group of four. The fast “high-speed”
Figure 10. Typical Device Power Consumption vs fmax
800
750
ispLSI 5512VA
High Speed Mode
700
650
600
550
500
450
400
350
ispLSI 5512VA
Low Power Mode
300
250
200
0
20
40
60
fmax (MHz)
80
100
120
Notes: Configuration of 32 16-bit Counters
Typical Current at 3.3V, 25° C
I
can be estimated for the ispLSI 5512VA using the following equation:
CC
High Speed Mode: ICC = 70 + (# of PTs * 0.4592) + (# of nets * Max. freq * 0.00391)
Low Power Mode: ICC = 70 + (# of PTs * 0.160) + (# of nets * Max. freq * 0.00391)
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The I
estimate is based on typical conditions (V
= 3.3V, room temperature) and an assumption of 2 GLB loads
is sensitive to operating conditions
CC
CC
on average exists. These values are for estimates only. Since the value of I
and the program in the device, the actual I
CC
should be verified.
CC
0127/5512va
16
Specifications ispLSI 5512VA
Signal Descriptions
Signal Name
Description
TMS
Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine.
Input - This pin is the Test Clock input pin used to clock through the JTAG state machine.
Input - This pin is the JTAG Test Data In pin used to load data.
TCK
TDI
TDO
Output - This pin is the JTAG Test Data Out pin used to shift data out.
TOE / I/O0
Input/Output-ThispinfunctionsaseithertheTestOutputEnablepinoranI/Opinbaseduponcustomer's
design. TOE tristates all I/O pins when a logic low is driven.
GOE0, GOE1
GSET/GRST
Input - These two pins are the Global Output Enable input pins.
Dedicated Set/Reset Input - This pin is available to all registers in the device and can independently be
configured as preset, reset or no effect on each register. The global polarity (active high or low input)
for this pin is also selectable.
I/O
Input/Output – These are the general purpose I/O used by the logic array.
GND
Ground
No connect.
Vcc
NC1
VCC
CLK0, CLK1
Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock
input to all registers in the device.
CLK2 / I/O,
CLK3 / I/O
Input/Output - These pins function as either dedicated clock inputs for all registers or an I/O
pin based upon customer's design. Both clocks are muxed before being used as the clock input
to all registers in the device.
VCCIO
Input - This pin is used if an optional 2.5V output is to be used. Every I/O can independently select either
3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must
be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current
from this supply.
1. NC pins are not to be connected to any active signals, VCC or GND.
17
Specifications ispLSI 5512VA
208-Pin PQFP Signal Locations
Signal
Pin
GOE0, GOE1
TOE / I/O0
GSET/GRST
TCK
78, 79
32
138
29
TDI
30
TDO
136
28
TMS
CLK0, CLK1
CLK2 / I/O89
CLK3 / I/O98
VCCIO
184,185
162
173
137
GND
3, 12, 19, 27, 39, 48, 58, 69, 77, 88, 99, 113, 121, 128, 135, 150, 164, 170, 179, 191, 199
7, 14, 22, 31, 41, 61, 80, 90, 110, 123, 139, 152, 156, 177, 186, 201
VCC
NC
49, 50, 51, 52, 101, 102, 103, 104, 105, 106, 107, 108, 109, 157, 158, 207, 208
1. NCs are not to be connected to any active signals, VCC or GND.
208-Pin PQFP I/O Locations
I/O #
Pin
I/O #
Pin
I/O #
Pin
I/O #
Pin
I/O #
Pin
I/O #
Pin
0*
1
2
3
4
5
6
7
8
32
33
34
35
36
37
38
40
42
43
44
45
46
47
53
54
55
56
57
59
60
62
63
64
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
65
66
67
68
70
71
72
73
74
75
76
81
82
83
84
85
86
87
89
91
92
93
94
95
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
96
97
98
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89*
90
91
92
93
94
95
140
141
142
143
144
145
146
147
148
149
151
153
154
155
159
160
161
162
163
165
166
167
168
169
96
97
98*
99
171
172
173
174
175
176
178
180
181
182
183
187
188
189
190
192
193
194
195
196
197
198
200
202
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
203
204
205
206
1
2
4
5
6
100
111
112
114
115
116
117
118
119
120
122
124
125
126
127
129
130
131
132
133
134
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
9
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
10
11
13
15
16
17
18
20
21
23
24
25
26
* I/O 89 is multiplexed with CLK2, I/O 98 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
18
Specifications ispLSI 5512VA
388-Ball BGA Signal Locations
Signal
Ball
GOE0, GOE1
TOE / I/O0
GSET/GRST
TCK
AF14, AD13
T1
L25
T2
TDI
R3
TDO
N24
TMS
R1
CLK0, CLK1
CLK2 / I/O179
CLK3 / I/O197
VCCIO
A13, C14
A23
B17
M26
GND
A1, A2, A26, B2, B25, B26, C3, C24, D4, D9, D14, D19, D23, H4, J23, L11, L12, L13, L14, L15, L16,
M11, M12, M13, M14, M15, M16, N4, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16,
P23, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16, V4, W23, AC4, AC8, AC13, AC18,
AC23, AD3, AD24, AE1, AE2, AE25, AF1, AF25, AF26
VCC
NC1
D6, D11, D16, D21, F4, F23, L4, L23, T4, T23, AA4, AA23, AC6, AC11, AC16, AC21
C9, D2, E24, L1, AC25, AF19
1. NCs are not to be connected to any active signals, VCC or GND.
19
Specifications ispLSI 5512VA
388-Ball BGA I/O Locations (Sorted by I/O)
I/O #
Ball
I/O #
Ball
I/O #
Ball
I/O #
Ball
I/O #
Ball
I/O #
Ball
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179*
180
181
182
183
184
185
186
187
188
189
190
191
M24
L26
M23
K25
L24
K26
K23
J25
K24
J26
H25
H26
J24
192
193
194
195
196
197*
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
D18
A19
C19
B18
A18
B17
C18
A17
D17
B16
C17
A16
B15
A15
C16
B14
D15
A14
C15
B13
D13
B12
C13
A12
B11
C12
A11
D12
B10
C11
A10
D10
B9
C10
A9
B8
A8
B7
D8
A7
C8
B6
D7
A6
C7
B5
A5
C6
0*
1
2
3
4
5
6
7
8
T1
R4
U2
T3
U1
U4
V2
U3
V1
W2
W1
V3
Y2
W4
Y1
W3
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
B4
D5
A4
C5
B3
C4
A3
B1
C2
C1
D3
D1
E2
E4
E3
E1
F2
G4
F3
F1
G2
G1
G3
H2
J4
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
AC9
AF8
AD8
AE9
AF9
AE10
AD9
96
97
98
99
AE23
AC22
AF23
AD22
AE24
AD23
AF24
AE26
AD25
AD26
AC24
AC26
AB25
AB23
AB24
AB26
AA25
Y23
AA24
AA26
Y25
Y26
Y24
W25
V23
W26
W24
V25
V26
U25
V24
U26
U23
T25
U24
T26
R25
R26
T24
P25
R23
P26
R24
N25
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
AF10
AC10
AE11
AD10
AF11
AE12
AF12
AD11
AE13
AC12
AF13
AD12
AE14
AC14
AE15
AD14
AF15
AE16
AD15
AF16
AC15
AE17
AD16
AF17
AC17
AE18
AD17
AF18
AE19
AD18
AE20
AC19
AF20
AD19
AE21
AC20
AF21
AD20
AE22
AF22
AD21
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
G25
H23
G26
H24
F25
G23
F26
G24
E25
E26
F24
D25
E23
D26
C25
D24
C26
A25
B24
A24
B23
C23
A23
B22
D22
C22
A22
B21
D20
C21
A21
B20
A20
C20
B19
AA2
Y4
AA1
Y3
AB2
AB1
AA3
AC2
AB4
AC1
AB3
AD2
AC3
AD1
AF2
AE3
AF3
AE4
AD4
AF4
AE5
AC5
AD5
AF5
AE6
AC7
AD6
AF6
AE7
AF7
AD7
AE8
H1
H3
J2
J1
K2
J3
K1
K4
L2
K3
M2
M1
L3
N2
M4
N1
M3
P2
P4
P1
N3
R2
P3
N23
N26
P24
M25
* I/O 179 is multiplexed with CLK2, I/O 197 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
20
Specifications ispLSI 5512VA
388-Ball BGA I/O Locations (Sorted by Ball)
I/O #
Ball
I/O #
Ball
I/O #
Ball
I/O #
Ball
I/O #
Ball
I/O #
Ball
16
22
114
112
115
21
20
26
24
109
110
108
111
25
23
28
37
41
48
56
64
68
75
79
86
90
97
106
107
29
27
34
38
42
46
50
54
58
62
66
70
73
77
81
84
88
92
95
AA02
AA03
AA24
AA25
AA26
AB01
AB02
AB03
AB04
AB23
AB24
AB25
AB26
AC01
AC02
AC03
AC05
AC07
AC09
AC10
AC12
AC14
AC15
AC17
AC19
AC20
AC22
AC24
AC26
AD01
AD02
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
246
242
238
235
231
228
226
222
218
215
209
205
203
199
196
193
189
187
183
179*
176
174
247
244
240
237
233
229
227
224
220
216
213
211
207
204
201
197*
195
191
188
184
180
177
175
249
248
245
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B01
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
C01
C02
C04
282
287
283
142
135
137
286
1
136
138
132
133
0*
P02
P03
P04
P24
P25
P26
R02
R04
R23
R24
R25
R26
T01
T03
T24
T25
T26
U01
U02
U03
U04
U23
U24
U25
U26
V01
V02
V03
V23
V24
V25
V26
W01
W02
W03
W04
W24
W25
W26
Y01
Y02
Y03
Y04
Y23
Y24
Y25
Y26
AA01
99
101
104
105
31
33
36
40
44
47
51
53
57
60
63
67
69
72
76
80
83
85
89
93
96
100
103
30
32
35
39
43
45
49
52
55
59
61
65
71
74
78
82
87
91
94
98
102
AD22
AD23
AD25
AD26
AE03
AE04
AE05
AE06
AE07
AE08
AE09
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE26
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
AF11
AF12
AF13
AF15
AF16
AF17
AF18
AF20
AF21
AF22
AF23
AF24
243
239
236
232
225
221
217
214
210
206
202
198
194
190
186
182
178
171
173
251
250
241
234
230
223
219
212
208
200
192
185
181
172
168
170
255
252
254
253
169
165
166
259
256
258
167
161
163
C05
C06
C07
C08
C10
C11
C12
C13
C15
C16
C17
C18
C19
C20
C21
C22
C23
C25
C26
D01
D03
D05
D07
D08
D10
D12
D13
D15
D17
D18
D20
D22
D24
D25
D26
E01
E02
E03
E04
E23
E25
E26
F01
F02
F03
F24
F25
F26
261
260
262
257
162
164
157
159
265
263
266
158
160
154
155
268
267
270
264
156
151
153
271
269
274
272
150
152
147
149
273
277
148
145
276
275
281
279
146
144
143
280
278
285
140
139
141
284
G01
G02
G03
G04
G23
G24
G25
G26
H01
H02
H03
H23
H24
H25
H26
J01
3
134
129
131
4
2
7
J02
J03
J04
J24
J25
J26
5
128
130
125
127
8
K01
K02
K03
K04
K23
K24
K25
K26
L02
L03
L24
L26
M01
M02
M03
M04
M23
M24
M25
N01
N02
N03
N23
N25
N26
P01
6
11
120
126
123
124
10
9
15
13
122
119
121
14
12
19
17
113
118
116
117
18
* I/O 179 is multiplexed with CLK2, I/O 197 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
21
Specifications ispLSI 5512VA
Signal Locations (272-Ball BGA)
Signal
Ball
GOE0, GOE1
TOE / I/O 0
GSET/GRST
TCK
V11, U11
M2
J18
L4
TDI
M1
TDO
J20
TMS
L3
CLK0, CLK1
CLK2 / I/O 119
CLK3 / I/O 131
VCCIO
C10, D10
A18
B13
J19
GND
A1, D4, D8, D13, D17, H4, H17, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10,
M11, M12, N4, N17, U4, U8, U13, U17
VCC
NC1
D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15
U1, W1, E2, U2, W2, Y2, B3, C3, D3, U3, C5, W4, T4, Y12, A17, T17, W17, B18, C18, B19, C19, D19,
W19, B20, T20, W20, Y20, P19, R3
1. NCs are not to be connected to any active signals, VCC or GND.
22
Specifications ispLSI 5512VA
272-Ball BGA I/O Locations (Sorted by I/O)
I/O #
Ball
I/O #
Ball
I/O #
Ball
I/O #
Ball
I/O #
Ball
I/O #
Ball
0*
1
2
3
4
5
6
7
8
M2
M3
M4
N1
N2
N3
P1
P2
R1
P3
R2
T1
P4
T2
T3
V1
V2
V3
Y1
W3
V4
U5
Y3
Y4
V5
W5
Y5
V6
U7
W6
Y6
V7
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
W7
Y7
V8
W8
Y8
U9
V9
W9
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
U16
V17
W18
Y19
V18
V19
U19
U18
V20
U20
T18
T19
R18
P17
R19
R20
P18
P20
N18
N19
N20
M17
M18
M19
M20
L19
L18
L20
K20
K19
K18
K17
96
97
98
99
J17
128
129
130
131*
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
B14
A14
C13
B13
A13
D12
C12
B12
A12
B11
C11
A11
A10
B10
A9
B9
C9
D9
A8
B8
C8
A7
B7
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
A3
D5
C4
B2
A2
B1
C2
D2
E4
C1
D1
E3
E1
F3
G4
F2
F1
G3
G2
G1
H3
H2
H1
J4
H20
H19
H18
G20
G19
F20
G18
F19
E20
G17
F18
E19
D20
E18
C20
E17
D18
A20
A19
B17
C17
D16
A18
C16
B16
A16
C15
D14
B15
A15
C14
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119*
120
121
122
123
124
125
126
127
Y9
9
W10
V10
Y10
Y11
W11
W12
V12
U12
Y13
W13
V13
Y14
W14
Y15
V14
W15
Y16
U14
V15
W16
Y17
V16
Y18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A6
C7
B6
A5
D7
C6
B5
A4
J3
J2
J1
K2
K3
K1
L1
L2
B4
* I/O 119 is multiplexed with CLK2, I/O 131 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
23
Specifications ispLSI 5512VA
272-Ball BGA I/O Locations (Sorted by Ball)
I/O #
164
160
158
154
151
149
146
142
140
139
136
132
129
126
122
119*
115
114
165
163
159
157
153
150
147
143
141
137
135
131*
128
125
Ball
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A18
A19
A20
B1
B2
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
I/O #
121
116
169
166
162
156
152
148
144
138
134
130
127
123
120
117
111
170
167
161
155
145
133
124
118
113
109
172
171
168
112
110
Ball
B16
B17
C1
C2
C4
C6
C7
C8
C9
C11
C12
C13
C14
C15
C16
C17
C20
D1
D2
D5
D7
D9
D12
D14
D16
D18
D20
E1
E3
E4
E17
E18
I/O #
108
105
176
175
173
107
104
102
179
178
177
174
106
103
101
100
182
181
180
99
Ball
E19
E20
F1
F2
F3
F18
F19
F20
G1
G2
G3
I/O #
93
92
190
191
90
89
91
0*
1
Ball
K19
K20
L1
I/O #
11
13
14
74
75
21
28
37
48
58
64
71
70
73
15
16
17
20
24
27
31
34
38
42
47
51
55
59
62
65
68
69
Ball
T1
T2
I/O #
72
19
25
29
32
35
39
41
45
46
50
53
56
60
66
18
22
23
26
30
33
36
40
43
44
49
52
54
57
61
63
67
Ball
V20
W3
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W18
Y1
Y3
Y4
Y5
Y6
T3
L2
T18
T19
U5
U7
U9
U12
U14
U16
U18
U19
U20
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V12
V13
V14
V15
V16
V17
V18
V19
L18
L19
L20
M2
M3
M4
M17
M18
M19
M20
N1
N2
N3
N18
N19
N20
P1
P2
P3
P4
2
85
86
87
88
3
4
5
82
83
84
6
G4
G17
G18
G19
G20
H1
H2
H3
H18
H19
H20
J1
J2
J3
J4
J17
K1
K2
K3
K17
K18
Y7
Y8
Y9
98
97
7
9
186
185
184
183
96
189
187
188
95
12
77
80
81
8
10
76
78
79
Y10
Y11
Y13
Y14
Y15
Y16
Y17
Y18
Y19
P17
P18
P20
R1
R2
R18
R19
R20
94
* I/O 119 is multiplexed with CLK2, I/O 131 is multiplexed with CLK3 and I/O 0 is multiplexed with TOE.
24
Specifications ispLSI 5512VA
Pin Configuration
ispLSI 5512VA 208-pin PQFP (with Heat Spreader)
1
2
3
4
5
6
7
8
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
I/O 124
I/O 125
GND
I/O 126
I/O 127
I/O 128
VCC
I/O 129
I/O 130
I/O 131
I/O 132
GND
VCC
I/O 85
I/O 84
I/O 83
VCC
I/O 82
GND
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
VCC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O 133
VCC
I/O 134
I/O 135
I/O 136
I/O 137
GND
I/O 138
I/O 139
VCC
I/O 140
I/O 141
I/O 142
I/O 143
GND
GSET/GRST
VCCIO
TDO
GND
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
GND
I/O 65
I/O 64
I/O 63
I/O 62
VCC
ispLSI 5512VA
Top View
TMS
TCK
TDI
VCC
2
I/O 0 / TOE
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
GND
I/O 7
VCC
I/O 61
GND
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
GND
I/O 53
I/O 52
VCC
1
1
1
1
1
NC
NC
NC
NC
NC
1
1
1
1
NC
NC
NC
NC
208-PQFP/5512VA
1. NC pins are not to be connected to any active signal, Vcc or GND.
2. Pins have dual function capability.
25
Specifications ispLSI 5512VA
Part Number Description
ispLSI 5512VA – XXX X XXXX X
Device Family
Device Number
Speed
Grade
Blank = Commercial
I = Industrial
Package
B388 = 388-Ball BGA
B272 = 272-Ball BGA
(Thermally Enhanced)
Q208 = 208-Pin PQFP
(with Heat Spreader)
110 = 110 MHz
100 = 100 MHz
f
f
max
max
70 = 70 MHz fmax
Power
L = Low
0212/5512va
Ordering Information
COMMERCIAL
Family
fmax
110
110
110
100
100
100
70
tpd
8.5
8.5
8.5
10
Ordering Number
Package
ispLSI5512VA-110LB272
ispLSI 5512VA-110LB388
ispLSI 5512VA-110LQ208
ispLSI 5512VA-100LB272
ispLSI 5512VA-100LB388
ispLSI 5512VA-100LQ208
ispLSI 5512VA-70LB272
ispLSI 5512VA-70LB388
ispLSI 5512VA-70LQ208
272-Ball BGA
388-Ball BGA
208-Pin PQFP
272-Ball BGA
388-Ball BGA
208-Pin PQFP
272-Ball BGA
388-Ball BGA
208-Pin PQFP
10
ispLSI
10
15
70
15
70
15
INDUSTRIAL
Family
ispLSI
fmax
tpd
Ordering Number
ispLSI 5512VA-70LB388I
Package
70
15
388-Ball BGA
26
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