ISPPAC-CLK5312S-01TN48C [LATTICE]
PLL Based Clock Driver, 5312 Series, 12 True Output(s), 0 Inverted Output(s), PQFP48, LEAD FREE, TQFP-48;
| 型号： | ISPPAC-CLK5312S-01TN48C |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | PLL Based Clock Driver, 5312 Series, 12 True Output(s), 0 Inverted Output(s), PQFP48, LEAD FREE, TQFP-48 驱动 逻辑集成电路 |
| 文件： | 总56页 (文件大小：1209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
ispClock 5300S Family
In-System Programmable, Zero-Delay
Universal Fan-Out Buffer, Single-Ended
October 2007
Preliminary Data Sheet DS1010
• Up to +/- 5ns skew range
• Coarse and fine adjustment modes
Features
■ Four Operating Configurations
■ Up to Three Clock Frequency Domains
• Zero delay buffer
• Zero delay and non-zero delay buffer
• Dual non-zero delay buffer
• Non-zero delay buffer with output divider
■ Flexible Clock Reference and External
Feedback Inputs
• Programmable single-ended or differential input
reference standards
■ 8MHz to 267MHz Input/Output Operation
■ Low Output to Output Skew (<100ps)
■ Low Jitter Peak-to-Peak (< 70 ps)
- LVTTL, LVCMOS, SSTL, HSTL, LVDS,
LVPECL, Differential HSTL, Differential
SSTL
• Clock A/B selection multiplexer
• Programmable Feedback Standards
- LVTTL, LVCMOS, SSTL, HSTL
• Programmable termination
■ Up to 20 Programmable Fan-out Buffers
• Programmable single-ended output standards
and individual enable controls
- LVTTL, LVCMOS, HSTL, eHSTL, SSTL
• Programmable output impedance
- 40 to 70Ω in 5Ω increments
■ All Inputs and Outputs are Hot Socket
Compliant
• Programmable slew rate
• Up to 10 banks with individual V
- 1.5V, 1.8V, 2.5V, 3.3V
■ Full JTAG Boundary Scan Test In-System
and GND
CCO
Programming Support
■ Exceptional Power Supply Noise Immunity
■ Fully Integrated High-Performance PLL
• Programmable lock detect
■ Commercial (0 to 70°C) and Industrial
(-40 to 85°C) Temperature Ranges
• Three “Power of 2” output dividers (5-bit)
• Programmable on-chip loop filter
• Compatible with spread spectrum clocks
• Internal/external feedback
■ 48-pin and 64-pin TQFP Packages
■ Applications
• Circuit board common clock distribution
• PLL-based frequency generation
• High fan-out clock buffer
■ Precision Programmable Phase Adjustment
(Skew) Per Output
• Zero-delay clock buffer
• 8 settings; minimum step size 156ps
- Locked to VCO frequency
ispClock5300S Family Functional Diagram
LOCK
PLL_BYPASS
REFA /
REFP
SKEW
CONTROL
OUTPUT
DRIVERS
+
OUTPUT
DIVIDERS
REFB /
REFN
OUTPUT 1
1
0
V0
5-Bit
PHASE
FREQ.
DETECT
LOOP
FILTER
0
1
VCO
V1
5-bit
V2
5-bit
REFSEL
FBK
OUTPUT
ROUTING
MATRIX
OUTPUT N
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1010_01.4
Lattice Semiconductor
ispClock5300S Family Data Sheet
General Description
The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution
applications. The ispClock5312S, the first member of the ispClock5300S family, provides up to 12 single-ended
ultra low skew outputs. Each pair of outputs may be independently configured to support separate I/O standards
(LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen-
dent programmable control of termination, slew-rate, and timing skew. All configuration information is stored on-
chip in non-volatile E2CMOS® memory.
The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the
on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three
frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32).
The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing
matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output.
The ispClock5300S device can be configured to operate in four modes: zero delay buffer mode, dual non-zero
delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay
buffer mode.
The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the
ispClock5300S device family.
Table 1. ispClock5300S Family
Number of Programmable
Clock Inputs
Number of Programmable
Single-Ended Outputs
Device
ispClock5320S
ispClock5316S
ispClock5312S
ispClock5308S
ispClock5304S
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
1 Differential, 2 Single-Ended
20
16
12
8
4
Figure 1. ispClock5304S Functional Block Diagram
LOCK
RESET
PLL_BYPASS
OEX
OEY
VTT_REFA
VTT_REFB
LOCK
DETECT
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
SKEW
CONTROL
OUTPUT
DRIVERS
REFA_REFP
REFB_REFN
+
BANK_0A
BANK_0B
OUTPUT
DIVIDERS
1
0
V0
5-bit
PHASE
DETECT
LOOP
FILTER
0
1
BANK_1A
BANK_1B
VCO
V1
5-bit
SKEW
CONTROL
OUTPUT
DRIVERS
REFSEL
V2
5-bit
FBK
VTT_FBK
JTAG INTERFACE
TDI
TMS TCK TDO
2
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 2. ispClock5308S Functional Block Diagram
LOCK
RESET
PLL_BYPASS
OEX
OEY
VTT_REFA
VTT_REFB
LOCK
DETECT
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
SKEW
CONTROL
OUTPUT
DRIVERS
+
REFA_REFP
REFB_REFN
OUTPUT
DIVIDERS
BANK_0A
BANK_0B
1
0
V0
5-bit
PHASE
DETECT
LOOP
FILTER
0
1
VCO
BANK_1A
BANK_1B
V1
5-bit
BANK_2A
BANK_2B
REFSEL
V2
5-bit
BANK_3A
BANK_3B
SKEW
CONTROL
OUTPUT
DRIVERS
FBK
VTT_FBK
JTAG INTERFACE
TDI
TMS TCK TDO
Figure 3. ispClock5312S Functional Block Diagram
LOCK
RESET
PLL_BYPASS
OEX
OEY
VTT_REFA
VTT_REFB
LOCK
DETECT
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
SKEW
CONTROL
OUTPUT
DRIVERS
REFA_REFP
REFB_REFN
+
OUTPUT
DIVIDERS
BANK_0A
BANK_0B
1
0
V0
5-bit
PHASE
DETECT
LOOP
FILTER
0
1
VCO
BANK_1A
BANK_1B
V1
5-bit
BANK_2A
BANK_2B
REFSEL
V2
5-bit
FBK
BANK_3A
BANK_3B
VTT_FBK
BANK_4A
BANK_4B
BANK_5A
BANK_5B
JTAG INTERFACE
SKEW
CONTROL
OUTPUT
DRIVERS
TDI
TMS TCK TDO
3
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 4. ispClock5316S Functional Block Diagram
LOCK
RESET
PLL_BYPASS
OEX
OEY
VTT_REFA
VTT_REFB
LOCK
DETECT
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
SKEW
CONTROL
OUTPUT
DRIVERS
REFA_REFP
REFB_REFN
OUTPUT
DIVIDERS
BANK _0A
BANK _0B
1
0
V0
5-bit
PHASE
DETECT
LOOP
FILTER
0
1
VCO
BANK _1A
BANK _1B
V1
5-bit
BANK _2A
BANK _2B
REFSEL
V2
5-bit
BANK _3A
FBK
BANK _3B
VTT_FBK
BANK _4A
BANK _4B
BANK _5A
BANK _5B
BANK _6A
BANK _6B
BANK _7A
BANK _7B
JTAG INTERFACE
SKEW
CONTROL
OUTPUT
DRIVERS
TDI
TMS TCK TDO
Figure 5. ispClock5320S Functional Block Diagram
LOCK
RESET
PLL_BYPASS
OEX
OEY
VTT_REFA
VTT_REFB
LOCK
DETECT
OUTPUT ENABLE
CONTROLS
OUTPUT ROUTING
MATRIX
SKEW
CONTROL
OUTPUT
DRIVERS
REFA_REFP
REFB_REFN
OUTPUT
DIVIDERS
BANK_0A
BANK_0B
1
0
V0
5-bit
PHASE
DETECT
LOOP
FILTER
0
1
VCO
BANK_1A
BANK_1B
V1
5-bit
BANK_2A
BANK_2B
REFSEL
V2
5-bit
BANK_3A
FBK
BANK_3B
VTT_FBK
BANK_4A
BANK_4B
BANK_5A
BANK_5B
BANK_6A
BANK_6B
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
BANK_9B
JTAG INTERFACE
SKEW
CONTROL
OUTPUT
DRIVERS
TDI
TMS TCK TDO
4
Lattice Semiconductor
ispClock5300S Family Data Sheet
Absolute Maximum Ratings
ispClock5300S
Core Supply Voltage V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
CCD
PLL Supply Voltage V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
CCA
JTAG Supply Voltage V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
CCJ
Output Driver Supply Voltage V
. . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
CCO
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Output Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature with power supplied . . . . . . . . . . . . . . . . . . . -40 to 130°C
1. When applied to an output when in high-Z condition
Recommended Operating Conditions
ispClock5300S
Symbol
Parameter
Core Supply Voltage
Conditions
Min.
Max.
3.6
Units
V
V
V
V
V
3.0
1.62
3.0
—
CCD
JTAG I/O Supply Voltage
Analog Supply Voltage
3.6
V
CCJ
3.6
V
CCA
V
Turn-on Ramp Rate
CC
All supply pins
0.33
120
130
701
V/µs
CCXSLEW
Commercial
Industrial
0
T
Operating Junction Temperature
Ambient Operating Temperature
°C
°C
JOP
-40
0
Commercial
Industrial
T
A
-40
851
1. Device power dissipation may also limit maximum ambient operating temperature.
Recommended Operating Conditions – VCCO vs. Logic Standard
V
(V)
V
(V)
V
(V)
CCO
REF
TT
Logic Standard
LVTTL
Min.
3.0
Typ.
3.3
1.8
2.5
3.3
1.8
2.5
3.3
1.5
1.8
Max.
3.6
Min.
—
Typ.
—
Max.
—
Min.
—
Typ.
—
Max.
—
LVCMOS 1.8V
LVCMOS 2.5V
LVCMOS 3.3V
SSTL1.8
1.71
2.375
3.0
1.89
2.625
3.6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.71
2.375
3.0
1.89
2.625
3.6
0.84
1.15
1.30
0.68
0.84
0.90
1.25
1.50
0.75
0.90
0.95
1.35
1.70
0.90
0.95
—
0.5 x V
—
CCO
SSTL2 Class 1
SSTL3 Class 1
HSTL Class 1
eHSTL Class 1
Note: ‘—’ denotes V
V
V
- 0.04
V
V
V
V
+ 0.04
REF
REF
REF
REF
REF
REF
- 0.05
+ 0.05
1.425
1.71
1.575
1.89
—
0.5 x V
0.5 x V
—
CCO
—
—
CCO
or V not applicable to this logic standard
REF
TT
5
Lattice Semiconductor
ispClock5300S Family Data Sheet
E2CMOS Memory Write/Erase Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
Erase/Reprogram Cycles
1000
—
—
Performance Characteristics – Power Supply
Symbol
Parameter
Core Supply Current2
Conditions
Typ.
Max.
Units
I
I
I
f
f
f
= 400MHz Feedback Output Active
110
150
mA
CCD
VCO
OUT
VCO
Incremental I
Output
per Active
CCD
= 267MHz
1.5
mA
CCDADDER
CCA
Analog Supply Current2
= 400MHz
5.5
16
21
27
7
mA
mA
mA
mA
µA
V
V
V
V
= 1.8V1, LVCMOS, f
= 2.5V1, LVCMOS, f
= 3.3V1, LVCMOS, f
= 1.8V
= 267MHz
= 267MHz
= 267MHz
20
CCO
CCO
CCO
CCJ
CCJ
CCJ
OUT
OUT
OUT
Output Driver Supply Current
(per Bank)
I
27
CCO
35
300
400
400
I
JTAG I/O Supply Current (static) V
V
= 2.5V
µA
CCJ
= 3.3V
µA
1. Supply current consumed by each bank, both outputs active, 5pF load.
2.All unused REFCLK and feedbacks connected to ground.
DC Electrical Characteristics – Single-Ended Logic
V
(V)
V
(V)
IL
IH
Logic Standard
LVTTL/LVCMOS 3.3V
LVCMOS 1.8V
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max.
Min.
Max.
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
Max. (V) V Min. (V)
I
(mA)
123
123
123
7.6
8
I (mA)
OH
OL
OH
OL
0.8
0.68
0.7
2
0.4
0.4
V
V
V
- 0.4
- 0.4
- 0.4
-123
CCO
CCO
CCO
1.07
1.7
-123
-123
-7.6
-8
LVCMOS 2.5V
0.4
SSTL2 Class 1
SSTL3 Class 1
HSTL Class 1
V
- 0.18 V
+ 0.18
+ 0.2
+ 0.1
+ 0.1
0.541
0.91
0.42
0.42
V
CCO
- 0.811
- 1.31
- 0.42
- 0.42
REF
REF
V
- 0.2
- 0.1
- 0.1
V
V
REF
REF
REF
REF
REF
REF
CCO
CCO
CCO
V
V
V
V
8
-8
eHSTL Class 1
V
V
8
-8
1. Specified for 40Ω internal series output termination.
2. Specified for ≈20Ω internal series output termination, fast slew rate setting.
3. For slower slew rate setting, I , I should be limited to 8mA.
OH OL
DC Electrical Characteristics – LVDS
Symbol
Parameter
Conditions
Min.
/2
Typ.
Max.
2.325
—
Units
V
V
Common Mode Input Voltage
V
ICM
THD
IN
THD
V
≤ 2V
100
150
0
—
—
—
mV
mV
V
ICM
V
V
Differential Input Threshold
Input Voltage
2V < V
< 2.325V
—
ICM
2.4
DC Electrical Characteristics – Differential LVPECL
Symbol
Parameter
Test Conditions
Min.
Typ.
—
Max.
- 0.88
CCD
Units
V
V
V
V
= 3.0 to 3.6V
= 3.3V
V
- 1.17
V
V
CCD
CCD
CCD
CCD
CCD
V
Input Voltage High
V
IH
IL
2.14
- 1.81
—
2.42
- 1.48
CCD
= 3.0 to 3.6V
= 3.3V
V
—
CCD
V
Input Voltage Low
V
1.49
—
1.83
6
Lattice Semiconductor
ispClock5300S Family Data Sheet
Electrical Characteristics – Differential SSTL18
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
V
V
Low-Logic Level Input Voltage
Hi Logic Level Input Voltage
0.61
V
V
IL
1.17
IH
IX
Input Pair Differential Crosspoint
Voltage
V
V
-175mV
V
+175mV
V
REF
REF
Electrical Characteristics – Differential SSTL2
Symbol
Parameter
Conditions
Min.
-0.03
0.62
Typ.
Max.
3.225
3.225
Units
V
V
DC Differential Input Voltage Swing
AC Input Differential Voltage
V
SWING(DC)
SWING(AC)
V
PP
Input Pair Differential Crosspoint
Voltage
V
V
- 200 mV
V + 200 mV
REF
V
IX
REF
Electrical Characteristics – Differential HSTL
Symbol
Parameter
Conditions
Min
-0.03
0.4
Typ
Typ
Max
3.325
3.325
Units
V
V
DC Differential Input Voltage Swing
AC Input Differential Voltage
V
SWING(DC)
SWING(AC)
V
PP
Input Pair Differential Crosspoint
Voltage
V
0.68
0.9
V
IX
Electrical Characteristics – Differential eHSTL
Symbol
Parameter
Conditions
Min
-0.03
0.4
Max
3.325
3.325
Units
V
V
DC Differential Input Voltage Swing
AC Input Differential Voltage
V
SWING(DC)
SWING(AC)
V
PP
Input Pair Differential Crosspoint
Voltage
V
0.68
0.9
V
IX
7
Lattice Semiconductor
ispClock5300S Family Data Sheet
DC Electrical Characteristics – Input/Output Loading
Symbol
Parameter
Input Leakage
Conditions
Min.
—
Typ.
—
Max.
10
Units
µA
I
Note 1
Note 2
LK
I
I
I
Input Pull-up Current
—
80
120
150
150
400
10
µA
PU
REFSEL, PLL_BYPASS
—
120
120
200
—
µA
Input Pull-down Current
OEX, OEY, 2.5V CMOS Logic Standard
—
µA
PD
OEX, OEY, & 3.3V CMOS Logic Standard
—
µA
Tristate Leakage Output
Input Capacitance
Note 4
—
µA
OLK
Notes 2, 3, 5
Note 6
—
8
10
pF
C
IN
—
10
11
pF
1. Applies to clock reference inputs when termination ‘open’.
2. Applies to TDI, TMS and RESET inputs.
3. Applies to REFSEL and PLL_BYPASS, OEX, OEY.
4. Applies to all logic types when in tristated mode.
5. Applies to OEX, OEY, TCK, RESET inputs.
6. Applies to REFA_REFP, REFB_REFN, FBK.
Switching Characteristics – Timing Adders for I/O Modes
Adder Type
Description
Min.
Typ.
Max.
Units
t
Input Adders2
IOI
LVTTL_in
Using LVTTL Standard
0.00
0.10
0.00
0.00
0.00
0.00
1.15
1.10
0.60
0.60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS18_in
LVCMOS25_in
LVCMOS33_in
SSTL2_in
Using LVCMOS 1.8V Standard
Using LVCMOS 2.5V Standard
Using LVCMOS 3.3V Standard
Using SSTL2 Standard
SSTL3_in
Using SSTL3 Standard
HSTL_in
Using HSTL Standard
eHSTL_in
Using eHSTL Standard
LVDS_in
Using LVDS Standard
LVPECL_in
Using LVPECL Standard
t
Output Adders1, 3
IOO
LVTTL_out
Output Configured as LVTTL Buffer
Output Configured as LVCMOS 1.8V Buffer
Output Configured as LVCMOS 2.5V Buffer
Output Configured as LVCMOS 3.3V Buffer
Output Configured as SSTL18 Buffer
Output Configured as SSTL2 Buffer
Output Configured as SSTL3 Buffer
Output Configured as HSTL Buffer
0.25
0.25
0.25
0.25
0.00
0.00
0.00
0.00
0.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS18_out
LVCMOS25_out
LVCMOS33_out
SSTL18_out
SSTL2_out
SSTL3_out
HSTL_out
eHSTL_out
Output Configured as eHSTL Buffer
t
Output Slew Rate Adders1
IOS
Slew_1
Slew_2
Slew_3
Slew_4
Output Slew_1 (Fastest)
Output Slew_2
—
—
—
—
0.00
475
—
—
—
—
ps
ps
ps
ps
Output Slew_3
950
Output Slew_4 (Slowest)
1900
1. Measured under standard output load conditions – see Figures 6 and 7.
2. All input adders referenced to LVTTL.
3. All output adders referenced to SSTL/HSTL/eHSTL.
8
Lattice Semiconductor
ispClock5300S Family Data Sheet
Output Rise and Fall Times – Typical Values1, 2
Slew 1 (Fastest)
Slew 2
Slew 3
Slew 4 (Slowest)
Output Type
LVTTL
t
t
t
t
t
t
t
t
F
Units
ns
R
F
R
F
R
F
R
0.54
0.75
0.57
0.55
0.55
0.50
0.50
0.60
0.55
0.76
0.69
0.69
0.77
0.40
0.40
0.45
0.45
0.40
0.60
0.88
0.65
0.60
—
0.87
0.78
0.78
0.87
—
0.78
0.83
0.99
0.78
—
1.26
1.11
0.98
1.26
—
1.05
1.20
1.65
1.05
—
1.88
1.68
1.51
1.88
—
LVCMOS 1.8V
LVCMOS 2.5V
LVCMOS 3.3V
SSTL18
ns
ns
ns
ns
SSTL2
—
—
—
—
—
—
ns
SSTL3
—
—
—
—
—
—
ns
HSTL
—
—
—
—
—
—
ns
eHSTL
—
—
—
—
—
—
ns
1. See Figures 6 and 7 for test conditions.
2. Measured between 20% and 80% points.
Output Test Loads
Figures 6 and 7 show the equivalent termination loads used to measure rise/fall times, output timing adders and
other selected parameters as noted in the various tables of this data sheet.
Figure 6. CMOS Termination Load
SCOPE
50Ω/3"
50Ω/36"
950Ω
ispClock
50Ω 5pF
Zo = 50Ω
Figure 7. eHSTL/HSTL/SSTL Termination Load
VTERM
50Ω
SCOPE
50Ω/3"
50Ω/36"
950Ω
ispCLOCK
50Ω 5pF
Zo = HSTL: ~20Ω
SSTL: 40Ω
9
Lattice Semiconductor
ispClock5300S Family Data Sheet
Programmable Input and Output Termination Characteristics
Symbol
Parameter
Conditions
Rin=40Ω setting
Rin=45Ω setting
Rin=50Ω setting
Rin=55Ω setting
Rin=60Ω setting
Rin=65Ω setting
Rin=70Ω setting
Rout≈20Ω setting
Min.
Typ.
Max.
Units
36
—
44
40.5
45
—
49.5
55
—
R
Input Resistance
49.5
54
—
60.5
66
Ω
IN
—
59
—
71.5
77
61
—
—
36
41
45
50
54
59
63
—
14
38
45
50
55
59
65
72
500
—
44
51
55
61
66
71
78
—
T = 25°C
A
Rout≈40Ω setting
T = 25°C
A
Rout≈45Ω setting
T = 25°C
A
Rout≈50Ω setting
T = 25°C
A
R
Output Resistance
Ω
OUT
Rout≈55Ω setting
T = 25°C
A
Rout≈60Ω setting
T = 25°C
A
Rout≈65Ω setting
T = 25°C
A
Rout≈70Ω setting
T = 25°C
A
Output Resistor
Temperature Coefficient
R
PPM/°C
OUT_TEMPCO
10
Lattice Semiconductor
ispClock5300S Family Data Sheet
Performance Characteristics – PLL
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Reference and feedback input
frequency range
f
f
8
267
MHz
REF, FBK
t
t
Reference and feedback input
clock HIGH and LOW times
CLOCKHI,
CLOCKLO
1.25
ns
ns
t
t
Reference and feedback input Measured between 20% and 80%
rise and fall times
RINP,
FINP
5
levels
Phase detector input frequency
range
f
f
8
160
1
267
400
32
MHz
MHz
PFD
VCO
VCO operating frequency
Output divider range (Power of
2)
V
DIV
Fine Skew Mode
5
267
200
MHz
MHz
f
Output frequency range1
OUT
Coarse Skew Mode
2.5
Output adjacent-cycle jitter5
(1000 cycle sample)
Output period jitter5
(10000 cycle sample)
Reference clock to output jitter5
t
t
t
(cc)
f
f
f
≥ 100MHz
≥ 100MHz
≥ 100MHz
70
9
ps (p-p)
JIT
PFD
PFD
PFD
(per)
ps (RMS)
JIT
φ
50
100
8
ps (RMS)
JIT( )
(2000 cycle sample)
Static phase offset4
tφ
tφ
PFD input frequency ≥100MHz3
-40
47
ps
ps
100MHz, Spread Spectrum
Modulation index = 0.5%
Output type LVCMOS 3.3V2
Dynamic phase offset
2
DYN
DC
Output duty cycle error
53
%
ERR
f
>100 MHz
OUT
Reference clock to output
propagation delay
t
V=1
6.5
3.5
ns
PDBYPASS
Reference to output propagation
delay in Non-Zero Delay Buffer V=1
Mode
t
2.5
5
ns
ps
PD_FOB
Reference to output delay with
V=1
t
t
500
internal feedback mode3
DELAY
From Power-up event
From RESET event
150
15
µs
µs
µs
µs
PLL lock time
LOCK
To same reference frequency
To different frequency
15
t
PLL relock time
RELOCK
150
f
V
= f
CCA
= 100MHz
IN
OUT
Power supply rejection, period
jitter vs. power supply noise
ps(RMS)
mV(p-p)
PSR
= V
= V modulated with
CCO
0.05
CCD
100kHz sinusoidal stimulus
1. In PLL Bypass mode (PLL_BYPASS = HIGH), output will support frequencies down to 0Hz (divider chain is a fully static design).
2. See Figures 6 and 7 for output loads.
3. Input and outputs LVCMOS mode
4. Inserted feedback loop delay < 7ns
5. Measured with f
= 100MHz, f
= 400MHz, input and output interface set to LVCMOS.
OUT
VCO
11
Lattice Semiconductor
ispClock5300S Family Data Sheet
Timing Specifications
Skew Matching
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Between any two identically configured and loaded
outputs regardless of bank.
t
Output-output Skew
—
—
100
ps
SKEW
Programmable Skew Control
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Fine Skew Mode, f
= 160 MHz
—
2.73
1.09
5.46
2.19
8
—
—
—
—
—
—
—
—
—
—
—
VCO
VCO
Fine Skew Mode, f
= 400 MHz
—
t
Skew Control Range1
Skew Steps per Range
Skew Step Size2
ns
SKRANGE
Coarse Skew Mode, f
Coarse Skew Mode, f
= 160 MHz
—
VCO
VCO
= 400 MHz
—
SK
t
—
STEPS
Fine Skew Mode, f
Fine Skew Mode, f
= 160 MHz
—
390
156
780
312
30
VCO
= 400 MHz
—
VCO
ps
ps
SKSTEP
Coarse Skew Mode, f
Coarse Skew Mode, f
Fine skew mode
= 160 MHz
—
—
VCO
VCO
= 400 MHz
—
t
Skew Time Error3
SKERR
Coarse skew mode
—
50
1. Skew control range is a function of VCO frequency (f
). In fine skew mode T
= 7/(16 x f
).
VCO
VCO
SKRANGE
In coarse skew mode T
= 7/(8 x f
).
SKRANGE
VCO
2. Skew step size is a function of VCO frequency (f
). In fine skew mode T
= 1/(16 x f
).
VCO
VCO
SKSTEP
In coarse skew mode T
= 1/(8 x f
).
SKSTEP
VCO
3. Only applicable to outputs with non-zero skew settings.
Control Functions
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Delay Time, OEX or OEY to Output Disabled/
Enabled
t
—
10
20
ns
DIS/OE
t
t
PLL RESET Pulse Width1
Logic RESET Pulse Width2
Reset Signal Slew Rate
1
—
—
—
—
ms
ns
PLL_RSTW
20
0.1
RSTW
RST_SLEW
V/µs
1. Will completely reset PLL.
2. Will only reset digital logic.
12
Lattice Semiconductor
ispClock5300S Family Data Sheet
Static Phase Offset vs. Reference Clock Logic Type
Reference Clock Logic
(REFA/REFB)
Feedback Input
Logic (FBK)
Feedback Output Logic
(BANK_xA/BANK_xB) Min. Max. Units
Symbol
LVCMOS 33
LVCMOS 25
LVCMOS 18
SSTL3
LVCMOS33
LVCMOS33
LVCMOS25
LVCMOS18
SSTL3
-40
-70
-80
-70
-70
-100
-100
140
80
100
80
ps
ps
ps
ps
ps
ps
ps
ps
ps
LVCMOS25
LVCMOS18
SSTL3
80
390
340
360
360
530
300
t φ – Static Phase Offset SSTL2
SSTL2
SSTL2
( )
HSTL(1.5V)
HSTL(1.5V)
eHSTL(1.8V)
LVDS-Single Ended
HSTL(1.5V)
eHSTL(1.8V)
LVCMOS25
eHSTL(1.8V)
LVDS (2.5V)1
LVPECL1
LVPECL-Single Ended LVCMOS33
1. The output clock to feedback can be skewed to center the static phase offset spread.
Boundary Scan Logic
Symbol
Parameter
Min.
40
20
20
8
Max.
Units
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK (BSCAN Test) Clock Cycle
—
—
—
—
—
—
10
10
10
—
—
25
25
25
BTCP
BTCH
BTCL
BTSU
BTH
TCK (BSCAN Test) Pulse Width High
ns
TCK (BSCAN Test) Pulse Width Low
ns
TCK (BSCAN Test) Setup Time
ns
TCK (BSCAN Test) Hold Time
10
50
—
—
—
8
ns
TCK (BSCAN Test) Rise and Fall Rate
mV/ns
ns
BRF
TAP Controller Falling Edge of Clock to Valid Output
TAP Controller Falling Edge of Clock to Data Output Disable
TAP Controller Falling Edge of Clock to Data Output Enable
BSCAN Test Capture Register Setup Time
BTCO
BTOZ
BTVO
ns
ns
ns
BVTCPSU
BTCPH
BTUCO
BTUOZ
BTUOV
BSCAN Test Capture Register Hold Time
10
—
—
—
ns
BSCAN Test Update Register, Falling Edge of Clock to Valid Output
BSCAN Test Update Register, Falling Edge of Clock to Output Disable
BSCAN Test Update Register, Falling Edge of Clock to Output Enable
ns
ns
ns
13
Lattice Semiconductor
ispClock5300S Family Data Sheet
JTAG Interface and Programming Mode
Symbol
Parameter
Maximum TCK Clock Frequency
TCK Clock Pulse Width, High
TCK Clock Pulse Width, Low
Program Enable Delay Time
Program Disable Delay Time
High Voltage Discharge Time, Program
High Voltage Discharge Time, Erase
Falling Edge of TCK to TDO Active
Falling Edge of TCK to TDO Disable
Setup Time
Condition
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
25
—
Units
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MAX
CKH
CKL
20
20
15
30
30
200
—
—
ns
—
µs
ISPEN
ISPDIS
HVDIS
HVDIS
CEN
—
µs
—
µs
—
µs
15
15
—
ns
—
ns
CDIS
SU1
8
ns
Hold Time
10
—
—
ns
H
Falling Edge of TCK to Valid Output
Verify Pulse Width
15
—
ns
CO
30
20
200
µs
PWV
PWP
BEW
Programming Pulse Width
Bulk Erase Pulse Width
—
ms
ms
—
14
Lattice Semiconductor
ispClock5300S Family Data Sheet
Timing Diagrams
Figure 8. Erase (User Erase or Erase All) Timing Diagram
VIH
TMS
VIL
tSU1
tSU1
tCKL
tSU1
tSU1
tSU1
tCKL
tSU1
tH
tH
tH
tH
tH
tH
tCKH
tBEW
tCKH
tCKH
tCKH
tCKH
VIH
VIL
TCK
Run-Test/Idle (Discharge)
Update-IR
Run-Test/Idle (Erase)
Select-DR Scan
State
Figure 9. Programming Timing Diagram
VIH
TMS
VIL
tSU1
tH
tSU1
tCKL
tH
tSU1
tH
tCKH
tSU1
tH
tSU1
tCKL
tH
tCKH
tPWP
tCKH
tCKH
VIH
TCK
VIL
Update-IR
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
Figure 10. Verify Timing Diagram
VIH
TMS
VIL
tSU1
tH
tSU1
tCKL
tH
tSU1
tH
tSU1
tH
tSU1
tCKL
tH
tCKH
tPWV
tCKH
tCKH
tCKH
VIH
VIL
TCK
Update-IR
State
Update-IR
Run-Test/Idle (Program)
Select-DR Scan
Figure 11. Discharge Timing Diagram
tHVDIS (Actual)
VIH
TMS
VIL
tSU1
tH
tSU1
tCKL
tH
tSU1
tH
tCKH
tSU1
tH
tSU1
tCKL
tH
tCKH
tSU1
tH
tCKH
tPWP or tBEW
tCKH
tPWV
tCKH
VIH
VIL
Actual
TCK
tPWV
Specified by the Data Sheet
Run-Test/Idle (Verify)
State
Update-IR
Run-Test/Idle (Erase or Program)
Select-DR Scan
15
Lattice Semiconductor
ispClock5300S Family Data Sheet
Typical Performance Characteristics
I
vs. Output Frequency
I
vs. f
CCO
CCD
VCO
(LVCMOS 3.3V, Normalized to 266MHz)
(Normalized to 400MHz)
1.2
1.0
0.8
0.6
0.4
0.2
0
1.2
1.0
0.8
0.6
0.4
0.2
0
0
50
100
150
200
250
300
150
200
250
300
(MHz)
350
400
300
300
Output Frequency (MHz)
f
VCO
Period Jitter vs. Input/Output Frequency
Adjacent Cycle Jitter vs. Input/Output Frequency
80
60
40
250
200
V=16
V=8
V=16
150
100
V=8
V=4
20
0
V=2
V=4
50
0
V=1
V=1
V=2
0
50
100
150
200
250
0
50
100
150
200
250
300
Input/Output Frequency (MHz)
Input/Output Frequency (MHz)
Phase Jitter vs. Input/Output Frequency
100
80
V=16
60
40
V=8
V=2
V=1
V=4
20
0
0
50
100
150
200
250
Input/Output Frequency (MHz)
16
Lattice Semiconductor
ispClock5300S Family Data Sheet
Detailed Description
PLL Subsystem
The ispClock5300S provides an integral phase-locked-loop (PLL) which may be used to generate output clock sig-
nals at lower, higher, or the same frequency as a user-supplied input reference signal. The core functions of the
PLL are an edge-sensitive phase detector, a programmable loop filter, and a high-speed voltage-controlled oscilla-
tor (VCO). Additionally, a set of programmable feedback dividers (V[0, 1, 2]) is provided to support the synthesis of
different output frequencies.
Phase/Frequency Detector
The ispClock5300S provides an edge-sensitive phase/frequency detector (PFD), which means that the device will
function properly over a wide range of input clock reference duty cycles. It is only necessary that the input refer-
ence clock meet specified minimum HIGH and LOW times (t
t
) for it to be properly recognized by
CLOCKHI, CLOCKLO
the PFD. The PFD’s output is of a classical charge-pump type, outputting charge packets which are then integrated
by the PLL‘s loop filter.
A lock-detection feature is also associated with the PFD. When the ispClock5300S is in a LOCKED state, the
LOCK output pin goes HIGH. The number of cycles required before asserting the LOCK signal in frequency-lock
mode can be set from 16 through 256.
When the lock condition is lost the LOCK signal will be de-asserted (Logic ‘0’) immediately.
Loop Filter: The loop filter parameters for each profile are automatically selected by the PAC-Designer software
depending on the following:
• Maximum VCO operating frequency
Spread Spectrum Support: The reference clock inputs of the ispClock5300S device are spread spectrum clock
tolerant. The tolerance limits are:
• Center spread 0.125% to 2%
• Down spread -0.25% to 0.5%
• 30-33kHz modulation frequency
The ispClock5300S PLL has two modes of operation:
• Spread Spectrum setting turned on - Spread Spectrum modulation is transferred from input to output with
minimal attenuation.
• Spread Spectrum setting turned off - Spread Spectrum modulation transfer from input to output is attenu-
ated. The extent of attenuation depends on the VCO operating frequency and the feedback divider value.
17
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 12. PLL Loop Bandwidth vs. Feedback Divider Setting (Nominal)
PLL Bandwidth vs.
VCO Frequency and V-Divider
PLL Loop Bandwidth vs.
VCO Frequency and V-Divider
(Spread Spectrum Compatible Mode)
(Standard Mode)
6.0
6.0
5.0
4.0
5.0
4.0
Vdiv=1
Vdiv=2
Vdiv=4
Vdiv=8
Vdiv=2
Vdiv=4
Vdiv=8
3.0
2.0
1.0
0.0
3.0
2.0
Vdiv=16
Vdiv=32
Vdiv=16
Vdiv=32
1.0
0.0
100
200
300
400
500
600
100
200
300
400
500
VCO Frequency (MHz)
VCO Frequency (MHz)
Dynamic Phase Offset vs.
Dynamic Phase Offset vs.
Input Frequency and Modulation Index (MI)
(Vdiv = 2)
Input Frequency and Modulation Index (MI)
(Vdiv = 4)
50
40
30
20
10
60
50
40
30
20
10
0
MI = 2.0%
MI = 2.0%
MI = 1.0%
MI = 1.0%
MI = 0.50%
MI = 0.25%
MI = 0.50%
MI = 0.25%
0
80 100 120 140 160 180 200 220 240 260
40
60
80
100
120
140
Input Frequency (MHz)
Input Frequency (MHz)
VCO
The ispClock5300S provides an internal VCO which provides an output frequency ranging from 160MHz to
400MHz. The VCO is implemented using differential circuit design techniques which minimize the influence of
power supply noise on measured output jitter. The VCO is also used to generate output clock skew as a function of
the total VCO period. Using the VCO as the basis for controlling output skew allows for highly precise and consis-
tent skew generation, both from device-to-device, as well as channel-to-channel within the same device.
Output V Dividers
The ispClock5300S incorporates a set of three 5-bit programmable Power of 2 dividers which provide the ability to
synthesize output frequencies differing from that of the reference clock input.
Each one of the three V dividers can be independently programmed to provide division ratios ranging from 1 to 32
in Power of 2 steps (1, 2, 4, 8, 16, 32).
18
Lattice Semiconductor
ispClock5300S Family Data Sheet
When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (f ) may be cal-
k
culated as:
V
V
fbk
(1)
=
f
k
f
ref
k
where
f is the frequency of V divider k
k
f
is the input reference frequency
ref
V
is the setting of the V divider used to close the PLL feedback path
fbk
V is the output divider K
k
Note that because the feedback may be taken from any V divider, V and V may refer to the same divider.
k
fbk
Because the VCO has an operating frequency range spanning 160 MHz to 400 MHz, and the V dividers provide
division ratios from 1 to 32, the ispClock5300S can generate output signals ranging from 2.5 MHz to 267 MHz.
PLL_BYPASS Mode
The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without
using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the reference clock is
routed directly to the inputs of the V dividers. The output frequency for a given V divider (f ) will be determined by
K
f
REF
(2)
=
f
k
V
K
When PLL_BYPASS mode is enabled, features such as lock detect and skew generation are unavailable and the
output clock is inverted when V =1.
K
Internal/External Feedback Support
The PLL feedback path can be sourced internally or externally through an output pin. When the internal feedback
path is selected, one can use all output pins for clock distribution. The programmable skew feature for the feedback
path is available in both feedback modes.
Reference and External Feedback Inputs
The ispClock5300S provides configurable, internally-terminated inputs for both clock reference and feedback sig-
nals.
The reference clock inputs pins can be interfaced with either one differential input (REFP, REFN) or two single-
ended (REFA, REFB) inputs with the active clock selection control through REFSEL pin. The following diagram
shows the possible reference clock configurations. Note: When the reference clock inputs are configured as differ-
ential input, the REFSEL pin should be grounded.
Table 2. REFSEL Operation for ispClock5300S Programmed as Single-Ended Clock Inputs
Selected
REFSEL
Input
REFA
REFB
0
1
Supported input logic reference standards:
• LVTTL (3.3V)
• LVCMOS (1.8V, 2.5V, 3.3V)
• SSTL2
• SSTL3
• HSTL
19
Lattice Semiconductor
ispClock5300S Family Data Sheet
• eHSTL
• Differential SSTL1.8
• Differential SSTL2
• Differential SSTL3
• Differential HSTL
• LVDS
• LVPECL (differential, 3.3V)
Figure 13. Reference and Feedback Input
+
–
REFA_REFP
REFB_REFN
PHASE
FREQ.
0
1
DETECT
REFSEL
FBK
INTERNAL
FEEDBACK
VTT_FBK
TO OUTPUT
ROUTING
MATRIX
Each input features internal programmable termination resistors as shown in Figure 14. The REFA and REFB
inputs terminate to VTT_REFA and VTT_REFB respectively. In order to interface to differential clock input one
should connect VTT_REFA and VTT_REFB pins together on circuit board and if necessary connect the common
node to VTT supply.
The direct connection from REFA and REFB pins to the output routing matrix becomes unavailable when the REFA
and REFB pins are configured as differential input pins.
20
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 14. Input Receiver Termination Configuration
Differential
Receiver
+
–
REFA_REFP
REFB_REFN
Single-ended
Receiver
To
Internal
Logic
R
T
VTT_REFA
VTT_REFB
R
T
Single-ended
Receiver
Feedback input is terminated to the VTT_FBK pin through a programmable resistor.
The following usage guidelines are suggested for interfacing to supported logic families.
21
Lattice Semiconductor
ispClock5300S Family Data Sheet
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal can be connected to either the REFA
or REFB pins. CMOS transmission lines are generally source terminated, so all termination resistors should be set
to the OPEN state. Figure 15 shows the proper configuration. Please note that because switching thresholds are
different for LVCMOS running at 1.8V, there is a separate configuration setting for this particular standard. Unused
reference inputs and VTT pins should be grounded.
Figure 15. LVCMOS/LVTTL Input Receiver Configuration
REFA_REFP /
REFB_REFN
R
T
Single-ended
Receiver
VTT_REFA /
VTT_REFB
Open
GND
HSTL, eHSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal can be connected to the REFA or REFB ter-
minal of the input pair and the associated VTT_REFA or VTT_REFB terminal should be tied to a VTT termination
supply. The terminating resistor should be set to 50Ω and the engaging switch should be closed. Figure 16 shows
an appropriate configuration. Refer to the “Recommended Operating Conditions - Supported Logic Standards”
table in this data sheet for suitable values of V
and V .
REF
TT
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator specifically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 16. SSTL2, SSTL3, eHSTL, HSTL Receiver Configuration
REFA_REFP /
REFB_REFN
50
Single-ended
Receiver
Closed
VTT_REFA /
VTT_REFB
Differential LVPECL/LVDS
The receiver should be set to LVDS or LVPECL mode as required and both termination resistors should be
engaged and set to 50Ω.The VTT_REFA and VTT_REFB pins, however, should be connected.This creates a float-
ing 100Ω differential termination resistance across the input terminals. The LVDS termination configuration is
shown in Figure 17.
Note: the REFSEL pin should be grounded when the input receiver is configured as differential.
22
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 17. LVDS Input Receiver Configuration
Differential
Receiver
+
REFA_REFP
LVDS
Driver
–
REFB_REFN
50
VTT_REFA
Close
50
Close
VTT_REFB
ispClock5300S
Note that while a floating 100Ω resistor forms a complete termination for an LVDS signal line, additional circuitry
may be required to satisfactorily terminate a differential LVPECL signal. This is because a true bipolar LVPECL out-
put driver typically requires an external DC ‘pull-down’ path to a V
termination voltage (typically VCC-2V) to
TERM
properly bias its open emitter output stage. When interfacing to an LVPECL input signal, the ispClock5300S inter-
nal termination resistors should not be used for this pull-down function, as they may be damaged from excessive
current. The pull-down should be implemented with external resistors placed close to the LVPECL driver
(Figure 18)
Figure 18. LVPECL Input Receiver Configuration
Differential
Receiver
REFA_REFP
+
LVPECL
Driver
–
REFB_REFN
R
R
PD
PD
50
REFA-VTT
V
Close
TERM
50
Close
REFB-VTT
ispClock5300S
Please note that while the above discussions specify using 50Ω termination impedances, the actual impedance
required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal.The
23
Lattice Semiconductor
ispClock5300S Family Data Sheet
actual impedance required will be a function of the driver used to generate the signal and the transmission medium
used (PCB traces, connectors and cabling). The ispClock5300S’s ability to adjust input impedance over a range of
40Ω to 70Ω allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to
swap out components.
Output Drivers
The ispClock5300S provides multiple banks, with each bank supporting two high-speed clock outputs which are
configurable and internally terminated. There are ten banks in the ispClock5320S, eight banks in the
ispClock5316S, six banks in the ispClock5312S, four banks in the ispClock5308S and two banks in the
ispClock5304S. Programmable internal source-series termination allows the ispClock5300S to be matched to
transmission lines with impedances ranging from 40 to 70Ω. The outputs may be independently enabled or dis-
abled, either from E2CMOS configuration or by external control lines. Additionally, each can be independently pro-
grammed to provide a fixed amount of signal delay or skew, allowing the user to compensate for the effects of
unequal PCB trace lengths or loading effects. Figure 19 shows a block diagram of a typical ispClock5300S output
driver bank and associated skew control.
Because of the high edge rates which can be generated by the ispClock5300S clock output drivers, the VCCO
power supply pin for each output bank should be individually bypassed. Low ESR capacitors with values ranging
from 0.01 to 0.1 µF may be used for this purpose. Each bypass capacitor should be placed as close to its respec-
tive output bank power pins (VCCO and GNDO) pins as is possible to minimize interconnect length and associated
parasitic inductances.
In the case where an output bank is unused, the associated VCCO pin may be either left floating or tied to ground
to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground
where possible. All GNDO pins must be tied to ground, regardless of whether or not the associated bank is used.
Figure 19. ispClock5300S Output Driver and Skew Control
VCCO-x
OE Control
Skew
Adjust*
Single Ended
Output A Driver
From
V-Dividers
Bank_xA
OE Control
Skew
Adjust*
Single Ended
Output B Driver
From
V-Dividers
Bank_xB
GNDO-x
*Skew Adjust Mechanism is applicable only to outputs connected to one of the three V-Dividers and
when PLL is active (PLL-Bypass pin = 0). For all other conditions, Skew Adjust Mechanism is bypassed.
24
Lattice Semiconductor
ispClock5300S Family Data Sheet
Each of the ispClock5300S’s output driver banks can be configured to support the following logic outputs:
• LVTTL
• LVCMOS (1.8V, 2.5V, 3.3V)
• SSTL2
• SSTL3
• HSTL
• eHSTL
To provide LVTTL, LVCMOS, SSTL2, SSTL3, HSTL and eHSTL outputs, the CMOS output drivers in each bank are
enabled. These circuits provide logic outputs which swing from ground to the VCCO supply rail. The choice of
VCCO to be supplied to a given bank is determined by the logic standard to which that bank is configured. Because
each pair of outputs has its own VCCO supply pin, each bank can be independently configured to support a differ-
ent logic standard. Note that the two outputs associated with a bank must necessarily be configured to the same
logic standard. The source impedance of each of the two outputs in each bank may be independently set over a
range of 40Ω to 70Ω in 5Ω steps. A low impedance option (≈20Ω) is also provided for cases where low source ter-
mination is desired on a given output.
Control of output slew rate is also provided in LVTTL, LVCMOS, SSTL2, SSTL3, HSTL and eHSTL output modes.
Four output slew-rate settings are provided, as specified in the “Output Rise Times” and “Output Fall Times” tables
in this data sheet.
Polarity control (true/inverted) is available for all output drivers. In the case of single-ended output standards, the
polarity of each of the two output signals from each bank may be controlled independently.
Suggested Usage
Figure 20 shows a typical configuration for the ispClock5300S output driver when configured to drive an LVTTL or
LVCMOS load. The ispClock5300S output impedance should be set to match the characteristic impedance of the
transmission line being driven. The far end of the transmission line should be left open, with no termination resis-
tors.
Figure 20. Configuration for LVTTL/LVCMOS Output Modes
ispClock5300S
LVCMOS/LVTTL
Mode
Zo
Ro = Zo
LVCMOS/LVTTL
Receiver
Figure 21 shows a typical configuration for the ispClock5300S output driver when configured to drive SSTL2,
SSTL3, HSTL or eHSTL loads. The ispClock5300S output impedance should be set to 40Ω for driving SSTL2 or
SSTL3 loads and to the ≈20Ω setting for driving HSTL and eHSTL.The far end of the transmission line must be ter-
minated to an appropriate VTT voltage through a 50Ω resistor.
25
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 21. Configuration for SSTL2, SSTL3, and HSTL Output Modes
VTT
ispClock5300S
RT=50
SSTL/HSTL/eHSTL
Mode
SSTL/HSTL/eHSTL
Receiver
Zo=50
Ro : 40 (SSTL)
20 (HSTL, eHSTL)
VREF
ispClock5300S Configurations
The ispClock5300S device can be configured to operate in four modes. They are:
•
•
•
•
Zero Delay Buffer Mode
Mixed Zero Delay and Non-Zero Delay Buffer Mode
Non-Zero Delay Buffer mode 1
Non-Zero Delay Buffer Mode 2
The output routing matrix of the ispClock5300S provides up to three independent any-to-any paths from inputs to
outputs:
•
•
•
From any V-Dividers to any output in ZDB mode or PLL Bypass modes
From selected clock via REFSEL pin to any output (note single ended reference clock)
From the other clock not selected by REFSEL pin to any output
Zero Delay Buffer Mode
Figure 22 shows the ispClock5300S device configured to operate in the Zero Delay Buffer mode. The Clock input
can be single ended or differential. Two single ended clocks can be selected by the use of REFSEL pin and if the
input is configured as a differential the REFSEL pin should be connected to GNDD. The input clock then drives the
Phase frequency detector of the PLL. Up to 3 output clock frequencies can be generated from the input reference
clock by the use of V-dividers at the output of PLL. Any V-divider output can be connected to any of the output pins.
However, one of the V-dividers should be used in the feedback path to set the PLL operating frequency. The PLL
can operate with internal or external feedback path.
In this mode, the skew control mechanism is active for all outputs.
26
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 22. ispClock5300S configured as Zero Delay Buffer Mode
ispClock5300S
V1
Single Ended /
Differential
Clock Input
PLL
V2
V3
Internal Feedback
External Feedback
Mixed Zero Delay and Non-Zero Delay Buffer Mode
Figure 23 shows the operation of the ispClock5300S in Mixed Zero Delay and Non Zero Delay modes. In this mode
the output switch matrix is configured to route non selected reference clock, selected reference clock, and the zero
delay clock through the PLL.
The skew control mechanism is available only to clocks sourced from the PLL.
27
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 23. Mixed Zero Delay and Non Zero Delay Buffer Mode
ispClock5300S
Single Ended /
Clock Input
V1
Single Ended /
Clock Input
PLL
V2
V3
Internal Feedback
External Feedback
28
Lattice Semiconductor
ispClock5300S Family Data Sheet
Non Zero Delay Buffer Mode 1
In the non zero delay buffer mode as shown in Figure 24 the output routing matrix completely bypasses the PLL.
Each of the single ended input reference clocks can be routed to any number of available output clocks.
In this mode of operation there is no skew control.
Figure 24. Non Zero Delay Fan Out Buffer Mode 1
ispClock5300S
Single Ended /
Clock Input
REFB_REFN /
REFA_REFP
V1
Single Ended /
PLL Bypassed
Clock Input
V2
V3
REFA_REFP /
REFB_REFN
29
Lattice Semiconductor
ispClock5300S Family Data Sheet
ispClock5300 Operating Configuration Summary
The following table summarizes the operating modes of the ispClock5300S.
Note:
• Whenever the input buffer is configured as differential input, the fan-out buffer paths become unavailable.
• Non-zero delay buffer for differential clock input is realized by using the PLL_BYPASS signal set to logical
‘1’.
• Output Skew control mechanism is available only to clock outputs sourced from PLL VCO.
Table 3. ispClock5300S Operating Modes
ispClock5300S
Operating Mode
Output Clock
Frequency Divider
Reference Input Clocks
Skew Control
Zero Delay Buffer Mode
Single Ended / Differential
Yes
Yes
Mixed Zero-Delay &
Non-Zero Delay Buffer Mode
Only to Zero Delay
Output Clocks
Only to Zero Delay
Output Clocks
Single Ended Only
Single Ended Only
Non-Zero Delay Fan-out Buffer
Mode 1
No
No
No
Non-Zero Delay Fan-out Buffer
Mode 2
Only to Clocks Sourced From
Bypassed PLL
Single Ended / Differential
Thermal Management
In applications where a majority of the ispClock5300S’s outputs are active and operating at or near maximum out-
put frequency, package thermal limitations may need to be considered to ensure a successful design. Thermal
characteristics of the packages employed by Lattice Semiconductor may be found in the document Thermal Man-
agement which may be obtained at www.latticesemi.com.
The maximum current consumption of the digital and analog core circuitry for ispClock5312S is 150mA worst case
(I
+ I
), and each of the output banks may draw up to 16mA worst case (LVCMOS 3.60V, CL=5pF, f
=100
CCD
CCA
OUT
MHz, both outputs in each bank enabled). This results in a total device dissipation:
P
= 3.60V x (6 x 16mA + 150mA) = 0.88W
(3)
DMAX
With a maximum recommended operating junction temperature (T
) of 130°C for an industrial grade device, the
JOP
maximum allowable ambient temperature (T
) can be estimated as
AMAX
T
= T
- PD
x Θ = 130°C - 0.88W x 48°C/W = 85°C
(4)
AMAX
JOP
MAX
JA
where Θ = 48°C/W for the 48 TQFP package in still air and Θ = 42°C/W for the 64 TQFP package in still air.
JA
JA
The above analysis represents the worst-case scenario. Significant improvement in maximum ambient operating
temperature can be realized with additional cooling. Providing a 200 LFM (Linear Feet per Minute) airflow reduces
Θ
to 44°C/W for the 48 TQFP package.
JA
While it is possible to perform detailed calculations to estimate the maximum ambient operating temperature from
operating conditions, some simpler rule-of-thumb guidance can also be obtained through the derating curves
shown in Figure 25 which shows the maximum ambient operating temperature permitted when operating a given
number of output banks at the maximum output frequency.
30
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 25. Maximum Ambient Temperature vs. Number of Active Output Banks
Temperature Derating Curves
Temperature Derating Curves
Outputs LVCMOS33, 3.3V, f = 100MHz Still Air
Outputs LVCMOS33, 3.3V, f
= 100MHz Still Air
OUT
OUT
(ispClock 5304S, 5308S, 5312S)
(ispClock 5316S, 5320S)
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
5312S Industrial
5320S Industrial
5312S Commercial
5320S Commercial
1
2
3
4
5
6
0
2
4
6
8
10
12
Number of Active Banks
Number of Active Banks
Note that because of variations in circuit board mounting, construction, and layout, as well as convective and forced
airflow present in a given design, actual die operating temperature is subject to considerable variation from that
which may be theoretically predicted from package characteristics and device power dissipation.
Output Enable Controls (OEX, OEY)
The ispClock5300S family provides two output control pins for enabling and disabling clock outputs. In addition, the
outputs can also be configured to be permanently enabled or permanently disabled.
Skew Control Units
Each of the ispClock5300S’s clock outputs is supported by a skew control unit which allows the user to insert an
individually programmable delay into each output signal. This feature is useful when it is necessary to de-skew
clock signals to compensate for physical length variations among different PCB clock paths.
The ispClock5300S’s skew adjustment feature provides exact and repeatable delays which exhibit extremely low
channel-to-channel and device-to-device variation. This is achieved by deriving all skew timing from the VCO,
which results in the skew increment being a linear function of the VCO period. For this reason, skews are defined in
terms of ‘unit delays’, which may be programmed by the user over a range of 0 to 7. The ispClock5300S family also
supports both ‘fine’ and ‘coarse’ skew modes. In fine skew mode, the unit skew ranges from 156ps to 390 ps, while
in the coarse skew mode unit skew varies from 312ps to 780ps. The exact unit skew (TU) may be calculated from
the VCO frequency (f ) by using the following expressions:
vco
For fine skew mode,
1
For coarse skew mode,
1
(5)
=
=
TU
TU
16f
8f
vco
vco
Please note that the skew control units are only usable when the PLL is selected. In PLL bypass mode
(PLL_BYPASS=1), output skew settings will be ineffective and all outputs will exhibit skew consistent with the
device’s propagation delay and the individual delays inherent in the output drivers consistent with the logic stan-
dard selected.
Coarse Skew Mode
The ispClock5300S family provides the user with the option of obtaining longer skew delays at the cost of reduced
time resolution through the use of coarse skew mode. Coarse skew mode provides unit delays ranging from 312ps
31
Lattice Semiconductor
ispClock5300S Family Data Sheet
(f
= 400MHz) to 780ps (f
= 160MHz), which is twice as long as those provided in fine skew mode. When
VCO
VCO
coarse skew mode is selected, an additional divide-by-2 stage is effectively inserted between the VCO and the V-
divider bank, as shown in Figure 26. When assigning divider settings in coarse skew mode, one must account for
this additional divide-by-two so that the VCO still operates within its specified range (160-400MHz).
Figure 26. Additional Factor-of-2 Division in Coarse Mode
Fine
Mode
VCO
V-dividers
Fout
Coarse
Mode
÷2
When one moves from fine skew mode to coarse skew mode with a given divider configuration, the VCO frequency
will attempt to double to compensate for the additional divide-by-2 stage. Because the f range is not increased,
VCO
however, one must modify the feedback path V-divider settings to bring f
back into its specified operating range
VCO
(160MHz to 400MHz). This can be accomplished by dividing all V-divider settings by two. All output frequencies will
remain unchanged from what they were in fine mode.
Output Skew Matching and Accuracy
Understanding the various factors which relate to output skew is essential for realizing optimal skew performance in
the ispClock5300S family of devices.
In the case where two outputs are identically configured, and driving identical loads, the maximum skew is defined
by t
which is specified as a maximum of 100ps. In Figure 27 the Bank1A and BANK2A outputs show the skew
SKEW,
error between two matched outputs.
Figure 27. Skew Matching Error Sources
1ns +/- (tSKEW) +/- (tSKERR
)
+/- tSKEW
BANK1A
(skew setting = 0)
BANK2A
(skew setting=0)
BANK3A
(skew setting = 1ns)
One can also program a user-defined skew between two outputs using the skew control units. Because the pro-
grammable skew is derived from the VCO frequency, as described in the previous section, the absolute skew is
very accurate. The typical error for any non-zero skew setting is given by the t
specification. For example, if
SKERR
one is in fine skew mode with a VCO frequency of 250MHz, and selects a skew of 4TU, the realized skew will be
1ns, which will typically be accurate to within +/-30 ps. An example of error vs. skew setting can be found in the
chart ‘Typical Skew Error vs. Setting’ in the typical performance characteristics section. Note that this parameter
adds to output-to-output skew error only if the two outputs have different skew settings. The Bank1A and Bank3A
32
Lattice Semiconductor
ispClock5300S Family Data Sheet
outputs in Figure 27 show how the various sources of skew error stack up in this case. Note that if two or more out-
puts are programmed to the same skew setting, then the contribution of the t skew error term does not apply.
SKERR
When outputs are configured or loaded differently, this also has an effect on skew matching. If an output is set to
support a different logic type, this can be accounted for by using the t(ioo) output adders specified in the table
‘Switching Characteristics’. That table specifies the additional skew added to an output using SSTL, HSTL, EHSTL
as a base-line. For instance, if one output is specified as LVTTL, it has a delay adder relative to SSTL of 0.25ns. If
another output is specified as SSTL3, then one would expect 0.25ns of additional skew between the two outputs
due to this adder. This timing relationship is shown in Figure 28a.
Figure 28. Output Timing Adders for Logic Type (a) and Output Slew Rate (b)
950ps
0.25ns
LVCMOS Output
(Slew rate=1)
SSTL3 Output
LVTTL Output
LVCMOS Output
(Slew rate=3)
(a)
(b)
By selecting the same feedback logic type and clock output, the output delay adders for the clock output are auto-
matically compensated for. Similarly, a reference clock delay adder can be compensated for by selecting the same
feedback input logic type and reference clock.
When the internal feedback mode is selected, however, one should add both input and output delay adders to t
specified in the Performance Characteristics PLL table to calculate the input-to-output delay.
DELAY
Similarly, when one changes the slew rate of an output, the output slew rate adders (t ) can be used to predict
IOS
the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are
measured. For example, in the case of outputs configured to the same logic type (e.g. LVCMOS 1.8V), if one output
is set to the fastest slew rate (1, t
= 0ps), and another set to slew rate 3 (t
= 950ps), then one could expect
IOS
IOS
950ps of skew between the two outputs, as shown in Figure 28b.
Static Phase Offset and Input-Output Skew
The ispClock5300S’s external feedback inputs can be used to obtain near-zero effective delays from the clock ref-
erence input pins to a designated output pin. Using external feedback (Figure 29), the PLL will attempt to force the
output phase so that the rising edge phase (tφ) at the feedback input matches the rising edge phase at the refer-
ence input. The residual error between the two is specified as the static phase error. Note that any propagation
delay (t
) in the external feedback path drives the phase of the output signal backwards in time as measured at
FBK
the output. For this reason, if zero input-to-output delays are required, the length of the signal path between the
output pin and the feedback pin should be minimized.
33
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 29. External Feedback Mode and Timing Relationships
Input Reference Clock
REF
ispClock5300S
BANK
OUTPUT
FBK
Delay = tFBK
tφ
REF
FBK
BANK
OUTPUT
tFBK
Other Features
RESET and Power-up Functions
To ensure proper PLL startup and synchronization of outputs, the ispClock5300S provides both internally gener-
ated and user-controllable external reset signals. An internal reset is generated whenever the device is powered
up. An external reset may be applied by asserting a logic LOW at the RESET pin. Asserting RESET resets all inter-
nal dividers, and will cause the PLL to lose lock. On losing lock, the VCO frequency will begin dropping. The length
of time required to regain lock is related to the length of time for which RESET was asserted.
When the ispClock5300S begins operating from initial power-on, the VCO starts running at a very low frequency
(<100 MHz) which gradually increases as it approaches a locked condition. To prevent invalid outputs from being
applied to the rest of the system, assert OEX or OEY high.This will result in the BANK outputs being held in a high-
impedance state until the OEX or OEY pin is pulled LOW.
After in-system programming the device through the JTAG interface, the reset pin must be activated at least for a
period of t
to reset the device.
PLL_RSTW
If the RESET pin is not driven by an external logic it should be pulled up to V
through a 10kΩ resistor.
CCD
Software-Based Design Environment
Designers can configure the ispClock5300S using Lattice’s PAC-Designer software, an easy to use, Microsoft Win-
dows compatible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer envi-
ronment. Full device programming is supported using PC parallel port I/O operations and a download cable
connected to the serial programming interface pins of the ispClock5300S. A library of configurations is included with
basic solutions and examples of advanced circuit techniques are available. In addition, comprehensive on-line and
printed documentation is provided that covers all aspects of PAC-Designer operation. PAC-Designer is available for
download from the Lattice web site at www.latticesemi.com. The PAC-Designer schematic window, shown in
Figure 30 provides access to all configurable ispClock5300S elements via its graphical user interface. All analog input
and output pins are represented. Static or non-configurable pins such as power, ground and the serial digital interface
are omitted for clarity. Any element in the schematic window can be accessed via mouse operations as well as menu
commands. When completed, configurations can be saved and downloaded to devices.
34
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 30. PAC-Designer Design Entry Screen
In-System Programming
The ispClock5300S is an In-System Programmable (ISP™) device. This is accomplished by integrating all
E2CMOS configuration control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant
serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored
on-chip, in non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all
ispClock5300S instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E2CMOS memory of the ispClock5300S. This consists
of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory
control data. The specifics this feature are discussed in the IEEE 1149.1 serial interface section of this data sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispClock5300S device to prevent unauthorized readout
of the E2CMOS configuration bit patterns. Once programmed, this cell prevents further access to the functional
user bits in the device. This cell can only be erased by reprogramming the device, so the original configuration can
not be examined once programmed. Usage of this feature is optional. The specifics of this feature are discussed in
the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
35
Lattice Semiconductor
Evaluation Fixture
ispClock5300S Family Data Sheet
Included in the basic ispClock5300S Design Kit is an engineering prototype board that can be connected to the
parallel port of a PC using a Lattice ispDOWNLOAD® cable. It demonstrates proper layout techniques for the
ispClock5300S and can be used in real time to check circuit operation as part of the design process. Input and out-
put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5300S for
a given application. (Figure 31).
Part Number
Description
PAC-SYSTEMCLK5312S
Complete system kit, evaluation board, ispDOWNLOAD cable and software.
Figure 31. Download from a PC
PAC-Designer
Software
Other
System
Circuitry
ispDownload
Cable (6')
4
ispClock5300S
Device
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispClock5300S is facilitated via an IEEE 1149.1 test
access port (TAP). It is used by the ispClock5300S both as a serial programming interface, and for boundary scan
test purposes. A brief description of the ispClock5300S JTAG interface follows. For complete details of the refer-
ence specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.
1149.1-1990 (which now includes IEEE Std. 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispClock5300S. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the configuration register, shifting
data in, and then executing a program configuration instruction, after which the data is transferred to internal
E2CMOS cells. It is these non-volatile cells that store the configuration of the ispClock5300S. A set of instructions
are defined that access all data registers and perform other internal control operations. For compatibility between
compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally spec-
ified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manu-
facturer. The two required registers are the bypass and boundary-scan registers. Figure 32 shows how the
instruction and various data registers are organized in an ispClock5300S.
36
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 32. ispClock5300S TAP Registers
Data Register
(42 Bits for ispClock5312S, 5308S 5304S,
61 Bits for ispClock5320S and 5316S)
E2CMOS
Non-Volatile
Memory
Address Register (10 Bits)
UES Register (32 Bits)
IDCODE Register (32 Bits)
Boundary Scan Register
(34 Bits for ispClock5312S, 5308S, 5304S,
50 Bits for ispClock5320S and 5316S)
Bypass Register (1 Bit)
Instruction Register (8 Bits)
Test Acess Port (TAP)
Logic
Output
Latch
TDI
TCK
TMS
TDO
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs.These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 33. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
37
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 33. TAP States
Test-Logic-Rst
1
0
0
1
1
1
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
Shift-DR
1
0
0
Shift-IR
0
1
Exit1-IR
0
1
1
Exit1-DR
0
Pause-DR
1
0
Pause-IR
1
0
0
0
Exit2-DR
Exit2-IR
1
1
Update-DR
Update-IR
1
0
1
0
Note: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state
and move to the desired state.The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction shift
is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruc-
tion shift is performed. The states of the Data and Instruction Register blocks are identical to each other differing
only in their entry points. When either block is entered, the first action is a capture operation. For the Data Regis-
ters, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previ-
ously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load
the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a
Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in a
compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state.
Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new
data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update
states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data
through either the Data or Instruction Register while an external operation is performed. From the Pause state,
shifting can resume by reentering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle
state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry
into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed,
erased or verified. All other instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec-
tively). The ispClock5300S contains the required minimum instruction set as well as one from the optional instruc-
tion set. In addition, there are several proprietary instructions that allow the device to be configured and verified.
38
Lattice Semiconductor
ispClock5300S Family Data Sheet
For ispClock5300S, the instruction word length is eight bits. All ispClock5300S instructions available to users are
shown in Table 4.
The following table lists the instructions supported by the ispClock5300S JTAG Test Access Port (TAP) controller:
Table 4. ispClock5300S TAP Instruction Table
Instruction
EXTEST
Code
Description
0000 0000 External Test.
0000 0001 Address register (10 bits)
ADDRESS_SHIFT
DATA_SHIFT
0000 0010 Address column data register (42 bits for ispClock5312S, 5308S and 5304S;
61 bits for ispClock5320S and 5316S)
BULK_ERASE
PROGRAM
0000 0011 Bulk Erase
0000 0111 Program column data register to E2
0000 1001 Program Electronic Security Fuse
0000 1010 Verify column
PROGRAM_SECURITY
VERIFY
DISCHARGE
PROGRAM_ENABLE
IDCODE
0001 0100 Fast VPP Discharge
0001 0101 Enable Program Mode
0001 0110 Address Manufacturer ID code register (32 bits)
0001 0111 Read UES data from E2 and addresses UES register (32 bits)
0001 1010 Program UES register into E2
USERCODE
PROGRAM_USERCODE
PROGRAM_DISABLE
HIGHZ
0001 1110 Disable Program Mode
0001 1000 Force all outputs to High-Z state
SAMPLE/PRELOAD
CLAMP
0001 1100 Capture current state of pins to boundary scan register
0010 0000 Drive I/Os with boundary scan register
0010 1100 Performs in-circuit functional testing of device.
0010 0100 Erases the ‘Done’ bit only
0010 0111 Program column data register to E2 and auto-increment address register
0010 1010 Load column data register from E2 and auto-increment address register
0010 1111 Programs the ‘Done’ Bit
INTEST
ERASE DONE
PROG_INCR
VERIFY_INCR
PROGRAM_DONE
NOOP
0011 0000 Functions Similarly to CLAMP instruction
BYPASS
1xxx xxxx
Bypass - Connect TDO to TDI
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the
ispClock5300S. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111).
The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The bit code for this instruction is defined by Lattice as shown in Table 4.
The EXTEST (external test) instruction is required and will place the device into an external boundary test mode
while also enabling the boundary scan register to be connected between TDI and TDO. The bit code of this instruc-
tion is defined by the 1149.1 standard to be all zeros (000000).
The optional IDCODE (identification code) instruction is incorporated in the ispClock5300S and leaves it in its func-
tional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO.
The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, device
type and version code (Figure 34). Access to the Identification Register is immediately available, via a TAP data
scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this
instruction is defined by Lattice as shown in Table 4.
39
Lattice Semiconductor
ispClock5300S Family Data Sheet
Figure 34. ispClock5300S Family ID Codes
MSB
LSB
XXXX / 0000 0001 0111 0010 /0000 0100 001 / 1
Version
(4 bits)
Constant ‘1’
(1 bit)
per 1149.1-1990
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Part Number
(16 bits)
0172h = ispClock5304S
(3.3V version)
E2 Configured
MSB
LSB
XXXX / 0000 0001 0111 0001 /0000 0100 001 / 1
Version
(4 bits)
Constant ‘1’
(1 bit)
per 1149.1-1990
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Part Number
(16 bits)
171h = ispClock5308S
(3.3V version)
E2 Configured
MSB
LSB
XXXX / 0000 0001 0111 0000/ 0000 0100 001 / 1
Version
(4 bits)
Constant ‘1’
(1 bit)
per 1149.1-1990
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Part Number
(16 bits)
0170h = ispClock5312S
(3.3V version)
E2 Configured
MSB
LSB
XXXX / 0000 0001 0111 1000 /0000 0100 001 / 1
Version
(4 bits)
Constant ‘1’
(1 bit)
per 1149.1-1990
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Part Number
(16 bits)
0178h = ispClock5316S
(3.3V version)
E2 Configured
MSB
LSB
XXXX / 0000 0001 0111 0110 /0000 0100 001 / 1
Version
(4 bits)
Constant ‘1’
(1 bit)
per 1149.1-1990
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Part Number
(16 bits)
0176h = ispClock5320S
(3.3V version)
E2 Configured
40
Lattice Semiconductor
ispClock5300S Family Data Sheet
In addition to the four instructions described above, there are 20 unique instructions specified by Lattice for the
ispClock5300S. These instructions are primarily used to interface to the various user registers and the E2CMOS
non-volatile memory. Additional instructions are used to control or monitor other features of the device, including
boundary scan operations. A brief description of each unique instruction is provided in detail below, and the bit
codes are found in Table 4.
PROGRAM_ENABLE – This instruction enables the ispClock5300S programming mode.
PROGRAM_DISABLE – This instruction disables the ispClock5300S programming mode.
BULK_ERASE – This instruction will erase all E2CMOS bits in the device, including the UES data and electronic
security fuse (ESF). A bulk erase instruction must be issued before reprogramming a device. The device must
already be in programming mode for this instruction to execute.
ADDRESS_SHIFT – This instruction shifts address data into the address register (10 bits) in preparation for either
a PROGRAM or VERIFY instruction.
DATA_SHIFT – This instruction shifts data into or out of the data register (43 bits for ispClock5312, 5308 and 5304;
61 bits for ispClock5320 and 5316), and is used with both the PROGRAM and VERIFY instructions.
PROGRAM – This instruction programs the contents of the data register to the E2CMOS memory column pointed
to by the address register. The device must already be in programming mode for this instruction to execute.
PROG_INCR – This instruction first programs the contents of the data register into E2CMOS memory column
pointed to by the address register and then auto-increments the value of the address register. The device must
already be in programming mode for this instruction to execute.
PROGRAM_SECURITY – This instruction programs the electronic security fuse (ESF). This prevents data other
than the ID code and UES strings from being read from the device. The electronic security fuse may only be reset
by issuing a BULK_ERASE command.The device must already be in programming mode for this instruction to exe-
cute.
VERIFY – This instruction loads data from the E2CMOS array into the column register. The data may then be
shifted out. The device must already be in programming mode for this instruction to execute.
VERIFY_INCR – This instruction copies the E2CMOS column pointed to by the address register into the data col-
umn register and then auto-increments the value of the address register. The device must already be in program-
ming mode for this instruction to execute.
DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispClock5300S for a read cycle.
PROGRAM_USERCODE – This instruction writes the contents of the UES register (32 bits) into E2CMOS memory.
The device must already be in programming mode for this instruction to execute.
USERCODE – This instruction both reads the UES string (32 bits) from E2CMOS memory into the UES register
and addresses the UES register so that this data may be shifted in and out.
HIGHZ – This instruction forces all outputs into a High-Z state.
CLAMP – This instruction drives I/O pins with the contents of the boundary scan register.
INTEST – This instruction performs in-circuit functional testing of the device.
ERASE_DONE – This instruction erases the ‘DONE’ bit only. This instruction is used to disable normal operation of
the device while in programming mode until a valid configuration pattern has been programmed.
PROGRAM_DONE – This instruction programs the ‘DONE’ bit only. This instruction is used to enable normal
device operation after programming is complete.
NOOP – This instruction behaves similarly to the CLAMP instruction.
41
Lattice Semiconductor
ispClock5300S Family Data Sheet
Pin Descriptions – ispClock5304S, 5308S, 5312S
Pin Number
ispClock5304S ispClock5308S ispClock5312S
Pin Name
VCCO_0
VCCO_1
VCCO_2
VCCO_3
VCCO_4
VCCO_5
GNDO_0
GNDO_1
GNDO_2
GNDO_3
GNDO_4
GNDO_5
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
VCCA
Description
Output Driver ‘0’VCC
Pin Type
Power
Power
Power
Power
Power
Power
GND
48 TQFP
48 TQFP
48 TQFP
5
32
—
5
9
1
Output Driver ‘1’VCC
5
Output Driver ‘2’VCC
28
9
Output Driver ‘3’VCC
—
32
28
Output Driver ‘4’VCC
—
—
32
Output Driver ‘5’VCC
—
—
36
Output Driver ‘0’ Ground
7
7
3
Output Driver ‘1’ Ground
GND
30
—
11
7
Output Driver ‘2’ Ground
GND
26
11
Output Driver ‘3’ Ground
GND
—
30
26
Output Driver ‘4’ Ground
GND
—
—
30
Output Driver ‘5’ Ground
GND
—
—
34
Clock Output driver 0, ‘A’ output
Clock Output driver 0, ‘B’ output
Clock Output driver 1, ‘A’ output
Clock Output driver 1, ‘B’ output
Clock Output driver 2, ‘A’ output
Clock Output driver 2, ‘B’ output
Clock Output driver 3, ‘A’ output
Clock Output driver 3, ‘B’ output
Clock Output driver 4, ‘A’ output
Clock Output driver 4, ‘B’ output
Clock Output driver 5, ‘A’ output
Clock Output driver 5, ‘B’ output
Analog VCC for PLL circuitry
Analog Ground for PLL circuitry
Digital Core VCC
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
GND
6
6
2
8
8
4
31
29
—
10
6
8
12
27
10
—
25
12
—
31
27
—
29
25
—
—
31
—
—
29
—
—
35
—
—
33
46
47
21, 22
23, 24, 48
14
46
46
GNDA
47
47
VCCD
Power
GND
21, 22
23, 24, 48
14
21, 22
23, 24, 48
14
GNDD
Digital GND
REFA_REFP Clock Reference A/Positive Differential
input3
Input
REFB_REFN Clock Reference B/Negative Differential
input3
Input
15
15
15
REFSEL
VTT_REFA
FBK
Clock Reference Select input (LVCMOS)
Termination voltage for reference input A
Feedback Input3
Input1
Power
Input
19
13
17
18
16
41
37
40
39
38
19
13
17
18
16
41
37
40
39
38
19
13
17
18
16
41
37
40
39
38
VTT_FBK
VTT_REFB
VCCJ
Termination voltage for feedback input
Termination input for reference input B
JTAG interface VCC
Power
Power
Power
Output
Input2
Input
TDO
JTAG TDO Output line
TDI
JTAG TDI Input line
TCK
JTAG Clock Input
TMS
JTAG Mode Select
Input2
42
Lattice Semiconductor
ispClock5300S Family Data Sheet
Pin Descriptions – ispClock5304S, 5308S, 5312S (Continued)
Pin Number
ispClock5304S ispClock5308S ispClock5312S
Pin Name
LOCK
Description
Pin Type
48 TQFP
48 TQFP
48 TQFP
PLL Lock indicator, HIGH indicates PLL lock Output
45
43
42
44
20
45
43
42
44
20
45
OEX
OEY
Output Enable X
Output Enable Y
Input1
Input1
Input1
Input2
n/a
43
42
PLL_BYPASS PLL Bypass
44
RESET
NC
Reset PLL
20
No internal connection
1, 2, 3, 4, 9, 10, 1, 2, 3, 4, 33, 34,
n/a
11, 12, 25, 26,
27, 28, 33, 34,
35, 36
35, 36
1. Internal pull-down resistor.
2. Internal pull-up resistor.
3. Must be connected to GNDD if this pin is not used.
43
Lattice Semiconductor
ispClock5300S Family Data Sheet
Pin Descriptions – ispClock5316S, 5320S
ispClock5316S ispClock5320S
Pin Name
VCC_0
Description
Pin Type
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
GND
64 TQFP
63
3
64 TQFP
63
3
Output Driver ‘0’VCC
Output Driver ‘1’VCC
Output Driver ‘2’VCC
Output Driver ‘3’VCC
Output Driver ‘4’VCC
Output Driver ‘5’VCC
Output Driver ‘6’VCC
Output Driver ‘7’VCC
Output Driver ‘8’VCC
Output Driver ‘9’VCC
VCC_1
VCC_2
7
7
VCC_3
11
38
42
46
50
—
—
64
6
11
17
32
38
42
46
50
64
6
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
GND_0
Output Driver ‘0’ GND
GND_1
Output Driver ‘1’ GND
GND
GND_2
Output Driver ‘2’ GND
GND
10
14
35
39
43
49
—
—
1
10
14
18
31
35
39
43
49
1
GND_3
Output Driver ‘3’ GND
GND
GND_4
Output Driver ‘4’ GND
GND
GND_5
Output Driver ‘5’ GND
GND
GND_6
Output Driver ‘6’ GND
GND
GND_7
Output Driver ‘7’ GND
GND
GND_8
Output Driver ‘8’ GND
GND
GND_9
Output Driver ‘9’ GND
GND
BANK_0A
BANK_0B
BANK_1A
BANK_1B
BANK_2A
BANK_2B
BANK_3A
BANK_3B
BANK_4A
BANK_4B
BANK_5A
BANK_5B
BANK_6A
BANK_6B
BANK_7A
BANK_7B
BANK_8A
BANK_8B
BANK_9A
BANK_9B
VCCA
Clock Output Driver 0, ‘A’ output
Clock Output Driver 0, ‘B’ output
Clock Output Driver 1, ‘A’ output
Clock Output Driver 1, ‘B’ output
Clock Output Driver 2, ‘A’ output
Clock Output Driver 2, ‘B’ output
Clock Output Driver 3, ‘A’ output
Clock Output Driver 3, ‘B’ output
Clock Output Driver 4, ‘A’ output
Clock Output Driver 4, ‘B’ output
Clock Output Driver 5, ‘A’ output
Clock Output Driver 5, ‘B’ output
Clock Output Driver 6, ‘A’ output
Clock Output Driver 6, ‘B’ output
Clock Output Driver 7, ‘A’ output
Clock Output Driver 7, ‘B’ output
Clock Output Driver 8, ‘A’ output
Clock Output Driver 8, ‘B’ output
Clock Output Driver 9, ‘A’ output
Clock Output Driver 9, ‘B’ output
Analog VCC for PLL Circuitry
Analog Ground for PLL circuitry
Digital Core VCC
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
GND
2
2
4
4
5
5
8
8
9
9
12
13
37
36
41
40
45
44
48
47
—
—
—
—
60
61
27, 28
12
13
15
16
34
33
37
36
41
40
45
44
48
47
60
61
27, 28
GNDA
VCCD
Power
44
Lattice Semiconductor
ispClock5300S Family Data Sheet
Pin Descriptions – ispClock5316S, 5320S (Continued)
ispClock5316S ispClock5320S
Pin Name
GNDD
Description
Pin Type
64 TQFP
64 TQFP
18, 29, 30, 31,
62
Digital GND
GND
29, 30, 62
REFA_REFP
REFB_REFN
REFSEL
VTT_REFA
FBK
Clock Reference A/ Positive Differential Input3
Clock Reference B/ Negative Differential Input3
Clock Reference Select input (LVCMOS)
Termination voltage for reference input A
Feedback input3
Input
Input
20
21
25
19
23
24
22
55
51
54
53
52
59
57
56
58
26
20
21
25
19
23
24
22
55
51
54
53
52
59
57
56
58
26
Input
Power
Input
VTT_FBK
VTT_REFB
VCCJ
Termination voltage for feedback input
Termination voltage for reference input B
JTAG Interface VCC
Power
Power
Power
Output
Input2
Input
Input2
Output
Input1
Input1
Input1
Input2
TDO
JTAG TDO output
TDI
JTAG TDI input
TCK
JTAG Clock input
TMS
JTAG Mode select
LOCK
PLL Lock indicator, HIGH indicates PLL Lock
Output enable X
OEX
OEY
Output enable Y
PLL_BYPASS
RESET
PLL Bypass
Reset PLL
15, 16, 17, 32,
33, 34
NC
No internal connection
N/A
—
1. Internal pull-down resistor.
2. Internal pull-up resistor.
3. Must be connected to GNDD if not used.
45
Lattice Semiconductor
ispClock5300S Family Data Sheet
Detailed Pin Descriptions
VCCO_[0..9], GNDO_[0..9] – These pins provide power and ground for each of the output banks. In the case when
an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to
ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When
a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1µF as close to its
VCCO and GNDO pins as is practical.
BANK_[0..9]A, BANK_[0..9]B – These pins provide clock output signals. The choice of output driver type (CMOS,
SSTL, etc.) may be selected on a bank-by-bank basis. The output impedance and slew rate may be selected on an
output-by-output basis.
VCCA, GNDA – These pins provide analog supply and ground for the ispClock5300S family’s internal analog cir-
cuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immu-
nity, it is suggested that the supply to the VCCA pin be isolated from other circuitry with a ferrite bead.
VCCD, GNDD – These pins provide digital supply and ground for the ispClock5300S family’s internal digital cir-
cuitry, and should be bypassed with a 0.1uF capacitor as close to the pins as is practical. To improve noise immu-
nity it is suggested that the supply to the VCCD pins be isolated with ferrite beads.
VCCJ – This pin provides power and a reference voltage for use by the JTAG interface circuitry. It may be set to
allow the ispClock5300S family devices to function in JTAG chains operating at voltages differing from VCCD.
REFA_REFP, REFB_REFN – These input pins provide the inputs for clock signals, and can accommodate either
single ended or differential signal protocols.
REFSEL – This input pin is used to select which clock input pair (REFA or REB) is selected for use as the reference
input. When REFSEL=0, REFA is used, and when REFSEL=1, REFB is used.
VTT_REFA, VTT_REFB – These pins are used to provide a termination voltage for the reference inputs when they
are configured for SSTL or HSTL logic, and should be connected to a suitable voltage supply in those cases.
FBK – This input pin provides feedback sense of the output clock signal, and can accommodate any of the single-
ended logic types.
VTT_FBK – This pin is used to provide a termination voltage for the feedback input when it is configured for SSTL
or HSTL logic, and should be connected to a suitable voltage supply in those cases.
TDO,TDI,TCK,TMS – These pins comprise the ispClock5300S device’s JTAG interface. The signal levels for these
pins are determined by the selection of the VCCJ voltage.
LOCK – This output pin indicates that the device’s PLL is in a locked condition when it goes HIGH.
OEX, OEY – These pins are used to enable the outputs or put them into a high-impedance condition. Each output
may be set so that it is always on, always off, enabled by OEX or enabled by OEY.
PLL_BYPASS – When this pin is pulled LOW, the V-dividers are driven from the output of the device’s VCO, and
the device behaves as a phase-locked loop. When this pin is pulled HIGH, the V-dividers are driven directly from a
selected reference input, and the PLL functions are effectively bypassed.
RESET – When this pin is pulled LOW, all on-board counters are reset, and lock is lost. If the RESET pin is not
driven by an external logic it should be pulled up to V
through a 10kΩ resistor.
CCD
NC – These pins have no internal connection. It is recommended that they be left unconnected.
46
Lattice Semiconductor
ispClock5300S Family Data Sheet
Package Diagrams
48-Pin TQFP (Dimensions in Millimeters)
PIN
1
INDICATOR
0.20 H A-B
D
D1
0.20 C A-B D
D
N
1
3.
A
E1
E
B
3.
e
D
3.
4X
8.
SEE DETAIL "A"
H
GAUGE PLANE
0.25
A
A2
A1
b
C
SEATING PLANE
0.08
M
C A-B D
0.08 C
0.20 MIN.
1.00 REF.
LEAD FINISH
0-7∞
b
L
c
c
1
DETAIL "A"
b
1
BASE METAL
SECTION B - B
SYMBOL
MIN.
-
NOM.
-
MAX.
1.60
0.15
1.45
A
NOTES:
A1
A2
D
0.05
1.35
-
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5
2. ALL DIMENSIONS ARE IN MILLIMETERS.
- 1982.
1.40
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.60
DATUMS A,
B AND D TO BE DETERMINED AT DATUM PLANE H.
3.
D1
E
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
DIMENSIONS.
E1
L
0.45
0.75
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
OF THE PACKAGE BY 0.15 MM.
N
48
6. SECTION B-B:
e
0.50 BSC
0.22
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
b
0.17
0.17
0.09
0.09
0.27
0.23
0.20
0.16
b1
c
0.20
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT ON THE PACKAGE BODY.
0.15
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8.
c1
0.13
47
Lattice Semiconductor
ispClock5300S Family Data Sheet
64-Pin TQFP (Dimensions in Millimeters)
PIN 1 INDICATOR
0.20
C
A-B D 64X
D
3
A
E
B
E1
e
3
D
D1
8
3
TOP VIEW
4X
0.20
H
A-B
D
BOTTOM VIEW
SIDE VIEW
SEE DETAIL 'A'
C
b
SEATING PLANE
LEAD FINISH
GAUGE PLANE
0.25
H
0.08
M
C A-B
D 64X
A
A2
A1
b
0.08 C
0.20 MIN.
1.00 REF.
0-7∞
L
c
c
1
DETAIL 'A'
SYMBOL
b
1
BASE METAL
MIN.
-
NOM.
MAX.
1.60
SECTION B-B
A
-
NOTES:
A1
A2
D
0.05
1.35
-
1.40
0.15
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
1.45
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.60
DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H.
D1
E
3.
4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1
DIMENSIONS.
E1
L
0.45
0.75
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
OF THE PACKAGE BY 0.15 MM.
N
64
6. SECTION B-B:
e
0.50 BSC
0.22
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP.
b
0.17
0.17
0.09
0.09
0.27
0.23
0.20
0.16
b1
c
0.20
7. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
TO THE LOWEST POINT ON THE PACKAGE BODY.
-
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8.
c1
-
48
Lattice Semiconductor
ispClock5300S Family Data Sheet
Part Number Description
ispPAC-CLK53XXS - 01 XXXX X
Device Family
Grade
I = Industrial Temp. Range
C = Commercial Temp. Range
Device Number
CLK5304S
CLK5308S
CLK5312S
CLK5316S
CLK5320S
Package
T48 = 48-pin TQFP
T64 = 64-pin TQFP
TN48 = Lead-Free 48-pin TQFP
TN64 = Lead-Free 64-pin TQFP
Performance Grade
01 = Standard
Ordering Information
Conventional Packaging
Commercial
Part Number
Clock Outputs
Supply Voltage
Package
TQFP
TQFP
TQFP
TQFP
TQFP
Pins
64
ispPAC-CLK5320S-01T64C
ispPAC-CLK5316S-01T64C
ispPAC-CLK5312S-01T48C
ispPAC-CLK5308S-01T48C
ispPAC-CLK5304S-01T48C
20
16
12
8
3.3V
3.3V
3.3V
3.3V
3.3V
64
48
48
4
48
Industrial
Part Number
ispPAC-CLK5320S-01T64I
ispPAC-CLK5316S-01T64I
ispPAC-CLK5312S-01T48I
ispPAC-CLK5308S-01T48I
ispPAC-CLK5304S-01T48I
Clock Outputs
Supply Voltage
3.3V
Package
TQFP
TQFP
TQFP
TQFP
TQFP
Pins
64
20
16
12
8
3.3V
64
3.3V
48
3.3V
48
4
3.3V
48
Lead-Free Packaging
Commercial
Part Number
Clock Outputs
Supply Voltage
3.3V
Package
Pins
64
ispPAC-CLK5320S-01TN64C
ispPAC-CLK5316S-01TN64C
ispPAC-CLK5312S-01TN48C
ispPAC-CLK5308S-01TN48C
ispPAC-CLK5304S-01TN48C
20
16
12
8
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
3.3V
64
3.3V
48
3.3V
48
4
3.3V
48
49
Lattice Semiconductor
ispClock5300S Family Data Sheet
Lead-Free Packaging (Cont.)
Industrial
Part Number
Clock Outputs
Supply Voltage
Package
Pins
64
ispPAC-CLK5320S-01TN64I
ispPAC-CLK5316S-01TN64I
ispPAC-CLK5312S-01TN48I
ispPAC-CLK5308S-01TN48I
ispPAC-CLK5304S-01TN48I
20
16
12
8
3.3V
3.3V
3.3V
3.3V
3.3V
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
64
48
48
4
48
50
Lattice Semiconductor
ispClock5300S Family Data Sheet
Package Options
ispClock5304S: 48-pin TQFP
NC
NC
1
36
35
34
33
32
31
30
29
28
27
26
25
NC
2
NC
NC
3
NC
NC
4
NC
VCCO_0
BANK_0A
GND_0
BANK_0B
NC
5
6
VCCO_1
BANK_1A
GNDO_1
BANK_1B
NC
ispPAC-CLK5304S-01T48C
7
8
9
NC
10
11
12
NC
NC
NC
NC
NC
51
Lattice Semiconductor
ispClock5300S Family Data Sheet
ispClock5308S: 48-pin TQFP
NC
NC
1
36
35
34
33
32
31
30
29
28
27
26
25
NC
2
NC
NC
3
NC
NC
4
NC
VCCO_0
BANK_0A
GNDO_0
BANK_0B
VCCO_1
BANK_1A
GNDO_1
BANK_1B
5
6
VCCO_3
BANK_3A
GNDO_3
BANK_3B
VCCO_2
BANK_2A
GNDO_2
BANK_2B
ispPAC-CLK5308S-01T48C
7
8
9
10
11
12
52
Lattice Semiconductor
ispClock5300S Family Data Sheet
ispClock5312S: 48-pin TQFP
VCCO_0
BANK_0A
GNDO_0
BANK_0B
VCCO_1
BANK_1A
GNDO_1
BANK_1B
VCCO_2
1
36
35
34
33
32
31
30
29
28
27
26
25
VCCO_5
BANK_5A
GNDO_5
BANK_5B
VCCO_4
BANK_4A
GNDO_4
BANK_4B
VCCO_3
BANK_3A
GNDO_3
BANK_3B
2
3
4
5
6
ispPAC-CLK5312S-01T48C
7
8
9
BANK_2A
GNDO_2
BANK_2B
10
11
12
53
Lattice Semiconductor
ispClock5300S Family Data Sheet
ispClock5316S: 64-pin TQFP
BANK_0A
BANK_0B
VCCO_1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
BANK_7A
BANK_7B
VCCO_6
3
BANK_1A
BANK_1B
GNDO_1
VCCO_2
4
BANK_6A
BANK_6B
GNDO_6
VCCO_5
5
6
7
BANK_2A
BANK_2B
GNDO_2
VCCO_3
8
9
BANK_5A
BANK_5B
GNDO_5
VCCO_4
ispPAC-CLK5316S-01T64C
10
11
12
BANK_3A
BANK_4A
BANK_3B
GNDO_3
NC
13
14
15
16
36
35
34
33
BANK_4B
GNDO_4
NC
NC
NC
54
Lattice Semiconductor
ispClock5300S Family Data Sheet
ispClock5320S: 64-pin TQFP
BANK_0A
BANK_0B
VCCO_1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
BANK_9A
BANK_9B
VCCO_8
3
BANK_1A
BANK_1B
GNDO_1
VCCO_2
4
BANK_8A
BANK_8B
GNDO_8
VCCO_7
5
6
7
BANK_2A
BANK_2B
GNDO_2
VCCO_3
8
9
BANK_7A
BANK_7B
GNDO_7
VCCO_6
ispPAC-CLK5320S-01T64C
10
11
12
BANK_3A
BANK_6A
BANK_3B
GNDO_3
13
14
15
16
36
35
34
33
BANK_6B
GNDO_6
BANK_4A
BANK_4B
BANK_5A
BANK_5B
55
Lattice Semiconductor
ispClock5300S Family Data Sheet
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-408-826-6002 (Outside North America)
e-mail: isppacs@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date
Version
Change Summary
April 2006
May 2006
01.0
Initial release.
01.1
Performance Characteristics-PLL table - Correction to min. output frequency, f
Skew Mode. Min frequency = 5MHz.
in Fine
OUT
Programmable Skew table - Correction to number of skew steps (from 16 to 8).
Programmable Skew table - Correction to Skew control range.
Output V Dividers section - Added explanation to V-divider settings as Power of 2 Settings
(1, 2, 4, 8, 16, 32).
June 2006
01.2
Added Reset Signal Slew Rate specification to Control Functions table.
Modified pin descriptions in Pin Descriptions table to reflect changes to pin 48 from NC to
GNDD.
Modified package diagrams to reflect the pin 48 changes from NC to GNDD.
Modified RESET pin description to include pull-up resistor when not driven.
Included references to ispClock5316S and ispClock5320S devices.
Added typical performance graphs.
October 2006
October 2007
01.3
01.4
Updated Boundary Scan Register information in ispClock5300S TAP Registers diagram.
Added support for the Internal Feedback mode of operation.
56
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