ISPPAC10 [LATTICE]

In-System Programmable Analog Circuit; 在系统可编程模拟电路
ISPPAC10
型号: ISPPAC10
厂家: LATTICE SEMICONDUCTOR    LATTICE SEMICONDUCTOR
描述:

In-System Programmable Analog Circuit
在系统可编程模拟电路

文件: 总23页 (文件大小:413K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
®
ispPAC 10  
In-System Programmable Analog Circuit  
Features  
Functional Block Diagram  
• IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG CIRCUIT  
— Four Instrument Amplifier Gain/Attenuation Stages  
— Signal Summation (Up to 4 Inputs)  
— Precision Active Filtering (10kHz to 100kHz)  
— No External Components Needed for Configuration  
— Non-Volatile E2CMOS® Cells (10,000 Cycles)  
— IEEE 1149.1 JTAG Serial Port Programming  
• FOUR LINEAR ELEMENT BUILDING BLOCKS  
— Programmable Gain Range (0dB to 80dB)  
— Bandwidth of 550kHz (G=1), 330kHz (G=10)  
— Low Distortion (THD < -74dB max @ 10kHz)  
— Auto-Calibrated Input Offset Voltage  
• TRUE DIFFERENTIAL I/O (±3V RANGE)  
— High CMR (69dB) Instrument Amplifier Inputs  
— 2.5V Common Mode Reference on Chip  
— Four Rail-to-Rail Voltage Outputs  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
OUT2+  
OUT2–  
IN2+  
OUT1+  
OUT1–  
IN1+  
OA  
OA  
3
IA  
IA  
IA  
IA  
4
IN2–  
IN1–  
5
TDI  
TEST  
TEST  
VREFOUT  
GND  
6
TRST  
VS  
Configuration Memory  
Analog Routing Pool  
7
8
TDO  
Reference & Auto-Calibration  
9
TCK  
CAL  
• 28-PIN PLASTIC DIP OR SOIC PACKAGE  
— Single Supply 5V Operation  
10  
11  
12  
13  
14  
IA  
IA  
IA  
IA  
TMS  
CMV  
IN  
• APPLICATIONS INCLUDE INTEGRATED:  
— Single +5V Supply Signal Conditioning  
— Active Filters, Gain Stages, Summing Blocks  
— Analog Front Ends, 12-Bit Data Acq. Systems  
— Sensor Signal Conditioning  
IN4–  
IN3–  
IN4+  
IN3+  
OUT4–  
OUT4+  
OUT3–  
OUT3+  
OA  
OA  
Description  
The ispPAC10 is a member of the Lattice family of In-  
SystemProgrammableanalogcircuits,digitallyconfigured  
via nonvolatile E CMOS technology.  
2
Typical Application Diagram  
5V  
5V  
Analog function modules, called PACblocks™, replace  
traditional analog components such as op amps and  
active filters, eliminating the need for most external  
resistors and capacitors. With no requirement for exter-  
nal configuration components, ispPAC10 expedites the  
design process, simplifying prototype circuit implemen-  
tation and change, while providing high performance and  
integrated functionality.  
12-Bit  
Differential  
Input ADC  
Vin  
Ain+  
Ain-  
Designers configure the ispPAC10 and verify its perfor-  
®
mance using PAC-Designer , an easy-to-use, Microsoft  
®
Windows compatible development tool. Device pro-  
gramming is supported using PC parallel port I/O  
operations. Alibraryofconfigurationsisincludedwithbasic  
solutions and examples of advanced circuit techniques.  
Ref+  
Ref-  
The ispPAC10 is configured through its IEEE Standard  
1149.1 (JTAG) compliant serial port. The flexible In-  
System Programming capability enables programming,  
verification and reconfiguration if desired, directly on the  
printed circuit board.  
ispPAC10  
Copyright©2000LatticeSemiconductorCorp. Allbrandorproductnamesaretrademarksorregisteredtrademarksoftheirrespectiveholders. Thespecificationsandinformationhereinaresubject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
September 2000  
pac10_04  
1
Specifications ispPAC10  
TA = 25°C; VS = 5.0V; Signal path = VIN to VOUT of one PACblock (second input unused); 1V VOUT 4V; Gain = 1; Output load = 200pf,  
1MΩ. Feedback enabled; Feedback capacitor = minimum; Auto-Cal initiated immediately prior. (Unless otherwise specified).  
DC Electrical Characteristics  
SYMBOL  
PARAMETER  
CONDITION  
MIN.  
TYP. MAX. UNITS  
Analog Input  
VIN± (1)  
Input Voltage Range  
Applied Either to VIN+ or VIN–  
1
6
4
V
Vp-p  
µV  
VIN-DIFF  
Differential Input Voltage Swing (2)  
Differential Offset Voltage (Input Referred)  
2| VIN+ VIN–  
G = 10  
|
VOS (2)  
20  
0.2  
50  
109  
2
100  
1.0  
G = 1  
mV  
VOS/T  
RIN  
Differential Offset Voltage Drift  
Input Resistance  
-40 to +85°C  
µV/°C  
CIN  
Input Capacitance  
pF  
IB  
Input Bias Current  
at DC  
3
pA  
eN  
Input Noise Voltage Density  
At 10kHz, Referred to Input, G = 10  
38  
nV/Hz  
Analog Output  
VOUT±  
Output Voltage Range  
Differential Output Voltage Swing (2)  
Output Current  
Present at Either VOUT+ or VOUT–  
0.1  
9.6  
4.9  
V
Vp-p  
mA  
V
VOUT-DIFF  
IOUT±  
2| VOUT+ VOUT|  
Source/Sink  
10  
VCM  
Common Mode Output Voltage  
(VOUT+ + VOUT-)/2 ; VIN+ = VIN–  
2.495  
2.500 2.505  
Static Performance  
G
Programmable Gain Range  
Gain Error  
Each Individual PACblock  
RL = 300Differential  
Between Two Inputs of Same PACblock  
-40 to +85°C  
0
20  
dB  
%
4.0  
Gain Matching  
3.0  
%
G/∆T  
Gain Drift  
20  
80  
77  
ppm/°C  
dB  
PSR  
Power Supply Rejection  
Differential at 1kHz  
Single-ended at 1kHz  
dB  
Common Mode Reference Output (VREFOUT  
)
VREFOUT  
CMVIN (4)  
Reference Output Voltage Range  
Nominally 2.500V  
Optional External Common-Mode Voltage  
-40 to +85°C  
-0.2  
0.2  
%
V
Common Mode Voltage Input  
Reference Output Voltage Drift  
Reference Output Current  
1.25  
3.25  
50  
50  
ppm/°C  
µA  
IREFOUT  
(VREFOUT = ±1%) Source  
(VREFOUT = ±1%) Sink  
350  
40  
µA  
Reference Output Noise Voltage  
Reference Power Supply Rejection  
10MHz Bandwidth; 1µF Bypass Capacitor  
1kHz  
µVRMS  
dB  
80  
Programming  
Erase/Reprogram Cycles  
10K  
cycles  
Digital I/O  
VIL  
Input Low Voltage  
Input High Voltage  
0
0.8  
VS  
V
V
VIH  
2.0  
IIL, IIH  
Input Leakage Current  
0V TCK Input VS  
0V CAL, TDI, TMS, TRST Inputs VS  
IOL = 4.0mA  
±10  
µA  
µA  
V
+40/-70  
0.5  
VOL  
Output Low Voltage (TDO)  
Output High Voltage (TDO)  
VOH  
IOH = -1.0mA  
2.4  
V
Power Supplies  
VS  
IS  
Operating Supply Voltage  
Supply Current  
4.75  
5.0  
5.25  
23  
V
VS = 5.0V  
VS = 5.0V  
mA  
mW  
PD  
Power Dissipation  
115  
Temperature Range  
Operation  
Storage  
-40  
-65  
+85  
°C  
°C  
+150  
2
Specifications ispPAC10  
AC Electrical Characteristics  
SYMBOL  
PARAMETER  
CONDITION  
MIN.  
TYP.  
MAX.  
UNITS  
Dynamic Performance  
THD  
Total Harmonic Distortion  
Differential  
FIN = 10kHz  
-88  
-72  
-67  
-63  
103  
69  
-74  
-62  
dB  
dB  
Single-Ended  
Differential  
FIN = 100kHz  
dB  
Single-Ended  
G = 1 to 10  
dB  
SNR  
CMR  
Signal to Noise  
0.1Hz to 100kHz  
10kHz  
dB  
Common Mode Rejection (VIN = 1V to 4V)  
Note: VIN+ and VIN- connected together  
dB  
100kHz  
55  
dB  
BW  
Small Signal Bandwidth  
G = 1  
550  
330  
330  
7.5  
4.0  
-90  
kHz  
kHz  
kHz  
V/µs  
µs  
G = 10  
VIN = 6  
BWFP  
SR  
Full Power Bandwidth  
Slew Rate  
VDIFF, VOUT = -3dB; G=1  
5.0  
10  
tS  
Settling Time  
Crosstalk  
0.1%  
6VDIFF Input Step  
Between Any Two Channels  
dB  
Filter Characteristics  
Filter Pole Programming Range  
Number of Poles in Range > 120  
Deviation From Calculated Value  
10kHz to 100kHz  
100  
5.0  
3.2  
kHz  
%
F0  
F0  
Absolute Pole Frequency Accuracy  
1.0  
Pole Step Size (Between Calculated Poles)  
Pole Frequency Change vs. Temperature  
%
F0/T  
-40 to +85°C  
0.02  
%/°C  
Notes: (1) A wider input range of 0.7V to 4.3V is typical, but not guaranteed. Inputs larger than this will be clipped. Input signals are also  
subject to common-mode voltage limitations. Refer to the table of conditions in this datasheet. (2) Refer to theory of operation section later in  
this datasheet for explanation of differential voltage swing computation. (3) To insure full spec performance an additional auto-calibration  
should be performed after initial turn-on and the device reaches thermal stability. (4) The user-provided voltage on this pin (CMVIN) becomes  
an optional (selected via programming) alternative to the default 2.5V VREFOUT  
.
Absolute Maximum Ratings  
Package Options  
Supply Voltage V .......................................-0.5 to +7V  
S
1
Logic and Analog Input Voltage Applied ........... 0 to V  
S
1
Logic and Analog Output Short Circuit Duration ..... Indefinite  
Lead Temperature (Soldering, 10 sec.).............. 260°C  
Ambient Temperature with Power Applied ... -55 to 125°C  
Storage Temperature................................ -65 to 150°C  
Note: Stresses above those listed may cause perma-  
nent damage to the device. These are stress only  
ratings and functional operation of the device at  
these or at any other conditions above those  
indicated in the operational sections of this speci-  
fication is not implied.  
28-Pin SOIC  
28-Pin PDIP  
Part Number Description  
ispPAC 10 XX X X  
ispPAC10 Ordering Information  
Device Family  
Device Number  
Ordering Number  
Package  
Performance Grade  
01 = Standard  
Package  
ispPAC10-01PI  
28-Pin DIP  
ispPAC10-01SI  
28-Pin SOIC  
P = PDIP, S = SOIC  
Grade  
Blank = Commercial  
I = Industrial Temperature  
3
Specifications ispPAC10  
Timing Specifications  
TA = 25°C; VS = +5.0V (Unless otherwise specified).  
SYMBOL  
PARAMETER  
CONDITION  
MIN.  
TYP.  
MAX. UNITS  
Dynamic Performance  
tckmin  
tckh  
Minimum Clock Period  
TCK High Time  
200  
50  
50  
15  
10  
15  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tckl  
TCK Low Time  
tmss  
TMS Setup Time  
tmsh  
tdis  
TMS Hold Time  
TDI Setup Time  
tdih  
TDI Hold Time  
tdozx  
tdov  
TDO Float to Valid Delay  
TDO Valid Delay  
60  
60  
60  
ns  
ns  
tdoxz  
trstmin  
tpwp  
TDO Valid to Float Delay  
Minimum reset pulse width  
Time for a programming operation  
Time for an erase operation  
Time for auto-cal operation on power-up  
Minimum auto-cal pulse width  
Time for user initiated auto-cal operation  
ns  
40  
80  
80  
ns  
Executed in Run-Test/Idle  
Executed in Run-Test/Idle  
100  
100  
250  
ms  
ms  
ms  
ns  
tpwe  
tpwcal1  
tcalmin  
tpwcal2  
Automatically executed at power-up  
40  
Executed on rising edge of CAL  
100  
ms  
tckh  
tckl  
tckmin  
tpwp, tpwe  
TCK  
tmss  
TCK  
TMS  
TDI  
tmss  
tmss tmsh  
*(PRGUSR/UBE executed in  
Run-Test/Idle state)  
TMS  
CAL  
tdis tdih  
(Note: CAL internally  
initiated at device turn-on.)  
tdozx  
tdov  
tdoxz  
tcalmin  
V
= 0V  
OUT  
DIFF  
V
TDO  
OUT  
tpwcal1, tpwcal2  
*Note: During device JTAG programming, analog outputs will stop responding to normal input stimulus. This is because all  
configuration information is erased and then re-written as part of a normal programming cycle, momentarily disrupting the input  
to output signal path. Behavior is not predictable during either of these steps since the analog outputs are not clamped during  
a programming cycle. Usually, however, the outputs will slew to either 0V (Ground) or 5V (Vsupply) or 2.5V (VREFOUT). This  
behavior is partially determined by conditions existing immediately prior to device reprogramming and intermediate configura-  
tions that occur during the process.  
4
Specifications ispPAC10  
Pin Descriptions  
Pin Symbol  
Name  
Description  
1
OUT2+  
Output 2(+)  
Differential output pin, VOUT . (Plus complement of VOUT with respect to VREFOUT,  
+
where differential VOUT = VOUT - VOUT ).  
+
-
2
3
4
5
6
OUT2-  
IN2+  
IN2-  
Output 2(-)  
Input 2(+)  
Input 2(-)  
Differential output pin, VOUT . (Minus component, where differential VOUT = VOUT - VOUT ).  
- + -  
Differential input pin, VIN . (Plus VIN, where differential VIN = VIN - VIN ).  
+
+
-
Differential input pin, VIN . (Minus component of differential VIN, where VIN = VIN - VIN ).  
-
+
-
TDI  
Test Data In  
Test Reset  
Serial interface logic input pin. Input data valid on rising edge of TCK.  
TRST  
Serial interface logic reset pin (input). Asynchronously resets logic controller. Active low.  
Reset is equivalent of power-on default.  
7
VS  
Supply Voltage  
Analog supply voltage pin (5V nominal).  
Should be bypassed to GND with 1µF and .01µF capacitors.  
8
TDO  
Test Data Out  
Test Clock  
Serial interface logic output pin. Input data valid on falling edge of TCK.  
Serial interface logic clock pin (input). Best analog performance when TCK is idle.  
Serial interface logic mode select pin (input).  
9
TCK  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
TMS  
Test Mode Select  
Input 4(-)  
IN4-  
Differential input pin, VIN  
Differential input pin, VIN  
-
IN4+  
Input 4(+)  
+
OUT4-  
OUT4+  
OUT3+  
OUT3-  
IN3+  
Output 4(-)  
Differential output pin, VOUT  
Differential output pin, VOUT  
Differential output pin, VOUT  
Differential output pin, VOUT  
-
Output 4(+)  
Output 3(+)  
Output 3(-)  
+
+
-
Input 3(+)  
Differential input pin, VIN  
Differential input pin, VIN  
+
-
IN3-  
Input 3(-)  
CMVIN  
Input for VCM Reference  
Input pin for optional (external) analog Common-Mode Voltage (VCM). Replaces VREFOUT  
(+2.5V) for any so programmed PACblock as its common-mode output voltage value.  
20  
21  
22  
CAL  
Auto-Calibrate  
Ground  
Digital input pin. Commands an auto-calibration sequence on a rising edge.  
Ground pin. Should normally be connected to analog ground plane.  
GND  
VREFOUT Common-Mode Reference Common-mode voltage reference output pin (+2.5V nominal). Must be bypassed to GND  
with a 0.1µF capacitor.  
23  
24  
25  
26  
27  
28  
TEST  
TEST  
IN1-  
Test Pin  
Manufacturing test pin. Connect to GND for proper circuit operation.  
Manufacturing test pin. Connect to GND for proper circuit operation.  
Test Pin  
Input 1(-)  
Input 1(+)  
Output 1(-)  
Output 1(+)  
Differential input pin, VIN  
Differential input pin, VIN  
-
IN1+  
+
OUT1-  
OUT1+  
Differential output pin, VOUT  
Differential output pin, VOUT  
-
+
Connection Notes  
Pin Configuration  
OUT2+  
OUT2–  
IN2+  
IN2–  
TDI  
TRST  
VS (5V)  
TDO  
OUT1+  
OUT1–  
IN1+  
IN1–  
TEST (tie to GND)  
TEST (tie to GND)  
VREFout  
GND (0V)  
CAL  
1. All inputs and outputs are labeled with plus (+) and  
minus (-) signs. Polarity is labeled for reference and  
can be selected externally by reversing pin connec-  
tions or internally under user programmable control.  
1
2. All analog output pins are hard-wiredto internal  
output devices and should be left open if not used.  
Outputs of uncommitted PACblocks are forced to  
TCK  
TMS  
IN4–  
VREF  
(2.5V) and can be used as low impedance  
OUT  
CMVin  
IN3–  
reference output buffers. V  
and V  
should not  
OUT+  
OUT-  
be tied together as unnecessary power will be dissi-  
pated.  
IN4+  
OUT4–  
OUT4+  
IN3+  
OUT3–  
OUT3+  
3. When the signal input is single-ended, the other half of  
the unused differential input must be connected to a  
28-Pin  
Top View  
DCcommon-modereference(usuallyVREF  
,2.5V).  
OUT  
5
Specifications ispPAC10  
Typical Performance Characteristics  
CMR vs. Frequency  
PSR vs. Frequency  
Input Noise Spectrum  
100  
90  
90  
1000  
100  
10  
Noise: Referred to Input  
G = 10  
80  
70  
60  
50  
40  
30  
80  
70  
60  
50  
40  
30  
20  
10  
100  
1k  
10k  
100k 1M  
100  
1k  
10k  
100k  
1M  
1
10 100  
1k  
10k 100k 1M  
Frequency (Hz)  
Frequency (Hz)  
Frequency (Hz)  
Small Signal BW vs. Gain  
THD vs. Frequency (Gain=1)  
THD vs. Frequency (Gain=10)  
-40  
-50  
-60  
-70  
21  
15  
9
-40  
-50  
-60  
-70  
G = 10  
G = 5  
Rload = 300Ω  
= 1kΩ  
Rload = 300Ω  
= 5kΩ  
= 600Ω  
= 5kΩ  
= No Load  
= 1kΩ  
= 600Ω  
= No Load  
G = 2  
G = 1  
3
-3  
-9  
-15  
-21  
-27  
-33  
-39  
-80  
-90  
-80  
-90  
-100  
-100  
1k  
10k  
100k  
1k  
10k  
100k  
1k  
10k  
100k  
1M  
10M  
Frequency (Hz)  
Frequency (Hz)  
Frequency (Hz)  
Capacitive Load Handling  
VOS Tempco  
VREFOUT Tempco  
24  
21  
18  
15  
12  
9
30  
25  
20  
15  
10  
5
30  
3 Wafer Lots  
PDIP Pkg  
-40°C to +85°C  
3 Wafer Lots  
PDIP Pkg  
0°C to +85°C  
25  
20  
15  
10  
5
6
3
0
0
0
0
-100  
-50  
+50 +100  
0
-160  
-80  
+80 +160  
10  
100  
1k  
10k  
µ
Offset Tempco (µV/°C)  
Offset Tempco ( V/°C)  
Capacitance (pF)  
6
Specifications ispPAC10  
Typical Performance Characteristics  
10.34kHz Filter FC Accuracy  
46.46kHz Filter FC Accuracy  
91.98kHz Filter FC Accuracy  
50  
40  
30  
20  
50  
50  
40  
30  
20  
2000 Units  
PDIP Pkg  
2000 Units  
PDIP Pkg  
2000 Units  
PDIP Pkg  
40  
30  
20  
10  
0
10  
0
10  
0
-4 -3 -2 -1  
0
1
2
3
4
-4 -3 -2 -1  
0
1
2
3
4
-4 -3 -2 -1  
0
1
2
3
4
Frequency Variation (%)  
Frequency Variation (%)  
Frequency Variation (%)  
Large-Signal Response  
Small-Signal Response  
20mV  
1µS  
1.0V  
1µS  
Gain = 1  
Load = No Load  
Gain = 1  
Load = No Load  
Large-Signal Response with 600pF Load  
Small-Signal Response with 600pF Load  
1.0V  
1µS  
20mV  
1µS  
Gain = 1  
Load = 600pF  
Gain = 1  
Load = 600pF  
7
Specifications ispPAC10  
Theory of Operation  
Introduction  
age common-mode reference or VREF  
pin (Pin 22).  
OUT  
The output common mode voltage is always referenced  
to 2.5V, regardless of the input common mode level. It is  
possible, when desired, to use an externally supplied  
The ispPAC10 consists of four programmable analog  
macrocells called PACblocks, each emulating a collec-  
tion of operational amplifiers, resistors and capacitors.  
Requiring no external components, it flexibly implements  
basic analog functions such as precision filtering, sum-  
ming/differencing,gain/attenuationandintegration.Each  
PACblock contains a summing amplifier, two differential  
input instrument amplifiers, and an array of feedback  
capacitors. The capacitors, combined with a fixed value  
feedbackelement,providemorethan120programmable  
poles between 10kHz to 100kHz with an absolute accu-  
racy of 5.0 percent. Variable gain input instrument  
amplifiers make it possible to program any PACblock  
gain in integer steps between ±1 and ±10. More complex  
signalprocessingfunctionsareperformedbyconfiguring  
additional PACblocks in combination with each other to  
achieve a variety of circuit functions.  
voltage instead of VREF  
, however. This optional  
OUT  
common-mode output voltage (V ) must be provided  
CM  
by the user via the CMV input pin (Pin 19). The only  
IN  
limitation is this reference voltage must be between  
1.25V and 3.25V. When an external voltage is present,  
an ispPAC10 must be programmed, on a per-PACblock  
basis, tousetheexternalreferenceinsteadoftheinternal  
2.5V.  
Configuring an ispPAC10 is accomplished using  
PAC-Designer, a Windows-based design environment.  
PAC-Designer includes an AC simulator for design veri-  
ficationpriortoprogramming. Theusercandownloadthe  
design to the ispPAC10 at any time via the devices IEEE  
Standard 1149.1 (JTAG) compliant serial port directly  
from the parallel port of a PC using an ispDOWNLOAD™  
cable. Once downloaded, the circuit topology and com-  
The ispPAC10 architecture is fully differential from input  
to output. This effectively doubles dynamic range versus  
single-ended I/O. It also affords improved performance  
withregardtospecificationssuchasinputcommonmode  
rejection (CMR) and total harmonic distortion (THD).  
2
ponent values are stored in non-volatile digital E CMOS  
cells on the ispPAC10 without any need for external  
programming voltages.  
Architecture  
Differential peak-peak voltage is determined by knowing  
the signal extremes on both differential input or output  
pins. For example, if V(+) equals 4V and V(-) equals 1V,  
the differential voltage is defined as V(+) - V(-) = Vdiff, or  
4V - 1V = +3V. Since either polarity can exist on differen-  
tial I/O pins, it is also possible for the opposite extreme to  
exist and would mean when V(+) equals 1V and V(-)  
equals 4V, the differential voltage is now 1V - 4V = -3V.  
To calculate the differential peak-peak voltage or full  
signal swing, the absolute difference between the two  
extreme Vdiffs is calculated. Using the previous ex-  
amples would result in |(+3V) - (-3V)| = 6V. It can be  
immediately seen that true differential signals result in a  
doubling of usable dynamic range. For more explanation  
of this and other differential circuit benefits, please refer  
to application note AN6019.  
In all ispPAC products, individual programmable circuit  
functions called PACellsare carefully combined to  
form larger analog macrocells or PACblocks. The isp-  
PAC10hasfoursuchPACblocksthatincorporatespecially  
configured PACells to perform amplification, summation,  
integration and filtering. Each of the four filtering/summa-  
tionorFilSumPACblockswithinispPAC10iscomprised  
of three separate PACells, two input instrument amplifi-  
ers and an output summing amplifier (see Figure 1). The  
input amplifier PACells act as front-end gain stages for  
the FilSum PACblock and allow multiple signals to be  
summed together. The PACblocks output amplifier is  
similar to the familiar operational amplifier except that it  
has true differential outputs. Also included with each  
output amplifier is a filter capacitor array and switchable  
DC feedback path element. These components in com-  
bination enable the filtering and integrating functions of  
the FilSum PACblock.  
Input polarity is programmable without affecting input  
impedance or dynamic performance, since no internal  
change is made other than routing to the input amplifier.  
Single-ended operation is achieved by using either one  
input and/or one output pin, as required, and adjusting  
gain settings to achieve desired output levels.  
The ispPAC10 operates on a single 5V supply and  
includes an internal reference generating 2.5V. This  
reference is made available externally through the volt-  
8
Specifications ispPAC10  
Theory of Operation (Continued)  
Figure 1. FilSum (Filtering/Summation) PACblock  
Diagram  
functionality: Signals can be summed, the resistive am-  
plifier feedback can be removed to create an integrator,  
the sign of PACblock transfer function can be changed  
without changing the input or output loading characteris-  
tics. The FilSum PACblock can precisely filter, amplify or  
attenuate signals, always maintaining the high imped-  
ance input qualities of instrumentation amplifiers.  
IA1  
V
C
F
IN+  
V
g
g
IN  
m1  
IAF  
m3  
V
OUT+  
V
IN-  
g
FilSum PACblock Operation  
V
OUT  
IA2  
m2  
V
V
IN+  
OUT-  
AllispPAC10inputsaredifferential,theinputsignalbeing  
the difference between input amplifier (IA) PACell pins  
V
IN  
C
F
V
V
(PositiveInput)andV (MinusInput). Thecommon  
IN-  
IN+  
IN-  
mode value of the input is ignored, and as long as the  
inputs are not within one volt of the supply rails, the part  
is in its linear operating region. As the input signal range  
exceeds these limits, distortion begins to increase until  
clippingoccurs. Thisisdiscussedfurtherintheadvanced  
topics section.  
Each FilSum PACblock actually employs three instrument  
amplifier(IA)PACells:twoattheinput(IA1andIA2)andone  
as a feedback element around the op amp (IAF). The  
instrument amplifier PACells all have differential I/O and  
convert an input voltage to an output current (refer to Figure  
2). This type of amplifier is sometimes referred to as an  
operational transconductance amplifier or OTA. When a  
differential input voltage is applied to these IAs, it is  
converted to a current proportional to the input signal.  
Because an AC signal common to both of the high  
impedance inputs of the IA does not create a net differ-  
ence in the input signal, it is rejected by the amplifier. This  
characterizes the function of what is commonly known as  
an instrument amplifier and is a very desirable property  
because it acts to preserve the integrity of small signals  
in the presence of otherwise overwhelming noise.  
The output is also differential, being the difference be-  
tween output amplifier (OA) PACell pins V  
and  
OUT+  
V
OUT-  
.Theoutputmaintainshighlinearitytowithin100mV  
of the supply rails under minimum load. The output has  
short circuit protection and is capable of driving resistive  
loads as low as 300or capacitances as large as  
1000pF.Theoutputcommonmodevoltageismaintained  
at VREF  
independent of the input common mode  
OUT  
level. That is, the output amplifier PACell re-references”  
the common mode level of the input signal. This is  
accomplished by continuously sensing the output com-  
mon mode voltage and comparing it to VREF  
as  
OUT  
shown in Figure 3, and makes it possible to use an  
individual FilSum PACblock as a VREF reference as  
Figure 2. Instrument Amplifier PACell  
OUT  
discussed in the section titled Using VREF  
.  
OUT  
Figure 3. Output VREFOUT Re-Referencing  
V
I
M
IN+  
C
F
g
V
m
IN  
V
I
P
IN-  
V
IAF  
OUT  
The two input instrument amplifiers have a program-  
mable transconductance (g ) value in 10 steps between  
m
2µA/V and 20µA/V with programmable input polarity,  
whereas the feedback amplifier is fixed at 2µA/V. The IA  
PACells exhibit extremely high input impedance so they  
dont load circuitry driving them and their outputs can be  
enabled or disabled under E CMOS control, effectively  
switching them in and out of the FilSum PACblock cir-  
cuitry. These simple characteristics permit a great deal of  
VCM  
IN (2.5V)  
C
F
Input Offset Auto-Calibration. A unique feature of the  
ispPAC10 is its ability to automatically calibrate itself to  
achieve very low offset error. This is done utilizing on-  
chip circuitry to perform an auto-calibration (auto-cal)  
2
9
Specifications ispPAC10  
Theory of Operation (Continued)  
sequence every time the device is turned on, or anytime feedbackcapacitancetooptimizethestepresponse. The  
it is commanded externally via the CAL pin or by a JTAG trimmed step response resembles that of a critically  
programming command. With this feature, the degrada- damped system with minimum overshoot.  
tion of device offset performance that could occur over  
The bandwidth trim ensures a nominal feedback capaci-  
time and temperature is dramatically reduced. Specifi-  
tanceisalwayspresent,limitingthesmallsignalbandwidth  
cally, this means one PACblock of an ispPAC10 in a gain  
of an OA PACell to about 600kHz when configured in a  
configuration of one is guaranteed to never have an input  
gain of 1 (G=1). This should not be confused with the  
offset error greater than 1mV, after being auto-cali-  
gain-bandwidth product of the op amp within the output  
brated. For higher gain settings when offset is especially  
amplifier PACells which is approximately 5MHz. It is  
important, the error is not multiplied by gain, but is  
important to note that the individual output amplifiers are  
instead divided by it, due to the unique architecture of the  
always in essentially the same fixed gain configuration  
ispPAC10. WhenanindividualPACblockisconfiguredin  
and do not, therefore, contribute to a decrease in signal  
bandwidth at higher PACblock gain settings. Since the  
gain of an individual PACblock is determined by varying  
a gain of ten, that results in an input referred offset error  
that never exceeds 100µV.  
Internally, auto-calibration is accomplished by simulta- the g of the input amplifier, bandwidth is not reduced in  
m
neous successive approximation routines (SAR) to direct proportion to gain, as it would be in a traditional  
determine the amount of offset error referred to each of voltage feedback amplifier configuration. Specifically,  
the four PACblock output amplifiers of the ispPAC10. smallsignalbandwidthisonlyreducedbyafactorof2,not  
That error is then nulled by a calibration DAC for each the expected 10, with a PACblock gain setting change of  
output amplifier. The calibration constant is not stored in G=1 to G=10. This is a significant advantage of the  
2
E CMOS memory, but is recomputed each time the PACblock architecture.  
device is powered up or auto-cal is otherwise initiated.  
Initiation of auto-cal occurs when an ispPAC10 is pow-  
Pole Accuracy Trim. Separate from the bandwidth trim  
capacitance, each FilSum PACblock contains a range of  
ered on as part of its normal power on routine, or by a  
user selectable op amp feedback capacitance. This is  
positive going pulse to the CAL pin (Pin 20), or by issuing  
made possible by a parallel arrangement of seven ca-  
the appropriate JTAG command.  
2
pacitors,eachinserieswithanE CMOSswitch.Theuser  
During auto-cal, all ispPAC10 outputs are driven to 0V controls the position of the switches when selecting from  
and remain there until calibration is complete. The timing the available capacitor values. The resulting capacitance  
for the calibration process is generated internally. At is in parallel with the op amp feedback element, IAF,  
poweron, thesequencetakesamaximumof250ms, and making 128 possible pole locations available. The ca-  
when auto-cal is initiated via the CAL pin or by JTAG pacitor values are not binarily weighted, instead they are  
programming, it takes a maximum of 100ms to complete. chosen to optimize and concentrate pole spacing below  
The longer time required at power on insures the device 100kHz. There are 122 poles between 10kHz and  
power supply reaches its final value before calibration 96kHz, which guarantees a step of no greater than 3.2%  
begins. Additional attempts to initiate auto-cal once cali- anywhere in that frequency range (to the nearest com-  
bration is in progress are ignored. Finally, the only direct puted pole location). In fact, step size in over 50% of that  
indication of auto-cal completion will be the devices range is less than 1.0%. Finally, capacitors are trimmed  
outputs returning to operational values from the 0V to achieve 5.0% accuracy (absolute) with regard to their  
clamped state.  
nominal value.  
To insure maximum accuracy of the auto-cal procedure,  
all digital signals to the ispPAC10 should be suspended  
when calibration is in progress to avoid feed-through of  
noise to critical analog circuitry. This is especially true  
when auto-cal is initiated via JTAG command and the  
programming port is in use. There is sufficient time,  
however, to clock the JTAG controller back to its reset”  
state without affecting the calibration process.  
PACblock Transfer Function  
The block diagram for a PACblock is shown in Figure 1.  
The transfer function for a transconductor is:  
I
= - g · V  
IN  
(1)  
(2)  
P
m
I
= g  
V
·
m IN  
M
Bandwidth Trim. The bandwidth of an OA PACell is  
trimmedduringmanufacturingbyadjustingtheamplifiers  
Using KCL (Kirchoffs current law) at the op amp inputs  
and assuming the input is connected to IA1 only:  
10  
Specifications ispPAC10  
Theory of Operation (Continued)  
- V  
V
g
+ V  
g
+(V  
(V- ))sC  
F
(3a)  
(3b)  
Figure 4. PAC-Designer FilSum PACblock  
IN m1  
OUT m3  
OUT+  
g
- V  
g
+(V  
(V+))sC  
PACblock  
C
F
Feedback Enable  
1pF to 62pF  
IN m1  
OUT m3  
OUT- F  
k
1
2
2
where V- and V+ are the voltages at the op amp inverting  
and non-inverting inputs respectively. Because of feed-  
back they are equal, so  
IA1  
Differential  
Output  
Two  
Differential  
Inputs  
R
Summation  
F
2
OA1  
IA2  
Common-  
Mode Voltage  
Input  
2.5V  
-VIN gm1 + VOUT gm3 +(VOUT+sCF )  
k
2
k
=1, 2...10  
(4)  
N
= VIN gm1 VOUT gm3 +(VOUT- sCF )  
TheFilSumPACblockimplementstwoprimaryfunctions:  
the lossy integrator (low pass filter) and the integrator,  
both with gain.  
and the differential output voltage V  
is the difference  
OUT  
V
- V  
,
OUT+  
OUT-  
VOUT  
VIN  
gm1  
sCF  
LossyIntegrator.Thelossyintegratorsschematicwithin  
PAC-Designer is shown in Figure 5. Manipulating the  
PACblock transfer function of Equation 5 to better show  
the pole frequency yields:  
=
(5a)  
gm3  
+
2
Since the PACblock has two separate inputs (IA1 and  
IA2) summed at the output amplifier input:  
k V +k V  
2 IN2  
1 IN1  
V
=
OUT  
sC  
F
(6)  
1+  
k1gmVIN1 +k2gmVIN2  
2g  
m
VOUT  
=
sCF  
2
(5b)  
gm3  
+
Figure 5. PAC-Designer PACblock Lossy Integrator  
The input amplifiers have a programmable gain of  
k·2µA/V (g and g ) where k is an integer from -10 to  
C
F
k
1
m1  
m2  
10.Thefeedbackamplifiertransconductanceg isfixed  
V
V
IN1  
IA1  
m3  
at 2µA/V, but may be disabled (g = 0) to open-circuit  
R
F
m3  
the output amplifiers resistive feedback. The program-  
mable feedback capacitance lies in the range 1pF to  
62pF.  
OA1  
2.5V  
V
OUT  
IN2  
IA2  
k
2
The PACblock model from PAC-Designer is shown in  
Figure 4. The output amplifier is configured as an invert-  
ing mode op amp and illustrates the summing  
configuration. The input instrument amplifiers are shown  
to make it clear that unlike a typical inverting op amp, the  
PACblock input impedance is extremely high. The input  
amplifier (IA) transconductance (gain) is shown as the  
value (k) above or below each amplifier. The gain of IA1  
and IA2 are independently programmable. Because the  
The DC gain of each input is set by k or k respectively,  
1
2
the gain constant for the input amplifiers. Below the pole  
frequency, this circuit can be viewed as a gain block.  
Because of the bandwidth trim capacitance, there is a  
minimum value of C causing the bandwidth to be ap-  
F
proximately 550kHz when the DC gain is one. For larger  
gains, the input amplifier bandwidth begins to dominate  
the overall PACblock response, limiting the bandwidth to  
about 330kHz when the gain is 10.  
feedback transconductor IAF (designated here as R )  
F
can be disabled by the user, a user configurable switch  
is shown in series.  
Examining this transfer function shows the pole fre-  
quency is (1/2π)(2g /C). Since g = 2µA/V and 1pF C  
m
m
F
62pF, then 600kHz f 10kHz. Due to the selection  
P
options for feedback capacitance, there are at least 120  
poles between 10kHz and 100kHz.  
11  
Specifications ispPAC10  
Theory of Operation (Continued)  
Integrator. Switching out R (turning off IAF) removes ItcanalsobeseenthatthetransferfunctionV (s)/V (s)  
F
FB  
IN  
the feedback element as shown in Figure 6. The implementsalowpassfilter. Thisapplicationisdiscussed  
integrators transfer function can be derived from Equa- further in a separate application note.  
tion 5b by setting g = 0 (open circuit IAF (R )).  
m3  
F
Figure 7b. Biquad Bandpass Filter Schematic  
Figure 6. PAC-Designer PACblock Integrator  
(IAF Disabled; gm3 = 0)  
8.19pF  
C
F
1
PACblock 1  
OUT1  
k
1
IA1  
V
V
IN1  
IA1  
R
F
OA1  
2.5V  
OA1  
V
OUT  
IA2  
-1  
IN2  
IN1  
IN2  
IA2  
2.5V  
k
2
16.05pF  
PACblock 2  
-1  
IA3  
k V +k V  
2 IN2  
1 IN1  
V
=
OUT  
sC  
F
(7)  
OA2  
2.5V  
2g  
m
IA4  
1
OUT2  
Theintegratorslopeisproportionalto1/fand,forthecase  
of a single input, the transfer function magnitude equals  
|k| when the frequency is (1/2π)(2g /C). The integrator  
m
should not be used as a stand-alone circuit element. It  
needs to be used in configurations that provide DC  
feedback to ensure the output does not saturate, as  
illustrated by the biquad filter circuit below.  
Attenuator. The PACblock architecture makes varia-  
tions possible on these two basic building blocks just  
described. An example uses summation to connect an  
input amplifier (IA2) in parallel with the feedback element  
(R ), as shown in Figure 8.  
F
Application Examples  
Figure 8. PACblock AV < 1  
Biquad Filter. By simply combining the two structures,  
the integrator providing feedback around the lossy inte-  
grator, creates a useful circuit. The block diagram is  
shown in Figure 7a  
C
R
F
k
1
V
IA1  
IN1  
F
Figure 7a. Biquad Bandpass Filter Block Diagram  
OA1  
V
OUT  
IA2  
2.5V  
B
Error  
k
2
V
V
s
IN  
OUT1  
(OUT1)  
1 +  
p
(IN1)  
1
The result is a circuit whose transfer function is:  
V
V
k
FB  
OUT  
1
A
s
= -  
V
OUT2  
sC  
V
F
IN  
(8)  
k –  
(OUT2)  
2
2g  
m
andtheschematicfromPAC-DesignerisshowninFigure  
7b. The transfer function OUT1(s)/IN1(s) is a band pass  
filter with programmable gain, Q and center frequency.  
Note the presence of DC feedback around the integrator.  
The gains k and k are independently set by the user;  
1
2
this circuit can either amplify or attenuate an input signal.  
The one in the denominator is due to R ; if R is disabled,  
F
F
12  
Specifications ispPAC10  
Theory of Operation (Continued)  
this term is eliminated. The level of attainable attenuation  
Interfacing  
is as low as 1/11 (-20.8dB) with R enabled or  
F
When used in a single-supply system where the system  
1/10 (-20dB) with R disabled.  
F
common mode voltage is near V /2, signals may be  
S
When configuring a PACblock to attenuate, it is neces-  
sary to increase the value of feedback capacitance to  
maintain stability. Increasing feedback capacitance has  
the same beneficial effect as for a discrete op amp: It  
increases the networks phase margin which assists in  
maintaining stability.  
directly connected to the ispPAC10 input. If the input  
signal does not have such a DC bias, then one needs to  
be added to the signal in order to accommodate the input  
requirements for the ispPAC10. A DC coupled bias can  
be added to a signal by using a voltage divider circuit as  
shown for one-half of the differential input in Figure 10a.  
Normally the choice for the reference DC voltage is the  
supply voltage, but other values may be used if neces-  
sary (and available).  
Using VREFOUT  
The VREF  
output is high impedance and it should be  
OUT  
buffered when used as a reference. A PACblock can be  
made into a VREF buffer as shown in Figure 9. The  
Figure 10a. DC Biasing an Input Signal  
OUT  
PACblock inputs are left unconnected and the feedback  
closed. In this condition the input amplifiers are tied to  
VREF  
forced to VREF  
and the output amplifiers outputs are thus  
OUT  
VREF  
OUT  
or 2.5V. Either output is now a  
OUT  
VREF  
voltage source. This reference has the same  
OUT  
R
2
drive capabilities of any ispPAC10 output. However, do  
not short the two outputs together. There is a small  
potential difference between them which will cause a  
steady state current to flow, thus needlessly dissipating  
power.  
V
IN+  
V
SE  
R
1
V
IN-  
*
*Single-Ended V  
:
SE  
Connect to VREF  
Figure 9. PACblock as VREFOUT Buffer  
or  
OUT  
other DC Reference.  
*Differential V  
:
SE  
OUT1=2.5V  
Duplicate Vin+ Network  
on Vin-.  
Unconnected  
1.07pF  
1
PACblock 1  
OUT1  
IN1  
V
R
VREF  
R
IA1  
SE  
2
OUT 1  
V
=
+
IN+  
R +R  
R +R  
1 2  
1
2
OA1  
2.5V  
IA2  
-1  
Where DC coupling is not required, the input signal may  
be AC coupled as shown in Figure 10b. This circuit forms  
a high pass filter with a cutoff frequency of 1/(2πRC) and  
adds the necessary DC bias to the signal to accommo-  
datetheispPAC10inputrequirements.TheDCreference  
It is not always necessary to buffer the VREF  
output.  
OUT  
If it is used to reference a high impedance source, i.e.,  
one that does not require more than 10µA, then it can be  
directly connected. An example is shifting the DC level of  
a signal connected to the input of a PACblock. In this  
case, the signal is AC coupled and terminatedin  
should equal V /2, making VREF  
the natural choice.  
S
OUT  
TheminimumresistancewhenusingtheVREF  
buffer  
OUT  
circuit of Figure 9 is 600; when using the VREF  
output pin it is 200k(as discussed earlier).  
OUT  
VREF  
through a minimum total resistance of 100k.  
OUT  
Referring to Figure 10b, if R is greater than 200kthen  
IN  
the VREF  
pin may be used without buffering.  
OUT  
13  
Specifications ispPAC10  
Theory of Operation (Continued)  
Figure 10b. AC-coupled Input with DC Bias  
requires DC current, the amount available for voltage  
swing is reduced. The output is capable of 10mA, so any  
DC current raises the minimum allowable load imped-  
ance.  
Noise vs. Gain  
C
IN  
Noise gain is the gain of a circuit configuration to its  
combined input-referred circuit noise. The noise gain of  
an inverting op amp circuit is:  
V
IN+  
C
IN  
V
IN-  
(9)  
Noise Gain =1+ClosedLoop Voltage Gain  
R
IN  
In this case, the noise gain of the circuit increases  
proportionally to the circuit gain.  
A FilSum PACblock contains an input amplifier stage  
followed by an output amplifier. In this way it can be  
viewed as a system, with each of the components having  
its own contribution to the overall noise as shown in  
VREF  
OUT  
Figure 11. Both the output amplifier noise (N ) and input  
2
Single-ended Operation  
amplifier noise (N ) contribute to the overall noise perfor-  
1
mance, but the contribution due to the output amplifier  
dominatesexceptatinputgainsnear10.Theresultisthat  
the SNR of a FilSum PACblock is nearly constant versus  
gain. This is different than the behavior predicted by  
Equation 9.  
Single-endedsignalsmaybeconnectedtotheispPAC10  
input and one of the two differential ispPAC10 outputs  
can be used to drive single-ended circuitry. So, in addi-  
tion to fully differential I/O, either the input, output or both  
may be used single-ended.  
Figure 11. Multistage ispPAC Noise Diagram  
Single-ended Input. To connect the ispPAC10 differen-  
tial input to a single-ended signal, one of the differential  
inputs needs to be connected to a DC bias, preferably  
VREF  
. The input signal must either be AC coupled  
OUT  
N
N
2
G
G
2
1
1
(as in Figure 10b) or have a DC bias equal to the DC level  
of the other input. Since the input voltage is defined as  
V
- V , the common mode level is ignored. The signal  
IN+ IN-  
Stage One  
Stage Two  
information is only present on one input, the other being  
connected to a voltage reference.  
G
2 = Constant  
Single-endedOutput.Connectingtheoutputtoasingle-  
ended circuit is simpler still. Simply connect one-half of  
the differential output, but not the other. Either output  
conveys the signal information, just at half the magnitude  
of the differential output. The DC level of the single-  
2
N
2
2
Output Noise Voltage = G G  
N +  
1
(10a)  
(10b)  
1
2
G
1
If N /G > 3·N , then  
2
1
1
ended output will be VREF  
due to the re-referencing  
OUT  
Output Noise Voltage G N  
2
2
aspect of the FilSum PACblock. If the load is not AC  
coupled and is at a DC potential other than VREF , the  
OUT  
There is a few dB decrease in SNR as the gain ap-  
proaches10.Thischaracteristicimpliestheinputamplifier  
noise contribution is approaching that of the op amp. As  
the gain of the input amplifier nears 10, its noise contribu-  
tion in Equation 10a (N ) approaches that of the op amp  
and becomes a factor in the overall output noise voltage,  
causing it to increase.  
load draws a constant current. Using one of the differen-  
tial outputs halves the available output voltage swing  
(3V versus6V )andsincetheoutputcurrentcapacity  
PP  
PP  
isthesamewhetherdrivingdifferentiallyorsingle-ended,  
a single output can drive twice the load as the differential  
output (150vs. 300or 2000pF vs. 1000pF). If the load  
1
14  
Specifications ispPAC10  
Theory of Operation (Continued)  
reached for a particular gain. The lowest V for a given  
Input Common-Mode Voltage Range  
CM  
gain setting is expressed by the formula, V  
= 0.675V  
CM–  
For the ispPAC10, both maximum input signal range and  
corresponding common-mode voltage range are a func-  
tion of the input gain setting. The maximum input voltage  
times the gain of an individual PACblock cannot exceed  
the output range of that block or clipping will occur. The  
+ 0.584G·V where G is the gain setting and V is the  
IN  
IN  
peak input voltage, expressed as |V  
- V | and the  
IN+  
IN–  
highest V  
is V  
= 5.0V - V  
where 5V is the  
CM–  
CM  
CM+  
nominal supply voltage.  
maximum guaranteed input range is 1V to 4V, with an In Table 1, the maximum V for a given V  
to V  
CM+  
IN  
CM–  
extended typical range of 0.7V to 4.3V for a 5V supply range is given. If the maximum V is known, find the  
IN  
voltage.  
equivalent or greater value under the appropriate gain  
column and the widest range for V will be found  
CM  
The input common-mode voltage is V = (V  
When the value of V is 2.5V, there are no further input  
restrictions other than the previously mentioned clipping  
consideration. This is easily achieved when the input  
signal is true differential and referenced to 2.5V.  
+ V )/2.  
CM  
CM+  
CM-  
horizontally across in the left-most two columns. Only a  
range equal to or less than this will give distortion-  
CM  
V
CM  
freeperformance.Conversely,ifthemaximumV range  
CM  
is known, the largest acceptable peak value of V can be  
IN  
found in the corresponding gain column. All values of V  
less than this will give full rated performance.  
IN  
When V is not 2.5V and the gain setting is greater than  
CM  
one, distortion will occur when the maximum input limit is  
Table 1. Input Common-Mode Voltage Range Limitations  
Input Voltage Magnitude (Volts-Peak)  
G=2 G=3 G=4 G=5 G=6  
0.186 0.139 0.111 0.093  
VCM-  
1.000  
1.100  
1.200  
1.300  
1.400  
1.500  
1.600  
1.700  
1.800  
1.900  
2.000  
2.100  
2.200  
2.300  
2.400  
2.426  
2.500  
VCM+  
4.000  
3.900  
3.800  
3.700  
3.600  
3.500  
3.400  
3.300  
3.200  
3.100  
3.000  
2.900  
2.800  
2.700  
2.600  
2.574  
2.500  
G=1  
G=7  
G=8  
G=9  
G=10  
0.056  
0.073  
0.090  
0.107  
0.124  
0.141  
0.158  
0.176  
0.193  
0.210  
0.227  
0.244  
0.261  
0.278  
0.295  
0.557  
0.728  
0.899  
1.071  
1.242  
1.413  
1.584  
1.756  
1.927  
2.098  
2.270  
2.441  
2.612  
2.783  
2.955  
0.278  
0.364  
0.450  
0.535  
0.621  
0.707  
0.792  
0.878  
0.964  
1.049  
1.135  
1.220  
1.306  
1.392  
1.477  
0.080  
0.104  
0.128  
0.153  
0.177  
0.202  
0.226  
0.251  
0.275  
0.300  
0.324  
0.349  
0.373  
0.398  
0.422  
0.070  
0.091  
0.112  
0.134  
0.155  
0.177  
0.198  
0.219  
0.241  
0.262  
0.284  
0.305  
0.327  
0.348  
0.369  
0.062  
0.081  
0.100  
0.119  
0.138  
0.157  
0.176  
0.195  
0.214  
0.233  
0.252  
0.271  
0.290  
0.309  
0.328  
0.243  
0.300  
0.357  
0.414  
0.471  
0.528  
0.585  
0.642  
0.699  
0.757  
0.814  
0.871  
0.928  
0.985  
0.182  
0.225  
0.268  
0.310  
0.353  
0.396  
0.439  
0.482  
0.525  
0.567  
0.610  
0.653  
0.696  
0.739  
0.146  
0.180  
0.214  
0.248  
0.283  
0.317  
0.351  
0.385  
0.420  
0.454  
0.488  
0.522  
0.557  
0.591  
0.121  
0.150  
0.178  
0.207  
0.236  
0.264  
0.293  
0.321  
0.350  
0.378  
0.407  
0.435  
0.464  
0.492  
3.000* 1.500* 1.000* 0.750* 0.600* 0.500* 0.429* 0.375* 0.333* 0.300*  
3.126 1.563 1.042 0.782 0.625 0.521 0.447 0.391 0.347 0.313  
*Peak input voltage for guaranteed performance at a given gain setting.  
15  
Specifications ispPAC10  
Software-Based Design Environment  
Design Entry Software  
in the schematic window can be accessed via mouse  
operations as well as menu commands. When com-  
pleted, configurations can be saved, simulated, and  
downloaded to devices.  
Designers configure the ispPAC10 and verify its perfor-  
mance using PAC-Designer, an easy to use, Microsoft  
Windows compatible program. Circuit designs are en-  
tered graphically and then verified, all within the  
PAC-Designer environment. Full device programming is  
supported using PC parallel port I/O operations and a  
download cable connected to the serial programming  
interface of the ispPAC10. A library of configurations is  
included with basic solutions and examples of advanced  
circuit techniques. In addition, comprehensive on-line  
and printed documentation is provided that covers all  
aspects of PAC-Designer operation.  
PAC-Designer operation can be automated and ex-  
®
tendedbyusingcustom-designedVisualBasic programs  
that set the interconnections and the parameters of  
ispPACproducts.Thesestand-aloneprogramsarecalled  
circuit generator macros. An example of such a macro is  
the biquad filter generator supplied with PAC-Designer.  
With this macro, filter parameters such as gain, Q and  
corner frequency are input directly and then automati-  
cally converted to a schematic configuration. The  
application example shown in Figure 7b was generated  
usingthebiquadfiltergeneratormacro. Moreinformation  
on this and other topics is included in the on-line docu-  
mentation as well as ispPAC application notes.  
The PAC-Designer schematic window, shown in Figure  
12, provides access to all configurable ispPAC10 ele-  
ments via its graphical user interface. All analog input  
and output pins are represented. Static or non-config-  
urable pins such as power, ground, VREF  
, and the  
OUT  
serial digital interface are omitted for clarity. Any element  
Figure 12. Initial PAC-Designer Schematic Design Entry Screen  
PAC Designer - [Design1]  
File  
Edit  
View Tools Options Window Help  
OUT1  
OUT3  
1.07 pF  
1.07 pF  
1
1
PAC Block 1  
PAC Block 3  
IA1  
IA5  
OA1  
2.5V  
OA3  
2.5V  
IA2  
1
IA6  
1
IN1  
IN2  
IN3  
1.07 pF  
1.07 pF  
1
1
PAC Block 2  
PAC Block 4  
IN4  
IA7  
IA3  
OA4  
2.5V  
OA2  
2.5V  
IA8  
1
IA4  
1
OUT4  
OUT2  
UES = 00000000  
Ready  
16  
Specifications ispPAC10  
Software-Based Design Environment (Continued)  
that intersects the curves on the plot, and reads out the  
gain and frequency in the lower right hand corner of the  
plot window when activated.  
Design Simulation Capability  
A powerful feature of PAC-Designer is its simulation  
capability enabling quick and accurate verification of  
circuit operation and performance. Once a circuit is  
configured via the interactive design process, gain and  
phase response between any input and output can then  
be determined. This function is part of the simulator  
capability which derives a transfer equation between the  
two points and then sweeps it over the user-specified  
frequency range. Figure 13 shows a typical screen plot of  
the gain/phase simulator. In it are the input to output  
response curves of a 2nd order biquad filter similar to the  
implementation illustrated in Figure 7b. In this example,  
the lowpass and bandpass characteristics of the filter are  
seen.  
In-System Programming  
The ispPAC10 is an in-system programmable device.  
This is accomplished by integrating all high voltage  
programmingcircuitryon-chip.Programmingisperformed  
through a 5-wire, IEEE 1149.1 (JTAG) compliant serial  
port interface at normal logic levels. Once a device is  
programmed,allconfigurationinformationisstoredinon-  
2
chip, non-volatile E CMOS memory cells. The specifics  
of the IEEE 1149.1 serial interface are described in the  
interface section of this data sheet.  
User Electronic Signature  
The simulator is capable of displaying up to four separate  
input to output responses. This allows multiple signal  
paths to be viewed as well as intermediate results of  
component changes so performance comparisons can  
bemade. Thereisalsoauserpositionedcrosshaircursor  
A user electronic signature (UES) feature is included in  
theE memoryoftheispPAC10. Itcontains8bitsthatcan  
be configured by the user to store unique data such as ID  
codes, revision numbers or inventory control data.  
2
Figure 13. PAC-Designer Simulation Plot Screen (Biquad Filter Configuration)  
PAC Designer - [Design1:2]  
File  
Edit  
View Curve Tools Options Window Help  
Gain Plot (dB)  
1.8  
Vo1/Vi1  
Vo2/Vi1  
-10  
-20  
-30  
-40  
-50  
100  
1K  
10K  
100K  
1M  
10M  
Phase Plot (Deg)  
Vo1/Vi1  
Vo2/Vi1  
150  
100  
50  
0
-50  
-100  
100  
1K  
10K  
100K  
1M  
10M  
Ready  
Curve:1 Vout1/Vin1  
17  
Specifications ispPAC10  
In-System Programmability  
Electronic Security  
ispPAC10 and can be used in real time to check circuit  
operation as part of the design process. Input and output  
connections as well as a breadboardcircuit area are  
provided to speed debugging of the circuit.  
Anelectronicsecurityfuse(ESF)bitisprovidedinevery  
ispPAC10 device to prevent unauthorized readout of the  
2
E CMOS user bit patterns. Once programmed, this cell  
prevents further access to the functional user bits in the  
device. This cell can only be erased by reprogramming  
the device, so the original configuration can not be  
examined once programmed. Usage of this feature is  
optional.  
Serial Port Programming Interface  
Communication with the ispPAC10 is facilitated via an  
IEEE 1149.1 test access port (TAP). It is used by the  
ispPAC10 as a serial programming interface, and not for  
boundary scan test purposes. There are no boundary  
scan logic cells in the ispPAC10 architecture. This does  
not prevent the ispPAC10 from functioning correctly,  
however, when placed in a valid serial chain with other  
IEEE 1149.1 compliant devices.  
Production Programming Support  
Onceafinalconfigurationisdetermined, anASCIIformat  
JEDEC file is created using the PAC-Designer software.  
Parts can then be ordered through the usual supply  
channels with the users specific configuration already  
preloaded into the parts. By virtue of its standard inter-  
face, compatibility is maintained with existing production  
programmingequipmentgivingcustomersawidedegree  
of freedom and flexibility in production planning.  
A brief description of the ispPAC10 serial interface fol-  
lows. For complete details of the reference specification,  
refer to the publication, Standard Test Access Port and  
Boundary-Scan Architecture, IEEE Standard 1149.1-  
1990(whichnowincludesIEEEStandard1149.1a-1993).  
Evaluation Fixture  
IncludedinthebasicispPAC10DesignKitisanengineer-  
ing prototype board that is connected to the parallel port  
of a PC. It demonstrates proper layout techniques for the  
Figure 14. Configuring the ispPAC10 In-Systemfrom a PC Parallel Port  
PAC-Designer  
Software  
Other  
System  
Circuitry  
ispDownload  
Cable (6')  
4
ispPAC10  
Device  
18  
Specifications ispPAC10  
IEEE Standard 1149.1 Interface  
Overview  
register. All instructions relating to boundary scan opera-  
tionsplacetheispPAC10intheBYPASSmodetomaintain  
compliance with the specification. The optional identifi-  
cation register described in IEEE 1149.1 is also included  
in the ispPAC10. One additional data register included in  
the TAP of the ispPAC10 is the Lattice defined user  
register. Figure15showshowtheinstructionandvarious  
data registers are placed in an ispPAC10.  
An IEEE 1149.1 test access port (TAP) provides the  
control interface for serially accessing the digital I/O of  
the ispPAC10. The TAP controller is a state machine  
driven with mode and clock inputs. Under the correct  
protocol, instructions are shifted into an instruction regis-  
ter which then determines subsequent data input, data  
output, and related operations. Device programming is  
performed by addressing the user register, shifting data  
in, and then executing a program user instruction, after  
TAP Controller Specifics  
2
The TAP is controlled by the Test Clock (TCK) and Test  
Mode Select (TMS) inputs. These inputs determine  
whether an Instruction Register or Data Register opera-  
tion is performed. Driven by the TCK input, the TAP  
consists of a small 16-state controller design. In a given  
state, the controller responds according to the level on  
the TMS input as shown in Figure 16. Test Data In (TDI)  
and TMS are latched on the rising edge of TCK, with Test  
Data Out (TDO) becoming valid on the falling edge of  
TCK. There are six steady states within the controller:  
Test-Logic-Reset, Run-Test/Idle, Shift-Data-Register,  
Pause-Data-Register, Shift-Instruction-Register, and  
Pause-Instruction-Register. But there is only one steady  
state for the condition when TMS is set high: the Test-  
Logic-Reset state. This allows a reset of the test logic  
within five TCKs or less by keeping the TMS input high.  
Return to the Test-Logic-Reset state can also be imme-  
diately accomplished by placing a logic low on the  
Test-Reset (TRST#) pin. Test-Logic-Reset is also the  
power-on default state.  
which the data is transferred to internal E CMOS cells. It  
is these non-volatile cells that determine the configura-  
tion of the ispPAC10. By cycling the TAP controller  
through the necessary states, data can also be shifted  
out of the user register to verify the current ispPAC10  
configuration. Instructions exist to access all data regis-  
ters and perform internal control operations.  
Figure 15. ispPAC10 TAP Registers  
User Register  
ID Register  
Bypass Register  
Instruction Register  
When the correct logic sequence is applied to the TMS  
and TCK inputs, the TAP will exit the Test-Logic-Reset  
state and move to the desired state. The next state after  
Test-Logic-ResetisRun-Test/Idle. Untiladataorinstruc-  
tion scan is performed, no action will occur in Run-Test/  
Idle (steady state = idle). After Run-Test/Idle, either a  
data or instruction scan is performed. The states of the  
DataandInstructionRegisterblocksareidenticaltoeach  
otherdifferingonlyintheirentrypoints. Wheneitherblock  
is entered, the first action is a capture operation. For the  
Data Registers, the Capture-DR state is very simple: it  
captures (parallel loads) data onto the selected serial  
data path (previously chosen with the appropriate in-  
struction). For the Instruction Register, the Capture-IR  
state will always load the IDCODE instruction. This  
condition will occur independently anytime a hardware  
reset (TRST#) is executed and is also the power-on  
default. It will always enable the ID Register for readout  
if no other instruction is loaded prior to a Shift-DR opera-  
Test Access Port  
(TAP) Logic  
Output  
Latch  
TDI TCK  
TMS TRST  
TDO  
For compatibility between compliant devices, two data  
registersaremandatedbytheIEEE1149.1specification.  
Others are functionally specified, but inclusion is strictly  
optional. Finally, there are provisions for optional data  
registers defined by the manufacturer. The two required  
registers are the bypass and boundary-scan registers.  
For ispPAC10, the bypass register is a 1-bit shift register  
that provides a short path through the device when  
boundary testing or other operations are not being per-  
formed. The ispPAC10, as mentioned, has no  
boundary-scan logic and therefore no boundary scan  
19  
Specifications ispPAC10  
IEEE Standard 1149.1 Interface (Continued)  
tion. This, in conjunction with mandated bit codes, allows function of three required and six optional instructions.  
a blindinterrogation of any device in a compliant IEEE Any additional instructions are left exclusively for the  
1149.1 serial chain.  
manufacturertodetermine.Theinstructionwordlengthis  
not mandated other than to be a minimum of 2 bits, with  
only the BYPASS and EXTEST instruction code patterns  
being specifically called out (all ones and all zeroes  
respectively). The ispPAC10 contains the required mini-  
mum instruction set as well as one from the optional  
instruction set. In addition, there are several proprietary  
instructions that allow the device to be configured and  
verified. For ispPAC10, the instruction word length is 5  
bits. All ispPAC10 instructions available to users are  
shown in Table 2.  
From the Capture state, the TAP transitions to either the  
Shift or Exit1 state. Normally the Shift state follows the  
Capture state so that test data or status information can  
be shifted out or new data shifted in. Following the Shift  
state, the TAP either returns to the Run-Test/Idle state  
via the Exit1 and Update states or enters the Pause state  
viaExit1. ThePausestateisusedtotemporarilysuspend  
the shifting of data through either the Data or Instruction  
Register while an external operation is performed. From  
the Pause state, shifting can resume by reentering the  
Shift state via the Exit2 state or be terminated by entering BYPASS is one of the three required instructions. It  
the Run-Test/Idle state via the Exit2 and Update states. selects the Bypass Register to be connected between  
If the proper instruction is shifted in during a Shift-IR TDI and TDO and allows serial data to be transferred  
operation, the next entry into Run-Test/Idle initiates the through the device without affecting the operation of the  
test mode (steady state = test). This is when the device ispPAC10. The bit code of this instruction is defined to be  
is actually programmed, erased or verified. All other all ones by the IEEE 1149.1 standard.  
instructions are executed in the Update state.  
Therequired SAMPLE/PRELOAD instructiondictatesthe  
Boundary-Scan Register be connected between TDI and  
TDO. The ispPAC10 has no boundary-scan register, so  
for compatibility it defaults to the BYPASS mode when-  
ever this instruction is received. The bit code for this  
instruction is defined by Lattice as shown in Table 2.  
Test Instructions  
Like data registers, the IEEE 1149.1 standard also man-  
dates the inclusion of certain instructions. It outlines the  
Figure 16. Test Access Port (TAP) Contoller State Diagram  
Test-Logic-Rst  
1
0
0
1
1
1
Run-Test/Idle  
Select-DR-Scan  
Select-IR-Scan  
0
0
1
1
Capture-DR  
Capture-IR  
0
Shift-DR  
1
0
Shift-IR  
1
0
0
1
1
Exit1-DR  
0
Exit1-IR  
0
Pause-DR  
1
0
Pause-IR  
1
0
0
0
Exit2-DR  
Exit2-IR  
1
1
Update-DR  
Update-IR  
1
0
1
0
Note: The value shown adjacent to each state transition in this figure  
represents the signal present at TMS at the time of a rising edge at TCK.  
20  
Specifications ispPAC10  
IEEE Standard 1149.1 Interface (Continued)  
The EXTEST (external test) instruction is required and ADDUSR (address user register) instruction is a Lattice  
would normally place the device into an external bound- defined instruction that selects the user register to be  
ary test mode while also enabling the Boundary-Scan shifted during a Shift-DR operation. Normal operation of  
Register to be connected between TDI and TDO. Again, a device is not interrupted by this instruction. It precedes  
since the ispPAC10 has no boundary-scan logic, the a PROGUSR (program user) instruction to shift in a new  
deviceisputintheBYPASSmodetoensurespecification configuration and follows a VERUSR (verify user) in-  
compatibility. The bit code of this instruction is defined by struction to shift out the current configuration. The bit  
the 1149.1 standard to be all zeros.  
code for this instruction is shown in Table 2.  
The PRGUSR (program user) is a Lattice instruction that  
Table 2. ispPAC10 TAP Instructions  
enables the data shifted into the user register to be  
2
programmed into the non-volatile E CMOS memory of  
Instruction Code  
Description  
the ispPAC10 and thereby alter its configuration. The  
user register is a 109-bit shift register that contains all the  
user-controlled parametric and interconnect data per-  
taining to the configuration of the ispPAC10. Normal  
operation of the device is interrupted during the actual  
programming time. A programming operation does not  
begin until entry of the Run-Test/Idle state. The time  
requiredtoinsuredataretentionisgivenintheTAPsignal  
specifications table. The user must ensure that the rec-  
ommended programming times are observed. The bit  
code for this instruction is shown in Table 2.  
EXTEST  
ADDUSR  
UBE  
00000 External test. Default to BYPASS.  
00001 Address User data register.  
00010 User bulk erase.  
VERUSR  
PRGUSR  
00011 Verify User data register.  
00100 Program User data register.  
IDCODE  
ENCAL  
01101 Read Identification data register.  
10000 Enable Calibration sequence.  
SAMPLE  
BYPASS  
11110 Sample/Preload. Default to BYPASS.  
11111 Bypass (connect TDI to TDO).  
VERUSR (verify user) is the next Lattice instruction and  
causes the current configuration of the ispPAC10 to be  
loaded into the user register. This operation doesnt  
interrupt operation of the device. The current configura-  
tioncanthenbeshiftedoutoftheuserregisterimmediately  
afteranADDUSRinstructionisexecuted.Thebitcodefor  
this instruction is shown in Table 2.  
The optional IDCODE (identification code) instruction is  
incorporated in the ispPAC10 and leaves it in its func-  
tional mode when executed. It selects the Device  
Identification Register to be connected between TDI and  
TDO. The Identification Register is a 32-bit shift register  
containing information regarding the IC manufacturer,  
device type and version code (see Figure 17). Access to  
the Identification Register is immediately available, via a ENCAL (enable calibration) is a Lattice instruction that  
TAP data scan operation, after power-up of the device, enables the start of an auto-calibration sequence. This  
after a reset using the optional TRST pin, or by issuing a operation causes all outputs of the device to go to 0V until  
Test-Logic-Reset instruction. The bit code for this in- the calibration sequence is completed (see timing speci-  
struction is defined by Lattice as shown in Table 2.  
fications). As with the programming instructions above,  
calibration does not begin until entry of the Run-Test/Idle  
state. The completion of the calibration is not dependent,  
however, on any further TAP control. This means the  
state of the TAP can be returned immediately to the Test-  
Logic-Reset state. The only consideration would be to  
not clock the TAP during critical analog operations. The  
first several milliseconds of the calibration routine are  
consumed waiting for configurations to settle, though,  
leaving more than enough time to clock the TAP back to  
the Test-Logic-Reset state. The bit code for this instruc-  
tion is shown in Table 2.  
The Figure 17. Identification Code (IDCODE)  
32-Bit Binary Word for Lattice ispPAC10  
MSB  
LSB  
XXXX / 0000 0001 0000 0000 / 0000 0100 001 / 1  
Part Number  
(16 bits)  
0100h = PAC10  
JEDEC Manfacturer  
Identity Code for  
Lattice Semiconductor  
(11 bits)  
Version  
(4 bits)  
Constant 1  
(1 bit)  
2
E
Configured  
per 1149.1-1990  
21  
Specifications ispPAC10  
IEEE Standard 1149.1 Interface (Continued)  
The last Lattice instruction is UBE (user bulk erase). The ADDUSR, BYPASS, EXTEST, IDCODE and  
Operation of the device is interrupted during UBE, after SAMPLE/PRELOAD instructions are all executed in the  
which all inputs are disconnected and all outputs driven Update-IR state. Other instructions: PRGUSR, VERUSR  
to VREF  
(2.5V). To economize internal circuitry, and UBE are executed upon entry of the Run-Test/Idle  
OUT  
programming can only be selectively done in one direc- state.  
tion (from zeroes to ones). The UBE is used to return all  
It is recommended that when all serial interface opera-  
user bits to a zero state at the same time. A UBE usually  
proceeds a PRGUSR operation, otherwise one to zero  
changes would not be implemented. It can also be used  
to erase all configuration information from a device and  
is the default condition of parts shipped from the factory.  
The same programming constraints apply to UBE as for  
PRGUSR. The bit code for this instruction is shown in  
Table 2.  
tions are completed, the TAP controller be reset and left  
in the Test-Logic-Reset state (the power-up default) and  
the TCK and TMS inputs idled. This will insure the best  
analogperformancepossiblebyminimizingtheeffectsof  
digital logic feed-through.”  
22  
Specifications ispPAC10  
Package Diagrams  
28-Pin Plastic DIP  
Dimensions in Inches MIN./MAX.  
(Dimensions in millimeters, shown in parenthesis, are for reference only)  
.300 / .325  
(7.61 / 8.25)  
.280 /.300  
(7.11 / 7.61)  
1.360 / 1.39  
(34.54 / 35.31)  
.008 / .012  
(.20 / .31)  
0°-15°  
.020 (.51) MIN  
.180 (4.57) MAX  
.125 / .135  
(3.17 / 3.43)  
.045 /.055  
(1.14 / 1.40)  
.015 /.021  
(.38 / .53)  
.100 (2.54) BSC  
28-Pin Plastic SOIC  
Dimensions in Inches MIN./MAX.  
(Dimensions in millimeters, shown in parenthesis, are for reference only)  
.292 (7.42)  
.299 (7.59)  
.400 (10.16)  
Top View  
.410 (10.41)  
Pin 1  
.0091 (.23)  
.0125 (.32)  
.050 (1.27) BSC  
0°  
.697 (17.70)  
8°  
.024 (.61)  
.040 (1.02)  
.712 (18.08)  
.097 (2.46)  
.104 (2.64)  
.0050 (.127)  
.014 (.35)  
.019 (.48)  
.0115 (.292)  
23  

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