LC4128ZE-7TN144I [LATTICE]
EE PLD, 7.5ns, 128-Cell, CMOS, PQFP144, 20 X 20 MM, LEAD FREE, TQFP-144;
| 型号： | LC4128ZE-7TN144I |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | EE PLD, 7.5ns, 128-Cell, CMOS, PQFP144, 20 X 20 MM, LEAD FREE, TQFP-144 时钟 输入元件 可编程逻辑 |
| 文件： | 总60页 (文件大小：4863K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ispMACH 4000ZE Family
1.8V In-System Programmable
Ultra Low Power PLDs
February 2012
Data Sheet DS1022
Broad Device Offering
• 32 to 256 macrocells
Features
High Performance
• Multiple temperature range support
– Commercial: 0 to 90°C junction (T )
– Industrial: -40 to 105°C junction (T )
• Space-saving ucBGA and csBGA packages*
• f
= 260MHz maximum operating frequency
MAX
j
• t = 4.4ns propagation delay
PD
j
• Up to four global clock pins with programmable
clock polarity control
• Up to 80 PTs per output
Easy System Integration
• Operation with 3.3V, 2.5V, 1.8V or 1.5V
LVCMOS I/O
Ease of Design
• Flexible CPLD macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI
interfaces
• Hot-socketing support
• Open-drain output option
• Programmable output slew rate
• 3.3V PCI compatible
• I/O pins with fast setup path
• Input hysteresis*
• 1.8V core power supply
• IEEE 1149.1 boundary scan testable
• IEEE 1532 ISC compliant
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
Ultra Low Power
• Standby current as low as 10µA typical
• 1.8V core; low dynamic power
• Operational down to 1.6V V
CC
• 1.8V In-System Programmable (ISP™) using
Boundary Scan Test Access Port (TAP)
• Pb-free package options (only)
• On-chip user oscillator and timer*
• Superior solution for power sensitive consumer
applications
• Per pin pull-up, pull-down or bus keeper
control*
• Power Guard with multiple enable signals*
*New enhanced features over original ispMACH 4000Z
Table 1. ispMACH 4000ZE Family Selection Guide
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
Macrocells
PD (ns)
32
4.4
64
4.7
128
5.8
256
5.8
t
tS (ns)
2.2
2.5
2.9
2.9
tCO (ns)
3.0
3.2
3.8
3.8
f
MAX (MHz)
260
1.8V
241
1.8V
200
1.8V
200
1.8V
Supply Voltages (V)
Packages1 (I/O + Dedicated Inputs)
48-Pin TQFP (7 x 7mm)
64-Ball csBGA (5 x 5mm)
64-Ball ucBGA (4 x 4mm)
100-Pin TQFP (14 x 14mm)
132-Ball ucBGA (6 x 6mm)
144-Pin TQFP (20 x 20mm)
144-Ball csBGA (7 x 7mm)
1. Pb-free only.
32+4
32+4
32+4
48+4
48+4
64+10
64+10
96+4
96+4
96+4
64+10
96+14
108+4
64+10
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1022_01.7
ispMACH 4000ZE Family Data Sheet
Introduction
The high performance ispMACH 4000ZE family from Lattice offers an ultra low power CPLD solution. The new fam-
ily is based on Lattice’s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation,
the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power
in a flexible CPLD family. For example, the family’s new Power Guard feature minimizes dynamic power consump-
tion by preventing internal logic toggling due to unnecessary I/O pin activity.
The ispMACH 4000ZE combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000ZE family offers densities ranging from 32 to 256 macrocells. There are multiple density-I/O
combinations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA), and Ultra Chip Scale BGA (ucBGA) pack-
ages ranging from 32 to 144 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key
parameters.
A user programmable internal oscillator and a timer are included in the device for tasks like LED control, keyboard
scanner and similar housekeeping type state machines. This feature can be optionally disabled to save power.
The ispMACH 4000ZE family has enhanced system integration capabilities. It supports a 1.8V supply voltage and
3.3V, 2.5V, 1.8V and 1.5V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank
is configured for 3.3V operation, making this family 5V tolerant. The ispMACH 4000ZE also offers enhanced I/O
features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors,
open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin”
basis. The ispMACH 4000ZE family members are 1.8V in-system programmable through the IEEE Standard 1532
interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test
equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to V (logic core).
CC
Overview
The ispMACH 4000ZE devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) intercon-
nected by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs),
which contain multiple I/O cells. This architecture is shown in Figure 1.
Figure 1. Functional Block Diagram
OSC
I/O
Block
I/O
Block
16
36
16
36
Generic
Logic
Block
Generic
Logic
Block
ORP
ORP
16
16
I/O
Block
I/O
Block
16
36
16
36
Generic
Logic
Block
Generic
Logic
Block
ORP 16
16
ORP
2
ispMACH 4000ZE Family Data Sheet
The I/Os in the ispMACH 4000ZE are split into two banks. Each bank has a separate I/O power supply. Inputs can
support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-
patible with the power supply provided to the bank. Support for a variety of standards helps designers implement
designs in mixed voltage environments. In addition, 5V tolerant inputs are specified within an I/O bank that is con-
nected to a V
of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.
CCO
Architecture
There are a total of two GLBs in the ispMACH 4032ZE, increasing to 16 GLBs in the ispMACH 4256ZE. Each GLB
has 36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to
be connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they
still must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent
and predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the asso-
ciated I/O cells in the I/O block.
Generic Logic Block
The ispMACH 4000ZE GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock
generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-
pled from macrocells through the ORP. Figure 2 illustrates the GLB.
Figure 2. Generic Logic Block
To GRP
Clock
Generator
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
36 Inputs
from GRP
To Product Term
Output Enable Sharing.
Also, To Input Enable of
Power Guard on I/Os
in the block.
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
3
ispMACH 4000ZE Family Data Sheet
Figure 3. AND Array
In[0]
In[34]
In[35]
PT0
PT1
PT2
PT3
PT4
Cluster 0
PT75
PT76
PT77
PT78
PT79
Cluster 15
PT80 Shared PT Clock
PT81 Shared PT Initialization
PT82 Shared PTOE/BIE
Note:
Indicates programmable fuse.
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000ZE family is 4+1 (total 5) product
terms. The software automatically considers the availability and distribution of product term clusters as it fits the
functions within a GLB. The logic allocator is designed to provide two speed paths: 20-PT Speed Locking path and
an up to 80-PT path. The availability of these two paths lets designers trade timing variability for increased perfor-
mance.
The enhanced Logic Allocator of the ispMACH 4000ZE family consists of the following blocks:
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
to to
from from
n-1 n-2
n-1 n-4
From
n-4
1-80
PTs
5-PT
n
To XOR (MC)
Cluster
to
n+1
from
n+2
from
n+1
To n+4
Individual Product
Term Allocator
Cluster
Allocator
SuperWIDE™
Steering Logic
4
ispMACH 4000ZE Family Data Sheet
Product Term Allocator
The product term allocator assigns product terms from a cluster to either logic or control applications as required
by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-
ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated
with the cluster. Table 2 shows the available functions for each of the five product terms in the cluster.
Table 2. Individual PT Steering
Product Term
PTn
Logic
Control
Logic PT
Logic PT
Logic PT
Logic PT
Logic PT
Single PT for XOR/OR
PTn+1
Individual Clock (PT Clock)
PTn+2
Individual Initialization or Individual Clock Enable (PT Initialization/CE)
Individual Initialization (PT Initialization)
PTn+3
PTn+4
Individual OE (PTOE)
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions
with more product terms. Table 3 shows which clusters can be steered to which macrocells. Used in this manner,
the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator
accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.
Table 3. Available Clusters for Each Macrocell
Macrocell
M0
Available Clusters
—
C0
C0
C1
C1
C2
C2
C3
M1
M2
C1
C2
C3
C4
M3
C2
C3
C4
C5
M4
C3
C4
C5
C6
M5
C4
C5
C6
C7
M6
C5
C6
C7
C8
M7
C6
C7
C8
C9
M8
C7
C8
C9
C10
C11
C12
C13
C14
C15
—
M9
C8
C9
C10
C11
C12
C13
C14
C15
—
M10
M11
M12
M13
M14
M15
C9
C10
C11
C12
C13
C14
C15
C10
C11
C12
C13
C14
—
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-
tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions
and allowing performance to be increased through a single GLB implementation. Table 4 shows the product term
chains.
5
ispMACH 4000ZE Family Data Sheet
Table 4. Product Term Expansion Capability
Expansion
Chains
Macrocells Associated with Expansion Chain
(with Wrap Around)
Max PT/
Macrocell
Chain-0
Chain-1
Chain-2
Chain-3
M0 Õ M4 Õ M8 Õ M12 Õ M0
M1 Õ M5 Õ M9 Õ M13 Õ M1
M2 Õ M6 Õ M10 Õ M14 Õ M2
M3 Õ M7 Õ M11 Õ M15 Õ M3
75
80
75
70
Every time the super cluster allocator is used, there is an incremental delay of t
. When the super cluster alloca-
EXP
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.
Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input
from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable
delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Power-up
Initialization
Shared PT Initialization
PT Initialization (optional)
PT Initialization/CE (optional)
Delay
From I/O Cell
R
P
From Logic Allocator
To ORP
To GRP
D/T/L
Q
CE
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Single PT
PT Clock (optional)
Shared PT Clock
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
• Block CLK0
• Block CLK1
6
ispMACH 4000ZE Family Data Sheet
• Block CLK2
• Block CLK3
• PT Clock
• PT Clock Inverted
• Shared PT Clock
• Ground
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
• PT Initialization/CE
• PT Initialization/CE Inverted
• Shared PT Clock
• Logic High
Initialization Control
The ispMACH 4000ZE family architecture accommodates both block-level and macrocell-level set and reset capa-
bility. There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macro-
cell level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset
functionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, pro-
viding flexibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a
known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a
signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the V rise must be monotonic, and the clock must be inactive until the reset
CC
delay time has elapsed.
GLB Clock Generator
Each ispMACH 4000ZE device has up to four clock pins that are also routed to the GRP to be used as inputs.
These pins drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock sig-
nals that can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations
of the true and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
CLK0
Block CLK0
CLK1
Block CLK1
CLK2
Block CLK2
CLK3
Block CLK3
7
ispMACH 4000ZE Family Data Sheet
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. The enhanced ORP of
the ispMACH 4000ZE family consists of the following elements:
• Output Routing Multiplexers
• OE Routing Multiplexers
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
OE Routing Multiplexer
From PTOE
To I/O
Cell
OE
Output Routing Multiplexer
From Macrocell
To I/O
Cell
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 5-7 provide the connection details.
Table 5. GLB/MC/ORP Combinations for ispMACH 4256ZE
GLB/MC
ORP Mux Input Macrocells
[GLB] [MC 0]
[GLB] [MC 1]
[GLB] [MC 2]
[GLB] [MC 3]
[GLB] [MC 4]
[GLB] [MC 5]
[GLB] [MC 6]
[GLB] [MC 7]
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
8
ispMACH 4000ZE Family Data Sheet
Table 6. GLB/MC/ORP Combinations for ispMACH 4128ZE
GLB/MC
ORP Mux Input Macrocells
[GLB] [MC 0]
[GLB] [MC 1]
[GLB] [MC 2]
[GLB] [MC 3]
[GLB] [MC 4]
[GLB] [MC 5]
[GLB] [MC 6]
[GLB] [MC 7]
[GLB] [MC 8]
[GLB] [MC 9]
[GLB] [MC 10]
[GLB] [MC 11]
M0, M1, M2, M3, M4, M5, M6, M7
M1, M2, M3, M4, M5, M6, M7, M8
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M5, M6, M7, M8, M9, M10, M11, M12
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M9, M10, M11, M12, M13, M14, M15, M0
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M13, M14, M15, M0, M1, M2, M3, M4
M14, M15, M0, M1, M2, M3, M4, M5
Table 7. GLB/MC/ORP Combinations for ispMACH 4032ZE and 4064ZE
GLB/MC
ORP Mux Input Macrocells
[GLB] [MC 0]
[GLB] [MC 1]
[GLB] [MC 2]
[GLB] [MC 3]
[GLB] [MC 4]
[GLB] [MC 5]
[GLB] [MC 6]
[GLB] [MC 7]
[GLB] [MC 8]
[GLB] [MC 9]
[GLB] [MC 10]
[GLB] [MC 11]
[GLB] [MC 12]
[GLB] [MC 13]
[GLB] [MC 14]
[GLB] [MC 15]
M0, M1, M2, M3, M4, M5, M6, M7
M1, M2, M3, M4, M5, M6, M7, M8
M2, M3, M4, M5, M6, M7, M8, M9
M3, M4, M5, M6, M7, M8, M9, M10
M4, M5, M6, M7, M8, M9, M10, M11
M5, M6, M7, M8, M9, M10, M11, M12
M6, M7, M8, M9, M10, M11, M12, M13
M7, M8, M9, M10, M11, M12, M13, M14
M8, M9, M10, M11, M12, M13, M14, M15
M9, M10, M11, M12, M13, M14, M15, M0
M10, M11, M12, M13, M14, M15, M0, M1
M11, M12, M13, M14, M15, M0, M1, M2
M12, M13, M14, M15, M0, M1, M2, M3
M13, M14, M15, M0, M1, M2, M3, M4
M14, M15, M0, M1, M2, M3, M4, M5
M15, M0, M1, M2, M3, M4, M5, M6
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer, Power Guard
and bus maintenance circuitry. Figure 8 details the I/O cell.
9
ispMACH 4000ZE Family Data Sheet
Figure 8. I/O Cell
GOE 0
GOE 1
GOE 2
GOE 3
I/O Bus Maintenance
From ORP
VCC
VCCO
From ORP
Power Guard
0
1
To Macrocell
To GRP
Power Guard Disable Fuse (PGDF)
Block Input Enable (BIE)
(From Block PT)
Each output supports a variety of output standards dependent on the V
supplied to its I/O bank. Outputs can
CCO
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the V
supplied to its I/O bank. The I/O standards supported are:
CCO
• LVTTL
• LVCMOS 1.8
• LVCMOS 3.3
• LVCMOS 2.5
• LVCMOS 1.5
• 3.3V PCI Compatible
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, pull-up resistor or pull-down
resistor selectable on a “per-pin” basis. A fourth option is to provide none of these. The default in both hardware
and software is such that when the device is erased or if the user does not specify, the input structure is configured
to be a Pull-down Resistor.
Each ispMACH 4000ZE device I/O has an individually programmable output slew rate control bit. Each output can
be individually configured for fast slew or slow slew. The typical edge rate difference between fast and slow slew
setting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer
reflections, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated
lines, the fast slew rate can be used to achieve the highest speed.
The ispMACH 4000ZE family has an always on, 200mV typical hysteresis for each input operational at 3.3V and
2.5V. This provides improved noise immunity for slow transitioning signals.
Power Guard
Power Guard allows easier achievement of standby current in the system. As shown in Figure 9, this feature con-
sists of an enabling multiplexer between an I/O pin and input buffer, and its associated circuitry inside the device.
If the enable signal (E) is held low, all inputs (D) can be optionally isolated (guarded), such that, if any of these were
toggled, it would not cause any toggle on internal pins (Q), thus, a toggling I/O pin will not cause any internal
dynamic power consumption.
10
ispMACH 4000ZE Family Data Sheet
Figure 9. Power Guard
Power Guard
0
1
Q
D
E
All the I/O pins in a block share a common Power Guard Enable signal. For a block of I/Os, this signal is called a
Block Input Enable (BIE) signal. BIE can be internally generated using MC logic, or could come from external
sources using one of the user I/O or input pins.
Any I/O pin in the block can be programmed to ignore the BIE signal. Thus, the feature can be enabled or disabled
on a pin-by-pin basis.
Figure 10 shows Power Guard and BIE across multiple I/Os in a block that has eight I/Os.
Figure 10. Power Guard and BIE in a Block with 8 I/Os
Power Guard
0
To Macrocell
To GRP
1
I/O 0
Power Guard
0
1
I/O 1
To Macrocell
To GRP
Block Input Enable (BIE)
From Block PT. The Block PT
is part of the block AND Array,
and can be driven by signals
from the GRP.
Power Guard
0
1
To Macrocell
To GRP
I/O 7
11
ispMACH 4000ZE Family Data Sheet
The number of BIE inputs, thus the number of Power Guard “Blocks” that can exist in a device, depends on the
device size. Table 8 shows the number of BIE signals available in the ispMACH 4000ZE family. The number of I/Os
available in each block is shown in the Ordering Information section of this data sheet.
Table 8. Number of BIE Signals Available in ispMACH 4000ZE Devices
Number of Logic Blocks, Power
Guard Blocks and BIE Signals
Device
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
Two (Blocks: A and B)
Four (Blocks: A, B, C and D)
Eight (Blocks: A, B, C, …, H)
Sixteen (Blocks: A, B, C, …, P)
Power Guard for Dedicated Inputs
Power Guard can optionally be applied to the dedicated inputs. The dedicated inputs and clocks are controlled by
the BIE of the logic blocks shown in Tables 9 and 10.
Table 9. Dedicated Clock Inputs to BIE Association
CLK/I
32 MC Block
64MC Block
128MC Block
256MC Block
CLK0 / I
CLK1 / I
CLK2 / I
CLK3 / I
A
A
B
B
A
B
C
D
A
D
E
H
A
H
I
P
Table 10. Dedicated Inputs to BIE Association
Dedicated Input
4064ZE Block
4128ZE Block
4256ZE Block
0
1
2
3
4
5
6
7
8
9
A
B
B
C
D
E
G
G
J
B
D
C
F
D
G
H
D
L
—
—
—
—
—
—
—
—
M
O
O
B
For more information on the Power Guard function refer to TN1174, Advanced Features of the ispMACH 4000ZE
Family.
Global OE (GOE) and Block Input Enable (BIE) Generation
Most ispMACH 4000ZE family devices have a 4-bit wide Global OE (GOE) Bus (Figure 11), except the ispMACH
4032 device that has a 2-bit wide Global OE Bus (Figure 12). This bus is derived from a 4-bit internal global OE
(GOE) PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be inverted.
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
12
ispMACH 4000ZE Family Data Sheet
The block-level OE PT of each GLB is also tied to Block Input Enable (BIE) of that block. Hence, for a 256-macro-
cell device (with 16 blocks), each block's BIE signal is driven by block-level OE PT from each block.
Figure 11. Global OE Generation for All Devices Except ispMACH 4032ZE
Internal Global OE
Global OE
PT Bus
(4 lines)
4-Bit
Global OE Bus
Shared PTOE
(Block 0)
BIE0
Shared PTOE
(Block n)
BIEn
Global
Fuses
GOE (0:3)
to I/O cells
Fuse connection
Hard wired
Figure 12. Global OE Generation for ispMACH 4032ZE
Internal Global OE
PT Bus
4-Bit
Global OE Bus
Global OE
(2 lines)
Shared PTOE
(Block 0)
BIE0
BIE1
Shared PTOE
(Block 1)
Global
Fuses
GOE (3:0)
to I/O cells
Fuse connection
Hard wired
On-Chip Oscillator and Timer
An internal oscillator is provided for use in miscellaneous housekeeping functions such as watchdog heartbeats,
digital de-glitch circuits and control state machines. The oscillator is disabled by default to save power. Figure 13
shows the block diagram of the oscillator and timer block.
13
ispMACH 4000ZE Family Data Sheet
Figure 13. On-Chip Oscillator and Timer
OSCOUT
DYNOSCDIS
TIMERRES
OSCTIMER
TIMEROUT
Table 11. On-Chip Oscillator and Timer Signal Names
Input or Out-
put
Optional /
Required
Signal Name
OSCOUT
Description
Output
Output
Input
Optional
Oscillator Output (Nominal Frequency: 5MHz)
TIMEROUT
TIMERRES
DYNOSCDIS
Optional
Optional
Optional
Oscillator Frequency Divided by an integer TIMER_DIV (Default 128)
Reset the Timer
Input
Disables the Oscillator, resets the Timer and saves the power.
OSCTIMER has two outputs, OSCOUT and TIMEROUT. The outputs feed into the Global Routing Pool (GRP).
From GRP, these signals can drive any macrocell input, as well as any output pin (with macrocell bypass). The out-
put OSCOUT is the direct oscillator output with a typical frequency of 5MHz, whereas, the output TIMEROUT is the
oscillator output divided by an attribute TIMER_DIV.
The attribute TIMER_DIV can be: 128 (7 bits), 1024 (10 bits) or 1,048,576 (20 bits). The divided output is provided
for those user situations, where a very slow clock is desired. If even a slower toggling clock is desired, then the pro-
grammable macrocell resources can be used to further divide down the TIMEROUT output.
Figure 14 shows the simplified relationship among OSCOUT, TIMERRES and TIMEROUT. In the diagram, the sig-
nal “R” is an internal reset signal that is used to synchronize TIMERRES to OSCOUT. This adds one extra clock
cycle delay for the first timer transition after TIMERRES.
Figure 14. Relationship Among OSCOUT, TIMERRES and TIMEROUT
n
n
-1
0
1
2
2
/ 2
2
OSCOUT
MPW
TIMERRES
R (Internal)
TIMEROUT
Note: n = Number of bits in the divider (7, 10 or 20)
Metastability: If the signal TIMERRES is not synchronous to OSCOUT, it could make a
difference of one or two clock cycles to the TIMEROUT going high the first time.
14
ispMACH 4000ZE Family Data Sheet
Some Simple Use Scenarios
The following diagrams show a few simple examples that omit optional signals for the OSCTIMER block:
A. An oscillator giving 5MHz nominal clock
B. An oscillator that can be disabled with an external signal (5MHz nominal clock)
C. An oscillator giving approximately 5 Hz nominal clock (TIMER_DIV = 220 (1,048,576))
D. An oscillator giving two output clocks: ~5MHz and ~5KHz (TIMER_DIV= 210 (1,024))
OSCTIME R
TIMER_DIV= N/A
OSCTIME R
TIMER_DIV= N/A
DYNOS CD IS
OSCOUT
OSCOUT
(A) A simple 5MHz oscillator.
(B) An oscillator with dynamic disable.
OSCTIME R
OSCTIME R
OSCOUT
TIMER_DIV= 220
TIMER_DIV= 210
TIMEROUT
TIMEROUT
(C) A simple 5Hz oscillator.
(D) Oscillator with two outputs (5MHz and 5KHz).
OSCTIMER Integration With CPLD Fabric
The OSCTIMER is integrated into the CPLD fabric using the Global Routing Pool (GRP). The macrocell (MC) feed-
back path for two macrocells is augmented with a programmable multiplexer, as shown in Figure 15. The OSC-
TIMER outputs (OSCOUT and TIMEROUT) can optionally drive the GRP lines, whereas the macrocell outputs can
drive the optional OSCTIMER inputs TIMERRES and DYNOSCDIS.
Figure 15. OSCTIMER Integration With CPLD Fabric
A Regular Macrocell
Macrocell
Feedback
Signal
To GRP
To GRP
OSC Macrocell
Macrocell 15
Feedback
Signal
1
0
OSCOUT DYNOSCDIS
TIMER Macrocell
Macrocell 15
Feedback
Signal
1
0
To GRP
TIMEROUT TIMERRES
Table 12 shows how these two MCs are designated in each of the ispMACH4000ZE device.
15
ispMACH 4000ZE Family Data Sheet
Table 12. OSC and TIMER MC Designation
Device
Macrocell
Block Number
MC Number
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
OSC MC
TIMER MC
A
B
15
15
OSC MC
TIMER MC
A
D
15
15
OSC MC
TIMER MC
A
G
15
15
OSC MC
TIMER MC
C
F
15
15
Zero Power/Low Power and Power Management
The ispMACH 4000ZE family is designed with high speed low power design techniques to offer both high speed
and low power. With an advanced E2 low power cell and non sense-amplifier design approach (full CMOS logic
approach), the ispMACH 4000ZE family offers fast pin-to-pin speeds, while simultaneously delivering low standby
power without needing any “turbo bits” or other power management schemes associated with a traditional sense-
amplifier approach.
The zero power ispMACH 4000ZE is based on the 1.8V ispMACH 4000Z family. With innovative circuit design
changes, the ispMACH 4000ZE family is able to achieve the industry’s lowest static power.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 4000ZE devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded
directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices
can be linked into a board-level serial scan path for more board-level testing. The test access port operates with an
LVCMOS interface that corresponds to the power supply voltage.
I/O Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispMACH 4000ZE family of devices
allows this by offering the user the ability to quickly configure the physical nature of the I/O cells. This quick config-
uration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's
ispVM™ System programming software can either perform the quick configuration through the PC parallel port, or
can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inven-
tory levels, higher quality and the ability to make in-field modifications. All ispMACH 4000ZE devices provide In-
System Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE
1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, well-
defined interface. All ispMACH 4000ZE devices are also compliant with the IEEE 1532 standard.
The ispMACH 4000ZE devices can be programmed across the commercial temperature and voltage range. The
PC-based Lattice software facilitates in-system programming of ispMACH 4000ZE devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
16
ispMACH 4000ZE Family Data Sheet
mated test equipment. This equipment can then be used to program ispMACH 4000ZE devices during the testing
of a circuit board.
User Electronic Signature
The User Electronic Signature (UES) allows the designer to include identification bits or serial numbers inside the
device, stored in E2CMOS memory. The ispMACH 4000ZE device contains 32 UES bits that can be configured by
the user to store unique data such as ID codes, revision numbers or inventory control codes.
Security Bit
A programmable security bit is provided on the ispMACH 4000ZE devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a
device programmer, securing proprietary designs from competitors. Programming and verification are also
defeated by the security bit. The bit can only be reset by erasing the entire device.
Hot Socketing
The ispMACH 4000ZE devices are well-suited for applications that require hot socketing capability. Hot socketing a
device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs with-
out being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The isp-
MACH 4000ZE devices provide this capability for input voltages in the range 0V to 3.0V.
Density Migration
The ispMACH 4000ZE family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-
geted for a high density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
17
ispMACH 4000ZE Family Data Sheet
Absolute Maximum Ratings1, 2, 3, 4
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V
CC
Output Supply Voltage (V
) . . . . . . . . . . . . . . . -0.5 to 4.5V
CCO
Input or I/O Tristate Voltage Applied5, 6 . . . . . . . . . -0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C
Junction Temperature (T ) with Power Applied. . .-55 to 150°C
j
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.
2. Compliance with Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Please refer to the Lattice ispMACH 4000V/B/C/ZC/ZE Product Family Qualification Summary for complete data, including
the ESD performance data.
5. Undershoot of -2V and overshoot of (VIH (MAX) + 2V), up to a total pin voltage of 6V is permitted for a duration of <20ns.
6. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
Recommended Operating Conditions
Symbol
Parameter
Min.
1.7
1.61
0
Max.
1.9
Units
V
Standard Voltage Operation
Extended Voltage Operation
VCC
Supply Voltage
1.9
V
Junction Temperature (Commercial)
Junction Temperature (Industrial)
90
°C
°C
Tj
-40
105
1. Devices operating at 1.6V can expect performance degradation up to 35%.
Erase Reprogram Specifications
Parameter
Erase/Reprogram Cycle
Min.
Max.
Units
1,000
—
Cycles
Note: Valid over commercial temperature range.
Hot Socketing Characteristics1,2,3
Symbol
Parameter
Condition
0 VIN 3.0V, Tj = 105°C
0 VIN 3.0V, Tj = 130°C
Min.
—
Typ.
30
Max.
150
Units
µA
IDK
Input or I/O Leakage Current
—
30
200
µA
1. Insensitive to sequence of VCC or VCCO. However, assumes monotonic rise/fall rates for VCC and VCCO, provided (VIN - VCCO) 3.6V.
2. 0 < VCC < VCC (MAX), 0 < VCCO < VCCO (MAX).
3. IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until fuse circuitry is active.
18
ispMACH 4000ZE Family Data Sheet
I/O Recommended Operating Conditions
VCCO (V)1
Max.
3.6
Standard
Min.
3.0
LVTTL
LVCMOS 3.3
Extended LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
PCI 3.3
3.0
3.6
2.7
3.6
2.3
2.7
1.65
1.4
1.95
1.6
3.0
3.6
1. Typical values for VCCO are the average of the min. and max. values.
DC Electrical Characteristics
Over Recommended Operating Conditions
Condition Min.
0 VIN < VCCO
Symbol
Parameter
Typ.
0.5
—
Max.
Units
µA
µA
µA
µA
µA
µA
µA
µA
V
1, 2
IIL, IIH
Input Leakage Current
—
1
1
IIH
Input High Leakage Current
I/O Weak Pull-up Resistor Current
VCCO < VIN 5.5V
0 VIN 0.7VCCO
—
10
IPU
-20
—
-150
IPD
I/O Weak Pull-down Resistor Current VIL (MAX) VIN VIH (MAX)
30
—
150
IBHLS
IBHHS
IBHLO
IBHHO
VBHT
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
VIN = VIL (MAX)
30
—
—
VIN = 0.7 VCCO
-20
—
—
0V VIN VBHT
—
—
150
VBHT VIN VCCO
—
—
—
-150
VCCO * 0.35
—
VCCO * 0.65
VCCO = 3.3V, 2.5V, 1.8V, 1.5V
VCC = 1.8V, VIO = 0 to VIH (MAX)
VCCO = 3.3V, 2.5V, 1.8V, 1.5V
—
—
—
—
—
—
—
—
—
—
—
—
C1
C2
C3
I/O Capacitance3
8
6
6
pf
pf
pf
Clock Capacitance3
Global Input Capacitance3
V
CC = 1.8V, VIO = 0 to VIH (MAX)
VCCO = 3.3V, 2.5V, 1.8V, 1.5V
CC = 1.8V, VIO = 0 to VIH (MAX)
V
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. IIH excursions of up to 1.5µA maximum per pin above the spec limit may be observed for certain voltage conditions on no more than 10% of
the device’s I/O pins.
3. Measured TA = 25°C, f = 1.0MHz.
19
ispMACH 4000ZE Family Data Sheet
Supply Current
To minimize transient current during power-on, configure CPLD I/Os to a pull-up or float state. If this logic scenario
is not possible, then the recommended power sequence should assert VCC and VCCO at the same time or VCC
before VCCO.
Symbol
Parameter
Condition
Min. Typ. Max. Units
ispMACH 4032ZE
Vcc = 1.8V, TA = 25°C
—
—
—
—
—
—
50
58
60
10
13
15
—
—
—
—
25
40
µA
µA
µA
µA
µA
µA
ICC1, 2, 3, 5, 6 Operating Power Supply Current
Vcc = 1.9V, TA = 0 to 70°C
Vcc = 1.9V, TA = -40 to 85°C
Vcc = 1.8V, TA = 25°C
ICC4, 5, 6
Standby Power Supply Current
Vcc = 1.9V, TA = 0 to 70°C
Vcc = 1.9V, TA = -40 to 85°C
ispMACH 4064ZE
Vcc = 1.8V, TA = 25°C
—
—
—
—
—
—
80
89
92
11
15
18
—
—
—
—
30
50
µA
µA
µA
µA
µA
µA
ICC1, 2, 3, 5, 6 Operating Power Supply Current
Vcc = 1.9V, TA = 0 to 70°C
Vcc = 1.9V, TA = -40 to 85°C
Vcc = 1.8V, TA = 25°C
ICC4, 5, 6
Standby Power Supply Current
Vcc = 1.9V, TA = 0 to 70°C
Vcc = 1.9V, TA = -40 to 85°C
ispMACH 4128ZE
Vcc = 1.8V, TA = 25°C
—
—
—
—
—
—
168
190
195
12
—
—
—
—
40
60
µA
µA
µA
µA
µA
µA
ICC1, 2, 3, 5, 6 Operating Power Supply Current
Vcc = 1.9V, TA = 0 to 70°C
Vcc = 1.9V, TA = -40 to 85°C
Vcc = 1.8V, TA = 25°C
ICC4, 5, 6
Standby Power Supply Current
Vcc = 1.9V, TA = 0 to 70°C
Vcc = 1.9V, TA = -40 to 85°C
16
19
ispMACH 4256ZE
Vcc = 1.8V, TA = 25°C
—
—
—
—
—
—
341
361
372
13
—
—
µA
µA
µA
µA
µA
µA
ICC1, 2, 3, 5, 6 Operating Power Supply Current
Vcc = 1.9V, TA = 0 to 70°C
Vcc = 1.9V, TA = -40 to 85°C
Vcc = 1.8V, TA = 25°C
—
—
ICC4, 5, 6
Standby Power Supply Current
Vcc = 1.9V, TA = 0 to 70°C
Vcc = 1.9V, TA = -40 to 85°C
32
65
100
43
1. Frequency = 1.0 MHz.
2. Device configured with 16-bit counters.
3. ICC varies with specific device configuration and operating frequency.
4. VCCO = 3.6V, VIN = 0V or VCCO, bus maintenance turned off. VIN above VCCO will add transient current above the specified standby ICC
.
5. Includes VCCO current without output loading.
6. This operating supply current is with the internal oscillator disabled. Enabling the internal oscillator adds approximately 15µA typical current
plus additional current from any logic it drives.
20
ispMACH 4000ZE Family Data Sheet
I/O DC Electrical Characteristics
Over Recommended Operating Conditions
VIH
Min (V)
VIL
Max (V)
1
1
VOL
VOH
Min (V)
IOL
IOH
Standard
LVTTL
Min (V)
Max (V) Max (V)
(mA) (mA)
0.40
VCCO - 0.40
8.0
0.1
8.0
0.1
8.0
0.1
2.0
0.1
2.0
0.1
1.5
-4.0
-0.1
-4.0
-0.1
-4.0
-0.1
-2.0
-0.1
-2.0
-0.1
-0.5
-0.3
0.80
0.80
2.0
2.0
5.5
0.20
V
V
V
V
V
CCO - 0.20
CCO - 0.40
CCO - 0.20
CCO - 0.40
CCO - 0.20
0.40
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
-0.3
-0.3
-0.3
5.5
0.20
0.40
0.70
1.70
3.6
0.20
0.40
VCCO - 0.45
CCO - 0.20
VCCO - 0.45
CCO - 0.20
0.9 VCCO
0.35 * VCC
0.35 * VCC
0.65 * VCC
0.65 * VCC
3.6
0.20
V
0.40
LVCMOS 1.52
PCI 3.3
-0.3
-0.3
3.6
0.20
V
0.3 * 3.3 * (VCC / 1.8) 0.5 * 3.3 * (VCC / 1.8)
5.5
0.1 VCCO
1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.
2. For 1.5V inputs, there may be an additional DC current drawn from VCC, if the ispMACH 4000ZE VCC and the VCC of the driving device
(VCCd-d; that determines steady state VIH) are in the extreme range of their specifications. Typically, DC current drawn from VCC will be
2µA per input.
1.8V VCCO
60
50
IOL
IOH
40
30
20
10
0
0
0.5
1.0
1.5
2.0
VO Output Voltage (V)
21
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE External Switching Characteristics
Over Recommended Operating Conditions
LC4032ZE
-4
LC4064ZE
-4
All Devices
-5
-7
Parameter
Description1, 2
Min. Max. Min. Max. Min. Max. Min. Max. Units
tPD
tS
20-PT combinatorial propagation delay
GLB register setup time before clock
—
4.4
—
—
4.7
—
—
5.8
—
—
7.5
—
ns
ns
2.2
2.5
2.9
4.5
GLB register setup time before clock with
T-type register
tST
2.4
1.0
—
—
2.7
1.1
—
—
3.1
1.3
—
—
4.7
1.4
—
—
ns
ns
GLB register setup time before clock, input
register path
tSIR
GLB register setup time before clock with zero
hold
tSIRZ
tH
2.0
0.0
0.0
—
—
—
2.1
0.0
0.0
—
—
—
2.9
0.0
0.0
—
—
—
4.0
0.0
0.0
—
—
—
ns
ns
ns
GLB register hold time after clock
GLB register hold time after clock with T-type
register
tHT
GLB register hold time after clock, input
register path
tHIR
1.0
0.0
—
—
1.0
0.0
—
—
1.3
0.0
—
—
1.3
0.0
—
—
ns
ns
GLB register hold time after clock, input
register path with zero hold
tHIRZ
tCO
tR
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
—
—
3.0
5.0
—
—
—
3.2
6.0
—
—
—
3.8
7.5
—
—
—
4.5
9.0
—
ns
ns
ns
tRW
1.5
1.7
2.0
4.0
Input to output local product term output
enable/disable
tPTOE/DIS
—
—
7.0
6.5
—
—
8.0
7.0
—
—
8.2
—
—
9.0
ns
ns
Input to output global product term output
enable/disable
tGPTOE/DIS
10.0
10.5
tGOE/DIS
tCW
Global OE input to output enable/disable
Global clock width, high or low
—
4.5
—
—
4.5
—
—
5.5
—
—
7.0
—
ns
ns
1.0
1.5
1.8
2.8
Global gate width low (for low transparent) or
high (for high transparent)
tGW
1.0
—
1.5
—
1.8
—
2.8
—
ns
tWIR
Input register clock width, high or low
1.0
—
—
1.5
—
—
1.8
—
—
2.8
—
—
ns
f
MAX (Int.)3 Clock frequency with internal feedback
260
241
200
172
MHz
clock frequency with external feedback,
[1 / (tS + tCO)]
fMAX (Ext.)
—
192
—
175
—
149
—
111
MHz
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching GRP loading of 1 and 1 output switching.
3. Standard 16-bit counter using GRP feedback.
Timing v.0.8
22
ispMACH 4000ZE Family Data Sheet
Timing Model
The task of determining the timing through the ispMACH 4000ZE family, like any CPLD, is relatively simple. The
timing model provided in Figure 16 shows the specific delay paths. Once the implementation of a given function is
determined either conceptually or from the software report file, the delay path of the function can easily be deter-
mined from the timing model. The Lattice design tools report the timing delays based on the same timing model for
a particular design. Note that the internal timing parameters are given for reference only, and are not tested. The
external timing parameters are tested and guaranteed for every device. For more information on the timing model
and usage, refer to TN1168, ispMACH 4000ZE Timing Model Design and Usage Guidelines.
Figure 16. ispMACH 4000ZE Timing Model
Oscillator/ Timer
Delays
tOSCDIS
tOSCEN
tOSCOD
Feedback
From
Feedback
Routing/GLB Delays
Feedback
Out
tPDi
tFBK
tROUTE
tBLA
tMCELL
tEXP
tIN
tIOI
tPGRT
tBUF
tIOO
tEN
DATA
Q
IN
tORP
tINREG
tINDIO
tDIS
tGCLK_IN
In/Out
Delays
SCLK
tIOI
tPGRT
tPTCLK
tBCLK
C.E.
S/R
tPTSR
tBSR
tBIE
Register/Latch
Delays
MC Reg.
tGPTOE
tPTOE
Control
Delays
tGOE
OE
tIOI
tPGRT
In/Out
Delays
Note: Italicized items are optional delay adders.
23
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters
Over Recommended Operating Conditions
LC4032ZE
-4
LC4064ZE
-4
Parameter
In/Out Delays
tIN
Description
Min.
Max.
Min.
Max.
Units
Input Buffer Delay
—
—
—
—
—
—
—
—
—
0.85
1.60
2.25
0.75
2.25
1.35
3.30
0.00
5.00
—
—
—
—
—
—
—
—
—
0.90
1.60
2.25
0.90
2.25
1.35
3.55
0.00
5.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
tGCLK_IN
tGOE
Global Clock Input Buffer Delay
Global OE Pin Delay
tBUF
Delay through Output Buffer
Output Enable Time
tEN
tDIS
Output Disable Time
tPGSU
Input Power Guard Setup Time
Input Power Guard Hold Time
Input Power Guard BIE Minimum Pulse Width
tPGH
tPGPW
Input Power Guard Recovery Time Following BIE
Dissertation
tPGRT
—
5.00
—
5.00
ns
Routing Delays
tROUTE
tPDi
Delay through GRP
—
—
—
—
—
—
1.60
0.25
0.65
0.90
0.55
0.30
—
—
—
—
—
—
1.70
0.25
0.65
1.00
0.55
0.30
ns
ns
ns
ns
ns
ns
Macrocell Propagation Delay
Macrocell Delay
tMCELL
tINREG
tFBK
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
Output Routing Pool Delay
tORP
Register/Latch Delays
tS
D-Register Setup Time (Global Clock)
0.70
1.25
1.50
0.90
1.45
1.50
0.85
1.45
1.15
0.90
—
—
—
0.85
1.85
1.65
1.05
1.65
1.65
0.80
1.45
1.30
1.10
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tS_PT
tH
D-Register Setup Time (Product Term Clock)
D-Register Hold Time
—
—
tST
T-Register Setup Time (Global Clock)
T-register Setup Time (Product Term Clock)
T-Resister Hold Time
—
—
tST_PT
tHT
—
—
—
—
tSIR
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
—
—
tSIR_PT
tHIR
tHIR_PT
tCOi
—
—
—
—
—
—
0.35
—
0.40
—
tCES
tCEH
tSL
1.00
0.00
0.70
1.45
1.40
—
2.00
0.00
0.95
1.85
1.80
—
Clock Enable Hold Time
—
—
Latch Setup Time (Global Clock)
—
—
tSL_PT
tHL
Latch Setup Time (Product Term Clock)
Latch Hold Time
—
—
—
—
tGOi
Latch Gate to Output/Feedback MUX Time
0.40
0.35
Propagation Delay through Transparent Latch to Output/
Feedback MUX
tPDLi
tSRi
—
—
0.30
0.30
—
—
0.25
0.30
ns
ns
Asynchronous Reset or Set to Output/Feedback MUX
Delay
24
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
LC4032ZE
-4
LC4064ZE
-4
Parameter
tSRR
Description
Min.
Max.
Min.
Max.
Units
Asynchronous Reset or Set Recovery Delay
—
2.00
—
1.70
ns
Control Delays
tBCLK
GLB PT Clock Delay
—
—
—
—
—
—
—
1.20
1.40
1.10
1.20
1.60
2.30
1.80
—
—
—
—
—
—
—
1.30
1.50
1.85
1.90
1.70
3.15
2.15
ns
ns
ns
ns
ns
ns
ns
tPTCLK
Macrocell PT Clock Delay
Block PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Power Guard Block Input Enable Delay
Macrocell PT OE Delay
tBSR
tPTSR
tBIE
tPTOE
tGPTOE
Global PT OE Delay
Internal Oscillator
tOSCSU
tOSCH
Oscillator DYNOSCDIS Setup Time
Oscillator DYNOSCDIS Hold Time
Oscillator OSCOUT Enable Time (To Stable)
Oscillator Output Delay
5.00
5.00
—
—
—
5.00
5.00
—
—
—
ns
ns
tOSCEN
tOSCOD
tOSCNOM
tOSCvar
5.00
4.00
5.00
30
5.00
4.00
5.00
30
ns
—
—
ns
Oscillator OSCOUT Nominal Frequency
Oscillator Variation of Nominal Frequency
MHz
%
—
—
—
—
Oscillator TIMEROUT Clock (Negative Edge) to Out
(20-Bit Divider)
tTMRCO20
tTMRCO10
12.50
7.50
12.50
7.50
ns
ns
Oscillator TIMEROUT Clock (Negative Edge) to Out
(10-Bit Divider)
—
—
Oscillator TIMEROUT Clock (Negative Edge) to Out
(7-Bit Divider)
tTMRCO7
tTMRRSTO
tTMRRR
—
—
6.00
5.00
4.00
—
—
—
6.00
5.00
4.00
—
ns
ns
ns
ns
Oscillator TIMEROUT Reset to Out (Going Low)
Oscillator TIMEROUT Asynchronous Reset Recovery
Delay
—
—
tTMRRSTPW
Oscillator TIMEROUT Reset Minimum Pulse Width
3.00
3.00
Optional Delay Adjusters
Base Parameter
tINREG
tINDIO
tEXP
tBLA
Input Register Delay
—
—
—
1.00
0.40
0.04
—
—
—
1.00
0.40
0.05
ns
ns
ns
Product Term Expander Delay
Additional Block Loading Adders
tMCELL
tROUTE
t
IOI Input Buffer Delays
Using LVTTL Standard with
Hysteresis
tIN, tGCLK_IN, tGOE
LVTTL_in
—
0.60
—
0.60
ns
LVCMOS15_in
LVCMOS18_in
Using LVCMOS 1.5 Standard
Using LVCMOS 1.8 Standard
tIN, tGCLK_IN, tGOE
tIN, tGCLK_IN, tGOE
—
—
0.20
0.00
—
—
0.20
0.00
ns
ns
Using LVCMOS 2.5 Standard with tIN, tGCLK_IN, tGOE
Hysteresis
LVCMOS25_in
LVCMOS33_in
PCI_in
—
—
—
0.80
0.80
0.80
—
—
—
0.80
0.80
0.80
ns
ns
ns
Using LVCMOS 3.3 Standard with tIN, tGCLK_IN, tGOE
Hysteresis
Using PCI Compatible Input with
Hysteresis
tIN, tGCLK_IN, tGOE
tIOO Output Buffer Delays
LVTTL_out Output Configured as TTL Buffer
tEN, tDIS, tBUF
—
0.20
—
0.20
ns
25
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
LC4032ZE
-4
LC4064ZE
-4
Parameter
Description
Min.
—
Max.
0.20
0.00
0.10
0.20
Min.
Max.
0.20
0.00
0.10
0.20
Units
ns
LVCMOS15_out Output Configured as 1.5V Buffer
LVCMOS18_out Output Configured as 1.8V Buffer
LVCMOS25_out Output Configured as 2.5V Buffer
LVCMOS33_out Output Configured as 3.3V Buffer
tEN, tDIS, tBUF
—
—
—
—
t
t
t
EN, tDIS, tBUF
EN, tDIS, tBUF
EN, tDIS, tBUF
—
ns
—
ns
—
ns
Output Configured as PCI Compati- tEN, tDIS, tBUF
ble Buffer
PCI_out
—
—
0.20
1.00
—
—
0.20
1.00
ns
ns
Output Configured for Slow Slew
Rate
tEN, tBUF
Slow Slew
Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for further details.
Timing v.0.8
26
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
All Devices
Max. Min.
-5
-7
Parameter
In/Out Delays
tIN
Description
Min.
Max.
Units
Input Buffer Delay
—
—
—
—
—
—
—
—
—
1.05
1.95
3.00
1.10
2.50
2.50
4.30
0.00
6.00
—
—
—
—
—
—
—
—
—
1.90
2.15
4.30
1.30
2.70
2.70
5.60
0.00
8.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
tGCLK_IN
tGOE
Global Clock Input Buffer Delay
Global OE Pin Delay
tBUF
Delay through Output Buffer
Output Enable Time
tEN
tDIS
Output Disable Time
tPGSU
Input Power Guard Setup Time
Input Power Guard Hold Time
Input Power Guard BIE Minimum Pulse Width
tPGH
tPGPW
Input Power Guard Recovery Time Following BIE Dis-
sertation
tPGRT
—
5.00
—
7.00
ns
Routing Delays
tROUTE
tPDi
Delay through GRP
—
—
—
—
—
—
2.25
0.45
0.65
1.00
0.75
0.30
—
—
—
—
—
—
2.50
0.50
1.00
1.00
0.30
0.30
ns
ns
ns
ns
ns
ns
Macrocell Propagation Delay
Macrocell Delay
tMCELL
tINREG
tFBK
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
Output Routing Pool Delay
tORP
Register/Latch Delays
tS
D-Register Setup Time (Global Clock)
0.90
2.00
2.00
1.10
2.20
2.00
1.20
1.45
1.40
1.10
—
—
—
1.25
2.35
3.25
1.45
2.65
3.25
0.65
1.45
2.05
1.20
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tS_PT
tH
D-Register Setup Time (Product Term Clock)
D-Register Hold Time
—
—
tST
T-Register Setup Time (Global Clock)
T-register Setup Time (Product Term Clock)
T-Resister Hold Time
—
—
tST_PT
tHT
—
—
—
—
tSIR
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
—
—
tSIR_PT
tHIR
tHIR_PT
tCOi
—
—
—
—
—
—
0.45
—
0.75
—
tCES
tCEH
tSL
2.00
0.00
0.90
2.00
2.00
—
2.00
0.00
1.55
2.05
1.17
—
Clock Enable Hold Time
—
—
Latch Setup Time (Global Clock)
—
—
tSL_PT
tHL
Latch Setup Time (Product Term Clock)
Latch Hold Time
—
—
—
—
tGOi
Latch Gate to Output/Feedback MUX Time
0.35
0.33
Propagation Delay through Transparent Latch to Output/
Feedback MUX
tPDLi
tSRi
—
—
0.25
0.95
—
—
0.25
0.28
ns
ns
Asynchronous Reset or Set to Output/Feedback MUX
Delay
27
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
All Devices
Max. Min.
-5
-7
Parameter
tSRR
Description
Min.
Max.
Units
Asynchronous Reset or Set Recovery Delay
—
1.80
—
1.67
ns
Control Delays
tBCLK
GLB PT Clock Delay
—
—
—
—
—
—
—
1.45
1.45
1.85
1.85
1.75
2.40
4.20
—
—
—
—
—
—
—
0.95
1.15
1.83
2.72
1.95
1.90
3.40
ns
ns
ns
ns
ns
ns
ns
tPTCLK
Macrocell PT Clock Delay
Block PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Power Guard Block Input Enable Delay
Macrocell PT OE Delay
tBSR
tPTSR
tBIE
tPTOE
tGPTOE
Global PT OE Delay
Internal Oscillator
tOSCSU
tOSCH
Oscillator DYNOSCDIS Setup Time
Oscillator DYNOSCDIS Hold Time
Oscillator OSCOUT Enable Time (To Stable)
Oscillator Output Delay
5.00
5.00
—
—
—
5.00
5.00
—
—
—
ns
ns
tOSCEN
tOSCOD
tOSCNOM
tOSCvar
5.00
4.00
5.00
30
5.00
4.00
5.00
30
ns
—
—
ns
Oscillator OSCOUT Nominal Frequency
Oscillator Variation of Nominal Frequency
MHz
%
—
—
—
—
Oscillator TIMEROUT Clock (Negative Edge) to Out
(20-Bit Divider)
tTMRCO20
tTMRCO10
12.50
7.50
14.50
9.50
ns
ns
Oscillator TIMEROUT Clock (Negative Edge) to Out
(10-Bit Divider)
—
—
Oscillator TIMEROUT Clock (Negative Edge) to Out
(7-Bit Divider)
tTMRCO7
tTMRRSTO
tTMRRR
—
—
6.00
5.00
4.00
—
—
—
8.00
7.00
6.00
—
ns
ns
ns
ns
Oscillator TIMEROUT Reset to Out (Going Low)
Oscillator TIMEROUT Asynchronous Reset Recovery
Delay
—
—
tTMRRSTPW
Oscillator TIMEROUT Reset Minimum Pulse Width
3.00
5.00
Optional Delay Adjusters
Base Parameter
tINREG
tINDIO
tEXP
tBLA
Input Register Delay
—
—
—
1.60
0.45
0.05
—
—
—
2.60
0.50
0.05
ns
ns
ns
Product Term Expander Delay
Additional Block Loading Adders
tMCELL
tROUTE
t
IOI Input Buffer Delays
Using LVTTL Standard with
Hysteresis
LVTTL_in
tIN, tGCLK_IN, tGOE
—
0.60
—
0.60
ns
LVCMOS15_in
LVCMOS18_in
Using LVCMOS 1.5 Standard
Using LVCMOS 1.8 Standard
tIN, tGCLK_IN, tGOE
tIN, tGCLK_IN, tGOE
—
—
0.20
0.00
—
—
0.20
0.00
ns
ns
Using LVCMOS 2.5 Standard with
Hysteresis
LVCMOS25_in
LVCMOS33_in
PCI_in
tIN, tGCLK_IN, tGOE
tIN, tGCLK_IN, tGOE
tIN, tGCLK_IN, tGOE
—
—
—
0.80
0.80
0.80
—
—
—
0.80
0.80
0.80
ns
ns
ns
Using LVCMOS 3.3 Standard with
Hysteresis
Using PCI Compatible Input with
Hysteresis
tIOO Output Buffer Delays
LVTTL_out Output Configured as TTL Buffer
tEN, tDIS, tBUF
—
0.20
—
0.20
ns
28
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
All Devices
Max. Min.
-5
-7
Parameter
Description
Min.
—
Max.
0.20
0.00
0.10
0.20
Units
ns
LVCMOS15_out Output Configured as 1.5V Buffer
LVCMOS18_out Output Configured as 1.8V Buffer
LVCMOS25_out Output Configured as 2.5V Buffer
LVCMOS33_out Output Configured as 3.3V Buffer
tEN, tDIS, tBUF
0.20
0.00
0.10
0.20
—
—
—
—
t
t
t
EN, tDIS, tBUF
EN, tDIS, tBUF
EN, tDIS, tBUF
—
ns
—
ns
—
ns
Output Configured as PCI Compati- tEN, tDIS, tBUF
ble Buffer
PCI_out
—
—
0.20
1.00
—
—
0.20
1.00
ns
ns
Output Configured for Slow Slew
Rate
tEN, tBUF
Slow Slew
Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for further details.
Timing v.0.8
29
ispMACH 4000ZE Family Data Sheet
Boundary Scan Waveforms and Timing Specifications
Symbol
tBTCP
tBTCH
tBTCL
tBTSU
tBTH
Parameter
Min.
40
20
20
8
Max.
—
Units
ns
TCK [BSCAN test] clock cycle
TCK [BSCAN test] pulse width high
—
ns
TCK [BSCAN test] pulse width low
—
ns
TCK [BSCAN test] setup time
—
ns
TCK [BSCAN test] hold time
10
50
—
—
—
8
—
ns
tBRF
TCK [BSCAN test] rise and fall time
—
mV/ns
ns
tBTCO
tBTOZ
tBTVO
tBTCPSU
tBTCPH
tBTUCO
tBTUOZ
tBTUOV
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
10
10
10
—
ns
ns
ns
BSCAN test Capture register hold time
10
—
—
—
—
ns
BSCAN test Update reg, falling edge of clock to valid output
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
25
25
25
ns
ns
ns
30
ispMACH 4000ZE Family Data Sheet
Power Consumption
ispMACH 4000ZE
Typical I
vs. Frequency
CC
70
60
50
40
30
20
10
0
4256ZE
4128ZE
4064ZE
4032ZE
0
50
100
150
200
250
300
Frequency (MHz)
Power Estimation Coefficients1
Device
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
A
B
0.010
0.009
0.009
0.009
0.009
0.011
0.012
0.013
1. For further information about the use of these coefficients, refer to TN1187, Power Esti-
mation in ispMACH 4000ZE Devices.
31
ispMACH 4000ZE Family Data Sheet
Switching Test Conditions
Figure 17 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 13.
Figure 17. Output Test Load, LVTTL and LVCMOS Standards
VCCO
R
1
2
Test
Point
DUT
R
C
L
0213A/ispm4k
Table 13. Test Fixture Required Components
1
Test Condition
R1
R2
CL
Timing Ref.
VCCO
LVCMOS 3.3 = 1.5V
LVCMOS 3.3 = 3.0V
VCCO
LVCMOS 2.5 = 2.3V
LVCMOS 1.8 = 1.65V
LVCMOS 1.5 = 1.4V
LVCMOS 2.5 =
2
LVCMOS I/O, (L -> H, H -> L)
106 106
35pF
VCCO
LVCMOS 1.8 =
2
VCCO
LVCMOS 1.5 =
2
LVCMOS I/O (Z -> H)
106
35pF
35pF
5pF
1.5V
1.5V
3.0V
3.0V
3.0V
3.0V
LVCMOS I/O (Z -> L)
106
LVCMOS I/O (H -> Z)
106
V
OH - 0.3
LVCMOS I/O (L -> Z)
106
5pF
VOL + 0.3
1. CL includes test fixtures and probe capacitance.
32
ispMACH 4000ZE Family Data Sheet
Signal Descriptions
Signal Names
Description
TMS
Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control
the state machine.
TCK
Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the
state machine.
TDI
Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data.
Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out.
TDO
GOE0/IO, GOE1/IO
These pins are configured to be either Global Output Enable Input or as general I/O
pins.
GND
Ground
NC
Not Connected
VCC
The power supply pins for logic core and JTAG port.
These pins are configured to be either CLK input or as an input.
The power supply pins for each I/O bank.
CLK0/I, CLK1/I, CLK2/I, CLK3/I
VCCO0, VCCO1
Input/Output1 – These are the general purpose I/O used by the logic array. y is GLB
reference (alpha) and z is macrocell reference (numeric). z: 0-15.
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
y: A-B
y: A-D
y: A-H
y: A-P
yzz
1. In some packages, certain I/Os are only available for use as inputs. See the Logic Signal Connections tables for details.
ORP Reference Table
4032ZE
4064ZE
4128ZE
4256ZE
Number of I/Os
32
2
32
4
48
4
64
4
64
8
96
8
64
16
4
96
16
6
108
16
Number of GLBs
Number of
I/Os per GLB
16
8
Mixture of
9, 10,
16
8
12
Mixture of
6, 7, 8
14, 15
Reference ORP
Table (I/Os per
GLB)
16
8
9, 10,
14, 15
16
8
12
4
6
6, 7, 8
33
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Power Supply and NC Connections1
Signal
48 TQFP2
64 csBGA3, 4
64 ucBGA3, 4
100 TQFP2
25, 40, 75, 90
VCC
12, 36
6
E4, D5
E4, D5
VCCO0
4032ZE: E3
4064ZE: E3, F4
C3, F3
F6, A6
13, 33, 95
VCCO (Bank 0)
VCCO1
30
4032ZE: D6
45, 63, 83
VCCO (Bank 1)
4064ZE: D6, C6
GND
13, 37
5
D4, E5
D4, E5
D4, E5
—
D4, D5
D4, D5
D4, D5
—
1, 26, 51, 76
7, 18, 32, 96
46, 57, 68, 82
—
GND (Bank 0)
GND (Bank 1)
NC
29
—
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
the bank shown.
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
ascending horizontally.
4. All bonded grounds are connected to the following two balls, D4 and E5.
34
ispMACH 4000ZE Family Data Sheet
ispMACH 4000ZE Power Supply and NC Connections1 (Cont.)
Signal
132 ucBGA3
144 csBGA3
144 TQFP2
VCC
M1, M7, A12, B5
H5, H8, E8, E5
36, 57, 108, 129
VCCO0
VCCO (Bank 0)
B1, H4, L2, J5, A4
E4, F4, G4, J5, D5
J8, H9, G9, F9, D8
3, 19, 34, 47, 136
VCCO1
K9, L12, F12, D9, C7
64, 75, 91, 106, 119
VCCO (Bank 1)
GND
E5, E8, H5, H8
E2, H2, M4, B7, B3
L7, J9, H12, E9, A9
—
F6, G6, G7, F7
1, 37, 73, 109
GND (Bank 0)
GND (Bank 1)
NC
G5, H4, H6, E6, F5
H7, J9, G8, F8, E7
10, 184, 27, 46, 127, 137
55, 65, 82, 904, 99, 118
4064ZE: E4, B2, B1, D2, D3, E1, 4128ZE: 17, 20, 38, 45, 72, 89, 92,
H1, H3, H2, L1, G4, M1, K3, M2, 110, 117, 144
M4, L5, H7, L8, M8, L10, K9, M11, 4256ZE: 18, 90
H9, L12, L11, J12, J11, H10, D10,
F10, D12, B12, F9, A12, C10, B10,
A9, B8, E6, B5, A5, C4, B3, A2
4128ZE: D2, D3, H2, M1, K3, M11,
J12, J11, D12, A12, C10, A2
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
the bank shown.
2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order
ascending horizontally.
4. For the LC4256ZE, pins 18 and 90 are no connects.
35
ispMACH 4000ZE Family Data Sheet
ispMACH 4032ZE and 4064ZE Logic Signal Connections: 48 TQFP
ispMACH 4032ZE
ispMACH 4064ZE
Pin Number
Bank Number
GLB/MC/Pad
GLB/MC/Pad
1
-
TDI
TDI
2
0
0
0
0
0
0
0
0
0
-
A5
A8
3
A6
A10
4
A7
A11
5
GND (Bank 0)
GND (Bank 0)
6
VCCO (Bank 0)
VCCO (Bank 0)
7
A8
A9
B15
B12
8
9
A10
B10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
A11
B8
TCK
VCC
GND
A12
TCK
VCC
GND
B6
-
-
0
0
0
0
0
1
1
1
1
1
1
-
A13
B4
A14
B2
A15
B0
CLK1/I
CLK2/I
B0
CLK1/I
CLK2/I
C0
B1
C1
B2
C2
B3
C4
B4
C6
TMS
B5
TMS
C8
1
1
1
1
1
1
1
1
1
-
B6
C10
B7
C11
GND (Bank 1)
VCCO (Bank 1)
B8
GND (Bank 1)
VCCO (Bank 1)
D15
B9
D12
B10
D10
B11
D8
TDO
VCC
GND
B12
TDO
VCC
GND
D6
-
-
1
1
1
1
1
B13
D4
B14
D2
B15/GOE1
CLK3/I
D0/GOE1
CLK3/I
36
ispMACH 4000ZE Family Data Sheet
ispMACH 4032ZE and 4064ZE Logic Signal Connections: 48 TQFP (Cont.)
ispMACH 4032ZE
ispMACH 4064ZE
Pin Number
Bank Number
GLB/MC/Pad
GLB/MC/Pad
43
44
45
46
47
48
0
0
0
0
0
0
CLK0/I
A0/GOE0
A1
CLK0/I
A0/GOE0
A1
A2
A2
A3
A4
A4
A6
37
ispMACH 4000ZE Family Data Sheet
ispMACH 4032ZE and 4064ZE Logic Signal Connections: 64 csBGA
ispMACH 4032ZE
ispMACH 4064ZE
Ball Number
B2
Bank Number
GLB/MC/Pad
GLB/MC/Pad
-
TDI
TDI
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
A5
A8
C2
A6
A10
C1
A7
A11
GND*
C3
GND (Bank 0)
GND (Bank 0)
NC
A12
E3
VCCO (Bank 0)
VCCO (Bank 0)
D1
A8
B15
D2
NC
B14
E1
A9
B13
D3
A10
B12
F1
A11
B11
E2
NC
B10
G1
NC
B9
F2
NC
B8
H1
TCK
TCK
E4
-
VCC
VCC
GND*
G2
-
GND
GND
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
-
A12
B6
H2
NC
B5
H3
A13
B4
GND*
F4
NC
GND (Bank 0)
NC
VCCO (Bank 0)
G3
A14
B3
F3
NC
B2
H4
A15
B0
G4
CLK1/I
CLK1/I
H5
CLK2/I
CLK2/I
F5
B0
C0
G5
B1
C1
G6
B2
C2
H6
B3
C4
F6
B4
C5
H7
NC
C6
TMS
H8
TMS
G7
1
1
1
1
1
1
1
B5
C8
F7
B6
C10
G8
B7
GND (Bank 0)
NC
C11
GND*
F8
GND (Bank 1)
C12
D6
VCCO (Bank 1)
B8
VCCO (Bank 1)
D15
E8
38
ispMACH 4000ZE Family Data Sheet
ispMACH 4032ZE and 4064ZE Logic Signal Connections: 64 csBGA (Cont.)
ispMACH 4032ZE
ispMACH 4064ZE
Ball Number
E7
Bank Number
GLB/MC/Pad
NC
GLB/MC/Pad
1
1
1
1
1
1
1
-
D14
E6
B9
D13
D7
B10
D12
D8
NC
D11
C5
NC
D10
C7
B11
D9
C8
NC
D8
B8
TDO
VCC
GND
B12
TDO
D5
-
VCC
GND*
A8
-
GND
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
D7
A7
NC
D6
B7
NC
D5
A6
B13
D4
GND (Bank 1)
VCCO (Bank 1)
D3
GND*
C6
NC
NC
B6
B14
A5
NC
D2
B5
B15/GOE1
CLK3/I
CLK0/I
A0/GOE0
A1
D0/GOE1
CLK3/I
CLK0/I
A0/GOE0
A1
A4
C4
B4
B3
A3
A2
A2
A2
A3
A4
A1
A4
A6
* All bonded grounds are connected to the following two balls, D4 and E5.
39
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE Logic Signal Connections: 64 ucBGA
Ball Number
Bank Number
GLB/MC/Pad
A1
-
TDI
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
A8
B2
A10
B3
A11
GND*
C1
GND (Bank 0)
A12
C3
VCCO (Bank 0)
C2
B15
D1
B14
D2
B13
D3
B12
E1
B11
E2
B10
E3
B9
F1
B8
F2
TCK
E4
-
VCC
GND*
H2
-
GND
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
-
B6
H1
B5
G1
B4
GND*
F3
GND (Bank 0)
VCCO (Bank 0)
G2
B3
G3
B2
H3
B0
G4
CLK1/I
F4
CLK2/I
H4
C0
H5
C1
G5
C2
H6
C4
H7
C5
H8
C6
G8
TMS
G7
1
1
1
1
1
1
1
1
C8
C10
G6
F8
C11
GND*
F7
GND (Bank 1)
C12
F6
VCCO (Bank 1)
D15
F5
E8
D14
40
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE Logic Signal Connections: 64 ucBGA (Cont.)
Ball Number
Bank Number
GLB/MC/Pad
E7
1
1
1
1
1
1
-
D13
E6
D12
D8
D11
D7
D10
D6
D9
C8
D8
C7
TDO
D5
-
VCC
GND*
B8
-
GND
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
D7
A8
D6
B7
D5
A7
D4
GND (Bank 1)
VCCO (Bank 1)
D3
GND*
A6
B6
C6
D2
A5
D0/GOE1
CLK3/I
CLK0/I
A0/GOE0
A1
B5
C5
A4
B4
C4
A2
A3
A4
A2
A6
* All bonded grounds are connected to the following two balls, D4 and E5.
41
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections:
100 TQFP
LC4064ZE
LC4128ZE
LC4256ZE
Pin
Bank
Number
Number
GLB/MC/Pad
GLB/MC/Pad
GLB/MC/Pad
1
2
-
GND
GND
GND
-
TDI
TDI
TDI
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
A8
B0
C12
4
A9
B2
C10
5
A10
B4
C6
6
A11
B6
C2
7
GND (Bank 0)
GND (Bank 0)
GND (Bank 0)
8
A12
B8
D12
9
A13
B10
D10
10
11
12*
13
14
15
16
17
18
19
20
21
22
23*
24
25
26
27*
28
29
30
31
32
33
34
35
36
37
38
39
40
41
A14
B12
D6
A15
B13
D4
I
I
I
VCCO (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
B15
C14
E4
B14
C12
E6
B13
C10
E10
B12
C8
E12
GND (Bank 0)
GND (Bank 0)
GND (Bank 0)
B11
C6
F2
B10
C5
F6
B9
C4
F10
B8
C2
F12
I
I
I
TCK
TCK
TCK
-
VCC
VCC
VCC
-
GND
GND
GND
0
0
0
0
0
0
0
0
0
0
0
0
1
-
I
I
I
B7
D13
G12
B6
D12
G10
B5
D10
G6
B4
D8
G2
GND (Bank 0)
GND (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
B3
B2
D6
D4
H12
H10
H6
B1
D2
B0
D0
H2
CLK1/I
CLK2/I
VCC
C0
CLK1/I
CLK2/I
VCC
E0
CLK1/I
CLK2/I
VCC
I2
1
42
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections:
100 TQFP (Cont.)
LC4064ZE
LC4128ZE
LC4256ZE
Pin
Bank
Number
Number
GLB/MC/Pad
GLB/MC/Pad
GLB/MC/Pad
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62*
63
64
65
66
67
68
69
70
71
72
73*
74
75
76
77*
78
79
80
81
82
1
1
1
1
1
1
1
1
1
-
C1
E2
I6
C2
E4
I10
C3
E6
I12
VCCO (Bank 1)
VCCO (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
GND (Bank 1)
GND (Bank 1)
C4
E8
J2
C5
E10
J6
C6
E12
J10
C7
E14
J12
GND
GND
GND
-
TMS
TMS
TMS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
C8
F0
K12
C9
F2
K10
C10
F4
K6
C11
F6
K2
GND (Bank 1)
GND (Bank 1)
GND (Bank 1)
C12
F8
L12
C13
F10
L10
C14
F12
L6
C15
F13
L4
I
I
I
VCCO (Bank 1)
VCCO (Bank 1)
VCCO (Bank 1)
D15
G14
M4
D14
G12
M6
D13
G10
M10
D12
G8
M12
GND (Bank 1)
GND (Bank 1)
GND (Bank 1)
D11
G6
N2
D10
G5
N6
D9
G4
N10
D8
G2
N12
I
I
I
TDO
TDO
TDO
-
VCC
VCC
VCC
-
GND
GND
GND
1
1
1
1
1
1
I
I
H13
I
D7
O12
O10
D6
H12
D5
D4
H10
O6
H8
O2
GND (Bank 1)
GND (Bank 1)
GND (Bank 1)
43
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections:
100 TQFP (Cont.)
LC4064ZE
LC4128ZE
LC4256ZE
GLB/MC/Pad
VCCO (Bank 1)
P12
Pin
Number
Bank
Number
GLB/MC/Pad
GLB/MC/Pad
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
1
1
1
1
1
0
-
VCCO (Bank 1)
VCCO (Bank 1)
D3
H6
H4
D2
P10
D1
H2
P6
D0/GOE1
H0/GOE1
CLK3/I
CLK0/I
VCC
P2/GOE1
CLK3/I
CLK0/I
VCC
CLK3/I
CLK0/I
VCC
0
0
0
0
0
0
0
0
0
0
A0/GOE0
A0/GOE0
A2
A2/GOE0
A6
A1
A2
A4
A10
A3
A6
A12
VCCO (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
A8
VCCO (Bank 0)
GND (Bank 0)
B2
GND (Bank 0)
A4
A5
A6
A7
A10
B6
A12
B10
A14
B12
* This pin is input only.
44
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE Logic Signal Connections: 132 ucBGA
Ball Number
GND*
A1
Bank Number
GLB/MC/Pad
-
GND
-
TDI
B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
VCCO (Bank 0)
D3
C1
D2
D1
E4
B0
B1
B2
B4
B5
F3
B6
E2
GND (Bank 0)
E1
B8
E3
B9
F4
B10
G4
F2
B12
B13
G3
H4
F1
B14
VCCO (Bank 0)
C14
G2
G1
H3
J4
C13
C12
C10
C9
H1
H2
J3
C8
GND (Bank 0)
C6
J1
C5
J2
C4
K3
C2
K2
C1
K1
C0
L2
VCCO (Bank 0)
L1
TCK
M1
GND*
L3
-
VCC
-
GND
0
0
0
0
0
0
0
0
0
D14
M2
K4
D13
D12
M3
K5
D10
D9
D8
L4
M4
J5
GND (Bank 0)
VCCO (Bank 0)
D6
L5
45
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE Logic Signal Connections: 132 ucBGA (Cont.)
Ball Number
Bank Number
GLB/MC/Pad
M5
0
0
0
0
0
0
1
1
-
D5
J6
D4
K6
D2
L6
D1
M6
D0
K7
CLK1/I
L7
GND (Bank 1)
J7
CLK2/I
M7
VCC
K8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
E0
L8
E1
M8
E2
J8
E4
L9
E5
M9
E6
K9
VCCO (Bank 1)
J9
GND (Bank 1)
L10
K10
M10
L11
K12
M11
GND*
M12
L12
K11
J10
H9
E8
E9
E10
E12
E13
E14
GND
-
TMS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VCCO (Bank 1)
F0
F1
F2
J12
J11
H10
H12
G9
F4
F5
F6
GND (Bank 1)
F8
H11
F9
F9
F10
G12
G11
G10
F12
F10
F11
E11
E10
F12
F13
F14
VCCO (Bank 1)
G14
G13
G12
G10
46
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE Logic Signal Connections: 132 ucBGA (Cont.)
Ball Number
D10
E12
E9
Bank Number
GLB/MC/Pad
1
1
1
1
1
1
1
1
1
1
-
G9
G8
GND (Bank 1)
D12
D11
C12
C10
C11
B11
D9
G6
G5
G4
G2
G1
G0
VCCO (Bank 1)
B12
A12
GND*
A10
A11
B10
C9
TDO
-
VCC
-
GND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
-
H14
H13
H12
H10
D8
H9
C8
H8
A9
GND (Bank 1)
C7
VCCO (Bank 1)
B9
H6
B8
H5
D7
H4
A8
H2
A7
H1
B6
H0/GOE1
C6
CLK3/I
B7
GND (Bank 0)
D6
CLK0/I
B5
VCC
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
A0/GOE0
C5
A1
B4
A2
A5
A4
C4
A5
D5
A6
A4
VCCO (Bank 0)
B3
GND (Bank 0)
D4
A8
A9
A3
C3
A10
A12
A13
B2
C2
47
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE Logic Signal Connections: 132 ucBGA (Cont.)
Ball Number
Bank Number
GLB/MC/Pad
A2
0
A14
* All bonded core grounds are connected to the following four balls, E5, E8, H5 and H8.
48
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections:
144 csBGA
LC4064ZE
GLB/MC/Pad
GND
LC4128ZE
LC4256ZE
Ball
Number
Bank
Number
GLB/MC/Pad
GLB/MC/Pad
F6
-
GND
GND
A1
E4
B2
B1
C3
C2
C1
D1
G5
D2
D3
E1
E2
F2
-
TDI
TDI
TDI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
NC Ball
NC Ball
NC Ball
A8
VCCO (Bank 0)
VCCO (Bank 0)
B0
C12
B1
C10
B2
C8
A9
B4
C6
A10
B5
C4
A11
B6
C2
GND (Bank 0)
NC Ball
NC Ball
NC Ball
A12
GND (Bank 0)
GND (Bank 0)
NC Ball
D14
NC Ball
D12
B8
D10
B9
D8
A13
B10
D6
D4
F1
A14
B12
D4
A15
B13
D2
F3*
F4
I
B14
D0
VCCO (Bank 0)
B15
VCCO (Bank 0)
VCCO (Bank 0)
G1
E3
G2
G3
H1
H3
H2
H4
J1
C14
C13
E0
B14
E2
B13
C12
E4
B12
C10
E6
NC Ball
NC Ball
NC Ball
GND (Bank 0)
B11
C9
E8
C8
E10
NC Ball
GND (Bank 0)
C6
E12
GND (Bank 0)
F2
J3
B10
C5
F4
F6
J2
B9
C4
K1
K2*
L1
B8
C2
F8
I
C1
F10
NC Ball
NC Ball
TCK
C0
F12
G4
L2
VCCO (Bank 0)
TCK
VCCO (Bank 0)
TCK
H5
G6
M1
K3
M2
L3*
-
VCC
VCC
VCC
GND
G14
-
GND
GND
NC Ball
NC Ball
D14
0
0
0
0
NC Ball
NC Ball
NC Ball
I
G12
G10
D13
G8
49
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections:
144 csBGA (Cont.)
LC4064ZE
GLB/MC/Pad
B7
LC4128ZE
LC4256ZE
Ball
Number
Bank
Number
GLB/MC/Pad
GLB/MC/Pad
J4
K4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
-
D12
G6
B6
D10
G4
M3
L4
B5
D9
G2
B4
D8
G0
H6
J5
GND (Bank 0)
VCCO (Bank 0)
NC Ball
NC Ball
B3
GND (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
M4
L5
D6
H12
D5
H10
K5
D4
H8
J6
B2
D2
H6
M5
K6
B1
D1
H4
B0
D0
H2
L6
CLK1/I
NC Ball
CLK2/I
VCC
CLK1/I
CLK1/I
H7
M6
H8
K7
GND (Bank 1)
GND (Bank 1)
CLK2/I
CLK2/I
VCC
VCC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
C0
E0
I2
M7
L7
C1
E1
I4
C2
E2
I6
J7
C3
E4
I8
L8
NC Ball
NC Ball
VCCO (Bank 1)
GND (Bank 1)
C4
E5
I10
M8
J8
E6
I12
VCCO (Bank 1)
VCCO (Bank 1)
J9
GND (Bank 1)
GND (Bank 1)
M9
L9
E8
J2
C5
E9
J4
K8
C6
E10
J6
M10
L10
K9
C7
E12
J8
NC Ball
NC Ball
NC Ball
GND
E13
J10
E14
J12
M11
G7
M12
H9
L12
L11
K10
K12
J10
K11
G8
NC Ball
J14
GND
GND
-
TMS
TMS
TMS
1
1
1
1
1
1
1
1
NC Ball
NC Ball
NC Ball
C8
VCCO (Bank 1)
VCCO (Bank 1)
F0
K12
F1
K10
F2
K8
C9
F4
K6
C10
F5
F6
K4
K2
C11
GND (Bank 1)
GND (Bank 1)
GND (Bank 1)
50
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections:
144 csBGA (Cont.)
LC4064ZE
GLB/MC/Pad
NC Ball
NC Ball
NC Ball
C12
LC4128ZE
LC4256ZE
Ball
Number
Bank
Number
GLB/MC/Pad
GLB/MC/Pad
J12
J11
H10
H12
G11
H11
G12
G10*
G9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
NC Ball
L14
NC Ball
L12
F8
L10
F9
L8
C13
F10
L6
C14
F12
L4
C15
F13
L2
I
F14
L0
VCCO (Bank 1)
D15
VCCO (Bank 1)
VCCO (Bank 1)
F12
F11
E11
E12
D10
F10
D12
F8
G14
M0
D14
G13
M2
D13
G12
M4
D12
G10
M6
NC Ball
NC Ball
NC Ball
GND (Bank 1)
D11
G9
M8
G8
M10
NC Ball
M12
GND (Bank 1)
GND (Bank 1)
E10
D11
E9
G6
N2
D10
G5
N4
D9
G4
N6
C12
C11*
B12
F9
D8
G2
N8
I
G1
N10
NC Ball
NC Ball
TDO
G0
N12
VCCO (Bank 1)
VCCO (Bank 1)
B11
E8
TDO
TDO
-
VCC
VCC
VCC
F7
-
GND
GND
GND
A12
C10
B10
A11*
D9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NC Ball
NC Ball
NC Ball
I
NC Ball
O14
NC Ball
O12
H14
O10
H13
O8
D7
H12
O6
B9
D6
H10
O4
C9
D5
H9
O2
A10
E7
D4
H8
O0
GND (Bank 1)
VCCO (Bank 1)
NC Ball
NC Ball
D3
GND (Bank 1)
GND (Bank 1)
D8
VCCO (Bank 1)
VCCO (Bank 1)
A9
H6
H5
P12
P10
B8
C8
H4
P8
A8
D2
H2
P6
D7
D1
H1
P4
B7
D0/GOE1
H0/GOE1
P2/GOE1
51
ispMACH 4000ZE Family Data Sheet
ispMACH 4064ZE, 4128ZE and 4256ZE Logic Signal Connections:
144 csBGA (Cont.)
LC4064ZE
GLB/MC/Pad
CLK3/I
NC Ball
CLK0/I
VCC
LC4128ZE
LC4256ZE
Ball
Number
Bank
Number
GLB/MC/Pad
GLB/MC/Pad
C7
E6
A7
E5
D6
B6
A6
C6
B5
A5
D5
F5
A4
B4
C5
A3
C4
B3
A2
1
0
0
-
CLK3/I
CLK3/I
GND (Bank 0)
GND (Bank 0)
CLK0/I
CLK0/I
VCC
VCC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0/GOE0
A1
A0/GOE0
A2/GOE0
A1
A4
A2
A2
A6
A3
A4
A8
NC Ball
NC Ball
VCCO (Bank 0)
GND (Bank 0)
A4
A5
A10
A6
A12
VCCO (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
GND (Bank 0)
A8
A9
B2
B4
A5
A6
A10
B6
A7
A12
B8
NC Ball
NC Ball
NC Ball
A13
B10
B12
B14
A14
NC Ball
* This pin is input only for the LC4064ZE.
52
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP
LC4128ZE
LC4256ZE
Pin Number
Bank Number
GLB/MC/Pad
GLB/MC/Pad
1
2
-
GND
GND
-
TDI
TDI
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
VCCO (Bank 0)
VCCO (Bank 0)
4
B0
C12
5
B1
C10
6
B2
C8
7
B4
C6
8
B5
C4
9
B6
C2
10
11
12
13
14
15
16
17*
18
19
20*
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38*
39
40
41
42
GND (Bank 0)
GND (Bank 0)
B8
D14
B9
D12
B10
D10
B12
D8
B13
D6
B14
D4
NC
I
GND (Bank 0)
NC
VCCO (Bank 0)
VCCO (Bank 0)
NC
I
C14
E2
C13
E4
C12
E6
C10
E8
C9
E10
C8
E12
GND (Bank 0)
GND (Bank 0)
C6
F2
C5
F4
C4
F6
C2
C1
F8
F10
C0
F12
VCCO (Bank 0)
TCK
VCCO (Bank 0)
TCK
VCC
GND
I
-
VCC
-
GND
NC
0
0
0
0
0
D14
G12
G10
G8
D13
D12
D10
G6
53
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.)
LC4128ZE
LC4256ZE
Pin Number
43
Bank Number
GLB/MC/Pad
GLB/MC/Pad
0
0
0
0
0
0
0
0
0
0
0
0
1
1
-
D9
G4
44
D8
G2
45*
46
NC
I
GND (Bank 0)
GND (Bank 0)
47
VCCO (Bank 0)
VCCO (Bank 0)
48
D6
H12
49
D5
H10
50
D4
H8
51
D2
H6
52
D1
H4
53
D0
H2
54
CLK1/I
CLK1/I
55
GND (Bank 1)
GND (Bank 1)
56
CLK2/I
CLK2/I
57
VCC
VCC
58
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
E0
I2
59
E1
I4
60
E2
I6
61
E4
I8
62
E5
I10
63
E6
I12
64
VCCO (Bank 1)
VCCO (Bank 1)
65
GND (Bank 1)
GND (Bank 1)
66
E8
J2
67
E9
J4
68
E10
J6
69
E12
J8
70
E13
J10
71
E14
J12
72*
73
NC
I
GND
GND
74
-
TMS
TMS
75
1
1
1
1
1
1
1
1
1
1
1
VCCO (Bank 1)
VCCO (Bank 1)
76
F0
K12
77
F1
K10
78
F2
K8
79
F4
K6
80
F5
K4
81
F6
K2
GND (Bank 1)
L14
82
GND (Bank 1)
83
F8
F9
84
L12
85
F10
L10
54
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.)
LC4128ZE
LC4256ZE
Pin Number
86
Bank Number
GLB/MC/Pad
GLB/MC/Pad
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
F12
L8
87
F13
L6
88
F14
L4
89*
90
NC
I
GND (Bank 1)
NC
91
VCCO (Bank 1)
VCCO (Bank 1)
92*
93
NC
I
G14
M2
94
G13
M4
95
G12
M6
96
G10
M8
97
G9
M10
98
G8
M12
99
GND (Bank 1)
GND (Bank 1)
100
101
102
103
104
105
106
107
108
109
110*
111
112
113
114
115
116
117*
118
119
120
121
122
123
124
125
126
127
128
G6
N2
G5
N4
G4
N6
G2
N8
G1
N10
G0
N12
VCCO (Bank 1)
VCCO (Bank 1)
TDO
TDO
-
VCC
VCC
-
GND
GND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
NC
I
H14
O12
H13
O10
H12
O8
H10
O6
H9
O4
H8
NC
O2
I
GND (Bank 1)
VCCO (Bank 1)
P12
GND (Bank 1)
VCCO (Bank 1)
H6
H5
P10
H4
P8
H2
P6
H1
P4
H0/GOE1
CLK3/I
GND (Bank 0)
CLK0/I
P2/GOE1
CLK3/I
GND (Bank 0)
CLK0/I
55
ispMACH 4000ZE Family Data Sheet
ispMACH 4128ZE and 4256ZE Logic Signal Connections: 144 TQFP (Cont.)
LC4128ZE
LC4256ZE
Pin Number
Bank Number
GLB/MC/Pad
GLB/MC/Pad
129
-
VCC
VCC
130
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0/GOE0
A2/GOE0
131
A1
A4
132
A2
A6
133
A4
A8
134
A5
A10
135
A6
A12
136
VCCO (Bank 0)
VCCO (Bank 0)
137
GND (Bank 0)
GND (Bank 0)
138
A8
A9
B2
B4
B6
B8
B10
B12
I
139
140
A10
A12
A13
A14
NC
141
142
143
144*
* This pin is input only for the LC4256ZE.
56
ispMACH 4000ZE Family Data Sheet
Part Number Description
LC XXXX XX – XX XX XXX X XX
Production Status
Device Family
Blank = Final production device
ES = Engineering samples
Device Number
4032 = 32 Macrocells
4064 = 64 Macrocells
4128 = 128 Macrocells
4256 = 256 Macrocells
Operating Temperature Range
C = Commercial
I = Industrial
Pin/Ball Count
48 (1.0 mm thickness)
64
Power
ZE = Zero Power, Enhanced
Speed
100
4 = 4.4ns (4032ZE Only)
4 = 4.7ns (4064ZE Only)
5 = 5.8ns (All Devices)
7 = 7.5ns (All Devices)
132
144
Package
TN = Lead-free TQFP
MN = Lead-free csBGA (0.5 mm pitch)
UMN = Lead-free ucBGA (0.4 mm pitch)
ispMACH 4000ZE Family Speed Grade Offering
-4
-5
-7
Commercial Commercial
Industrial
Commercial
Industrial
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
Ordering Information
Note: ispMACH 4000ZE devices are dual marked except for the slowest commercial speed grade. For example, the
commercial speed grade LC4128ZE-5TN100C is also marked with the industrial grade -7I. The commercial grade
is always one speed grade faster than the associated dual mark industrial grade. The slowest commercial speed
grade devices are marked as commercial grade only. The markings appear as follows:
Figure 18. Mark Format for 100 TQFP and 144 TQFP Packages
LC4128ZE
5TN100C-7I
Datecode
LC4128ZE
7TN100C
Datecode
Dual Mark
Single Mark
Figure 19. Mark Format for 48 TQFP, 64 csBGA and 144 csBGA Packages
LC4032ZE
5MN-7I
Datecode
LC4032ZE
7MN
Datecode
Dual Mark
Single Mark
57
ispMACH 4000ZE Family Data Sheet
Figure 20. Mark Format for 64 ucBGA and 132 ucBGA Packages
LC4064ZE
4UN-5I
Datecode
LC4128ZE
7UN
Datecode
Dual Mark
Single Mark
Lead-Free Packaging
Commercial
Macrocells Voltage tPD
Pin/Ball
Count I/O Grade
Device
Part Number
LC4032ZE-4TN48C
LC4032ZE-5TN48C
LC4032ZE-7TN48C
LC4032ZE-4MN64C
LC4032ZE-5MN64C
LC4032ZE-7MN64C
LC4064ZE-4TN48C
LC4064ZE-5TN48C
LC4064ZE-7TN48C
LC4064ZE-4TN100C
LC4064ZE-5TN100C
LC4064ZE-7TN100C
LC4064ZE-4MN64C
LC4064ZE-5MN64C
LC4064ZE-7MN64C
LC4064ZE-4MN144C
LC4064ZE-5MN144C
LC4064ZE-7MN144C
LC4128ZE-5TN100C
LC4128ZE-7TN100C
LC4128ZE-5TN144C
LC4128ZE-7TN144C
LC4128ZE-5UMN132C
LC4128ZE-7UMN132C
LC4128ZE-5MN144C
LC4128ZE-7MN144C
LC4256ZE-5TN100C
LC4256ZE-7TN100C
LC4256ZE-5TN144C
LC4256ZE-7TN144C
LC4256ZE-5MN144C
LC4256ZE-7MN144C
Package
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free csBGA
Lead-Free csBGA
Lead-Free csBGA
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free csBGA
Lead-Free csBGA
Lead-Free csBGA
Lead-Free csBGA
Lead-Free csBGA
Lead-Free csBGA
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free ucBGA
Lead-Free ucBGA
Lead-Free csBGA
Lead-Free csBGA
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free csBGA
Lead-Free csBGA
32
32
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
4.4
5.8
7.5
4.4
5.8
7.5
4.7
5.8
7.5
4.7
5.8
7.5
4.7
5.8
7.5
4.7
5.8
7.5
5.8
7.5
5.8
7.5
5.8
7.5
5.8
7.5
5.8
7.5
5.8
7.5
5.8
7.5
48
48
32
32
32
32
32
32
32
32
32
64
64
64
48
48
48
64
64
64
64
64
96
96
96
96
96
96
64
64
96
96
108
108
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
32
48
LC4032ZE
32
64
32
64
32
64
64
48
64
48
64
48
64
100
100
100
64
64
64
LC4064ZE
64
64
64
64
64
64
144
144
144
100
100
144
144
132
132
144
144
100
100
144
144
144
144
64
64
128
128
128
128
128
128
128
128
256
256
256
256
256
256
LC4128ZE
LC4256ZE
58
ispMACH 4000ZE Family Data Sheet
Industrial
Macrocells Voltage tPD
Pin/Ball
Count I/O Grade
Device
Part Number
LC4032ZE-5TN48I
LC4032ZE-7TN48I
LC4032ZE-5MN64I
LC4032ZE-7MN64I
LC4064ZE-5TN48I
LC4064ZE-7TN48I
LC4064ZE-5TN100I
LC4064ZE-7TN100I
LC4064ZE-5MN64I
LC4064ZE-7MN64I
LC4064ZE-5UMN64I
LC4064ZE-7UMN64I
LC4064ZE-5MN144I
LC4064ZE-7MN144I
LC4128ZE-7TN100I
LC4128ZE-7UMN132I
LC4128ZE-7TN144I
LC4128ZE-7MN144I
LC4256ZE-7TN100I
Package
Lead-Free TQFP
Lead-Free TQFP
Lead-Free csBGA
Lead-Free csBGA
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free csBGA
Lead-Free csBGA
Lead-Free ucBGA
Lead-Free ucBGA
Lead-Free csBGA
Lead-Free csBGA
Lead-Free TQFP
Lead-Free ucBGA
Lead-Free TQFP
Lead-Free csBGA
Lead-Free TQFP
Lead-Free TQFP
Lead-Free csBGA
32
32
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
5.8
7.5
5.8
7.5
5.8
7.5
5.8
7.5
5.8
7.5
5.8
7.5
5.8
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
48
48
32
32
32
32
32
32
64
64
48
48
48
48
64
64
64
96
96
96
64
96
108
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LC4032ZE
32
64
32
64
64
48
64
48
64
100
100
64
64
64
LC4064ZE
64
64
64
64
64
64
64
144
144
100
132
144
144
100
144
144
64
128
128
128
128
256
256
256
I
I
I
I
I
I
I
LC4128ZE
LC4256ZE LC4256ZE-7TN144I
LC4256ZE-7MN144I
1. Contact factory for product availability.
For Further Information
In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH
4000ZE family:
• TN1168, ispMACH 4000ZE Timing Model Design and Usage Guidelines
• TN1174, Advanced Features of the ispMACH 4000ZE Family
• TN1187, Power Estimation in ispMACH 4000ZE Devices
• Package Diagrams
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
59
ispMACH 4000ZE Family Data Sheet
Revision History
Date
Version
01.0
Change Summary
April 2008
July 2008
Initial release.
01.1
Updated Features bullets.
Updated typical Hysteresis voltage.
Updated Power Guard for Dedicated Inputs section.
Updated DC Electrical Characteristics table.
Updated Supply Current table.
Updated I/O DC Electrical Characteristics table and note 2.
Updated ispMACH 4000ZE Timing Model.
Added new parameters for the Internal Oscillator.
Updated ORP Reference table.
Updated Power Supply and NC Connections table.
Updated 100 TQFP Logic Signal Connections table with LC4128ZE and 4256ZE.
Updated 144 csBGA Logic Signal Connections table with LC4128ZE and 4256ZE.
Added 144 TQFP Logic Signal Connections table.
Data sheet status changed from advance to final.
Updated Supply Current table.
August 2008
01.2
01.3
Updated External Switching Characteristics.
Updated Internal Timing Parameters.
Updated Power Consumption graph and Power Estimation Coefficients table.
Updated Ordering Information mark format example.
December 2008
Updated ispMACH 4000ZE Family Selection Guide table to include 64-ball ucBGA and 132-ball
ucBGA packages.
Updated ispMACH 4000ZE Power Supply and NC Connections table to include 64-ball ucBGA
and 132-ball ucBGA packages.
Added Logic Signal Connections tables for 64-ball ucBGA and 132-ball ucBGA packages.
Updated Part Number Description diagram for 64-ball ucBGA and 132-ball ucBGA packages.
Updated Ordering Information tables for 64-ball ucBGA and 132-ball ucBGA packages.
May 2009
June 2011
01.4
01.5
Correction to tCW, tGW, tWIR and fMAX parameters in External Switching Characteristics table.
Added copper bond package part numbers.
Added footnote 4 to Absolute Maximum Ratings.
February 2012
February 2012
01.6
01.7
Updated document with new corporate logo.
Removed copper bond packaging information. Refer to PCN 04A-12 for further information.
Updated topside marks with new logos in the Ordering Information section.
60
相关型号：
LC4128ZE-7UMN132C
EE PLD, 7.5ns, 128-Cell, CMOS, PBGA132, 6 X 6 MM, 0.4 MM PITCH, LEAD FREE, UCBGA-132
LATTICE
LC4128ZE-7UMN132I
EE PLD, 7.5ns, 128-Cell, CMOS, PBGA132, 6 X 6 MM, 0.4 MM PITCH, LEAD FREE, UCBGA-132
LATTICE
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