LC4256B-3F256AI [LATTICE]
EE PLD, 3.8ns, 256-Cell, CMOS, PBGA256,;型号: | LC4256B-3F256AI |
厂家: | LATTICE SEMICONDUCTOR |
描述: | EE PLD, 3.8ns, 256-Cell, CMOS, PBGA256, 可编程逻辑 |
文件: | 总59页 (文件大小:1407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TM
ispMACH 4000V/B/C Family
3.3V/2.5V/1.8V In-System Programmable
TM
SuperFAST High Density PLDs
July 2002
Data Sheet
■ Broad Device Offering
• 32 to 512 macrocells
• 30 to 208 I/O pins
Features
■ High Performance
• f
= 400MHz maximum operating frequency
MAX
• 44 to 256 pins/balls in TQFP or fpBGA packages
• Commercial and industrial temperature ranges
• t = 2.5ns propagation delay
PD
• Up to four global clock pins with programmable
clock polarity control
■ Easy System Integration
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Operation with 3.3V (4000V), 2.5V (4000B) or
1.8V (4000C) supplies
• Up to 80 PTs per output
■ Ease of Design
• Enhanced macrocells with individual clock,
reset, preset and clock enable controls
• Up to four global OE controls
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT
path
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V In-System Programmable
(ISP™) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Wide input gating (36 input logic blocks) for fast
counters, state machines and address decoders
■ Low Power
• 1.8V core E2CMOS® technology
• CMOS design techniques provide low static and
dynamic power
Table 1. ispMACH 4000V/B/C Family Selection Guide
ispMACH
ispMACH
ispMACH
ispMACH
ispMACH
ispMACH
4032V/B/C
4064V/B/C
4128V/B/C
4256V/B/C
4384V/B/C
4512V/B/C
Macrocells
User I/O Options
32
30/32
2.5
64
30/32/64
2.5
128
64/92
2.7
256
64/128/160
3.0
384
128/192
3.5
512
128/208
3.5
t
(ns)
PD
t (ns)
1.8
1.8
1.8
2.0
2.0
2.0
S
t
f
(ns)
2.2
400
2.2
400
2.7
333
2.7
322
2.7
322
2.7
322
CO
(MHz)
MAX
Supply Voltages (V)
Pins/Package
3.3/2.5/1.8V
3.3/2.5/1.8V
3.3/2.5/1.8V
3.3/2.5/1.8V
3.3/2.5/1.8V
3.3/2.5/1.8V
44 TQFP
44 TQFP
48 TQFP
100 TQFP
48 TQFP
100 TQFP
128 TQFP
100 TQFP
176 TQFP
176 TQFP
256 fpBGA
176 TQFP
256 fpBGA
256 fpBGA*
*128-I/O and 160-I/O configurations.
www.latticesemi.com
1
ispm4k_10
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI® 2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low
power in a flexible CPLD family.
The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP) and Fine Pitch BGA (fpBGA) packages ranging from 44 to 256 pins/balls.
Table 1 shows the macrocell, package and I/O options, along with other key parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. The ispMACH 4000 also offers
enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down
resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/2.5V/1.8V in-system
programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability
also allows product testing on automated test equipment.
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
contain multiple I/O cells. This architecture is shown in Figure 1.
Figure 1. Functional Block Diagram
I/O
Block
I/O
Block
16
36
16
36
Generic
Logic
Block
Generic
Logic
Block
ORP
ORP
16
16
I/O
Block
I/O
Block
16
36
16
36
Generic
Logic
Block
Generic
Logic
Block
ORP 16
16
ORP
2
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can
support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-
patible with the power supply provided to the bank. Support for a variety of standards helps designers implement
designs in mixed voltage environments.
ispMACH 4000 Architecture
There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has
36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be
connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still
must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and
predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-
ated I/O cells in the I/O block.
Generic Logic Block
The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock
generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-
pled from macrocells through the ORP. Figure 2 illustrates the GLB.
Figure 2. Generic Logic Block
To GRP
Clock
Generator
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
36 Inputs
from GRP
To
Product Term
Output Enable
Sharing
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
3
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Figure 3. AND Array
In[0]
In[34]
In[35]
PT0
PT1
PT2
PT3
PT4
Cluster 0
PT75
PT76
PT77
PT78
PT79
Cluster 15
PT80 Shared PT Clock
PT81 Shared PT Initialization
PT82 Shared PTOE
Note:
Indicates programmable fuse.
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms.
The software automatically considers the availability and distribution of product term clusters as it fits the functions
within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed
Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for
increased performance.
The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
to to
n-1 n-2
from from
n-1 n-4
Fast 5-PT
Path
From
n-4
1-80
PTs
5-PT
n
To XOR (MC)
Cluster
to
n+1
from
n+2
from
n+1
To n+4
Individual Product
Term Allocator
Cluster
Allocator
SuperWIDE™
Steering Logic
4
Lattice Semiconductor
Product Term Allocator
ispMACH 4000V/B/C Family Data Sheet
The product term allocator assigns product terms from a cluster to either logic or control applications as required
by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-
ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated
with the cluster. Table 2 shows the available functions for each of the five product terms in the cluster. The OR gate
output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic
allocator.
Table 2. Individual PT Steering
Product Term
PTn
Logic
Control
Logic PT
Logic PT
Logic PT
Logic PT
Logic PT
Single PT for XOR/OR
Individual Clock (PT Clock)
PTn+1
PTn+2
PTn+3
PTn+4
Individual Initialization or Individual Clock Enable (PT Initialization/CE)
Individual Initialization (PT Initialization)
Individual OE (PTOE)
Cluster Allocator
The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions
with more product terms. Table 3 shows which clusters can be steered to which macrocells. Used in this manner,
the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator
accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.
Table 3. Available Clusters for Each Macrocell
Macrocell
M0
Available Clusters
—
C0
C0
C1
C1
C2
C2
C3
M1
M2
C1
C2
C3
C4
M3
C2
C3
C4
C5
M4
C3
C4
C5
C6
M5
C4
C5
C6
C7
M6
C5
C6
C7
C8
M7
C6
C7
C8
C9
M8
M9
C7
C8
C9
C10
C11
C12
C13
C14
C8
C9
C9
C10
C11
C12
C13
C14
C15
—
C10
C11
C12
C13
C14
C15
—
M10
M11
M12
M13
M14
M15
C10
C11
C12
C13
C14
C15
—
Wide Steering Logic
The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-
tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions
and allowing performance to be increased through a single GLB implementation. Table 4 shows the product term
chains.
5
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Table 4. Product Term Expansion Capability
Expansion
Chains
Macrocells Associated with Expansion Chain
(with Wrap Around)
Max PT/
Macrocell
Chain-0
Chain-1
Chain-2
Chain-3
M0 → M4 → M8 → M12 → M0
M1 → M5 → M9 → M13 → M1
M2 → M6 → M10 → M14 → M2
M3 → M7 → M11 → M15 → M3
75
80
75
70
Every time the super cluster allocator is used, there is an incremental delay of t
. When the super cluster alloca-
EXP
tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-
ter is steered to M (n+4), then M (n) is ground).
Macrocell
The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-
grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions. Figure
5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input from
the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable delay in
this path allows designers to choose between the fastest possible set-up time and zero hold time.
Figure 5. Macrocell
Power-up
Initialization
Shared PT Initialization
PT Initialization (optional)
PT Initialization/CE (optional)
Delay
From I/O Cell
R
P
From Logic Allocator
To ORP
To GRP
D/T/L
Q
CE
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Single PT
PT Clock (optional)
Shared PT Clock
Enhanced Clock Multiplexer
The clock input to the flip-flop can select any of the four block clocks along with the shared PT clock, and true and
complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The
eight sources for the clock multiplexer are as follows:
• Block CLK0
• Block CLK1
6
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
• Block CLK2
• Block CLK3
• PT Clock
• PT Clock Inverted
• Shared PT Clock
• Ground
Clock Enable Multiplexer
Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-
lowing four sources:
• PT Initialization/CE
• PT Initialization/CE Inverted
• Shared PT Clock
• Logic High
Initialization Control
The ispMACH 4000 family architecture accommodates both block-level and macrocell-level set and reset capability.
There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell
level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset func-
tionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing
flexibility.
Note that the reset/preset swapping selection feature affects power-up reset as well. All flip-flops power up to a
known state for predictable system initialization. If a macrocell is configured to SET on a signal from the block-level
initialization, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a
signal from the block-level initialization or is not configured for set/reset, then that macrocell will RESET on power-
up. To guarantee initialization values, the V rise must be monotonic, and the clock must be inactive until the reset
CC
delay time has elapsed.
GLB Clock Generator
Each ispMACH 4000 device has four clock pins that are also routed to the GRP to be used as inputs. These pins
drive a clock generator in each GLB, as shown in Figure 6. The clock generator provides four clock signals that can
be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the true
and complement edges of the global clock signals.
Figure 6. GLB Clock Generator
CLK0
Block CLK0
CLK1
Block CLK1
CLK2
Block CLK2
CLK3
Block CLK3
7
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater flexibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-
put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the
output routing multipliers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists of
the following elements:
• Output Routing Multiplexers
• OE Routing Multiplexers
• Output Routing Pool Bypass Multiplexers
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
OE Routing Multiplexer
From PTOE
To I/O
Cell
OE
ORP
Bypass
Multiplexer
5-PT Fast Path
From Macrocell
To I/O
Cell
Output
Output Routing Multiplexer
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 5, 6, 7 and 8 provide the connection details.
Table 5. ORP Combinations for I/O Blocks with 8 I/Os
I/O Cell
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
8
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Table 6. ORP Combinations for I/O Blocks with 16 I/Os
I/O Cell
Available Macrocells
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
M0, M1, M2, M3, M4, M5, M6, M7
M1, M2, M3, M4, M5, M6, M7, M8
M2, M3, M4, M5, M6, M7, M8, M9
M3, M4, M5, M6, M7, M8, M9, M10
M4, M5, M6, M7, M8, M9, M10, M11
M5, M6, M7, M8, M9, M10, M11, M12
M6, M7, M8, M9, M10, M11, M12, M12
M7, M8, M9, M10, M11, M12, M13, M14
I/O 8
I/O 9
M8, M9, M10, M11, M12, M13, M14, M15
M9, M10, M11, M12, M13, M14, M15, M0
M10, M11, M12, M13, M14, M15, M0, M1
M11, M12, M13, M14, M15, M0, M1, M2
M12, M13, M14, M15, M0, M1, M2, M3
M13, M14, M15, M0, M1, M2, M3, M4
M14, M15, M0, M1, M2, M3, M4, M5
M15, M0, M1, M2, M3, M4, M5, M6
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
Table 7. ORP Combinations for I/O Blocks with 4 I/Os
I/O Cell
Available Macrocells
I/O 0
I/O 1
I/O 2
I/O 3
M0, M1, M2, M3, M4, M5, M6, M7
M4, M5, M6, M7, M8, M9, M10, M11
M8, M9, M10, M11, M12, M13, M14, M15
M12, M13, M14, M15, M0, M1, M2, M3
Table 8. ORP Combinations for I/O Blocks with 10 I/Os
I/O Cell
Available Macrocells
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M10, M11, M12, M13, M14, M15, M0, M1
M12, M13, M14, M15, M0, M1, M2, M3
M14, M15, M0, M1, M2, M3, M4, M5
M2, M3, M4, M5, M6, M7, M8
M10, M11, M12, M13, M14, M15, M0, M1
9
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ORP Bypass and Fast Output Multiplexers
The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the
ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also
allows the register output to bypass the ORP to achieve faster t
.
CO
Output Enable Routing Multiplexers
The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.
I/O Cell
The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus
maintenance circuitry. Figure 8 details the I/O cell.
Figure 8. I/O Cell
GOE 0
GOE 1
GOE 2
GOE 3
From ORP
VCC
VCCO
VCCO
*
*
*
From ORP
To Macrocell
To GRP
*Global fuses
Each output supports a variety of output standards dependent on the V
supplied to its I/O bank. Outputs can
CCO
also be configured for open drain operation. Each input can be programmed to support a variety of standards, inde-
pendent of the V
• LVTTL
supplied to its I/O bank. The I/O standards supported are:
CCO
• LVCMOS 1.8
• LVCMOS 3.3
• LVCMOS 2.5
• 3.3V PCI Compatible
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
configured to be a Pull-up Resistor.
Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be
individually configured for the higher speed transition (~3V/ns) or for the lower noise transition (~1V/ns). For high-
speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise and
keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be
used to achieve the highest speed. The slew rate is adjusted independent of power.
Global OE Generation
Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a
2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or
GOE pins. Each signal that drives the bus can optionally be inverted.
10
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
Figure 9. Global OE Generation for All Devices Except ispMACH 4032
Internal Global OE
Global OE
PT Bus
(4 lines)
4-Bit
Global OE Bus
Shared PTOE
(Block 0)
Shared PTOE
(Block n)
Global
Fuses
GOE (0:3)
to I/O cells
Fuse connection
Hard wired
Figure 10. Global OE Generation for ispMACH 4032
Internal Global OE
PT Bus
4-Bit
Global OE Bus
Global OE
(2 lines)
Shared PTOE
(Block 0)
Shared PTOE
(Block 1)
Global
Fuses
GOE (3:0)
to I/O cells
Fuse connection
Hard wired
11
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Low Power and Power Management
The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and
low power. With an advanced E2 low power cell and non sense-amplifier design approach (full CMOS logic
approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low
standby power without needing any “turbo bits” or other power management schemes associated with a traditional
sense-amplifier approach.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows
functional testing of the circuit board on which the device is mounted through a serial scan path that can access all
critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked
into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS
interface that corresponds to the power supply voltage.
I/O Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized.The ispMACH 4000 family of devices allows
this by offering the user the ability to quickly configure the physical nature of the I/O cells. This quick configuration
takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's
ispVM™ System programming software can either perform the quick configuration through the PC parallel port, or
can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inven-
tory levels, higher quality and the ability to make in-field modifications. All ispMACH 4000 devices provide In-Sys-
tem Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been
implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE
1149.1 as the communication interface through which ISP is achieved, users get the benefit of a standard, well-
defined interface. All ispMACH 4000 devices are also compliant with the IEEE 1532 standard.
The ispMACH 4000 devices can be programmed across the commercial temperature and voltage range. The PC-
based Lattice software facilitates in-system programming of ispMACH 4000 devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
mated test equipment. This equipment can then be used to program ispMACH 4000 devices during the testing of a
circuit board.
Security Bit
A programmable security bit is provided on the ispMACH 4000 devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a
device programmer, securing proprietary designs from competitors. Programming and verification are also
defeated by the security bit. The bit can only be reset by erasing the entire device.
Hot Socketing
The ispMACH 4000 devices are well-suited for applications that require hot socketing capability. Hot socketing a
device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs with-
out being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals.
12
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Density Migration
The ispMACH 4000 family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-
geted for a high density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
13
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Absolute Maximum Ratings1, 2, 3
ispMACH 4000C
(1.8V)
ispMACH 4000B
(2.5V)
ispMACH 4000V
(3.3V)
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V. . . . . . . . . . -0.5 to 5.5V
CC
Output Supply Voltage (V
) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V. . . . . . . . . . -0.5 to 4.5V
CCO
Input or I/O Tristate Voltage Applied4 . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V. . . . . . . . . . -0.5 to 4.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C. . . . . . . . . -65 to 150°C . . . . . . . . .-65 to 150°C
Junction Temperature (T ) with Power Applied . . .-55 to 150°C. . . . . . . . . -55 to 150°C . . . . . . . . .-55 to 150°C
j
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied.
2. Compliance with Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (V (MAX) +2) volts is permitted for a duration of < 20ns.
IH
Recommended Operating Conditions
Symbol
Parameter
Min
1.65
2.3
3.0
0
Max
1.95
2.7
3.6
90
Units
Supply Voltage for 1.8V Devices
Supply Voltage for 2.5V Devices
Supply Voltage for 3.3V Devices
Junction Temperature (Commercial)
Junction Temperature (Industrial)
V
V
V
C
C
V
CC
T
j
-40
105
Erase Reprogram Specifications
Parameter
Erase/Reprogram Cycle
Min
1,000
Max
—
Units
Cycles
Note: Valid over commercial temperature range.
Hot Socketing Characteristics1,2,3
Symbol
Parameter
Condition
0 ≤ V ≤ V (MAX)
Min
—
Typ
—
Max
±150
Units
µA
I
Input or I/O Leakage Current
DK
IN
IH
1. Insensitive to sequence of V and V
. However, assumes monotonic rise/fall rates for V and V
.
CC
CCO
CC
CCO
2. 0 < V < V (MAX), 0 < V
< V
(MAX).
CC
CC
CCO
CCO
3. I is additive to I , I or I . Device defaults to pull-up until fuse circuitry is active.
DK
PU PD
BH
I/O Recommended Operating Conditions
V
(V)1
CCO
Standard
Min
3.0
Max
3.6
LVTTL
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
PCI 3.3
3.0
2.3
1.65
3.0
3.6
2.7
1.95
3.6
1. Typical values for V
are the average of the Min and Max values.
CCO
14
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Input Leakage Current
I/O Weak Pull-up Resistor Current
I/O Weak Pull-down Resistor Current V (MAX) ≤ V ≤ V (MIN)
Bus Hold Low Sustaining Current
Bus Hold High Sustaining Current
Bus Hold Low Overdrive Current
Bus Hold High Overdrive Current
Bus Hold Trip Points
Condition
0 ≤ V ≤ V (MAX)
Min
—
Typ
—
—
—
—
—
—
—
—
Max
10
150
150
—
—
150
-150
Units
µA
µA
µA
µA
µA
µA
µA
V
1
I , I
IL IH
IN
IH
I
I
I
I
I
I
0 ≤ V ≤ 0.7V
30
30
30
-30
—
PU
IN
CCO
PD
IL
IN
IH
V
V
= V (MAX)
BHLS
BHHS
BHLO
BHHO
IN
IL
= 0.7 V
IN
CCO
0V ≤ V ≤ V
IN
BHT
V
≤ V ≤ V
—
BHT
IN
CCO
V
—
V
* 0.35
V
* 0.65
BHT
CCO
CCO
V
V
V
V
V
V
= 3.3V, 2.5V, 1.8V
—
—
—
—
—
—
—
—
—
—
—
—
CCO
C
C
C
I/O Capacitance2
8
6
6
pf
pf
pf
1
2
3
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
= 3.3V, 2.5V, 1.8V
CCO
Clock Capacitance2
Global Input Capacitance2
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
= 3.3V, 2.5V, 1.8V
CCO
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not
measured with the output driver active. Bus maintenance circuits are disabled.
2. T = 25°C, f = 1.0MHz
A
15
Lattice Semiconductor
Supply Current
ispMACH 4000V/B/C Family Data Sheet
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min
Typ
Max
Units
ispMACH 4032V/B/C
V
V
V
V
V
V
= 3.3V
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
—
—
—
—
—
—
11.8
11.8
1.8
11.3
11.3
1.3
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
CC
CC
CC
CC
CC
CC
1, 2, 3
I
I
Operating Power Supply Current
Standby Power Supply Current
CC
4
CC
ispMACH 4064V/B/C
V
V
V
V
V
V
= 3.3V
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
—
—
—
—
—
—
12
12
2
11.5
11.5
1.5
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
CC
CC
CC
CC
CC
CC
1, 2, 3
I
I
Operating Power Supply Current
Standby Power Supply Current
CC
4
CC
ispMACH 4128V/B/C
V
V
V
V
V
V
= 3.3V
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
—
—
—
—
—
—
12
12
2
11.5
11.5
1.5
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
CC
CC
CC
CC
CC
CC
1, 2, 3
I
I
Operating Power Supply Current
Standby Power Supply Current
CC
4
CC
ispMACH 4256V/B/C
V
V
V
V
V
V
= 3.3V
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
—
—
—
—
—
—
12.5
12.5
2.5
12
12
2
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
CC
CC
CC
CC
CC
CC
1, 2, 3
I
I
Operating Power Supply Current
Standby Power Supply Current
CC
4
CC
ispMACH 4384V/B/C
V
V
V
V
V
V
= 3.3V
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
—
—
—
—
—
—
13.5
13.5
3.5
12.5
12.5
2.5
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
CC
CC
CC
CC
CC
CC
1, 2, 3
I
I
Operating Power Supply Current
Standby Power Supply Current
CC
4
CC
ispMACH 4512V/B/C
V
V
V
V
V
V
= 3.3V
= 2.5V
= 1.8V
= 3.3V
= 2.5V
= 1.8V
—
—
—
—
—
—
14
14
4
13
13
3
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
CC
CC
CC
CC
CC
CC
1, 2, 3
I
I
Operating Power Supply Current
Standby Power Supply Current
CC
4
CC
1. T = 25°C, frequency = 1.0MHz. 2. Device configured with 16-bit counters. 3. I varies with specific device configuration and operating
A
CC
frequency. 4. T = 25°C
A
16
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
I/O DC Electrical Characteristics
Over Recommended Operating Conditions
V
V
1
1
IL
IH
V
V
I
I
OH
OL
OH
OL
Standard
LVTTL
Min (V)
Max (V)
Min (V)
Max (V) Max (V)
Min (V)
(mA) (mA)
0.40
0.20
0.40
0.20
0.40
0.20
0.40
0.20
V
V
V
V
V
V
V
V
V
V
- 0.40
8.0
0.1
8.0
0.1
8.0
0.1
2.0
0.1
2.0
0.1
1.5
1.5
-4.0
-0.1
-4.0
-0.1
-4.0
-0.1
-2.0
-0.1
-2.0
-0.1
-0.5
-0.5
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
CCO
-0.3
0.80
0.80
0.70
0.63
2.0
2.0
3.6
- 0.20
- 0.40
- 0.20
- 0.40
- 0.20
- 0.45
- 0.20
- 0.45
- 0.20
LVCMOS 3.3
LVCMOS 2.5
-0.3
-0.3
-0.3
-0.3
3.6
1.70
1.17
3.6
LVCMOS 1.8
(4000V/B)
3.6
0.40
0.20
LVCMOS 1.8
(4000C)
0.35 V
0.65 * V
1.5
3.6
CC
CC
PCI 3.3 (4000V/B)
PCI 3.3 (4000C)
-0.3
-0.3
1.08
3.6
3.6
0.1 V
0.1 V
0.9 V
0.9 V
CCO
CCO
0.3 * 3.3 * (V / 1.8) 0.5 * 3.3 * (V / 1.8)
CC
CC
CCO
CCO
1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.
3.3V VCCO
2.5V VCCO
70
60
50
40
30
20
100
80
60
40
20
0
IOL
IOH
IOL
IOH
10
0
0
0.5
1.0
1.5
2.0
2.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
VO Output Voltage (V)
VO Output Voltage (V)
1.8V VCCO
60
50
IOL
IOH
40
30
20
10
0
0
0.5
1.0
1.5
2.0
VO Output Voltage (V)
17
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V/B/C External Switching Characteristics
Over Recommended Operating Conditions
-25
-27
-3
-35
Parameter
Description1, 2, 3
Min. Max. Min. Max. Min. Max. Min. Max. Units
5-PT bypass combinatorial propagation
—
—
2.5
3.2
—
—
2.7
3.5
—
—
3.0
3.8
—
—
3.5
4.2
ns
ns
t
PD
delay
20-PT combinatorial propagation delay
through macrocell
GLB register setup time before clock
t
t
t
PD_MC
1.8
2.0
—
—
1.8
2.0
—
—
2.0
2.2
—
—
2.0
2.2
—
—
ns
ns
S
GLB register setup time before clock
ST
with T-type register
GLB register setup time before clock,
input register path
0.7
1.7
—
—
1.0
2.0
—
—
1.0
2.0
—
—
1.0
2.0
—
—
t
ns
ns
SIR
GLB register setup time before clock
t
t
t
SIRZ
H
with zero hold
GLB register hold time after clock
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
GLB register hold time after clock with
HT
T-type register
GLB register hold time after clock, input
register path
0.9
0.0
—
—
1.0
0.0
—
—
1.0
0.0
—
—
1.0
0.0
—
—
t
t
ns
ns
HIR
GLB register hold time after clock, input
HIRZ
register path with zero hold
t
t
t
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
—
—
1.5
—
2.2
3.5
—
—
—
1.5
—
2.7
4.0
—
—
—
1.5
—
2.7
4.4
—
—
—
1.5
—
2.7
4.5
-
ns
ns
ns
CO
R
RW
Input to output local product term output
4.0
4.5
5.0
5.5
t
t
ns
ns
PTOE/DIS
enable/disable
Input to output global product term out-
put enable/disable
—
5.0
—
6.5
—
8.0
—
8.0
GPTOE/DIS
t
t
Global OE input to output enable/disable
Global clock width, high or low
—
1.1
1.1
3.0
—
—
—
1.3
1.3
3.5
—
—
—
1.3
1.3
4.0
—
—
—
1.3
1.3
4.5
—
—
ns
ns
GOE/DIS
CW
Global gate width low (for low transpar-
t
ns
GW
ent) or high (for high transparent)
t
f
Input register clock width, high or low
Clock frequency with internal feedback
1.1
400
—
—
—
1.3
333
222
—
—
—
1.3
322
212
—
—
—
1.3
322
212
—
—
—
ns
MHz
WIR
4
MAX
Clock frequency with external feedback, 250
f
(Ext.)
MHz
MAX
[1/ (t + t )]
S
CO
Timing v.3.1
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
18
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V/B/C External Switching Characteristics (Cont.)
Over Recommended Operating Conditions
-5
-75
-105
Parameter
Description1, 2, 3
Min. Max. Min. Max. Min. Max. Units
t
5-PT bypass combinatorial propagation delay
—
—
5.0
5.5
—
—
7.5
8.0
—
—
10.0
10.5
ns
ns
PD
20-PT combinatorial propagation delay through macro-
t
t
t
PD_MC
S
cell
GLB register setup time before clock
3.0
3.2
—
—
4.5
4.7
—
—
5.5
5.5
—
—
ns
ns
GLB register setup time before clock with
ST
T-type register
t
t
t
GLB register setup time before clock, input register path
GLB register setup time before clock with zero hold
GLB register hold time after clock
1.2
2.2
0.0
0.0
—
—
—
—
1.7
2.7
0.0
0.0
—
—
—
—
1.7
2.7
0.0
0.0
—
—
—
—
ns
ns
ns
ns
SIR
SIRZ
H
GLB register hold time after clock with
t
t
t
HT
T-type register
GLB register hold time after clock, input register path
1.0
0.0
—
—
1.0
0.0
—
—
1.0
0.0
—
—
ns
ns
HIR
HIRZ
GLB register hold time after clock, input register path with
zero hold
t
t
t
t
t
t
t
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output enable/disable
Input to output global product term output enable/disable
Global OE input to output enable/disable
Global clock width, high or low
—
—
2.0
—
—
—
3.40
6.30
—
7.00
9.00
5.00
—
—
—
4.0
—
—
—
4.5
9.0
—
9.0
10.3
7.0
—
—
—
4.0
—
—
—
6.0
10.5
—
10.5
12.0
8.0
—
ns
ns
ns
ns
ns
ns
ns
CO
R
RW
PTOE/DIS
GPTOE/DIS
GOE/DIS
CW
2.2
2.2
3.3
3.3
4.0
4.0
Global gate width low (for low transparent) or high (for
—
—
—
t
ns
GW
high transparent)
t
f
Input register clock width, high or low
Clock frequency with internal feedback
Clock frequency with external feedback,
2.2
227
156
—
—
—
3.3
168
111
—
—
—
4.0
125
86
—
—
—
ns
MHz
WIR
4
MAX
f
(Ext.)
MHz
MAX
[1/ (t + t )]
S
CO
Timing v.3.1
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
5. Only available in industrial grade.
19
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Timing Model
The task of determining the timing through the ispMACH 4000 family, like any CPLD, is relatively simple. The timing
model provided in Figure 10 shows the specific delay paths. Once the implementation of a given function is deter-
mined either conceptually or from the software report file, the delay path of the function can easily be determined
from the timing model. The Lattice design tools report the timing delays based on the same timing model for a par-
ticular design. Note that the internal timing parameters are given for reference only, and are not tested. The exter-
nal timing parameters are tested and guaranteed for every device. For more information on the timing model and
usage, please refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines.
Figure 10. ispMACH 4000 Timing Model
Routing/GLB Delays
From
Feedback
tPDb
tPDi
Feedback
Out
tFBK
tROUTE
tBLA
tMCELL
tEXP
tIN
tBUF
tIOO
tEN
DATA
IN
tORP
tIOI
Q
tINREG
tINDIO
tDIS
tGCLK_IN
tIOI
In/Out
Delays
SCLK
tPTCLK
tBCLK
C.E.
S/R
tPTSR
tBSR
Register/Latch
Delays
MC Reg.
tGPTOE
tPTOE
Control
Delays
tGOE
tIOI
OE
In/Out
Delays
Note: Italicized items are optional delay adders.
20
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V/B/C Internal Timing Parameters
Over Recommended Operating Conditions
-25
-27
-3
-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
In/Out Delays
t
t
t
t
t
t
Input Buffer Delay
Global OE Pin Delay
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
—
—
—
—
—
—
0.60
2.04
0.78
0.85
0.96
0.96
—
—
—
—
—
—
0.60
2.54
1.28
0.85
0.96
0.96
—
—
—
—
—
—
0.70
3.04
1.28
0.85
0.96
0.96
—
—
—
—
—
—
0.70
3.54
1.28
0.85
0.96
0.96
ns
ns
ns
ns
ns
ns
IN
GOE
GCLK_IN
BUF
EN
Output Disable Time
DIS
Routing/GLB Delays
t
t
t
t
t
t
Delay through GRP
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
—
—
—
—
—
—
0.61
0.45
0.11
0.00
0.44
0.64
—
—
—
—
—
—
0.81
0.55
0.31
0.00
0.44
0.64
—
—
—
—
—
—
1.01
0.55
0.31
0.00
0.44
0.64
—
—
—
—
—
—
1.01
0.65
0.31
0.00
0.94
0.94
ns
ns
ns
ns
ns
ns
ROUTE
MCELL
INREG
FBK
PDb
PDi
Register/Latch Delays
t
t
D-Register Setup Time (Global Clock)
0.92
1.42
—
—
1.12
1.32
—
—
1.02
1.32
—
—
0.92
1.32
—
—
ns
ns
S
D-Register Setup Time (Product Term
S_PT
Clock)
t
t
T-Register Setup Time (Global Clock)
1.12
1.42
—
—
1.32
1.32
—
—
1.22
1.32
—
—
1.12
1.32
—
—
ns
ns
ST
T-Register Setup Time (Product Term
ST_PT
Clock)
t
t
t
D-Register Hold Time
T-Register Hold Time
0.88
0.88
0.82
—
—
—
0.68
0.68
1.37
—
—
—
0.98
0.98
1.27
—
—
—
1.08
1.08
1.27
—
—
—
ns
ns
ns
H
HT
SIR
D-Input Register Setup Time (Global
Clock)
t
t
t
t
D-Input Register Setup Time (Product
Term Clock)
1.45
0.88
0.88
—
—
—
1.45
0.63
0.63
—
—
—
1.45
0.73
0.73
—
—
—
1.45
0.73
0.73
—
—
—
ns
ns
ns
ns
SIR_PT
HIR
D-Input Register Hold Time (Global
Clock)
D-Input Register Hold Time (Product
Term Clock)
—
—
—
—
HIR_PT
COi
Register Clock to Output/Feedback
0.52
0.52
0.52
0.52
MUX Time
t
t
t
t
t
t
Clock Enable Setup Time
Clock Enable Hold Time
Latch Setup Time (Global Clock)
Latch Setup Time (Product Term Clock) 1.42
Latch Hold Time
2.25
1.88
0.92
—
—
—
—
—
2.25
1.88
1.12
1.32
1.17
—
—
—
—
—
—
2.25
1.88
1.02
1.32
1.17
—
—
—
—
—
—
2.25
1.88
0.92
1.32
1.17
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
CES
CEH
SL
SL_PT
HL
1.17
—
Latch Gate to Output/Feedback MUX
0.33
0.33
0.33
0.33
GOi
Time
t
t
Propagation Delay through Transparent
Latch to Output/Feedback MUX
—
—
0.25
0.28
—
—
0.25
0.28
—
—
0.25
0.28
—
—
0.25
0.28
ns
ns
PDLi
SRi
Asynchronous Reset or Set to Output/
Feedback MUX Delay
21
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V/B/C Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
-25
-27
-3
-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
Asynchronous Reset or Set Recovery
—
1.67
—
1.67
—
1.67
—
1.67
ns
SRR
Delay
Control Delays
t
t
t
t
t
t
GLB PT Clock Delay
—
—
—
—
—
—
1.12
0.87
1.83
1.11
2.83
1.83
—
—
—
—
—
—
1.12
0.87
1.83
1.41
4.13
2.13
—
—
—
—
—
—
1.12
0.87
1.83
1.51
5.33
2.33
—
—
—
—
—
—
1.12
0.87
1.83
1.61
5.33
2.83
ns
ns
ns
ns
ns
BCLK
PTCLK
BSR
Macrocell PT Clock Delay
Block PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Global PT OE Delay
PTSR
GPTOE
PTOE
Macrocell PT OE Delay
ns
Timing v.3.1
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
22
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V/B/C Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
-5
-75
-101
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
In/Out Delays
t
t
t
t
t
t
Input Buffer Delay
Global OE Pin Delay
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
—
—
—
—
—
—
0.95
4.04
1.83
1.00
0.96
0.96
—
—
—
—
—
—
1.50
6.04
2.28
1.50
0.96
0.96
—
—
—
—
—
—
2.00
7.04
3.28
1.50
0.96
0.96
ns
ns
ns
ns
ns
ns
IN
GOE
GCLK_IN
BUF
EN
Output Disable Time
DIS
Routing/GLB Delays
t
t
t
t
t
t
Delay through GRP
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
—
—
—
—
—
—
1.51
1.05
0.56
0.00
1.54
0.94
—
—
—
—
—
—
2.26
1.45
0.96
0.00
2.24
1.24
—
—
—
—
—
—
3.26
1.95
1.46
0.00
3.24
1.74
ns
ns
ns
ns
ns
ns
ROUTE
MCELL
INREG
FBK
PDb
PDi
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
T-Register Setup Time (Global Clock)
T-Register Setup Time (Product Term Clock)
D-Register Hold Time
1.32
1.32
1.52
1.32
1.68
1.68
1.52
1.45
0.68
0.68
—
2.25
1.88
1.32
1.32
1.17
—
—
—
—
—
—
—
—
—
—
—
0.52
—
—
—
—
—
0.33
0.25
1.57
1.32
1.77
1.32
2.93
2.93
1.57
1.45
1.18
1.18
—
2.25
1.88
1.57
1.32
1.17
—
—
—
—
—
—
—
—
—
—
—
0.67
—
—
—
—
—
0.33
0.25
1.57
1.32
1.77
1.32
3.93
3.93
1.57
1.45
1.18
1.18
—
2.25
1.88
1.57
1.32
1.17
—
—
—
—
—
—
—
—
—
—
—
1.17
—
—
—
—
—
0.33
0.25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S
S_PT
ST
ST_PT
H
T-Register Hold Time
HT
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
Clock Enable Hold Time
Latch Setup Time (Global Clock)
Latch Setup Time (Product Term Clock)
Latch Hold Time
Latch Gate to Output/Feedback MUX Time
SIR
SIR_PT
HIR
HIR_PT
COi
CES
CEH
SL
SL_PT
HL
GOi
Propagation Delay through Transparent Latch to Output/
—
—
—
PDLi
Feedback MUX
t
Asynchronous Reset or Set to Output/Feedback MUX
Delay
Asynchronous Reset or Set Recovery Delay
—
—
0.28
1.67
—
—
0.28
1.67
—
—
0.28
1.67
ns
ns
SRi
t
SRR
Control Delays
t
t
t
t
GLB PT Clock Delay
—
—
—
—
1.12
0.87
1.83
2.51
—
—
—
—
1.12
0.87
1.83
3.41
—
—
—
—
0.62
0.87
1.83
3.41
ns
ns
ns
ns
BCLK
PTCLK
BSR
Macrocell PT Clock Delay
GLB PT Set/Reset Delay
Macrocell PT Set/Reset Delay
PTSR
23
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V/B/C Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
-5
-75
-101
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
t
t
Global PT OE Delay
Macrocell PT OE Delay
—
—
5.58
3.58
—
—
5.58
4.28
—
—
5.78
4.28
ns
ns
GPTOE
PTOE
Timing v.3.1
Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.
1. Only available in industrial grade.
24
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V/B/C Timing Adders1
-25
-27
-3
-35
Adder
Base
Type
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Optional Delay Adders
t
t
t
t
t
Input register delay
—
—
—
—
0.95
0.33
0.05
0.03
—
—
—
—
1.00
0.33
—
—
—
—
1.00
0.33
—
—
—
—
1.00
0.33
ns
ns
INDIO
INREG
Product term expander
t
EXP
MCELL
delay
—
Output routing pool delay
0.05
0.05
0.05
0.05
0.05
0.05
ns
ns
ORP
BLA
Additional block loading
t
ROUTE
adder
t
Input Adjusters
IOI
t , t
,
,
,
,
,
IN GCLK_IN
GOE
LVTTL_in
Using LVTTL standard
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
ns
ns
ns
ns
ns
t
t , t
Using LVCMOS 3.3
standard
IN GCLK_IN
GOE
LVCMOS33_in
LVCMOS25_in
LVCMOS18_in
PCI_in
t
t , t
Using LVCMOS 2.5
IN GCLK_IN
GOE
t
standard
t , t
Using LVCMOS 1.8
standard
IN GCLK_IN
GOE
t
t , t
Using PCI compatible
IN GCLK_IN
GOE
t
input
t
Output Adjusters
IOO
Output configured as
LVTTL_out
t
, t , t
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
—
—
—
—
—
—
0.20
0.20
0.10
0.00
0.20
1.00
ns
ns
ns
ns
ns
ns
BUF EN DIS
TTL buffer
Output configured as
LVCMOS33_out t
LVCMOS25_out t
LVCMOS18_out t
, t , t
BUF EN DIS
3.3V buffer
Output configured as
, t , t
BUF EN DIS
2.5V buffer
Output configured as
, t , t
BUF EN DIS
1.8V buffer
Output configured as
PCI_out
t
, t , t
BUF EN DIS
PCI compatible buffer
Output configured for
Slow Slew
t
, t
BUF EN
slow slew rate
Timing v.3.1
Note: Open drain timing is the same as corresponding LVCMOS timing.
1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
25
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V/B/C Timing Adders1
-5
-75
-102
Adder
Base
Type
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
Optional Delay Adders
t
t
t
t
t
t
Input register delay
Product term expander delay
Output routing pool delay
—
—
—
—
1.00
0.33
0.05
0.05
—
—
—
—
1.00
0.33
0.05
0.05
—
—
—
—
1.00
0.33
0.05
0.05
ns
ns
ns
ns
INDIO
EXP
INREG
MCELL
—
ORP
BLA
t
Additional block loading adder
ROUTE
t
Input Adjusters
IOI
t , t
,
,
,
,
,
IN GCLK_IN
GOE
LVTTL_in
Using LVTTL standard
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
—
—
—
—
—
0.60
0.60
0.60
0.00
0.60
ns
ns
ns
ns
ns
t
t , t
IN GCLK_IN
GOE
LVCMOS33_in
LVCMOS25_in
LVCMOS18_in
PCI_in
Using LVCMOS 3.3 standard
Using LVCMOS 2.5 standard
Using LVCMOS 1.8 standard
Using PCI compatible input
t
t , t
IN GCLK_IN
GOE
t
t , t
IN GCLK_IN
GOE
t
t , t
IN GCLK_IN
GOE
t
t
Output Adjusters
IOO
LVTTL_out
t
, t , t
, t , t
, t , t
, t , t
Output configured as TTL buffer
Output configured as 3.3V buffer
Output configured as 2.5V buffer
Output configured as 1.8V buffer
—
—
—
—
0.20
0.20
0.10
0.00
—
—
—
—
0.20
0.20
0.10
0.00
—
—
—
—
0.20
0.20
0.10
0.00
ns
ns
ns
ns
BUF EN DIS
LVCMOS33_out t
LVCMOS25_out t
LVCMOS18_out t
BUF EN DIS
BUF EN DIS
BUF EN DIS
Output configured as PCI compatible
PCI_out
t
, t , t
—
—
0.20
1.00
—
—
0.20
1.00
—
—
0.20
ns
BUF EN DIS
buffer
Slow Slew
t
, t
Output configured for slow slew rate
1.00
ns
BUF EN
Timing v.3.1
Note: Open drain timing is the same as corresponding LVCMOS timing.
1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.
2. Only available in industrial grade.
26
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Boundary Scan Waveforms and Timing Specifications
Symbol
Parameter
Min.
40
20
20
8
10
50
—
—
—
8
Max.
—
—
—
—
—
—
10
10
10
—
Units
ns
ns
ns
ns
ns
mV/ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK [BSCAN test] clock cycle
TCK [BSCAN test] pulse width high
TCK [BSCAN test] pulse width low
TCK [BSCAN test] setup time
TCK [BSCAN test] hold time
TCK [BSCAN test] rise and fall time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
BTCP
BTCH
BTCL
BTSU
BTH
BRF
BTCO
BTOZ
BTVO
BTCPSU
BTCPH
BTUCO
BTUOZ
BTUOV
ns
ns
ns
ns
BSCAN test Capture register hold time
10
—
—
—
—
BSCAN test Update reg, falling edge of clock to valid output
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
25
25
25
ns
27
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Power Consumption
ispMACH 4000V/B
ispMACH 4000C
Typical I vs. Frequency
Typical I
vs. Frequency
CC
CC
4512V/B
4384V/B
300
250
200
150
100
300
250
200
150
100
4512C
4384C
4256V/B
4256C
4128C
4128V/B
4064V/B
4032V/B
50
0
50
0
4064C
4032C
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
Note: The devices are configured with maximum number
Note: The devices are configured with maximum number
of 16-bit counters, typical current at 1.8V, 25°C.
of 16-bit counters, typical current at 3.3V, 2.5V, 25°C.
Power Estimation Coefficients
Device
ispMACH 4032V/B
ispMACH 4032C
ispMACH 4064V/B
ispMACH 4064C
ispMACH 4128V/B
ispMACH 4128C
ispMACH 4256V/B
ispMACH 4256C
ispMACH 4384V/B
ispMACH 4384C
ispMACH 4512V/B
ispMACH 4512C
A
B
11.3
1.3
11.5
1.5
11.5
1.5
12
0.010
0.010
0.010
0.010
0.011
0.011
0.011
0.011
0.013
0.013
0.013
0.013
2
12.5
2.5
13
3
Note: For further information about the use of these coefficients, refer to Technical Note TN1005, Power Estimation in ispMACH 4000V/B/C
Devices.
28
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Switching Test Conditions
Figure 11 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 9.
Figure 11. Output Test Load, LVTTL and LVCMOS Standards
V
CCO
R
1
2
Test
Point
DUT
R
C
L
0213A/ispm4k
Table 9.Test Fixture Required Components
1
Test Condition
R
R
C
Timing Ref.
V
CCO
1
2
L
LVCMOS 3.3 = 1.5V
LVCMOS 3.3 = 3.0V
LVCMOS I/O, (L -> H, H -> L)
106Ω 106Ω
35pF
LVCMOS 2.5 = V
LVCMOS 1.8 = V
1.5V
/2
/2
LVCMOS 2.5 = 2.3V
LVCMOS 1.8 = 1.65V
3.0V
3.0V
3.0V
3.0V
CCO
CCO
LVCMOS I/O (Z -> H)
LVCMOS I/O (Z -> L)
LVCMOS I/O (H -> Z)
LVCMOS I/O (L -> Z)
∞
106Ω
∞
35pF
35pF
5pF
106Ω
∞
1.5V
106Ω
∞
V
V
- 0.3
+ 0.3
OH
OL
106Ω
5pF
1. C includes test fixtures and probe capacitance.
L
29
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Signal Descriptions
Signal Names
Description
TMS
Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control
the state machine
TCK
Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the
state machine
TDI
TDO
GOE0, GOE1
GND
Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data
Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out
Input – These pins are the Global Output Enable Input pins
Ground
NC
Not Connected
V
The power supply pins for logic core
CC
CLK0/I, CLK1/I, CLK2/I, CLK3/I
, V
These pins are configured to be either CLK input or as an input
The power supply pins for each I/O bank
V
CCO0 CCO1
Input/Output1 – These are the general purpose I/O used by the logic array. y is GLB
reference (alpha) and z is macrocell reference (numeric). z: 0-15
ispMACH 4032
ispMACH 4064
ispMACH 4128
ispMACH 4256
ispMACH 4384
ispMACH 4512
y: A-B
y: A-D
y: A-H
yzz
y: A-P
y: A-P, AX-HX
y: A-P, AX-PX
1. In some packages, certain I/O are only available for use as inputs. See the signal connections table for details.
30
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V/B/C Power Supply and NC Connections1
Signal
VCC
44 TQFP
11, 33
48 TQFP
12, 36
100 TQFP 128 TQFP 176 TQFP
256 fpBGA2, 3
25, 40, 75, 32, 51, 96, 42, 69, 88, B2, B15, G8, G9, K8, K9, R2, R15
90
115
130, 157,
176
VCCO0
VCCO1
GND
6
6
13, 33, 95
45, 63, 83
3, 17, 30,
41, 122
4, 22, 40,
56, 166
D6, F4, H7, J7, L4, N6
28
30
13, 37
5
58, 67, 81, 78, 92, 110, D11, F13, H10, J10, L13, N11
94, 105 128, 144
12, 34
1, 26, 51, 76 1, 33, 65, 97 2, 46, 65,
A1, A16, C6, C11, F3, F14, G7, G10, H8,
90, 134, 153 H9, J8, J9, K7, K10, L3, L14, P6, P11, T1,
T16
GND (Bank 0) 5
GND (Bank 1) 27
7, 18, 32, 96 10, 24, 40, 13, 31, 55,
113, 123
155, 167
29
—
46, 57, 68, 49, 59, 74, 67, 79, 101,
82
—
88, 104
—
119, 143
1, 43, 44,
NC
—
4256V/B/C, 128 I/O: A4, A5, A6, A11,
45, 89, 131, A12, A13, A15, B5, B6, B11, B12, B14,
132, 133
C7, D1, D4, D5, D10, D12, D16, E1, E2,
E4, E5, E7, E10, E13, E14, E15, E16, F1,
F2, F15, F16, G1, G4, G5, G6, G12, G13,
G14, J11, K3, K4, K15, L1, L2, L12, L15,
L16, M1, M2, M3, M4, M5, M12, M13,
M15, M16, N1, N2, N7, N10, N12, N14,
P5, P12, R4, R5, R6, R11, R12, R16, T2,
T4, T5, T6, T11, T12, T13, T15
4256V/B/C, 160 I/O: A5, A12, A15, B5,
B6, B11, B12, B14, D4, D5, D12, E1, E4,
E5, E13, E15, E16, F1, F2, F15, G1, G5,
G12, G14, L1, L2, L12, L15, L16, M1, M2,
M3, M12, M16, N1, N12, N14, P5, R4,
R5, R6, R11, R12, R16, T4, T5, T12, T15
4384V/B/C: B5, B12, D5, D12, E1, E15,
E16, F2, L12, M1, M2, M16, N12, R5,
R12, T4
4512V/B/C: None
1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with
the bank shown.
2. Internal GNDs and I/O GNDs (Bank 0/1) are connected inside package.
3. V
balls connect to two power planes within the package, one for V
and one for V
.
CCO1
CCO
CCO0
31
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections:
44-Pin TQFP
ispMACH 4032V/B/C
GLB/MC/Pad ORP
ispMACH 4064V/B/C
Pin Number
Bank Number
GLB/MC/Pad
ORP
-
1
2
3
4
5
6
7
8
-
TDI
A5
A6
A7
-
A^5
A^6
A^7
-
TDI
0
0
0
0
0
0
0
0
-
A10
A12
A14
A^5
A^6
A^7
-
GND (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
-
VCCO (Bank 0)
-
A8
A9
A10
A^8
A^9
A^10
-
B0
B2
B4
B^0
B^1
B^2
-
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
TCK
TCK
-
-
VCC
GND
A12
A13
A14
A15
CLK2/I
B0
B1
B2
B3
B4
TMS
B5
B6
-
-
VCC
GND
B8
B10
B12
B14
CLK2/I
C0
C2
C4
C6
C8
TMS
C10
C12
-
-
0
0
0
0
1
1
1
1
1
1
-
1
1
1
1
1
1
1
1
-
A^12
A^13
A^14
A^15
-
B^0
B^1
B^2
B^3
B^4
-
B^4
B^5
B^6
B^7
-
C^0
C^1
C^2
C^3
C^4
-
B^5
B^6
B^7
-
C^5
C^6
C^7
-
B7
C14
GND (Bank 1)
VCCO (Bank 1)
B8
GND (Bank 1)
VCCO (Bank 1)
D0
-
-
B^8
B^9
B^10
-
-
-
B^12
B^13
B^14
B^15
-
D^0
D^1
D^2
-
-
-
D^4
D^5
D^6
D^7
-
B9
B10
TDO
VCC
GND
B12
D2
D4
TDO
VCC
GND
D8
-
-
1
1
1
1
0
0
0
B13
B14
B15/GOE1
CLK0/I
A0/GOE0
A1
D10
D12
D14/GOE1
CLK0/I
A0/GOE0
A2
A^0
A^1
A^0
A^1
32
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections:
44-Pin TQFP (Cont.)
ispMACH 4032V/B/C
ispMACH 4064V/B/C
Pin Number
Bank Number
GLB/MC/Pad
ORP
A^2
A^3
A^4
GLB/MC/Pad
ORP
A^2
A^3
A^4
42
43
44
0
0
0
A2
A3
A4
A4
A6
A8
ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections:
48-Pin TQFP
ispMACH 4032V/B/C
GLB/MC/Pad ORP
ispMACH 4064V/B/C
Pin Number
Bank Number
GLB/MC/Pad
ORP
-
1
2
3
4
5
6
7
8
-
TDI
A5
A6
A7
-
A^5
A^6
A^7
-
TDI
0
0
0
0
0
0
0
0
0
-
A10
A12
A14
A^5
A^6
A^7
-
GND (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
-
VCCO (Bank 0)
-
A8
A9
A10
A11
A^8
A^9
A^10
A^11
-
B0
B2
B4
B6
B^0
B^1
B^2
B^3
-
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TCK
TCK
-
-
VCC
-
VCC
-
GND
-
GND
-
0
0
0
0
0
1
1
1
1
1
1
-
1
1
1
1
1
1
1
A12
A13
A14
A15
A^12
A^13
A^14
A^15
-
B8
B10
B12
B14
B^4
B^5
B^6
B^7
-
CLK1/I
CLK1/I
CLK2/I
-
CLK2/I
-
B0
B1
B2
B3
B4
TMS
B^0
B^1
B^2
B^3
B^4
-
C0
C2
C4
C6
C8
TMS
C^0
C^1
C^2
C^3
C^4
-
B5
B6
B^5
B^6
B^7
-
C10
C12
C14
C^5
C^6
C^7
-
B7
GND (Bank 1)
VCCO (Bank 1)
B8
GND (Bank 1)
VCCO (Bank 1)
D0
-
-
B^8
B^9
D^0
D^1
B9
D2
33
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections:
48-Pin TQFP (Cont.)
ispMACH 4032V/B/C
ispMACH 4064V/B/C
Pin Number
Bank Number
GLB/MC/Pad
ORP
B^10
B^11
-
-
-
B^12
B^13
B^14
B^15
-
GLB/MC/Pad
D4
ORP
D^2
D^3
-
-
-
D^4
D^5
D^6
D^7
-
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1
1
-
-
-
1
1
1
1
1
0
0
0
0
0
0
B10
B11
TDO
VCC
GND
B12
D6
TDO
VCC
GND
D8
B13
B14
D10
D12
B15/GOE1
CLK3/I
CLK0/I
A0/GOE0
A1
D14/GOE1
CLK3/I
CLK0/I
A0/GOE0
A2
-
-
A^0
A^1
A^2
A^3
A^4
A^0
A^1
A^2
A^3
A^4
A2
A3
A4
A4
A6
A8
ispMACH 4064V/B/C, 4128V/B/C, 4256V/B/C Logic Signal Connections:
100-Pin TQFP
ispMACH 4064V/B/C
ispMACH 4128V/B/C
ispMACH 4256V/B/C
Bank
Pin Number
Number
GLB/MC/Pad
ORP
-
GLB/MC/Pad
ORP
-
GLB/MC/Pad
ORP
-
1
2
-
GND
GND
GND
-
TDI
-
TDI
-
TDI
-
3
4
5
6
7
8
9
10
11
12*
13
14
15
16
17
18
19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A8
A9
A10
A11
A^8
A^9
A^10
A^11
-
A^12
A^13
A^14
A^15
-
B0
B2
B4
B6
B^0
B^2
B^4
B^6
-
B^8
B^10
B^12
B^13
-
C12
C10
C6
C2
C^6
C^5
C^3
C^1
-
D^6
D^5
D^3
D^2
-
GND (Bank 0)
GND (Bank 0)
GND (Bank 0)
A12
A13
A14
A15
B8
B10
B12
B13
D12
D10
D6
D4
I
VCCO (Bank 0)
B15
I
I
-
VCCO (Bank 0)
-
VCCO (Bank 0)
-
B^15
B^14
B^13
B^12
-
C14
C12
C10
C^14
C^12
C^10
C^8
-
E4
E6
E10
E^2
E^3
E^5
E^6
-
B14
B13
B12
C8
GND (Bank 0)
C6
E12
GND (Bank 0)
B11
GND (Bank 0)
F2
B^11
C^6
F^1
34
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4064V/B/C, 4128V/B/C, 4256V/B/C Logic Signal Connections:
100-Pin TQFP (Cont.)
ispMACH 4064V/B/C
ispMACH 4128V/B/C
ispMACH 4256V/B/C
Bank
Pin Number
20
Number
GLB/MC/Pad
ORP
B^10
B^9
B^8
-
GLB/MC/Pad
ORP
C^5
C^4
C^2
-
GLB/MC/Pad
ORP
F^3
F^5
F^6
-
0
0
0
0
-
B10
B9
B8
I
C5
C4
C2
I
F6
F10
F12
I
21
22
23*
24
TCK
-
TCK
-
TCK
-
25
-
VCC
-
VCC
-
VCC
-
26
-
GND
-
GND
-
GND
-
27*
28
29
30
31
32
33
34
35
36
37
38
39
0
0
0
0
0
0
0
0
0
0
0
0
1
-
I
-
I
-
I
-
B7
B6
B5
B4
B^7
B^6
B^5
B^4
-
D13
D12
D10
D8
D^13
D^12
D^10
D^8
-
G12
G10
G6
G2
G^6
G^5
G^3
G^1
-
GND (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
-
-
-
B3
B2
B1
B0
CLK1/I
CLK2/I
VCC
B^3
B^2
B^1
B^0
-
D6
D4
D2
D0
CLK1/I
CLK2/I
VCC
D^6
D^4
D^2
D^0
-
H12
H10
H6
H2
CLK1/I
CLK2/I
VCC
H^6
H^5
H^3
H^1
-
-
-
-
-
-
-
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
1
1
1
1
1
1
1
1
1
-
C0
C1
C2
C3
C^0
C^1
C^2
C^3
-
E0
E2
E4
E6
E^0
E^2
E^4
E^6
-
I2
I6
I10
I12
I^1
I^3
I^5
I^6
-
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
-
-
-
C4
C5
C6
C^4
C^5
C^6
C^7
-
E8
E10
E12
E^8
E^10
E^12
E^14
-
J2
J6
J10
J^1
J^3
J^5
J^6
-
C7
E14
J12
GND
TMS
C8
C9
C10
GND
TMS
F0
F2
F4
GND
TMS
K12
K10
K6
-
-
-
-
1
1
1
1
1
1
1
1
1
C^8
C^9
C^10
C^11
-
C^12
C^13
C^14
C^15
F^0
F^2
F^4
F^6
-
F^8
F^10
F^12
F^13
K^6
K^5
K^3
K^1
-
L^6
L^5
L^3
L^2
C11
GND (Bank 1)
C12
F6
K2
57
58
59
60
GND (Bank 1)
F8
GND (Bank 1)
L12
C13
C14
C15
F10
F12
F13
L10
L6
L4
61
35
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4064V/B/C, 4128V/B/C, 4256V/B/C Logic Signal Connections:
100-Pin TQFP (Cont.)
ispMACH 4064V/B/C
ispMACH 4128V/B/C
ispMACH 4256V/B/C
Bank
Pin Number
Number
GLB/MC/Pad
ORP
-
GLB/MC/Pad
ORP
-
GLB/MC/Pad
ORP
-
62*
63
64
65
66
67
68
69
70
71
72
73*
1
1
1
1
1
1
1
1
1
1
1
1
-
I
I
I
VCCO (Bank 1)
-
VCCO (Bank 1)
-
VCCO (Bank 1)
-
D15
D14
D13
D12
D^15
D^14
D^13
D^12
-
G14
G12
G10
G8
G^14
G^12
G^10
G^8
-
M4
M6
M10
M12
M^2
M^3
M^5
M^6
-
GND (Bank 1)
GND (Bank 1)
GND (Bank 1)
D11
D10
D9
D8
D^11
D^10
D^9
D^8
-
G6
G5
G4
G2
G^6
G^5
G^4
G^2
-
N2
N6
N10
N12
N^1
N^3
N^5
N^6
-
I
I
I
74
TDO
-
TDO
-
TDO
-
75
-
VCC
-
VCC
-
VCC
-
76
-
GND
-
GND
-
GND
-
77*
78
79
80
81
82
83
84
85
86
87
88
89
90
1
1
1
1
1
1
1
1
1
1
1
1
0
-
I
-
I
-
I
-
D7
D6
D5
D4
D^7
D^6
D^5
D^4
-
H13
H12
H10
H8
H^13
H^12
H^10
H^8
-
O12
O10
O6
O2
O^6
O^5
O^3
O^1
-
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
P12
-
-
-
D3
D2
D1
D^3
D^2
D^1
D^0
-
H6
H4
H2
H^6
H^4
H^2
H^0
-
P^6
P^5
P^3
P^1
-
P10
P6
P2/OE1
CLK3/I
CLK0/I
VCC
D0/GOE1
CLK3/I
CLK0/I
VCC
H0/GOE1
CLK3/I
CLK0/I
VCC
-
-
-
-
-
-
91
92
93
94
95
96
97
98
0
0
0
0
0
0
0
0
0
0
A0/GOE0
A^0
A^1
A^2
A^3
-
A0/GOE0
A2
A^0
A^2
A^4
A^6
-
A2/GOE0
A6
A^1
A^3
A^5
A^6
-
A1
A2
A3
A4
A6
A10
A12
VCCO (Bank 0)
GND (Bank 0)
B2
VCCO (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
A8
-
-
-
A4
A5
A6
A7
A^4
A^5
A^6
A^7
A^8
A^10
A^12
A^14
B^1
B^3
B^5
B^6
A10
A12
A14
B6
B10
B12
99
100
*This pin is input only.
36
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP
ispMACH 4128V/B/C
Pin Number
Bank Number
GLB/MC/Pad
ORP
-
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GND
2
3
4
5
6
7
8
9
TDI
-
-
VCCO (Bank 0)
B0
B1
B2
B4
B5
B6
B^0
B^1
B^2
B^4
B^5
B^6
-
B^8
B^9
B^10
B^12
B^13
B^14
-
C^14
C^13
C^12
C^10
C^9
C^8
-
C^6
C^5
C^4
C^2
C^0
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
GND (Bank 0)
B8
B9
B10
B12
B13
B14
VCCO (Bank 0)
C14
C13
C12
C10
C9
C8
GND (Bank 0)
C6
C5
C4
C2
C0
VCCO (Bank 0)
TCK
VCC
GND
D14
D13
D12
D10
D9
-
-
-
D^14
D^13
D^12
D^10
D^9
D^8
-
D8
GND (Bank 0)
VCCO (Bank 0)
D6
-
D^6
D^5
D5
37
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.)
ispMACH 4128V/B/C
Pin Number
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
Bank Number
GLB/MC/Pad
ORP
D^4
D^2
D^1
D^0
-
-
-
-
E^0
E^1
E^2
E^4
E^5
E^6
-
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D4
D2
D1
D0
CLK1/I
GND (Bank 1)
CLK2/I
VCC
E0
E1
E2
E4
E5
E6
VCCO (Bank 1)
GND (Bank 1)
-
E8
E9
E10
E12
E14
GND
TMS
E^8
E^9
E^10
E^12
E^14
-
-
-
VCCO (Bank 1)
F0
F1
F2
F4
F5
F6
F^0
F^1
F^2
F^4
F^5
F^6
-
F^8
F^9
F^10
F^12
F^13
F^14
-
GND (Bank 1)
F8
F9
F10
F12
F13
F14
VCCO (Bank 1)
G14
G^14
G^13
G^12
G^10
G^9
G13
G12
G10
G9
38
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.)
ispMACH 4128V/B/C
Pin Number
87
Bank Number
GLB/MC/Pad
ORP
G^8
-
G^6
G^5
G^4
G^2
G^0
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
G8
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
GND (Bank 1)
G6
G5
G4
G2
G0
VCCO (Bank 1)
TDO
VCC
GND
H14
H13
H12
H10
H9
-
-
-
H^14
H^13
H^12
H^10
H^9
H^8
-
H8
GND (Bank 1)
VCCO (Bank 1)
-
H6
H5
H4
H2
H^6
H^5
H^4
H^2
H^1
H^0
-
-
-
-
A^0
A^1
A^2
A^4
A^5
A^6
-
H1
H0/GOE1
CLK3/I
GND (Bank 0)
CLK0/I
VCC
A0/GOE0
A1
A2
A4
A5
A6
VCCO (Bank 0)
GND (Bank 0)
-
A8
A9
A10
A12
A14
A^8
A^9
A^10
A^12
A^14
39
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections:
176-Pin TQFP
ispMACH 4256V/B/C
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Bank
Pin Number
Number
GLB/MC/Pad
ORP
-
GLB/MC/Pad
ORP
-
GLB/MC/Pad
ORP
-
1
-
NC
NC
NC
2
-
GND
-
GND
-
GND
-
3
-
TDI
-
TDI
-
TDI
-
4
5
6
7
8
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
VCCO (Bank 0)
-
VCCO (Bank 0)
-
VCCO (Bank 0)
-
C14
C12
C10
C8
C6
C4
C2
C0
C^7
C^6
C^5
C^4
C^3
C^2
C^1
C^0
-
D^7
D^6
D^5
D^4
D^3
D^2
D^1
D^0
-
E^0
E^1
E^2
E^3
E^4
E^5
E^6
E^7
-
F^0
F^1
F^2
F^3
F^4
F^5
F^6
F^7
-
C14
C12
C10
C8
C6
C4
C2
C0
C^7
C^6
C^5
C^4
C^3
C^2
C^1
C^0
-
E^7
E^6
E^5
E^4
E^3
E^2
E^1
E^0
-
H^0
H^1
H^2
H^3
H^4
H^5
H^6
H^7
-
J^0
J^1
J^2
J^3
J^4
J^5
J^6
J^7
-
C14
C12
C10
C8
C6
C4
C2
C0
C^7
C^6
C^5
C^4
C^3
C^2
C^1
C^0
-
G^7
G^6
G^5
G^4
G^3
G^2
G^1
G^0
-
J^0
J^1
J^2
J^3
J^4
J^5
J^6
J^7
-
N^0
N^1
N^2
N^3
N^4
N^5
N^6
N^7
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
GND (Bank 0)
GND (Bank 0)
GND (Bank 0)
D14
D12
D10
D8
D6
D4
D2
D0
E14
E12
E10
E8
E6
E4
E2
E0
G14
G12
G10
G8
G6
G4
G2
G0
VCCO (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
E0
E2
E4
E6
E8
E10
E12
E14
H0
H2
H4
H6
H8
H10
H12
H14
J0
J2
J4
J6
J8
J10
J12
J14
GND (Bank 0)
GND (Bank 0)
GND (Bank 0)
F0
F2
F4
F6
F8
F10
F12
J0
J2
J4
J6
J8
J10
J12
N0
N2
N4
N6
N8
N10
N12
F14
J14
N14
VCCO (Bank 0)
TCK
VCCO (Bank 0)
TCK
VCCO (Bank 0)
TCK
-
-
-
40
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections:
176-Pin TQFP (Cont.)
ispMACH 4256V/B/C
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Bank
Pin Number
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
Number
GLB/MC/Pad
ORP
-
GLB/MC/Pad
ORP
-
GLB/MC/Pad
ORP
-
-
VCC
VCC
VCC
-
-
-
-
NC
NC
NC
-
-
-
-
NC
NC
NC
-
-
-
-
NC
NC
NC
-
-
-
-
GND (Bank 0)
GND (Bank 0)
GND (Bank 0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
G14
G12
G10
G8
G6
G4
G2
G0
G^7
G^6
G^5
G^4
G^3
G^2
G^1
G^0
-
K14
K12
K10
K8
K6
K4
K2
K0
K^7
K^6
K^5
K^4
K^3
K^2
K^1
K^0
-
O14
O12
O10
O8
O6
O4
O2
O^7
O^6
O^5
O^4
O^3
O^2
O^1
O^0
-
O0
GND (Bank 0)
VCCO (Bank 0)
P14
GND (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
-
-
-
H14
H12
H10
H8
H6
H4
H2
H0
H^7
H^6
H^5
H^4
H^3
H^2
H^1
H^0
-
-
-
-
-
I^0
I^1
I^2
I^3
I^4
I^5
I^6
I^7
-
L14
L12
L10
L8
L6
L4
L2
L0
L^7
L^6
L^5
L^4
L^3
L^2
L^1
L^0
-
-
-
-
-
M^0
M^1
M^2
M^3
M^4
M^5
M^6
M^7
-
P^7
P^6
P^5
P^4
P^3
P^2
P^1
P^0
-
-
-
-
-
AX^0
AX^1
AX^2
AX^3
AX^4
AX^5
AX^6
AX^7
-
P12
P10
P8
P6
P4
P2
P0
GND
GND
CLK1/I
GND (Bank 1)
GND
CLK1/I
GND (Bank 1)
0
1
1
-
CLK1/I
GND (Bank 1)
CLK2/I
VCC
CLK2/I
VCC
I0
I2
I4
I6
I8
I10
CLK2/I
VCC
M0
M2
M4
M6
M8
M10
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AX0
AX2
AX4
AX6
AX8
AX10
AX12
AX14
I12
I14
M12
M14
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
BX0
-
-
-
J0
J2
J4
J6
J^0
J^1
J^2
J^3
N0
N2
N4
N6
N^0
N^1
N^2
N^3
BX^0
BX^1
BX^2
BX^3
BX2
BX4
BX6
41
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections:
176-Pin TQFP (Cont.)
ispMACH 4256V/B/C
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Bank
Pin Number
84
Number
GLB/MC/Pad
ORP
J^4
J^5
J^6
J^7
-
GLB/MC/Pad
ORP
N^4
N^5
N^6
N^7
-
GLB/MC/Pad
ORP
BX^4
BX^5
BX^6
BX^7
-
1
1
1
1
-
J8
J10
N8
N10
BX8
BX10
BX12
BX14
VCC
85
86
87
88
J12
J14
N12
N14
VCC
VCC
89
-
NC
-
NC
-
NC
-
90
91
-
-
GND (Bank 1)
-
-
GND (Bank 1)
TMS
-
-
GND (Bank 1)
TMS
-
-
TMS
92
93
94
95
96
97
98
99
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VCCO (Bank 1)
-
VCCO (Bank 1)
O14
-
VCCO (Bank 1)
CX14
CX12
CX10
CX8
-
K14
K12
K10
K8
K6
K4
K2
K0
K^7
K^6
K^5
K^4
K^3
K^2
K^1
K^0
-
L^7
L^6
L^5
L^4
L^3
L^2
L^1
L^0
-
M^0
M^1
M^2
M^3
M^4
M^5
M^6
M^7
-
N^0
N^1
N^2
N^3
N^4
N^5
O^7
O^6
O^5
O^4
O^3
O^2
O^1
O^0
-
AX^7
AX^6
AX^5
AX^4
AX^3
AX^2
AX^1
AX^0
-
DX^0
DX^1
DX^2
DX^3
DX^4
DX^5
DX^6
DX^7
-
FX^0
FX^1
FX^2
FX^3
FX^4
FX^5
CX^7
CX^6
CX^5
CX^4
CX^3
CX^2
CX^1
CX^0
-
GX^7
GX^6
GX^5
GX^4
GX^3
GX^2
GX^1
GX^0
-
JX^0
JX^1
JX^2
JX^3
JX^4
JX^5
JX^6
JX^7
-
NX^0
NX^1
NX^2
NX^3
NX^4
NX^5
O12
O10
O8
O6
O4
O2
O0
CX6
CX4
CX2
CX0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
GND (Bank 1)
GND (Bank 1)
AX14
AX12
AX10
AX8
GND (Bank 1)
GX14
GX12
GX10
GX8
L14
L12
L10
L8
L6
L4
L2
L0
AX6
AX4
AX2
AX0
GX6
GX4
GX2
GX0
VCCO (Bank 1)
VCCO (Bank 1)
DX0
VCCO (Bank 1)
JX0
M0
M2
M4
M6
M8
M10
M12
M14
DX2
DX4
DX6
DX8
JX2
JX4
JX6
JX8
JX10
JX12
JX14
DX10
DX12
DX14
GND (Bank 1)
FX0
GND (Bank 1)
GND (Bank 1)
NX0
N0
N2
N4
N6
N8
FX2
FX4
FX6
FX8
NX2
NX4
NX6
NX8
N10
FX10
NX10
42
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections:
176-Pin TQFP (Cont.)
ispMACH 4256V/B/C
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Bank
Pin Number
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
Number
GLB/MC/Pad
ORP
N^6
N^7
-
GLB/MC/Pad
ORP
FX^6
FX^7
-
GLB/MC/Pad
ORP
NX^6
NX^7
-
1
1
1
-
N12
N14
VCCO (Bank 1)
FX12
FX14
VCCO (Bank 1)
TDO
NX12
NX14
VCCO (Bank 1)
TDO
TDO
-
-
-
-
-
-
-
VCC
NC
NC
NC
-
-
-
-
VCC
NC
NC
NC
-
-
-
-
VCC
NC
NC
NC
-
-
-
-
-
GND (Bank 1)
-
GND (Bank 1)
GX14
-
GND (Bank 1)
OX14
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
O14
O12
O10
O8
O6
O4
O2
O0
O^7
O^6
O^5
O^4
O^3
O^2
O^1
O^0
-
GX^7
GX^6
GX^5
GX^4
GX^3
GX^2
GX^1
GX^0
-
OX^7
OX^6
OX^5
OX^4
OX^3
OX^2
OX^1
OX^0
-
GX12
GX10
GX8
GX6
GX4
GX2
GX0
OX12
OX10
OX8
OX6
OX4
OX2
OX0
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
HX14
GND (Bank 1)
VCCO (Bank 1)
PX14
-
-
-
P14
P12
P10
P8
P^7
P^6
P^5
P^4
P^3
P^2
P^1
P^0
-
-
-
-
-
A^0
A^1
A^2
A^3
A^4
A^5
A^6
A^7
-
HX^7
HX^6
HX^5
HX^4
HX^3
HX^2
HX^1
HX^0
-
-
-
-
-
A^0
A^1
A^2
A^3
A^4
A^5
A^6
A^7
-
PX^7
PX^6
PX^5
PX^4
PX^3
PX^2
PX^1
PX^0
-
-
-
-
-
A^0
A^1
A^2
A^3
A^4
A^5
A^6
A^7
-
HX12
HX10
HX8
HX6
PX12
PX10
PX8
PX6
P6
P4
P2/GOE1
P0
HX4
HX2/GOE1
HX0
PX4
PX2/GOE1
PX0
GND
GND
GND
1
0
0
-
CLK3/I
GND (Bank 0)
CLK0/I
VCC
A0
A2/GOE0
A4
CLK3/I
GND (Bank 0)
CLK0/I
VCC
A0
A2/GOE0
A4
CLK3/I
GND (Bank 0)
CLK0/I
VCC
A0
A2//GOE0
A4
0
0
0
0
0
0
0
0
0
0
A6
A8
A10
A12
A6
A8
A10
A12
A6
A8
A10
A12
A14
A14
A14
VCCO (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
-
-
-
43
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C, Logic Signal Connections:
176-Pin TQFP (Cont.)
ispMACH 4256V/B/C
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Bank
Pin Number
168
Number
GLB/MC/Pad
ORP
B^0
B^1
B^2
B^3
B^4
B^5
B^6
B^7
-
GLB/MC/Pad
ORP
B^0
B^1
B^2
B^3
B^4
B^5
B^6
B^7
-
GLB/MC/Pad
ORP
B^0
B^1
B^2
B^3
B^4
B^5
B^6
B^7
-
0
0
0
0
0
0
0
0
-
B0
B2
B4
B0
B2
B4
B0
B2
B4
169
170
171
172
173
174
175
176
B6
B8
B6
B8
B6
B8
B10
B12
B14
VCC
B10
B12
B14
VCC
B10
B12
B14
VCC
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:
256-Ball fpBGA
ispMACH 4256V/B/C
ispMACH 4256V/B/C
128-I/O
160-I/O
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Ball
I/O
Number
Bank
GLB/MC/Pad
ORP
-
-
GLB/MC/Pad
ORP
-
-
GLB/MC/Pad
ORP
-
-
GLB/MC/Pad
ORP
-
-
-
-
-
-
-
-
VCC
GND
VCC
GND
GND
GND
C3
-
0
-
TDI
-
-
TDI
-
-
TDI
-
-
TDI
-
-
VCCO (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
B1
F5
D3
C1
C2
E3
D2
F6
D1
E2
E4
G5
E1
-
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C14
C12
C10
C8
C6
C4
C2
C0
NC
NC
NC
NC
NC
-
C^7
C^6
C^5
C^4
C^3
C^2
C^1
C^0
-
-
-
-
-
-
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
NC
NC
C^9
C^8
C^7
C^6
C^5
C^4
C^3
C^2
C^1
C^0
-
C14
C12
C10
C8
C6
C4
C2
C0
F6
F4
D6
D4
C^7
C^6
C^5
C^4
C^3
C^2
C^1
C^0
F^3
F^2
D^3
D^2
-
C14
C12
C10
C8
C6
C4
C1
C0
H0
H4
F4
F6
C^7
C^6
C^5
C^4
C^3
C^2
C^1
C^0
H^0
H^2
F^2
F^3
F^4
-
-
-
-
NC
NC
F8
VCCO (Bank 0)
VCCO (Bank 0)
-
VCCO (Bank 0)
-
-
GND (Bank 0)
-
GND (Bank 0)
-
GND (Bank 0)
-
GND (Bank 0)
-
F2
F1
G1
G6
G4
H6
0
0
0
0
0
0
NC
NC
NC
NC
NC
D14
-
-
-
-
-
NC
NC
NC
D9
D8
D7
-
-
-
NC
D2
D0
F2
F0
E14
-
F10
F12
F14
H8
H12
G14
F^5
F^6
F^7
H^4
H^6
G^7
D^1
D^0
F^1
F^0
E^7
D^9
D^8
D^7
D^7
44
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:
256-Ball fpBGA (Cont.)
ispMACH 4256V/B/C
ispMACH 4256V/B/C
128-I/O
160-I/O
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Ball
I/O
Number
Bank
GLB/MC/Pad
ORP
D^6
D^5
D^4
D^3
D^2
D^1
D^0
-
GLB/MC/Pad
ORP
D^6
D^5
D^4
D^3
D^2
D^1
D^0
-
GLB/MC/Pad
ORP
E^6
E^5
E^4
E^3
E^2
E^1
E^0
-
GLB/MC/Pad
ORP
G^6
G^5
G^4
G^3
G^2
G^1
G^0
-
G3
H5
G2
H1
H2
H3
H4
-
0
0
0
0
0
0
0
-
D12
D10
D8
D6
D4
D2
D0
D6
D5
D4
D3
D2
D1
D0
E12
E10
E8
E6
E4
E2
E0
G12
G10
G8
G6
G4
G2
G0
VCCO (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
-
-
-
-
GND (Bank 0)
-
GND (Bank 0)
-
GND (Bank 0)
-
J4
J3
J2
J1
K1
J5
K2
J6
K3
K4
L1
L2
M1
-
0
0
0
0
0
0
0
0
0
0
0
0
0
-
E0
E2
E4
E6
E8
E10
E12
E14
NC
NC
NC
NC
E^0
E^1
E^2
E^3
E^4
E^5
E^6
E^7
-
-
-
-
-
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
NC
NC
E^0
E^1
E^2
E^3
E^4
E^5
E^6
E^7
E^8
E^9
-
H0
H2
H4
H6
H8
H10
H12
H14
G0
G2
I14
I12
H^0
H^1
H^2
H^3
H^4
H^5
H^6
H^7
G^0
G^1
I^7
I^6
-
J0
J2
J4
J6
J8
J10
J12
J14
I0
I4
K0
K2
J^0
J^1
J^2
J^3
J^4
J^5
J^6
J^7
I^0
I^2
K^0
K^1
K^2
-
-
-
-
NC
NC
NC
K4
GND (Bank 0)
-
GND (Bank 0)
GND (Bank 0)
-
GND (Bank 0)
-
-
-
-
VCCO (Bank 0)
-
VCCO (Bank 0)
-
VCCO (Bank 0)
-
M2
N1
M3
M4
N2
K5
P1
K6
N3
L5
P2
L6
R1
-
0
0
0
0
0
0
0
0
0
0
0
0
0
-
NC
NC
NC
NC
NC
F0
F2
F4
F6
F8
F10
F12
F14
-
-
-
-
NC
NC
NC
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
-
-
-
NC
I10
I8
G4
G6
J0
J2
J4
J6
J8
J10
J12
J14
-
K6
K8
K10
I8
I12
N0
N2
N4
N6
N8
N10
N12
N14
K^3
K^4
K^5
I^4
I^6
N^0
N^1
N^2
N^3
N^4
N^5
N^6
N^7
-
I^5
I^4
G^2
G^3
J^0
J^1
J^2
J^3
J^4
J^5
J^6
J^7
-
F^0
F^1
F^2
F^3
F^4
F^5
F^6
F^7
F^8
F^9
-
-
F^0
F^1
F^2
F^3
F^4
F^5
F^6
F^7
-
VCCO (Bank 0)
TCK
VCCO (Bank 0)
TCK
VCCO (Bank 0)
TCK
VCCO (Bank 0)
TCK
P3
-
0
-
-
-
-
-
-
-
-
-
VCC
VCC
VCC
VCC
-
-
GND
-
GND
-
GND
-
GND
-
45
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:
256-Ball fpBGA (Cont.)
ispMACH 4256V/B/C
ispMACH 4256V/B/C
128-I/O
160-I/O
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Ball
I/O
Number
Bank
GLB/MC/Pad
ORP
-
-
GLB/MC/Pad
GND (Bank 0)
ORP
-
GLB/MC/Pad
GND (Bank 0)
ORP
-
GLB/MC/Pad
GND (Bank 0)
ORP
-
-
T2
M5
N4
T3
R3
M6
P4
L7
N5
M7
P5
R4
T4
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
0
0
-
NC
NC
G14
G12
G10
G8
G6
G4
G2
G0
NC
NC
G9
G8
G7
G6
G5
G4
G3
G2
G1
G0
NC
NC
G^9
G^8
G^7
G^6
G^5
G^4
G^3
G^2
G^1
G^0
-
-
-
-
-
-
-
-
H^9
H^8
H^7
H^6
H^5
H^4
H^3
H^2
H^1
H^0
-
-
-
-
-
I^0
I^1
I^2
I^3
I^4
I^5
I^6
I6
I4
K14
K12
K10
K8
K6
K4
K2
K0
G8
G10
I^3
I^2
K^7
K^6
K^5
K^4
K^3
K^2
K^1
K^0
G^4
G^5
-
K12
K14
O14
O12
O10
O8
O6
O4
O2
O0
M0
M4
K^6
K^7
O^7
O^6
O^5
O^4
O^3
O^2
O^1
O^0
M^0
M^2
L^0
-
-
G^7
G^6
G^5
G^4
G^3
G^2
G^1
G^0
-
-
-
-
-
NC
NC
NC
L0
GND (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
GND (Bank 0)
VCCO (Bank 0)
-
-
-
GND (Bank 0)
VCCO (Bank 0)
L4
-
-
R5
T5
R6
T6
N7
P7
R7
L8
T7
M8
N8
R8
P8
-
T8
-
N9
-
P9
R9
T9
T10
R10
M9
P10
NC
NC
NC
NC
NC
H14
H12
H10
H8
H6
H4
H2
-
-
-
-
NC
NC
NC
H9
H8
H7
H6
H5
H4
H3
H2
H1
NC
I2
I0
G12
G14
L14
L12
L10
L8
L6
L^2
L^4
L^6
M^4
M^6
P^7
P^6
P^5
P^4
P^3
P^2
P^1
P^0
-
I^1
I^0
G^6
G^7
L^7
L^6
L^5
L^4
L^3
L^2
L^1
L^0
-
L8
L12
M8
M12
P14
P12
P10
P8
P6
P4
P2
P0
-
H^7
H^6
H^5
H^4
H^3
H^2
H^1
H^0
-
-
-
-
-
I^0
I^1
I^2
I^3
I^4
I^5
I^6
L4
L2
L0
H0
GND
CLK1/I
GND (Bank 1)
H0
GND
CLK1/I
GND (Bank 1)
GND
CLK1/I
GND (Bank 1)
CLK2/I
VCC
M0
GND
CLK1/I
GND (Bank 1)
CLK2/I
VCC
AX0
0
-
1
-
1
1
1
1
1
1
1
-
-
-
-
-
-
-
-
CLK2/I
VCC
I0
I2
I4
I6
I8
I10
I12
CLK2/I
VCC
I0
I1
I2
I3
I4
I5
I6
M^0
M^1
M^2
M^3
M^4
M^5
M^6
AX^0
AX^1
AX^2
AX^3
AX^4
AX^5
AX^6
M2
M4
M6
M8
M10
M12
AX2
AX4
AX6
AX8
AX10
AX12
46
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:
256-Ball fpBGA (Cont.)
ispMACH 4256V/B/C
ispMACH 4256V/B/C
128-I/O
160-I/O
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Ball
I/O
Number
Bank
GLB/MC/Pad
ORP
I^7
-
-
-
-
-
-
GLB/MC/Pad
ORP
I^7
I^8
I^9
-
-
-
-
-
GLB/MC/Pad
ORP
M^7
BX^7
BX^6
P^0
P^1
-
-
-
-
BX^5
BX^4
N^0
N^1
N^2
N^3
N^4
N^5
N^6
N^7
P^2
P^3
-
GLB/MC/Pad
AX14
ORP
AX^7
DX^0
DX^2
EX^0
EX^2
EX^4
-
L9
N10
T11
R11
T12
N12
-
1
1
1
1
1
1
-
I14
NC
NC
NC
NC
NC
I7
I8
I9
NC
NC
NC
M14
BX14
BX12
P0
P2
NC
DX0
DX4
EX0
EX4
EX8
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
EX12
-
-
-
-
-
-
R12
T13
P12
M10
R13
L10
T14
M11
R14
P13
N13
M12
T15
-
1
1
1
1
1
1
1
1
1
1
1
1
1
-
NC
NC
NC
J0
J2
J4
J6
J8
J10
J12
J14
NC
NC
VCC
NC
J0
J1
J2
J3
J4
J5
J6
J7
J8
J9
NC
NC
VCC
-
NC
BX10
BX8
N0
N2
N4
N6
N8
N10
N12
N14
P4
P6
VCC
EX^6
DX^4
DX^6
BX^0
BX^1
BX^2
BX^3
BX^4
BX^5
BX^6
BX^7
FX^0
FX^1
-
J^0
J^1
J^2
J^3
J^4
J^5
J^6
J^7
J^8
J^9
-
DX8
DX12
BX0
BX2
BX4
BX6
BX8
BX10
BX12
BX14
FX0
FX2
-
J^0
J^1
J^2
J^3
J^4
J^5
J^6
J^7
-
-
-
-
-
VCC
-
-
GND
-
GND
-
GND
-
GND
-
-
-
1
-
-
-
-
-
-
-
-
GND (Bank 1)
TMS
VCCO (Bank 1)
-
-
-
-
-
-
GND (Bank 1)
TMS
VCCO (Bank 1)
-
-
-
-
GND (Bank 1)
TMS
VCCO (Bank 1)
FX4
-
-
-
P14
-
TMS
VCCO (Bank 1)
L12
R16
N14
P15
L11
P16
K11
M14
K12
N15
N16
M15
M13
-
1
1
1
1
1
1
1
1
1
1
1
1
1
-
NC
NC
NC
K14
K12
K10
K8
K6
K4
K2
K0
NC
NC
-
NC
NC
NC
K9
K8
K7
K6
K5
K4
K3
K2
K1
K0
NC
P8
P10
O14
O12
O10
O8
O6
O4
O2
O0
BX6
BX4
FX^2
FX^3
FX^4
CX^7
CX^6
CX^5
CX^4
CX^3
CX^2
CX^1
CX^0
HX^0
HX^2
-
P^4
P^5
O^7
O^6
O^5
O^4
O^3
O^2
O^1
O^0
BX^3
BX^2
-
FX6
FX8
CX14
CX12
CX10
CX8
CX6
CX4
CX2
CX0
HX0
HX4
K^7
K^6
K^5
K^4
K^3
K^2
K^1
K^0
-
K^9
K^8
K^7
K^6
K^5
K^4
K^3
K^2
K^1
K^0
-
-
-
-
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
-
-
GND (Bank 1)
-
-
-
47
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:
256-Ball fpBGA (Cont.)
ispMACH 4256V/B/C
ispMACH 4256V/B/C
128-I/O
160-I/O
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Ball
I/O
Number
Bank
GLB/MC/Pad
ORP
-
-
-
-
GLB/MC/Pad
ORP
-
-
GLB/MC/Pad
NC
ORP
-
P^6
GLB/MC/Pad
FX10
FX12
FX14
HX8
ORP
FX^5
FX^6
FX^7
HX^4
HX^6
GX^7
GX^6
GX^5
GX^4
GX^3
GX^2
GX^1
GX^0
-
M16
L15
L16
J11
K15
J12
K13
K14
K16
J16
J15
H16
J13
-
1
1
1
1
1
1
1
1
1
1
1
1
1
-
NC
NC
NC
NC
NC
L14
L12
L10
L8
L6
L4
L2
NC
NC
NC
L9
L8
L7
L6
L5
L4
L3
L2
L1
P12
P14
BX2
BX0
AX14
AX12
AX10
AX8
AX6
AX4
-
P^7
L^9
L^8
L^7
L^6
L^5
L^4
L^3
L^2
L^1
L^0
-
BX^1
BX^0
AX^7
AX^6
AX^5
AX^4
AX^3
AX^2
AX^1
AX^0
-
-
HX12
GX14
GX12
GX10
GX8
GX6
GX4
GX2
GX0
L^7
L^6
L^5
L^4
L^3
L^2
L^1
L^0
-
AX2
AX0
VCCO (Bank 1)
GND (Bank 1)
DX0
L0
L0
VCCO (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
JX0
-
-
-
M0
M2
M4
M6
-
-
-
-
J14
H15
H14
H13
G16
H12
G15
H11
F16
G13
G14
F15
E16
-
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
1
1
1
1
1
1
1
1
1
1
1
M^0
M^1
M^2
M^3
M^4
M^5
M^6
M^7
-
-
-
-
-
-
-
-
-
-
-
-
M0
M1
M2
M3
M4
M5
M6
M7
M8
M9
NC
NC
M^0
M^1
M^2
M^3
M^4
M^5
M^6
M^7
M^8
M^9
-
-
-
-
-
-
-
-
N^0
N^1
N^2
N^3
N^4
N^5
N^6
N^7
DX^0
DX^1
DX^2
DX^3
DX^4
DX^5
DX^6
DX^7
CX^0
CX^1
EX^7
EX^6
-
JX^0
JX^1
JX^2
JX^3
JX^4
JX^5
JX^6
JX^7
IX^0
IX^2
KX^0
KX^1
KX^2
-
DX2
DX4
DX6
DX8
DX10
DX12
DX14
CX0
JX2
JX4
JX6
JX8
JX10
JX12
JX14
IX0
IX4
KX0
KX2
KX4
M8
M10
M12
M14
NC
NC
NC
CX2
EX14
EX12
NC
NC
NC
NC
GND (Bank 1)
-
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
NC
-
-
-
GND (Bank 1)
VCCO (Bank 1)
KX6
-
-
E15
G12
E13
D16
E14
G11
D15
F11
C16
F12
D14
NC
NC
NC
NC
NC
N0
N2
N4
NC
NC
NC
N0
N1
N2
N3
N4
N5
N6
N7
KX^3
KX^4
KX^5
IX^4
IX^6
NX^0
NX^1
NX^2
NX^3
NX^4
NX^5
EX10
EX8
CX4
CX6
FX0
FX2
FX4
FX6
FX8
EX^5
EX^4
CX^2
CX^3
FX^0
FX^1
FX^2
FX^3
FX^4
FX^5
KX8
KX10
IX8
IX12
NX0
NX2
NX4
NX6
NX8
N^0
N^1
N^2
N^3
N^4
N^5
N6
N8
N10
FX10
NX10
48
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:
256-Ball fpBGA (Cont.)
ispMACH 4256V/B/C
ispMACH 4256V/B/C
128-I/O
160-I/O
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Ball
I/O
Number
Bank
GLB/MC/Pad
ORP
N^6
N^7
-
-
-
GLB/MC/Pad
ORP
N^8
N^9
-
-
-
GLB/MC/Pad
FX12
FX14
VCCO (Bank 1)
TDO
ORP
FX^6
FX^7
-
-
-
GLB/MC/Pad
NX12
NX14
VCCO (Bank 1)
TDO
ORP
NX^6
NX^7
-
-
-
C15
B16
-
C14
-
1
1
-
1
-
N12
N14
VCCO (Bank 1)
N8
N9
VCCO (Bank 1)
TDO
VCC
TDO
VCC
VCC
VCC
-
-
GND
-
GND
-
GND
-
GND
-
-
-
-
-
-
GND (Bank 1)
-
-
-
GND (Bank 1)
EX6
-
GND (Bank 1)
KX12
-
A15
B14
E12
A14
C13
D13
E11
B13
F10
C12
E10
A13
D12
-
1
1
1
1
1
1
1
1
1
1
1
1
1
-
NC
NC
O14
O12
O10
O8
O6
O4
O2
O0
NC
NC
NC
NC
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
EX^3
EX^2
GX^7
GX^6
GX^5
GX^4
GX^3
GX^2
GX^1
GX^0
CX^4
CX^5
-
KX^6
KX^7
OX^7
OX^6
OX^5
OX^4
OX^3
OX^2
OX^1
OX^0
MX^0
MX^2
LX^0
-
-
O^7
O^6
O^5
O^4
O^3
O^2
O^1
O^0
-
-
-
-
-
-
-
-
-
EX4
GX14
GX12
GX10
GX8
GX6
GX4
GX2
GX0
CX8
CX10
NC
KX14
OX14
OX12
OX10
OX8
OX6
OX4
OX2
OX0
MX0
MX4
LX0
O^9
O^8
O^7
O^6
O^5
O^4
O^3
O^2
O^1
O^0
-
NC
NC
GND (Bank 1)
VCCO (Bank 1)
GND (Bank 1)
VCCO (Bank 1)
-
-
-
-
GND (Bank 1)
VCCO (Bank 1)
NC
-
-
-
GND (Bank 1)
VCCO (Bank 1)
LX4
-
-
-
B12
A12
B11
A11
D10
C10
B10
A10
A9
F9
B9
E9
C9
-
1
1
1
1
1
1
1
1
1
1
1
1
1
-
NC
NC
NC
NC
NC
P14
P12
P10
P8
NC
NC
NC
P9
P8
P7
P6
P5
P4
LX^2
LX^4
LX^6
MX^4
MX^6
PX^7
PX^6
PX^5
PX^4
PX^3
PX^2
PX^1
PX^0
-
EX2
EX0
CX12
CX14
HX14
HX12
HX10
HX8
EX^1
EX^0
CX^6
CX^7
HX^7
HX^6
HX^5
HX^4
HX^3
HX^2
HX^1
HX^0
-
LX8
LX12
MX8
MX12
PX14
PX12
PX10
PX8
-
P^9
P^8
P^7
P6
P^5
P^4
P^3
P^2
P^1
P^0
-
P^7
P^6
P^5
P^4
P^3
P^2
P^1
P^0
-
-
-
-
-
P6
P4
P2/GOE1
P0
GND
CLK3/I
GND (Bank 0)
CLK0/I
VCC
A0
P3
P2
HX6
HX4
HX2/GOE1
HX0
PX6
PX4
PX2/GOE1
PX0
P1/GOE1
P0
GND
CLK3/I
GND (Bank 0)
CLK0/I
VCC
A0
GND
GND
D9
-
B8
-
D8
0
-
0
-
-
-
-
-
CLK3/I
GND (Bank 0)
CLK0/I
VCC
-
-
-
-
CLK3/I
GND (Bank 0)
CLK0/I
VCC
-
-
-
-
0
A^0
A^0
A0
A^0
A0
A^0
49
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:
256-Ball fpBGA (Cont.)
ispMACH 4256V/B/C
ispMACH 4256V/B/C
128-I/O
160-I/O
ispMACH 4384V/B/C
ispMACH 4512V/B/C
Ball
I/O
Number
Bank
GLB/MC/Pad
A2/GOE0
ORP
A^1
A^2
A^3
A^4
A^5
A^6
A^7
-
-
-
-
-
-
GLB/MC/Pad
A1/GOE0
ORP
A^1
A^2
A^3
A^4
A^5
A^6
A^7
A^8
A^9
-
GLB/MC/Pad
A2/GOE0
ORP
A^1
A^2
A^3
A^4
A^5
A^6
A^7
F^7
F^6
D^7
D^6
-
GLB/MC/Pad
A2/GOE0
ORP
A^1
A^2
A^3
A^4
A^5
A^6
A^7
D^0
D^2
E^0
E^2
E^4
-
C8
A8
A7
B7
E8
D7
F8
C7
A6
B6
A5
B5
-
0
0
0
0
0
0
0
0
0
0
0
0
-
A4
A6
A8
A10
A12
A14
NC
NC
A2
A3
A4
A5
A6
A7
A8
A9
A4
A6
A8
A10
A12
A14
F14
F12
A4
A6
A8
A10
A12
A14
D0
D4
NC
NC
NC
NC
NC
NC
D14
D12
NC
E0
E4
E8
-
-
-
VCCO (Bank 0)
VCCO (Bank 0)
VCCO (Bank 0)
-
VCCO (Bank 0)
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
GND (Bank 0)
-
-
-
GND (Bank 0)
-
-
GND (Bank 0)
-
-
GND (Bank 0)
-
D5
A4
E7
A3
F7
B4
C5
A2
E6
B3
C4
D4
E5
-
NC
NC
NC
B0
B2
B4
NC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
NC
NC
VCC
-
NC
F10
F8
B0
B2
B4
B6
B8
B10
B12
B14
D10
D8
E12
D8
D12
B0
B2
B4
B6
B8
B10
B12
B14
F0
F2
E^6
D^4
D^6
B^0
B^1
B^2
B^3
B^4
B^5
B^6
B^7
F^0
F^1
-
B^0
B^1
B^2
B^3
B^4
B^5
B^6
B^7
B^8
B^9
-
F^5
F^4
B^0
B^1
B^2
B^3
B^4
B^5
B^6
B^7
D^5
D^4
-
-
B^0
B^1
B^2
B^3
B^4
B^5
B^6
B^7
-
-
-
-
-
B6
B8
B10
B12
B14
NC
NC
VCC
-
-
-
-
-
VCC
GND
GND (Bank 0)
VCC
GND
GND (Bank 0)
-
-
-
-
-
-
-
-
-
-
50
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
Part Number Description
LC XXXX X – XX X XXX X X XX
Production Status
Device Family
Blank = Final production
ES = Engineering Samples
Device Number
4032 = 32 Macrocells
4064 = 64 Macrocells
4128 = 128 Macrocells
4256 = 256 Macrocells
4384 = 384 Macrocells
4512 = 512 Macrocells
Grade
C = Commercial
I = Industrial
I/O Designator
A = 128 I/Os
B = 160 I/Os
Supply Voltage
V = 3.3V
B = 2.5V
Pin/Ball Count
44 (1.0mm thickness)
48 (1.0mm thickness)
C = 1.8V
Speed
100
128
176
256
25 = 2.5ns
27 = 2.7ns
3 = 3.0ns
35 = 3.5ns
5 = 5.0ns
75 = 7.5ns
10 = 10.0ns
Package
T = TQFP
F = fpBGA
0212/ispm4K
Ordering Information
ispMACH 4000C Commercial Devices
Device
Part Number
LC4032C-25T48C
LC4032C-5T48C
LC4032C-75T48C
LC4032C-25T44C
LC4032C-5T44C
LC4032C-75T44C
LC4064C-25T100C
LC4064C-5T100C
LC4064C-75T100C
LC4064C-25T48C
LC4064C-5T48C
LC4064C-75T48C
LC4064C-25T44C
LC4064C-5T44C
LC4064C-75T44C
Macrocells Voltage
t
Package Pin/Ball Count
I/O
32
32
32
30
30
30
64
64
64
32
32
32
30
30
30
Grade
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
PD
32
32
32
32
32
32
64
64
64
64
64
64
64
64
64
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
2.5
5
7.5
2.5
5
7.5
2.5
5
7.5
2.5
5
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
48
48
48
44
44
LC4032C
44
100
100
100
48
48
48
44
44
44
LC4064C
7.5
2.5
5
7.5
51
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000C Commercial Devices (Cont.)
Device
Part Number
Macrocells Voltage
t
Package Pin/Ball Count
I/O
92
92
92
64
Grade
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
PD
LC4128C-27T128C
LC4128C-5T128C
LC4128C-75T128C
LC4128C-27T100C
LC4128C-5T100C
LC4128C-75T100C
LC4256C-3F256AC
LC4256C-5F256AC
LC4256C-75F256AC
LC4256C-3F256BC
LC4256C-5F256BC
LC4256C-75F256BC
LC4256C-3T176C
LC4256C-5T176C
LC4256C-75T176C
LC4256C-3T100C
LC4256C-5T100C
LC4256C-75T100C
LC4384C-35F256C
LC4384C-5F256C
LC4384C-75F256C
LC4384C-35T176C
LC4384C-5T176C
LC4384C-75T176C
LC4512C-35F256C
LC4512C-5F256C
LC4512C-75F256C
LC4512C-35T176C
LC4512C-5T176C
LC4512C-75T176C
128
128
128
128
128
128
256
256
256
256
256
256
256
256
256
256
256
256
384
384
384
384
384
384
512
512
512
512
512
512
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
2.7
5
7.5
2.7
5
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
128
128
128
100
100
100
256
256
256
256
256
256
176
176
176
100
100
100
256
256
256
176
176
176
256
256
256
176
176
176
LC4128C
64
64
7.5
3
128
128
128
160
160
160
128
128
128
64
5
7.5
3
5
7.5
3
LC4256C
5
7.5
3
5
64
64
7.5
3.5
5
7.5
3.5
5
7.5
3.5
5
7.5
3.5
5
192
192
192
128
128
128
208
208
208
128
128
128
LC4384C
LC4512C
7.5
ispMACH 4000B Commercial Devices
Device
Part Number
LC4032B-25T48C
LC4032B-5T48C
LC4032B-75T48C
LC4032B-25T44C
LC4032B-5T44C
LC4032B-75T44C
Macrocells Voltage
t
Package Pin/Ball Count
I/O
32
32
32
30
30
30
Grade
PD
32
32
32
32
32
32
2.5
2.5
2.5
2.5
2.5
2.5
2.5
5
7.5
2.5
5
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
48
48
48
44
44
44
C
C
C
C
C
C
LC4032B
7.5
52
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000B Commercial Devices (Cont.)
Device
Part Number
Macrocells Voltage
t
Package Pin/Ball Count
I/O
64
64
64
32
32
32
30
30
30
92
92
92
64
64
64
128
128
128
160
160
160
128
128
128
64
Grade
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
PD
LC4064B-25T100C
LC4064B-5T100C
LC4064B-75T100C
LC4064B-25T48C
LC4064B-5T48C
LC4064B-75T48C
LC4064B-25T44C
LC4064B-5T44C
64
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
5
7.5
2.5
5
7.5
2.5
5
7.5
2.7
5
7.5
2.7
5
7.5
3
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
100
100
100
48
48
48
44
44
44
64
64
64
64
64
64
64
64
LC4064B
LC4064B-75T44C
LC4128B-27T128C
LC4128B-5T128C
LC4128B-75T128C
LC4128B-27T100C
LC4128B-5T100C
LC4128B-75T100C
LC4256B-3F256AC
LC4256B-5F256AC
LC4256B-75F256AC
LC4256B-3F256BC
LC4256B-5F256BC
LC4256B-75F256BC
LC4256B-3T176C
LC4256B-5T176C
LC4256B-75T176C
LC4256B-3T100C
LC4256B-5T100C
LC4256B-75T100C
LC4384B-35F256C
LC4384B-5F256C
LC4384B-75F256C
LC4384B-35T176C
LC4384B-5T176C
LC4384B-75T176C
LC4512B-35F256C
LC4512B-5F256C
LC4512B-75F256C
LC4512B-35T176C
LC4512B-5T176C
LC4512B-75T176C
128
128
128
128
128
128
256
256
256
256
256
256
256
256
256
256
256
256
384
384
384
384
384
384
512
512
512
512
512
512
128
128
128
100
100
100
256
256
256
256
256
256
176
176
176
100
100
100
256
256
256
176
176
176
256
256
256
176
176
176
LC4128B
5
7.5
3
5
7.5
3
LC4256B
5
7.5
3
5
64
64
7.5
3.5
5
7.5
3.5
5
7.5
3.5
5
7.5
3.5
5
192
192
192
128
128
128
208
208
208
128
128
128
LC4384B
LC4512B
7.5
53
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V Commercial Devices
Device
Part Number
LC4032V-25T48C
LC4032V-5T48C
Macrocells Voltage
t
Package Pin/Ball Count
I/O
32
32
32
30
30
30
64
64
64
32
32
32
30
30
30
92
Grade
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
PD
32
32
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
2.5
5
7.5
2.5
5
7.5
2.5
5
7.5
2.5
5
7.5
2.5
5
7.5
2.7
5
7.5
2.7
5
7.5
3
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
48
48
48
44
44
LC4032V-75T48C
LC4032V-25T44C
LC4032V-5T44C
LC4032V-75T44C
LC4064V-25T100C
LC4064V-5T100C
LC4064V-75T100C
LC4064V-25T48C
LC4064V-5T48C
32
32
32
32
64
64
64
64
64
64
64
64
LC4032V
44
100
100
100
48
48
48
44
44
44
LC4064V
LC4128V
LC4064V-75T48C
LC4064V-25T44C
LC4064V-5T44C
LC4064V-75T44C
LC4128V-27T128C
LC4128V-5T128C
LC4128V-75T128C
LC4128V-27T100C
LC4128V-5T100C
LC4128V-75T100C
LC4256V-3F256AC
LC4256V-5F256AC
LC4256V-75F256AC
LC4256V-3F256BC
LC4256V-5F256BC
LC4256V-75F256BC
LC4256V-3T176C
LC4256V-5T176C
LC4256V-75T176C
LC4256V-3T100C
LC4256V-5T100C
LC4256V-75T100C
LC4384V-35F256C
LC4384V-5F256C
LC4384V-75F256C
LC4384V-35T176C
LC4384V-5T176C
LC4384V-75T176C
64
128
128
128
128
128
128
256
256
256
256
256
256
256
256
256
256
256
256
384
384
384
384
384
384
128
128
128
100
100
100
256
256
256
256
256
256
176
176
176
100
100
100
256
256
256
176
176
176
92
92
64
64
64
128
128
128
160
160
160
128
128
128
64
5
7.5
3
5
7.5
3
LC4256V
5
7.5
3
5
64
64
7.5
3.5
5
7.5
3.5
5
192
192
192
128
128
128
LC4384V
7.5
54
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V Commercial Devices (Cont.)
Device
Part Number
Macrocells Voltage
t
Package Pin/Ball Count
I/O
208
208
208
128
128
128
Grade
PD
LC4512V-35F256C
LC4512V-5F256C
LC4512V-75F256C
LC4512V-35T176C
LC4512V-5T176C
LC4512V-75T176C
512
512
512
512
512
512
3.3
3.3
3.3
3.3
3.3
3.3
3.5
5
7.5
3.5
5
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
256
256
256
176
176
176
C
C
C
C
C
C
LC4512V
7.5
Note: The ispMACH 4000V/B/C family is dual-marked with both commercial and industrial grades. The commercial speed grade is one speed
grade faster (i.e. LC4128C-5T100C) than the industrial speed grade (i.e. LC4128C-75T100I).
ispMACH 4000C Industrial Devices
Family
Part Number
LC4032C-5T48I
Macrocells Voltage
t
Package Pin/Ball Count
I/O
32
32
32
30
30
30
64
64
64
32
32
32
30
30
30
92
92
92
64
64
64
Grade
PD
32
32
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
48
48
48
44
44
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LC4032C-75T48I
LC4032C-10T48I
LC4032C-5T44I
LC4032C-75T44I
LC4032C-10T44I
LC4064C-5T100I
LC4064C-75T100I
LC4064C-10T100I
LC4064C-5T48I
LC4064C-75T48I
LC4064C-10T48I
LC4064C-5T44I
LC4064C-75T44I
LC4064C-10T44I
LC4128C-5T128I
LC4128C-75T128I
LC4128C-10T128I
LC4128C-5T100I
LC4128C-75T100I
LC4128C-10T100I
32
32
32
32
LC4032C
44
64
64
64
64
100
100
100
48
48
48
44
44
44
128
128
128
100
100
100
LC4064C
LC4128C
64
64
64
64
64
128
128
128
128
128
128
7.5
10
55
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000C Industrial Devices (Cont.)
Family
Part Number
Macrocells Voltage
t
Package Pin/Ball Count
I/O
128
128
128
160
160
160
128
128
128
64
Grade
PD
LC4256C-5F256AI
LC4256C-75F256AI
LC4256C-10F256AI
LC4256C-5F256BI
LC4256C-75F256BI
LC4256C-10F256BI
LC4256C-5T176I
LC4256C-75T176I
LC4256C-10T176I
LC4256C-5T100I
LC4256C-75T100I
LC4256C-10T100I
LC4384C-5F256I
LC4384C-75F256I
LC4384C-10F256I
LC4384C-5T176I
LC4384C-75T176I
LC4384C-10T176I
LC4512C-5F256I
LC4512C-75F256I
LC4512C-10F256I
LC4512C-5T176I
LC4512C-75T176I
LC4512C-10T176I
256
256
256
256
256
256
256
256
256
256
256
256
384
384
384
384
384
384
512
512
512
512
512
512
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
256
256
256
256
256
256
176
176
176
100
100
100
256
256
256
176
176
176
256
256
256
176
176
176
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LC4256C
64
64
192
192
192
128
128
128
208
208
208
128
128
128
LC4384C
LC4512C
ispMACH 4000B Industrial Devices
Family
Part Number
LC4032B-5T48I
LC4032B-75T48I
LC4032B-10T48I
LC4032B-5T44I
LC4032B-75T44I
LC4032B-10T44I
LC4064B-5T100I
LC4064B-75T100I
LC4064B-10T100I
LC4064B-5T48I
LC4064B-75T48I
LC4064B-10T48I
LC4064B-5T44I
LC4064B-75T44I
LC4064B-10T44I
Macrocells Voltage
t
Package Pin/Ball Count
I/O
32
32
32
30
30
30
64
64
64
32
32
32
30
30
30
Grade
PD
32
32
32
32
32
32
64
64
64
64
64
64
64
64
64
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
48
48
48
44
44
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LC4032B
44
100
100
100
48
48
48
44
44
44
LC4064B
7.5
10
56
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000B Industrial Devices (Cont.)
Family
Part Number
Macrocells Voltage
t
Package Pin/Ball Count
I/O
92
92
92
64
Grade
PD
LC4128B-5T128I
LC4128B-75T128I
LC4128B-10T128I
LC4128B-5T100I
LC4128B-75T100I
LC4128B-10T100I
LC4256B-5F256AI
LC4256B-75F256AI
LC4256B-10F256AI
LC4256B-5F256BI
LC4256B-75F256BI
LC4256B-10F256BI
LC4256B-5T176I
LC4256B-75T176I
LC4256B-10T176I
LC4256B-5T100I
LC4256B-75T100I
LC4256B-10T100I
LC4384B-5F256I
LC4384B-75F256I
LC4384B-10F256I
LC4384B-5T176I
LC4384B-75T176I
LC4384B-10T176I
LC4512B-5F256I
LC4512B-75F256I
LC4512B-10F256I
LC4512B-5T176I
LC4512B-75T176I
LC4512B-10T176I
128
128
128
128
128
128
256
256
256
256
256
256
256
256
256
256
256
256
384
384
384
384
384
384
512
512
512
512
512
512
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
128
128
128
100
100
100
256
256
256
256
256
256
176
176
176
100
100
100
256
256
256
176
176
176
256
256
256
176
176
176
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LC4128B
64
64
128
128
128
160
160
160
128
128
128
64
LC4256B
64
64
192
192
192
128
128
128
208
208
208
128
128
128
LC4384B
LC4512B
7.5
10
5
7.5
10
ispMACH 4000V Industrial Devices
Family
Part Number
LC4032V-5T48I
LC4032V-75T48I
LC4032V-10T48I
LC4032V-5T44I
LC4032V-75T44I
LC4032V-10T44I
Macrocells Voltage
t
Package Pin/Ball Count
I/O
32
32
32
30
30
30
Grade
PD
5
32
32
32
32
32
32
3.3
3.3
3.3
3.3
3.3
3.3
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
48
48
48
44
44
44
I
I
I
I
I
I
7.5
10
5
7.5
10
LC4032V
57
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
ispMACH 4000V Industrial Devices (Cont.)
Family
Part Number
Macrocells Voltage
t
Package Pin/Ball Count
I/O
64
64
64
32
32
32
30
30
30
92
92
92
64
64
64
128
128
128
160
160
160
128
128
128
64
Grade
PD
LC4064V-5T100I
LC4064V-75T100I
LC4064V-10T100I
LC4064V-5T48I
LC4064V-75T48I
LC4064V-10T48I
LC4064V-5T44I
64
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
7.5
10
5
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
fpBGA
fpBGA
fpBGA
TQFP
TQFP
TQFP
100
100
100
48
48
48
44
44
44
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
64
64
64
64
64
64
64
64
LC4064V
LC4064V-75T44I
LC4064V-10T44I
LC4128V-5T128I
LC4128V-75T128I
LC4128V-10T128I
LC4128V-5T100I
LC4128V-75T100I
LC4128V-10T100I
LC4256V-5F256AI
LC4256V-75F256AI
LC4256V-10F256AI
LC4256V-5F256BI
LC4256V-75F256BI
LC4256V-10F256BI
LC4256V-5T176I
LC4256V-75T176I
LC4256V-10T176I
LC4256V-5T100I
LC4256V-75T100I
LC4256V-10T100I
LC4384V-5F256I
LC4384V-75F256I
LC4384V-10F256I
LC4384V-5T176I
LC4384V-75T176I
LC4384V-10T176I
LC4512V-5F256I
LC4512V-75F256I
LC4512V-10F256I
LC4512V-5T176I
LC4512V-75T176I
LC4512V-10T176I
128
128
128
128
128
128
256
256
256
256
256
256
256
256
256
256
256
256
384
384
384
384
384
384
512
512
512
512
512
512
128
128
128
100
100
100
256
256
256
256
256
256
176
176
176
100
100
100
256
256
256
176
176
176
256
256
256
176
176
176
LC4128V
LC4256V
64
64
192
192
192
128
128
128
208
208
208
128
128
128
LC4384V
LC4512V
7.5
10
Note: The ispMACH 4000V/B/C family is dual-marked with both commercial and industrial grades. The commercial speed grade is one speed
grade faster (i.e. LC4128C-5T100C) than the industrial speed grade (i.e. LC4128C-75T100I).
58
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
For Further Information
In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH
4000V/B/C family:
• ispMACH 4000 Timing Model Design and Usage Guidelines (TN1004)
• ispMACH 4000V/B/C Power Consumption (TN1005)
59
相关型号:
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