LC4256ZC-45T100C_技术文档

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 1. Functional Block Diagram

I/O

Block

I/O

Block

16

36

16

36

Generic

Logic

Block

Generic

Logic

Block

ORP

16

I/O

Block

I/O

Block

16

36

16

36

Generic

Logic

Block

Generic

Logic

Block

ORP 16

16

ORP

The I/Os in the ispMACH 4000 are split into two banks. Each bank has a separate I/O power supply. Inputs can

support a variety of standards independent of the chip or bank power supply. Outputs support the standards com-

patible with the power supply provided to the bank. Support for a variety of standards helps designers implement

designs in mixed voltage environments. In addition, 5V tolerant inputs are speciﬁed within an I/O bank that is con-

nected to V

of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI interfaces.

CCO

ispMACH 4000 Architecture

There are a total of two GLBs in the ispMACH 4032, increasing to 32 GLBs in the ispMACH 4512. Each GLB has

36 inputs. All GLB inputs come from the GRP and all outputs from the GLB are brought back into the GRP to be

connected to the inputs of any other GLB on the device. Even if feedback signals return to the same GLB, they still

must go through the GRP. This mechanism ensures that GLBs communicate with each other with consistent and

predictable delays. The outputs from the GLB are also sent to the ORP. The ORP then sends them to the associ-

ated I/O cells in the I/O block.

Generic Logic Block

The ispMACH 4000 GLB consists of a programmable AND array, logic allocator, 16 macrocells and a GLB clock

generator. Macrocells are decoupled from the product terms through the logic allocator and the I/O pins are decou-

pled from macrocells through the ORP. Figure 2 illustrates the GLB.

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Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 2. Generic Logic Block

To GRP

Clock

Generator

1+OE

36 Inputs

from GRP

To

Product Term

Output Enable

Sharing

AND Array

The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are

used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-

nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic

allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and

Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being

fed to the macrocells.

Every set of ﬁve product terms from the 80 logic product terms forms a product term cluster starting with PT0.

There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND

Array.

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Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 3. AND Array

In[0]

In[34]

In[35]

PT0

PT1

PT2

PT3

PT4

Cluster 0

PT75

PT76

PT77

PT78

PT79

Cluster 15

PT80 Shared PT Clock

PT81 Shared PT Initialization

PT82 Shared PTOE

Note:

Indicates programmable fuse.

Enhanced Logic Allocator

Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term

cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms.

The software automatically considers the availability and distribution of product term clusters as it ﬁts the functions

within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed

Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for

increased performance.

The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:

• Product Term Allocator

• Cluster Allocator

• Wide Steering Logic

Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.

Figure 4. Macrocell Slice

to to

n-1 n-2

from from

n-1 n-4

Fast 5-PT

Path

From

n-4

1-80

PTs

5-PT

n

To XOR (MC)

Cluster

to

n+1

from

n+2

from

n+1

To n+4

Individual Product

Term Allocator

Cluster

Allocator

SuperWIDE™

Steering Logic

5

Lattice Semiconductor

Product Term Allocator

ispMACH 4000V/B/C/Z Family Data Sheet

The product term allocator assigns product terms from a cluster to either logic or control applications as required

by the design being implemented. Product terms that are used as logic are steered into a 5-input OR gate associ-

ated with the cluster. Product terms that used for control are steered either to the macrocell or I/O cell associated

with the cluster. Table 3 shows the available functions for each of the ﬁve product terms in the cluster. The OR gate

output connects to the associated I/O cell, providing a fast path for narrow combinatorial functions, and to the logic

allocator.

Table 3. Individual PT Steering

Product Term

PTn

Logic

Control

Logic PT

Single PT for XOR/OR

Individual Clock (PT Clock)

PTn+1

PTn+2

PTn+3

PTn+4

Individual Initialization or Individual Clock Enable (PT Initialization/CE)

Individual Initialization (PT Initialization)

Individual OE (PTOE)

Cluster Allocator

The cluster allocator allows clusters to be steered to neighboring macrocells, thus allowing the creation of functions

with more product terms. Table 4 shows which clusters can be steered to which macrocells. Used in this manner,

the cluster allocator can be used to form functions of up to 20 product terms. Additionally, the cluster allocator

accepts inputs from the wide steering logic. Using these inputs, functions up to 80 product terms can be created.

Table 4. Available Clusters for Each Macrocell

Macrocell

M0

Available Clusters

—

C0

C1

C2

C3

M1

M2

C1

C2

C3

C4

M3

C2

C3

C4

C5

M4

C3

C4

C5

C6

M5

C4

C5

C6

C7

M6

C5

C6

C7

C8

M7

C6

C7

C8

C9

M8

M9

C7

C8

C9

C10

C11

C12

C13

C14

C8

C9

C10

C11

C12

C13

C14

C15

—

C10

C11

C12

C13

C14

C15

—

M10

M11

M12

M13

M14

M15

C10

C11

C12

C13

C14

C15

—

Wide Steering Logic

The wide steering logic allows the output of the cluster allocator n to be connected to the input of the cluster alloca-

tor n+4. Thus, cluster chains can be formed with up to 80 product terms, supporting wide product term functions

and allowing performance to be increased through a single GLB implementation. Table 5 shows the product term

chains.

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Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Table 5. Product Term Expansion Capability

Expansion

Chains

Macrocells Associated with Expansion Chain

(with Wrap Around)

Max PT/

Macrocell

Chain-0

Chain-1

Chain-2

Chain-3

M0 → M4 → M8 → M12 → M0

M1 → M5 → M9 → M13 → M1

M2 → M6 → M10 → M14 → M2

M3 → M7 → M11 → M15 → M3

75

80

75

70

Every time the super cluster allocator is used, there is an incremental delay of t

. When the super cluster alloca-

EXP

tor is used, all destinations other than the one being steered to, are given the value of ground (i.e., if the super clus-

ter is steered to M (n+4), then M (n) is ground).

Macrocell

The 16 macrocells in the GLB are driven by the 16 outputs from the logic allocator. Each macrocell contains a pro-

grammable XOR gate, a programmable register/latch, along with routing for the logic and control functions.

Figure 5 shows a graphical representation of the macrocell. The macrocells feed the ORP and GRP. A direct input

from the I/O cell allows designers to use the macrocell to construct high-speed input registers. A programmable

delay in this path allows designers to choose between the fastest possible set-up time and zero hold time.

Figure 5. Macrocell

Power-up

Initialization

Shared PT Initialization

PT Initialization (optional)

PT Initialization/CE (optional)

Delay

From I/O Cell

R

P

From Logic Allocator

To ORP

To GRP

D/T/L

Q

CE

Block CLK0

Block CLK1

Block CLK2

Block CLK3

Single PT

PT Clock (optional)

Shared PT Clock

Enhanced Clock Multiplexer

The clock input to the ﬂip-ﬂop can select any of the four block clocks along with the shared PT clock, and true and

complement forms of the optional individual term clock. An 8:1 multiplexer structure is used to select the clock. The

eight sources for the clock multiplexer are as follows:

• Block CLK0

• Block CLK1

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Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

• Block CLK2

• Block CLK3

• PT Clock

• PT Clock Inverted

• Shared PT Clock

• Ground

Clock Enable Multiplexer

Each macrocell has a 4:1 clock enable multiplexer. This allows the clock enable signal to be selected from the fol-

lowing four sources:

• PT Initialization/CE

• PT Initialization/CE Inverted

• Shared PT Clock

• Logic High

Initialization Control

The ispMACH 4000 family architecture accommodates both block-level and macrocell-level set and reset capability.

There is one block-level initialization term that is distributed to all macrocell registers in a GLB. At the macrocell

level, two product terms can be “stolen” from the cluster associated with a macrocell to be used for set/reset func-

tionality. A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing

ﬂexibility.

Note that the reset/preset swapping selection feature affects power-up reset as well. All ﬂip-ﬂops power up to a

known state for predictable system initialization. If a macrocell is conﬁgured to SET on a signal from the block-level

initialization, then that macrocell will be SET during device power-up. If a macrocell is conﬁgured to RESET on a

signal from the block-level initialization or is not conﬁgured for set/reset, then that macrocell will RESET on power-

up. To guarantee initialization values, the V rise must be monotonic, and the clock must be inactive until the reset

CC

delay time has elapsed.

GLB Clock Generator

Each ispMACH 4000 device has up to four clock pins that are also routed to the GRP to be used as inputs. These

pins drive a clock generator in each GLB, as shown in Figure 6.The clock generator provides four clock signals that

can be used anywhere in the GLB. These four GLB clock signals can consist of a number of combinations of the

true and complement edges of the global clock signals.

Figure 6. GLB Clock Generator

CLK0

Block CLK0

CLK1

Block CLK1

CLK2

Block CLK2

CLK3

Block CLK3

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Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Output Routing Pool (ORP)

The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.

This provides greater ﬂexibility in determining the pinout and allows design changes to occur without affecting the

pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This

allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-

put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the

output routing multipliers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists of

the following elements:

• Output Routing Multiplexers

• OE Routing Multiplexers

• Output Routing Pool Bypass Multiplexers

Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each

ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.

Figure 7. ORP Slice

OE Routing Multiplexer

From PTOE

To I/O

Cell

OE

ORP

Bypass

Multiplexer

5-PT Fast Path

From Macrocell

To I/O

Cell

Output

Output Routing Multiplexer

Output Routing Multiplexers

The details of connections between the macrocells and the I/O cells vary across devices and within a device

dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details.

Table 6. ORP Combinations for I/O Blocks with 8 I/Os

I/O Cell

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

Available Macrocells

M0, M1, M2, M3, M4, M5, M6, M7

M2, M3, M4, M5, M6, M7, M8, M9

M4, M5, M6, M7, M8, M9, M10, M11

M6, M7, M8, M9, M10, M11, M12, M13

M8, M9, M10, M11, M12, M13, M14, M15

M10, M11, M12, M13, M14, M15, M0, M1

M12, M13, M14, M15, M0, M1, M2, M3

M14, M15, M0, M1, M2, M3, M4, M5

9

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Table 7. ORP Combinations for I/O Blocks with 16 I/Os

I/O Cell

Available Macrocells

I/O 0

I/O 1

M0, M1, M2, M3, M4, M5, M6, M7

M1, M2, M3, M4, M5, M6, M7, M8

I/O 2

M2, M3, M4, M5, M6, M7, M8, M9

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

M3, M4, M5, M6, M7, M8, M9, M10

M4, M5, M6, M7, M8, M9, M10, M11

M5, M6, M7, M8, M9, M10, M11, M12

M6, M7, M8, M9, M10, M11, M12, M13

M7, M8, M9, M10, M11, M12, M13, M14

M8, M9, M10, M11, M12, M13, M14, M15

M9, M10, M11, M12, M13, M14, M15, M0

M10, M11, M12, M13, M14, M15, M0, M1

M11, M12, M13, M14, M15, M0, M1, M2

M12, M13, M14, M15, M0, M1, M2, M3

M13, M14, M15, M0, M1, M2, M3, M4

M14, M15, M0, M1, M2, M3, M4, M5

M15, M0, M1, M2, M3, M4, M5, M6

Table 8. ORP Combinations for I/O Blocks with 4 I/Os

I/O Cell

Available Macrocells

I/O 0

I/O 1

I/O 2

I/O 3

M0, M1, M2, M3, M4, M5, M6, M7

M4, M5, M6, M7, M8, M9, M10, M11

M8, M9, M10, M11, M12, M13, M14, M15

M12, M13, M14, M15, M0, M1, M2, M3

Table 9. ORP Combinations for I/O Blocks with 10 I/Os

I/O Cell

Available Macrocells

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

M0, M1, M2, M3, M4, M5, M6, M7

M2, M3, M4, M5, M6, M7, M8, M9

M4, M5, M6, M7, M8, M9, M10, M11

M6, M7, M8, M9, M10, M11, M12, M13

M8, M9, M10, M11, M12, M13, M14, M15

M10, M11, M12, M13, M14, M15, M0, M1

M12, M13, M14, M15, M0, M1, M2, M3

M14, M15, M0, M1, M2, M3, M4, M5

M2, M3, M4, M5, M6, M7, M8, M9

M10, M11, M12, M13, M14, M15, M0, M1

10

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Table 10. ORP Combinations for I/O Blocks with 12 I/Os

I/O Cell

Available Macrocells

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

M0, M1, M2, M3, M4, M5, M6, M7

M1, M2, M3, M4, M5, M6, M7, M8

M2, M3, M4, M5, M6, M7, M8, M9

M4, M5, M6, M7, M8, M9, M10, M11

M5, M6, M7, M8, M9, M10, M11, M12

M6, M7, M8, M9, M10, M11, M12, M13

M8, M9, M10, M11, M12, M13, M14, M15

M9, M10, M11, M12, M13, M14, M15, M0

M10, M11, M12, M13, M14, M15, M0, M1

M12, M13, M14, M15, M0, M1, M2, M3

M13, M14, M15, M0, M1, M2, M3, M4

M14, M15, M0, M1, M2, M3, M4, M5

ORP Bypass and Fast Output Multiplexers

The ORP bypass and fast-path output multiplexer is a 4:1 multiplexer and allows the 5-PT fast path to bypass the

ORP and be connected directly to the pin with either the regular output or the inverted output. This multiplexer also

allows the register output to bypass the ORP to achieve faster t

.

CO

Output Enable Routing Multiplexers

The OE Routing Pool provides the corresponding local output enable (OE) product term to the I/O cell.

I/O Cell

The I/O cell contains the following programmable elements: output buffer, input buffer, OE multiplexer and bus

maintenance circuitry. Figure 8 details the I/O cell.

Figure 8. I/O Cell

GOE 0

GOE 1

GOE 2

GOE 3

From ORP

VCC

V_CCO

*

From ORP

To Macrocell

To GRP

*Global fuses

Each output supports a variety of output standards dependent on the V

supplied to its I/O bank. Outputs can

CCO

also be conﬁgured for open drain operation. Each input can be programmed to support a variety of standards, inde-

pendent of the V supplied to its I/O bank. The I/O standards supported are:

CCO

11

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

• LVTTL

• LVCMOS 1.8

• 3.3V PCI Compatible

• LVCMOS 3.3

• LVCMOS 2.5

All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down

Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both

hardware and software is such that when the device is erased or if the user does not specify, the input structure is

conﬁgured to be a Pull-up Resistor.

Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be

individually conﬁgured for fast slew or slow slew. The typical edge rate difference between fast and slow slew set-

ting is 20%. For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reﬂec-

tions, less noise and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the

fast slew rate can be used to achieve the highest speed.

Global OE Generation

Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a

2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or

GOE pins. Each signal that drives the bus can optionally be inverted.

Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a

256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10

show a graphical representation of the global OE generation.

Figure 9. Global OE Generation for All Devices Except ispMACH 4032

Internal Global OE

Global OE

PT Bus

(4 lines)

4-Bit

Global OE Bus

Shared PTOE

(Block 0)

Shared PTOE

(Block n)

Global

Fuses

GOE (0:3)

to I/O cells

Fuse connection

Hard wired

12

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Figure 10. Global OE Generation for ispMACH 4032

Internal Global OE

PT Bus

4-Bit

Global OE Bus

Global OE

(2 lines)

Shared PTOE

(Block 0)

Shared PTOE

(Block 1)

Global

Fuses

GOE (3:0)

to I/O cells

Fuse connection

Hard wired

Zero Power/Low Power and Power Management

The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and

low power. With an advanced E²low power cell and non sense-ampliﬁer design approach (full CMOS logic

approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low

standby power without needing any “turbo bits” or other power management schemes associated with a traditional

sense-ampliﬁer approach.

The zero power ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design

changes, the ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.

IEEE 1149.1-Compliant Boundary Scan Testability

All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows

functional testing of the circuit board on which the device is mounted through a serial scan path that can access all

critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto

test nodes, or test node data to be captured and shifted out for veriﬁcation. In addition, these devices can be linked

into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS

interface that corresponds to the power supply voltage.

I/O Quick Conﬁguration

To facilitate the most efﬁcient board test, the physical nature of the I/O cells must be set before running any continu-

ity tests. As these tests are fast, by nature, the overhead and time that is required for conﬁguration of the I/Os’

physical nature should be minimal so that board test time is minimized.The ispMACH 4000 family of devices allows

this by offering the user the ability to quickly conﬁgure the physical nature of the I/O cells. This quick conﬁguration

takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's

ispVM™ System programming software can either perform the quick conﬁguration through the PC parallel port, or

can generate the ATE or test vectors necessary for a third-party test system.

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Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

IEEE 1532-Compliant In-System Programming

Programming devices in-system provides a number of signiﬁcant beneﬁts including: rapid prototyping, lower inven-

tory levels, higher quality and the ability to make in-ﬁeld modiﬁcations. All ispMACH 4000 devices provide In-Sys-

tem Programming (ISP™) capability through the Boundary Scan Test Access Port. This capability has been

implemented in a manner that ensures that the port remains complaint to the IEEE 1149.1 standard. By using IEEE

1149.1 as the communication interface through which ISP is achieved, users get the beneﬁt of a standard, well-

deﬁned interface. All ispMACH 4000 devices are also compliant with the IEEE 1532 standard.

The ispMACH 4000 devices can be programmed across the commercial temperature and voltage range. The PC-

based Lattice software facilitates in-system programming of ispMACH 4000 devices. The software takes the

JEDEC ﬁle output produced by the design implementation software, along with information about the scan chain,

and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain

via the parallel port of a PC. Alternatively, the software can output ﬁles in formats understood by common auto-

mated test equipment. This equipment can then be used to program ispMACH 4000 devices during the testing of a

circuit board.

Security Bit

A programmable security bit is provided on the ispMACH 4000 devices as a deterrent to unauthorized copying of

the array conﬁguration patterns. Once programmed, this bit defeats readback of the programmed pattern by a

device programmer, securing proprietary designs from competitors. Programming and veriﬁcation are also

defeated by the security bit. The bit can only be reset by erasing the entire device.

Hot Socketing

The ispMACH 4000 devices are well-suited for applications that require hot socketing capability. Hot socketing a

device requires that the device, during power-up and down, can tolerate active signals on the I/Os and inputs with-

out being damaged. Additionally, it requires that the effects of I/O pin loading be minimal on active signals. The

ispMACH 4000 devices provide this capability for input voltages in the range 0V to 3.0V.

Density Migration

The ispMACH 4000 family has been designed to ensure that different density devices in the same package have

the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration

from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-

geted for a high density device to a lower density device. However, the exact details of the ﬁnal resource utilization

will impact the likely success in each case.

14

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Absolute Maximum Ratings^{1, 2, 3}

ispMACH 4000C/Z

ispMACH 4000B

(2.5V)

ispMACH 4000V

(3.3V)

(1.8V)

Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V. . . . . . . . . . . -0.5 to 5.5V

CC

Output Supply Voltage (V

) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V. . . . . . . . . . . -0.5 to 4.5V

CCO

Input or I/O Tristate Voltage Applied^{4, 5}. . . . . . . . . -0.5 to 5.5V . . . . . . . . . .-0.5 to 5.5V. . . . . . . . . . . -0.5 to 5.5V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C. . . . . . . . . -65 to 150°C. . . . . . . . . .-65 to 150°C

Junction Temperature (T ) with Power Applied . . .-55 to 150°C. . . . . . . . . -55 to 150°C. . . . . . . . . .-55 to 150°C

j

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation

is not implied.

2. Compliance with Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Undershoot of -2V and overshoot of (V (MAX) + 2V), up to a total pin voltage of 6.0V, is permitted for a duration of < 20ns.

IH

5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.

Recommended Operating Conditions

Symbol

Parameter

Min.

1.65

1.7

Max.

1.95

1.9

Units

V

ispMACH 4000C

ispMACH 4000Z

Supply Voltage for 1.8V Devices

ispMACH 4000Z, Extended Functional Voltage

1.6^{1, 2}

V

1.9

V

CC

Operation

Supply Voltage for 2.5V Devices

Supply Voltage for 3.3V Devices

Junction Temperature (Commercial)

Junction Temperature (Industrial)

Junction Temperature (Automotive)

2.3

3.0

0

-40

2.7

3.6

90

105

130

V

C

T

j

1. Devices operating at 1.6V can expect performance degradation up to 35%.

2. Applicable for devices with 2004 datecodes and later. Contact factory for ordering instructions.

Erase Reprogram Speciﬁcations

Parameter

Erase/Reprogram Cycle

Min.

1,000

Max.

—

Units

Cycles

Note: Valid over commercial temperature range.

Hot Socketing Characteristics^1,2,3

Symbol

Parameter

Condition

0 ≤ V ≤ 3.0V, Tj = 105°C

Min.

—

Typ.

±30

Max.

±150

±200

Units

µA

IN

I

Input or I/O Leakage Current

DK

0 ≤ V ≤ 3.0V, Tj = 130°C

IN

1. Insensitive to sequence of V or V

However, assumes monotonic rise/fall rates for V and V

provided (V - V

) ≤ 3.6V.

CC

CCO.

CC

CCO,

IN

CCO

2. 0 < V < V (MAX), 0 < V

< V (MAX).

CCO

CC

CCO

3. I is additive to I , I or I . Device defaults to pull-up until fuse circuitry is active.

DK

PU PD

BH

15

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

I/O Recommended Operating Conditions

V

(V)¹

CCO

Standard

Min.

3.0

2.7

2.3

Max.

LVTTL

3.6

2.7

1.95

3.6

LVCMOS 3.3

Extended LVCMOS 3.3²

LVCMOS 2.5

LVCMOS 1.8

PCI 3.3

1.65

3.0

1. Typical values for V

are the average of the min. and max. values.

CCO

2. ispMACH 4000Z only.

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Input Leakage Current (ispMACH

0 ≤ V ≤ V

1

IN CCO

I , I

—

0.5

1

µA

IL IH

4000Z)

Input High Leakage Current

(ispMACH 4000Z)

V

< V ≤ 5.5V

CCO IN

1

I

—

10

µA

IH

0 ≤ V ≤ 3.6V, T = 105°C

—

10

15

µA

Input Leakage Current (ispMACH

4000V/B/C)

IN

j

1

I , I

IL IH

0 ≤ V ≤ 3.6V, T = 130°C

IN

j

3.6V < V ≤ 5.5V, T = 105°C

IN

j

—

20

50

µA

3.0V ≤ V

≤ 3.6V

Input High Leakage Current

(ispMACH 4000V/B/C)

CCO

1,2

I

IH

3.6V < V ≤ 5.5V, T = 130°C

IN

CCO

j

3.0V ≤ V

≤ 3.6V

I

I/O Weak Pull-up Resistor Current

I/O Weak Pull-down Resistor Current V (MAX) ≤ V ≤ V (MIN)

0 ≤ V ≤ 0.7V

-30

30

-30

—

-150

150

—

150

-150

µA

V

PU

IN

CCO

PD

IL

IN

IH

Bus Hold Low Sustaining Current

Bus Hold High Sustaining Current

Bus Hold Low Overdrive Current

Bus Hold High Overdrive Current

Bus Hold Trip Points

V

= V (MAX)

BHLS

BHHS

BHLO

BHHO

IN

IL

= 0.7 V

IN

CCO

0V ≤ V ≤ V

IN

BHT

V

≤ V ≤ V

—

BHT

IN

CCO

V

—

V

* 0.35

V

* 0.65

BHT

CCO

V

= 3.3V, 2.5V, 1.8V

—

CCO

C

I/O Capacitance³

8

6

pf

1

2

3

= 1.8V, V = 0 to V (MAX)

CC

IO

IH

= 3.3V, 2.5V, 1.8V

CCO

Clock Capacitance³

Global Input Capacitance³

= 1.8V, V = 0 to V (MAX)

CC

IO

IH

= 3.3V, 2.5V, 1.8V

CCO

= 1.8V, V = 0 to V (MAX)

CC

IO

IH

1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tristated. It is not

measured with the output driver active. Bus maintenance circuits are disabled.

2. 5V tolerant inputs and I/O should only be placed in banks where 3.0V ≤ V

≤ 3.6V.

CCO

3. T = 25°C, f = 1.0MHz

A

16

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000V/B/C

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

ispMACH 4032V/B/C

Vcc = 3.3V

—

11.8

1.8

11.3

1.3

—

mA

ICC^1,2,3

ICC⁴

Operating Power Supply Current

Standby Power Supply Current

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

ispMACH 4064V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

12

2

11.5

1.5

—

mA

ICC^1,2,3

Operating Power Supply Current

ICC⁵

Standby Power Supply Current

ispMACH 4128V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

12

2

11.5

1.5

—

mA

ICC^1,2,3

Operating Power Supply Current

ICC⁴

Standby Power Supply Current

ispMACH 4256V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

12.5

2.5

12

2

—

mA

1,2,3

I

Operating Power Supply Current

Standby Power Supply Current

CC

4

CC

ispMACH 4384V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

13.5

3.5

12.5

2.5

—

mA

1,2,3

I

Operating Power Supply Current

Standby Power Supply Current

CC

4

CC

ispMACH 4512V/B/C

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

—

14

4

—

mA

1,2,3

I

Operating Power Supply Current

CC

17

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000V/B/C (Cont.)

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Vcc = 3.3V

Vcc = 2.5V

Vcc = 1.8V

Min.

—

Typ.

13

3

Max.

—

Units

mA

4

I

Standby Power Supply Current

CC

—

mA

1. T = 25°C, frequency = 1.0 MHz.

A

2. Device conﬁgured with 16-bit counters.

3. I varies with speciﬁc device conﬁguration and operating frequency.

CC

4. T = 25°C

A

Supply Current, ispMACH 4000Z

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min. Typ. Max. Units

ispMACH 4032ZC

Vcc = 1.8V, T = 25°C

—

50

58

60

70

10

13

15

22

—

20

25

—

µA

A

Vcc = 1.9V, T = 70°C

A

ICC^{1, 2, 3, 5}

Operating Power Supply Current

Standby Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

Vcc = 1.8V, T = 25°C

A

Vcc = 1.9V, T = 70°C

A

ICC^{4, 5}

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

ispMACH 4064ZC

Vcc = 1.8V, T = 25°C

—

80

89

92

109

11

15

18

37

—

25

35

—

µA

A

Vcc = 1.9V, T = 70°C

A

ICC^{1, 2, 3, 5}

Operating Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

Vcc = 1.8V, T = 25°C

A

Vcc = 1.9V, T = 70°C

A

ICC^{4, 5}

Standby Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

ispMACH 4128ZC

Vcc = 1.8V, T = 25°C

—

168

190

195

212

12

16

19

42

—

35

50

—

µA

A

Vcc = 1.9V, T = 70°C

A

ICC^{1, 2, 3, 5}

Operating Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

Vcc = 1.8V, T = 25°C

A

Vcc = 1.9V, T = 70°C

A

ICC^{4, 5}

Standby Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

18

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Supply Current, ispMACH 4000Z (Cont.)

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min. Typ. Max. Units

ispMACH 4256ZC

Vcc = 1.8V, T = 25°C

—

341

361

372

468

13

32

43

135

—

55

90

—

µA

A

Vcc = 1.9V, T = 70°C

A

ICC^{1, 2, 3, 5}

Operating Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

Vcc = 1.8V, T = 25°C

A

Vcc = 1.9V, T = 70°C

A

ICC^{4, 5}

Standby Power Supply Current

Vcc = 1.9V, T = 85°C

A

Vcc = 1.9V, T = 125°C

A

1. T = 25°C, frequency = 1.0 MHz.

A

2. Device conﬁgured with 16-bit counters.

3. I varies with speciﬁc device conﬁguration and operating frequency.

CC

4. V

= 3.6V, V = 0V or V

bus maintenance turned off. V above V

will add transient current above the speciﬁed standby I

.

CC

CCO

IN

CCO,

IN

CCO

5. Includes V

current without output loading.

CCO

19

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

I/O DC Electrical Characteristics

Over Recommended Operating Conditions

V

1

IL

IH

V

I

OH

OL

OH

OL

Standard

LVTTL

Min (V)

Max (V)

Min (V)

Max (V) Max (V)

Min (V)

(mA) (mA)

0.40

0.20

0.40

0.20

0.40

0.20

0.40

0.20

V

- 0.40

8.0

0.1

8.0

0.1

8.0

0.1

2.0

0.1

2.0

0.1

1.5

-4.0

-0.1

-4.0

-0.1

-4.0

-0.1

-2.0

-0.1

-2.0

-0.1

-0.5

CCO

-0.3

0.80

0.70

0.63

2.0

5.5

- 0.20

- 0.40

- 0.20

- 0.40

- 0.20

- 0.45

- 0.20

- 0.45

- 0.20

LVCMOS 3.3

LVCMOS 2.5

-0.3

5.5

1.70

1.17

3.6

LVCMOS 1.8

(4000V/B)

3.6

0.40

0.20

LVCMOS 1.8

(4000C/Z)

0.35 * V

1.08

0.65 * V

1.5

3.6

CC

PCI 3.3 (4000V/B)

PCI 3.3 (4000C/Z)

-0.3

5.5

0.1 V

0.9 V

CCO

0.3 * 3.3 * (V / 1.8) 0.5 * 3.3 * (V / 1.8)

CC

CCO

1. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of

the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND

connections or between the last GND in a bank and the end of a bank.

20

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

3.3V V_CCO

2.5V V_CCO

70

100

80

60

40

20

0

60

I_OL

I_OH

50

I_OL

I_OH

40

30

20

10

0

0.5

1.0

1.5

2.0

2.5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5

V_OOutput Voltage (V)

1.8V V_CCO

60

50

I_OL

I_OH

40

30

20

10

0

0.5

1.0

1.5

2.0

V_OOutput Voltage (V)

21

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C External Switching Characteristics

Over Recommended Operating Conditions

-25

-27

-3

-35

Parameter

Description^{1, 2, 3}

Min. Max. Min. Max. Min. Max. Min. Max. Units

5-PT bypass combinatorial propagation

t

—

2.5

—

2.7

—

3.0

—

3.5

ns

PD

delay

20-PT combinatorial propagation delay

through macrocell

GLB register setup time before clock

t

—

3.2

—

3.5

—

3.8

—

4.2

—

ns

PD_MC

1.8

2.0

1.8

2.0

2.2

2.0

2.2

S

GLB register setup time before clock

—

ST

with T-type register

GLB register setup time before clock,

input register path

t

0.7

—

1.0

—

1.0

—

1.0

—

ns

SIR

GLB register setup time before clock

t

1.7

0.0

—

2.0

0.0

—

2.0

0.0

—

2.0

0.0

—

ns

SIRZ

H

with zero hold

GLB register hold time after clock

GLB register hold time after clock with

HT

T-type register

GLB register hold time after clock, input

register path

t

0.9

0.0

—

1.0

0.0

—

1.0

0.0

—

1.0

0.0

—

ns

HIR

GLB register hold time after clock, input

HIRZ

register path with zero hold

t

GLB register clock-to-output delay

External reset pin to output delay

External reset pulse duration

—

1.5

2.2

3.5

—

1.5

2.7

4.0

—

1.5

2.7

4.4

—

1.5

2.7

4.5

-

ns

CO

R

RW

Input to output local product term output

t

—

4.0

5.0

—

4.5

6.5

—

5.0

8.0

—

5.5

8.0

ns

PTOE/DIS

enable/disable

Input to output global product term

output enable/disable

GPTOE/DIS

t

Global OE input to output enable/disable

Global clock width, high or low

—

1.1

3.0

—

1.3

3.5

—

1.3

4.0

—

1.3

4.5

—

ns

GOE/DIS

CW

Global gate width low (for low

t

1.1

—

1.3

—

1.3

—

1.3

—

ns

GW

transparent) or high (for high transparent)

t

f

Input register clock width, high or low

Clock frequency with internal feedback

Clock frequency with external feedback,

1.1

400

—

1.3

333

—

1.3

322

—

1.3

322

—

ns

MHz

WIR

4

MAX

f

(Ext.)

250

—

222

—

212

—

212

—

MHz

MAX

[1/ (t + t )]

S

CO

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

Timing v.3.2

22

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C External Switching Characteristics (Cont.)

Over Recommended Operating Conditions

-5

-75

-10

Parameter

Description^{1, 2, 3}

Min. Max. Min. Max. Min. Max. Units

t

5-PT bypass combinatorial propagation delay

20-PT combinatorial propagation delay through macrocell

GLB register setup time before clock

GLB register setup time before clock with T-type register

GLB register setup time before clock, input register path

GLB register setup time before clock with zero hold

GLB register hold time after clock

—

5.0

5.5

—

7.5

8.0

—

10.0

10.5

—

ns

PD

t

PD_MC

S

3.0

3.2

1.2

2.2

0.0

1.0

4.5

4.7

1.7

2.7

0.0

1.0

5.5

1.7

2.7

0.0

1.0

ST

SIR

SIRZ

H

GLB register hold time after clock with T-type register

GLB register hold time after clock, input register path

HT

HIR

GLB register hold time after clock, input register path with

t

0.0

—

0.0

—

0.0

—

ns

HIRZ

zero hold

t

GLB register clock-to-output delay

External reset pin to output delay

External reset pulse duration

Input to output local product term output enable/disable

Input to output global product term output enable/disable

Global OE input to output enable/disable

Global clock width, high or low

—

2.0

—

3.4

6.3

—

7.0

9.0

5.0

—

4.0

—

4.5

9.0

—

9.0

10.3

7.0

—

4.0

—

6.0

10.5

—

10.5

12.0

8.0

ns

CO

R

RW

PTOE/DIS

GPTOE/DIS

GOE/DIS

CW

2.2

3.3

4.0

—

Global gate width low (for low transparent) or high (for

t

2.2

—

3.3

—

4.0

—

ns

GW

high transparent)

t

f

Input register clock width, high or low

Clock frequency with internal feedback

(Ext.) Clock frequency with external feedback, [1/ (t + t )]

2.2

227

156

—

3.3

168

111

—

4.0

125

86

—

ns

MHz

WIR

4

MAX

S

CO

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

Timing v.3.2

23

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z External Switching Characteristics

Over Recommended Operating Conditions

-35

-37

-42

Parameter

Description^{1, 2, 3}

Min.

Max.

Min.

Max.

Min.

Max.

Units

t

5-PT bypass combinatorial propagation delay

—

3.5

—

3.7

—

4.2

ns

PD

20-PT combinatorial propagation delay

—

4.4

—

4.7

—

5.7

—

ns

PD_MC

through macrocell

GLB register setup time before clock

2.2

2.4

2.5

2.7

2.9

S

GLB register setup time before clock with

—

ST

T-type register

GLB register setup time before clock, input

register path

t

1.0

—

1.1

—

1.3

—

ns

SIR

GLB register setup time before clock with zeto

t

2.0

0.0

—

2.1

0.0

—

2.6

0.0

—

ns

SIRZ

hold

GLB register hold time after clock

H

GLB register hold time after clock with T-type

HT

register

GLB register hold time after clock, input

register path

t

1.0

0.0

—

1.0

0.0

—

1.3

0.0

—

ns

HIR

GLB register hold time after clock, input

HIRZ

register path with zero hold

t

GLB register clock-to-output delay

External reset pin to output delay

External reset pulse duration

—

1.5

3.0

5.0

—

1.7

3.2

6.0

—

2.0

3.5

7.3

—

ns

CO

R

RW

Input to output local product term output

t

—

7.0

6.5

—

8.0

7.0

—

8.0

ns

PTOE/DIS

enable/disable

Input to output global product term output

enable/disable

GPTOE/DIS

t

Global OE input to output enable/disable

Global clock width, high or low

—

1.0

4.5

—

1.5

4.5

—

1.8

4.8

—

ns

GOE/DIS

CW

Global gate width low (for low transparent) or

t

1.0

—

1.5

—

1.8

—

ns

GW

high (for high transparent)

t

f

Input register clock width, high or low

Clock frequency with internal feedback

clock frequency with external feedback,

1.0

267

—

1.5

250

—

1.8

220

—

ns

MHz

WIR

4

MAX

t

(Ext.)

192

—

175

—

161

—

MHz

MAX

[1 / (t + t )]

S

CO

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

Timing v.2.2

24

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z External Switching Characteristics (Cont.)

Over Recommended Operating Conditions

-45

-5

-75

Parameter

Description^{1, 2, 3}

Min.

Max.

Min.

Max.

Min.

Max.

Units

t

5-PT bypass combinatorial propagation delay

—

4.5

—

5.0

—

7.5

ns

PD

20-PT combinatorial propagation delay

—

5.8

—

6.0

—

8.0

—

ns

PD_MC

through macrocell

GLB register setup time before clock

2.9

3.1

3.0

3.2

4.5

4.7

S

GLB register setup time before clock with T-

—

ST

type register

GLB register setup time before clock, input

register path

t

1.3

—

1.3

—

1.4

—

ns

SIR

GLB register setup time before clock with zeto

t

2.6

0.0

—

2.6

0.0

—

2.7

0.0

—

ns

SIRZ

H

hold

GLB register hold time after clock

GLB register hold time after clock with T-type

HT

register

GLB register hold time after clock, input regis-

ter path

t

1.3

0.0

—

1.3

0.0

—

1.3

0.0

—

ns

HIR

GLB register hold time after clock, input regis-

HIRZ

ter path with zero hold

t

GLB register clock-to-output delay

External reset pin to output delay

External reset pulse duration

—

2.0

3.8

7.5

—

2.0

4.2

7.5

—

4.0

4.5

9.0

—

ns

CO

R

RW

Input to output local product term output

t

—

8.2

—

8.5

—

9.0

ns

PTOE/DIS

enable/disable

Input to output global product term output

enable/disable

10.0

10.5

GPTOE/DIS

t

Global OE input to output enable/disable

Global clock width, high or low

—

1.8

5.5

—

2.0

6.0

—

3.3

7.0

—

ns

GOE/DIS

CW

Global gate width low (for low transparent) or

t

1.8

—

2.0

—

3.3

—

ns

GW

high (for high transparent)

t

f

Input register clock width, high or low

Clock frequency with internal feedback

clock frequency with external feedback, [1 /

1.8

200

—

2.0

200

—

3.3

168

—

ns

MHz

WIR

4

MAX

t

(Ext.)

150

—

139

—

111

—

MHz

MAX

(t + t )]

S

CO

1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.

2. Measured using standard switching GRP loading of 1 and 1 output switching.

3. Pulse widths and clock widths less than minimum will cause unknown behavior.

4. Standard 16-bit counter using GRP feedback.

Timing v.2.2

25

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Timing Model

The task of determining the timing through the ispMACH 4000 family, like any CPLD, is relatively simple. The timing

model provided in Figure 11 shows the speciﬁc delay paths. Once the implementation of a given function is deter-

mined either conceptually or from the software report ﬁle, the delay path of the function can easily be determined

from the timing model. The Lattice design tools report the timing delays based on the same timing model for a par-

ticular design. Note that the internal timing parameters are given for reference only, and are not tested. The exter-

nal timing parameters are tested and guaranteed for every device. For more information on the timing model and

usage, please refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines.

Figure 11. ispMACH 4000 Timing Model

Routing/GLB Delays

From

Feedback

t_PDb

t_PDi

Feedback

Out

t_FBK

t_ROUTE

t_BLA

t_MCELL

t_EXP

t_IN

t_BUF

t_IOO

t_EN

DATA

IN

t_ORP

t_IOI

Q

t_INREG

t_INDIO

t_DIS

t_{GCLK_IN}

t_IOI

In/Out

Delays

SCLK

t_PTCLK

t_BCLK

C.E.

S/R

t_PTSR

t_BSR

Register/Latch

Delays

MC Reg.

t_GPTOE

t_PTOE

Control

Delays

t_GOE

t_IOI

OE

In/Out

Delays

Note: Italicized items are optional delay adders.

26

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters

Over Recommended Operating Conditions

Parameter

Description

-2.5

-2.7

-3

-3.5

Units

In/Out Delays

t

Input Buffer Delay

Global OE Pin Delay

Global Clock Input Buffer Delay

Delay through Output Buffer

Output Enable Time

—

0.60

2.04

0.78

0.85

0.96

—

0.60

2.54

1.28

0.85

0.96

—

0.70

3.04

1.28

0.85

0.96

—

0.70

3.54

1.28

0.85

0.96

ns

IN

GOE

GCLK_IN

BUF

EN

Output Disable Time

DIS

Routing/GLB Delays

t

Delay through GRP

Macrocell Delay

—

0.61

0.45

—

0.81

0.55

—

1.01

0.55

—

1.01

0.65

ns

ROUTE

MCELL

Input Buffer to Macrocell Register

t

—

0.11

—

0.31

—

0.31

—

0.31

ns

INREG

Delay

t

Internal Feedback Delay

5-PT Bypass Propagation Delay

Macrocell Propagation Delay

—

0.00

0.44

0.64

—

0.00

0.44

0.64

—

0.00

0.44

0.64

—

0.00

0.94

ns

FBK

PDb

PDi

Register/Latch Delays

D-Register Setup Time

t

0.92

1.42

1.12

1.42

—

1.12

1.32

—

1.02

1.32

1.22

1.32

—

0.92

1.32

1.12

1.32

—

ns

S

(Global Clock)

D-Register Setup Time

S_PT

ST

(Product Term Clock)

T-Register Setup Time

(Global Clock)

T-Register Setup Time

ST_PT

(Product Term Clock)

t

D-Register Hold Time

T-Register Hold Time

0.88

—

0.68

—

0.98

—

1.08

—

ns

H

HT

D-Input Register Setup Time

t

0.82

1.45

0.88

—

1.37

1.45

0.63

—

1.27

1.45

0.73

—

1.27

1.45

0.73

—

ns

SIR

(Global Clock)

D-Input Register Setup Time

(Product Term Clock)

SIR_PT

HIR

D-Input Register Hold Time

—

(Global Clock)

D-Input Register Hold Time

(Product Term Clock)

—

HIR_PT

COi

Register Clock to Output/Feedback

0.52

MUX Time

t

Clock Enable Setup Time

Clock Enable Hold Time

2.25

1.88

—

2.25

1.88

—

2.25

1.88

—

2.25

1.88

—

ns

CES

CEH

Latch Setup Time

t

0.92

—

1.12

—

1.02

—

0.92

—

ns

SL

(Global Clock)

Latch Setup Time (Product Term

Clock)

Latch Hold Time

t

1.42

1.17

—

1.32

1.17

—

1.32

1.17

—

1.32

1.17

—

ns

SL_PT

HL

Latch Gate to Output/Feedback

0.33

GOi

MUX Time

27

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

Parameter

Description

-2.5

-2.7

-3

-3.5

Units

Propagation Delay through

Transparent Latch to Output/

Feedback MUX

t

—

0.25

—

0.25

—

0.25

—

0.25

ns

PDLi

Asynchronous Reset or Set to

t

0.28

1.67

—

0.28

1.67

—

0.28

1.67

—

0.28

1.67

—

ns

SRi

Output/Feedback MUX Delay

Asynchronous Reset or Set

Recovery Time

SRR

Control Delays

t

GLB PT Clock Delay

—

1.12

0.87

1.83

1.11

2.83

1.83

—

1.12

0.87

1.83

1.41

4.13

2.13

—

1.12

0.87

1.83

1.51

5.33

2.33

—

1.12

0.87

1.83

1.61

5.33

2.83

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

Block PT Set/Reset Delay

Macrocell PT Set/Reset Delay

Global PT OE Delay

PTSR

GPTOE

PTOE

Macrocell PT OE Delay

ns

Timing v.3.2

Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.

28

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters

Over Recommended Operating Conditions

-5

-75

-10

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

Global OE Pin Delay

Global Clock Input Buffer Delay

Delay through Output Buffer

Output Enable Time

—

0.95

4.04

1.83

1.00

0.96

—

1.50

6.04

2.28

1.50

0.96

—

2.00

7.04

3.28

1.50

0.96

ns

IN

GOE

GCLK_IN

BUF

EN

Output Disable Time

DIS

Routing/GLB Delays

t

Delay through GRP

Macrocell Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

5-PT Bypass Propagation Delay

Macrocell Propagation Delay

—

1.51

1.05

0.56

0.00

1.54

0.94

—

2.26

1.45

0.96

0.00

2.24

1.24

—

3.26

1.95

1.46

0.00

3.24

1.74

ns

ROUTE

MCELL

INREG

FBK

PDb

PDi

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

T-Register Setup Time (Global Clock)

T-Register Setup Time (Product Term Clock)

D-Register Hold Time

1.32

1.52

1.32

1.68

1.52

1.45

0.68

—

2.25

1.88

1.32

1.17

—

0.52

—

0.33

0.25

1.57

1.32

1.77

1.32

2.93

1.57

1.45

1.18

—

2.25

1.88

1.57

1.32

1.17

—

0.67

—

0.33

0.25

1.57

1.32

1.77

1.32

3.93

1.57

1.45

1.18

—

2.25

1.88

1.57

1.32

1.17

—

1.17

—

0.33

0.25

ns

S

S_PT

ST

ST_PT

H

T-Register Hold Time

HT

D-Input Register Setup Time (Global Clock)

D-Input Register Setup Time (Product Term Clock)

D-Input Register Hold Time (Global Clock)

D-Input Register Hold Time (Product Term Clock)

Register Clock to Output/Feedback MUX Time

Clock Enable Setup Time

Clock Enable Hold Time

Latch Setup Time (Global Clock)

Latch Setup Time (Product Term Clock)

Latch Hold Time

Latch Gate to Output/Feedback MUX Time

SIR

SIR_PT

HIR

HIR_PT

COi

CES

CEH

SL

SL_PT

HL

GOi

Propagation Delay through Transparent Latch to Output/

—

PDLi

Feedback MUX

t

Asynchronous Reset or Set to Output/Feedback MUX

Delay

Asynchronous Reset or Set Recovery Time

0.28

1.67

—

0.28

1.67

—

0.28

1.67

—

ns

SRi

t

SRR

Control Delays

t

GLB PT Clock Delay

—

1.12

0.87

1.83

2.51

—

1.12

0.87

1.83

3.41

—

0.62

0.87

1.83

3.41

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

GLB PT Set/Reset Delay

Macrocell PT Set/Reset Delay

PTSR

29

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

-5

-75

-10

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

t

Global PT OE Delay

Macrocell PT OE Delay

—

5.58

3.58

—

5.58

4.28

—

5.78

4.28

ns

GPTOE

PTOE

Timing v.3.2

Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details.

30

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Internal Timing Parameters

Over Recommended Operating Conditions

-35

-37

-42

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

Global OE Pin Delay

Global Clock Input Buffer Delay

Delay through Output Buffer

Output Enable Time

—

0.75

2.25

1.60

0.75

2.25

1.35

—

0.80

2.25

1.60

0.90

2.25

1.35

—

0.75

2.30

1.95

0.90

2.50

ns

IN

GOE

GCLK_IN

BUF

EN

Output Disable Time

DIS

Routing/GLB Delays

t

Delay through GRP

Macrocell Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

5-PT Bypass Propagation Delay

Macrocell Propagation Delay

—

1.60

0.65

0.91

0.05

0.40

0.25

—

1.60

0.75

1.00

0.00

0.40

0.25

—

2.15

0.85

1.00

0.00

0.40

0.65

ns

ROUTE

MCELL

INREG

FBK

PDb

PDi

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

T-Register Setup Time (Global Clock)

T-register Setup Time (Product Term Clock)

D-Register Hold Time

0.80

1.35

1.00

1.55

1.40

0.94

1.45

1.06

0.88

—

1.00

0.00

0.80

1.55

1.40

—

0.65

—

0.40

0.95

1.95

1.15

1.75

1.55

0.90

1.45

1.20

1.00

—

2.00

0.00

0.95

1.95

1.80

—

0.70

—

0.33

0.90

1.90

1.10

2.10

1.80

1.50

1.45

1.10

1.00

—

2.00

0.00

0.90

1.90

1.80

—

0.65

—

0.33

ns

S

S_PT

ST

ST_PT

H

T-Resister Hold Time

HT

D-Input Register Setup Time (Global Clock)

D-Input Register Setup Time (Product Term Clock)

D-Input Register Hold Time (Global Clock)

D-Input Register Hold Time (Product Term Clock)

Register Clock to Output/Feedback MUX Time

Clock Enable Setup Time

Clock Enable Hold Time

Latch Setup Time (Global Clock)

Latch Setup Time (Product Term Clock)

Latch Hold Time

Latch Gate to Output/Feedback MUX Time

SIR

SIR_PT

HIR

HIR_PT

COi

CES

CEH

SL

SL_PT

HL

GOi

Propagation Delay through Transparent Latch to Output/

t

—

0.30

—

0.25

—

0.25

ns

PDLi

Feedback MUX

t

Asynchronous Reset or Set to Output/Feedback MUX Delay

Asynchronous Reset or Set Recovery Delay

—

0.28

2.00

—

0.28

1.67

—

1.27

1.80

ns

SRi

SRR

Control Delays

t

GLB PT Clock Delay

—

1.30

1.50

1.10

1.22

—

1.50

1.70

1.83

2.02

—

1.55

1.83

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

GLB PT Set/Reset Delay

Macrocell PT Set/Reset Delay

PTSR

31

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

-35

-37

-42

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

t

Global PT OE Delay

Macrocell PT OE Delay

—

1.9

2.4

—

2.35

3.35

—

2.60

ns

GPTOE

PTOE

Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for

further details.

Timing v.2.2

32

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

-45

-5

-75

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

In/Out Delays

t

Input Buffer Delay

Global OE Pin Delay

Global Clock Input Buffer Delay

Delay through Output Buffer

Output Enable Time

—

0.95

3.00

1.95

1.10

2.50

—

1.25

3.50

2.05

1.00

2.50

—

1.80

4.30

2.15

1.30

2.70

ns

IN

GOE

GCLK_IN

BUF

EN

Output Disable Time

DIS

Routing/GLB Delays

t

Delay through GRP

Macrocell Delay

Input Buffer to Macrocell Register Delay

Internal Feedback Delay

5-PT Bypass Propagation Delay

Macrocell Propagation Delay

—

2.25

0.65

1.00

0.35

0.20

0.45

—

2.05

0.65

1.00

0.05

0.70

0.65

—

2.50

1.00

0.05

1.90

1.00

ns

ROUTE

MCELL

INREG

FBK

PDb

PDi

Register/Latch Delays

t

D-Register Setup Time (Global Clock)

D-Register Setup Time (Product Term Clock)

T-Register Setup Time (Global Clock)

T-register Setup Time (Product Term Clock)

D-Register Hold Time

1.00

2.10

1.20

2.30

1.90

1.30

1.45

1.30

1.00

—

2.00

0.00

1.00

2.10

2.00

—

0.75

—

0.33

1.10

1.90

1.30

2.10

1.90

1.10

1.45

1.50

1.00

—

2.00

0.00

1.00

1.90

2.00

—

1.15

—

0.33

1.35

2.45

1.55

2.75

3.15

0.75

1.45

1.95

1.18

—

2.00

0.00

1.65

2.15

1.17

—

1.05

—

0.33

ns

S

S_PT

ST

ST_PT

H

T-Resister Hold Time

HT

D-Input Register Setup Time (Global Clock)

D-Input Register Setup Time (Product Term Clock)

D-Input Register Hold Time (Global Clock)

D-Input Register Hold Time (Product Term Clock)

Register Clock to Output/Feedback MUX Time

Clock Enable Setup Time

Clock Enable Hold Time

Latch Setup Time (Global Clock)

Latch Setup Time (Product Term Clock)

Latch Hold Time

Latch Gate to Output/Feedback MUX Time

SIR

SIR_PT

HIR

HIR_PT

COi

CES

CEH

SL

SL_PT

HL

GOi

Propagation Delay through Transparent Latch to Output/

t

—

0.25

—

0.25

—

0.25

ns

PDLi

Feedback MUX

t

Asynchronous Reset or Set to Output/Feedback MUX Delay

Asynchronous Reset or Set Recovery Delay

—

0.97

1.80

—

0.97

1.80

—

0.28

1.67

ns

SRi

SRR

Control Delays

t

GLB PT Clock Delay

—

1.55

1.83

4.30

—

1.55

1.83

4.20

—

1.25

1.83

2.72

3.50

ns

BCLK

PTCLK

BSR

Macrocell PT Clock Delay

GLB PT Set/Reset Delay

Macrocell PT Set/Reset Delay

Global PT OE Delay

PTSR

GPTOE

33

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Internal Timing Parameters (Cont.)

Over Recommended Operating Conditions

-45

-5

-75

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

t

Macrocell PT OE Delay

—

2.50

—

2.70

—

2.00

ns

PTOE

Note: Internal Timing Parameters are not tested and are for reference only. Refer to the timing model in this data sheet for

further details.

Timing v.2.2

34

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Timing Adders¹

-25

-27

-3

-35

Adder

Base

Type

Parameter

Description

Min. Max. Min. Max. Min. Max. Min. Max. Units

Optional Delay Adders

t

Input register delay

—

0.95

0.33

0.05

0.03

—

1.00

0.33

—

1.00

0.33

—

1.00

0.33

ns

INDIO

INREG

Product term expander

t

EXP

MCELL

delay

—

Output routing pool delay

0.05

ns

ORP

BLA

Additional block loading

t

ROUTE

adder

t

Input Adjusters

IOI

t , t

,

IN GCLK_IN

GOE

LVTTL_in

Using LVTTL standard

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

ns

t

t , t

Using LVCMOS 3.3

standard

IN GCLK_IN

GOE

LVCMOS33_in

LVCMOS25_in

LVCMOS18_in

PCI_in

t

t , t

Using LVCMOS 2.5

IN GCLK_IN

GOE

t

standard

t , t

Using LVCMOS 1.8

standard

IN GCLK_IN

GOE

t

t , t

Using PCI compatible

IN GCLK_IN

GOE

t

input

t

Output Adjusters

IOO

Output conﬁgured as

LVTTL_out

t

, t , t

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

ns

BUF EN DIS

TTL buffer

Output conﬁgured as

LVCMOS33_out t

LVCMOS25_out t

LVCMOS18_out t

, t , t

BUF EN DIS

3.3V buffer

Output conﬁgured as

, t , t

BUF EN DIS

2.5V buffer

Output conﬁgured as

, t , t

BUF EN DIS

1.8V buffer

Output conﬁgured as

PCI_out

t

, t , t

BUF EN DIS

PCI compatible buffer

Output conﬁgured for

Slow Slew

, t

BUF EN

slow slew rate

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.3.2

1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.

35

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C Timing Adders¹(Cont.)

-5

-75

-10

Adder

Base

Type

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Optional Delay Adders

t

Input register delay

Product term expander delay

Output routing pool delay

—

1.00

0.33

0.05

—

1.00

0.33

0.05

—

1.00

0.33

0.05

ns

INDIO

EXP

INREG

MCELL

—

ORP

BLA

t

Additional block loading adder

ROUTE

t

Input Adjusters

IOI

t , t

,

IN GCLK_IN

GOE

LVTTL_in

Using LVTTL standard

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

ns

t

t , t

IN GCLK_IN

GOE

LVCMOS33_in

LVCMOS25_in

LVCMOS18_in

PCI_in

Using LVCMOS 3.3 standard

Using LVCMOS 2.5 standard

Using LVCMOS 1.8 standard

Using PCI compatible input

t

t , t

IN GCLK_IN

GOE

t

t , t

IN GCLK_IN

GOE

t

t , t

IN GCLK_IN

GOE

t

Output Adjusters

IOO

LVTTL_out

t

, t , t

Output conﬁgured as TTL buffer

Output conﬁgured as 3.3V buffer

Output conﬁgured as 2.5V buffer

Output conﬁgured as 1.8V buffer

—

0.20

0.10

0.00

—

0.20

0.10

0.00

—

0.20

0.10

0.00

ns

BUF EN DIS

LVCMOS33_out t

LVCMOS25_out t

LVCMOS18_out t

, t , t

BUF EN DIS

, t , t

BUF EN DIS

, t , t

BUF EN DIS

Output conﬁgured as PCI compatible

PCI_out

t

, t , t

—

0.20

1.00

—

0.20

1.00

—

0.20

ns

BUF EN DIS

buffer

Slow Slew

t

, t

Output conﬁgured for slow slew rate

1.00

ns

BUF EN

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.3.2

1. Refer to Technical Note TN1004: ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these adders.

36

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Timing Adders ¹

-35

-37

-42

Adder

Base

Type

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Optional Delay Adders

t

Input register delay

—

1.00

0.40

—

1.00

0.40

—

1.30

0.45

ns

INDIO

EXP

INREG

MCELL

Product term expander

delay

t

—

Output routing pool

delay

ORP

BLA

—

0.40

0.04

—

0.40

0.05

—

0.40

0.05

ns

t

Additional block load-

ROUTE

ing adder

t

Input Adjusters

IOI

LVTTL_in

LVCMOS33_in

t

Using LVTTL standard

—

0.60

—

0.60

—

0.60

ns

IN, GCLK_IN, GOE

Using LVCMOS 3.3

IN, GCLK_IN, GOE

standard

LVCMOS25_in

LVCMOS18_in

PCI_in

t

Using LVCMOS 2.5

standard

IN, GCLK_IN, GOE

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

ns

t

Using LVCMOS 1.8

IN, GCLK_IN, GOE

standard

t

Using PCI compatible

input

IN, GCLK_IN, GOE

t

Output Adjusters

IOO

LVTTL_out

t

Output conﬁgured as

BUF, EN, DIS

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

ns

TTL buffer

LVCMOS33_out

LVCMOS25_out

LVCMOS18_out

PCI_out

t

Output conﬁgured as

BUF, EN, DIS

3.3V buffer

t

Output conﬁgured as

BUF, EN, DIS

2.5V buffer

t

Output conﬁgured as

BUF, EN, DIS

1.8V buffer

t

Output conﬁgured as

BUF, EN, DIS

PCI compatible buffer

Slow Slew

t

Output conﬁgured for

BUF, EN

ns

slow slew rate

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.2.2

1. Refer to Technical Note TN 1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding the use of these

adders.

37

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z Timing Adders (Cont.)¹

-45

-5

-75

Adder

Base

Type

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Optional Delay Adders

t

Input register delay

—

1.30

0.45

—

1.30

0.45

—

1.30

0.50

ns

INDIO

EXP

INREG

MCELL

Product term expander

delay

t

—

Output routing pool

delay

ORP

BLA

—

0.40

0.05

—

0.40

0.05

—

0.40

0.05

ns

t

Additional block load-

ROUTE

ing adder

t

Input Adjusters

IOI

LVTTL_in

LVCMOS33_in

t

Using LVTTL standard

—

0.60

—

0.60

—

0.60

ns

IN, GCLK_IN, GOE

Using LVCMOS 3.3

IN, GCLK_IN, GOE

standard

LVCMOS25_in

LVCMOS18_in

PCI_in

t

Using LVCMOS 2.5

standard

IN, GCLK_IN, GOE

—

0.60

0.00

0.60

—

0.60

0.00

0.60

—

0.60

0.00

0.60

ns

t

Using LVCMOS 1.8

IN, GCLK_IN, GOE

standard

t

Using PCI compatible

input

IN, GCLK_IN, GOE

t

Output Adjusters

IOO

LVTTL_out

t

Output conﬁgured as

BUF, EN, DIS

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

—

0.20

0.10

0.00

0.20

1.00

ns

TTL buffer

LVCMOS33_out

LVCMOS25_out

LVCMOS18_out

PCI_out

t

Output conﬁgured as

BUF, EN, DIS

3.3V buffer

t

Output conﬁgured as

BUF, EN, DIS

2.5V buffer

t

Output conﬁgured as

BUF, EN, DIS

1.8V buffer

t

Output conﬁgured as

BUF, EN, DIS

PCI compatible buffer

Slow Slew

t

Output conﬁgured for

BUF, EN

ns

slow slew rate

Note: Open drain timing is the same as corresponding LVCMOS timing.

Timing v.2.2

1. Refer to Technical Note TN 1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding use of these

adders.

38

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Boundary Scan Waveforms and Timing Speciﬁcations

Symbol

Parameter

Min.

40

20

8

10

50

—

8

Max.

—

10

—

Units

ns

mV/ns

ns

t

TCK [BSCAN test] clock cycle

TCK [BSCAN test] pulse width high

TCK [BSCAN test] pulse width low

TCK [BSCAN test] setup time

TCK [BSCAN test] hold time

TCK [BSCAN test] rise and fall time

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to data output disable

TAP controller falling edge of clock to data output enable

BSCAN test Capture register setup time

BTCP

BTCH

BTCL

BTSU

BTH

BRF

BTCO

BTOZ

BTVO

BTCPSU

BTCPH

BTUCO

BTUOZ

BTUOV

ns

BSCAN test Capture register hold time

10

—

BSCAN test Update reg, falling edge of clock to valid output

BSCAN test Update reg, falling edge of clock to output disable

BSCAN test Update reg, falling edge of clock to output enable

25

ns

39

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Power Consumption

ispMACH 4000Z

ispMACH 4000V/B

ispMACH 4000C

Typical I vs. Frequency

Typical I

vs. Frequency

Typical I

vs. Frequency

CC

(Preliminary Information)

4512V/B

4384V/B

100

80

60

40

20

0

300

250

200

150

100

300

250

200

150

100

4512C

4384C

4256ZC

4256V/B

4256C

4128C

4128ZC

4064ZC

4128V/B

4064V/B

4032V/B

50

0

50

0

4032ZC

4064C

4032C

0

50

100

150

200

250

300

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

Note: The devices are configured with maximum number

of 16-bit counters, typical current at 1.8V, 25°C.

of 16-bit counters, typical current at 3.3V, 2.5V, 25°C.

Power Estimation Coefﬁcients¹

Device

ispMACH 4032V/B

ispMACH 4032C

ispMACH 4064V/B

ispMACH 4064C

ispMACH 4128V/B

ispMACH 4128C

ispMACH 4256V/B

ispMACH 4256C

ispMACH 4384V/B

ispMACH 4384C

ispMACH 4512V/B

ispMACH 4512C

ispMACH 4032ZC

ispMACH 4064ZC

ispMACH 4128ZC

ispMACH 4256ZC

A

11.3

1.3

11.5

1.5

11.5

1.5

12

2

12.5

2.5

13

3

B

0.010

0.011

0.013

0.010

0.011

0.012

0.013

1. For further information about the use of these coefﬁcients, refer to Technical Note

TN1005, Power Estimation in ispMACH 4000V/B/C/Z Devices.

40

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Switching Test Conditions

Figure 12 shows the output test load that is used for AC testing. The speciﬁc values for resistance, capacitance,

voltage, and other test conditions are shown in Table 11.

Figure 12. Output Test Load, LVTTL and LVCMOS Standards

V

CCO

R

1

2

Test

Point

DUT

R

C

L

0213A/ispm4k

Table 11. Test Fixture Required Components

1

Test Condition

R

C

Timing Ref.

V

CCO

1

2

L

LVCMOS 3.3 = 1.5V

LVCMOS 3.3 = 3.0V

LVCMOS I/O, (L -> H, H -> L)

106Ω 106Ω

35pF

LVCMOS 2.5 = V

LVCMOS 1.8 = V

1.5V

/2

LVCMOS 2.5 = 2.3V

LVCMOS 1.8 = 1.65V

3.0V

CCO

LVCMOS I/O (Z -> H)

LVCMOS I/O (Z -> L)

LVCMOS I/O (H -> Z)

LVCMOS I/O (L -> Z)

∞

106Ω

∞

35pF

5pF

106Ω

∞

1.5V

106Ω

∞

V

- 0.3

+ 0.3

OH

OL

106Ω

5pF

1. C includes test ﬁxtures and probe capacitance.

L

41

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Signal Descriptions

Signal Names

Description

TMS

Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control

the state machine

TCK

Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the

state machine

TDI

TDO

Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data

Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out

GOE0/IO, GOE1/IO

These pins are conﬁgured to be either Global Output Enable Input or as general I/O

pins

GND

NC

Ground

Not Connected

V

The power supply pins for logic core

These pins are conﬁgured to be either CLK input or as an input

The power supply pins for each I/O bank

CC

CLK0/I, CLK1/I, CLK2/I, CLK3/I

, V

V

CCO0 CCO1

Input/Output¹– These are the general purpose I/O used by the logic array. y is GLB

reference (alpha) and z is macrocell reference (numeric). z: 0-15

ispMACH 4032

ispMACH 4064

ispMACH 4128

ispMACH 4256

ispMACH 4384

ispMACH 4512

y: A-B

y: A-D

y: A-H

yzz

y: A-P

y: A-P, AX-HX

y: A-P, AX-PX

1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details.

ispMACH 4000V/B/C ORP Reference Table

4032V/B/C

4064V/B/C

4128V/B/C

64

92³96

4256V/B/C

4384V/B/C

128 192 128

4512V/B/C

30¹

2

32 30²32

64

16

96⁴

128

16

160

16

208

16

Number of I/Os

Number of GLBs

2

4

8

4

8

4

8

16

8

16

8

16

8

Number of I/Os /

Mixture

16

8

12 12

4

8

10

of 8 & 4⁵

GLB

8 I/Os /

GLB

Reference ORP

Table

16 I/Os /

GLB

8 I/Os / 16 I/Os / 8 I/Os / 12 I/Os / 4 I/Os / 8 I/Os / 8 I/Os / 10 I/Os / 8 I/Os / 8 I/Os /

GLB

4 I/Os /

GLB

1. 32-macrocell device, 44 TQFP: 2 GLBs have 15 out of 16 I/Os bonded out.

2. 64-macrocesll device, 44 TQFP: 2 GLBs have 7 out of 8 I/Os bonded out.

3. 128-macrocell device, 128 TQFP: 4 GLBs have 11 out of 12 I/Os

4. 256-macrocell device, 144 TQFP: 16 GLBs have 6 I/Os per

5. 512-macrocell device: 20 GLBs have 8 I/Os per, 12 GLBs have 4 I/Os per

ispMACH 4000Z ORP Reference Table

4032Z

32

4064Z

4128Z

4256Z

Number of I/Os

Number of GLBs

Number of I/Os / GLB

32

4

64

4

64

8

96

8

12

64

16

4

96¹

16

8

128

16

8

2

16

8

16

16 I/Os /

8 I/Os /

16 I/Os /

8 I/Os /

12 I/Os /

4 I/Os /

8 I/Os /

Reference ORP Table

GLB

1. 256-macrocell device, 132 csBGA: 16 GLBs have 6 I/Os per

42

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C/Z Power Supply and NC Connections¹

Signal

44-pin TQFP²

11, 33

48-pin TQFP²

12, 36

56-ball csBGA³

K2, A9

100-pin TQFP²

25, 40, 75, 90

13, 33, 95

128-pin TQFP²

32, 51, 96, 115

3, 17, 30, 41, 122

VCC

VCCO0

6

F3

VCCO (Bank 0)

VCCO1

28

30

E8

45, 63, 83

58, 67, 81, 94, 105

VCCO (Bank 0)

GND

12, 34

5

27

13, 37

5

29

H3, C8

D3

G8

1, 26, 51, 76

7, 18, 32, 96

46, 57, 68, 82

1, 33, 65, 97

10, 24, 40, 113, 123

49, 59, 74, 88, 104

—

GND (Bank 0)

GND (Bank 1)

NC

—

4032Z: A8, B10, E1, —

E3, F8, F10, J1, K3

1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with

the bank shown.

2. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.

3. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order

ascending horizontally.

43

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V/B/C/Z Power Supply and NC Connections¹(Cont.)

Signal

VCC

132-ball csBGA⁷

P1, A14, B7, N8

144-pin TQFP⁴

36, 57, 108, 129

176-pin TQFP⁴

256-ball fpBGA^{2, 3, 7}

B2, B15, G8, G9, K8, K9, R2, R15

42, 69, 88, 130,

157, 176

VCCO0

G3, P5, C1⁸, M2⁸,

3, 19, 34, 47, 136

4, 22, 40, 56, 166 D6, F4, H7, J7, L4, N6

VCCO (Bank 0) C5

VCCO1

M10, M14⁸, H12,

64, 75, 91, 106, 119 78, 92, 110, 128, D11, F13, H10, J10, L13, N11

144

1, 37, 73, 109

VCCO (Bank 1) A10, C13⁸

GND

B1, P2, N14, A13

2, 46⁵, 65, 90, 134, A1, A16, C6, C11, F3, F14, G7, G10, H8,

153

H9, J8, J9, K7, K10, L3, L14, P6, P11, T1,

T16

GND (Bank 0) E2, K2, N4, B4

10, 18⁶, 27, 46, 127, 13, 31, 55, 155,

137 167

GND (Bank 1) N11, K13, E13, B11 55, 65, 82, 90⁶, 99, 67, 79, 101, 119,

118

143

1, 43, 44, 45, 89, 4256V/B/C, 128 I/O: A4, A5, A6, A11, A12,

NC

4064Z: C1, C3, E1, 4128V: 17, 20, 38,

E3, H2, J3, K1, M2, 45, 72, 89, 92, 110, 131, 132, 133

M4, N5, P7, P8, M8, 117, 144

A13, A15, B5, B6, B11, B12, B14, C7, D1,

D4, D5, D10, D12, D16, E1, E2, E4, E5, E7,

E10, E13, E14, E15, E16, F1, F2, F15, F16,

G1, G4, G5, G6, G12, G13, G14, J11, K3,

K4, K15, L1, L2, L12, L15, L16, M1, M2, M3,

M4, M5, M12, M13, M15, M16, N1, N2, N7,

N10, N12, N14, P5, P12, R4, R5, R6, R11,

R12, R16, T2, T4, T5, T6, T11, T12, T13, T15

P10, P11, P14, M12,

K14, K12, G13,

G14, E14, C13, B13,

B10, C10, A7, B5,

A5, A4, A1

4256V: 18, 90

4128Z: P8, A7

4256V/B/C, 160 I/O: A5, A12, A15, B5, B6,

B11, B12, B14, D4, D5, D12, E1, E4, E5,

E13, E15, E16, F1, F2, F15, G1, G5, G12,

G14, L1, L2, L12, L15, L16, M1, M2, M3,

M12, M16, N1, N12, N14, P5, R4, R5, R6,

R11, R12, R16, T4, T5, T12, T15

4384V/B/C: B5, B12, D5, D12, E1, E15,

E16, F2, L12, M1, M2, M16, N12, R5, R12,

T4

4512V/B/C: None

1. All grounds must be electrically connected at the board level. However, for the purposes of I/O current loading, grounds are associated with

the bank shown.

2. Internal GNDs and I/O GNDs (Bank 0/1) are connected inside package.

3. V

balls connect to two power planes within the package, one for V

and one for V

.

CCO1

CCO

CCO0

4. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.

5. ispMACH 4384V/B/C pin 46 is tied to GND (Bank 0).

6. ispMACH 4128V only.

7. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order

ascending horizontally.

8. ispMACH 4128Z and 4256Z only. NC for ispMACH 4064Z.

44

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections:

44-Pin TQFP

ispMACH 4032V/B/C

GLB/MC/Pad ORP

ispMACH 4064V/B/C

Pin Number

Bank Number

GLB/MC/Pad

ORP

-

1

2

3

4

5

6

7

8

-

TDI

A5

A6

A7

-

A^5

A^6

A^7

-

TDI

0

-

A10

A12

A14

A^5

A^6

A^7

-

GND (Bank 0)

VCCO (Bank 0)

-

VCCO (Bank 0)

-

A8

A9

A10

A^8

A^9

A^10

-

B0

B2

B4

B^0

B^1

B^2

-

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

TCK

-

VCC

GND

A12

A13

A14

A15

CLK2/I

B0

B1

B2

B3

B4

TMS

B5

B6

-

VCC

GND

B8

B10

B12

B14

CLK2/I

C0

C2

C4

C6

C8

TMS

C10

C12

-

0

1

-

1

-

A^12

A^13

A^14

A^15

-

B^0

B^1

B^2

B^3

B^4

-

B^4

B^5

B^6

B^7

-

C^0

C^1

C^2

C^3

C^4

-

B^5

B^6

B^7

-

C^5

C^6

C^7

-

B7

C14

GND (Bank 1)

VCCO (Bank 1)

B8

GND (Bank 1)

VCCO (Bank 1)

D0

-

B^8

B^9

B^10

-

B^12

B^13

B^14

B^15

-

D^0

D^1

D^2

-

D^4

D^5

D^6

D^7

-

B9

B10

TDO

VCC

GND

B12

D2

D4

TDO

VCC

GND

D8

-

1

0

B13

B14

B15/GOE1

CLK0/I

A0/GOE0

A1

D10

D12

D14/GOE1

CLK0/I

A0/GOE0

A2

A^0

A^1

A^0

A^1

45

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4032V/B/C and 4064V/B/C Logic Signal Connections:

44-Pin TQFP (Cont.)

ispMACH 4032V/B/C

ispMACH 4064V/B/C

Pin Number

Bank Number

GLB/MC/Pad

ORP

A^2

A^3

A^4

GLB/MC/Pad

ORP

A^2

A^3

A^4

42

43

44

0

A2

A3

A4

A6

A8

ispMACH 4032V/B/C/Z and 4064V/B/C/Z Logic Signal Connections:

48-Pin TQFP

ispMACH 4032V/B/C

ispMACH 4064V/B/C

ispMACH 4064Z

Bank

Number Number GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

1

-

TDI

2

3

4

5

6

7

8

9

0

-

A5

A6

A7

A^5

A^6

A^7

-

A10

A12

A14

A^5

A^6

A^7

-

A8

A10

A11

A^5

A^6

A^7

-

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

-

A8

A9

A10

A11

TCK

VCC

GND

A12

A13

A14

A15

CLK1/I

CLK2/I

B0

B1

B2

A^8

A^9

A^10

A^11

-

B0

B2

B4

B6

TCK

VCC

GND

B8

B10

B12

B14

CLK1/I

CLK2/I

C0

C2

C4

B^0

B^1

B^2

B^3

-

B15

B12

B10

B8

TCK

VCC

GND

B6

B4

B2

B0

CLK1/I

CLK2/I

C0

C1

C2

B^7

B^6

B^5

B^4

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

-

0

1

-

1

A^12

A^13

A^14

A^15

-

B^4

B^5

B^6

B^7

-

B^3

B^2

B^1

B^0

-

B^0

B^1

B^2

B^3

B^4

-

B^5

B^6

B^7

-

C^0

C^1

C^2

C^3

C^4

-

C^5

C^6

C^7

-

C^0

C^1

C^2

C^3

C^4

-

C^5

C^6

C^7

-

B3

B4

TMS

B5

C6

C8

TMS

C10

C4

C6

TMS

C8

C10

B6

C12

C14

GND (Bank 1)

VCCO (Bank 1)

D0

B7

GND (Bank 1)

VCCO (Bank 1)

B8

C11

GND (Bank 1)

VCCO (Bank 1)

D15

-

B^8

B^9

D^0

D^1

D^7

D^6

B9

D2

D12

46

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4032V/B/C/Z and 4064V/B/C/Z Logic Signal Connections:

48-Pin TQFP (Cont.)

ispMACH 4032V/B/C

ispMACH 4064V/B/C

ispMACH 4064Z

Bank

Number Number GLB/MC/Pad

ORP

B^10

B^11

-

B^12

B^13

B^14

B^15

-

GLB/MC/Pad

ORP

D^2

D^3

-

D^4

D^5

D^6

D^7

-

GLB/MC/Pad

ORP

D^5

D^4

-

D^3

D^2

D^1

D^0

-

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

1

-

1

0

B10

B11

TDO

VCC

GND

B12

D4

D6

TDO

VCC

GND

D8

D10

D8

TDO

VCC

GND

D6

B13

B14

D10

D12

D4

D2

B15/GOE1

CLK3/I

CLK0/I

A0/GOE0

A1

D14/GOE1

CLK3/I

CLK0/I

A0/GOE0

A2

D0/GOE1

CLK3/I

CLK0/I

A0/GOE0

A1

-

A^0

A^1

A^2

A^3

A^4

A^0

A^1

A^2

A^3

A^4

A^0

A^1

A^2

A^3

A^4

A2

A3

A4

A6

A8

A2

A4

A6

ispMACH 4032Z and 4064Z Logic Signal Connections: 56-Ball csBGA

ispMACH 4032Z

ispMACH 4064Z

GLB/MC/Pad ORP

Ball Number

Bank Number

GLB/MC/Pad

ORP

B1

C3

C1

D1

D3

E3

E1

F3

F1

G3

G1

H1

J1

K1

K2

H3

K3

K4

H4

H5

-

TDI

A5

A6

A7

-

TDI

A8

A10

A11

-

A^5

A^6

A^7

-

B^7

B^6

B^5

B^4

-

0

-

0

A^5

A^6

A^7

-

A^8

A^9

A^10

A^11

-

GND (Bank 0)

NC

I

VCCO (Bank 0)

A8

A9

A10

A11

NC

TCK

VCC

GND

B15

B12

B10

B8

I

TCK

VCC

GND

I

B6

B4

A12

A13

A14

A^12

A^13

A^14

B^3

B^2

B^1

B2

47

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4032Z and 4064Z Logic Signal Connections: 56-Ball csBGA (Cont.)

ispMACH 4032Z

GLB/MC/Pad

ispMACH 4064Z

GLB/MC/Pad

Ball Number

K5

Bank Number

ORP

A^15

-

ORP

B^0

-

0

1

-

1

-

A15

CLK1/I

CLK2/I

B0

B1

B2

B3

B4

TMS

B5

B6

B7

B0

CLK1/I

CLK2/I

C0

C1

C2

C4

C6

TMS

C8

C10

C11

H6

K6

H7

K7

K8

K9

K10

J10

H8

H10

G10

G8

F8

F10

E8

-

B^0

B^1

B^2

B^3

B^4

-

B^5

B^6

B^7

-

C^0

C^1

C^2

C^3

C^4

-

C^5

C^6

C^7

-

GND (Bank 1)

NC

-

I

-

VCCO (Bank 1)

B8

VCCO (Bank 1)

E10

D8

B^8

B^9

B^10

B^11

-

D15

D12

D10

D8

D^7

D^6

D^5

D^4

-

D^3

D^2

D^1

D^0

-

B9

B10

B11

NC

D10

C10

B10

A10

A9

C8

A8

A7

C7

C6

A6

C5

A5

C4

A4

A3

A2

I

TDO

VCC

GND

NC

-

TDO

VCC

GND

I

D6

D4

-

1

0

B12

B13

B14

B^12

B^13

B^14

B^15

-

D2

B15/GOE1

CLK3/I

CLK0/I

A0/GOE0

A1

D0/GOE1

CLK3/I

CLK0/I

A0/GOE0

A1

-

A^0

A^1

A^2

A^3

A^4

A^0

A^1

A^2

A^3

A^4

A2

A3

A4

A2

A4

A6

A1

48

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064V/B/C/Z, 4128V/B/C/Z, 4256V/B/C/Z Logic Signal Connections:

100-Pin TQFP

ispMACH 4064V/B/C/Z

ispMACH 4128V/B/C/Z

ispMACH 4256V/B/C/Z

Bank

Pin Number

Number

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

1

2

-

GND

-

TDI

-

TDI

-

TDI

-

3

4

5

6

7

8

9

0

-

A8

A9

A10

A11

A^8

A^9

A^10

A^11

-

A^12

A^13

A^14

A^15

-

B0

B2

B4

B6

B^0

B^1

B^2

B^3

-

B^4

B^5

B^6

B^7

-

C12

C10

C6

C2

C^3

C^2

C^1

C^0

-

D^3

D^2

D^1

D^0

-

GND (Bank 0)

A12

A13

A14

A15

B8

B10

B12

B13

D12

D10

D6

D4

10

11

12*

13

14

15

16

17

18

19

20

21

22

23*

24

25

26

27*

28

29

30

31

32

33

34

35

36

37

38

39

40

41

I

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

B15

B14

B13

B12

B^15

B^14

B^13

B^12

-

B^11

B^10

B^9

B^8

-

C14

C12

C10

C8

C^7

C^6

C^5

C^4

-

C^3

C^2

C^1

C^0

-

E4

E6

E10

E12

E^0

E^1

E^2

E^3

-

F^0

F^1

F^2

F^3

-

GND (Bank 0)

B11

B10

B9

B8

C6

C5

C4

C2

F2

F6

F10

F12

I

TCK

VCC

GND

I

B7

B6

B5

B4

-

TCK

VCC

GND

I

D13

D12

D10

D8

-

TCK

VCC

GND

I

G12

G10

G6

G2

-

0

1

-

B^7

B^6

B^5

B^4

-

D^7

D^6

D^5

D^4

-

G^3

G^2

G^1

G^0

-

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

-

B3

B2

B1

B^3

B^2

B^1

B^0

-

D6

D4

D2

D^3

D^2

D^1

D^0

-

H12

H10

H6

H^3

H^2

H^1

H^0

-

I^0

B0

D0

H2

CLK1/I

CLK2/I

VCC

C0

CLK1/I

CLK2/I

VCC

E0

CLK1/I

CLK2/I

VCC

I2

-

1

C^0

E^0

49

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064V/B/C/Z, 4128V/B/C/Z, 4256V/B/C/Z Logic Signal Connections:

100-Pin TQFP (Cont.)

ispMACH 4064V/B/C/Z

ispMACH 4128V/B/C/Z

ispMACH 4256V/B/C/Z

Bank

Pin Number

42

Number

GLB/MC/Pad

ORP

C^1

C^2

C^3

-

GLB/MC/Pad

ORP

E^1

E^2

E^3

-

GLB/MC/Pad

ORP

I^1

I^2

I^3

-

1

-

C1

C2

C3

E2

E4

E6

I6

I10

I12

43

44

45

46

47

48

49

50

VCCO (Bank 1)

GND (Bank 1)

-

GND (Bank 1)

-

GND (Bank 1)

-

C4

C5

C6

C7

C^4

C^5

C^6

C^7

-

E8

E10

E12

E14

E^4

E^5

E^6

E^7

-

J2

J6

J10

J12

J^0

J^1

J^2

J^3

-

51

GND

52

-

TMS

-

TMS

-

TMS

-

53

54

55

56

57

58

59

60

61

62*

63

64

65

66

67

68

69

1

-

C8

C9

C10

C11

C^8

C^9

C^10

C^11

-

C^12

C^13

C^14

C^15

-

F0

F2

F4

F6

F^0

F^1

F^2

F^3

-

F^4

F^5

F^6

F^7

-

K12

K10

K6

K2

K^3

K^2

K^1

K^0

-

L^3

L^2

L^1

L^0

-

GND (Bank 1)

C12

C13

C14

C15

F8

F10

F12

F13

L12

L10

L6

L4

I

VCCO (Bank 1)

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

D15

D14

D13

D12

D^15

D^14

D^13

D^12

-

D^11

D^10

D^9

D^8

-

G14

G12

G10

G8

G^7

G^6

G^5

G^4

-

G^3

G^2

G^1

G^0

-

M4

M6

M10

M12

M^0

M^1

M^2

M^3

-

N^0

N^1

N^2

N^3

-

GND (Bank 1)

D11

D10

D9

D8

G6

G5

G4

G2

N2

N6

N10

N12

70

71

72

73*

74

I

TDO

-

TDO

-

TDO

-

75

-

VCC

-

VCC

-

VCC

-

76

-

GND

-

GND

-

GND

-

77*

78

79

80

81

1

I

-

I

H13

H12

H10

H8

-

I

-

D7

D6

D5

D4

D^7

D^6

D^5

D^4

-

H^7

H^6

H^5

H^4

-

O12

O10

O6

O^3

O^2

O^1

O^0

-

O2

82

GND (Bank 1)

50

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064V/B/C/Z, 4128V/B/C/Z, 4256V/B/C/Z Logic Signal Connections:

100-Pin TQFP (Cont.)

ispMACH 4064V/B/C/Z

ispMACH 4128V/B/C/Z

ispMACH 4256V/B/C/Z

Bank

Pin Number

Number

GLB/MC/Pad

VCCO (Bank 1)

ORP

-

GLB/MC/Pad

VCCO (Bank 1)

ORP

-

GLB/MC/Pad

VCCO (Bank 1)

ORP

-

83

84

85

86

87

88

89

90

1

0

-

D3

D2

D1

D^3

D^2

D^1

D^0

-

H6

H4

H2

H^3

H^2

H^1

H^0

-

P12

P10

P6

P2/OE1

CLK3/I

CLK0/I

VCC

P^3

P^2

P^1

P^0

-

D0/GOE1

CLK3/I

H0/GOE1

CLK3/I

CLK0/I

VCC

CLK0/I

-

VCC

-

91

92

93

94

95

96

97

98

0

A0/GOE0

A^0

A^1

A^2

A^3

-

A0/GOE0

A2

A^0

A^1

A^2

A^3

-

A2/GOE0

A6

A^0

A^1

A^2

A^3

-

A1

A2

A3

A4

A6

A10

A12

VCCO (Bank 0)

GND (Bank 0)

B2

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

A8

-

A4

A5

A6

A7

A^4

A^5

A^6

A^7

A^4

A^5

A^6

A^7

B^0

B^1

B^2

B^3

A10

A12

A14

B6

B10

B12

99

100

*This pin is input only.

ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP

ispMACH 4128V/B/C

Pin Number

Bank Number

GLB/MC/Pad

ORP

-

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

0

GND

TDI

VCCO (Bank 0)

-

B0

B1

B2

B4

B5

B6

B^0

B^1

B^2

B^3

B^4

B^5

-

B^6

B^7

B^8

B^9

B^10

B^11

-

GND (Bank 0)

B8

B9

B10

B12

B13

B14

VCCO (Bank 0)

C14

C^11

51

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.)

ispMACH 4128V/B/C

Pin Number

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

Bank Number

GLB/MC/Pad

ORP

C^10

C^9

C^8

C^7

C^6

-

C^5

C^4

C^3

C^2

C^0

-

0

1

C13

C12

C10

C9

C8

GND (Bank 0)

C6

C5

C4

C2

C0

VCCO (Bank 0)

TCK

VCC

GND

D14

D13

D12

D10

D9

-

D^11

D^10

D^9

D^8

D^7

D^6

-

D8

GND (Bank 0)

VCCO (Bank 0)

-

D6

D5

D4

D2

D1

D0

D^5

D^4

D^3

D^2

D^1

D^0

-

E^0

E^1

E^2

E^3

E^4

E^5

-

CLK1/I

GND (Bank 1)

CLK2/I

VCC

E0

E1

E2

E4

E5

E6

VCCO (Bank 1)

GND (Bank 1)

E8

-

E^6

E^7

E9

52

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.)

ispMACH 4128V/B/C

Pin Number

62

Bank Number

GLB/MC/Pad

ORP

E^8

E^9

E^11

-

1

E10

E12

E14

GND

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

TMS

-

VCCO (Bank 1)

F0

F1

F2

F4

F5

F6

F^0

F^1

F^2

F^3

F^4

F^5

-

F^6

F^7

F^8

F^9

F^10

F^11

-

G^11

G^10

G^9

G^8

G^7

G^6

-

G^5

G^4

G^3

G^2

G^0

-

GND (Bank 1)

F8

F9

F10

F12

F13

F14

VCCO (Bank 1)

G14

G13

G12

G10

G9

G8

GND (Bank 1)

G6

G5

G4

G2

G0

VCCO (Bank 1)

95

96

97

98

TDO

VCC

GND

H14

H13

H12

H10

H9

H8

-

H^11

H^10

H^9

H^8

H^7

H^6

-

99

100

101

102

103

104

GND (Bank 1)

53

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V/B/C Logic Signal Connections: 128-Pin TQFP (Cont.)

ispMACH 4128V/B/C

Pin Number

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

Bank Number

GLB/MC/Pad

VCCO (Bank 1)

ORP

-

1

0

H6

H5

H4

H2

H^5

H^4

H^3

H^2

H^1

H^0

-

A^0

A^1

A^2

A^3

A^4

A^5

-

H1

H0/GOE1

CLK3/I

GND (Bank 0)

CLK0/I

VCC

A0/GOE0

A1

A2

A4

A5

A6

VCCO (Bank 0)

GND (Bank 0)

-

A8

A9

A10

A12

A14

A^6

A^7

A^8

A^9

A^11

ispMACH 4064Z, 4128Z and 4256Z Logic Signal Connections:

132-Ball csBGA

ispMACH 4064Z

Ball Number Bank Number GLB/MC/Pad ORP

ispMACH 4128Z

GLB/MC/Pad ORP

ispMACH 4256Z

GLB/MC/Pad

ORP

B1

B2

C1

C3

C2

D1

D3

D2

E1

E2

E3

F2

-

GND

TDI

NC

A8

A9

A10

A11

NC

-

GND

TDI

VCCO (Bank 0)

-

GND

TDI

VCCO (Bank 0)

-

0

-

B0

B1

B2

B4

B5

B6

B^0

B^1

B^2

B^3

B^4

B^5

-

C12

C10

C8

C6

C4

C2

C^6

C^5

C^4

C^3

C^2

C^1

-

A^8

A^9

A^10

A^11

GND (Bank 0)

NC

-

GND (Bank 0)

D12

B8

B9

B^6

B^7

D^6

D^5

A12

A^12

D10

54

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064Z, 4128Z and 4256Z Logic Signal Connections:

132-Ball csBGA (Cont.)

ispMACH 4064Z

Ball Number Bank Number GLB/MC/Pad ORP

ispMACH 4128Z

ispMACH 4256Z

GLB/MC/Pad

ORP

B^8

B^9

B^10

B^11

-

GLB/MC/Pad

ORP

D^4

D^3

D^2

D^1

-

E^1

E^2

E^3

E^4

E^5

E^6

-

F^1

F^2

F^3

F^4

F^5

F^6

-

F1

F3

G1

G2

G3

H2

H1

H3

J1

J2

J3

K2

K1

K3

L2

0

-

A13

A14

A15

I

A^13

A^14

A^15

-

B^15

B^14

B^13

B^12

-

B^11

B^10

B^9

B^8

-

B10

B12

B13

B14

D8

D6

D4

D2

VCCO (Bank 0)

NC

B15

B14

B13

B12

NC

C14

C13

C12

C10

C9

C8

C^11

C^10

C^9

C^8

C^7

C^6

-

C^5

C^4

C^3

C^2

C^1

C^0

-

E2

E4

E6

E8

E10

E12

GND (Bank 0)

NC

B11

B10

B9

B8

I

NC

TCK

VCC

GND

I

B7

B6

B5

B4

C6

C5

C4

C2

C1

C0

F2

F4

F6

F8

L1

L3

F10

F12

VCCO (Bank 0)

M1

M2

N1

P1

P2

N2

P3

M3

N3

P4

M4

N4

P5

N5

M5

N6

P6

M6

P7

N7

M7

N8

P8

M8

VCCO (Bank 0)

TCK

VCC

GND

D14

D13

D12

D10

D9

-

TCK

VCC

GND

G12

G10

G8

G6

G4

-

0

1

-

D^11

D^10

D^9

D^8

D^7

D^6

-

G^6

G^5

G^4

G^3

G^2

G^1

-

B^7

B^6

B^5

B^4

-

B^3

B^2

B^1

B^0

-

NC

D8

G2

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

-

NC

B3

B2

B1

B0

D6

D5

D4

D2

D1

D^5

D^4

D^3

D^2

D^1

D^0

-

H12

H10

H8

H6

H4

H^6

H^5

H^4

H^3

H^2

H^1

-

I^1

NC

D0

H2

CLK1/I

CLK2/I

VCC

NC

CLK1/I

CLK2/I

VCC

NC

CLK1/I

CLK2/I

VCC

I

1

NC

E0

E^0

I2

55

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064Z, 4128Z and 4256Z Logic Signal Connections:

132-Ball csBGA (Cont.)

ispMACH 4064Z

Ball Number Bank Number GLB/MC/Pad ORP

ispMACH 4128Z

ispMACH 4256Z

GLB/MC/Pad ORP

GLB/MC/Pad

ORP

E^1

E^2

E^3

E^4

E^5

-

P9

N9

M9

1

-

C0

C1

C2

C3

C^0

C^1

C^2

C^3

-

C^4

C^5

C^6

C^7

-

E1

E2

E4

E5

I4

I6

I8

I10

I^2

I^3

I^4

I^5

I^6

-

N10

P10

M10

N11

P11

M11

P12

N12

P13

P14

N14

N13

M14

M12

M13

L14

L12

L13

K14

K13

K12

J13

J14

J12

H14

H13

H12

G13

G14

G12

F14

F13

F12

E13

E14

E12

D13

D14

NC

E6

I12

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

-

GND (Bank 1)

-

NC

C4

C5

C6

C7

NC

GND

E8

E9

E10

E12

E13

E14

GND

E^6

E^7

E^8

E^9

E^10

E^11

-

J2

J4

J6

J8

J10

J12

GND

J^1

J^2

J^3

J^4

J^5

J^6

-

TMS

-

TMS

-

TMS

-

1

NC

C8

C9

C10

C11

NC

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

F0

F1

F2

F4

F5

F6

F^0

F^1

F^2

F^3

F^4

F^5

-

K12

K10

K8

K6

K4

K2

K^6

K^5

K^4

K^3

K^2

K^1

-

C^8

C^9

C^10

C^11

-

GND (Bank 1)

-

GND (Bank 1)

NC

C12

C13

C14

C15

I

F8

F9

F10

F12

F13

F14

F^6

F^7

F^8

F^9

F^10

F^11

-

L12

L10

L8

L6

L4

L2

L^6

L^5

L^4

L^3

L^2

L^1

-

C^12

C^13

C^14

C^15

-

D^15

D^14

D^13

D^12

-

VCCO (Bank 1)

NC

D15

D14

D13

G14

G13

G12

G10

G9

G8

G^11

G^10

G^9

G^8

G^7

G^6

-

M2

M4

M6

M8

M^1

M^2

M^3

M^4

M^5

M^6

-

M10

M12

GND (Bank 1)

D12

GND (Bank 1)

NC

GND (Bank 1)

-

G6

G5

G4

G2

G^5

G^4

G^3

G^2

N2

N4

N6

N8

N^1

N^2

N^3

N^4

D11

D10

D9

D^11

D^10

D^9

56

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4064Z, 4128Z and 4256Z Logic Signal Connections:

132-Ball csBGA (Cont.)

ispMACH 4064Z

Ball Number Bank Number GLB/MC/Pad ORP

ispMACH 4128Z

ispMACH 4256Z

GLB/MC/Pad

ORP

G^1

G^0

-

GLB/MC/Pad

ORP

N^5

N^6

-

D12

C14

C13

B14

A14

A13

B13

A12

C12

B12

A11

C11

B11

A10

B10

C10

B9

1

-

D8

I

NC

TDO

VCC

GND

NC

I

D7

D6

D5

D4

D^8

-

D^7

D^6

D^5

D^4

-

G1

G0

N10

N12

VCCO (Bank 1)

TDO

VCC

GND

H14

H13

H12

H10

H9

-

TDO

VCC

GND

O12

O10

O8

O6

O4

-

1

0

-

H^11

H^10

H^9

H^8

H^7

H^6

-

O^6

O^5

O^4

O^3

O^2

O^1

-

H8

O2

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

-

NC

D3

D2

H6

H5

H4

H2

H^5

H^4

H^3

H^2

H^1

H^0

-

P12

P10

P8

P6

P^6

P^5

P^4

P^3

P^2

P^1

-

D^3

D^2

D^1

D^0

-

A9

C9

A8

B8

C8

B7

D1

H1

P4

P2/GOE1

CLK3/I

CLK0/I

VCC

D0/GOE1

CLK3/I

CLK0/I

VCC

H0/GOE1

CLK3/I

CLK0/I

VCC

-

A7

C7

A6

B6

C6

B5

A5

C5

B4

A4

C4

A3

B3

A2

A1

0

NC

A0/GOE0

-

NC

A0/GOE0

-

I

-

A^0

A^1

A^2

A^3

A^4

A^5

-

A2/GOE0

A^1

A^2

A^3

A^4

A^5

A^6

-

A1

A2

A3

NC

A^0

A^1

A^2

A^3

-

A^4

A^5

A^6

A^7

-

A1

A2

A4

A5

A4

A6

A8

A10

NC

A6

A12

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

-

NC

A4

A5

A6

A7

NC

A8

A9

A10

A12

A13

A14

A^6

A^7

A^8

A^9

A^10

A^11

B2

B4

B6

B8

B10

B12

B^1

B^2

B^3

B^4

B^5

B^6

57

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP

ispMACH 4128V

GLB/MC/Pad

ispMACH 4256V

GLB/MC/Pad

Pin Number

Bank Number

ORP

-

ORP

-

1

-

GND

2

-

TDI

-

TDI

-

3

4

5

6

7

8

9

0

-

0

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

B0

B1

B2

B4

B5

B6

B^0

B^1

B^2

B^3

B^4

B^5

-

B^6

B^7

B^8

B^9

B^10

B^11

-

C12

C10

C8

C6

C4

C2

C^6

C^5

C^4

C^3

C^2

C^1

-

D^7

D^6

D^5

D^4

D^3

D^2

-

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

GND (Bank 0)

B8

B9

B10

B12

D14

D12

D10

D8

B13

D6

B14

D4

NC²

I²

GND (Bank 0)¹

-

NC¹

-

VCCO (Bank 0)

NC²

I²

E2

E4

E6

C14

C13

C12

C10

C9

C8

C^11

C^10

C^9

C^8

C^7

C^6

-

C^5

C^4

C^3

C^2

C^1

C^0

-

E^1

E^2

E^3

E^4

E^5

E^6

-

F^1

F^2

F^3

F^4

F^5

F^6

-

E8

E10

E12

GND (Bank 0)

C6

C5

C4

C2

C1

F2

F4

F6

F8

F10

F12

C0

VCCO (Bank 0)

TCK

VCCO (Bank 0)

-

TCK

VCC

GND

I²

G12

G10

G8

-

0

VCC

GND

NC²

D14

D13

D12

D10

D^11

D^10

D^9

D^8

G^6

G^5

G^4

G^3

G6

58

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.)

ispMACH 4128V

GLB/MC/Pad

ispMACH 4256V

GLB/MC/Pad

Pin Number

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

Bank Number

ORP

D^7

D^6

-

D^5

D^4

D^3

D^2

D^1

D^0

-

ORP

G^2

G^1

-

H^6

H^5

H^4

H^3

H^2

H^1

-

I^1

I^2

I^3

I^4

I^5

I^6

-

0

-

D9

G4

D8

G2

NC²

I²

0

1

-

1

-

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

D6

D5

D4

D2

D1

D0

H12

H10

H8

H6

H4

H2

CLK1/I

GND (Bank 1)

CLK1/I

GND (Bank 1)

-

CLK2/I

VCC

E0

E1

E2

E4

E5

E6

CLK2/I

VCC

I2

I4

I6

I8

I10

I12

E^0

E^1

E^2

E^3

E^4

E^5

-

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

-

E8

E9

E10

E12

E^6

E^7

E^8

E^9

E^10

E^11

-

J2

J4

J6

J8

J^1

J^2

J^3

J^4

J^5

J^6

-

K^6

K^5

K^4

K^3

K^2

K^1

-

L^7

L^6

L^5

E13

J10

E14

J12

NC²

I²

-

GND

TMS

VCCO (Bank 1)

-

GND

TMS

VCCO (Bank 1)

1

F0

F1

F2

F4

F5

F6

F^0

F^1

F^2

F^3

F^4

F^5

-

F^6

F^7

F^8

K12

K10

K8

K6

K4

K2

GND (Bank 1)

L14

GND (Bank 1)

F8

F9

F10

L12

L10

59

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.)

ispMACH 4128V

GLB/MC/Pad

ispMACH 4256V

GLB/MC/Pad

Pin Number

86

Bank Number

ORP

F^9

F^10

F^11

-

ORP

L^4

L^3

L^2

-

1

-

1

-

F12

F13

L8

L6

87

88

89

90

91

92

F14

L4

NC²

I²

GND (Bank 1)¹

NC¹

VCCO (Bank 1)

NC²

I²

93

94

95

96

97

98

99

1

-

G14

G13

G12

G10

G9

G8

G^11

G^10

G^9

G^8

G^7

G^6

-

G^5

G^4

G^3

G^2

G^1

G^0

-

M2

M4

M6

M8

M^1

M^2

M^3

M^4

M^5

M^6

-

N^1

N^2

N^3

N^4

N^5

N^6

-

M10

M12

GND (Bank 1)

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

G6

G5

G4

G2

G1

G0

N2

N4

N6

N8

N10

N12

VCCO (Bank 1)

TDO

VCC

-

TDO

VCC

-

GND

NC²

I²

1

-

1

0

H14

H13

H12

H10

H^11

H^10

H^9

H^8

H^7

H^6

-

O12

O10

O8

O6

O^6

O^5

O^4

O^3

O^2

O^1

-

H9

O4

H8

O2

NC²

I²

GND (Bank 1)

VCCO (Bank 1)

H6

-

GND (Bank 1)

VCCO (Bank 1)

P12

-

H^5

H^4

H^3

H^2

H^1

H^0

-

P^6

P^5

P^4

P^3

P^2

P^1

-

H5

H4

H2

H1

P10

P8

P6

P4

H0/GOE1

CLK3/I

GND (Bank 0)

CLK0/I

P2/GOE1

CLK3/I

GND (Bank 0)

CLK0/1

-

60

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4128V and 4256V Logic Signal Connections: 144-Pin TQFP (Cont.)

ispMACH 4128V

GLB/MC/Pad

ispMACH 4256V

GLB/MC/Pad

Pin Number

129

Bank Number

ORP

-

ORP

-

VCC

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

0

-

A0/GOE0

A^0

A^1

A^2

A^3

A^4

A^5

-

A2/GOE0

A^1

A^2

A^3

A^4

A^5

A^6

-

A1

A2

A4

A5

A4

A6

A8

A10

A6

A12

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

-

A8

A9

A^6

A^7

A^8

A^9

A^10

A^11

-

B2

B4

B6

B8

B10

B12

I²

B^1

B^2

B^3

B^4

B^5

B^6

-

A10

A12

A13

A14

NC²

1. For device migration considerations, these NC pins are GND pins for I/O banks in ispMACH 4128V devices.

2. For device migration considerations, these NC pins are input signal pins in ispMACH 4256V devices.

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

Number

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

1

2

-

NC

-

GND

-

GND

-

GND

-

3

-

TDI

-

TDI

-

TDI

-

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

0

VCCO (Bank 0)

-

VCCO (Bank 0)

-

VCCO (Bank 0)

-

C14

C12

C10

C8

C6

C4

C2

C0

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

D^7

D^6

D^5

D^4

D^3

C14

C12

C10

C8

C6

C4

C2

C0

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

E^7

E^6

E^5

E^4

E^3

C14

C12

C10

C8

C6

C4

C2

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

G^7

G^6

G^5

G^4

G^3

C0

GND (Bank 0)

G14

GND (Bank 0)

D14

D12

D10

D8

E14

E12

E10

E8

G12

G10

G8

G6

D6

E6

61

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP (Cont.)

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

Number

GLB/MC/Pad

ORP

D^2

D^1

D^0

-

GLB/MC/Pad

ORP

E^2

E^1

E^0

-

GLB/MC/Pad

ORP

G^2

G^1

G^0

-

0

-

D4

D2

D0

E4

E2

E0

G4

G2

G0

VCCO (Bank 0)

E0

E2

E4

E6

E8

E10

E12

E14

E^0

E^1

E^2

E^3

E^4

E^5

E^6

E^7

-

H0

H2

H4

H6

H8

H10

H12

H14

H^0

H^1

H^2

H^3

H^4

H^5

H^6

H^7

-

J0

J2

J4

J6

J8

J10

J12

J14

J^0

J^1

J^2

J^3

J^4

J^5

J^6

J^7

-

GND (Bank 0)

F0

F2

F4

F6

F8

F10

F12

F14

F^0

F^1

F^2

F^3

F^4

F^5

F^6

F^7

-

J0

J2

J4

J6

J8

J10

J12

J14

J^0

J^1

J^2

J^3

J^4

J^5

J^6

J^7

-

N0

N2

N4

N6

N8

N10

N12

N14

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

VCCO (Bank 0)

TCK

-

TCK

-

TCK

-

VCC

NC

GND

G14

G12

G10

G8

G6

G4

G2

G0

-

VCC

NC

-

VCC

NC

GND

O14

O12

O10

O8

O6

O4

O2

O0

-

GND (Bank 0)

-

0

G^7

G^6

G^5

G^4

G^3

G^2

G^1

G^0

-

K14

K12

K10

K8

K6

K4

K2

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

-

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O^0

-

K0

GND (Bank 0)

VCCO (Bank 0)

L14

GND (Bank 0)

VCCO (Bank 0)

H14

GND (Bank 0)

VCCO (Bank 0)

P14

-

H^7

H^6

H^5

L^7

L^6

L^5

P^7

P^6

P^5

H12

H10

L12

L10

P12

P10

62

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP (Cont.)

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

60

Number

GLB/MC/Pad

ORP

H^4

H^3

H^2

H^1

H^0

-

GLB/MC/Pad

ORP

L^4

L^3

L^2

L^1

L^0

-

GLB/MC/Pad

ORP

P^4

P^3

P^2

P^1

P^0

-

0

-

H8

H6

L8

L6

P8

P6

P4

61

62

63

64

H4

H2

H0

L4

L2

L0

P2

P0

65

GND

66

67

68

69

0

1

-

CLK1/I

GND (Bank 1)

-

CLK1/I

GND (Bank 1)

-

CLK1/I

GND (Bank 1)

CLK2/I

VCC

-

CLK2/I

VCC

CLK2/I

VCC

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

1

-

I0

I2

I4

I6

I8

I10

I12

I14

I^0

I^1

I^2

I^3

I^4

I^5

I^6

I^7

-

M0

M2

M4

M6

M8

M10

M12

M14

M^0

M^1

M^2

M^3

M^4

M^5

M^6

M^7

-

AX0

AX2

AX4

AX6

AX^0

AX^1

AX^2

AX^3

AX^4

AX^5

AX^6

AX^7

-

AX8

AX10

AX12

AX14

VCCO (Bank 1)

GND (Bank 1)

BX0

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

-

J0

J2

J4

J6

J8

J10

J12

J14

J^0

J^1

J^2

J^3

J^4

J^5

J^6

J^7

-

N0

N2

N4

N6

N8

N10

N12

N14

VCC

NC

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

BX^0

BX^1

BX^2

BX^3

BX^4

BX^5

BX^6

BX^7

-

BX2

BX4

BX6

BX8

BX10

BX12

BX14

VCC

86

87

88

89

VCC

NC

-

NC

-

90

91

92

93

94

95

96

97

-

GND

TMS

VCCO (Bank 1)

-

GND

TMS

VCCO (Bank 1)

O14

O12

O10

O8

-

GND

TMS

-

1

VCCO (Bank 1)

CX14

CX12

CX10

CX8

K14

K12

K10

K8

K6

K4

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O^0

CX^7

CX^6

CX^5

CX^4

CX^3

CX^2

CX^1

CX^0

O6

O4

O2

O0

CX6

CX4

CX2

CX0

98

99

100

K2

K0

63

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP (Cont.)

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

Number

GLB/MC/Pad

GND (Bank 1)

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

1

-

GND (Bank 1)

AX14

AX12

AX10

AX8

GND (Bank 1)

GX14

GX12

GX10

GX8

L14

L12

L10

L8

L6

L4

L2

L0

L^7

L^6

L^5

L^4

L^3

L^2

L^1

L^0

-

AX^7

AX^6

AX^5

AX^4

AX^3

AX^2

AX^1

AX^0

-

DX^0

DX^1

DX^2

DX^3

DX^4

DX^5

DX^6

DX^7

-

FX^0

FX^1

FX^2

FX^3

FX^4

FX^5

FX^6

FX^7

-

GX^7

GX^6

GX^5

GX^4

GX^3

GX^2

GX^1

GX^0

-

JX^0

JX^1

JX^2

JX^3

JX^4

JX^5

JX^6

JX^7

-

NX^0

NX^1

NX^2

NX^3

NX^4

NX^5

NX^6

NX^7

-

AX6

AX4

AX2

AX0

GX6

GX4

GX2

GX0

VCCO (Bank 1)

DX0

VCCO (Bank 1)

JX0

M0

M2

M4

M6

M8

M10

M12

M14

M^0

M^1

M^2

M^3

M^4

M^5

M^6

M^7

-

DX2

DX4

DX6

DX8

JX2

JX4

JX6

JX8

JX10

JX12

JX14

DX10

DX12

DX14

GND (Bank 1)

FX0

GND (Bank 1)

NX0

N0

N2

N4

N6

N8

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

FX2

FX4

FX6

FX8

NX2

NX4

NX6

NX8

N10

N12

N14

VCCO (Bank 1)

TDO

VCC

NC

FX10

FX12

FX14

VCCO (Bank 1)

TDO

NX10

NX12

NX14

VCCO (Bank 1)

TDO

-

VCC

-

VCC

-

NC

-

NC

-

1

NC

-

NC

GND

GX14

GX12

GX10

GX8

GX6

GX4

-

NC

GND

OX14

OX12

OX10

OX8

OX6

OX4

-

GND

O14

O12

O10

O8

O6

O4

O2

O^7

O^6

O^5

O^4

O^3

O^2

O^1

GX^7

GX^6

GX^5

GX^4

GX^3

GX^2

GX^1

OX^7

OX^6

OX^5

OX^4

OX^3

OX^2

OX^1

GX2

OX2

64

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C/Z, 4384V/B/C, 4512V/B/C, Logic Signal Connections:

176-Pin TQFP (Cont.)

ispMACH 4256V/B/C/Z

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Bank

Pin Number

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

Number

GLB/MC/Pad

ORP

O^0

-

GLB/MC/Pad

GX0

GND (Bank 1)

ORP

GX^0

-

GLB/MC/Pad

OX0

GND (Bank 1)

ORP

OX^0

-

1

-

O0

GND (Bank 1)

VCCO (Bank 1)

-

VCCO (Bank 1)

-

VCCO (Bank 1)

-

P14

P12

P10

P8

P^7

P^6

P^5

P^4

P^3

P^2

P^1

P^0

-

HX14

HX12

HX10

HX8

HX6

HX4

HX^7

HX^6

HX^5

HX^4

HX^3

HX^2

HX^1

HX^0

-

PX14

PX12

PX10

PX8

PX6

PX4

PX^7

PX^6

PX^5

PX^4

PX^3

PX^2

PX^1

PX^0

-

P6

P4

P2/GOE1

P0

GND

HX2/GOE1

HX0

PX2/GOE1

PX0

GND

1

0

-

CLK3/I

GND (Bank 0)

CLK0/I

VCC

A0

A2/GOE0

-

CLK3/I

GND (Bank 0)

CLK0/I

VCC

A0

A2/GOE0

A4

-

CLK3/I

GND (Bank 0)

CLK0/I

VCC

A0

A2//GOE0

A4

-

0

-

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

-

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

-

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

-

A4

A6

A8

A10

A12

A14

A6

A8

A10

A12

A6

A8

A10

A12

A14

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

B0

VCCO (Bank 0)

GND (Bank 0)

B0

-

B0

B2

B4

B6

B8

B10

B12

B14

VCC

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

-

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

-

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

-

B2

B4

B6

B8

B10

B12

B14

VCC

B2

B4

B6

B8

B10

B12

B14

VCC

65

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball fpBGA

ispMACH 4256V/B/C

128-I/O

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

VCC

-

GND

-

GND

-

GND

-

GND

-

C3

-

TDI

-

TDI

-

TDI

-

TDI

-

0

VCCO (Bank 0)

B1

F5

D3

C1

C2

E3

D2

F6

D1

E2

E4

G5

E1

-

C14

C12

C10

C8

C6

C4

C2

C0

NC

-

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

D^7

D^6

D^5

D^4

D^3

D^2

D^1

D^0

-

C14

C12

C10

C9

C8

C6

C4

C2

C1

C0

NC

C^9

C^8

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

-

D^9

D^8

D^7

D^6

D^5

D^4

D^3

D^2

D^1

D^0

-

C14

C12

C10

C8

C6

C4

C2

C0

F6

F4

D6

D4

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

F^3

F^2

D^3

D^2

-

C14

C12

C10

C8

C6

C4

C2

C0

H0

H4

F4

F6

C^7

C^6

C^5

C^4

C^3

C^2

C^1

C^0

H^0

H^1

F^2

F^3

F^4

-

NC

F8

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

-

VCCO (Bank 0)

GND (Bank 0)

-

GND (Bank 0)

-

F2

F1

G1

G6

G4

H6

G3

H5

G2

H1

H2

H3

H4

-

NC

D14

D12

D10

D8

D6

D4

D2

NC

D14

D12

D10

D9

D8

D6

D4

D2

D1

NC

D2

D0

F2

F0

E14

E12

E10

E8

E6

E4

E2

F10

F12

F14

H8

H12

G14

G12

G10

G8

G6

G4

G2

F^5

F^6

F^7

H^2

H^3

G^7

G^6

G^5

G^4

G^3

G^2

G^1

G^0

-

D^1

D^0

F^1

F^0

E^7

E^6

E^5

E^4

E^3

E^2

E^1

E^0

-

D0

E0

G0

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

-

J4

J3

J2

J1

K1

J5

K2

E0

E2

E4

E6

E8

E10

E12

E^0

E^1

E^2

E^3

E^4

E^5

E^6

E0

E1

E2

E4

E6

E8

E9

E^0

E^1

E^2

E^3

E^4

E^5

E^6

H0

H2

H4

H6

H8

H^0

H^1

H^2

H^3

H^4

H^5

H^6

J0

J2

J4

J6

J8

J^0

J^1

J^2

J^3

J^4

J^5

J^6

H10

H12

J10

J12

66

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

E^7

-

GLB/MC/Pad

ORP

E^7

E^8

E^9

-

GLB/MC/Pad

ORP

H^7

G^0

G^1

I^7

I^6

-

I^5

I^4

G^2

G^3

J^0

J^1

J^2

J^3

J^4

J^5

J^6

J^7

-

GLB/MC/Pad

ORP

J^7

I^0

I^1

K^0

K^1

K^2

-

J6

K3

K4

L1

L2

M1

-

0

-

E14

NC

E10

E12

E14

NC

H14

G0

G2

I14

I12

NC

J14

I0

I4

K0

K2

K4

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

-

M2

N1

M3

M4

N2

K5

P1

K6

N3

L5

P2

L6

R1

-

NC

F0

F2

F4

F6

F8

F10

F12

NC

F0

F1

F2

F4

F6

F8

F9

F10

F12

-

NC

I10

I8

G4

G6

J0

J2

J4

J6

J8

J10

J12

K6

K8

K10

I8

I12

N0

N2

N4

N6

N8

N10

N12

K^3

K^4

K^5

I^2

I^3

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

F^0

F^1

F^2

F^3

F^4

F^5

F^6

F^7

F^8

F^9

-

F^0

F^1

F^2

F^3

F^4

F^5

F^6

F^7

-

F14

J14

N14

VCCO (Bank 0)

P3

-

TCK

VCC

-

TCK

VCC

-

TCK

VCC

-

TCK

VCC

-

GND

-

GND

-

GND

-

GND

-

0

-

GND (Bank 0)

-

GND (Bank 0)

-

GND (Bank 0)

-

T2

M5

N4

T3

R3

M6

P4

L7

N5

M7

P5

R4

T4

-

NC

G14

G12

G10

G8

G6

G4

G2

G0

NC

G14

G12

G10

G9

G8

G6

G4

G2

G1

G0

NC

G^9

G^8

G^7

G^6

G^5

G^4

G^3

G^2

G^1

G^0

-

I6

I4

K14

K12

K10

K8

K6

K4

K2

K0

G8

G10

NC

I^3

I^2

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

G^4

G^5

-

K12

K14

O14

O12

O10

O8

O6

O4

O2

O0

M0

M4

L0

K^6

K^7

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O^0

M^0

M^1

L^0

-

G^7

G^6

G^5

G^4

G^3

G^2

G^1

G^0

-

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

GND (Bank 0)

VCCO (Bank 0)

-

GND (Bank 0)

VCCO (Bank 0)

-

67

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

-

I^1

GLB/MC/Pad

L4

ORP

L^1

L^2

R5

T5

R6

T6

N7

P7

R7

L8

0

-

NC

H14

H12

H10

H8

H6

H4

H2

NC

H14

H12

H10

H9

H8

H6

H4

H2

H1

NC

I2

I0

G12

G14

L14

L12

L10

L8

L6

L4

L2

L8

L12

M8

M12

P14

P12

P10

P8

P6

P4

P2

P0

-

I^0

L^3

H^9

H^8

H^7

H^6

H^5

H^4

H^3

H^2

H^1

H^0

-

G^6

G^7

L^7

L^6

L^5

L^4

L^3

L^2

L^1

L^0

-

M^2

M^3

P^7

P^6

P^5

P^4

P^3

P^2

P^1

P^0

-

H^7

H^6

H^5

H^4

H^3

H^2

H^1

H^0

-

T7

M8

N8

R8

P8

-

T8

-

N9

-

H0

GND

CLK1/I

GND (Bank 1)

H0

GND

CLK1/I

GND (Bank 1)

L0

GND

CLK1/I

GND (Bank 1)

GND

CLK1/I

GND (Bank 1)

CLK2/I

VCC

0

1

-

CLK2/I

VCC

CLK2/I

VCC

CLK2/I

VCC

P9

R9

T9

1

I0

I2

I4

I6

I8

I10

I12

I14

NC

I^0

I^1

I^2

I^3

I^4

I^5

I^6

I^7

-

I0

I1

I2

I4

I6

I8

I9

I10

I12

I14

NC

I^0

I^1

I^2

I^3

I^4

I^5

I^6

I^7

I^8

I^9

-

M0

M2

M4

M6

M8

M10

M12

M14

BX14

BX12

P0

P2

M^0

M^1

M^2

M^3

M^4

M^5

M^6

M^7

BX^7

BX^6

P^0

P^1

-

AX0

AX2

AX4

AX6

AX^0

AX^1

AX^2

AX^3

AX^4

AX^5

AX^6

AX^7

DX^0

DX^1

EX^0

EX^1

EX^2

-

T10

R10

M9

P10

L9

N10

T11

R11

T12

N12

-

AX8

AX10

AX12

AX14

DX0

DX4

EX0

-

EX4

EX8

VCCO (Bank 1)

GND (Bank 1)

EX12

DX8

NC

VCCO (Bank 1)

GND (Bank 1)

-

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

-

R12

T13

P12

M10

R13

L10

T14

M11

NC

J0

J2

J4

NC

J0

J1

J2

J4

J6

J8

J9

-

NC

BX10

BX8

N0

N2

N4

EX^3

DX^2

DX^3

BX^0

BX^1

BX^2

BX^3

BX^4

J^0

J^1

J^2

J^3

J^4

J^5

J^6

BX^5

BX^4

N^0

N^1

N^2

N^3

N^4

-

DX12

BX0

BX2

BX4

BX6

J^0

J^1

J^2

J^3

J^4

J6

J8

N6

N8

BX8

68

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

J^5

J^6

J^7

-

GLB/MC/Pad

ORP

J^7

J^8

J^9

-

GLB/MC/Pad

ORP

N^5

N^6

N^7

P^2

P^3

-

GLB/MC/Pad

BX10

ORP

BX^5

BX^6

BX^7

FX^0

FX^1

-

R14

P13

N13

M12

T15

-

1

-

J10

J12

J14

NC

VCC

J10

J12

J14

NC

VCC

N10

N12

N14

P4

P6

VCC

BX12

BX14

FX0

FX2

-

VCC

-

GND

-

GND

-

GND

-

GND

-

1

-

GND (Bank 1)

TMS

VCCO (Bank 1)

-

GND (Bank 1)

TMS

VCCO (Bank 1)

-

GND (Bank 1)

TMS

VCCO (Bank 1)

FX4

-

P14

-

TMS

VCCO (Bank 1)

1

L12

R16

N14

P15

L11

P16

K11

M14

K12

N15

N16

M15

M13

-

NC

K14

K12

K10

K8

K6

K4

K2

K0

NC

-

NC

K14

K12

K10

K9

K8

K6

K4

K2

K1

NC

P8

P10

O14

O12

O10

O8

O6

O4

O2

O0

BX6

BX4

FX^2

FX^3

FX^4

CX^7

CX^6

CX^5

CX^4

CX^3

CX^2

CX^1

CX^0

HX^0

HX^1

-

P^4

P^5

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O^0

BX^3

BX^2

-

FX6

FX8

CX14

CX12

CX10

CX8

CX6

CX4

CX2

CX0

HX0

HX4

-

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

-

K^9

K^8

K^7

K^6

K^5

K^4

K^3

K^2

K^1

K^0

-

K0

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

NC

VCCO (Bank 1)

GND (Bank 1)

FX10

-

GND (Bank 1)

-

M16

L15

L16

J11

K15

J12

K13

K14

K16

J16

J15

H16

J13

-

NC

L14

L12

L10

L8

L6

L4

L2

NC

L14

L12

L10

L9

L8

L6

L4

L2

L1

L0

FX^5

FX^6

FX^7

HX^2

HX^3

GX^7

GX^6

GX^5

GX^4

GX^3

GX^2

GX^1

GX^0

-

P12

P14

BX2

BX0

AX14

AX12

AX10

AX8

AX6

AX4

AX2

AX0

P^6

P^7

BX^1

BX^0

AX^7

AX^6

AX^5

AX^4

AX^3

AX^2

AX^1

AX^0

-

FX12

FX14

HX8

HX12

GX14

GX12

GX10

GX8

GX6

GX4

GX2

GX0

L^9

L^8

L^7

L^6

L^5

L^4

L^3

L^2

L^1

L^0

-

L^7

L^6

L^5

L^4

L^3

L^2

L^1

L^0

-

L0

VCCO (Bank 1)

GND (Bank 1)

M0

VCCO (Bank 1)

GND (Bank 1)

DX0

VCCO (Bank 1)

GND (Bank 1)

JX0

-

J14

M0

M^0

DX^0

JX^0

69

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

M^1

M^2

M^3

M^4

M^5

M^6

M^7

-

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

-

GLB/MC/Pad

ORP

M^1

M^2

M^3

M^4

M^5

M^6

M^7

M^8

M^9

-

N^0

N^1

N^2

N^3

N^4

N^5

N^6

N^7

N^8

N^9

-

GLB/MC/Pad

DX2

ORP

DX^1

DX^2

DX^3

DX^4

DX^5

DX^6

DX^7

CX^0

CX^1

EX^7

EX^6

-

GLB/MC/Pad

JX2

ORP

JX^1

JX^2

JX^3

JX^4

JX^5

JX^6

JX^7

IX^0

IX^1

KX^0

KX^1

KX^2

-

H15

H14

H13

G16

H12

G15

H11

F16

G13

G14

F15

E16

-

1

-

M2

M4

M6

M8

M10

M12

M14

NC

M1

M2

M4

M6

M8

M9

M10

M12

M14

NC

DX4

DX6

DX8

DX10

DX12

DX14

CX0

JX4

JX6

JX8

JX10

JX12

JX14

IX0

IX4

CX2

EX14

EX12

NC

KX0

KX2

KX4

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

NC

-

GND (Bank 1)

VCCO (Bank 1)

KX6

-

NC

N0

N2

N4

-

E15

G12

E13

D16

E14

G11

D15

F11

C16

F12

D14

C15

B16

-

NC

N0

N1

N2

N4

N6

N8

N9

N10

N12

KX^3

KX^4

KX^5

IX^2

IX^3

NX^0

NX^1

NX^2

NX^3

NX^4

NX^5

NX^6

NX^7

-

EX10

EX8

CX4

CX6

FX0

FX2

FX4

FX6

FX8

EX^5

EX^4

CX^2

CX^3

FX^0

FX^1

FX^2

FX^3

FX^4

FX^5

FX^6

FX^7

-

KX8

KX10

IX8

IX12

NX0

NX2

NX4

NX6

NX8

N6

N8

N10

N12

N14

VCCO (Bank 1)

TDO

VCC

GND

-

FX10

FX12

FX14

VCCO (Bank 1)

TDO

VCC

GND

GND (Bank 1)

EX6

NX10

NX12

NX14

VCCO (Bank 1)

TDO

N14

VCCO (Bank 1)

C14

-

TDO

VCC

GND

GND (Bank 1)

NC

-

VCC

GND

-

1

GND (Bank 1)

KX12

KX14

OX14

OX12

OX10

OX8

A15

B14

E12

A14

C13

D13

E11

B13

F10

NC

O14

O12

O10

O8

O6

O4

O2

-

EX^3

EX^2

GX^7

GX^6

GX^5

GX^4

GX^3

GX^2

GX^1

KX^6

KX^7

OX^7

OX^6

OX^5

OX^4

OX^3

OX^2

OX^1

NC

O14

O12

O10

O9

O8

O6

O4

EX4

O^7

O^6

O^5

O^4

O^3

O^2

O^1

O^9

O^8

O^7

O^6

O^5

O^4

O^3

GX14

GX12

GX10

GX8

GX6

GX4

OX6

OX4

OX2

GX2

70

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

O^0

-

P^7

P^6

P^5

P^4

P^3

P^2

P^1

P^0

-

GLB/MC/Pad

ORP

O^2

O^1

O^0

-

GLB/MC/Pad

GX0

ORP

GX^0

CX^4

CX^5

-

EX^1

EX^0

CX^6

CX^7

HX^7

HX^6

HX^5

HX^4

HX^3

HX^2

HX^1

HX^0

-

GLB/MC/Pad

ORP

OX^0

MX^0

MX^1

LX^0

-

C12

E10

A13

D12

-

1

-

O0

NC

O2

O1

O0

NC

OX0

MX0

MX4

CX8

CX10

NC

LX0

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

GND (Bank 1)

VCCO (Bank 1)

NC

GND (Bank 1)

VCCO (Bank 1)

LX4

-

B12

A12

B11

A11

D10

C10

B10

A10

A9

F9

B9

E9

C9

-

NC

P14

P12

P10

NC

P14

P12

P10

P9

P8

LX^1

LX^2

LX^3

MX^2

MX^3

PX^7

PX^6

PX^5

PX^4

PX^3

PX^2

PX^1

PX^0

-

EX2

EX0

LX8

LX12

MX8

MX12

PX14

PX12

PX10

PX8

-

P^9

P^8

P^7

P6

P^5

P^4

P^3

P^2

P^1

P^0

CX12

CX14

HX14

HX12

HX10

HX8

P8

P6

P4

P6

P4

P2

HX6

HX4

HX2/GOE1

HX0

PX6

PX4

PX2/GOE1

PX0

P2/GOE1

P0

GND

P1/GOE1

P0

GND

D9

-

B8

-

1

0

-

CLK3/I

GND (Bank 0)

-

CLK3/I

GND (Bank 0)

-

CLK3/I

GND (Bank 0)

CLK0/I

VCC

-

CLK3/I

GND (Bank 0)

CLK0/I

VCC

-

CLK0/I

VCC

CLK0/I

VCC

-

D8

C8

A8

A7

B7

E8

D7

F8

C7

A6

B6

A5

B5

-

0

A0

A2/GOE0

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

-

A0

A1/GOE0

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

A^8

A^9

-

A0

A2/GOE0

A4

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

F^7

F^6

D^7

D^6

-

A0

A2/GOE0

A4

A^0

A^1

A^2

A^3

A^4

A^5

A^6

A^7

D^0

D^1

E^0

E^1

E^2

-

A4

A6

A8

A10

A12

A14

NC

A2

A4

A6

A8

A9

A10

A12

A14

A6

A8

A10

A12

A14

F14

F12

D14

A6

A8

A10

A12

A14

D0

D4

E0

NC

-

D12

NC

E4

E8

NC

VCCO (Bank 0)

GND (Bank 0)

NC

VCCO (Bank 0)

GND (Bank 0)

NC

-

VCCO (Bank 0)

GND (Bank 0)

NC

-

VCCO (Bank 0)

GND (Bank 0)

E12

-

D5

A4

-

E^3

D^2

NC

B0

B^0

F10

F^5

D8

71

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4256V/B/C, 4384V/B/C, 4512V/B/C Logic Signal Connections:

256-Ball fpBGA (Cont.)

ispMACH 4256V/B/C

128-I/O

160-I/O

ispMACH 4384V/B/C

ispMACH 4512V/B/C

Ball

I/O

Number

Bank

GLB/MC/Pad

ORP

-

GLB/MC/Pad

ORP

B^1

B^2

B^3

B^4

B^5

B^6

B^7

B^8

B^9

-

GLB/MC/Pad

ORP

F^4

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

D^5

D^4

-

GLB/MC/Pad

ORP

D^3

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

F^0

F^1

-

E7

A3

F7

B4

C5

A2

E6

B3

C4

D4

E5

-

0

-

NC

B0

B2

B4

B6

B1

B2

B4

B6

B8

B9

B10

B12

B14

NC

VCC

-

F8

B0

B2

B4

B6

B8

B10

B12

B14

D12

B0

B2

B4

B6

B8

B10

B12

B14

B^0

B^1

B^2

B^3

B^4

B^5

B^6

B^7

-

B8

B10

B12

B14

NC

VCC

-

D10

D8

F0

F2

-

VCC

GND

GND (Bank 0)

VCC

GND

GND (Bank 0)

-

0

-

Note: VCC, VCCO and GND are tied together to their respective common signal on the package substrate. See Power Supply and NC Con-

nections table for VCC/ VCCO/GND pin deﬁnitions.

72

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Part Number Description

LC XXXX X X – XX XX XXX X X XX

Production Status

Device Family

Blank = Final production

ES = Engineering Samples

Device Number

4032 = 32 Macrocells

4064 = 64 Macrocells

4128 = 128 Macrocells

4256 = 256 Macrocells

4384 = 384 Macrocells

4512 = 512 Macrocells

Operating Temperature Range

C = Commercial

I = Industrial

E = Automotive

I/O Designator (if applicable)

A = 128 I/Os

Power

Z = Zero Power

Blank = Low Power

B = 160 I/Os

Pin/Ball Count

Supply Voltage

V = 3.3V

B = 2.5V

44 (1.0mm thickness)

48 (1.0mm thickness)

56

100

C = 1.8V

Speed

128

25 = 2.5ns

27 = 2.7ns

3 = 3.0ns

35 = 3.5ns

37 = 3.7ns

42 = 4.2ns

45 = 4.5ns

5 = 5.0ns

75 = 7.5ns

10 = 10.0ns

132

144

176

256

Package

T = TQFP TN = Lead-free TQFP

F = fpBGA FN = Lead-free fpBGA

M = csBGA MN = Lead-free csBGA

ispMACH 4000 Family Speed Grade Offering

-25

-27

-3

-35

-37

-42

-45

-5

-75

Ind

✔

-10

Ind

✔

Com Com Com Com Com Com Com Com

Ind

✔

Com

✔

Auto

✔

1

ispMACH 4032V/B/C

ispMACH 4064V/B/C

ispMACH 4128V/B/C

ispMACH 4256V/B/C

ispMACH 4384V/B/C

ispMACH 4512V/B/C

ispMACH 4032ZC

ispMACH 4064ZC

ispMACH 4128ZC

ispMACH 4256ZC

1. 3.3V only.

✔

1

✔

1

✔

1

✔

73

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

Ordering Information

Note: ispMACH 4000 devices are all dual marked except the slowest commercial speed grade ispMACH 4000Z

devices. For example, the commercial speed grade LC4128C-5T100C is also marked with the industrial grade -75I.

The commercial grade is always one speed grade faster than the associated dual mark industrial grade. The slow-

est commercial speed grade ispMACH 4000Z devices are marked as commercial grade only.

Conventional Packaging

ispMACH 4000ZC (Zero Power, 1.8V) Commercial Devices

Device

Part Number

LC4032ZC-35M56C

LC4032ZC-5M56C

LC4032ZC-75M56C

LC4032ZC-35T48C

LC4032ZC-5T48C

LC4032ZC-75T48C

LC4064ZC-37M132C¹

LC4064ZC-5M132C¹

LC4064ZC-75M132C¹

LC4064ZC-37T100C

LC4064ZC-5T100C

LC4064ZC-75T100C

LC4064ZC-37M56C

LC4064ZC-5M56C

LC4064ZC-75M56C

LC4064ZC-37T48C

LC4064ZC-5T48C

LC4064ZC-75T48C

LC4128ZC-42M132C¹

LC4128ZC-75M132C¹

LC4128ZC-42T100C

LC4128ZC-75T100C

LC4256ZC-45T176C

LC4256ZC-75T176C

LC4256ZC-45M132C¹

LC4256ZC-75M132C¹

LC4256ZC-45T100C

LC4256ZC-75T100C

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

64

32

96

64

128

96

64

Grade

C

PD

32

1.8

3.5

5

7.5

3.5

5

7.5

3.7

5

7.5

3.7

5

7.5

3.7

5

7.5

3.7

5

7.5

4.2

7.5

4.2

7.5

4.5

7.5

4.5

7.5

4.5

7.5

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

56

48

32

64

LC4032ZC

48

132

100

56

48

64

LC4064ZC

48

128

256

132

100

176

132

100

LC4128ZC

LC4256ZC

1. Contact factory for product availability.

ispMACH 4000ZC (1.8V, Zero Power) Industrial Devices

Device

Part Number

LC4032ZC-5M56I

LC4032ZC-75M56I

LC4032ZC-5T48I

LC4032ZC-75T48I

Macrocells Voltage tPD Package Pin/Ball Count

I/O

32

Grade

32

1.8

5

7.5

5

csBGA

TQFP

56

48

I

LC4032ZC

7.5

74

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000ZC (1.8V, Zero Power) Industrial Devices (Cont.)

Device

Part Number

LC4064ZC-5M132I¹

LC4064ZC-75M132I¹

LC4064ZC-5T100I

LC4064ZC-75T100I

LC4064ZC-5M56I

LC4064ZC-75M56I

LC4064ZC-5T48I

LC4064ZC-75T48I

LC4128ZC-75M132I¹

LC4128ZC-75T100I

LC4256ZC-75T176I

LC4256ZC-75M132I¹

LC4256ZC-75T100I

Macrocells Voltage tPD Package Pin/Ball Count

I/O

64

34

32

96

64

128

96

64

Grade

64

1.8

5

7.5

5

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

csBGA

TQFP

132

100

56

I

64

7.5

5

LC4064ZC

64

7.5

5

56

48

64

7.5

48

128

256

132

100

176

132

100

LC4128ZC

LC4256ZC

1. Contact factory for product availability.

ispMACH 4000ZC (1.8V, Zero Power) Automotive Devices

Family

LC4032ZC

Part Number

LC4032ZC-75T48E

LC4064ZC-75T100E

LC4064ZC-75T48E

LC4128ZC-75T100E

LC4256ZC-75T176E

LC4256ZC-75T100E

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

64

32

64

Grade

PD

32

64

1.8

7.5

TQFP

48

100

48

100

176

100

E

LC4064ZC

LC4128ZC

LC4256ZC

64

128

256

128

64

ispMACH 4000C (1.8V) Commercial Devices

Device

Part Number

LC4032C-25T48C

LC4032C-5T48C

LC4032C-75T48C

LC4032C-25T44C

LC4032C-5T44C

LC4032C-75T44C

LC4064C-25T100C

LC4064C-5T100C

LC4064C-75T100C

LC4064C-25T48C

LC4064C-5T48C

LC4064C-75T48C

LC4064C-25T44C

LC4064C-5T44C

LC4064C-75T44C

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

Grade

C

PD

32

64

1.8

2.5

5

7.5

2.5

5

7.5

2.5

5

7.5

2.5

5

TQFP

48

44

LC4032C

44

100

48

44

LC4064C

7.5

2.5

5

7.5

75

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Commercial Devices (Cont.)

Device

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

92

64

Grade

C

PD

LC4128C-27T128C

LC4128C-5T128C

LC4128C-75T128C

LC4128C-27T100C

LC4128C-5T100C

LC4128C-75T100C

LC4256C-3F256AC

LC4256C-5F256AC

LC4256C-75F256AC

LC4256C-3F256BC

LC4256C-5F256BC

LC4256C-75F256BC

LC4256C-3T176C

LC4256C-5T176C

LC4256C-75T176C

LC4256C-3T100C

LC4256C-5T100C

LC4256C-75T100C

LC4384C-35F256C

LC4384C-5F256C

LC4384C-75F256C

LC4384C-35T176C

LC4384C-5T176C

LC4384C-75T176C

LC4512C-35F256C

LC4512C-5F256C

LC4512C-75F256C

LC4512C-35T176C

LC4512C-5T176C

LC4512C-75T176C

128

256

384

512

1.8

2.7

5

7.5

2.7

5

TQFP

fpBGA

TQFP

fpBGA

TQFP

fpBGA

TQFP

128

100

256

176

100

256

176

256

176

LC4128C

64

7.5

3

128

160

128

64

5

7.5

3

5

7.5

3

LC4256C

5

7.5

3

5

64

7.5

3.5

5

7.5

3.5

5

7.5

3.5

5

7.5

3.5

5

192

128

208

128

LC4384C

LC4512C

7.5

ispMACH 4000C (1.8V) Industrial Devices

Family

Part Number

LC4032C-5T48I

LC4032C-75T48I

LC4032C-10T48I

LC4032C-5T44I

LC4032C-75T44I

LC4032C-10T44I

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

Grade

PD

5

32

1.8

TQFP

48

44

I

7.5

10

5

7.5

10

LC4032C

76

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Industrial Devices (Cont.)

Family

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

64

32

30

92

64

128

160

128

64

Grade

PD

5

LC4064C-5T100I

LC4064C-75T100I

LC4064C-10T100I

LC4064C-5T48I

LC4064C-75T48I

LC4064C-10T48I

LC4064C-5T44I

64

1.8

TQFP

fpBGA

TQFP

fpBGA

TQFP

fpBGA

TQFP

100

48

44

I

64

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

LC4064C

LC4064C-75T44I

LC4064C-10T44I

LC4128C-5T128I

LC4128C-75T128I

LC4128C-10T128I

LC4128C-5T100I

LC4128C-75T100I

LC4128C-10T100I

LC4256C-5F256AI

LC4256C-75F256AI

LC4256C-10F256AI

LC4256C-5F256BI

LC4256C-75F256BI

LC4256C-10F256BI

LC4256C-5T176I

LC4256C-75T176I

LC4256C-10T176I

LC4256C-5T100I

LC4256C-75T100I

LC4256C-10T100I

LC4384C-5F256I

LC4384C-75F256I

LC4384C-10F256I

LC4384C-5T176I

LC4384C-75T176I

LC4384C-10T176I

LC4512C-5F256I

LC4512C-75F256I

LC4512C-10F256I

LC4512C-5T176I

LC4512C-75T176I

LC4512C-10T176I

128

256

384

512

128

100

256

176

100

256

176

256

176

LC4128C

LC4256C

64

192

128

208

128

LC4384C

LC4512C

7.5

10

77

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000B (2.5V) Commercial Devices

Device

Part Number

LC4032B-25T48C

LC4032B-5T48C

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

92

Grade

C

PD

32

2.5

5

7.5

2.5

5

7.5

2.5

5

7.5

2.5

5

7.5

2.5

5

7.5

2.7

5

7.5

2.7

5

7.5

3

TQFP

fpBGA

TQFP

fpBGA

TQFP

48

44

LC4032B-75T48C

LC4032B-25T44C

LC4032B-5T44C

LC4032B-75T44C

LC4064B-25T100C

LC4064B-5T100C

LC4064B-75T100C

LC4064B-25T48C

LC4064B-5T48C

32

64

LC4032B

44

100

48

44

LC4064B

LC4128B

LC4064B-75T48C

LC4064B-25T44C

LC4064B-5T44C

LC4064B-75T44C

LC4128B-27T128C

LC4128B-5T128C

LC4128B-75T128C

LC4128B-27T100C

LC4128B-5T100C

LC4128B-75T100C

LC4256B-3F256AC

LC4256B-5F256AC

LC4256B-75F256AC

LC4256B-3F256BC

LC4256B-5F256BC

LC4256B-75F256BC

LC4256B-3T176C

LC4256B-5T176C

LC4256B-75T176C

LC4256B-3T100C

LC4256B-5T100C

LC4256B-75T100C

LC4384B-35F256C

LC4384B-5F256C

LC4384B-75F256C

LC4384B-35T176C

LC4384B-5T176C

LC4384B-75T176C

64

128

256

384

128

100

256

176

100

256

176

92

64

128

160

128

64

5

7.5

3

5

7.5

3

LC4256B

5

7.5

3

5

64

7.5

3.5

5

7.5

3.5

5

192

128

LC4384B

7.5

78

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000B (2.5V) Commercial Devices (Cont.)

Device

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

208

128

Grade

PD

LC4512B-35F256C

LC4512B-5F256C

LC4512B-75F256C

LC4512B-35T176C

LC4512B-5T176C

LC4512B-75T176C

512

2.5

3.5

5

7.5

3.5

5

fpBGA

TQFP

256

176

C

LC4512B

7.5

ispMACH 4000B (2.5V) Industrial Devices

Family

Part Number

LC4032B-5T48I

LC4032B-75T48I

LC4032B-10T48I

LC4032B-5T44I

LC4032B-75T44I

LC4032B-10T44I

LC4064B-5T100I

LC4064B-75T100I

LC4064B-10T100I

LC4064B-5T48I

LC4064B-75T48I

LC4064B-10T48I

LC4064B-5T44I

LC4064B-75T44I

LC4064B-10T44I

LC4128B-5T128I

LC4128B-75T128I

LC4128B-10T128I

LC4128B-5T100I

LC4128B-75T100I

LC4128B-10T100I

LC4256B-5F256AI

LC4256B-75F256AI

LC4256B-10F256AI

LC4256B-5F256BI

LC4256B-75F256BI

LC4256B-10F256BI

LC4256B-5T176I

LC4256B-75T176I

LC4256B-10T176I

LC4256B-5T100I

LC4256B-75T100I

LC4256B-10T100I

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

92

Grade

PD

5

32

2.5

TQFP

fpBGA

TQFP

48

44

I

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

32

64

LC4032B

44

100

48

44

128

100

256

176

100

LC4064B

LC4128B

64

128

256

92

64

128

160

128

64

7.5

10

5

7.5

10

5

LC4256B

7.5

10

64

79

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000B (2.5V) Industrial Devices (Cont.)

Family

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

192

128

208

128

Grade

PD

5

LC4384B-5F256I

LC4384B-75F256I

LC4384B-10F256I

LC4384B-5T176I

LC4384B-75T176I

LC4384B-10T176I

LC4512B-5F256I

LC4512B-75F256I

LC4512B-10F256I

LC4512B-5T176I

LC4512B-75T176I

LC4512B-10T176I

384

512

2.5

fpBGA

TQFP

fpBGA

TQFP

256

176

256

176

I

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

LC4384B

LC4512B

ispMACH 4000V (3.3V) Commercial Devices

Device

Part Number

LC4032V-25T48C

LC4032V-5T48C

LC4032V-75T48C

LC4032V-25T44C

LC4032V-5T44C

LC4032V-75T44C

LC4064V-25T100C

LC4064V-5T100C

LC4064V-75T100C

LC4064V-25T48C

LC4064V-5T48C

LC4064V-75T48C

LC4064V-25T44C

LC4064V-5T44C

LC4064V-75T44C

LC4128V-27T144C

LC4128V-5T144C

LC4128V-75T144C

LC4128V-27T128C

LC4128V-5T128C

LC4128V-75T128C

LC4128V-27T100C

LC4128V-5T100C

LC4128V-75T100C

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

96

92

64

Grade

C

PD

32

3.3

2.5

5

7.5

2.5

5

7.5

2.5

5

7.5

2.5

5

7.5

2.5

5

7.5

2.7

5

7.5

2.7

5

7.5

2.7

5

TQFP

48

44

32

LC4032V

44

64

100

48

44

144

128

100

LC4064V

64

128

LC4128V

7.5

80

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Commercial Devices (Cont.)

Device

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

128

160

128

96

Grade

C

PD

3

5

LC4256V-3F256AC

LC4256V-5F256AC

LC4256V-75F256AC

LC4256V-3F256BC

LC4256V-5F256BC

LC4256V-75F256BC

LC4256V-3T176C

LC4256V-5T176C

LC4256V-75T176C

LC4256V-3T144C

LC4256V-5T144C

LC4256V-75T144C

LC4256V-3T100C

LC4256V-5T100C

LC4256V-75T100C

LC4384V-35F256C

LC4384V-5F256C

LC4384V-75F256C

LC4384V-35T176C

LC4384V-5T176C

LC4384V-75T176C

LC4512V-35F256C

LC4512V-5F256C

LC4512V-75F256C

LC4512V-35T176C

LC4512V-5T176C

LC4512V-75T176C

256

384

512

3.3

fpBGA

TQFP

fpBGA

TQFP

fpBGA

TQFP

256

176

144

100

256

176

256

176

7.5

3

5

7.5

3

LC4256V

5

7.5

3

5

96

64

7.5

3

5

7.5

3.5

5

7.5

3.5

5

7.5

3.5

5

7.5

3.5

5

64

192

128

208

128

LC4384V

LC4512V

C

7.5

ispMACH 4000V (3.3V) Industrial Devices

Family

Part Number

LC4032V-5T48I

LC4032V-75T48I

LC4032V-10T48I

LC4032V-5T44I

LC4032V-75T44I

LC4032V-10T44I

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

Grade

PD

5

32

3.3

TQFP

48

44

I

7.5

10

5

7.5

10

LC4032V

81

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Industrial Devices (Cont.)

Family

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

64

32

30

96

92

64

Grade

PD

5

LC4064V-5T100I

LC4064V-75T100I

LC4064V-10T100I

LC4064V-5T48I

LC4064V-75T48I

LC4064V-10T48I

LC4064V-5T44I

64

3.3

TQFP

fpBGA

TQFP

fpBGA

TQFP

100

48

44

I

64

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

7.5

10

5

LC4064V

LC4064V-75T44I

LC4064V-10T44I

LC4128V-5T144I

LC4128V-75T144I

LC4128V-10T144I

LC4128V-5T128I

LC4128V-75T128I

LC4128V-10T128I

LC4128V-5T100I

LC4128V-75T100I

LC4128V-10T100I

LC4256V-5F256AI

LC4256V-75F256AI

LC4256V-10F256AI

LC4256V-5F256BI

LC4256V-75F256BI

LC4256V-10F256BI

LC4256V-5T176I

LC4256V-75T176I

LC4256V-10T176I

LC4256V-5T144I

LC4256V-75T144I

LC4256V-10T144I

LC4256V-5T100I

LC4256V-75T100I

LC4256V-10T100I

LC4384V-5F256I

LC4384V-75F256I

LC4384V-10F256I

LC4384V-5T176I

LC4384V-75T176I

LC4384V-10T176I

128

256

384

144

128

100

256

176

144

100

256

176

LC4128V

64

128

160

128

96

LC4256V

96

64

192

128

LC4384V

7.5

10

82

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000V (3.3V) Industrial Devices (Cont.)

Family

Part Number

Macrocells Voltage

t

Package Pin/Ball Count

I/O

208

128

Grade

PD

5

LC4512V-5F256I

LC4512V-75F256I

LC4512V-10F256I

LC4512V-5T176I

LC4512V-75T176I

LC4512V-10T176I

512

3.3

fpBGA

TQFP

256

176

I

7.5

10

5

7.5

10

LC4512V

ispMACH 4000V (3.3V) Automotive Devices

Device

Part Number

LC4032V-75T48E

LC4032V-75T44E

LC4064V-75T100E

LC4064V-75T48E

LC4064V-75T44E

LC4128V-75T144E

LC4128V-75T128E

LC4128V-75T100E

LC4256V-75T176E

LC4256V-75T144E

LC4256V-75T100E

Macrocells Voltage

t

Package Pin/Ball Count

I/O

32

30

64

32

30

96

92

64

128

96

64

Grade

PD

32

3.3

7.5

TQFP

48

44

100

48

E

LC4032V

64

LC4064V

LC4128V

LC4256V

44

128

256

144

128

100

176

144

100

83

Lattice Semiconductor

Lead-Free Packaging

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z (Zero Power, 1.8V) Lead-Free Commercial Devices

Pin/Ball

Device

Part Number

Macrocells Voltage

t

Package

3.5 Lead-free csBGA

Lead-free csBGA

Count

I/O

32

64

32

96

64

128

96

64

Grade

C

PD

LC4032ZC-35MN56C

LC4032ZC-5MN56C

LC4032ZC-75MN56C

LC4032ZC-35TN48C

LC4032ZC-5TN48C

LC4032ZC-75TN48C

LC4064ZC-37MN132C¹

LC4064ZC-5MN132C¹

LC4064ZC-75MN132C¹

LC4064ZC-37TN100C

LC4064ZC-5TN100C

LC4064ZC-75TN100C

LC4064ZC-37MN56C

LC4064ZC-5MN56C

LC4064ZC-75MN56C

LC4064ZC-37TN48C

LC4064ZC-5TN48C

LC4064ZC-75TN48C

LC4128ZC-42MN132C¹

LC4128ZC-75MN132C¹

LC4128ZC-42TN100C

LC4128ZC-75TN100C

LC4256ZC-45TN176C

LC4256ZC-75TN176C

LC4256ZC-45MN132C¹

LC4256ZC-75MN132C¹

LC4256ZC-45TN100C

LC4256ZC-75TN100C

32

1.8

56

48

5

32

64

7.5 Lead-free csBGA

3.5 Lead-free TQFP

LC4032ZC

5

Lead-free TQFP

7.5 Lead-free TQFP

3.7 Lead-free csBGA

48

132

100

56

48

5

Lead-free csBGA

7.5 Lead-free csBGA

3.7 Lead-free TQFP

64

5

Lead-free TQFP

7.5 Lead-free TQFP

3.7 Lead-free csBGA

LC4064ZC

5

Lead-free csBGA

7.5 Lead-free csBGA

3.7 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

4.2 Lead-free csBGA

7.5 Lead-free csBGA

4.2 Lead-free TQFP

7.5 Lead-free TQFP

4.5 Lead-free TQFP

7.5 Lead-free TQFP

4.5 Lead-free csBGA

7.5 Lead-free csBGA

4.5 Lead-free TQFP

7.5 Lead-free TQFP

48

128

256

132

100

176

132

100

LC4128ZC

LC4256ZC

1. Contact factory for product availability.

ispMACH 4000Z (Zero Power, 1.8V) Lead-Free Industrial Devices

Pin/Ball

Device

Part Number

LC4032ZC-5MN56I

LC4032ZC-75MN56I

LC4032ZC-5TN48I

LC4032ZC-75TN48I

Macrocells Voltage

t

Package

Lead-free csBGA

Count

56

I/O

32

Grade

PD

5

32

1.8

I

7.5 Lead-free csBGA

Lead-free TQFP

7.5 Lead-free TQFP

56

48

LC4032ZC

5

84

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000Z (Zero Power, 1.8V) Lead-Free Industrial Devices (Cont.)

Pin/Ball

Device

Part Number

Macrocells Voltage

t

Package

Lead-free csBGA

Count

I/O

64

32

96

64

128

96

64

Grade

PD

5

LC4064ZC-5MN132I¹

LC4064ZC-75MN132I¹

LC4064ZC-5TN100I

LC4064ZC-75TN100I

LC4064ZC-5MN56I

LC4064ZC-75MN56I

LC4064ZC-5TN48I

64

1.8

132

100

56

48

132

100

176

132

100

I

7.5 Lead-free csBGA

Lead-free TQFP

7.5 Lead-free TQFP

Lead-free csBGA

7.5 Lead-free csBGA

Lead-free TQFP

7.5 Lead-free TQFP

7.5 Lead-free csBGA

7.5 Lead-free TQFP

7.5 Lead-free csBGA

7.5 Lead-free TQFP

64

5

LC4064ZC

5

64

5

LC4064ZC-75TN48I

LC4128ZC-75MN132I¹

LC4128ZC-75TN100I

LC4256ZC-75TN176I

LC4256ZC-75MN132I¹

LC4256ZC-75TN100I

128

256

LC4128ZC

LC4256ZC

1. Contact factory for product availability.

ispMACH 4000Z (Zero Power, 1.8V) Lead-Free Automotive Devices

Pin/Ball

Device

LC4032ZC

Part Number

LC4032ZC-75TN48E

LC4064ZC-75TN100E

LC4064ZC-75TN48E

LC4128ZC-75TN100E

LC4256ZC-75TN176E

LC4256ZC-75TN100E

Macrocells Voltage

t

Package

Count

48

I/O

32

64

32

64

Grade

PD

32

64

1.8

7.5 Lead-free TQFP

E

100

48

100

176

100

LC4064ZC

LC4128ZC

LC4256ZC

64

128

256

128

64

ispMACH 4000C (1.8V) Lead-Free Commercial Devices

Pin/Ball

Count

Device

Part Number

LC4032C-25TN48C

LC4032C-5TN48C

LC4032C-75TN48C

LC4032C-25TN44C

LC4032C-5TN44C

LC4032C-75TN44C

Macrocells Voltage

t

Package

2.5 Lead-free TQFP

Lead-free TQFP

I/O

32

30

Grade

PD

32

1.8

48

44

C

5

7.5 Lead-free TQFP

2.5 Lead-free TQFP

LC4032C

5

Lead-free TQFP

7.5 Lead-free TQFP

85

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Lead-Free Commercial Devices (Cont.)

Pin/Ball

Device

Part Number

Macrocells Voltage

t

Package

2.5 Lead-free TQFP

Lead-free TQFP

Count

I/O

64

32

30

92

64

128

160

128

64

Grade

C

PD

LC4064C-25TN100C

LC4064C-5TN100C

LC4064C-75TN100C

LC4064C-25TN48C

LC4064C-5TN48C

LC4064C-75TN48C

LC4064C-25TN44C

LC4064C-5TN44C

64

1.8

100

48

44

64

5

7.5 Lead-free TQFP

2.5 Lead-free TQFP

LC4064C

5

Lead-free TQFP

7.5 Lead-free TQFP

2.5 Lead-free TQFP

5

Lead-free TQFP

LC4064C-75TN44C

LC4128C-27TN128C

LC4128C-5TN128C

LC4128C-75TN128C

LC4128C-27TN100C

LC4128C-5TN100C

LC4128C-75TN100C

LC4256C-3FN256AC

LC4256C-5FN256AC

LC4256C-75FN256AC

LC4256C-3FN256BC

LC4256C-5FN256BC

LC4256C-75FN256BC

LC4256C-3TN176C

LC4256C-5TN176C

LC4256C-75TN176C

LC4256C-3TN100C

LC4256C-5TN100C

LC4256C-75TN100C

LC4384C-35FN256C

LC4384C-5FN256C

LC4384C-75FN256C

LC4384C-35TN176C

LC4384C-5TN176C

LC4384C-75TN176C

LC4512C-35FN256C

LC4512C-5FN256C

LC4512C-75FN256C

LC4512C-35TN176C

LC4512C-5TN176C

LC4512C-75TN176C

7.5 Lead-free TQFP

2.7 Lead-free TQFP

128

256

384

512

128

100

256

176

100

256

176

256

176

5

Lead-free TQFP

7.5 Lead-free TQFP

2.7 Lead-free TQFP

LC4128C

5

Lead-free TQFP

7.5 Lead-free TQFP

3

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3

5

Lead-free fpBGA

7.5 Lead-free fpBGA

LC4256C

3

5

Lead-free TQFP

7.5 Lead-free TQFP

3

5

Lead-free TQFP

64

7.5 Lead-free TQFP

3.5 Lead-free fpBGA

192

128

208

128

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3.5 Lead-free TQFP

LC4384C

LC4512C

5

Lead-free TQFP

7.5 Lead-free TQFP

3.5 Lead-free fpBGA

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3.5 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

86

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Lead-Free Industrial Devices

Pin/Ball

Count

Device

Part Number

LC4032C-5TN48I

Macrocells Voltage

t

Package

Lead-free TQFP

I/O

32

30

64

32

30

92

Grade

PD

5

32

1.8

48

44

I

LC4032C-75TN48I

LC4032C-10TN48I

LC4032C-5TN44I

LC4032C-75TN44I

LC4032C-10TN44I

LC4064C-5TN100I

LC4064C-75TN100I

LC4064C-10TN100I

LC4064C-5TN48I

7.5 Lead-free TQFP

10 Lead-free TQFP

32

64

LC4032C

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

44

5

Lead-free TQFP

100

48

44

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

LC4064C

LC4128C

LC4064C-75TN48I

LC4064C-10TN48I

LC4064C-5TN44I

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

LC4064C-75TN44I

LC4064C-10TN44I

LC4128C-5TN128I

LC4128C-75TN128I

LC4128C-10TN128I

LC4128C-5TN100I

LC4128C-75TN100I

LC4128C-10TN100I

LC4256C-5FN256AI

LC4256C-75FN256AI

LC4256C-10FN256AI

LC4256C-5FN256BI

LC4256C-75FN256BI

LC4256C-10FN256BI

LC4256C-5TN176I

LC4256C-75TN176I

LC4256C-10TN176I

LC4256C-5TN100I

LC4256C-75TN100I

LC4256C-10TN100I

LC4384C-5FN256I

LC4384C-75FN256I

LC4384C-10FN256I

LC4384C-5TN176I

LC4384C-75TN176I

LC4384C-10TN176I

64

10 Lead-free TQFP

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

128

256

384

5

128

100

256

176

100

256

176

92

64

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

64

5

Lead-free fpBGA

128

160

128

64

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free fpBGA

7.5 Lead-free fpBGA

10 Lead-free fpBGA

LC4256C

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

64

5

Lead-free fpBGA

192

128

7.5 Lead-free fpBGA

10 Lead-free fpBGA

LC4384C

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

87

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (1.8V) Lead-Free Industrial Devices (Cont.)

Pin/Ball

Device

Part Number

Macrocells Voltage

t

Package

Lead-free fpBGA

Count

I/O

208

128

Grade

PD

5

LC4512C-5FN256I

LC4512C-75FN256I

LC4512C-10FN256I

LC4512C-5TN176I

LC4512C-75TN176I

LC4512C-10TN176I

512

1.8

256

176

I

7.5 Lead-free fpBGA

10 Lead-free fpBGA

LC4512C

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

ispMACH 4000C (3.3V) Lead-Free Commercial Devices

Pin/Ball

Count

Device

Part Number

LC4032V-25TN48C

LC4032V-5TN48C

LC4032V-75TN48C

LC4032V-25TN44C

LC4032V-5TN44C

LC4032V-75TN44C

LC4064V-25TN100C

LC4064V-5TN100C

LC4064V-75TN100C

LC4064V-25TN48C

LC4064V-5TN48C

LC4064V-75TN48C

LC4064V-25TN44C

LC4064V-5TN44C

LC4064V-75TN44C

LC4128V-27TN144C

LC4128V-5TN144C

LC4128V-75TN144C

LC4128V-27TN128C

LC4128V-5TN128C

LC4128V-75TN128C

LC4128V-27TN100C

LC4128V-5TN100C

LC4128V-75TN100C

Macrocells Voltage

t

Package

2.5 Lead-free TQFP

Lead-free TQFP

I/O

32

30

64

32

30

96

92

64

Grade

C

PD

32

3.3

48

44

5

32

7.5 Lead-free TQFP

2.5 Lead-free TQFP

LC4032V

5

Lead-free TQFP

7.5 Lead-free TQFP

2.5 Lead-free TQFP

44

64

100

48

44

144

128

100

5

Lead-free TQFP

7.5 Lead-free TQFP

2.5 Lead-free TQFP

LC4064V

64

5

Lead-free TQFP

7.5 Lead-free TQFP

2.5 Lead-free TQFP

5

Lead-free TQFP

64

7.5 Lead-free TQFP

2.7 Lead-free TQFP

128

5

Lead-free TQFP

7.5 Lead-free TQFP

2.7 Lead-free TQFP

LC4128V

5

Lead-free TQFP

7.5 Lead-free TQFP

2.7 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

88

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (3.3V) Lead-Free Commercial Devices (Cont.)

Pin/Ball

Device

Part Number

Macrocells Voltage

t

Package

Lead-free fpBGA

Count

I/O

128

160

128

96

Grade

C

PD

3

5

LC4256V-3FN256AC

LC4256V-5FN256AC

LC4256V-75FN256AC

LC4256V-3FN256BC

LC4256V-5FN256BC

LC4256V-75FN256BC

LC4256V-3TN176C

LC4256V-5TN176C

LC4256V-75TN176C

LC4256V-3TN144C

LC4256V-5TN144C

LC4256V-75TN144C

LC4256V-3TN100C

LC4256V-5TN100C

LC4256V-75TN100C

LC4384V-35FN256C

LC4384V-5FN256C

LC4384V-75FN256C

LC4384V-35TN176C

LC4384V-5TN176C

LC4384V-75TN176C

LC4512V-35FN256C

LC4512V-5FN256C

LC4512V-75FN256C

LC4512V-35TN176C

LC4512V-5TN176C

LC4512V-75TN176C

256

384

512

3.3

256

176

144

100

256

176

256

176

7.5 Lead-free fpBGA

3

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3

5

Lead-free TQFP

LC4256V

7.5 Lead-free TQFP

3

5

Lead-free TQFP

96

64

7.5 Lead-free TQFP

3

5

Lead-free TQFP

7.5 Lead-free TQFP

3.5 Lead-free fpBGA

64

192

128

208

128

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3.5 Lead-free TQFP

LC4384V

LC4512V

5

Lead-free TQFP

7.5 Lead-free TQFP

3.5 Lead-free fpBGA

5

Lead-free fpBGA

7.5 Lead-free fpBGA

3.5 Lead-free TQFP

C

5

Lead-free TQFP

7.5 Lead-free TQFP

ispMACH 4000C (3.3V) Lead-Free Industrial Devices

Pin/Ball

Count

Device

Part Number

LC4032V-5TN48I

LC4032V-75TN48I

LC4032V-10TN48I

LC4032V-5TN44I

LC4032V-75TN44I

LC4032V-10TN44I

Macrocells Voltage

t

Package

Lead-free TQFP

I/O

32

30

Grade

PD

5

32

3.3

48

44

I

7.5 Lead-free TQFP

10 Lead-free TQFP

LC4032V

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

89

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (3.3V) Lead-Free Industrial Devices (Cont.)

Pin/Ball

Device

Part Number

Macrocells Voltage

t

Package

Lead-free TQFP

Count

I/O

64

32

30

96

92

64

Grade

PD

5

LC4064V-5TN100I

LC4064V-75TN100I

LC4064V-10TN100I

LC4064V-5TN48I

LC4064V-75TN48I

LC4064V-10TN48I

LC4064V-5TN44I

64

3.3

100

48

44

I

64

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

LC4064V

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

LC4064V-75TN44I

LC4064V-10TN44I

LC4128V-5TN144I

LC4128V-75TN144I

LC4128V-10TN144I

LC4128V-5TN128I

LC4128V-75TN128I

LC4128V-10TN128I

LC4128V-5TN100I

LC4128V-75TN100I

LC4128V-10TN100I

LC4256V-5FN256AI

LC4256V-75FN256AI

LC4256V-10FN256AI

LC4256V-5FN256BI

LC4256V-75FN256BI

LC4256V-10FN256BI

LC4256V-5TN176I

LC4256V-75TN176I

LC4256V-10TN176I

LC4256V-5TN144I

LC4256V-75TN144I

LC4256V-10TN144I

LC4256V-5TN100I

LC4256V-75TN100I

LC4256V-10TN100I

LC4384V-5FN256I

LC4384V-75FN256I

LC4384V-10FN256I

LC4384V-5TN176I

LC4384V-75TN176I

LC4384V-10TN176I

10 Lead-free TQFP

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

128

256

384

5

144

128

100

256

176

144

100

256

176

5

Lead-free TQFP

LC4128V

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

64

5

Lead-free fpBGA

128

160

128

96

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free fpBGA

7.5 Lead-free fpBGA

10 Lead-free fpBGA

5

Lead-free TQFP

LC4256V

7.5 Lead-free TQFP

10 Lead-free TQFP

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

96

64

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

64

5

Lead-free fpBGA

192

128

7.5 Lead-free fpBGA

10 Lead-free fpBGA

LC4384V

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

90

Lattice Semiconductor

ispMACH 4000V/B/C/Z Family Data Sheet

ispMACH 4000C (3.3V) Lead-Free Industrial Devices (Cont.)

Pin/Ball

Device

Part Number

Macrocells Voltage

t

Package

Lead-free fpBGA

Count

I/O

208

128

Grade

PD

5

LC4512V-5FN256I

LC4512V-75FN256I

LC4512V-10FN256I

LC4512V-5TN176I

LC4512V-75TN176I

LC4512V-10TN176I

512

3.3

256

176

I

7.5 Lead-free fpBGA

10 Lead-free fpBGA

LC4512V

5

Lead-free TQFP

7.5 Lead-free TQFP

10 Lead-free TQFP

ispMACH 4000C (3.3V) Lead-Free Automotive Devices

Pin/Ball

Count

48

44

100

48

Device

Part Number

LC4032V-75TN48E

LC4032V-75TN44E

LC4064V-75TN100E

LC4064V-75TN48E

LC4064V-75TN44E

LC4128V-75TN144E

LC4128V-75TN128E

LC4128V-75TN100E

LC4256V-75TN176E

LC4256V-75TN144E

LC4256V-75TN100E

Macrocells Voltage

t

Package

I/O

32

30

64

32

30

96

92

64

128

96

64

Grade

PD

32

3.3

7.5 Lead-free TQFP

E

LC4032V

64

LC4064V

LC4128V

LC4256V

44

128

256

144

128

100

176

144

100

For Further Information

In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH

4000V/B/C/Z family:

• ispMACH 4000 Timing Model Design and Usage Guidelines (TN1004)

• ispMACH 4000V/B/C/Z Power Consumption (TN1005)

• Low Power Design Guide (TN1042)

91


型号：	LC4256ZC-45T100C
厂家：	LATTICE SEMICONDUCTOR
描述：	3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs 3.3V / 2.5V / 1.8V在系统可编程超快高密度的客运专线可编程逻辑器件光电二极管输入元件时钟
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LC4256ZC-45T100C [LATTICE]

相关型号：

LC4256ZC-45T176C

LC4256ZC-45TN100C

LC4256ZC-45TN176C

LC4256ZC-75M132C

LC4256ZC-75M132C1

LC4256ZC-75M132I

LC4256ZC-75MN132C

LC4256ZC-75MN132I

LC4256ZC-75T100C

LC4256ZC-75T100E

LC4256ZC-75T100I

LC4256ZC-75T176C