LC5512MV-75FN484C [LATTICE]
3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family; 3.3V , 2.5V和1.8V在系统可编程扩展可编程逻辑器件XPLD ™产品系列型号: | LC5512MV-75FN484C |
厂家: | LATTICE SEMICONDUCTOR |
描述: | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
文件: | 总92页 (文件大小:601K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TM
ispXPLD 5000MX Family
3.3V, 2.5V and 1.8V In-System Programmable
eXpanded Programmable Logic Device XPLD™ Family
March 2006
Data Sheet
■ Expanded In-System Programmability (ispXP™)
• Instant-on capability
Features
■ Flexible Multi-Function Block (MFB)
Architecture
• Single chip convenience
• In-System Programmable via IEEE 1532
Interface
• Infinitely reconfigurable via IEEE 1532 or
sysCONFIG™ microprocessor interface
• Design security
• SuperWIDE™ logic (up to 136 inputs)
• Arithmetic capability
• Single- or Dual-port SRAM
• FIFO
• Ternary CAM
■ High Speed Operation
■ sysCLOCK™ PLL Timing Control
• Multiply and divide between 1 and 32
• Clock shifting capability
• 4.0ns pin-to-pin delays, 300MHz f
• Deterministic timing
MAX
■ Low Power Consumption
• External feedback capability
• Typical static power: 20 to 50mA (1.8V),
30 to 60mA (2.5/3.3V)
■ sysIO™ Interfaces
• LVCMOS 1.8, 2.5, 3.3V
– Programmable impedance
– Hot-socketing
• 1.8V core for low dynamic power
■ Easy System Integration
• 3.3V (5000MV), 2.5V (5000MB) and 1.8V
(5000MC) power supply operation
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
– Flexible bus-maintenance (Pull-up, pull-
down, bus-keeper, or none)
– Open drain operation
• SSTL 2, 3 (I & II)
• HSTL (I, III, IV)
• PCI 3.3
• GTL+
• LVDS
• LVPECL
• IEEE 1149.1 interface for boundary scan testing
• sysIO quick configuration
• Density migration
• Multiple density and package options
• PQFP and fine pitch BGA packaging
• Lead-free package options
• LVTTL
Table 1. ispXPLD 5000MX Family Selection Guide
ispXPLD 5256MX ispXPLD 5512MX ispXPLD 5768MX ispXPLD 51024MX
Macrocells
256
8
512
16
768
24
1,024
32
Multi-Function Blocks
Maximum RAM Bits
Maximum CAM Bits
sysCLOCK PLLs
128K
48K
256K
384K
144K
2
512K
192K
2
96K
2
2
t
(Propagation Delay)
4.0ns
2.2ns
2.8ns
300MHz
75K
4.5ns
2.8ns
3.0ns
275MHz
150K
5.0ns
2.8ns
3.2ns
250MHz
225K
193/317
5.2ns
3.0ns
3.7ns
250MHz
300K
317/381
PD
t (Register Set-up Time)
S
t
f
(Register Clock to Out Time)
CO
(Maximum Operating Frequency)
MAX
System Gates
I/Os
141
149/193/253
Packages
208 PQFP
256 fpBGA
484 fpBGA
256 fpBGA
256 fpBGA
484 fpBGA
484 fpBGA
672 fpBGA
© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
5kmx_12.2
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Figure 1. ispXPLD 5000MX Block Diagram
ISP Port
VCCO0
VREF0
VCCO3
VREF3
MFB
MFB
MFB
MFB
sysIO
Bank 0
sysIO
Bank 3
GCLCK0
VCCP
GCLCK3
GCLK2
Global
Routing
Pool
sysCLOCK
PLL 0
sysCLOCK
PLL 1
GNDP
(GRP)
GCLK1
sysIO
Bank 1
sysIO
Bank 2
MFB
MFB
MFB
MFB
RESET
GOE0
GOE1
Optional
sysCONFIG
Interface
VREF1
VCCO1
VREF2
VCCO2
Introduction
The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic
Devices (XPLDs). These devices extend the capability of Lattice’s popular SuperWIDE ispMACH 5000 architecture
by providing flexible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM
operation. Extra logic has also been included to allow efficient implementation of arithmetic functions. In addition,
sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers.
The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design
security, and extreme reconfigurability. The use of advanced process technology provides industry-leading perfor-
mance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and oper-
ating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The
ispXPLD 5000MX architecture provides predictable deterministic timing.
The availability of 3.3, 2.5 and 1.8V versions of these devices along with the flexibility of the sysIO interface helps
users meet the challenge of today’s mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O
bank is configured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases inte-
gration into today’s complex systems. A variety of density and package options increase the likelihood of a good fit
for a particular application. Table 1 shows the members of the ispXPLD 5000MX family.
Architecture
The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool.
Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD
2
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
5000MX. Incoming signals may connect to the global routing pool or the registers in the MFBs. An Output Sharing
Array (OSA) increases the number of I/O available to each MFB, allowing a complete function high-performance
access to the I/O. There are four clock pins that drive four global clock nets within the device. Two sysCLOCK PLLs
are provided to allow the synthesis of new clocks and control of clock skews.
Multi-Function Block (MFB)
Each MFB in the ispXPLD 5000MX architecture can be configured in one of the six following modes. This provides
a flexible approach to implementing logic and memory that allows the designer to achieve the mix of functions that
are required for a particular design, maximizing resource utilization. The six modes supported by the MFB are:
• SuperWIDE Logic Mode
• True Dual-port SRAM Mode
• Pseudo Dual-port SRAM Mode
• Single-port SRAM Mode
• FIFO Mode
• Ternary CAM Mode
The MFB consists of a multi-function array and associated routing. Depending on the chosen functions the multi-
function array uses up to 68 inputs from the GRP and the four global clock and reset signals. The array outputs
data along with certain control functions to the macrocells. Output signals can be routed internally for use else-
where in the device and to the sysIO banks for output. Figure 2 shows the block diagram of the MFB. The various
configurations are described in more detail in the following sections.
Figure 2. MFB Block Diagram
To Routing
Multifunction Array
True Dual Port
RAM
(8,192 bit)
Pseudo Dual
Port RAM
(16,384 bit)
Single Port
RAM
(16,384 bit)
FIFO
(16,384 bit)
Ternary CAM
(128*48)
Logic
(68 Input * 164 Product
Term Array, 32 MC)
PTOE
Sharing
Cascade Out
3
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Cascading For Wide Operation
In several modes it is possible to cascade adjacent MFBs to support wider operation. Table 2 details the different
cascading options. There are chains of MFBs in each device which determine those MFBs that are adjacent for the
purposes of cascading. Table 3 indicates these chains. The ispXPLD 5000MX design tools automatically cascade
blocks if required by a particular design.
Table 2. Cascading Modes For Wide Support
Mode
Logic
Cascading Function
Input Width. Allows two MFBs to act as a 136-input block.
Arithmetic. Allow the carry chain to pass between two MFBs.
FIFO
CAM
Memory Width Expansion. Allows MFBs to be cascaded for greater width support.
Memory Width Expansion. Allows up to four MFBs to be cascaded for greater width support.
Table 3. MFB Cascade Chain
Device
MFBs in Cascade Chain
A → B → C → D
H -> G -> F -> E
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
A → B → C → D → E → F → G → H
P → Ο → N → M → L → K → J → I
D → C → B → A → X → W → V → U → T → S → R → Q
E → F → G → H → I → J → K → L → M → N → O → P
H → G → F → E → D → C → B → A → AF → AE → AD → AC → AB → AA → Z → Y
I → J → K → L → M → N → O → P → Q → R → S → T → U → V → W → X
SuperWIDE Logic Mode
In logic mode, each MFB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic
product terms and four control product terms. The MFB has 68 inputs from the Global Routing Pool, which are
available in both true and complement form for every product term. It is also possible to cascade adjacent MFBs to
create a block with 136 inputs. The four control product terms are used for shared reset, clock, clock enable, and
output enable functions. Figure 3 shows the overall structure of the MFB in logic mode while Figure 4 provides a
more detailed view from the perspective of a macrocell slice.
4
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Figure 3. MFB in SuperWIDE Logic Mode†
To Routing
68 Inputs
from
Routing
68 Inputs
from
Adjacent
MFB
Shared PT Clk
Shared PT Clk En
Shared PT Reset
PTOE
Sharing
Carry Out
Figure 4. Macrocell Slice in Logic Mode AND-Array
From
GRP
From Carry-in
n-7
PT OE to
I/O Block
From
I/O Cell
68
PTSA Bypass
Output
to I/O Block or
Internal Control
(See Pin Table
D
Q
PTSA
for Assignments)
Shared
PT CE
PT Clock
Clk En
GRP
R/L
Shared PTCLK
CLK0
Clk
P
CLK1
CLK2
CLK3
R
PT Preset
PT Reset
Shared PT Reset
Global Reset
AND Array
Dual-OR Array
Macrocell
Carry-out
To
n+7
5
Lattice Semiconductor
AND-Array
ispXPLD 5000MX Family Data Sheet
The programmable AND-Array consists of 68 inputs and 164 output product terms.The 68 inputs from the GRP are
used to form 136 lines in the AND-Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 164 output product terms via a wired AND. Each of the 160 logic product terms feed the Dual-
OR Array with the remaining four control product terms feeding the Shared PT Clock, Shared PT Clock Enable,
Shared PT Reset and Shared PT OE. Starting with PT0 sets of five product terms form product term clusters.
There is one product term cluster for every macrocell in the MFB. In addition to the four control product terms, the
first, third, fourth and fifth product terms of each cluster can be used as a PTOE, PT Clock, PT Preset and PT
Reset, respectively. Figure 5 is a graphical representation of the AND-Array.
Figure 5. AND Array
In[0]
In[66]
In[67]
PT0
PT1
PT2
PT3
PT4
Cluster 0
PT155
PT156
PT157
PT158
PT159
Cluster 31
PT160 Shared clock enable
PT161 Shared clock
PT162 Shared reset
PT163 Shared OE
Note:
Indicates programmable fuse.
Dual-OR Array (Including Arithmetic Support)
The Dual-OR Array consists of 64 OR gates. There are two OR gates per macrocell in the MFB. These OR gates
are referred to as the Expandable PTSA OR gate and the PTSA-Bypass OR gate. The PTSA-Bypass OR gate
receives its five inputs from the combination of product terms associated with the product term cluster. The PTSA-
Bypass OR gate feeds the macrocell directly for fast narrow logic. The Expandable PTSA OR gate receives five
inputs from the combination of product terms associated with the product term cluster. It also receives an additional
input from the Expanded PTSA OR gate of the N-7 macrocell, where N is the number of the macrocell associated
with the current OR gate. The Expandable PTSA OR gate feeds the PTSA for sharing with other product terms and
the N+7 Expandable PTSA OR gate. This allows cascading of multiple OR gates for wide functions. There is a
small timing adder for each level of expansion. Figure 6 is a graphical representation of the Dual-OR Array.
The Dual-OR PT sharing array also contains logic to aid in the efficient implementation of arithmetic functions. This
logic takes Carry In and allows the generation of Carry Out along with a SUM signal. Subtractors can be imple-
mented using the two’s complement method. Carry is propagated from macrocells 0 to macrocell 31. Macrocell
zero can have its carry input connected to the carry output of macrocell 31 in an adjacent MFB or it can be set to
zero or one. If a macrocell is not used in an arithmetic function carry can bypass it. The carry chain flows is the
same as that for PT cascading.
6
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Figure 6. Dual-OR PT Sharing Array
From Carry
n-7
In
To I/O Block
PT OE
From PT0
From PT1
To Macrocell
PTSA Bypass
N
To PTSA
From PT2
From PT3
To Macrocell
PT Clock
To Macrocell
PT Preset
From PT4
To Macrocell
PT Reset
Carry
Out
To
n+7
Product Term Sharing Array
The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array (Expandable PTSA OR) and
32 outputs directly to the macrocells. Each output is the OR term of any combination of the seven Expandable
PTSA OR terms connected to that output. Every Nth macrocell is connected to N-3, N-2, N-1, N, N+1, N+2 and
N+3 PTSA OR terms via a programmable connection. This wraps around the logic, for example, Macrocell 0 gets
its logic from 29, 30, 31, 0, 1, 2, 3. The Expandable PTSA OR used in conjunction with the PTSA allows wide func-
tions to be implemented easily and efficiently. Without using the Expandable PTSA OR capability, the greatest
number of product terms that can be included in a single function with one pass of delay is 35. Up to 160 product
terms can be included in a single function through the use of the expandable PTSA OR capability. Figure 7 shows
the graphical representation of the PTSA.
Figure 7. Product Term Sharing Array (PTSA)
PTSA OR 0
Macrocell 0
Macrocell 1
Macrocell 2
PTSA OR 1
PTSA OR 2
PTSA OR 3
PTSA OR 29
Macrocell 29
PTSA OR 30
Macrocell 30
PTSA OR 31
Macrocell 31
7
Lattice Semiconductor
Macrocell
ispXPLD 5000MX Family Data Sheet
The 32 registered macrocells in the MFB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks
and control logic to allow combinatorial or registered operation. All macrocells have an output that feeds the GRP.
Selected macrocells have an additional output that feeds the OSA and hence I/Os. This dual or concurrent output
capability from the macrocell gives efficient use of the hardware resources. One output can be a registered function
for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O
cell facilitates efficient use of the macrocell to construct high-speed input registers. Macrocell registers can be
clocked from one of several global or product term clocks available on the device. A global and product term clock
enable is also provided, eliminating the need to gate the clock to the macrocell registers directly. Reset and preset
for the macrocell register is provided from both global and product term signals. The macrocell register can be pro-
grammed to operate as a D-type register or a D-type latch. Figure 8 is a graphical representation of the macrocell.
Figure 8. Macrocell
From
I/O Cell
PTSA Bypass
Output to
I/O Block
D
Q
From PTSA
PT Clock
Shared
PT CE
Clk En
GRP
R/L
Shared PT Clock
CLK0
Clk
P
CLK1
CLK2
CLK3
R
PT Preset
PT Reset
Shared PT Reset
Global Reset
Memory Modes
The ispXPLD 5000MX architecture allows the MFB to be configured as a variety of memory blocks as detailed in
Table 4. The remainder of this section details operation of each of the memory modes. Additional information
regarding the memory modes can also be found in technical note number TN1030, Using Memory in ispXPLD
5000MX Devices.
8
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Table 4. MFB Memory Configuration
Max. Configuration
Size1
Memory Mode
Dual-port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 8
512 x 16
Single-port, Pseudo Dual Port, FIFO
16,384 x1
8,192 x 2
4,096 x 4
2,048 x 8
1,024 x 16
512 x 32
CAM
128 x 48
1. Smaller configurations are possible.
Input and Output
The data input and control signals to a MFB in memory mode are generated from inputs from the routing. Data sig-
nals are only available in the true non-inverted format. True or complemented versions of the inputs are available
for generating the control signals. Data and flag outputs are fed from the MFB to the GRP and OSA. Unused inputs
and outputs are not accessible in memory mode.
ROM Operation
In each of the memory modes it is possible to specify the power-on state of each bit in the memory array. This
allows the memory to be used as ROM if desired.
Increased Depth And Width
Designs that require a memory depth or width that is greater than that support by a single MFB can be supported
by cascading multiple blocks. For dual port, single port, and pseudo dual port modes additional width is easily pro-
vided by sharing address lines. Additional depth is supported by multiplexing the RAM output. For FIFO and CAM
modes additional width is supported through the cascading of MFBs.
The Lattice design tools automatically combine blocks to support the memory size specified in the user’s design.
Bus Size Matching
All of the memory modes apart from CAM mode support different widths on each of the ports. The RAM bits are
mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of
words for each port varies this mapping scheme applies to each port.
9
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
True Dual-Port SRAM Mode
In Dual-Port SRAM Mode the multi-function array is configured as a dual port SRAM. In this mode two independent
read/write ports access the same 8,192-bits of memory. Data widths of 1, 2, 4, 8, and 16 are supported by the
MFB. Figure 9 shows the block diagram of the dual port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Resets are asynchronous. All inputs on the same port share the same
clock, clock enable, and reset selections. All outputs on the same port share the same clock, clock enable, and
reset selections. Selections may be made independently between both inputs and outputs and ports. Table 5
shows the possible sources for the clock, clock enable and initialization signals for the various registers.
Figure 9. Dual-Port SRAM Block Diagram
CLK0
PORT A
CLK1
CLK2
RD Data A
Read/Write Address
CLK3
(DOA[0:0-15])
(ADA[0:8-12])
RESET
Reset A (RSTA)
Clock A (CLKA)
Clk En A (CENA)
Write/Read A (WRA)
Chip Sel A (CSA [0:1])
Dual
Port
SRAM
Array
68 Inputs
From
Routing
Write Data
(DIA[0:0,1,3,7,15])
PORT B
Similar signals
RD Data B
as PORT A:
(DOB[0:0-15])
ADB[0:8-12], RSTB,
CLKB, CENB, WRB,
CSB[0,1], DIB[0:0,1,3,7,15]
Table 5. Register Clock, Clock Enable, and Reset in Dual-Port SRAM Mode
Register
Input
Clock
Source
CLKA (CLKB) or one of the global clocks (CLK0 - CLK3). The selected sig-
nal can be inverted if desired.
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
CENA (CENB) or one of the global clocks (CLK1 - CLK 2). The selected sig-
nal can be inverted if required.
Clock Enable
Reset
Created by the logical OR of the global reset signal and RSTA (RSTB).
RSTA (RSTB) can be inverted is desired.
10
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Pseudo Dual-Port SRAM Mode
In Pseudo Dual-Port SRAM Mode the multi-function array is configured as a SRAM with an independent read and
write ports that access the same 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 10 shows the block diagram of the Pseudo Dual-Port SRAM.
Write data, write address, chip select and write enable signals are always synchronous (registered). The read data
and read address signals can be synchronous or asynchronous. Reset is asynchronous. All write signals share the
same clock, and clock enable. All read signals share the same clock and clock enable. Reset is shared by both
read and write signals. Table 6 shows the possible sources for the clock, clock enable and initialization signals for
the various registers.
Figure 10. Pseudo Dual-Port SRAM Block Diagram
CLK0
CLK1
Read Address
CLK2
Read Data
(RAD[0:8-13])
CLK3
RESET
(RD[0:0-15])
Write Address
(WAD[0:8-13])
Write Data
16,384 bit
Pseudo
Dual
Port
SRAM
(WD[0:0,1,3,7,15,31])
Write Enable (WE)
Write Clock (WCLK)
68 Inputs
From
Routing
Write Chip Sel (WCS[0,1])
Array
Write Clk Enable (WCEN)
Read Clk Enable (RCEN)
Read Clock (RCLK)
Reset (RST)
Table 6. Register Clock, Clock Enable, and Reset in Pseudo Dual-Port SRAM Mode
Register
Input
Clock
Source
WCLK or one of the global clocks (CLK0 - CLK3). The selected signal can
be inverted if desired.
Write Address, Write
Data, Write Enable,
and Write Chip Select
Clock Enable WCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
be inverted if desired.
Reset
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
Clock
RCLK or one of the global clocks (CLK0 - CLK3).The selected signal can be
inverted if desired.
Read Data and Read Clock Enable RCEN or one of the global clocks (CLK1 - CLK2). The selected signal can
Address
be inverted if desired.
Reset
Created by the logical OR of the global reset signal and RST. RST may have
inversion if desired.
11
Lattice Semiconductor
Single-Port SRAM Mode
ispXPLD 5000MX Family Data Sheet
In Single-Port SRAM Mode the multi-function array is configured as a single-port SRAM. In this mode one ports
accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the MFB. Figure 11 shows
the block diagram of the single-port SRAM.
Write data, address, chip select and read/write signals are always synchronous (registered.) The output data sig-
nals can be synchronous or asynchronous. Reset is asynchronous. All signals share a common clock, clock
enable, and reset. Table 7 shows the possible sources for the clock, clock enable and reset signals.
Figure 11. Single-Port SRAM Block Diagram
CLK0
CLK1
CLK2
Read Data
(DO[0-0,31])
Read/Write Address
(AD[0-8:13])
CLK3
RESET
Write Data
(DI[0-0,1,3,7,15,31])
Write/Read (WR)
Clock (CLK)
16,384-Bit
SRAM
68 Inputs
from
Routing
Array
Chip Select (CS0,1)
Clk Enable (CEN)
Reset (RST)
Table 7. Register Clock, Clock Enable, and Reset in Single-Port SRAM Mode
Register
Input
Clock
Source
CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can
be inverted if required.
Address, Write Data,
Read Data, Read/
Write, and Chip
Select
Clock Enable CEN or one of the global clocks (CLK1 - CLK 2). Each of these signals can
be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed
by the multifunction array from GRP, with inversion if desired.
12
Lattice Semiconductor
FIFO Mode
ispXPLD 5000MX Family Data Sheet
In FIFO Mode the multi-function array is configured as a FIFO (First In First Out) buffer with built in control. The
read and write clocks can be different or the same dependent on the application. Four flags show the status of the
FIFO; Full, Empty, Almost Full, and Almost Empty. The thresholds for Full, Almost full and Almost empty are pro-
grammable by the user. It is possible to reset the read pointer, allowing support of frame retransmit in communica-
tions applications. If desired, the block can be used in show ahead mode allowing the early reading of the next read
address.
In this mode one ports accesses 16,384-bits of memory. Data widths of 1, 2, 4, 8, 16 and 32 are supported by the
MFB. Figure 12 shows the block diagram of the FIFO.
Write data, write enable, flag outputs and read enable are synchronous. The Write Data, Almost Full and Full share
the same clock and clock enables. Read outputs are synchronous although these can be configured in look ahead
mode. The Read Data, Empty and Almost Empty signals share the same clock and clock enables. Reset is shared
by all signals. Table 8 shows the possible sources for the clock, clock enable and reset signals for the various reg-
isters.
Figure 12. FIFO Block Diagram
Write Enable (WE)
CLK0
CLK1
Write Clock (WCLK)
CLK2
CLK3
RESET
FIFO
Reset (RST)
FIFO
Control
Logic
Flags*
Full, Empty,
Almost Full,
Almost Empty
Read Clock (RCLK)
Reset_RP (RSTRP)
Read Enable (RE)
68 Inputs
From
Routing
Write Data
(DI[0:0-31])
Read Data
(DO[0:0-31])
16,384-bit
SRAM
Array
*Control logic can be
duplicated in adjacent MFB
in 32-bit mode
Table 8. Register Clocks, Clock Enables, and Initialization in FIFO Mode
Register
Input
Clock
Source
Write Data,
Write Enable
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Clock
Enable
Reset
Clock
N/A
Full and
Almost Full
Flags
WCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Clock
Enable
Reset
Clock
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
Read Data,
Empty and
AlmostEmpty
Flags
RCLK or one of the global clocks (CLK0 - CLK3). Each of these signals can be inverted if required.
RE or one of the global clocks (CLK1 - CLK 2). Each of these signals can be inverted if required.
Clock
Enable
Reset
Created by the logical OR of the global reset signal and RST. RST is routed by the multifunction
array from GRP, with inversion if desired.
13
Lattice Semiconductor
CAM Mode
ispXPLD 5000MX Family Data Sheet
In CAM Mode the multi-function array is configured as a Ternary Content Addressable Memory (CAM). CAM
behaves like a reverse memory where the input is data and the output is an address. It can be used to perform a
variety of high-performance look-up functions. As such, CAM has two modes of operation. In write or update mode
the CAM behaves as a RAM and data is written to the supplied address. In read or compare operations data is sup-
plied to the CAM and if this matches any of the data in the array the Match and Multiple Match (if there is more than
one match) flags are set to true and the lowest address with matching data is output. The CAM contains 128
entries of 48 bits. Figure 13 shows the block diagram of the CAM.
To further enhance the flexibility of the CAM a mask register is available. If enabled during updates, bits corre-
sponding with those set to 1 in the mask register are not updated. If enabled during compare operations, bits corre-
sponding to those set to 1 in the mask register are not included in the compare. A write don’t care signal allows
don’t cares to be programmed into the CAM if desired. Like other write operations the mask register controls this.
The write/comp data, write address, write enable, write chip select, and write don’t care signals are synchronous.
The CAM Output signals, match flag, and multimatch flag can be synchronous or asynchronous. The Enable mask
register input is not latched but must meet setup and hold times relative to the write clock. All inputs must use the
same clock and clock enable signals. All outputs must use the same clock and clock enable signals. Reset is com-
mon for both inputs and outputs. Table 9 shows the allowable sources for clock, clock enable, and reset for the var-
ious CAM registers.
Figure 13. CAM Mode
CLK0
Write/Comp Data
CLK1
CLK2
(WD[0:31])
CLK3
RESET
CAM
Output
Write Address
(WAD[0:6])
CO[0:6]
En Mask Reg (EN_MASK)
Write Enable (WE)
128X48
CAM
Match
Out
MATCH
Write Chip Sel (WCS[0:1])
68 Inputs
From
Routing
WR Mask Reg (WR_MASK)
WR don t care (WR_DC)
Reset (RST)
Multi-
CLK (CLK)
match
Out
MUL_MATCH
Clock Enable (CE)
Table 9. Register Clocks, Clock Enables, and Initialization in CAM Mode
Register
Input
Clock
Source
CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can
be inverted if required.
Write data, Write address,
Enable mask register, Write
enable, write chip select, and
write don’t care, CAM Output,
Match, and Multimatch
Clock Enable WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can
be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed
by the multifunction array from GRP, with inversion if desired
14
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Clock Distribution
The ispXPLD 5000MX family has four dedicated clock input pins: GCLK0-GCLK3. GLCK0 and GCLK3 can be
routed through a PLL circuit or routed directly to the internal clock nets. The internal clock nets (CLK0-CLK3) are
directly related to the dedicated clock pins (see Secondary Clock Divider exception when using the sysCLOCK cir-
cuit). These feed the registers in the MFBs. Note at each register there is the option of inverting the clock if
required. Figure 14 shows the clock distribution network.
Figure 14. Clock Distribution Network
I/O/CLK_OUT0
GCLK0
CLK0
To Macrocells
To Macrocells
Clock Net
Clock Net
CLK_OUT0
SEC_OUT0
VREF0
PLL0
CLK1
GCLK1
VREF1
sysCLOCK PLLs
Global Clock Routing
VREF2
GCLK2
To Macrocells
To Macrocells
Clock Net
CLK2
SEC_OUT1
PLL1
VREF3
GCLK3
CLK_OUT1
Clock Net
CLK3
I/O/CLK_OUT1
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset and feedback
signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and gener-
ate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are de-
skewed either at the board level or the device level.
The ispXPLD 5000MX devices provide two PLL circuits. PLL0 receives its clock inputs from GCLK 0 and provides
outputs to CLK 0 (CLK 1 when using the secondary clock). PLL1 operates with signals from GCLK 3 and CLK 3
(CLK 2 when using the secondary clock). The optional outputs CLK_OUT can be routed to an I/O pin. The optional
PLL_LOCK output is routed into the GRP. The optional input PLL_RST can be routed either from the GRP or
directly from an I/O pin. The optional PLL_FBK into can be routed directly from a pin. Figure 15 shows the ispXPLD
5000MX PLL block diagram. Figure 16 shows the connection of optional inputs and outputs.
15
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Figure 15. PLL Block Diagram
Input Clock
(M) Divider
Post-scalar
(V) Divider
CLK_OUT
PLL_LOCK
CLK_IN
Clock Net
VCO
and
Phase
Detector
Programable
Delay
PLL_RST
Feedback
Loop
Secondary
Clock
SEC_OUT
Clock Net
(N) Divider
(K) Divider
PLL_FBK
Figure 16. Connection of Optional PLL Inputs and Outputs
To GRP
PLL_LOCK
CLK_OUT
I/O Pin*
From Macrocell
To GRP
PLL_RST
I/O Pin*
To GRP
From Macrocell
To GRP
PLL_FBK
I/O Pin*
From Macrocell
*See pinout table for details
In order to facilitate the multiply and divide capabilities of the PLL, each PLL has dividers associated with it: M, N
and K. The M divider is used to divide the clock signal, while the N divider is used to multiply the clock signal. The
K divider is only used when a secondary clock output is needed. This divider divides the primary clock output and
feeds to a separate global clock net. The V divider is used to provide lower frequency output clocks, while maintain-
ing a stable, high frequency output from the PLL’s VCO circuit.The PLL also has a delay feature that allows the out-
put clock to be advanced or delayed to improve set-up and clock-to-out times for better performance. For more
information on the PLL, please refer to Lattice technical note number TN1003, Lattice sysCLOCK PLL Usage
Guidelines.
16
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Output Sharing Array (OSA)
A number of I/O pads are available in each sysIO bank to route the selected number of macrocells from the MFB
outputs directly to the I/O pads in logic mode. In the ispXPLD 5000MX, the large number of inputs and PTs to the
MFB as well as the presence of the PTSA can cover most routing flexibility of signals to I/O cells. The Output Shar-
ing Array gives additional routing capability and I/O access to an MFB when a wide output function takes up the
whole MFB and cannot be easily divided across multiple MFBs. By using the OSA, the wide output function, such
as 32-bit FIFO, can have all of its output signals from the one MFB routed to I/O cells. In a given I/O block, the wide
output functions must share the I/O pads with other logic functions.
The OSA bypass option routes the MFB signal directly to the I/O cell, allowing a direct connection to the I/O cell.
The logic functions use the option to provide faster speed to the outputs. The Logic Signal Connection tables list
the OSA bypass as the primary macrocell and OSA options as alternate macrocells. Similarly, the Alternate Input
listing in the table shows the alternate macrocell input connection for a given I/O pin. Figure 17 shows the alternate
macrocell connections in an I/O cell.
sysIO Banks
The ispXPLD 5000MX devices are divided into four sysIO banks, consisting of multiple I/O cells, where each bank
is capable of supporting 16 different I/O standards. Each sysIO bank has its own I/O voltage (V
) and reference
CCO
voltage (V
) resources allowing complete independence from the others.
REF
I/O Cell
The I/O cell of the ispXPLD 5000MX devices contains an output enable (OE) MUX, a programmable tri-state output
buffer, a programmable input buffer, and programmable bus-maintenance circuitry.
The I/O cell receives inputs from its associated macrocells and the device pin.The I/O cell has a feedback line to its
associated macrocells and a direct path to GRP. The output enable (OE) MUX selects the OE signal per I/O cell.
The inputs to the OE MUX are the four global PTOE signals, PTOE and the two GOE signals. The OE MUX also
has the ability to choose either the true or inverse of each of these signals.The output of the OE MUX goes through
a logical AND with the TOE signal to allow easy tri-stating of the outputs for testing purposes. The MFBs are
grouped into segments of four for the purpose of generating Shared PTOE signals. Each Shared PTOE signal is
derived from PT 163 from one of the four MFBs. Table 10 shows the segments. The PTOE signal is derived from
the first product term in each macrocell cluster, which is directly routed to the OE MUX. Therefore, every I/O cell
can have a different OE signal. Figure 17 is a graphical representation of the I/O cell.
17
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Figure 17. I/O Cell
Shared PTOE 0
Shared PTOE 1
Shared PTOE 2
Shared PTOE 3
PTOE
Output Buffer
(VCCO Independent
for Open Drain
Outputs)
VCCO for
this Bank
GOE0
GOE1
TOE
Data Output from
Primary Macrocell
VCCO to All
Other I/Os
in Bank
Data Output from
Alternate Macrocells
Differential
Output Buffer
GND
Output Sharing
Array (OSA)
I/O
Pad
CMOS/TTL
Input Buffer
To Adjacent I/O Pad
(VREF Independent)
Data Input to Routing
Delay Element
+
–
To Primary
Macrocell
V
REF to All
other I/Os in Bank
VREF Dependent
Input Buffer
To Alternate
Macrocell
+
–
Differential
I/O Buffer
To Adjacent
I/O Pad
Table 10. Shared PTOE Segments
Device
MFBs Associated With Segments
ispXPLD 5256MX
ispXPLD 5512MX
(A, B, C, D) (E, F, G, H)
(A, B, C, D) (E, F, G, H)
(I, J, K, L) (M, N, O, P)
ispXPLD 5768MX
ispXPLD 51024MX
(A, B, C, D) (E, F, G, H)
(I, J, K, L) (M, N, O, P)
(Q, R, S, T) (U, V, W, Z)
(A, B, C, D) (E, F, G, H)
(I, J, K, L) (M, N, O, P)
(Q, R, S, T) (U, V, W, Z)
(Y, Z, AA, AB) (AC, AD, AE, AF)
sysIO Standards
Each I/O within a bank is individually configurable based on the V
and V
settings. Some standards also
CCO
REF
require the use of an external termination voltage. Table 12 lists the sysIO standards with the typical values for
and V For more information on the sysIO capability, please refer to Lattice technical note number
V
V
CCO, REF
TT.
TN1000, sysIO Usage Guidelines for Lattice Devices, available at www.latticesemi.com.
Table 11. Number of I/Os per Bank
Device
Maximum Number of I/Os per Bank (n)
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
36
68
96
96
18
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Table 12. ispXPLD 5000MX Supported I/O Standards
sysIO Standard
Nominal V
3.3V
3.3V
2.5V
1.8V
3.3V
3.3V
3.3V
2.5V
3.3V
2.5V
1.5V
1.5V
1.5V
N/A
Nominal V
N/A
Nominal V
N/A
CCO
REF
TT
LVTTL
LVCMOS-3.3
LVCMOS-2.5
LVCMOS-1.8
PCI 3.3V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
AGP-1X
N/A
N/A
SSTL3, Class I & II
SSTL2, Class I & II
CTT 3.3
1.5V
1.25V
1.5V
1.25V
0.75V
0.9V
0.9V
1.0V
N/A
1.5V
1.25V
1.5V
1.25V
0.75V
0.75V
0.75V
1.5V
N/A
CTT 2.5
HSTL, Class I
HSTL, Class III
HSTL, Class IV
GTL+
LVPECL, Differential
LVDS
2.5V, 3.3V
2.5V, 3.3V
N/A
N/A
Table 13. Differential Interface Standard Support1
sysIO Buffer
Driver
Supported
LVDS
Receiver
Driver
Supported with standard termination
Supported with external resistor network
Supported with termination
LVPECL
Receiver
1. For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines for Lattice Devices, available at
www.latticesemi.com.
Control, Clock, sysCONFIG and JTAG Signals
Global clock pins support the same sysIO standards as general purpose I/O. When required the V
signal is
REF
derived from the adjacent bank. When differential standards are supported two adjacent clock pins are paired to
form the input. The TOE, PROGRAM, CFG0 and DONE pins of the ispXPLD 5000MX device are the only pins that
do not have sysIO capabilities. The JTAG TAP pins support only LVCMOS 3.3, 2.5 and 1.8V standards. The voltage
is controlled by V
These pins only support the LVTTL and LVCMOS standards applicable to the power supply
CCJ.
voltage of the device. The global reset global output enable pins are associated with Bank 2 and support all of the
sysIO standards.
Hotsocketing
The I/O on the ispXPLD 5000MX devices are well suited for those applications that require hot socketing capability,
when configured as LVCMOS or LVTTL. Hot socketing a device requires that the device, when powered down, can
tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the
powered-down device be minimal on active signals.
Programmable Drive Strength
The drive strength of I/Os that are programmed as LVCMOS is tightly controlled and can be programmed to a vari-
ety of different values. Thus the impedance an output driver can be closely match to the characteristic impedance
of the line it is driving. This allows users to eliminate the need for external series termination resistors.
19
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Programmable Slew Rate
The slew rate of outputs is carefully controlled. When outputs are configured as LVCMOS the devices support two
slew rates. This allows system noise and performance to be balanced in a design.
Programmable Bus-Maintenance
All general-purpose inputs have programmable bus maintenance circuitry. These are intended to maintain a valid
logic level into a device when driving devices go into the tri-state mode. Four options are available for users: pull-
up, pull-down, bus-keeper, or nothing.
Expanded In-System Programmability (ispXP)
The ispXPLD 5000MX family utilizes a combination of EEPROM non-volatile cells and SRAM technology to deliver
a logic solution that provides “instant-on” at power-up, a convenient single chip solution, and the capability for infi-
nite reconfiguration. A non-volatile array distributed within the device stores the device configuration. At power-up
this information is transferred in a massively parallel fashion into SRAM bits that control the operation of the device.
Figure 18 shows the different ports and modes that are used in the configuration and programming of the ispXPLD
5000MX devices.
Figure 18. ispXP Block Diagram
ISP 1149.1 TAP Port
sysCONFIG Peripheral Port
sysCONFIG
Port
ISP
Mode
BACKGND
1532
Programming
in seconds
Configuration
in milliseconds
Power-up
Refresh
E2CMOS
Memory Space
SRAM
Memory Space
Download in
microseconds
Memory Space
IEEE 1532 ISP
In-system programming of devices provides a number of significant benefits including rapid prototyping, lower
inventory levels, higher quality and the ability to make in-field modifications. All ispXPLD 5000MX devices provide
in-system programmability through their Boundary Scan Test Access Port. This capability has been implemented in
a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532 as the
communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined inter-
face.
The IEEE1532 programming interface allows programming of either the non-volatile array or reconfiguration of the
SRAM bits.
The ispXPLD 5000MX devices can be programmed across the commercial temperature and voltage range. The
PC-based Lattice software facilitates in-system programming of ispXPLD 5000MX devices. The software takes the
JEDEC file output produced by the design implementation software, along with information about the scan chain,
and creates a set of vectors used to drive the scan chain. The software can use these vectors to drive a scan chain
via the parallel port of a PC. Alternatively, the software can output files in formats understood by common auto-
mated test equipment. This equipment can then be used to program ispXPLD 5000MX devices during the testing
of a circuit board.
20
Lattice Semiconductor
sysCONFIG Interface
ispXPLD 5000MX Family Data Sheet
In addition to being able to program the device through the IEEE 1532 interface a microprocessor style interface
(sysCONFIG interface) allows reconfiguration of the SRAM bits within the device. For more information on the
sysCONFIG capability, please refer to technical note number TN1026, ispXP Configuration Usage Guidelines.
Security Scheme
A programmable security scheme is provided on the ispXPLD 5000MX devices as a deterrent to unauthorized
copying of the array configuration patterns. Once programmed, this bit prevents readback of the programmed pat-
tern by a device programmer, securing proprietary designs from competitors. The security bit also prevents pro-
gramming and verification. The entire device must be erased in order to erase the security bit.
Low Power Consumption
The ispXPLD 5000MX devices use zero power non-volatile cells along with full CMOS design to provide low static
power consumption. The 1.8V core reduces dynamic power consumption compared with devices with higher core
voltages. For information on estimating power consumption, please refer to Lattice technical note number TN1031,
Power Estimation in ispXPLD 5000MX Devices.
Density Migration
The ispXPLD 5000MX family has been designed to ensure that different density devices in the same package have
compatible pin-outs. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-
geted for a high-density device to a lower density device. However, the exact details of the final resource utilization
will impact the likely success in each case.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispXPLD 5000MX devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic notes. Internal boundary scan registers are linked internally, allowing test data to be shifted
in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition,
these devices can be linked into a board-level serial scan path for board-level testing. The test access port has its
own supply voltage and can operate with LVCMOS3.3, 2.5 and 1.8V standards.
sysIO Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispXPLD 5000MX family of devices
allows this by offering the user the ability to quickly configure the physical nature of the sysIO cells. This quick con-
figuration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lat-
tice’s ispVM™ System programming software can either perform the quick configuration through the PC parallel
port, or can generate the ATE or test vectors necessary for a third-party test system.
21
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Absolute Maximum Ratings1, 2, 3
ispXPLD 5000MC
1.8V
ispXPLD 5000MB/V
2.5V/3.3V
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V. . . . . . . . . . . . . . . . -0.5 to 5.5V
CC
PLL Supply Voltage (V
) . . . . . . . . . . . . . . . . . . -0.5 to 2.5V. . . . . . . . . . . . . . . . -0.5 to 5.5V
CCP
Output Supply Voltage (V
) . . . . . . . . . . . . . . . . -0.5 to 4.5V. . . . . . . . . . . . . . . . -0.5 to 4.5V
CCO
IEEE 1149.1 TAP Supply Voltage (V
) . . . . . . . . -0.5 to 4.5V. . . . . . . . . . . . . . . . -0.5 to 4.5V
CCJ
Input Voltage Applied4, 5 . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V. . . . . . . . . . . . . . . . -0.5 to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C
Junction Temperature (T ) with Power Applied . . . -55 to 150°C . . . . . . . . . . . . . . . -55 to 150°C
J
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, following the programming specifications).
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and Undershoot of -2V to (V
+2) volts not to exceed 6V is permitted for a duration of <20ns.
IHMAX
5. A maximum of 64 I/Os per device with V > 3.6V is allowed.
IN
Recommended Operating Conditions
Symbol
Parameter
Supply Voltage for 1.8V Devices (ispXPLD 5000MC)
Supply Voltage for 2.5V Devices (ispXPLD 5000MB)
Supply Voltage for 3.3V Devices (ispXPLD 5000MV)
PLL Block Supply Voltage for PLL 1.8V Devices
PLL Block Supply Voltage for PLL 2.5V Devices
PLL Block Supply Voltage for PLL 3.3V Devices
Junction Temperature (Commercial Operation)
Junction Temperature (Industrial Operation)
Min.
1.65
2.3
3
Max.
1.95
2.7
Units
V
V
V
CC
3.6
V
1.65
2.3
3
1.95
2.7
V
V
V
CCP
J
3.6
V
0
90
C
T
-40
105
C
E2CMOS Erase Reprogram Specifications
Parameter
Erase/Reprogram Cycle1
Min.
Max.
Units
1,000
—
Cycles
1. Valid over commercial temperature range.
Hot Socketing Characteristics1, 2, 3, 4
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
I
Input or I/O Leakage Current
0 ≤ V ≤ 3.0V
—
+/-50
+/-800
μA
DK
IN
1. Insensitive to sequence of V and V
when V
≤ 1.0V. For V
> 1.0V, V min must be present. However, assumes monotonic
CCO CC
CC
CCO
CCO
rise/fall rates for V and V
provided (V - V
) ≤ 3.6V.
CC
CCO,
IN
CCO
2. 0 ≤ V ≤ V (MAX), 0 ≤ V
≤ V
(MAX)
CC
CC
CCO
CCO
3. I is additive to I , I or I . Device defaults to pull-up until non-volatile cells are active.
DK
PU PD
BH
4. LVTTL, LVCMOS only.
22
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
0 ≤ V ≤ (V - 0.2V)
Min.
—
Typ.
—
Max.
10
Units
µA
IN
CCO
1
I
I
I
Input or I/O Leakage
IL, IH
(V
- 0.2V) < V ≤ 3.6V
—
—
40
µA
CCO
IN
3.6V < V ≤ 5.5V and
4
IN
Input High Leakage Current
—
—
3
mA
IH
3.0V ≤ V
≤ 3.6V
CCO
3
I
I
I
I
I
I
I/O Active Pullup Current
0 ≤ V ≤ 0.7 V
CCO
-30
30
30
30
—
—
—
—
—
—
—
—
8
-150
150
—
µA
µA
µA
µA
µA
µA
PU
IN
I/O Active Pulldown Current
Bus Hold Low Sustaining Current
V
V
(MAX) ≤ V ≤ V (MAX)
IN IH
PD
IL
= V (MAX)
BHLS
BHHS
BHLO
BHHO
IN
IL
Bus Hold High Sustaining Current V = 0.7 V
—
IN
CCO
Bus Hold Low Overdrive Current 0 ≤ V ≤ V (MAX)
150
150
IN
IH
Bus Hold High Overdrive Current 0 ≤ V ≤ V (MAX)
—
IN
IH
V
Bus Hold Trip Points
I/O Capacitance2
0 ≤ V ≤ V (MAX)
V
* 0.35
V
* 0.65 µA
CCO
BHT
IN
IH
CCO
V
V
V
V
V
V
= 3.3V, 2.5V, 1.8V
—
—
—
—
—
—
—
—
—
—
—
—
pf
pf
pf
pf
pf
pf
CCO
C1
C2
C3
= 1.8V, V = 0 to V (MAX)
8
CC
IO
IH
= 3.3V, 2.5V, 1.8V
8
CCO
Clock Capacitance2
= 1.8V, V = 0 to V (MAX)
8
CC
IO
IH
= 3.3V, 2.5V, 1.8V
8
CCO
Global Input Capacitance2
= 1.8V, V = 0 to V (MAX)
8
CC
IO
IH
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tristated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. T 25°C, f=1.0MHz
A
3. I on JTAG pins has a maximum of -175µA for 5512MX devices.
PU
4. 5V tolerant inputs and I/Os should be placed in banks where 3.0V ≤ V
≤ 3.6V.The JTAG and sysCONFIG ports are not included for the
CCO
5V tolerant interface.
23
Lattice Semiconductor
Supply Current
ispXPLD 5000MX Family Data Sheet
Symbol
Parameter
Condition
Min.
Typ.3
Max.
Units
ispXPLD 5256
V
V
V
V
V
V
V
V
V
V
V
V
= 3.3V, f = 1.0MHz
= 2.5V, f = 1.0MHz
= 1.8V, f = 1.0MHz
—
—
—
—
—
—
—
—
—
—
—
—
26
26
16
4
—
—
—
—
—
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
1,2
I
I
I
I
Operating Power Supply Current
CC
CC
CC
= 3.3V, f = 1.0MHz, unloaded
= 2.5V, f = 1.0MHz, unloaded
= 1.8V, f = 1.0MHz, unloaded
= 3.3V, f = 10MHz
= 2.5V, f = 10MHz
= 1.8V, f = 10MHz
= 3.3V
CCO
CCO
CCO
CCP
CCP
CCP
CCJ
CCJ
CCJ
Standby Power Supply Current
(per I/O Bank)
4
CCO
CCP
CCJ
3
11
11
3
PLL Power Supply Current
(per PLL Bank)
1
Standby IEEE 1149.1 TAP Power
Supply Current
= 2.5V
1
= 1.8V
1
ispXPLD 5512
V
V
V
V
V
V
V
V
V
V
V
V
= 3.3V, f = 1.0MHz
= 2.5V, f = 1.0MHz
= 1.8V, f = 1.0MHz
—
—
—
—
—
—
—
—
—
—
—
—
33
33
22
4
—
—
—
—
—
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
1,2
I
I
I
I
Operating Power Supply Current
CC
CC
CC
= 3.3V, f = 1.0MHz, unloaded
= 2.5V, f = 1.0MHz, unloaded
= 1.8V, f = 1.0MHz, unloaded
= 3.3V, f = 10MHz
= 2.5V, f = 10MHz
= 1.8V, f = 10MHz
= 3.3V
CCO
CCO
CCO
CCP
CCP
CCP
CCJ
CCJ
CCJ
Standby Power Supply Current
(per I/O Bank)
4
CCO
CCP
CCJ
3
11
11
3
PLL Power Supply Current
(per PLL Bank)
1
Standby IEEE 1149.1 TAP Power
Supply Current
= 2.5V
1
= 1.8V
1
ispXPLD 5768
V
V
V
V
V
V
V
V
V
V
V
V
= 3.3V, f = 1.0MHz
= 2.5V, f = 1.0MHz
= 1.8V, f = 1.0MHz
—
—
—
—
—
—
—
—
—
—
—
—
40
40
30
4
—
—
—
—
—
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
1,2
I
I
I
I
Operating Power Supply Current
CC
CC
CC
= 3.3V, f = 1.0MHz, unloaded
= 2.5V, f = 1.0MHz, unloaded
= 1.8V, f = 1.0MHz, unloaded
= 3.3V, f = 10MHz
= 2.5V, f = 10MHz
= 1.8V, f = 10MHz
= 3.3V
CCO
CCO
CCO
CCP
CCP
CCP
CCJ
CCJ
CCJ
Standby Power Supply Current
(per I/O Bank)
4
CCO
CCP
CCJ
3
11
11
3
PLL Power Supply Current
(per PLL Bank)
1
Standby IEEE 1149.1 TAP Power
Supply Current
= 2.5V
1
= 1.8V
1
24
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Supply Current (Continued)
Symbol
Parameter
Condition
Min.
Typ.3
Max.
Units
ispXPLD 51024
V
V
V
V
V
V
V
V
V
V
V
V
= 3.3V, f = 1.0MHz
= 2.5V, f = 1.0MHz
= 1.8V, f = 1.0MHz
—
—
—
—
—
—
—
—
—
—
—
—
75
75
55
4
—
—
—
—
—
—
—
—
—
—
—
—
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
1,2
I
I
I
I
Operating Power Supply Current
CC
CC
CC
= 3.3V, f = 1.0MHz, unloaded
= 2.5V, f = 1.0MHz, unloaded
= 1.8V, f = 1.0MHz, unloaded
= 3.3V, f = 10MHz
= 2.5V, f = 10MHz
= 1.8V, f = 10MHz
= 3.3V
CCO
CCO
CCO
CCP
CCP
CCP
CCJ
CCJ
CCJ
Standby Power Supply Current
(per I/O Bank)
4
CCO
CCP
CCJ
3
11
11
3
PLL Power Supply Current
(per PLL Bank)
1
Standby IEEE 1149.1 TAP Power
Supply Current
= 2.5V
1
= 1.8V
1
1. Device configured with 16-bit counters.
2. ICC varies with specific device configuration and operating frequency.
3. T = 25°C
A
25
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
sysIO Recommended Operating Conditions
V
(V)2
V
(V)
REF
CCO
Standard
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.81
LVTTL
Min.
3.0
2.3
1.65
3.0
3.0
3.15
2.3
3.0
3.0
2.3
1.4
1.4
1.4
1.4
2.3
Typ.
Max.
3.6
2.7
1.95
3.6
3.6
3.45
2.7
3.6
3.6
2.7
1.6
1.6
1.6
3.6
3.6
Min.
—
Typ.
—
Max.
—
3.3
2.5
—
—
—
1.8
—
—
—
3.3
—
—
—
PCI 3.3
3.3
—
—
—
AGP-1X
3.3
—
—
—
SSTL 2
2.5
1.15
1.3
1.35
1.35
0.68
—
1.25
1.5
1.5
1.5
0.75
0.9
0.9
1.0
—
1.35
1.7
1.65
1.65
0.9
—
SSTL 3
3.3
CTT 3.3
3.3
CTT 2.5
2.5
HSTL Class I
HSTL Class III
HSTL Class IV
GTL+
1.5
1.5
1.5
—
—
—
0.882
—
1.122
—
LVDS
2.5/3.3
1. Design tools default setting.
2. Inputs are independent of V
setting. However, V
must be set within the valid operating range for one of the supported standards.
CCO
CCO
26
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
sysIO Single Ended DC Electrical Characteristics
Over Recommended Operating Conditions
V
V
IH
2
2
IL
Input/Output
Standard
V
V
I
I
OH
OL
OH
OL
Min (V)
Max (V)
Min (V)
Max (V)
Max (V)
Min (V)
(mA)
(mA)
20, 16, 12, -20, -16, -12,
8, 5.33, 4 -8, -5.33, -4
0.4
2.4
LVCMOS 3.3
LVTTL
-0.3
0.8
2.0
5.5
0.2
0.4
0.2
V
- 0.2
0.1
4
-0.1
-4
CCO
2.4
-0.3
-0.3
0.8
0.7
2.0
1.7
5.5
3.6
V
V
- 0.2
0.1
-0.1
CCO
16, 12, 8, -16, -12, -8,
0.4
- 0.4
CCO
5.33, 4
-5.33, -4
LVCMOS 2.5
0.2
0.4
0.4
0.2
V
V
- 0.2
- 0.4
0.1
-0.1
CCO
LVCMOS 1.81, 3
LVCMOS 1.83
-0.3
-0.3
0.68
0.68
1.07
1.07
3.6
3.6
8
-8
CCO
V
-0.4 12, 5.33, 4 -12, -5.33, -4
CCO
CCO
V
- 0.2
0.1
1.5
1.5
8
-0.1
-0.5
-0.5
-8
PCI 3.34
AGP-1X4
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
1.08
1.08
1.5
1.5
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.1 V
0.9 V
0.9 V
CCO
CCO
0.1 V
CCO
CCO
SSTL3 class I
SSTL3 class II
SSTL2 class I
SSTL2 class II
CTT 3.3
V
V
- 0.2
- 0.2
V
V
+ 0.2
0.7
0.5
V
- 1.1
REF
REF
REF
REF
REF
REF
REF
CCO
CCO
+ 0.2
V
- 0.9
- 0.62
- 0.43
+ 0.4
+ 0.4
- 0.4
16
7.6
15.2
8
-16
-7.6
-15.2
-8
V
- 0.18 V
- 0.18 V
+ 0.18
+ 0.18
+ 0.2
+ 0.2
+ 0.1
+ 0.1
+ 0.1
+ 0.2
0.54
0.35
V
V
REF
REF
CCO
CCO
V
V
- 0.2
- 0.3
- 0.1
- 0.2
- 0.3
- 0.2
V
V
V
- 0.4
- 0.4
V
REF
REF
REF
REF
REF
REF
REF
REF
REF
CTT 2.5
V
V
V
8
-8
REF
REF
REF
REF
REF
REF
HSTL class I
HSTL class III
HSTL class IV
GTL+
V
V
V
V
V
V
V
V
0.4
V
V
V
8
-8
CCO
CCO
CCO
0.4
0.4
0.6
- 0.4
24
48
36
-8
- 0.4
-8
n/a
n/a
1. Software default setting.
2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.
3. For 1.8V devices (ispXPLD 5000MC) these specifications are V = 0.35 * V and V = 0.65 * V
IL
CC
IH
CC.
4. For 1.8V devices (ispXPLD 5000MC) these specifications are V = 0.3 * V * 3.3/1.8, V = 0.5 * V * 3.3/1.8.
IL
CC
IH
CC
27
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
sysIO Differential DC Electrical Characteristics
Over Recommended Operating Conditions
Parameter
LVDS
Description
Test Conditions
Min.
Typ.
Max.
V
V
Input Voltage
0V
+/-100mV
—
—
—
2.4V
—
INP
Differential Input Threshold
Input Current
0.2 ≤ V
≤ 1.8V
THD
CM
I
Power On
—
+/-10uA
1.60V
—
IN
V
V
V
Output High Voltage for V or V
RT = 100 Ohm
RT = 100 Ohm
—
1.38V
1.03V
350mV
—
OH
OL
OD
OP
OM
Output Low Voltage for V or V
0.9V
250mV
—
OP
OM
Output Voltage Differential
(V - V ), R = 100 Ohm
450mV
50mV
1.375V
50mV
OP
OM
T
ΔV
Change in V Between High and Low
OD
OD
V
Output Voltage Offset
(V - V )/2, R = 100 Ohm
1.125V
—
1.20V
—
OS
OP
OM
T
ΔV
Change in V Between H and L
OS
OS
I
Output Short Circuit Current
V
= 0V Driver outputs
OSD
OD
—
—
24mA
shorted
LVPECL1
DC
Parameter
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
V
3.0
3.3
3.6
V
V
V
V
V
V
CCO
V
V
V
V
V
Input Voltage High
Input Voltage Low
1.49
0.86
1.7
2.72
2.125
2.11
1.27
—
1.49
0.86
1.92
1.06
0.3
2.72
2.125
2.28
1.43
—
1.49
0.86
2.03
1.3
2.72
2.125
2.41
1.57
—
IH
IL
Output Voltage High
Output Voltage Low
Differential Input voltage
OH
OL
0.96
0.3
2
0.3
DIFF
1. These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 19).
The V levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.
OH
2. Valid for 0.2 ≤ V
≤ 1.8V
CM
Figure 19. LVPECL Driver with Three Resistor Pack
1/4 of Bourns P/N
ispXPLD Emulated
CAT 16-PC4F12
LVPECL Buffer
A
Zo
Zo
Rs
to LVPECL
differential
receiver
Rs
28
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family External Switching Characteristics 1, 2, 3
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Data Propagation Delay,
5-PT Bypass
t
t
t
—
—
4.0
4.8
—
—
—
4.5
5.7
—
—
—
5.0
6.0
—
—
—
5.2
6.5
—
—
—
7.5
9.5
—
ns
ns
ns
PD
Data propagation delay
PD_PTSA
S
MFB Register Setup Time
Before Clock, 5-PT Bypass
2.2
2.8
2.8
3.0
4.5
MFB Register Setup Time
Before Clock
t
2.5
1.0
—
—
3.1
1.0
—
—
3.1
1.0
—
—
3.6
0.5
—
—
5.5
1.7
—
—
ns
ns
S_PTSA
SIR
MFB Register Setup Time
Before Clock, Input Register
Path
t
MFB Register Hold Time
Before Clock, 5-PT Bypass
t
t
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
—
—
ns
ns
H
MFB Register Hold Time
Before Clock
H_PTSA
MFB Register Hold Time
Before Clock, Input Register
Path
t
t
0.5
—
—
0.5
—
—
0.5
—
—
1.0
—
—
1.3
—
—
ns
ns
HIR
CO
MFB Register Clock-to-Out-
put Delay
2.8
3.0
3.2
3.7
5.0
External Reset Pin to Output
Delay
t
t
t
—
1.8
—
4.0
—
—
1.8
—
4.5
—
—
1.8
—
5.0
—
—
2.0
—
5.0
—
—
3.0
—
7.5
—
ns
ns
ns
R
Reset Pulse Duration
RW
Input to Output Local Product
Term Output Enable/Disable
6.0
7.0
7.5
8.5
10.5
LPTOE/DIS
Input to Output Shared
Product Term Output Enable/
Disable
t
—
6.0
—
7.0
—
7.5
—
8.5
—
10.5
ns
SPTOE/DIS
Global OE Input to Output
Enable/Disable
t
t
—
4.5
—
—
5.5
—
—
5.5
—
—
6.5
—
—
7.5
—
ns
ns
GOE/DIS
Clock Width, High or Low
1.5
1.5
1.5
1.8
2.5
CW
Gate Width Low (for Low
Transparent) or High (for
High Transparent)
t
1.5
—
1.5
—
1.5
—
1.8
—
2.5
—
ns
GW
Input Register Clock Width,
High or Low
t
t
f
1.5
—
—
0.6
300
1.5
—
—
0.6
275
1.5
—
—
0.6
250
1.8
—
—
0.6
250
2.5
—
—
ns
ns
WIR
Clock-to-Out Skew, Block
Level
1.0
SKEW
Clock Frequency with
Internal Feedback
4
—
—
—
—
—
150 MHz
105 MHz
MAX
Clock Frequency with
External Feedback,
f
(Ext.)
—
200
—
171
—
166
—
149
—
MAX
1/ (t + t
)
S
CO
Clock Frequency Max.
Toggle
f
f
f
(Tog.)
—
—
—
333
280
150
—
—
—
333
280
150
—
—
—
333
230
150
—
—
—
277
230
135
—
—
—
200 MHz
168 MHz
MAX
MAX
MAX
Clock Frequency to CAM
(Configure Mode)
(CAMC)5
(CAM)5
Clock Frequency to CAM
(Compare Mode)
90
MHz
29
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family External Switching Characteristics (Continued)1, 2, 3
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Parameter
Description
Clock Frequency to RAM in:
Single Port Mode
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
—
—
—
—
—
155
155
180
225
200
—
—
—
—
—
155
155
180
220
200
—
—
—
—
—
155
155
160
210
200
—
—
—
—
—
155
155
160
210
200
—
—
—
—
—
93
93
MHz
MHz
f
(RAM)5
MAX
Dual Port Mode
Pseudo Dual Port Mode
Clock Frequency to FIFO
Power-on Time
106 MHz
132 MHz
f
t
(FIFO)5
MAX
PWR_ON
200
µs
Timing v.1.8
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate timing for other standards.
2. Measured using standard switching circuit, global routing loading of 1, worst case PTSA loading and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
5. CAM, FIFO, RAM f
specification used shared PT Clk.
MAX
30
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Timing Model
The task of determining timing in a ispXPLD 5000MX device is relatively simple. The timing model show in
Figure 20 shows the specific delay paths. Once the implementation of a given function is determined either con-
ceptually or from the software report file, the delay path of a function can easily be determined from the timing
model. The Lattice design tools report the timing delays based on the same timing model. Note that internal timing
parameters are for reference only, and are not tested. The external timing parameters are tested and guaranteed
for every device.
Figure 20. ispXPLD 5000MX Timing Model Diagram
tPDb
From Feedback
Feedback
OUT
tPDi
tFBK
t PTSA
tEXP
tCICOMFB
tROUTE
tROUTEMF
tIN
tIOI
Memory
Functions
tBUF
tIOO
tEN
DATA
tOSA
IN
tBLA
tCASC
tCICOMC
tSUM
Q
tINREG
tINDIO
tDIS
tGCLK
tPTCLK
tBCLK
tGCLK _IN
tIOI
GCLK
C.E.
tPLL _DELAY
tPLL
_SEC_DELAY
tPTSR
tBSR
S/R
3
MC Reg.
CLK, CE and Reset Only
t RST
tIOI
RST
OE
tPTOE
tSPTOE
tGPTOE
tGOE
tIOI
Path only available for
FIFO Flags
Some paths not available in memory
mode. Refer to timing tables for details.
31
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Base
Parameter
Description
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
In/Out Delays
t
Input Buffer Delay
—
—
—
—
0.70
0.40
—
—
0.91
0.35
—
—
0.96
0.35
—
—
1.11
0.35
—
—
1.30 ns
0.55 ns
IN
Global Clock Input
Buffer Delay
t
GCLK_IN
Global RESET Pin
Delay
t
t
—
—
—
—
3.77
1.98
—
—
4.24
2.66
—
—
4.71
2.34
—
—
4.71
2.87
—
—
7.07 ns
3.27 ns
RST
Global OE Pin
Delay
GOE
Delay through
Output Buffer
t
t
t
—
—
—
—
—
—
1.16
2.52
1.92
—
—
—
1.30
2.84
2.40
—
—
—
1.45
3.16
2.40
—
—
—
1.60
3.63
2.40
—
—
—
2.17 ns
4.23 ns
3.60 ns
BUF
Output Enable Time
EN
Output Disable
Time
DIS
Routing Delays
t
Delay through SRP
—
—
—
—
1.95
0.60
—
—
2.06
0.60
—
—
2.34
0.60
—
—
2.24
0.47
—
—
3.66 ns
1.63 ns
ROUTE
Input Buffer to
Macrocell Register
Delay
t
INREG
Product Term
Sharing Array Delay
t
t
t
t
t
t
t
t
t
t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.50
0.19
0.52
0.12
0.12
0.30
0.72
0.60
0.83
0.83
—
—
—
—
—
—
—
—
—
—
0.50
0.02
0.32
0.14
0.14
0.30
0.81
0.75
1.19
1.19
—
—
—
—
—
—
—
—
—
—
0.53
0.39
0.72
0.15
0.15
0.30
0.90
0.75
1.04
1.04
—
—
—
—
—
—
—
—
—
—
0.83
0.03
0.82
0.15
0.15
0.30
0.94
0.75
1.52
1.52
—
—
—
—
—
—
—
—
—
—
1.34 ns
0.60 ns
0.78 ns
0.23 ns
0.23 ns
0.30 ns
1.35 ns
1.13 ns
1.31 ns
1.31 ns
PTSA
Internal Feedback
Delay
FBK
Global Clock Tree
Delay
GCLK
Block PT Clock
Delay
BCLK
Macrocell PT Clock
Delay
PTCLK
PLL_DELAY
BSR
Programmable PLL
Delay Increment
Block PT Reset
Delay
Macrocell PT Set/
Reset Delay
PTSR
Macrocell PT OE
Delay
LPTOE
SPTOE
Segment PT OE
Delay
Output Sharing
Array Delay
t
t
t
—
—
—
—
—
—
0.80
0.83
0.20
—
—
—
0.90
1.04
0.23
—
—
—
1.00
1.04
0.25
—
—
—
1.00
1.04
0.25
—
—
—
1.50 ns
1.56 ns
0.38 ns
OSA
PTOE
PDB
Global PT OE Delay
5-PT Bypass
Propagation Delay
Macrocell
Propagation Delay
t
—
—
0.50
—
0.93
—
0.72
—
0.72
—
1.04 ns
PDI
32
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Base
Parameter
Description
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Registered Delays
D-Register Setup
Time, Global Clock
t
t
t
t
t
t
—
—
—
—
—
—
0.28
-0.13
1.90
—
—
—
0.31
-0.11
2.56
—
—
—
0.35
-0.10
2.50
—
—
—
0.55
-0.10
2.40
—
—
—
0.52
-0.07
4.00
—
—
—
—
ns
ns
ns
S
D-Register Setup
Time, PT Clock
S_PT
H
D-Register Hold
Time
—
—
—
—
Register Clock to
OSA Time
0.72
—
1.03
—
0.68
—
0.93
—
1.50 ns
COi
CESi
CEHi
Clock Enable Setup
Time
1.07
0.00
1.20
0.00
1.33
0.00
1.33
0.00
2.00
0.00
—
—
ns
ns
Clock Enable Hold
Time
—
—
—
—
D-Input Register
Setup Time, Global
Clock
t
t
t
t
—
—
—
—
0.66
0.42
0.84
0.00
—
—
—
—
0.20
0.37
1.31
0.00
—
—
—
—
0.53
0.34
1.01
0.00
—
—
—
—
0.12
0.34
1.41
0.00
—
—
—
—
0.08
0.22
2.91
0.00
—
—
—
—
ns
ns
ns
ns
SIR
D-Input Register
Setup Time, PT
Clock
SIR_PT
HIR
D-Input Register
Hold Time, Global
Clock
D-Input Register
Hold Time, PT
Clock
HIR_PT
Latched Delays
Latch Setup Time,
Global Clock
t
—
0.18
—
0.00
—
0.00
—
0.00
—
0.00
—
ns
SL
Latch Setup Time,
PT Clock
t
t
t
—
—
—
0.18
-0.06
—
—
—
0.00
0.00
—
—
—
0.00
0.00
—
—
—
0.00
0.00
—
—
—
0.34
-0.03
—
—
—
ns
ns
SL_PT
Latch Hold Time
HL
Latch Gate to OSA
Time
0.07
0.08
0.08
0.08
0.13 ns
GOi
Propagation Delay
through Latch to
OSA Transparent
t
—
—
0.52
—
0.58
—
0.65
—
0.65
—
0.97 ns
PDLi
Reset and Set Delays
Asynchronous
t
Reset or Set to OSA
Delay
—
—
—
—
0.23
0.42
—
—
0.26
0.47
—
—
0.29
0.53
—
—
0.29
0.55
—
—
0.43 ns
0.79 ns
SRi
Asynchronous
Reset or Set
Recovery
t
SRR
eXtended Function Routing Delays
Delay through SRP
when Implementing
Memory Functions
t
—
—
2.00
—
2.25
—
2.51
—
2.61
—
3.76 ns
ROUTEMF
33
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Base
Parameter
Description
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Additional Delay for
PT Cascading
between MFBs
t
t
t
—
—
—
—
—
—
0.71
0.35
0.10
—
—
—
0.80
0.39
0.11
—
—
—
0.89
0.44
0.13
—
—
—
0.92
0.46
0.13
—
—
—
1.33 ns
0.66 ns
0.19 ns
CASC
Carry Chain Delay,
MFB to MFB
CICOMFB
CICOMC
Carry Chain Delay,
Macro-Cell to
Macro-Cell
Routing Delay for
Extended Function
Flags
t
—
—
2.62
—
2.94
—
3.27
—
3.40
—
4.91 ns
FLAG
Additional Flag
Delay when
Expanding Data
Widths
t
,
FLAGFULL
t
FLAGAFULL,
t
t
—
—
2.57
0.80
—
—
2.89
0.90
—
—
3.21
1.00
—
—
3.34
1.04
—
—
4.82 ns
1.50 ns
FLAGEXP
t
t
,
FLAGEMPTY
FLAGAEMPTY
Counter Sum Delay
t
PTSA
SUM
Optional Adjusters
Block Loading
Adder
t
t
t
t
t
t
—
—
—
0.04
0.53
0.50
—
—
—
0.04
0.60
0.56
—
—
—
0.05
0.66
0.63
—
—
—
0.05
0.69
0.65
—
—
—
0.07 ns
0.99 ns
0.94 ns
BLA
ROUTE
PT Expander Adder
EXP
ROUTE
Additional Delay for
the Input Register
t
INDIO
INREG
Secondary PLL
Output Delay
PLL_SEC_DELA
t
—
—
0.91
0.62
—
—
0.91
0.70
—
—
0.91
0.78
—
—
0.91
0.81
—
—
0.91 ns
1.16 ns
PLL_DELAY
Y
t
MFB Input Extender
t
ROUTE
INEXP
Input and Output Buffer Delays
Input Buffer Selec-
tion Adder
t
t
GCLK_IN, IN,
t
ns
ns
IOI
t
t
GOE, RST
Refer to sysIO Adjuster Tables
Output Buffer
Selection Adder
t
t
IOO
BUF
FIFO
Write Data Setup
before Write Clock
Time
t
t
—
—
-0.27
-0.01
—
—
-0.27
-0.01
—
—
-0.22
-0.01
—
—
-0.22
-0.01
—
—
-0.21
-0.01
—
—
ns
ns
FIFOWCLKS
Write Data Hold
after Write Clock
Time
FIFOWCLKH
Opposite Clock
Cycle Delay
t
t
—
—
—
—
1.40
3.08
—
—
1.40
3.08
—
—
1.76
3.85
—
—
1.76
3.85
—
—
1.83 ns
4.00 ns
FIFOCLKSKEW
Write Clock to Full
Flag Delay
FIFOFULL
Write Clock to
Almost Full Flag
Delay
t
t
t
—
—
—
—
—
—
3.08
3.08
3.08
—
—
—
3.08
3.08
3.08
—
—
—
3.86
3.86
3.86
—
—
—
3.86
3.86
3.86
—
—
—
4.01 ns
4.01 ns
4.01 ns
FIFOAFULL
FIFOEMPTY
FIFOAEMPTY
Read Clock to
Empty Flag Delay
Read Clock to
Almost Empty Flag
Delay
34
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Base
Parameter
Description
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Write-Enable setup
before Write Clock
t
t
t
t
t
—
—
—
—
—
2.33
-2.95
2.69
-3.17
—
—
—
2.33
-2.95
2.35
-3.17
—
—
—
2.91
-2.36
2.79
-2.53
—
—
—
2.91
-2.36
2.38
-2.53
—
—
—
3.03
-2.27
4.14
-2.44
—
—
—
—
—
ns
ns
ns
ns
FIFOWES
Write-Enable hold
after Write Clock
FIFOWEH
FIFORES
FIFOREH
FIFORSTO
Read-Enable setup
before Read Clock
—
—
—
—
Read-Enable hold
after Read Clock
—
—
—
—
Reset to Output
Delay
3.30
3.30
4.13
4.13
4.29 ns
Reset Recovery
Time
t
t
t
—
—
—
1.20
0.14
—
—
—
1.20
0.14
—
—
—
1.50
0.18
—
—
—
1.50
0.18
—
—
—
1.56
0.19
—
—
—
ns
ns
FIFORSTR
Reset Pulse Width
FIFORSTPW
FIFORCLKO
Read Clock to FIFO
Out Delay
3.73
3.73
4.66
4.66
4.84 ns
CAM – Update Mode
Memory Select
Setup before CLK
t
—
—
1.40
—
—
0.70
—
—
1.50
—
—
1.40
—
—
1.44
—
—
ns
ns
CAMMSS
CAMMSH
Memory Select
Hold after CLK
t
-0.01
-0.01
-0.01
-0.01
-0.01
Enable Mask
Register Setup
Time before CLK
t
t
—
—
-0.27
-0.01
—
—
-0.27
-0.01
—
—
-0.22
-0.01
—
—
-0.22
-0.01
—
—
-0.21
-0.01
—
—
ns
ns
CAMENMSKS
Enable Mask
Register Setup
Time after CLK
CAMENMSKH
Address Setup
Time before Clock
t
t
t
t
t
t
t
t
t
t
—
—
—
—
—
—
—
—
—
—
-0.27
-0.01
-0.41
-0.01
-0.27
-0.01
-0.27
-0.01
1.55
—
—
—
—
—
—
—
—
—
—
-0.27
-0.01
-0.41
-0.01
-0.27
-0.01
-0.27
-0.01
1.55
—
—
—
—
—
—
—
—
—
—
-0.22
-0.01
-0.33
-0.01
-0.22
-0.01
-0.22
-0.01
1.94
—
—
—
—
—
—
—
—
—
—
-0.22
-0.01
-0.33
-0.01
-0.22
-0.01
-0.22
-0.01
1.94
—
—
—
—
—
—
—
—
—
—
-0.21
-0.01
-0.31
-0.01
-0.21
-0.01
-0.21
-0.01
2.02
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAMADDS
CAMADDH
CAMDATAS
CAMDATAH
CAMDCS
CAMDCH
CAMRWS
CAMRWH
CAMCES
Address Hold Time
after Clock
Data Setup Time
before Clock
Data Hold Time
after Clock
“Don’t Care” Setup
Time before Clock
“Don’t Care” Hold
Time after Clock
R/W Setup Time
before Clock
R/W Enable Hold
Time after Clock
Clock Enable Setup
Time before Clock
Clock Enable Hold
Time after Clock
-2.95
-2.95
-2.36
-2.36
-2.27
CAMCEH
35
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Base
Parameter
Description
Write Mask
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
Register Setup
Time before Clock
—
-0.27
—
-0.27
—
-0.22
—
-0.22
—
-0.21
—
—
ns
ns
CAMWMSKS
Write Mask
Register Setup
Time after Clock
t
t
—
—
-0.01
—
—
-0.01
—
—
-0.01
—
—
-0.01
—
—
-0.01
—
CAMWMSKH
Reset to CAM
Output Delay
3.30
3.30
4.13
4.13
4.29 ns
CAMRSTO
Reset Recovery
Time
t
t
—
—
1.20
0.14
—
—
1.20
0.14
—
—
1.50
0.18
—
—
1.50
0.18
—
—
1.56
0.19
—
—
ns
ns
CAMRSTR
Reset Pulse Width
CAMRSTPW
CAM – Compare Mode
Data Setup Time
before Clock
t
—
—
-0.41
-0.01
—
—
-0.41
-0.01
—
—
-0.33
-0.01
—
—
-0.33
-0.01
—
—
-0.31
-0.01
—
—
ns
ns
CAMDATAS
CAMDATAH
Data Hold Time
after Clock
t
Enable Mask
Register Setup
Time before Clock
t
—
-0.27
—
-0.27
—
-0.22
—
-0.22
—
-0.21
—
—
ns
ns
CAMENMSKS
Enable Mask
Register Setup
Time after Clock
t
t
t
—
—
—
-0.01
—
—
-0.01
—
—
-0.01
—
—
-0.01
—
—
-0.01
—
CAMENMSKH
CAMCASC
CAMCO
CAM Width
Expansion Delay
0.40
6.19
0.40
6.13
0.50
6.81
0.50
6.61
0.51 ns
9.63 ns
Clock to Output
(Address Out)
Delay
—
—
—
—
—
Clock to Match Flag
Delay
t
t
t
—
—
—
—
—
—
6.19
5.50
3.16
—
—
—
6.13
5.50
3.16
—
—
—
6.07
6.38
3.95
—
—
—
6.61
6.38
3.95
—
—
—
10.22 ns
7.72 ns
4.11 ns
CAMMATCH
Clock to Multi-
Match Flag Delay
CAMMMATCH
CAM Reset to Flags
Delay
CAMRSTFLAG
Single Port RAM
Address to Data
Delay
t
—
—
—
5.97
—
—
5.97
—
—
5.97
—
—
5.97
—
—
7.76 ns
SPADDDATA
Memory Select
Setup Before Clock
Time
t
-0.27
-0.27
-0.27
-0.27
-0.21
—
ns
SPMSS
Memory Select
Hold time after
Clock Time
t
t
t
t
—
—
—
—
-0.01
2.30
—
—
—
—
-0.01
2.30
—
—
—
—
-0.01
2.30
—
—
—
—
-0.01
2.30
—
—
—
—
-0.01
9.80
—
—
—
—
ns
ns
ns
ns
SPMSH
SPCES
SPCEH
SPADDS
Clock Enable Setup
before Clock Time
Clock Enable Hold
time after Clock
Time
-2.95
-0.27
-2.95
-0.27
-2.95
-0.27
-2.95
-0.27
-2.27
-0.21
Address Setup
before Clock Time
36
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Base
Parameter
Description
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Address Hold time
after Clock Time
t
t
t
t
t
t
t
—
—
—
—
—
—
—
-0.01
-0.27
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.27
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.27
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.27
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.21
-0.01
-0.21
-0.01
—
—
—
—
—
—
ns
ns
ns
ns
ns
SPADDH
R/W Setup before
Clock Time
SPRWS
R/W Hold time after
Clock Time
—
—
—
—
SPRWH
SPDATAS
SPDATAH
SPCLKO
SPRSTO
Data Setup before
Clock Time
—
—
—
—
Data Hold time after
Clock Time
—
—
—
—
Clock to Output
Delay
5.97
3.30
5.97
3.30
5.97
3.30
5.97
3.30
9.86 ns
4.29 ns
Reset to RAM
Output Delay
—
—
—
—
—
Reset Recovery
Time
t
t
—
—
1.20
0.14
—
—
1.20
0.14
—
—
1.20
0.14
—
—
1.20
0.14
—
—
1.56
0.19
—
—
ns
ns
SPRSTR
Reset Pulse Width
SPRSTPW
Pseudo Dual Port RAM
Memory Select
Setup Before Clock
t
—
—
-0.27
-0.01
—
—
-0.27
-0.01
—
—
-0.22
-0.01
—
—
-0.22
-0.01
—
—
-0.21
-0.01
—
—
ns
ns
PDPMSS
Memory Select
Hold time after
Clock
t
PDPMSH
Clock Enable Setup
before Read Clock
Time
t
t
t
t
t
t
t
—
—
—
—
—
—
—
2.33
-2.95
1.87
—
—
—
—
—
—
—
2.33
-2.95
1.87
—
—
—
—
—
—
—
2.91
-2.36
2.34
—
—
—
—
—
—
—
2.91
-2.36
2.34
—
—
—
—
—
—
—
3.03
-2.27
2.43
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
PDPRCES
PDPRCEH
PDPWCES
PDPWCEH
PDPRADDS
PDPRADDH
PDPWADDS
Clock Enable Hold
time after Read
Clock Time
Clock Enable Setup
before Write Clock
Time
Clock Enable Hold
time after Write
Clock Time
-2.95
-0.27
-0.01
-0.27
-2.95
-0.27
-0.01
-0.27
-2.36
-0.22
-0.01
-0.22
-2.36
-0.22
-0.01
-0.22
-2.27
-0.21
-0.01
-0.21
Read Address
Setup before Read
Clock Time
Read Address Hold
after Read Clock
Time
Write Address
Setup before Write
Clock Time
Write Address Hold
after Write Clock
Time
t
t
—
—
-0.01
-0.27
—
—
-0.01
-0.27
—
—
-0.01
-0.22
—
—
-0.01
-0.22
—
—
-0.01
-0.21
—
—
ns
ns
PDPWADDH
R/W Setup before
Clock Time
PDPRWS
37
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Base
Parameter
Description
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
R/W Hold time after
Clock Time
t
t
t
t
t
t
—
—
—
—
—
—
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.22
-0.01
—
—
—
-0.01
-0.22
-0.01
—
—
—
-0.01
-0.21
-0.01
—
—
—
—
ns
ns
ns
PDPRWH
Data Setup before
Clock Time
PDPDATAS
PDPDATAH
PDPRCLKO
PDPCLKSKEW
PDPRSTO
Data Hold time after
Clock Time
—
—
—
—
Read Clock to
Output Delay
5.08
—
5.02
—
5.66
—
5.45
—
8.54 ns
ns
4.29 ns
Opposite Clock
Cycle Delay
1.40
—
1.40
—
1.76
—
1.76
—
1.83
—
—
Reset to RAM
Output Delay
3.30
3.30
4.13
4.13
Reset Recovery
Time
t
t
—
—
1.20
0.14
—
—
1.20
0.14
—
—
1.50
0.18
—
—
1.50
0.18
—
—
1.56
0.19
—
—
ns
ns
PDPRSTR
Reset Pulse Width
PDPRSTPW
Dual Port RAM
Memory Select A
Setup Before R/W A
Time
t
t
t
—
—
—
-0.27
-0.01
3.72
—
—
—
-0.27
-0.01
3.72
—
—
—
-0.27
-0.01
3.72
—
—
—
-0.27
-0.01
3.72
—
—
—
-0.21
-0.01
4.84
—
—
—
ns
ns
ns
DPMSAS
DPMSAH
DPCEAS
Memory Select
Hold time after R/W
A Time
Clock Enable A
Setup before Clock
A Time
Clock Enable A
Hold time after
Clock A Time
t
t
t
—
—
—
-2.95
-0.27
-0.01
—
—
—
-2.95
-0.27
-0.01
—
—
—
-2.95
-0.27
-0.01
—
—
—
-2.95
-0.27
-0.01
—
—
—
-2.27
-0.21
-0.01
—
—
—
ns
ns
ns
DPCEAH
DPADDAS
DPADDAH
Address A Setup
before Clock A Time
Address A Hold
time after Clock A
Time
R/W A Setup before
Clock A Time
t
t
t
—
—
—
-0.27
-0.01
-0.27
—
—
—
-0.27
-0.01
-0.27
—
—
—
-0.27
-0.01
-0.27
—
—
—
-0.27
-0.01
-0.27
—
—
—
-0.21
-0.01
-0.21
—
—
—
ns
ns
ns
DPRWAS
DPRWAH
DPDATAAS
R/W A Hold time
after Clock A Time
Write Data A Setup
before Clock A Time
Write Data A Hold
time after Clock A
Time
t
t
t
—
—
—
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.27
-0.01
—
—
—
-0.01
-0.21
-0.01
—
—
—
ns
ns
ns
DPDATAAH
DPMSBS
DPMSBH
Memory Select B
Setup Before R/W B
Time
Memory Select
Hold time after R/W
B Time
38
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
-4
-45
-5
-52
-75
Base
Parameter
Description
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Clock Enable B
Setup before Clock
B Time
t
—
2.33
—
2.33
—
2.33
—
2.33
—
3.03
—
ns
DPCEBS
Clock Enable Hold
B after Clock B
Time
t
t
t
—
—
—
-2.95
-0.27
-0.01
—
—
—
-2.95
-0.27
-0.01
—
—
—
-2.95
-0.27
-0.01
—
—
—
-2.95
-0.27
-0.01
—
—
—
-2.27
-0.21
-0.01
—
—
—
ns
ns
ns
DPCEBH
DPADDBS
DPADDBH
Address B Setup
before Clock B Time
Address B Hold
time after Clock B
Time
R/W B Setup before
Clock B Time
t
t
t
t
t
t
t
t
—
—
—
—
—
—
—
—
-0.27
-0.01
-0.27
-0.01
—
—
—
-0.27
-0.01
-0.27
-0.01
—
—
—
-0.27
-0.01
-0.27
-0.01
—
—
—
-0.27
-0.01
-0.27
-0.01
—
—
—
-0.21
-0.01
-0.21
-0.01
—
—
—
—
—
ns
ns
ns
ns
DPRWBS
R/W B Hold time
after Clock B Time
DPRWBH
Write Data B Setup
before Clock B Time
—
—
—
—
DPDATABS
DPDATABH
DPRCLKAO
DPRCLKBO
DPCLKSKEW
DPRSTO
Write Data B Hold
after Clock B Time
—
—
—
—
Read Clock A to
Output Delay
5.97
5.16
—
5.92
5.16
—
5.86
5.16
—
5.65
5.16
—
9.86 ns
6.71 ns
Read Clock B to
Output Delay
—
—
—
—
—
Opposite Clock
Cycle Delay
1.40
—
1.40
—
1.40
—
1.40
—
1.83
—
—
ns
Reset to RAM
Output Delay
3.30
3.30
3.30
3.30
4.29 ns
Reset Recovery
Time
t
t
—
—
1.20
0.14
—
—
1.20
0.14
—
—
1.20
0.14
—
—
1.20
0.14
—
—
1.56
0.19
—
—
ns
ns
DPRSTR
Reset Pulse Width
DPRSTPW
Timing v.1.8
1. The PT-delay to clock of RAM/FIFO/CAM should be t
instead of t
PTCLK.
BCLK
2. The PT-delay to set/reset of RAM/FIFO/CAM should be t
instead of t
BSR
PTSR.
39
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Timing Adders
-4
-45
-5
-52
-75
Base
Parameter
Description
Param. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
Input Adjusters
IOI
LVTTL_in
Using 3.3V TTL
t
t
—
—
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
ns
ns
IOIN
Using 1.8V
CMOS
LVCMOS_18_in
IOIN
Using 2.5V
CMOS
LVCMOS_25_in
LVCMOS_33_in
t
t
—
—
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
—
—
0.0
0.0
ns
ns
IOIN
IOIN
Using 3.3V
CMOS
AGP_1X_in
CTT25_in
CTT33_in
GTL+_in
Using AGP 1x
Using CTT 2.5V
Using CTT 3.3V
Using GTL+
t
t
t
t
—
—
—
—
1.0
1.0
1.0
0.5
—
—
—
—
1.0
1.0
1.0
0.5
—
—
—
—
1.0
1.0
1.0
0.5
—
—
—
—
1.0
1.0
1.0
0.5
—
—
—
—
1.0
1.0
1.0
0.5
ns
ns
ns
ns
IOIN
IOIN
IOIN
IOIN
Using HSTL 2.5V,
Class I
HSTL_I_in
HSTL_III_in
HSTL_IV_in
t
t
t
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
ns
ns
ns
IOIN
IOIN
IOIN
Using HSTL 2.5V,
Class III
Using HSTL 2.5V,
Class IV
Using Low Volt-
age Differential
Signaling (LVDS)
LVDS_in
t
—
0.5
—
0.5
—
0.5
—
0.5
—
0.5
ns
IOIN
Using Low
Voltage PECL
LVPECL_in
PCI_in
t
t
t
—
—
—
0.5
1.0
0.5
—
—
—
0.5
1.0
0.5
—
—
—
0.5
1.0
0.5
—
—
—
0.5
1.0
0.5
—
—
—
0.5
1.0
0.5
ns
ns
ns
IOIN
IOIN
IOIN
Using PCI
Using SSTL 2.5V,
Class I
SSTL2_I_in
Using SSTL 2.5V,
Class II
SSTL2_II_in
SSTL3_I_in
SSTL3_II_in
t
t
t
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
ns
ns
ns
IOIN
IOIN
IOIN
Using SSTL 3.3V,
Class I
Using SSTL 3.3V,
Class II
t
Output Adjusters – Output Signal Modifiers
IOO
Using Slow Slew
(LVTTL and
LVCMOS
t
t
IOBUF,
IOEN
Slow Slew
—
0.9
—
0.9
—
0.9
—
0.9
—
0.9
ns
Outputs Only)
t
Output Adjusters – Output Configurations
IOO
t
t
t
IOBUF,
IOEN
IODIS
Using 3.3V TTL
Drive
LVTTL_out
,
—
—
—
1.2
0.3
0.3
—
—
—
1.2
0.3
0.3
—
—
—
1.2
0.3
0.3
—
—
—
1.2
0.3
0.3
—
—
—
1.2
0.3
0.3
ns
ns
ns
Using 1.8V
t
IOBUF,
LVCMOS_18_4mA_out
CMOS Standard, t
,
IOEN
4mA Drive
t
IODIS
Using 1.8V
t
IOBUF,
LVCMOS_18_5.33mA_out CMOS Standard, t
,
IOEN
5.33mA Drive
t
IODIS
40
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Timing Adders (Continued)
-4
-45
-5
-52
-75
Base
Parameter
Description
Using 1.8V
CMOS Standard, t
Param. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
IOBUF,
IOEN
IODIS
LVCMOS_18_8mA_out
,
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.0
0.0
1.2
1.0
0.4
0.4
0.4
1.2
1.2
0.8
0.6
0.6
0.3
0.6
0.3
0.2
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.0
0.0
1.2
1.0
0.4
0.4
0.4
1.2
1.2
0.8
0.6
0.6
0.3
0.6
0.3
0.2
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.0
0.0
1.2
1.0
0.4
0.4
0.4
1.2
1.2
0.8
0.6
0.6
0.3
0.6
0.3
0.2
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.0
0.0
1.2
1.0
0.4
0.4
0.4
1.2
1.2
0.8
0.6
0.6
0.3
0.6
0.3
0.2
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.0
0.0
1.2
1.0
0.4
0.4
0.4
1.2
1.2
0.8
0.6
0.6
0.3
0.6
0.3
0.2
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8mA Drive
t
Using 1.8V
t
IOBUF,
LVCMOS_18_12mA_out CMOS Standard, t
,
IOEN
12mA Drive
t
IODIS
Using 2.5V
CMOS Standard, t
t
IOBUF,
LVCMOS_25_4mA_out
,
IOEN
4mA Drive
t
IODIS
Using 2.5V
t
IOBUF,
LVCMOS_25_5.33mA_out CMOS Standard, t
,
IOEN
5.33 mA Drive
t
IODIS
Using 2.5V
CMOS Standard, t
t
IOBUF,
LVCMOS_25_8mA_out
,
IOEN
8mA Drive
t
IODIS
Using 2.5V
t
IOBUF,
LVCMOS_25_12mA_out CMOS Standard, t
,
IOEN
12mA Drive
t
IODIS
Using 2.5V
t
IOBUF,
LVCMOS_25_16mA_out CMOS Standard, t
,
IOEN
16mA Drive
t
IODIS
Using 3.3V
CMOS Standard, t
t
IOBUF,
LVCMOS_33_4mA_out
,
IOEN
4mA Drive
t
IODIS
Using 3.3V
t
IOBUF,
LVCMOS_33_5.33mA_out CMOS Standard, t
,
IOEN
5.33mA Drive
t
IODIS
Using 3.3V
CMOS Standard, t
t
IOBUF,
LVCMOS_33_8mA_out
,
IOEN
8mA Drive
t
IODIS
Using 3.3V
t
IOBUF,
LVCMOS_33_12mA_out CMOS Standard, t
,
IOEN
12mA Drive
t
IODIS
Using 3.3V
t
IOBUF,
LVCMOS_33_16mA_out CMOS Standard, t
,
IOEN
16mA Drive
t
IODIS
Using 3.3V
t
IOBUF,
LVCMOS_33_20mA_out CMOS Standard, t
,
IOEN
20mA Drive
t
IODIS
t
t
t
IOBUF,
Using AGP 1x
Standard
AGP_1X_out
CTT25_out
CTT33_out
GTL+_out
,
IOEN
IODIS
t
t
t
IOBUF,
Using CTT 2.5V
Using CTT 3.3V
Using GTL+
,
IOEN
IODIS
t
t
t
IOBUF,
,
IOEN
IODIS
t
t
t
IOBUF,
,
IOEN
IODIS
41
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Timing Adders (Continued)
-4
-45
-5
-52
-75
Base
Parameter
HSTL_I_out
Description
Param. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
IOBUF,
Using HSTL 2.5V,
Class I
t
t
,
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
—
—
—
0.5
0.6
0.6
ns
ns
ns
IOEN
IODIS
t
t
t
IOBUF,
IOEN
IODIS
Using HSTL 2.5V,
Class III
HSTL_III_out
HSTL_IV_out
,
t
t
t
IOBUF,
IOEN
IODIS
Using HSTL 2.5V,
Class IV
,
Using Low
t
t
t
IOBUF,
IOEN
IODIS
Voltage Differen-
tial Signaling
(LVDS)
LVDS_out
,
—
0.8
—
0.8
—
0.8
—
0.8
—
0.8
ns
t
t
t
IOBUF,
IOEN
IODIS
Using Low
Voltage PECL
LVPECL_out
PCI_out
,
—
—
—
—
—
—
0.3
0.6
0.3
0.5
0.2
0.4
—
—
—
—
—
—
0.3
0.6
0.3
0.5
0.2
0.4
—
—
—
—
—
—
0.3
0.6
0.3
0.5
0.2
0.4
—
—
—
—
—
—
0.3
0.6
0.3
0.5
0.2
0.4
—
—
—
—
—
—
0.3
0.6
0.3
0.5
0.2
0.4
ns
ns
ns
ns
ns
ns
t
t
t
IOBUF,
IOEN
IODIS
Using PCI
Standard
,
t
t
t
IOBUF,
IOEN
IODIS
Using SSTL 2.5V,
Class I
SSTL2_I_out
SSTL2_II_out
SSTL3_I_out
SSTL3_II_out
,
t
t
t
IOBUF,
IOEN
IODIS
Using SSTL 2.5V,
Class II
,
t
t
t
IOBUF,
IOEN
IODIS
Using SSTL 3.3V,
Class I
,
t
t
t
IOBUF,
IOEN
IODIS
Using SSTL 3.3V,
Class II
,
Timing v.1.8
42
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
Min
1.2
1.2
—
Max
—
Units
ns
t
t
Input clock, high time
80% to 80%
20% to 20%
20% to 80%
PWH
PWL
Input clock, low time
—
ns
t , t
Input Clock, rise and fall time
Input clock stability, cycle to cycle (peak)
M Divider input, frequency range
M Divider output, frequency range
N Divider input, frequency range
N Divider output, frequency range
V Divider input, frequency range
V Divider output, frequency range
Output clock, duty cycle
3.0
ns
R
F
t
f
f
f
f
f
f
t
—
+/- 250
320
320
320
320
400
320
60
ps
INSTB
10
MHz
MHz
MHz
MHz
MHz
MHz
%
MDIVIN
MDIVOUT
NDIVIN
10
10
10
NDIVOUT
VDIVIN
100
10
VDIVOUT
OUTDUTY
40
Clean reference.
10 MHz < f
100MHz < f
< 20 MHz or
< 160 MHz1
—
—
—
—
+/- 250
+/- 150
+/- 300
+/- 150
ps
ps
ps
ps
MDIVOUT
VDIVIN
t
Output clock, cycle to cycle jitter (peak)
Output clock, period jitter (peak)
JIT(CC)
Clean reference.
20 MHz < f
< 320 MHz and
< 320 MHz1
MDIVOUT
160MHz < f
VDIVIN
Clean reference.
10 MHz < f
< 20 MHz or
< 160 MHz1
MDIVOUT
100MHz < f
VDIVIN
2
T
JIT(PERIOD)
Clean reference.
20 MHz < f
< 320 MHz and
< 320 MHz1
MDIVOUT
160MHz < f
VDIVIN
t
t
t
t
t
t
t
Input clock to CLK_OUT delay
Input clock to external feedback delta
Time to acquire phase lock after input stable
Delay increment (Lead/Lag)
Internal feedback
External feedback
—
—
—
3.0
600
25
ns
ps
us
ps
ns
ns
ns
CLK_OUT_DLY
PHASE
LOCK
Typical = +/- 250ps
+/- 120 +/- 550
+/- 0.84 +/- 3.85
PLL_DELAY
RANGE
Total output delay range (lead/lag)
Minimum reset pulse width
—
—
1.8
1.0
PLL_RSTW
3
Global clock input delay
CLK_IN
t
Y
Secondary PLL output delay (t
)
PLL_SEC_DELA
PLL_DELAY
—
1.5
ns
1. This condition assures that the output phase jitter will remain within specification.
2. Accumulated jitter measured over 10,000 waveform samples.
3. Internal timing for reference only.
43
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXP sysCONFIG Port Timing Specifications
Symbol
Timing Parameter
Min.
Max.
Units
sysCONFIG Write Cycle Timing
t
t
t
t
t
t
t
t
t
t
f
Input setup time of CS to CCLK rise
Hold time of CS to CCLK rise
Input setup time of write data to CCLK rise
Hold time of write data to CCLK rise
Low time to reset device SRAM
INIT delay time
10
1
—
—
—
—
50
5
ns
ns
SUCS
HCS
10
0
ns
SUWD
HWD
ns
5
ns
PRGM
DINIT
IODISS
IOENSS
WH
—
—
—
18
18
—
ms
ns
User I/O disable
—
—
—
—
27
User I/O enable
ns
Write clock High pulse width
Write clock Low pulse width
ns
ns
WL
Write f
MHz
MAXW
MAX
sysCONFIG Read Cycle Timing
t
t
t
t
f
t
Hold time of READ to CCLK rise
Input setup time of READ High to CCLK rise
READ clock high pulse width
1
—
—
—
—
27
25
ns
ns
HREAD
SUREAD
RH
15
18
18
—
—
ns
READ clock low pulse width
ns
RL
Read f
MHz
ns
MAXR
CORD
MAX
Clock to out for read data
44
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Boundary Scan Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min
40
20
20
8
Max
—
Units
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK [BSCAN] clock pulse width
BTCP
TCK [BSCAN] clock pulse width high
—
ns
BTCPH
BTCPL
BTS
TCK [BSCAN] clock pulse width low
—
ns
TCK [BSCAN] setup time
—
ns
TCK [BSCAN] hold time
10
50
—
—
—
8
—
ns
BTH
TCK [BSCAN] rise/fall time
—
mV/ns
ns
BTRF
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
10
10
10
—
BTCO
ns
BTCODIS
BTCOEN
BTCRS
BTCRH
BUTCO
BTUODIS
BTUPOEN
ns
ns
BSCAN test capture register hold time
10
—
—
—
—
ns
BSCAN test update register, falling edge of clock to valid output
BSCAN test update register, falling edge of clock to valid disable
BSCAN test update register, falling edge of clock to valid enable
25
25
25
ns
ns
ns
45
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Power Consumption
ispXPLD 5000MC Typical ICC vs. Frequency
ispXPLD 5000MV/B Typical ICC vs. Frequency
51024V/B
800
700
600
500
400
300
200
100
800
700
600
500
400
300
200
100
51024MC
5768MV/B
5768MC
5512MC
5256MC
5512V/B
5256V/B
0
0
0
0
100
200
400
100
200
400
Operating Frequency (MHz)
Operating Frequency (MHz)
Note: The device is configured with maximum
number of 16-bit counters, no PLL, typical
current at 3.3V (MV) or 2.5V (MB), 25°C.
Note: The device is configured with maximum
number of 16-bit counters, no PLL, typical
current at 1.8V, 25°C.
Power Estimation Coefficients
DC
ispXPLD
5000MC
ispXPLD
Device
ispXPLD 5256
ispXPLD 5512
ispXPLD 5768
ispXPLD 51024
K0
2.2
2.2
2.2
2.2
K1
8.4
8.4
8.4
8.4
K2
7
K3
12
K4
K5
K6
K7
5000MV/B
100
151
170
200
0.1379 0.0433 6.476
0.1379 0.0433 6.476
0.1379 0.0433 6.476
0.1379 0.0433 6.476
16
17
27
35
24
25
36
43
9.4
10.2
13
18
21
27.6
Note: For further information about the use of these coefficients, refer to technical note TN1031, Power Estimation in ispXPLD 5000MX
Devices.
Memory Coefficients
Device
ispXPLD 5256
ispXPLD 5512
ispXPLD 5768
ispXPLD 51024
K8
K9
K10
4.4
4.4
4.4
4.4
K11
2.9
2.9
2.9
2.9
0.004719
0.004719
0.004719
0.004719
0.0924
0.0924
0.0924
0.0924
• K0 = Current per MFB input (µA/MHz)
• K1 = Current per Product Term (µA/MHz)
• K2 = Current per GRP from MFB (µA/MHz)
• K3 = Current per GRP from I/O (µA/MHz)
• K4 = Global clock tree current (µA/MHz)
• K5 = PLL digital (mA/MHz)
• K6 = PLL analog (mA/MHz)
• K7 = PLL analog baseline (mA)
• DC = Baseline current at 0Mhz (mA)
• K8 = CAM frequency component (mA/MHz)
• K9 = CAM DC component (mA)
• K10 = Current per row decoder (µA/MHz)
46
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
• K11 = Current per column driver (µA/MHz)
Power Estimation Equations
ICC = ICC_DC + IMFB_CPLD + IMFB_ SRAM/PDPRAM/FIFO + IMFB_DPRAM + IMFB_CAM + IPLL_D
ICC_DC
Use the appropriate value for 5000MC (1.8V power supply) or 5000MV/B (2.5V/3.3V power supply) from the data
sheet.
IMFB_CPLD
= ((K0 * CPLD MFB inputs + K1 * CPLD Logical Product Terms + K2 * CPLD GRP from MFB + K3 * CPLD GRP
from IFB) * AF+ K4) * FREQ / 1000µA/mA
IMFB_CAM
= CAM Memory MFBs * ((FREQ * K8) + K9) (CAM operating in typical mode)
IMFB_ SRAM/PDPRAM/FIFO
= (WR_ PERCENT * (K1 + WR_ PERCENT * 8 * K0 + K10 + K11) + RD_ PERCENT * (K1 + 128 * RD_PERCENT
* K0 + 8 * OSW_PERCENT * K2)) * SRAM/PDPRAM/FIFO Memory MFBs * FREQ / 1000µA/mA
IMFB_ DPRAM
= (WR_ PERCENT * (2 * K1 + 2 * WR_ PERCENT * 8 * K0 + K10 + K11) + RD_ PERCENT * (2 * K1 + 2 * 128 *
RD_PERCENT * K0 + 8 * OSW_PERCENT * K2)) * DPRAM Memory MFBs * FREQ / 1000µA/mA
IPLL_D
= K5 * PLL_FREQ * number of PLLs used. IPPL_D is the PLL digital component of the VCC supply current.
Analog portion of PLL supply current consumption, from PLL power pin:
IPLL_A = (K6 * PLL_FREQ + K7) * number of PLLs used
Notes:
• ICC = Current consumption of VCC power supply (mA)
• ICC-DC = ICC DC component – Current consumption at 0Mhz (mA)
• IMFB_CPLD = CPLD (non-memory logic) current consumption (mA)
• IMFB_SRAM/PDPRAM/FIFO = Current consumption for SRAM, PDPRAM, and FIFO (mA)
• IMFB_DPRAM = Current consumption for DPRAM (mA)
• IMFB_CAM = Current consumption for CAM (mA)
• IPLL_D = PLL Current consumption of digital VCC power supply (mA)
• IPLL_A = PLL analog power pin current consumption (VCCP pin)
47
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Switching Test Conditions
Figure 21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 14.
Figure 21. Output Test Load, LVTTL and LVCMOS Standards
V
CCO
R
1
2
Test
Point
Device
Output
R
C *
L
*C includes test fixture and probe capacitance.
L
Table 14. Test Fixture Required Components
Test Condition
R
R
C
Timing Ref.
/2
V
CCO
1
2
L
Default LVCMOS 1.8 I/O (L -> H, H -> L)
106
106
35pF
V
1.8V
LVCMOS3.3 = 3.0V
LVCMOS2.5 = 2.3V
LVCMOS1.8 = 1.65V
1.65V
CCO
LVCMOS3.3 = 1.5V
LVCMOS I/O (L -> H, H -> L)
—
—
35pF
LVCMOS2.5 = V
LVCMOS1.8 = V
/2
/2
CCO
CCO
Default LVCMOS 1.8 I/O (Z -> H)
Default LVCMOS 1.8 I/O (Z -> L)
Default LVCMOS 1.8 I/O (H -> Z)
Default LVCMOS 1.8 I/O (L -> Z)
—
106
—
106
—
35pF
35pF
5pF
V
V
/2
/2
CCO
CCO
1.65V
106
—
V
- 0.15
+ 0.15
1.65V
OH
106
5pF
V
1.65V
OL
Note: Output test conditions for all other interfaces are determined by the respective standards.
48
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Signal Descriptions
Signal Names
Descriptions
TMS
Input – This pin is the Test Mode Select input, which is used to control the IEEE 1149.1
state machine.
TCK
Input – This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state
machine.
TDI
Input – This pin is the IEEE 1149.1 Test Data in pin, used to load data.
Output – This pin is the IEEE 1149.1 Test Data out pin used to shift data out.
Input – Test Output Enable pin. TOE tristates all I/O pins when driven low.
Input – Global output enable inputs.
TDO
TOE
GOE0, GOE1
RESET
Input – This pin resets all the registers in the device. The global polarity for this pin is
selectable on a global basis. The default is active low. An external pull-down is required
when polarity is set to active high.
Input/Output – These are the general purpose I/O used by the logic array. y is the MFB
reference (alpha) and z is the macrocell reference (numeric)
y: A-X (768 macrocells)
yzz
y: A-P (512 macrocells)
y: A-H (256 macrocells)
z: 0-31
GND
NC
GND – Ground
No connect
V
V
V
V
V
– The power supply pins for core logic.
CC
CCO0, CCO1, CCO2, CCO3
CC
CC
V
V
V
– The power supply pins for I/O banks 0, 1, 2, and 3.
V
V
V
Input – This pin defines the reference voltage for I/O banks 0, 1, 2, and 3.
Input – Global clock/clock enable inputs (see Figure 14 for differential pairing).
Output – Optional clock output from PLL 0 and 1.
REF0, REF1, REF2, REF3
GCLK0, GCLK1, GCLK2, GCLK3
CLK_OUT0, CLK_OUT1
PLL_RST0, PLL_RST1
PLL_FBK0, PLL_FBK1
GNDP
Input – Optional input resets the M divider in PLL 0 and 1.
Input – Optional feedback input for PLL 0 and 1.
GND – Ground for PLLs.
V
V
V
V
– The power supply pin for PLLs.
CCP
CCJ
CC
CC
– The power supply for the IEEE 1149.1 interface.
DATAx
CSB
I/O – sysCONFIG data pins, bit x.
Input – sysCONFIG interface chip select. Drive low to select sysCONFIG interface.
Input – Defines SRAM configuration mode. Low: sysCONFIG port, high: E2CMOS or
CFG0
IEEE 1149.1 TAP.
PROGRAMB
CCLK1
Input – Controls the programming of SRAM. Hold high for normal operation. Toggle low
to reload SRAM from E2 memory.
Input – Clock for sysCONFIG interface. Reads and writes occur on the rising edge of
the clock.
READ1
INITB
Input – Drive high to perform reads from the sysCONFIG interface.
I/O – Indicates status of configuration. Can be driven low to inhibit configuration.
Output (open drain) – Indicates status of configuration.
DONE
1. These inputs should not toggle during power up for proper power-up configuration.
49
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Power Supply and NC Connections1
Signals
208 PQFP4
10, 49, 76, 114, D4, D13, F6, F11, L6, A17, A6, AA2, AA21, AB17,
153, 180 L11, N4, N13 AB6, B2, B21, D19, D4, F1,
256 fpBGA3, 5
484 fpBGA, 53
672 fpBGA3, 5
VCC
AA21, AA6, F21, F6, G20, G7, J13,
J14, K13, K14, L13, L14, M13, M14,
F22, G10, G11, G12, G13, K16, N10, N11, N12, N15, N16, N17, N18,
K7, L16, L7, M16, M7, T10, T11, N9, P10, P11, P12, P15, P16, P17,
T12, T13, T14, T9, U1, U22,
W19, W4
P18, P9, R13, R14, T13, T14, U13,
U14, V13, V14, Y20, Y7
VCCO0
VCCO1
VCCO2
5, 17, 189, 204 A1, F7, G6
B9, C3, G8, G9, H7, J2, J7, P4 H10, H11, H8, H9, J8, J9, K8, L8, M8,
N8
42, 57, 72
K6, L7, T1
AA9, R7, T3, T8, Y3
P8, R8, T8, U8, V8, V9, W10, W11,
W8, W9
85, 100, 107,
121
K11, L10, T16
AA14, R16, T15, T20, Y20
P19, R19, T19, U19, V18, V19, W12,
W13, W14, W15, W16, W17, W18,
W19
VCCO3
146, 161, 176 A16, F10, G11
B14, C20, G14, G15, H16, J16, H12, H13, H14, H15, H16, H17, H18,
J21, P19
H19, J18, J19, K19, L19, M19, N19
VCCP
VCCJ
GND
136
27
J16
J1
M22
N25
N4
M1
15, 29, 44, 81, K1, C3, C14, E5, E12, N1, A1, A2, A21, A22, AA1,
119, 148, 185, G7, G8, G9, G10, H7, AA22, AB1, AB22, B1, B22,
7, 19, 191, 205, H8, H9, H10, J7, J8, J9, C15, C8, D11, D12, E18, E5,
40, 56, 70, 87, J10, K7, K8, K9, K10, F17, F6, G16, G7, H10, H11,
A11, A16, A2, A25, AE1, AE2, AE25,
AE26, AF11, AF16, AF2, AF25, B1,
B2, B25, B26, J10, J11, J12, J15, J16,
J17, K10, K11, K12, K15, K16, K17,
101, 109, 123, M5, M12, P3
144, 160, 174
H12, H13, H14, H15, H20, H3, K18, K9, L1, L10, L11, L12, L15, L16,
H8, H9, J10, J11, J12, J13, J14, L17, L18, L26, L9, M10, M11, M12,
J15, J8, J9, K10, K11, K12,
K13, K14, K15, K8, K9, L10,
L11, L12, L13, L14, L15, L19,
L4, L8, L9, M10, M11, M12,
M15, M16, M17, M18, M9, N13, N14,
P13, P14, R10, R11, R12, R15, R16,
R17, R18, R9, T1, T10, T11, T12, T15,
T16, T17, T18, T26, T9, U10, U11,
M13, M14, M19, M4, M9, N10, U12, U15, U16, U17, U18, U9, V10,
N11, N12, N13, N14, N9, P10, V11, V12, V15, V16, V17
P11, P12, P13, P14, P9, R10,
R11, R12, R13, R14, R15, R8,
R9, T16, T7, W11, W12, Y15, Y8
GNDP
NC2
134
—
K16
N22
P26
5256MX: A2, A11, A12, 5512MX:P1, AA19, AB2, AB21, A12, A13, A14, A15, AA10, AA11,
A15, B2, B12, B15,
B16, C4, C12, C15,
C16, D1, D11, D14,
J17, J6, K1, K17, K18, K19, K2, AA12, AA13, AA14, AA15, AA16,
K20, K21, K22, K3, K4, K5, K6, AA17, AA7, AB10, AB11, AB12,
L1, L17, L18, L2, L20, L21, L22, AB13, AB14, AB15, AB16, AB17,
D15, D16, E1, E4, E10, L3, L5, L6, M15, M17, M18, M2, AC10, AC11, AC12, AC13, AC14,
E11, E13, E14, F4, F5, M20, M21, M3, M5, M6, M8, AC15, AC16, AC17, AD11, AD12,
F12, F13, L1, L4, M3, N15, N17, N18, N19, N2, N20, AD13, AD14, AD15, AD16, AE11,
M7, M13, N2, N6, P1, N21, N3, N4, N5, N6, N8, P15, AE12, AE13, AE14, AE15, AE16,
P2, P5, P6, P13, P14, P17, P18, P2, P21, P22, P5, AF12, AF13, AF14, AF15, B11, B12,
P15, P16, R1, R2, R4, P6, P8, U17, U6, V18, V5, W6 B13, B14, B15, B16, C11, C12, C13,
R5, R6, R16, T2, T3,
T4, T5, T6
C14, C15, C16, C3, D10, D11, D12,
D13, D14, D15, D16, D17, E10, E11,
E12, E13, E14, E15, E16, E17, E6,
E7, E8, F10, F11, F12, F13, F14, F15,
F16, F17, G10, G11, G12, G13, G14,
G15, G16, G17, Y10, Y11, Y12, Y13,
Y14, Y15, Y16, Y17
5768MX/51024MX: None
5512MX/5768MX: L1
1. All grounds must be electrically connected at the board level.
2. NC pins should not be connected to any active signals, V or GND.
CC
3. Balls for GND, V and V
are connected within the substrate to their respective common signals. Pin orientation A1 starts from the
CC
CCOX
upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.
4. Pin orientation follows the conventional counter-clockwise order from pin 1 marking of the topside view.
5. Internal GNDs and I/O GNDs (Bank 0 - Bank 3) are connected inside package. V
balls connect to four power planes within the pack-
CCO
age, one each for V
CCOX.
50
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5256MX Logic Signal Connections
Alternate Outputs
Primary Macrocell/
Function
256 fpBGA
Ball Number
sysIO Bank LVDS Pair
Macrocell 1
Macrocell 2
Alternate Input
0
0
0
0
0
0
-
61N
61P
62N
62P
63N
63P
-
H30
G17
G16
G15
G14
G13
G12
-
H17
H16
H15
H14
H13
H12
-
H31
H29
H27
H25
H23
-
B1
H28
C1
H26
D3
H24
C2
H22
E3
H21
D2
VCC
-
VCC
0
0
0
0
-
64N
64P
65N
65P
-
H20
H18/CLK_OUT0
H16
G11
G10
G9
G8
-
H11
H10
H9
H8
-
-
E2
H19
H17
H15
-
F2
F1
H14
G1
GND
GND
0
-
66N
-
H12
G7
-
H7
-
H13
-
F3
VCCO0
H10
VCCO0
0
-
66P
-
G6
-
H6
-
H11
-
G5
GND (Bank 0)
H8
GND (Bank 0)
0
0
0
0
0
0
-
67N
67P
68N
68P
69N
69P
GCLK0P
G5
G4
-
H5
H4
-
H9
H7
-
H5
G4
G3
H3
G2
H1
H2
H6/PLL_RST0
H5
H4/PLL_FBK0
H2
-
-
-
-
-
H3
H1
-
H0
-
-
GCLK0
-
-
See Power Supply and
NC Connections Table
-
-
VCCJ
-
-
-
-
-
GCLK0N
GCLK1
GND
-
-
-
-
-
J2
-
-
-
GND
-
TDI
-
-
-
H6
-
-
TMS
-
-
-
-
H4
-
-
TCK
-
-
J6
-
-
TDO
-
-
-
K2
1
1
1
1
1
1
-
0P
0N
1P
1N
2P
2N
-
A0/DATA0
A2/DATA1
A4/DATA2
A5/DATA3
A6/DATA4
A8/DATA5
GND (Bank 1)
A10/DATA6
VCCO1
A12/DATA7
GND
A0
A1
A2
A3
A4
A5
-
B0
B1
B2
B3
B4
B5
-
A1
A3
-
K3
J3
J5
-
J4
A7
A9
-
L2
M1
GND (Bank 1)
K4
1
-
3P
-
A6
-
B6
-
A11
-
VCCO1
L3
1
-
3N
-
A7
-
B7
-
A13
-
GND
1
4P
A14/INITB
A8
B8
A15
K5
51
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5256MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
256 fpBGA
sysIO Bank LVDS Pair
Function
A16/CSB
A18/READ
A20/CCLK
VCC
Macrocell 1
A9
Macrocell 2
B9
Alternate Input
Ball Number
1
1
1
-
4N
5P
5N
-
A17
A19
A21
-
L5
A10
A11
-
B10
B11
-
N1
M2
VCC
-
-
DONE
A22
-
-
-
M4
1
1
1
1
-
6P
6N
7P
7N
-
A12
A13
A14
A15
-
B12
B13
B14
B15
-
A23
A25
A27
A29
-
N3
A24
P4
A26
N5
A28
M6
PROGRAMB
GND (Bank 1)
VCCO1
CFG0
B2
R3
-
-
-
-
-
GND (Bank 1)
-
-
-
-
-
VCC01
-
-
-
-
-
L8
1
1
1
1
1
1
1
1
1
1
1
-
8P
8N
9P
9N
10P
10N
11P
11N
-
A16
A17
A18
A19
A20
A21
A22
A23
-
B16
B17
B18
B19
B20
B21
B22
B23
-
B3
-
T7
R7
B4
B5
-
N7
B6
B7
B9
B11
B13
B15
B17
B19
-
P7
B8
T8
B10
R8
B12
M8
B14
P8
B16/VREF1
B18
L9
12P
12N
-
A24
A25
-
B24
B25
-
N8
B20
M9
GND (Bank 1)
B21
-
GND (Bank 1)
N10
1
-
13P
-
A26
-
B26
-
-
VCCO1
B22
-
VCCO1
T9
1
1
1
-
13N
14P
14N
-
A27
A28
A29
-
B27
B28
B29
-
B23
B25
B27
-
B24
T10
B26
R9
VCC
VCC
P9
1
1
2
2
2
2
2
-
15P
15N
16P
16N
17P
17N
18P
-
B28
A30
A31
C0
C1
C2
C3
C4
-
B30
B31
D0
D1
D2
D3
D4
-
B29
B31
C1
C3
-
B30
N9
C0
T11
C2
T12
C4
P10
C5
-
R10
C6
C7
-
R11
VCCO2
C8
VCCO2
M10
GND (Bank 2)
M11
T13
2
-
18N
-
C5
-
D5
-
C9
-
GND (Bank 2)
C10
2
2
19P
19N
C6
C7
D6
D7
C11
C13
C12
52
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5256MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
256 fpBGA
sysIO Bank LVDS Pair
Function
C14
Macrocell 1
Macrocell 2
Alternate Input
Ball Number
2
2
2
2
2
2
2
2
2
2
-
20P
20N
21P
21N
22P
22N
23P
23N
24P
24N
-
-
-
C15
C17
C19
-
P11
T14
C16/VREF2
C18
-
-
C8
C9
C10
C11
C12
C13
C14
C15
-
D8
D9
D10
D11
D12
D13
D14
D15
-
R12
C20
R13
C21
-
N11
C22
C23
C25
C27
C29
C31
-
T15
C24
R14
C26
N12
C28
P12
C30
R15
VCCO2
GND (Bank 2)
D0
VCCO2
GND (Bank 2)
N15
-
-
-
-
-
2
2
2
2
2
2
-
25P
25N
26P
26N
27P
27N
-
-
-
D1
D3
-
D2
-
-
N14
D4
C16
C17
C18
C19
-
D16
D17
D18
D19
-
N16
D5
-
M16
D6
D7
D9
-
M14
D8
M15
VCC
VCC
L13
2
2
2
2
-
28P
28N
29P
29N
-
D10
C20
C21
C22
C23
-
D20
D21
D22
D23
-
D11
D13
D15
D17
-
D12
L12
D14
L15
D16
L16
GND
D18
GND
L14
2
-
30P
-
C24
-
D24
-
D19
-
VCCO2
D20
VCCO2
K15
2
-
30N
-
C25
-
D25
-
-
GND (Bank 2)
D21
-
GND (Bank 2)
K14
2
2
2
2
2
2
-
31P
31N
32P
32N
33P
33N
-
C26
C27
C28
C29
C30
C31
-
D26
D27
D28
D29
D30
D31
-
-
D22
D23
D25
D27
D29
D31
-
K12
D24
K13
D26
J13
D28
J14
D30
J12
TOE
J15
-
-
RESET
GOE0
GOE1
-
-
-
J11
-
-
-
-
-
H11
-
-
-
-
-
H13
See Power Supply and
NC Connections Table
-
-
-
-
-
GNDP
GCLK2
VCCP
-
-
-
-
-
-
-
-
-
-
-
-
GCLK3N
-
H15
See Power Supply and
NC Connections Table
GCLK3P
GCLK3
H16
53
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5256MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
256 fpBGA
Ball Number
sysIO Bank LVDS Pair
Function
Macrocell 1
Macrocell 2
Alternate Input
3
3
3
3
3
3
-
34N
34P
35N
35P
36N
36P
-
E30
-
-
E31
E29
E27
E25
E23
-
H14
G16
E28
-
-
E26
-
-
G15
E24/PLL_FBK1
-
-
F15
E22/PLL_RST1
E27
E26
-
F27
F26
-
H12
E21
G14
GND (Bank 3)
-
GND (Bank 3)
F16
3
-
37N
-
E20
E25
-
F25
-
-
VCCO3
-
VCCO3
E16
3
-
37P
-
E18
E24
-
F24
-
E19
-
GND
GND
G13
3
3
3
3
-
38N
38P
39N
39P
-
E16
E23
E22
E21
E20
-
F23
F22
F21
F20
-
E17
E15
E13
E11
-
E14
G12
E12
F14
E10/CLK_OUT1
E15
VCC
VCC
D12
3
3
3
3
3
3
-
40N
40P
41N
41P
42N
42P
-
E8
E19
E18
E17
E16
E31
E30
-
F19
F18
F17
F16
F31
F30
-
E9
E7
-
E6
B14
E5
C13
E4
E2
-
A14
E3
E1
-
A13
E0
B13
GND (Bank 3)
VCCO3
F30
GND (Bank 3)
VCCO3
B11
-
-
-
-
-
3
3
3
3
3
3
3
3
3
3
3
3
-
43N
43P
44N
44P
45N
45P
46N
46P
47N
47P
48N
48P
-
E15
E14
E13
E12
E11
E10
E9
E8
E29
E28
E7
E6
-
F15
F14
F13
F12
F11
F10
F9
F8
F29
F28
F7
F6
-
F31
F29
F27
F25
F23
-
F28
C11
F26
B10
F24
A10
F22
C10
F21
D10
F20
-
C9
F18
F19
F17
F15
F13
F11
-
E9
F16/VREF3
F14
D9
F9
F12
A9
F10
F8
GND (Bank 3)
F8
GND (Bank 3)
E8
3
-
49N
-
E5
-
F5
-
F9
-
VCCO3
F6
VCCO3
A8
3
3
3
-
49P
50N
50P
-
E4
E3
E2
-
F4
F3
F2
-
F7
-
F5
B9
F4
-
D8
VCC
-
VCC
54
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5256MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
256 fpBGA
sysIO Bank LVDS Pair
Function
F2
Macrocell 1
E1
Macrocell 2
F1
Alternate Input
Ball Number
3
3
0
0
-
51N
51P
52N
52P
-
F3
F1
G31
G29
-
B8
F0
E0
F0
C8
G30
G31
G30
-
H31
H30
-
B7
G28
A7
GND
G26
NC
0
0
0
-
53N
53P
54N
-
G29
G28
G27
-
H29
H28
H27
-
G27
G25
G23
-
D7
G24
C7
G22
B6
VCCO0
G21
VCCO0
0
-
54P
-
G26
-
H26
-
-
E7
GND (Bank 0)
G20
-
GND (Bank 0)
0
0
0
0
0
0
0
0
0
0
0
0
-
55N
55P
56N
56P
57N
57P
58N
58P
59N
59P
60N
60P
-
G25
G24
G3
H25
H24
H3
-
E6
G18
G19
G17
G15
G13
G11
G9
G7
-
A6
G16/VREF0
G14
A5
G2
H2
A4
G12
G23
G22
G21
G20
G19
G18
G1
H23
H22
H21
H20
H19
H18
H1
B5
G10
A3
G8
B4
G6
B3
G5
C5
C6
G4
-
G2
G3
G1
-
D5
G0
G0
H0
D6
VCCO0
GND (Bank 0)
-
-
VCCO0
GND (Bank 0)
-
-
-
-
-
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs
55
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5512MX Logic Signal Connections
Alternate Outputs
sysIO
Bank
LVDS
Pair
Primary Macrocell/
Function
Alternate 208 PQFP
256 fpBGA
484 fpBGA
Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number
0
0
109N
109P
110N
110P
111N
—
O30
O28
O26
O24
O22
O11
O10
M17
M16
M15
—
P18
P16
O17
O16
O15
—
O31
O29
O27
O25
O23
—
208
1
C4
E4
B1
C1
D3
B4
A4
B3
A3
F5
0
2
0
3
0
4
—
0
V
5
V
V
CCO0
CCO0
CCO0
111P
—
O20
GND (Bank 0)
O18
M14
—
O14
—
O21
—
6
C2
G6
—
0
7
GND (Bank 0) GND (Bank 0)
112N
112P
113N
113P
114N
114P
115N
115P
116N
—
M13
M12
O9
O8
O7
O6
O5
O4
O3
—
O13
O12
P14
P12
P10
P8
O19
O17
O15
O13
O11
O9
8
E3
D2
—
—
—
—
—
—
—
H6
G5
D3
D2
E4
E3
F4
G4
C2
0
O16
9
0
O14
—
—
—
—
—
—
—
—
—
—
—
—
—
10
—
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0
O12
0
O10
0
O8
0
O6
P6
O7
0
O4
P4
O5
0
O2
P2
O3
—
0
V
—
—
V
V
CCO0
CCO0
CCO0
116P
—
O0
O2
—
P0
O1
—
C1
—
0
GND (Bank 0)
—
—
GND (Bank 0) GND (Bank 0)
117N
117P
118N
—
P30
P28
P26
O1
O0
O31
—
—
P31
P29
P27
—
D1
E1
F4
F3
G3
H4
0
—
0
—
—
0
V
—
V
V
CC
CC
CC
118P
119N
119P
120N
120P
—
P24
P22
O30
M11
M10
M9
M8
—
—
P25
P23
P21
P19
P17
—
F5
J4
0
O11
O10
O9
O8
—
E2
F2
H5
J5
0
P20/CLK_OUT0
P18
0
F1
E2
0
P16
G1
GND
F3
F2
—
0
GND
GND
D1
121N
—
P14
M7
—
O7
—
P15
—
—
0
V
V
V
CCO0
CCO0
CCO0
121P
—
P12
GND (Bank 0)
P10
M6
—
O6
—
P13
—
G5
E1
—
0
GND (Bank 0) GND (Bank 0)
122N
122P
123N
123P
124N
124P
GCLK0P
M5
M4
—
O5
O4
—
P11
P9
H5
G4
G3
H3
G2
H1
H2
J3
H2
G2
G1
H1
J1
0
P8/PLL_RST0
P6
0
P7
0
P4/PLL_FBK0
P2
—
—
P5
0
—
—
P3
0
P0
—
—
P1
—
GCLK0
—
—
—
N7
See Power Supply and
NC Connections Table
—
—
V
—
—
—
CCJ
56
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5512MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
LVDS
Pair
Primary Macrocell/
Function
Alternate 208 PQFP
256 fpBGA
484 fpBGA
Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number
—
—
—
—
—
—
1
GCLK0N
—
GCLK1
GND
—
—
—
—
—
—
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
—
49
—
—
—
—
—
—
—
—
—
—
—
—
50
51
52
53
54
55
—
56
J2
GND
H6
H4
J6
P7
GND
R1
R2
T1
—
TDI
—
—
—
—
TMS
—
—
—
—
TCK
—
—
—
—
TDO
—
—
—
K2
K3
J3
V1
0P
0N
1P
1N
2P
2N
—
A0/DATA0
A2/DATA1
A4/DATA2
A6/DATA3
A8/DATA4
A10/DATA5
GND (Bank 1)
A12/DATA6
B0
B1
B2
B3
B4
B5
—
D0
D1
D2
D3
D4
D5
—
A1
W1
Y1
1
A3
1
A5
J5
P3
1
A7
J4
R3
T2
1
A9
L2
1
A11
—
M1
U2
—
1
GND (Bank 1) GND (Bank 1)
3P
—
B6
—
D6
—
A13
—
K4
V2
—
1
V
V
V
CCO1
CCO1
CCO1
3N
—
A14/DATA7
GND
B7
—
D7
—
A15
—
L3
W2
—
1
GND
K5
GND
R4
4P
4N
5P
5N
6P
—
A16/INITB
A18/CSB
A20/READ
A22/CCLK
A24
B8
B9
B10
B11
—
D8
D9
D10
D11
—
A17
A19
A21
A23
A25
—
1
L5
T4
1
N1
R6
1
M2
—
R5
1
U3
—
1
VCC
—
—
VCC
P11
M3
L4
VCC
V3
6N
7P
7N
8P
8N
—
A26
—
—
A27
A29
A31
B1
1
A28
—
—
Y2
1
A30
—
—
W3
U5
1
B0
A0
A2
—
—
N2
1
B2
—
B3
P2
T5
—
1
GND (Bank 1)
B4
—
—
GND (Bank 1) GND (Bank 1)
9P
—
A4
—
—
—
R1
U4
—
1
V
—
—
V
V
CCO1
CCO1
CCO1
9N
10P
10N
—
B5
A6
A8
A10
A12
—
—
—
R2
V4
1
B6
B8
—
B7
T2
T3
—
AA3
AB3
Y4
1
—
B9
1
B10
DONE
B14
—
B11
—
—
1
—
—
M4
N3
P4
N5
M6
R3
P5
AA4
AB4
AB5
T6
11P
11N
12P
12N
—
B12
B13
B14
B15
—
D12
D13
D14
D15
—
B15
B17
B19
B21
—
1
B16
1
B18
1
B20
U7
—
1
PROGRAMB
B22
W5
U8
—
A14
—
—
B23
—
—
—
GND (Bank 1)
—
GND (Bank 1) GND (Bank 1)
57
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5512MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
LVDS
Pair
Primary Macrocell/
Function
Alternate 208 PQFP
256 fpBGA
484 fpBGA
Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number
1
—
1
13P
—
B24
A16
—
—
—
B25
—
—
57
—
—
—
—
—
—
—
—
—
—
—
—
58
—
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
—
82
83
84
T4
V6
V
V
V
CCO1
CCO1
CCO1
13N
14P
14N
15P
15N
16P
16N
17P
17N
18P
18N
—
B26
A18
A20
A22
—
—
B27
B29
B31
C1
T5
V7
1
B28
—
R4
N6
R5
P6
—
Y5
1
B30
—
AA5
Y6
1
C0
—
1
C2
—
—
C3
Y7
1
C4
C8
—
—
C5
AA6
AA7
W7
V8
1
—
—
C9
—
1
C10
—
—
C11
C13
C17
C19
—
—
M71
1
C12
—
—
1
C16
—
—
T6
W8
U9
1
C18
—
—
R6
—
—
—
1
GND0 (Bank 1)
CFG0
—
—
GND (Bank 1) GND (Bank 1)
—
—
—
—
L8
U10
—
V
—
—
—
V
V
CCO1
CCO1
CCO1
19P
19N
20P
20N
21P
21N
22P
22N
—
C24
C26
C28
D0
B16
B17
B18
B19
B20
B21
B22
B23
—
D16
D17
D18
D19
D20
D21
D22
D23
—
C25
C27
C29
D1
T7
AB7
1
R7
N7
P7
T8
R8
M8
P8
L9
AA8
AB8
AB9
W9
1
1
1
D2
D3
1
D4
D5
Y9
1
D6
D7
AB10
AA10
W10
Y10
Y11
1
D8
D9
1
D10/V
D11
D13
D17
—
REF1
1
23P
23N
—
D12
D16
B24
B25
—
D24
D25
—
N8
M9
1
—
1
GND (Bank 1)
D18
GND (Bank 1) GND (Bank 1)
24P
—
B26
—
D26
—
D19
—
N10
V9
—
1
VCCO1
D20
V
V
CCO1
CCO1
24N
25P
25N
—
B27
B28
B29
—
D27
D28
D29
—
D21
D23
D25
—
T9
V10
AA11
AB11
VCC
U11
1
D22
T10
R9
1
D24
—
1
VCC
D26
VCC
P9
26P
26N
27P
27N
—
B30
B31
F0
D30
D31
H0
H1
—
D27
D29
E1
1
D28
N9
V11
2
E0
T11
T12
NC
AB12
AA12
GND
GND
Y12
2
E2
F1
E3
—
—
2
GND
GND
E4
—
—
—
—
—
—
GND
P10
R10
R11
28P
28N
29P
F2
H2
H3
H4
E5
2
E6
F3
E7
AA13
V12
2
E8
F4
E9
58
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5512MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
LVDS
Pair
Primary Macrocell/
Function
Alternate 208 PQFP
256 fpBGA
484 fpBGA
Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number
—
2
—
V
—
F5
—
—
H5
—
—
E11
—
85
86
87
88
89
90
91
92
93
94
95
96
97
98
—
V
V
CCO2
CCO2
CCO2
29N
—
E10
GND (Bank 2)
E12
M10
U12
—
2
GND (Bank 2) GND (Bank 2)
30P
30N
31P
31N
32P
32N
33P
33N
34P
34N
35P
—
F6
F7
—
H6
H7
—
E13
E17
E19
E21
E23
E25
E27
E29
F1
M11
T13
P11
T14
R12
R13
N11
T15
R14
N12
P12
AB13
Y13
2
E16
2
E18
V13
2
E20/V
—
—
W13
V14
REF2
2
E22
F8
F9
F10
F11
F12
F13
F14
—
H8
H9
H10
H11
H12
H13
H14
—
2
E24
E26
E28
F0
W14
Y14
2
2
AB14
AB15
AA15
U13
2
2
F2
F3
2
F4
F5
—
2
V
—
V
V
CCO2
CCO2
CCO2
35N
—
F6
F15
—
H15
—
F7
99
—
R15
U14
—
2
GND (Bank 2)
F8
—
GND (Bank 2) GND (Bank 2)
36P
36N
37P
37N
38P
38N
39P
39N
40P
40N
41P
—
E0
E2
E4
E6
E8
E10
E12
E16
E20
E22
—
—
F9
—
—
—
—
—
—
—
—
—
—
—
—
W15
W16
Y16
2
F10
—
F11
F13
F17
F19
F21
F23
F25
F27
F29
G1
—
2
F12
—
—
2
F16
—
—
AA16
AB16
AA17
Y17
2
F18
—
—
2
F20
—
—
2
F22
—
—
2
F24
—
—
AA18
W17
W18
V15
2
F26
—
—
2
F28
—
—
2
G0
—
—
—
2
V
—
—
—
100
—
V
V
CCO2
CCO2
CCO2
41N
—
G2
—
—
G3
—
U15
—
2
GND (Bank 2)
G4
—
—
—
101
102
103
—
GND (Bank 2) GND (Bank 2)
42P
42N
43P
43N
44P
44N
45P
45N
46P
46N
47P
—
—
—
G5
P13
P15
M13
P14
—
Y18
V17
2
G6
—
—
G7
2
G8
—
—
G9
V16
2
G10
—
—
G11
G13
G15
G17
G19
G21
G23
G25
—
—
U16
2
G12
—
—
—
AB18
AB19
U18
2
G14
—
—
—
—
2
G16
—
—
—
—
2
G18
—
—
—
—
T17
2
G20
—
—
104
105
106
107
R16
P16
N15
AB20
AA20
Y19
2
G22
—
—
2
G24
—
—
—
V
—
—
V
V
CCO2
CCO2
CCO2
59
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5512MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
LVDS
Pair
Primary Macrocell/
Function
Alternate 208 PQFP
256 fpBGA
484 fpBGA
Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number
2
—
2
47N
—
G26
—
—
—
—
G27
—
108
109
110
111
112
113
—
N14
V19
GND (Bank 2)
GND (Bank 2) GND (Bank 2)
48P
48N
49P
49N
50P
—
G28
G30
H0
F16
F17
F18
F19
E24
—
H16
H17
H18
H19
—
G29
G31
H1
H3
H5
—
N16
M16
M14
M15
—
T18
R17
U19
T19
2
2
2
H2
2
H4
V20
VCC
U20
W20
Y21
R18
R19
GND
W21
—
2
V
—
114
—
VCC
NC
CC
50N
51P
51N
52P
52N
—
H6
H8
E26
F20
F21
F22
F23
—
—
H7
H9
H11
H13
H15
—
2
H20
H21
H22
H23
—
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
L13
L12
L15
L16
GND
L14
2
H10
H12
H14
GND
H16
2
2
—
2
53P
—
F24
—
H24
—
H17
—
—
2
V
V
V
CCO2
CCO2
CCO2
53N
—
H18
F25
—
H25
—
H19
—
K15
Y22
—
2
GND (Bank 2)
H20
GND (Bank 2) GND (Bank 2)
54P
54N
55P
55N
56P
56N
—
F26
F27
F28
F29
F30
F31
—
H26
H27
H28
H29
H30
H31
—
H21
H23
H25
H27
H29
H31
—
K14
K12
K13
J13
J14
J12
J15
J11
H11
H13
R20
P20
T21
R21
U21
V21
W22
V22
T22
R22
2
H22
2
H24
2
H26
2
H28
2
H30
—
—
—
—
—
—
—
—
3
TOE
—
RESET
GOE0
GOE1
GNDP
GCLK2
—
—
—
—
—
—
—
—
—
—
—
See Power Supply and NC Connections Table
—
—
—
—
GCLK3N
—
—
—
—
135
H15
P16
See Power Supply and NC Connections Table
V
—
—
—
CCP
GCLK3P
57N
57P
58N
58P
59N
59P
—
GCLK3
—
—
—
137
138
139
140
141
142
143
144
145
146
147
148
H16
H14
G16
G15
F15
H12
G14
N16
J22
I30
—
—
I31
I29
I27
I25
I23
I21
—
3
I28
I26
—
—
H22
E22
E21
G22
F21
3
—
—
3
I24/PLL_FBK1
I22/PLL_RST1
I20
—
—
3
I27
I26
—
K27
K26
—
3
—
3
GND (Bank 3)
I18
GND (Bank 3) GND (Bank 3)
F16 H21
60N
—
I25
—
K25
—
I19
—
—
3
VCCO3
I16
V
V
CCO3
CCO3
60P
—
I24
—
K24
—
I17
—
E16
G21
—
GND
GND
GND
60
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5512MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
LVDS
Pair
Primary Macrocell/
Function
Alternate 208 PQFP
256 fpBGA
484 fpBGA
Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number
3
3
61N
61P
62N
62P
63N
—
I14
I23
I22
I21
I20
K31
—
K23
K22
K21
K20
—
I15
I13
I11
I9
149
150
151
152
—
G13
G12
F14
E15
F12
VCC
F13
D16
D15
D22
D21
J20
I12
3
I10
I8/CLK_OUT1
I6
3
J19
3
I7
E20
VCC
F20
H17
H18
—
3
V
—
—
153
—
CC
63P
64N
64P
—
I4
K30
K29
K28
—
L30
L28
L26
—
I5
3
I2
I3
—
3
I0
GND (Bank 3)
J30
I1
—
—
3
—
—
GND (Bank 3) GND (Bank 3)
65N
—
K27
—
—
J31
—
—
—
J18
—
3
V
—
—
V
V
CCO3
CCO3
CCO3
65P
66N
66P
67N
67P
68N
68P
69N
69P
—
J28
K26
K25
K24
K23
K22
K21
K20
K19
K18
—
—
J29
J27
J25
J23
J21
J19
J17
J15
J13
—
—
—
H19
G20
G19
C22
C21
D20
C19
F19
E19
3
J26
J24
J22
J20
J18
J16
J14
J12
—
—
—
—
—
—
—
—
3
—
—
3
—
—
3
—
—
3
—
—
3
—
—
3
—
—
C16
B16
3
—
—
—
3
GND (Bank 3)
J10
—
—
GND (Bank 3) GND (Bank 3)
C15 G18
70N
—
K17
—
—
J11
—
—
—
3
V
—
—
V
V
CCO3
CCO3
CCO3
70P
71N
71P
72N
72P
73N
73P
74N
74P
75N
75P
—
J8
K16
K15
K14
K13
K12
I19
I18
I17
I16
I31
I30
—
—
J9
—
B15
F18
3
J6
J4
J2
J0
—
J7
—
E14
D14
E13
A15
D12
B14
C13
A14
A13
B13
B20
B19
A20
A19
D18
C18
G17
F16
E17
D17
3
—
J5
—
3
—
J3
—
3
—
J1
—
3
K30
K28
K19
K18
K17
K16
K31
K30
—
K31
K29
K27
K25
K23
—
154
155
156
157
158
159
160
—
3
3
K26
3
K24
3
K22
3
K21
—
3
GND (Bank 3)
K20
—
GND (Bank 3) GND (Bank 3)
D11 B18
76N
—
K11
—
L21
—
—
—
3
V
—
161
—
V
V
CCO3
CCO3
CCO3
76P
77N
77P
78N
78P
K18
K16
K14
K12
K10
K10
K9
L20
L18
L16
L12
L10
K19
K17
K15
K13
K11
B12
A18
3
—
C12
E11
—
C17
B17
C16
B16
3
K8
—
3
K7
—
3
K6
—
—
61
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5512MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
LVDS
Pair
Primary Macrocell/
Function
Alternate 208 PQFP
256 fpBGA
484 fpBGA
Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number
3
3
79N
79P
80N
80P
81N
81P
—
K8
K5
K4
K3
K2
K1
K0
—
L8
L6
K9
K7
—
—
—
F13
F15
D16
E16
A16
A15
K6
—
3
K5
L5
—
—
—
3
K4
L4
—
—
E101
A12
A11
3
K2
K0
L2
K3
—
3
L0
K1
—
—
3
GND (Bank 3)
L30
—
—
—
GND (Bank 3) GND (Bank 3)
B11 B15
82N
—
I15
—
K15
—
L31
—
162
—
—
3
V
V
V
CCO3
CCO3
CCO3
82P
83N
83P
84N
84P
85N
85P
86N
86P
87N
87P
—
L28
L26
I14
I13
I12
I11
I10
I9
K14
K13
K12
K11
K10
K9
L29
L27
L25
L23
—
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
—
C11
A14
3
B10
A10
C10
D10
C9
D15
E15
D14
F14
A13
B13
C14
E14
E13
F12
3
L24
3
L22
3
L21
3
L20
—
3
L18
I8
K8
L19
L17
L15
L13
L11
—
E9
3
L16/VREF3
L14
I29
I28
I7
K29
K28
K7
D9
3
F9
3
L12
A9
3
L10
I6
K6
F8
—
3
GND (Bank 3)
L8
—
—
GND (Bank 3) GND (Bank 3)
88N
—
I5
K5
L9
E8
D13
—
3
V
—
—
—
V
V
CCO3
CCO3
CCO3
88P
89N
89P
—
L6
I4
K4
L7
A8
C13
3
L5
L4
I3
K3
—
B9
D8
E12
C12
VCC
B12
A12
E11
C11
GND
GND
B11
A11
F11
3
I2
K2
—
—
3
VCC
L2
—
—
—
VCC
B8
90N
90P
91N
91P
—
I1
K1
L3
3
L0
I0
K0
L1
C8
0
M30
M28
GND
GND
M26
M24
M22
M31
M30
—
O31
O30
—
M31
M29
—
B7
0
A7
—
—
0
—
—
—
—
—
GND
D7
92N
92P
93N
—
M29
M28
M27
—
O29
O28
O27
—
M27
M25
M23
—
186
187
188
189
190
191
192
193
194
195
0
C7
0
B6
—
0
V
V
V
CCO0
CCO0
CCO0
93P
—
M21
M26
—
O26
—
M22
—
E7
F10
—
0
GND (Bank 0)
M20
GND (Bank 0) GND (Bank 0)
94N
94P
95N
95P
M25
M24
M3
M2
O25
O24
O3
O2
M21
M19
M17
M15
E6
A6
A5
A4
E10
C10
D10
B10
0
M18
0
M16/V
REF0
0
M14
62
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5512MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
LVDS
Pair
Primary Macrocell/
Function
Alternate 208 PQFP
256 fpBGA
484 fpBGA
Macrocell 1 Macrocell 2 Input Pin Number Ball Number Ball Number
0
0
96N
96P
M12
M10
M8
M23
M22
M21
M20
M19
M18
M1
O23
O22
O21
O20
O19
O18
O1
—
M13
M11
M9
M7
—
196
197
198
199
200
201
202
—
B5
A3
B4
B3
C5
C6
D5
A10
A9
C9
D9
F9
0
97N
0
97P
M6
0
98N
M5
0
98P
M4
—
E9
A8
0
99N
M2
M3
—
—
0
—
V
—
V
V
CCO0
CCO0
CCO0
99P
M0
M0
O0
—
M1
—
203
—
D6
B8
—
0
—
GND (Bank 0)
N30
—
GND (Bank 0) GND (Bank 0)
100N
100P
101N
101P
102N
102P
103N
103P
104N
104P
105N
—
O29
O28
O27
O26
O25
O24
O23
O22
O21
O20
O19
—
—
N31
N29
N27
N25
N23
—
—
—
—
—
—
—
—
—
—
—
—
—
A7
B7
A5
B5
B6
C7
E8
E7
E6
D6
D8
0
N28
—
—
0
N26
—
—
0
N24
—
—
0
N22
—
—
0
N21
—
—
0
N20
—
—
—
0
N18
—
N19
N17
N15
N13
—
—
0
N16
—
—
0
N14
—
—
0
N12
—
—
—
0
V
—
204
—
V
V
CCO0
CCO0
CCO0
105P
—
N10
O18
—
—
N11
—
—
F8
—
0
GND (Bank 0)
—
205
—
GND (Bank 0) GND (Bank 0)
106N
106P
107N
107P
108N
108P
N8
N6
N5
N4
N2
N0
O17
O16
O15
O14
O13
O12
—
N9
—
—
A2
B2
—
—
F7
D7
C6
C5
C4
D5
0
—
N7
—
0
—
—
206
207
—
0
—
—
0
—
N3
0
—
N1
—
1. Not available for differential pair.
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs.
63
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections
Alternate Outputs
Primary Macrocell/
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Function
Macrocell 1
S11
S10
Q17
Q16
Q15
-
Macrocell 2
Ball Number Ball Number
0
0
0
0
0
-
127N
127P
128N
128P
129N
-
S22
T18
T16
S17
S16
S15
-
S23
S21
S19
S17
S15
-
C4
E4
B4
A4
S20
S18
B1
B3
S16
C1
A3
S14
D3
F5
VCCO0
VCCO0
C2
VCCO0
G6
0
-
129P
-
S12
Q14
-
S14
-
S13
-
GND (Bank 0)
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
-
130N
130P
131N
131P
132N
-
S10
Q13
Q12
S9
S13
S12
T14
T12
T10
-
S11
S9
S7
S5
S3
-
E3
D2
H6
G5
S8
S6
—
D3
S4
S8
—
D2
S2
S7
—
E4
VCC
-
VCC
—
VCC
E3
0
-
132P
-
S0
S6
T8
-
S1
-
GND
-
GND
—
GND
F4
0
0
0
-
133N
133P
134N
-
T30
S5
T6
T4
T2
-
T31
T29
T27
-
T28
S4
—
G4
T26
S3
—
C2
VCCO0
-
VCCO0
—
VCCO0
C1
0
-
134P
-
T24
S2
T0
-
T25
-
GND (Bank 0)
-
GND (Bank 0) GND (Bank 0)
0
0
0
-
135N
135P
136N
-
T22
S1
-
T23
T21
T19
-
D1
E1
F3
G3
T20
S0
-
T18
S31
-
-
F4
H4
VCC
-
VCC
F5
VCC
J4
0
0
0
0
0
-
136P
137N
137P
138N
138P
-
T16
S30
Q11
Q10
Q9
Q8
-
-
T17
T15
T13
T11
T9
T14
S11
S10
S9
S8
-
E2
H5
T12/CLK_OUT0
F2
J5
T10
F1
E2
T8
G1
F2
GND
-
GND
F3
GND
D1
0
-
139N
-
T6
VCCO0
T4
Q7
-
S7
-
T7
-
VCCO0
G5
VCCO0
E1
0
-
139P
-
Q6
-
S6
-
T5
GND (Bank 0)
T2
-
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
140N
140P
141N
141P
142N
142P
Q5
Q4
U31
U30
U29
U28
S5
S4
W31
W30
W29
W28
T3
H5
G4
G3
H3
—
J3
H2
G2
G1
J6
T0/PLL_RST0
U30
T1
U31
U29
U27
U25
U28/PLL_FBK0
U26
U24
—
K4
64
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
U27
-
Macrocell 2
W27
-
Ball Number Ball Number
0
-
143N
-
U22
VCCO0
U20
U23
-
—
VCCO0
—
K6
VCCO0
K3
0
-
143P
-
U26
-
W26
-
U21
-
GND (Bank 0)
U18
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
0
0
0
-
144N
144P
145N
145P
146N
146P
147N
147P
148N
-
U25
U24
U23
U22
U21
U20
U19
U18
U17
-
W25
W24
W23
W22
W21
W20
W19
W18
W17
-
U19
U17
U15
U13
U11
U9
U7
U5
U3
-
—
—
K5
K2
U16
U14
—
L5
U12
—
K1
U10
—
L6
U8
—
L1
U6
—
M5
L2
U4
—
U2
—
N5
VCCO0
U0
VCCO0
—
VCCO0
L3
0
-
148P
-
U16
-
W16
-
U1
-
GND (Bank 0)
W30
GND (Bank 0) GND (Bank 0)
0
0
0
-
149N
149P
150N
-
U15
U14
U13
-
W15
W14
W13
-
W31
W29
W27
-
—
—
M6
M2
W28
W26
—
P5
VCC
VCC
—
VCC
P6
0
0
0
0
0
-
150P
151N
151P
152N
152P
-
W24
U12
U11
U10
U9
W12
W11
W10
W9
W8
-
W25
W23
W21
W19
W17
-
W22
—
M3
W20
—
N6
W18
—
N2
W16
U8
—
P1
GND
W14
-
GND
—
GND
N3
0
-
153N
-
U7
W7
-
W15
-
VCCO0
W12
-
VCCO0
—
VCCO0
M8
0
-
153P
-
U6
W6
-
W13
-
GND (Bank 0)
W10
-
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
-
154N
154P
155N
155P
156N
156P
GCLK0P
U5
W5
W4
W3
W2
W1
W0
-
W11
-
—
—
N8
P2
P8
N4
H1
J1
W8
U4
W6
U3
W7
W5
W3
W1
-
—
W4
U2
—
W2
U1
G2
H1
H2
W0
U0
GCLK0
-
N7
See Power Supply and
NC Connections Table
-
-
VCCJ
-
-
-
-
-
-
-
GCLK0N
GCLK1
GND
TDI
-
-
-
-
-
-
-
-
-
-
-
-
J2
GND
H6
P7
GND
R1
-
-
-
TMS
H4
R2
65
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
Macrocell 2
Ball Number Ball Number
-
-
-
TCK
TDO
-
-
-
-
J6
K2
K3
J3
T1
V1
W1
Y1
P3
R3
T2
U2
-
-
-
1
1
1
1
1
1
-
0P
0N
1P
1N
2P
2N
-
A30/DATA0
A28/DATA1
A26/DATA2
A24/DATA3
A22/DATA4
A20/DATA5
GND (Bank 1)
A18/DATA6
VCCO1
A16/DATA7
GND
C0
C1
C2
C3
C4
C5
-
A0
A31
A29
A27
A25
A23
A21
-
A1
A2
J5
A3
J4
A4
L2
M1
A5
-
GND (Bank 1) GND (Bank 1)
1
-
3P
-
C6
-
A6
A19
-
K4
VCCO1
L3
V2
VCCO1
W2
GND
R4
-
1
-
3N
-
C7
-
A7
A17
-
-
GND
K5
1
1
1
1
1
-
4P
4N
5P
5N
6P
-
A14/INITB
A12/CSB
A10/READ
A8/CCLK
A6
C8
C9
C10
C11
-
A8
A15
A13
A11
A9
A7
-
A9
L5
T4
A10
N1
R6
A11
M2
R5
-
—
U3
VCC
-
-
VCC
P1
VCC
V3
1
1
1
1
1
-
6N
7P
7N
8P
8N
-
A4
-
-
A5
A3
A1
B31
B29
-
A2
-
-
M3
Y2
A0
-
-
L4
W3
U5
B30
D0
D2
-
-
N2
B28
-
P2
T5
GND (Bank 1)
B26
-
GND (Bank 1) GND (Bank 1)
1
-
9P
-
D4
-
-
B27
-
R1
VCCO1
R2
U4
VCCO1
V4
VCCO1
B24
-
1
1
1
1
-
9N
10P
10N
-
D6
D8
D10
D12
-
-
B25
B23
B21
B19
-
B22
-
T2
AA3
AB3
Y4
B20
-
T3
B18
-
—
-
DONE
B14
-
M4
AA4
AB2
U6
1
1
-
11P
11N
-
-
-
B15
B13
-
—
B12
-
-
—
GND (Bank 1)
B10
-
-
-
GND (Bank 1) GND (Bank 1)
1
-
12P
-
-
B11
-
—
VCCO1
—
V5
VCCO1
W6
VCCO1
B8
-
-
1
1
1
1
1
-
12N
13P
13N
14P
14N
-
-
-
B9
B7
B5
B3
B1
-
B6
C12
C13
C14
C15
-
A12
A13
A14
A15
-
N3
AB4
AB5
T6
B4
P4
B2
N5
B0
M6
U7
PROGRAMB
R3
W5
66
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
Macrocell 2
Ball Number Ball Number
1
-
-
C28
GND (Bank 1)
C26
D14
-
C29
-
P5 U8
GND (Bank 1) GND (Bank 1)
-
-
-
1
-
15P
-
D16
-
C27
-
T4
VCCO1
T5
V6
VCCO1
V7
VCCO1
C24
-
-
1
-
15N
-
D18
-
C25
-
GND
C22
-
-
GND
R4
GND
Y5
1
-
16P
-
D20
-
C23
-
VCC
C20
-
-
VCC
N6
VCC
AA5
Y6
1
1
1
1
1
1
1
1
1
-
16N
17P
17N
18P
18N
19P
19N
20P
20N
-
D22
-
C21
C19
C17
C15
C13
C11
C9
C7
C5
-
C18
-
-
R5
C16
-
-
-
P6
Y7
C14
-
-
—
AA6
AA7
W7
C12
-
—
C10
-
-
—
C8
-
-
M7
V8
C6
-
-
T6
W8
C4
-
-
R6
U9
GND (Bank 1)
CFG0
VCCO1
C0
-
-
GND (Bank 1) GND (Bank 1)
-
-
-
-
-
L8
VCCO1
T7
U10
VCCO1
AB7
AA8
AB8
AB9
W9
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
-
21P
21N
22P
22N
23P
23N
24P
24N
-
C16
C17
C18
C19
C20
C21
C22
C23
-
A16
A17
A18
A19
A20
A21
A22
A23
-
C1
D31
D29
D27
D25
D23
D21
D19
D17
D15
D13
-
D30
R7
D28
N7
D26
P7
D24
T8
D22
R8
Y9
D20
M8
P8
AB10
AA10
W10
Y10
D18
D16/VREF1
D14
L9
25P
25N
-
C24
C25
-
A24
A25
-
N8
D12
M9
Y11
GND (Bank 1)
D10
GND (Bank 1) GND (Bank 1)
1
-
26P
-
C26
-
A26
-
D11
-
N10
VCCO1
T9
V9
VCCO1
V10
VCCO1
D8
1
1
-
26N
27P
-
C27
C28
-
A27
A28
-
D9
D7
-
D6
T10
AA11
GND
AB11
VCC
U11
GND
D4
GND
R9
1
-
27N
-
C29
-
A29
-
D5
-
VCC
D2
VCC
P9
1
1
2
-
28P
28N
29P
-
C30
C31
F0
-
A30
A31
H0
-
D3
D1
E1
-
D0
N9
V11
E0
T11
AB12
VCC
VCC
VCC
67
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
F1
Macrocell 2
Ball Number Ball Number
2
-
29N
-
E2
GND
E4
H1
-
E3
-
T12
GND
P10
AA12
GND
Y12
-
2
2
2
-
30P
30N
31P
-
F2
H2
H3
H4
-
E5
E7
E9
-
E6
F3
R10
AA13
V12
E8
F4
R11
VCCO2
E10
-
VCCO2
M10
VCCO2
U12
2
-
31N
-
F5
H5
-
E11
-
GND (Bank 2)
E12
-
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
2
2
2
2
2
-
32P
32N
33P
33N
34P
34N
35P
35N
36P
36N
37P
-
F6
H6
H7
-
E13
E15
E17
E19
E21
E23
E25
E27
E29
E31
F1
M11
T13
AB13
Y13
E14
F7
E16
H0
H1
F8
P11
V13
E18/VREF2
E20
-
T14
W13
V14
H8
H9
H10
H11
H12
H13
H14
-
R12
R13
N11
T15
E22
F9
W14
Y14
E24
F10
F11
F12
F13
F14
-
E26
AB14
AB15
AA15
U13
E28
R14
N12
P12
E30
F0
VCCO2
F2
-
VCCO2
R15
VCCO2
U14
2
-
37N
-
F15
-
H15
-
F3
GND (Bank 2)
F4
-
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
2
2
2
-
38P
38N
39P
39N
40P
40N
41P
41N
42P
-
H2
H3
H4
H5
H6
H7
H8
H9
H10
-
E0
E2
E4
E6
E8
E10
E12
E16
E20
-
F5
—
—
W15
W16
Y16
F6
F7
F8
F9
—
F10
F11
F13
F15
F17
F19
F21
-
—
AA16
AB16
AA17
Y17
F12
—
F14
—
F16
—
F18
—
AA18
W17
VCC
W18
GND
V15
F20
—
VCC
F22
VCC
—
2
-
42N
-
H11
-
E22
-
F23
-
GND
F24
GND
—
2
-
43P
-
H12
-
-
F25
-
VCCO2
F26
-
VCCO2
—
VCCO2
U15
2
-
43N
-
H13
-
-
F27
-
GND (Bank 2)
F28
-
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
44P
44N
45P
45N
46P
H14
H15
H16
H17
H18
-
F29
F31
G1
G3
G5
P13
P15
M13
P14
—
Y18
V17
F30
-
G0
-
V16
G2
-
U16
AB18
G4
-
68
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
H19
H20
-
Macrocell 2
Ball Number Ball Number
2
2
-
46N
47P
-
G6
G8
-
G7
G9
-
—
—
AB19
AA19
VCCO2
U17
-
VCCO2
G10
-
VCCO2
—
2
-
47N
-
H21
-
-
G11
-
GND (Bank 2)
G12
-
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
2
-
48P
48N
49P
49N
50P
50N
51P
-
H22
H23
H24
H25
H26
H27
H28
-
-
G13
G15
G17
G19
G21
G23
G25
-
—
—
V18
AB21
U18
G14
-
G16
-
-
—
G18
—
T17
G20
-
R16
P16
N15
VCCO2
N14
AB20
AA20
Y19
G22
-
G24
-
VCCO2
G26
-
VCCO2
V19
2
-
51N
-
H29
-
-
G27
-
GND (Bank 2)
G28
-
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
-
52P
52N
53P
53N
54P
-
F16
F17
F18
F19
H30
-
H16
H17
H18
H19
E24
-
G29
G31
H1
H3
H5
-
N16
M16
M14
M15
—
T18
R17
G30
H0
U19
H2
T19
H4
V20
VCC
VCC
—
VCC
U20
2
2
2
2
2
-
54N
55P
55N
56P
56N
-
H6
H31
F20
F21
F22
F23
-
E26
H20
H21
H22
H23
-
H7
H9
H11
H13
H15
-
H8
L13
W20
Y21
H10
L12
H12
L15
R18
H14
L16
R19
GND
H16
GND
L14
GND
W21
VCCO2
Y22
2
-
57P
-
F24
-
H24
-
H17
-
VCCO2
H18
VCCO2
K15
2
-
57N
-
F25
-
H25
-
H19
-
GND (Bank 2)
H20
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
-
58P
58N
59P
59N
60P
60N
-
F26
F27
F28
F29
F30
F31
-
H26
H27
H28
H29
H30
H31
-
H21
H23
H25
H27
H29
H31
-
K14
K12
K13
J13
J14
J12
J15
J11
H11
H13
R20
P20
T21
R21
U21
V21
W22
V22
T22
R22
H22
H24
H26
H28
H30
TOE
-
-
RESET
GOE0
GOE1
-
-
-
-
-
-
-
-
-
-
-
-
-
See Power Supply and
NC Connections Table
-
-
GNDP
-
-
-
69
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
Macrocell 2
Ball Number Ball Number
-
-
GCLK3N
-
GCLK2
VCCP
-
-
-
-
H15 P16
See Power Supply and
NC Connections Table
-
-
-
GCLK3P
61N
61P
62N
62P
63N
63P
-
GCLK3
-
-
-
H16
H14
G16
—
N16
J22
3
3
3
3
3
3
-
J0
L31
L30
L29
L28
L27
L26
-
J31
J30
J29
J28
J27
J26
-
-
J2
J3
H22
N19
P15
P21
N15
J4
J5
J6
J8
J7
—
J9
—
J10
J11
-
—
GND (Bank 3)
J12
GND (Bank 3) GND (Bank 3)
3
-
64N
-
L25
-
J25
-
J13
-
—
VCCO3
—
M15
VCCO3
N20
VCCO3
J14
3
-
64P
-
L24
-
J24
-
J15
-
GND
J16
GND
—
GND
P22
3
3
3
3
3
-
65N
65P
66N
66P
67N
-
L23
L22
L21
L20
L19
-
J23
J22
J21
J20
J19
-
J17
J19
J21
J23
J25
-
J18
—
N21
J20
—
N17
J22
—
M20
P17
J24
—
VCC
J26
VCC
—
VCC
P18
3
3
3
-
67P
68N
68P
-
L18
L17
L16
-
J18
J17
J16
-
J27
J29
J31
-
J28
—
M21
M17
J30
—
GND (Bank 3)
L0
GND (Bank 3) GND (Bank 3)
3
-
69N
-
L15
-
J15
-
-
—
VCCO3
—
L20
VCCO3
N18
L21
VCCO3
L2
-
3
3
3
3
3
3
3
3
3
-
69P
70N
70P
71N
71P
72N
72P
73N
73P
-
L14
L13
L12
L11
L10
L9
J14
J13
J12
J11
J10
J9
L3
L5
L7
L9
L11
L13
L15
L17
L19
-
L4
—
L6
—
M18
L22
L8
—
L10
—
L17
L12
—
K22
L14
L8
J8
—
L18
L16
L7
J7
—
K21
L18
L6
J6
—
K18
GND (Bank 3)
L20
-
-
GND (Bank 3) GND (Bank 3)
3
-
74N
-
L5
J5
L21
-
—
VCCO3
—
K20
VCCO3
K17
VCCO3
L22
-
-
3
3
3
3
74P
75N
75P
76N
L4
J4
L23
L25
L27
L29
L24
L3
J3
—
K19
L26
L2
J2
—
J17
L28
L1
J1
G15
E22
70
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
L0
Macrocell 2
Ball Number Ball Number
3
3
3
-
76P
77N
77P
-
L30/PLL_FBK1
J0
L31
M1
M3
-
F15
H12
G14
E21
G22
F21
M0/PLL_RST1
P27
P26
-
N27
M2
GND (Bank 3)
M4
N26
-
GND (Bank 3) GND (Bank 3)
3
-
78N
-
P25
-
N25
M5
-
F16
VCCO3
E16
H21
VCCO3
G21
GND
D22
VCCO3
M6
-
3
-
78P
-
P24
-
N24
-
GND
M8
-
-
GND
G13
G12
F14
3
3
3
3
3
-
79N
79P
80N
80P
81N
-
P23
P22
P21
P20
N31
-
N23
M9
M11
M13
M15
M17
-
M10
N22
D21
M12
N21
J20
M14/CLK_OUT1
M16
N20
E15
J19
-
F12
E20
VCC
-
VCC
F13
VCC
F20
3
3
3
-
81P
82N
82P
-
M18
N30
N29
N28
-
M30
M19
M21
M23
-
M20
M28
D16
H17
M22
M26
D15
H18
GND (Bank 3)
M24
-
GND (Bank 3) GND (Bank 3)
3
-
83N
-
N27
-
-
M25
-
—
VCCO3
—
J18
VCCO3
H19
VCCO3
M26
-
3
3
3
-
83P
84N
84P
-
N26
N25
N24
-
-
M27
M29
M31
-
M28
-
—
G20
G19
GND
C22
M30
-
—
GND
N0
-
GND
—
3
-
85N
-
N23
-
-
N1
-
VCC
-
VCC
—
VCC
C21
3
3
3
3
3
-
85P
86N
86P
87N
87P
-
N2
N22
N21
N20
N19
N18
-
-
N3
-
N4
-
—
D20
N6
-
-
—
C19
N8
-
N9
N11
-
C16
B16
F19
N10
-
E19
GND (Bank 3)
N12
-
GND (Bank 3) GND (Bank 3)
3
-
88N
-
N17
-
-
N13
-
C15
VCCO3
B15
G18
VCCO3
F18
VCCO3
N14
-
3
3
3
3
3
3
3
3
3
88P
89N
89P
90N
90P
91N
91P
92N
92P
N16
N15
N14
N13
N12
P19
P18
P17
P16
-
N15
N17
N19
N21
N23
N25
N27
N29
N31
N16
-
-
E14
B20
N18
D14
B19
N20
-
E13
A20
N22
-
A15
A19
N24
N19
N18
N17
N16
D12
D18
N26
B14
C18
N28
C13
G17
F16
N30
A14
71
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
P31
P30
-
Macrocell 2
N31
N30
-
Ball Number Ball Number
3
3
-
93N
93P
-
O0
O2
O1
O3
-
A13
B13
E17
D17
GND (Bank 3)
O4
GND (Bank 3) GND (Bank 3)
3
-
94N
-
N11
-
M21
-
O5
-
D11
VCCO3
B12
GND
C12
VCC
E11
—
B18
VCCO3
A18
VCCO3
O6
3
-
94P
-
N10
-
M20
-
O7
-
GND
O8
GND
C17
VCC
B17
3
-
95N
-
N9
-
M18
-
O9
-
VCC
O10
3
3
3
3
3
3
3
3
3
-
95P
96N
96P
97N
97P
98N
98P
99N
99P
-
N8
N7
N6
N5
N4
N3
N2
N1
N0
-
M16
M12
M10
M8
M6
M5
M4
M2
M0
-
O11
O13
O15
O17
O19
O21
O23
O25
O27
-
O12
C16
B16
O14
—
O16
—
F13
O18
—
F15
O20
—
D16
E16
O22
E10
A12
A11
O24
A16
O26
A15
GND (Bank 3)
O28
GND (Bank 3) GND (Bank 3)
3
-
100N
-
P15
-
N15
-
O29
-
B11
VCCO3
C11
B10
A10
C10
D10
C9
B15
VCCO3
A14
VCCO3
O30
3
3
3
3
3
3
3
3
3
3
3
-
100P
101N
101P
102N
102P
103N
103P
104N
104P
105N
105P
-
P14
P13
P12
P11
P10
P9
P8
P29
P28
P7
P6
-
N14
N13
N12
N11
N10
N9
N8
N29
N28
N7
N6
-
O31
P1
P0
D15
E15
P2
P3
P4
P5
D14
F14
P6
P7
P8
P9
A13
P10
P11
P13
P15
P17
P19
-
E9
B13
P12/VREF3
P14
D9
C14
E14
F9
P16
A9
E13
P18
F8
F12
GND (Bank 3)
P20
GND (Bank 3) GND (Bank 3)
3
-
106N
-
P5
-
N5
-
P21
-
E8
VCCO3
A8
D13
VCCO3
C13
VCCO3
P22
3
3
-
106P
107N
-
P4
P3
-
N4
N3
-
P23
P25
-
P24
B9
E12
GND
P26
GND
D8
GND
C12
3
-
107P
-
P2
-
N2
-
P27
-
VCC
P28
VCC
B8
VCC
B12
3
3
0
108N
108P
109N
P1
P0
Q31
N1
N0
S31
P29
P31
Q31
P30
C8
A12
Q30
B7
E11
72
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
-
Macrocell 2
Ball Number Ball Number
-
-
VCC
Q28
-
-
VCC
A7
VCC
C11
0
-
109P
-
Q30
-
S30
Q29
-
GND
Q26
-
GND
D7
GND
B11
0
0
0
-
110N
110P
111N
-
Q29
Q28
Q27
-
S29
Q27
Q25
Q23
-
Q24
S28
C7
A11
Q22
S27
B6
F11
VCCO0
Q20
-
VCCO0
E7
VCCO0
F10
0
-
111P
-
Q26
-
S26
Q21
-
GND (Bank 0)
Q18
-
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
0
0
0
0
0
-
112N
112P
113N
113P
114N
114P
115N
115P
116N
116P
117N
-
Q25
Q24
Q3
S25
Q19
Q17
Q15
Q13
Q11
Q9
Q7
Q5
Q3
Q1
R31
-
E6
A6
E10
C10
D10
B10
A10
A9
Q16
S24
Q14/VREF0
Q12
S3
A5
Q2
S2
A4
Q10
Q23
Q22
Q21
Q20
Q19
Q18
Q1
S23
B5
Q8
S22
A3
Q6
S21
B4
C9
Q4
S20
B3
D9
Q2
S19
C5
F9
Q0
S18
C6
E9
R30
S1
-
D5
A8
VCCO0
R28
-
VCCO0
D6
VCCO0
B8
0
-
117P
-
Q0
S0
-
R29
-
GND (Bank 0)
R26
-
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
0
0
0
-
118N
118P
119N
119P
120N
120P
121N
121P
122N
-
S29
S28
S27
S26
S25
S24
S23
S22
S21
-
-
R27
R25
R23
R21
R19
R17
R15
R13
R11
-
—
—
A7
B7
R24
-
R22
-
—
A5
R20
-
—
B5
R18
-
—
B6
R16
-
—
C7
R14
-
—
E8
R12
-
—
E7
R10
-
—
E6
VCC
R8
-
VCC
—
VCC
D6
0
-
122P
-
S20
-
-
R9
-
GND
R6
-
GND
—
GND
D8
0
-
123N
-
S19
-
-
R7
-
VCCO0
R4
-
VCCO0
—
VCCO0
F8
0
-
123P
-
S18
-
-
R5
-
GND (Bank 0)
R2
-
GND (Bank 0) GND (Bank 0)
0
0
0
0
124N
124P
125N
125P
S17
S16
S15
S14
-
R3
R1
S31
S29
—
—
F7
D7
C6
C5
R0
-
S30
-
A2
B2
S28
-
73
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5768MX Logic Signal Connections (Continued)
Alternate Outputs
Primary Macrocell/
Function
Alternate
Inputs
256 fpBGA
484 fpBGA
sysIO Bank LVDS Pair
Macrocell 1
S13
Macrocell 2
Ball Number Ball Number
0
0
126N
126P
S26
S24
-
-
S27
S25
—
—
C4
D5
S12
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to
receive differential clocks; where GCLK0 and GCLK3 are the positive LVDS inputs.
74
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
AB18
AB16
AA17
AA16
AA15
-
Ball Number Ball Number
0
0
0
0
0
-
159N
159P
160N
160P
161N
-
AA22
AA20
AA11
AA10
Y17
Y16
Y15
-
AA23
AA21
AA19
AA17
AA15
-
B4
A4
C2
C1
AA18
B3
D4
AA16
A3
D3
AA14
F5
D2
VCCO0
AA12
VCCO0
G6
VCCO0
D1
0
-
161P
-
Y14
-
AA14
-
AA13
-
GND (Bank 0)
AA10
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
-
162N
162P
163N
163P
164N
-
Y13
Y12
AA9
AA8
AA7
-
AA13
AA12
AB14
AB12
AB10
-
AA11
AA9
AA7
AA5
AA3
-
H6
G5
E5
E4
AA8
AA6
D3
E3
AA4
D2
E2
AA2
E4
E1
VCC
VCC
E3
VCC
F2
0
-
164P
-
AA0
AA6
-
AB8
-
AA1
-
GND
GND
F4
GND
F5
0
0
0
-
165N
165P
166N
-
AB30
AA5
AA4
AA3
-
AB6
AB4
AB2
-
AB31
AB29
AB27
-
AB28
G4
G6
AB26
C2
F4
VCCO0
AB24
VCCO0
C1
VCCO0
F3
0
-
166P
-
AA2
-
AB0
-
AB25
-
GND (Bank 0)
AB22
GND (Bank 0) GND (Bank 0)
0
0
0
-
167N
167P
168N
-
AA1
AA0
AA31
-
-
AB23
AB21
AB19
F3
G3
F1
G1
AB20
-
AB18
-
H4
G5
VCC
-
VCC
J4
VCC
G4
0
0
0
0
0
-
168P
169N
169P
170N
170P
-
AB16
AA30
Y11
Y10
Y9
-
AB17
AB15
AB13
AB11
AB9
-
AB14
AA11
AA10
AA9
AA8
-
H5
H7
AB12/CLK_OUT0
AB10
J5
J7
E2
G3
AB8
Y8
F2
G2
GND
-
GND
D1
GND
H6
0
-
171N
-
AB6
Y7
AA7
-
AB7
-
VCCO0
AB4
-
VCCO0
E1
VCCO0
J6
0
-
171P
-
Y6
AA6
-
AB5
-
GND (Bank 0)
AB2
-
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
172N
172P
173N
173P
174N
174P
Y5
AA5
AA4
AE31
AE30
AE29
AE28
AB3
AB1
AC31
AC29
AC27
AC25
J3
H2
G2
G1
J6
H5
H4
H3
H2
H1
J1
AB0/PLL_RST0
AC30
Y4
AC31
AC30
AC29
AC28
AC28/PLL_FBK0
AC26
AC24
K4
75
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
AE27
-
Ball Number Ball Number
0
-
175N
-
AC22
VCCO0
AC20
AC27
-
AC23
-
K6
VCCO0
K3
J5
VCCO0
J4
0
-
175P
-
AC26
-
AE26
-
AC21
-
GND (Bank 0)
AC18
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
0
0
0
-
176N
176P
177N
177P
178N
178P
179N
179P
180N
-
AC25
AC24
AC23
AC22
AC21
AC20
AC19
AC18
AC17
-
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
-
AC19
AC17
AC15
AC13
AC11
AC9
AC7
AC5
AC3
-
K5
K2
K7
L7
AC16
AC14
L5
J3
AC12
K1
J2
AC10
L6
K6
AC8
L1
L6
AC6
M5
L2
K5
AC4
K4
AC2
N5
K3
VCCO0
AC0
VCCO0
L3
VCCO0
K2
0
-
180P
-
AC16
-
AE16
-
AC1
-
GND (Bank 0)
AE30
GND (Bank 0) GND (Bank 0)
0
0
0
-
181N
181P
182N
-
AC15
AC14
AC13
-
AE15
AE14
AE13
-
AE31
AE29
AE27
-
M6
M2
K1
L2
AE28
AE26
P5
L5
VCC
VCC
P6
VCC
L4
0
0
0
0
0
-
182P
183N
183P
184N
184P
-
AE24
AC12
AC11
AC10
AC9
AC8
-
AE12
AE11
AE10
AE9
AE8
-
AE25
AE23
AE21
AE19
AE17
-
AE22
M3
L3
AE20
N6
M3
AE18
N2
M7
AE16
P1
N7
GND
GND
N3
GND
M5
0
-
185N
-
AE14
AC7
-
AE7
-
AE15
-
VCCO0
AE12
VCCO0
M8
VCCO0
M4
0
-
185P
-
AC6
-
AE6
-
AE13
-
GND (Bank 0)
AE10
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
-
186N
186P
187N
187P
188N
188P
GCLK0P
AC5
AC4
AC3
AC2
AC1
AC0
-
AE5
AE4
AE3
AE2
AE1
AE0
-
AE11
AE9
AE7
AE5
AE3
AE1
-
N8
P2
P8
N4
H1
J1
M6
N6
M2
M1
N1
N2
N5
AE8
AE6
AE4
AE2
AE0
GCLK0
N7
See Power Supply and
NC Connections Table
-
-
VCCJ
-
-
-
-
-
-
-
GCLK0N
GCLK1
GND
TDI
-
-
-
-
-
-
-
-
-
-
-
-
P7
GND
R1
N3
GND
P4
-
-
-
TMS
R2
P5
76
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
-
Ball Number Ball Number
-
-
-
TCK
TDO
A30
-
-
T1
V1
—
—
—
—
—
—
P3
P2
P1
R1
P6
R6
P7
R7
-
-
-
-
1
1
1
1
1
1
-
0P
0N
1P
1N
2P
2N
-
A0
A1
A2
A3
A4
A5
-
C0
C1
C2
C3
C4
C5
-
A31
A29
A27
A25
A23
A21
-
A28
A26
A24
A22
A20
GND (Bank 1)
A18
GND (Bank 1) GND (Bank 1)
1
-
3P
-
A6
-
C6
-
A19
-
—
VCCO1
—
R4
VCCO1
R5
VCCO1
A16
1
-
3N
-
A7
-
C7
-
A17
-
GND
A14
GND
—
GND
R3
1
-
4P
-
A8
-
C8
-
A15
-
VCC
A12
VCC
—
VCC
R2
1
1
1
1
1
1
1
-
4N
5P
5N
6P
6N
7P
7N
-
A9
A10
A11
A12
A13
A14
A15
-
C9
C10
C11
C12
C13
C14
C15
-
A13
A11
A9
A7
A5
A3
A1
-
A10
—
T2
A8
—
T3
A6
—
T4
A4
—
T5
A2
—
U2
A0
—
U3
GND (Bank 1)
C30
GND (Bank 1) GND (Bank 1)
1
-
8P
-
A16
-
C16
-
C31
-
—
VCCO1
—
U4
VCCO1
U5
VCCO1
C28
1
1
1
1
1
1
1
1
1
-
8N
9P
9N
10P
10N
11P
11N
12P
12N
-
A17
A18
A19
A20
A21
A22
A23
A24
A25
-
C17
C18
C19
C20
C21
C22
C23
C24
C25
-
C29
C27
C25
C23
C21
C19
C17
C15
C13
-
C26
—
T6
C24
—
U6
C22
—
T7
C20
—
U7
C18
—
U1
C16
—
V1
C14
—
V2
C12
—
V3
GND (Bank 1)
C10
GND (Bank 1) GND (Bank 1)
1
-
13P
-
A26
-
C26
-
C11
-
—
VCCO1
—
V5
VCCO1
V4
VCCO1
C8
1
-
13N
-
A27
-
C27
-
C9
-
GND
C6
GND
—
GND
W2
1
-
14P
-
A28
-
C28
-
C7
-
VCC
C4
VCC
—
VCC
W3
1
1
14N
15P
A29
A30
C29
C30
C5
C3
C2
—
W4
77
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
Ball Number Ball Number
1
1
1
1
1
1
1
-
15N
16P
16N
17P
17N
18P
18N
-
C0
E30/DATA0
E28/DATA1
E26/DATA2
E24/DATA3
E22/DATA4
E20/DATA5
GND (Bank 1)
E18/DATA6
VCCO1
E16/DATA7
GND
A31
G0
G1
G2
G3
G4
G5
-
C31
E0
E1
E2
E3
E4
E5
-
C1
E31
E29
E27
E25
E23
E21
-
—
W1
Y1
P3
R3
T2
U2
W5
W1
Y1
V6
W6
Y2
Y3
GND (Bank 1) GND (Bank 1)
1
-
19P
-
G6
-
E6
-
E19
-
V2
VCCO1
W2
GND
R4
Y4
VCCO1
Y5
1
-
19N
-
G7
-
E7
-
E17
-
GND
V7
1
1
1
1
1
-
20P
20N
21P
21N
22P
-
E14/INITB
E12/CSB
E10/READ
E8/CCLK
E6
G8
G9
G10
G11
-
E8
E9
E10
E11
-
E15
E13
E11
E9
E7
-
T4
W7
R6
AA1
AA2
AA3
VCC
AA4
Y6
R5
U3
VCC
-
-
VCC
V3
1
1
1
1
1
-
22N
23P
23N
24P
24N
-
E4
-
-
E5
E3
E1
F31
F29
-
E2
-
-
Y2
E0
-
-
W3
U5
AA5
AB2
AB3
F30
H0
H2
-
-
F28
-
T5
GND (Bank 1)
F26
-
GND (Bank 1) GND (Bank 1)
1
-
25P
-
H4
-
F27
-
U4
VCCO1
V4
AB4
VCCO1
AB5
VCCO1
F24
-
-
-
-
-
-
-
-
-
1
1
1
1
-
25N
26P
26N
-
H6
H8
H10
H12
-
F25
F23
F21
F19
-
F22
AA3
AB3
Y4
AB1
F20
AC2
F18
AC3
-
DONE
F14
AA4
AB2
U6
AC4
1
1
-
27P
27N
-
-
F15
F13
-
AC1
F12
-
AD1
GND (Bank 1)
F10
-
GND (Bank 1) GND (Bank 1)
1
-
28P
-
F11
-
V5
VCCO1
W6
AD2
VCCO1
AD3
Y8
VCCO1
F8
-
-
1
1
1
1
1
-
28N
29P
29N
30P
30N
-
F9
F6
G12
G13
G14
G15
-
E12
E13
E14
E15
-
F7
AB4
AB5
T6
F4
F5
Y9
F2
F3
AA8
AA9
AB8
AB9
F0
F1
U7
PROGRAMB
G28
-
W5
1
-
H14
-
G29
U8
78
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
Ball Number Ball Number
-
-
GND (Bank 1)
G26
-
-
-
GND (Bank 1) GND (Bank 1)
1
-
31P
-
H16
-
G27
-
V6
VCCO1
V7
AB7
VCCO1
AC7
VCCO1
G24
-
-
1
-
31N
-
H18
-
G25
-
GND
G22
-
-
GND
Y5
GND
AB6
1
-
32P
-
H20
-
G23
-
VCC
G20
-
-
VCC
AA5
Y6
VCC
AC6
1
1
1
1
1
1
1
1
1
-
32N
33P
33N
34P
34N
35P
35N
36P
36N
-
H22
-
G21
G19
G17
G15
G13
G11
G9
G7
G5
-
G18
-
-
AC8
G16
-
-
-
Y7
AC9
G14
-
-
AA6
AA7
W7
AC5
G12
-
AD4
AD5
AD6
AD7
AD8
G10
-
-
G8
-
-
V8
G6
-
-
W8
G4
-
-
U9
GND (Bank 1)
CFG0
VCCO1
G0
-
-
GND (Bank 1) GND (Bank 1)
-
-
-
-
-
U10
VCCO1
AB7
AA8
AB8
AB9
W9
AE3
VCCO1
AD9
-
-
-
-
-
1
1
1
1
1
1
1
1
1
1
1
-
37P
37N
38P
38N
39P
39N
40P
40N
-
G16
G17
G18
G19
G20
G21
G22
G23
-
E16
E17
E18
E19
E20
E21
E22
E23
-
G1
H31
H29
H27
H25
H23
H21
H19
H17
H15
H13
-
H30
AD10
AE4
H28
H26
AE5
H24
AE6
H22
Y9
AE7
H20
AB10
AA10
W10
Y10
AE8
H18
AE9
H16/VREF1
H14
AE10
AF3
41P
41N
-
G24
G25
-
E24
E25
-
H12
Y11
AF4
GND (Bank 1)
H10
GND (Bank 1) GND (Bank 1)
1
-
42P
-
G26
-
E26
-
H11
-
V9
VCCO1
V10
AF5
VCCO1
AF6
VCCO1
H8
1
1
-
42N
43P
-
G27
G28
-
E27
E28
-
H9
H7
-
H6
AA11
GND
AB11
VCC
U11
AF7
GND
H4
GND
AF8
1
-
43N
-
G29
-
E29
-
H5
-
VCC
H2
VCC
AF9
1
1
2
-
44P
44N
45P
-
G30
G31
J0
-
E30
E31
L0
-
H3
H1
I1
H0
V11
AF10
AF17
VCC
AF18
I0
AB12
VCC
AA12
VCC
I2
-
2
45N
J1
L1
I3
79
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
Ball Number Ball Number
-
-
GND
-
J2
J3
J4
-
-
L2
L3
L4
-
-
GND
Y12
GND
AF19
2
2
2
-
46P
46N
47P
-
I4
I5
I6
I7
AA13
V12
AF20
I8
I9
AF21
VCCO2
-
VCCO2
U12
VCCO2
AF22
2
-
47N
-
I10
J5
-
L5
-
I11
-
GND (Bank 2)
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
2
2
2
2
2
-
48P
48N
49P
49N
50P
50N
51P
51N
52P
52N
53P
-
I12
J6
J7
L0
L1
J8
J9
J10
J11
J12
J13
J14
-
L6
L7
-
I13
I15
I17
I19
I21
I23
I25
I27
I29
I31
J1
-
AB13
Y13
AF23
AF24
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AD17
VCCO2
AD18
I14
I16
V13
I18/VREF2
-
W13
V14
I20
L8
L9
L10
L11
L12
L13
L14
-
I22
W14
Y14
I24
I26
AB14
AB15
AA15
U13
I28
I30
J0
VCCO2
VCCO2
U14
2
-
53N
-
J2
J15
-
L15
-
J3
-
GND (Bank 2)
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
2
2
2
-
54P
54N
55P
55N
56P
56N
57P
57N
58P
-
J4
J6
L2
L3
L4
L5
L6
L7
L8
L9
L10
-
I0
I2
I4
I6
I8
I10
I12
I16
I20
-
J5
J7
J9
J11
J13
J15
J17
J19
J21
-
W15
W16
Y16
AD19
AD20
AD21
AD22
AD23
AD24
AC22
AC21
AC18
VCC
J8
J10
AA16
AB16
AA17
Y17
J12
J14
J16
J18
AA18
W17
VCC
W18
GND
V15
J20
VCC
J22
2
-
58N
-
L11
-
I22
-
J23
-
AC19
GND
GND
J24
2
-
59P
-
L12
-
J25
-
AC20
VCCO2
AB21
VCCO2
J26
-
VCCO2
U15
2
-
59N
-
L13
-
-
J27
-
GND (Bank 2)
J28
-
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
60P
60N
61P
61N
62P
62N
L14
L15
L16
L17
L18
L19
-
J29
J31
K1
K3
K5
K7
Y18
V17
AB18
AB19
AB20
AA20
AA19
Y19
J30
-
K0
-
V16
K2
-
U16
K4
-
AB18
AB19
K6
-
80
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
Ball Number Ball Number
2
-
63P
-
K8
VCCO2
K10
L20
-
-
-
K9
-
AA19
VCCO2
U17
AA18
VCCO2
Y18
2
-
63N
-
L21
-
-
K11
-
GND (Bank 2)
K12
-
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
2
-
64P
64N
65P
65N
66P
66N
67P
-
L22
L23
L24
L25
L26
L27
L28
-
-
K13
K15
K17
K19
K21
K23
K25
-
V18
AB21
U18
AD25
AD26
AC23
AC24
AC25
AC26
AB22
VCCO2
AB23
K14
-
K16
-
K18
-
T17
K20
-
AB20
AA20
Y19
K22
-
K24
-
VCCO2
K26
-
VCCO2
V19
2
-
67N
-
L29
-
-
K27
-
GND (Bank 2)
K28
-
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
-
68P
68N
69P
69N
70P
-
J16
J17
J18
J19
L30
-
L16
L17
L18
L19
I24
-
K29
K31
L1
T18
R17
AB24
AB25
AB26
AA26
AA22
VCC
K30
L0
U19
L2
L3
T19
L4
L5
V20
VCC
L6
-
VCC
U20
2
2
2
2
2
-
70N
71P
71N
72P
72N
-
L31
J20
J21
J22
J23
-
I26
L20
L21
L22
L23
-
L7
Y21
L8
L9
W20
Y21
AA23
AA24
AA25
Y26
L10
L11
L13
L15
-
L12
R18
L14
R19
GND
L16
GND
W21
VCCO2
Y22
GND
Y22
2
-
73P
-
J24
-
L24
-
L17
-
VCCO2
L18
VCCO2
Y23
2
-
73N
-
J25
-
L25
-
L19
-
GND (Bank 2)
L20
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
2
2
2
-
74P
74N
75P
75N
76P
76N
77P
77N
78P
-
J26
J27
J28
J29
J30
J31
P0
P1
P2
-
L26
L27
L28
L29
L30
L31
N0
N1
N2
-
L21
L23
L25
L27
L29
L31
N1
N3
N5
-
R20
P20
T21
R21
U21
V21
—
W20
V20
L22
L24
W21
V21
L26
L28
Y24
L30
Y25
N0
W22
W23
W24
VCC
W25
GND
W26
N2
—
N4
—
VCC
N6
VCC
—
2
-
78N
-
P3
-
N3
-
N7
-
GND
N8
GND
—
2
79P
P4
N4
N9
81
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
Ball Number Ball Number
-
-
VCCO2
N10
-
-
-
VCCO2
—
VCCO2
V26
2
-
79N
-
P5
-
N5
-
N11
-
GND (Bank 2)
N12
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
2
2
2
-
80P
80N
81P
81N
82P
82N
83P
83N
84P
-
P6
P7
P8
P9
P10
P11
P12
P13
P14
-
N6
N7
N8
N9
N10
N11
N12
N13
N14
-
N13
N15
N17
N19
N21
N23
N25
N27
N29
-
—
—
V22
V23
N14
N16
—
V24
N18
—
V25
N20
—
U20
T20
N22
—
N24
—
U26
U25
U21
VCCO2
T21
N26
—
N28
—
VCCO2
N30
VCCO2
—
2
-
84N
-
P15
-
N15
-
N31
-
GND (Bank 2)
P0
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
2
-
85P
85N
86P
86N
87P
87N
88P
-
P16
P17
P18
P19
P20
P21
P22
-
N16
N17
N18
N19
N20
N21
N22
-
P1
P3
P5
P7
P9
P11
P13
-
—
—
U22
U23
P2
P4
—
U24
P6
—
T24
P8
—
T23
P10
—
T22
P12
—
T25
VCC
VCC
—
VCC
R26
2
-
88N
-
P14
P23
-
N23
-
P15
-
GND
P16
GND
—
GND
R25
2
-
89P
-
P24
-
N24
-
P17
-
VCCO2
P18
VCCO2
—
VCCO2
R24
2
-
89N
-
P25
-
N25
-
P19
-
GND (Bank 2)
P20
GND (Bank 2) GND (Bank 2)
2
2
2
2
2
2
-
90P
90N
91P
91N
92P
92N
-
P26
P27
P28
P29
P30
P31
-
N26
N27
N28
N29
N30
N31
-
P21
P23
P25
P27
P29
P31
-
—
—
R21
P21
R22
R23
R20
P20
P25
P24
P23
P22
P22
P24
—
P26
—
P28
—
P30
—
TOE
W22
V22
T22
R22
-
-
RESET
GOE0
GOE1
-
-
-
-
-
-
-
-
-
-
-
-
-
See Power Supply and
NC Connections Table
-
-
-
-
GNDP
GCLK2
VCCP
-
-
-
-
-
-
-
-
-
GCLK3N
-
P16
N26
See Power Supply and
NC Connections Table
82
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
-
Ball Number Ball Number
-
GCLK3P
93N
93P
94N
94P
95N
95P
-
GCLK3
-
-
N16
J22
N24
N23
N22
M26
M25
M23
M22
3
3
3
3
3
3
-
R0
T31
T30
T29
T28
T27
T26
-
R31
R30
R29
R28
R27
R26
-
R1
R3
R5
R7
R9
R11
-
R2
H22
N19
P15
P21
N15
R4
R6
R8
R10
GND (Bank 3)
GND (Bank 3) GND (Bank 3)
3
-
96N
-
R12
T25
-
R25
-
R13
-
M15
VCCO3
N20
N20
VCCO3
M20
GND
N21
VCCO3
3
-
96P
-
R14
T24
-
R24
-
R15
-
GND
GND
P22
3
3
3
3
3
-
97N
97P
98N
98P
99N
-
R16
T23
T22
T21
T20
T19
-
R23
R22
R21
R20
R19
-
R17
R19
R21
R23
R25
-
R18
N21
M21
M24
L24
R20
N17
R22
M20
P17
R24
L23
VCC
VCC
P18
VCC
L22
3
3
3
-
99P
100N
100P
-
R26
T18
T17
T16
-
R18
R17
R16
-
R27
R29
R31
-
R28
M21
M17
L25
R30
K26
GND (Bank 3)
GND (Bank 3) GND (Bank 3)
3
-
101N
-
T0
T15
-
R15
-
T1
L20
VCCO3
N18
L21
K25
VCCO3
K24
K23
K22
J25
VCCO3
-
3
3
3
3
3
3
3
3
3
-
101P
102N
102P
103N
103P
104N
104P
105N
105P
-
T2
T14
T13
T12
T11
T10
T9
R14
R13
R12
R11
R10
R9
T3
T4
T5
T6
T7
M18
L22
T8
T9
T10
T11
T13
T15
T17
T19
-
L17
J24
T12
K22
L21
T14
T16
T8
R8
L18
K21
L20
T7
R7
K21
T18
T6
R6
K18
K20
GND (Bank 3)
T20
-
-
GND (Bank 3) GND (Bank 3)
3
-
106N
-
T5
R5
T21
-
K20
VCCO3
K17
J23
VCCO3
J22
VCCO3
T22
-
-
3
3
3
3
3
3
3
106P
107N
107P
108N
108P
109N
109P
T4
R4
T23
T25
T27
T29
T31
U1
U3
T24
T3
R3
K19
J26
T26
T2
R2
J17
H26
T28
T1
R1
E22
H25
T30/PLL_FBK1
U0/PLL_RST1
U2
T0
R0
E21
H24
X27
X26
V27
V26
G22
F21
H23
H22
83
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
Ball Number Ball Number
-
-
GND (Bank 3)
-
-
-
GND (Bank 3) GND (Bank 3)
3
-
110N
-
U4
VCCO3
U6
X25
-
V25
U5
-
H21
VCCO3
G21
GND
D22
J21
VCCO3
H21
-
3
-
110P
-
X24
-
V24
U7
-
GND
U8
-
GND
G25
G24
G23
G22
J20
3
3
3
3
3
-
111N
111P
112N
112P
113N
-
X23
X22
X21
X20
V31
-
V23
U9
U11
U13
U15
U17
-
U10
V22
D21
U12
V21
J20
U14/CLK_OUT1
U16
V20
J19
-
E20
VCC
-
VCC
F20
VCC
H20
3
3
3
-
113P
114N
114P
-
U18
V30
V29
V28
-
U30
U19
U21
U23
-
U20
U28
H17
G26
F25
U22
U26
H18
GND (Bank 3)
U24
-
GND (Bank 3) GND (Bank 3)
3
-
115N
-
V27
-
-
U25
-
J18
VCCO3
H19
F24
VCCO3
F23
VCCO3
U26
-
3
3
3
-
115P
116N
116P
-
V26
V25
V24
-
-
U27
U29
U31
-
U28
-
G20
G19
GND
C22
G21
F22
U30
-
GND
V0
-
GND
F26
3
-
117N
-
V23
-
-
V1
-
VCC
-
VCC
C21
VCC
E26
3
3
3
3
3
-
117P
118N
118P
119N
119P
-
V2
V22
V21
V20
V19
V18
-
-
V3
V5
V7
V9
V11
-
V4
-
D20
E25
V6
-
C19
E24
V8
-
F19
E23
V10
-
E19
E22
GND (Bank 3)
V12
-
GND (Bank 3) GND (Bank 3)
3
-
120N
-
V17
-
-
V13
-
G18
VCCO3
F18
D26
VCCO3
D25
D24
D23
C26
C25
G19
F19
VCCO3
V14
-
3
3
3
3
3
3
3
3
3
3
3
-
120P
121N
121P
122N
122P
123N
123P
124N
124P
125N
125P
-
V16
V15
V14
V13
V12
X19
X18
X17
X16
X31
X30
-
-
-
V15
V17
V19
V21
V23
V25
V27
V29
V31
W1
W3
-
V16
B20
V18
-
B19
V20
-
A20
V22
-
A19
V24
V19
V18
V17
V16
V31
V30
-
D18
C18
G17
F16
V26
V28
G18
F18
V30
W0
E17
F20
W2
D17
E20
GND (Bank 3)
GND (Bank 3) GND (Bank 3)
84
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
U21
-
Ball Number Ball Number
3
-
126N
-
W4
VCCO3
W6
V11
-
W5
-
B18
VCCO3
A18
E19
VCCO3
E18
3
-
126P
-
V10
-
U20
-
W7
-
GND
W8
GND
C17
VCC
B17
GND
C24
3
-
127N
-
V9
-
U18
-
W9
-
VCC
W10
VCC
C23
3
3
3
3
3
3
3
3
3
-
127P
128N
128P
129N
129P
130N
130P
131N
131P
-
V8
V7
V6
V5
V4
V3
V2
V1
V0
-
U16
U12
U10
U8
U6
U5
U4
U2
U0
-
W11
W13
W15
W17
W19
W21
W23
W25
W27
-
W12
C16
B16
D22
W14
D21
W16
F13
E21
W18
F15
D20
W20
D16
E16
D19
W22
D18
W24
A16
C22
W26
A15
C21
GND (Bank 3)
W28
GND (Bank 3) GND (Bank 3)
3
-
132N
-
X15
-
V15
-
W29
-
B15
VCCO3
A14
C20
VCCO3
C19
C18
C17
B24
VCCO3
W30
3
3
3
3
3
3
3
3
3
3
3
-
132P
133N
133P
134N
134P
135N
135P
136N
136P
137N
137P
-
X14
X13
X12
X11
X10
X9
X8
X29
X28
X7
X6
-
V14
V13
V12
V11
V10
V9
V8
V29
V28
V7
V6
-
W31
X1
X0
D15
E15
X2
X3
X4
X5
D14
F14
X6
X7
B23
X8
X9
A13
B22
X10
X11
X13
X15
X17
X19
-
B13
B21
X12/VREF3
X14
C14
E14
B20
B19
X16
E13
B18
X18
F12
B17
GND (Bank 3)
X20
GND (Bank 3) GND (Bank 3)
3
-
138N
-
X5
-
V5
-
X21
-
D13
VCCO3
C13
A24
VCCO3
A23
VCCO3
X22
3
3
-
138P
139N
-
X4
X3
-
V4
V3
-
X23
X25
-
X24
E12
A22
GND
X26
GND
C12
GND
A21
3
-
139P
-
X2
-
V2
-
X27
-
VCC
X28
VCC
B12
VCC
A20
3
3
0
-
140N
140P
141N
-
X1
X0
Y31
-
V1
V0
AA31
-
X29
X31
Y31
-
X30
A12
A19
Y30
E11
A18
VCC
Y28
VCC
C11
VCC
A17
0
-
141P
-
Y30
-
AA30
-
Y29
-
GND
GND
GND
85
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 51024MX Logic Signal Connections (Continued)
Alternate Outputs
sysIO
Bank
Primary
Alternate
Input
484 fpBGA
672 fpBGA
LVDS Pair Macrocell/Function Macrocell 1
Macrocell 2
Ball Number Ball Number
0
0
0
-
142N
142P
143N
-
Y26
Y24
Y29
Y28
Y27
-
AA29
Y27
Y25
Y23
-
B11
A11
A10
A9
AA28
Y22
AA27
F11
A8
VCCO0
Y20
-
VCCO0
F10
VCCO0
A7
0
-
143P
-
Y26
-
AA26
Y21
-
GND (Bank 0)
Y18
-
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
0
0
0
0
0
-
144N
144P
145N
145P
146N
146P
147N
147P
148N
148P
149N
-
Y25
Y24
Y3
AA25
Y19
Y17
Y15
Y13
Y11
Y9
E10
C10
D10
B10
A10
A9
A6
A5
Y16
AA24
Y14/VREF0
Y12
AA3
A4
Y2
AA2
A3
Y10
Y23
Y22
Y21
Y20
Y19
Y18
Y1
AA23
B10
B9
Y8
AA22
Y6
AA21
Y7
C9
B8
Y4
AA20
Y5
D9
B7
Y2
AA19
Y3
F9
B6
Y0
AA18
Y1
E9
B5
Z30
AA1
Z31
-
A8
B4
VCCO0
Z28
-
-
VCCO0
B8
VCCO0
B3
0
-
149P
-
Y0
AA0
Z29
-
GND (Bank 0)
Z26
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
0
0
0
-
150N
150P
151N
151P
152N
152P
153N
153P
154N
-
AA29
AA28
AA27
AA26
AA25
AA24
AA23
AA22
AA21
-
Z27
Z25
Z23
Z21
Z19
Z17
Z15
Z13
Z11
-
A7
B7
C10
C9
Z24
Z22
A5
C8
Z20
B5
C7
Z18
B6
C6
Z16
C7
C5
Z14
E8
C4
Z12
E7
D5
Z10
E6
D9
VCC
Z8
VCC
D6
VCC
D8
0
-
154P
-
AA20
-
Z9
GND
Z6
-
GND
D8
GND
D7
0
-
155N
-
AA19
-
Z7
VCCO0
Z4
-
VCCO0
F8
VCCO0
D6
0
-
155P
-
AA18
-
Z5
GND (Bank 0)
Z2
-
GND (Bank 0) GND (Bank 0)
0
0
0
0
0
0
156N
156P
157N
157P
158N
158P
AA17
AA16
AA15
AA14
AA13
AA12
Z3
F7
D7
C6
C5
C4
D5
F9
E9
F7
F8
G8
G9
Z0
Z1
AA30
AA28
AA26
AA24
AA31
AA29
AA27
AA25
Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to receive differen-
tial clocks; where GCLK0 and GCLK3 are the positive LVDS inputs.
86
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
Part Number Description
LC XXXXX X X – XX XX XXX X
Grade
C = Commercial
I = Industrial
Device Family
LC
Device Number
5256 = 256 Macrocells
5512 = 512 Macrocells
5768 = 768 Macrocells
51024 = 1,024 Macrocells
Pin/Ball Count
208
256
484
672
Memory
M
Package
F = fpBGA
FN = Lead-Free fpBGA
Q = PQFP
Supply Voltage
V = 3.3V
B = 2.5V
C = 1.8V
Speed
4 = 4.0ns
45 = 4.5ns
5 = 5.0ns
52 = 5.2ns
75 = 7.5ns
Ordering Information
Note: For voltage families offered in industrial temperature grades and for all but the slowest commercial speed
grade, the speed grades on these devices are dual marked. For example, the commercial speed grade -45XXXXC
is also marked with the industrial grade -75I. The commercial grade is always one speed grade faster than the
associated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only.
Conventional Packaging
ispXPLD 5000MC (1.8V) Commercial Devices
Pin/Ball
Device
Part Number
Macrocells Voltage (V)
t
(ns)
Package
fpBGA
fpBGA
fpBGA
PQFP
PQFP
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Count
256
256
256
208
208
256
256
484
484
256
256
484
484
I/O
Grade
C
PD
LC5256MC-4F256C
256
256
256
512
512
512
512
512
512
768
768
768
768
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
4.0
141
141
141
149
149
193
193
253
253
193
193
317
317
LC5256MC LC5256MC-5F256C
LC5256MC-75F256C
5.0
7.5
4.5
7.5
4.5
7.5
4.5
7.5
5.0
7.5
5.0
7.5
C
C
LC5512MC-45Q208C
C
LC5512MC-75Q208C
C
LC5512MC-45F256C
LC5512MC
C
LC5512MC-75F256C
C
LC5512MC-45F484C
LC5512MC-75F484C
LC5768MC-5F256C
C
C
C
LC5768MC-75F256C
LC5768MC
C
LC5768MC-5F484C
C
LC5768MC-75F484C
C
87
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MC (1.8V) Commercial Devices (Continued)
Pin/Ball
Count
Device
Part Number
Macrocells Voltage (V)
t
(ns)
Package
fpBGA
fpBGA
fpBGA
fpBGA
I/O
317
317
381
381
Grade
PD
LC51024MC-52F484C
LC51024MC-75F484C
LC51024MC-52F672C
LC51024MC-75F672C
1024
1024
1024
1024
1.8
1.8
1.8
1.8
5.2
484
484
672
672
C
C
C
C
7.5
5.2
7.5
LC51024MC
ispXPLD 5000MC (1.8V) Industrial Devices
Pin/Ball
Count
Device
Part Number
LC5256MC-5F256I
LC5256MC-75F256I
LC5512MC-75Q208I
Macrocells Voltage (V)
t
(ns)
Package
fpBGA
fpBGA
PQFP
I/O
141
141
149
193
253
193
317
317
381
Grade
PD
256
256
512
512
512
768
768
1024
1024
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
5.0
256
256
208
256
484
256
484
484
672
I
I
I
I
I
I
I
I
I
LC5256MC
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
LC5512MC LC5512MC-75F256I
LC5512MC-75F484I
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
LC5768MC-75F256I
LC5768MC
LC5768MC-75F484I
LC51024MC-75F484I
LC51024MC
LC51024MC-75F672I
ispXPLD 5000MB (2.5V) Commercial Devices
Pin/Ball
Count
Device
Part Number
Macrocells Voltage (V)
t
(ns)
Package
fpBGA
fpBGA
fpBGA
PQFP
PQFP
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
I/O
Grade
C
PD
LC5256MB-4F256C
256
256
256
512
512
512
512
512
512
768
768
768
768
1024
1024
1024
1024
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
4.0
256
256
256
208
208
256
256
484
484
256
256
484
484
484
484
672
672
141
141
141
149
149
193
193
253
253
193
193
317
317
317
317
381
381
LC5256MB LC5256MB-5F256C
LC5256MB-75F256C
5.0
7.5
4.5
7.5
4.5
7.5
4.5
7.5
5.0
7.5
5.0
7.5
5.2
7.5
5.2
7.5
C
C
LC5512MB-45Q208C
C
LC5512MB-75Q208C
C
LC5512MB-45F256C
LC5512MB
C
LC5512MB-75F256C
C
LC5512MB-45F484C
LC5512MB-75F484C
LC5768MB-5F256C
C
C
C
LC5768MB-75F256C
LC5768MB
C
LC5768MB-5F484C
C
LC5768MB-75F484C
LC51024MB-52F484C
C
C
LC51024MB-75F484C
LC51024MB
C
LC51024MB-52F672C
C
LC51024MB-75F672C
C
ispXPLD 5000MB (2.5V) Industrial Devices
Pin/Ball
Count
Device
Part Number
LC5256MB-5F256I
LC5256MB-75F256I
Macrocells Voltage (V)
t
(ns)
Package
fpBGA
I/O
141
141
Grade
PD
256
256
2.5
2.5
5.0
7.5
256
256
I
I
LC5256MB
fpBGA
88
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MB (2.5V) Industrial Devices (Continued)
Pin/Ball
Count
Device
Part Number
Macrocells Voltage (V)
t
(ns)
Package
PQFP
I/O
149
193
253
193
317
317
381
Grade
PD
LC5512MB-75Q208I
512
512
2.5
2.5
2.5
2.5
2.5
2.5
2.5
7.5
208
256
484
256
484
484
672
I
I
I
I
I
I
I
LC5512MB LC5512MB-75F256I
LC5512MB-75F484I
7.5
7.5
7.5
7.5
7.5
7.5
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
512
LC5768MB-75F256I
LC5768MB
768
LC5768MB-75F484I
768
LC51024MB-75F484I
LC51024MB
1024
1024
LC51024MB-75F672I
ispXPLD 5000MV (3.3V) Commercial Devices
Pin/Ball
Count
Device
Part Number
Macrocells Voltage (V)
t
(ns)
Package
fpBGA
fpBGA
fpBGA
PQFP
PQFP
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
I/O
Grade
C
PD
LC5256MV-4F256C
256
256
256
512
512
512
512
512
512
768
768
768
768
1024
1024
1024
1024
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
4.0
256
256
256
208
208
256
256
484
484
256
256
484
484
484
484
672
672
141
141
141
149
149
193
193
253
253
193
193
317
317
317
317
381
381
LC5256MV LC5256MV-5F256C
LC5256MV-75F256C
5.0
7.5
4.5
7.5
4.5
7.5
4.5
7.5
5.0
7.5
5.0
7.5
5.2
7.5
5.2
7.5
C
C
LC5512MV-45Q208C
C
LC5512MV-75Q208C
C
LC5512MV-45F256C
LC5512MV
C
LC5512MV-75F256C
C
LC5512MV-45F484C
LC5512MV-75F484C
LC5768MV-5F256C
C
C
C
LC5768MV-75F256C
LC5768MV
C
LC5768MV-5F484C
C
LC5768MV-75F484C
LC51024MV-52F484C
C
C
LC51024MV-75F484C
LC51024MV
C
LC51024MV-52F672C
C
LC51024MV-75F672C
C
ispXPLD 5000MV (3.3V) Industrial Devices
Pin/Ball
Count
Device
Part Number
LC5256MV-5F256I
LC5256MV-75F256I
LC5512MV-75Q208I
Macrocells Voltage (V)
t
(ns)
Package
fpBGA
fpBGA
PQFP
I/O
141
141
149
193
253
193
317
317
381
Grade
PD
256
256
512
512
512
768
768
1024
1024
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5.0
256
256
208
256
484
256
484
484
672
I
I
I
I
I
I
I
I
I
LC5256MV
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
LC5512MV LC5512MV-75F256I
LC5512MV-75F484I
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
LC5768MV-75F256I
LC5768MV
LC5768MV-75F484I
LC51024MV-75F484I
LC51024MV
LC51024MV-75F672I
89
Lattice Semiconductor
Lead-Free Packaging
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MC (1.8V) Lead-Free Commercial Devices
Pin/Ball
Count
Device
Part Number
Macrocells Voltage (V)
t
(ns)
Package
I/O
Grade
C
PD
LC5256MC-4FN256C
256
256
256
512
512
512
512
512
512
768
768
768
768
1024
1024
1024
1024
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
4.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free PQFP
Lead-free PQFP
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
256
256
256
208
208
256
256
484
484
256
256
484
484
484
484
672
672
141
141
141
149
149
193
193
253
253
193
193
317
317
317
317
381
381
LC5256MC LC5256MC-5FN256C
LC5256MC-75FN256C
5.0
7.5
4.5
7.5
4.5
7.5
4.5
7.5
5.0
7.5
5.0
7.5
5.2
7.5
5.2
7.5
C
C
LC5512MC-45QN208C
C
LC5512MC-75QN208C
C
LC5512MC-45FN256C
LC5512MC
C
LC5512MC-75FN256C
C
LC5512MC-45FN484C
LC5512MC-75FN484C
LC5768MC-5FN256C
C
C
C
LC5768MC-75FN256C
LC5768MC
C
LC5768MC-5FN484C
C
LC5768MC-75FN484C
LC51024MC-52FN484C
C
C
LC51024MC-75FN484C
LC51024MC
C
LC51024MC-52FN672C
C
LC51024MC-75FN672C
C
ispXPLD 5000MC (1.8V) Lead-Free Industrial Devices
Pin/Ball
Count
Device
Part Number
LC5256MC-5FN256I
LC5256MC-75FN256I
LC5512MC-75QN208I
Macrocells Voltage (V)
t
(ns)
Package
I/O
Grade
PD
256
256
512
512
512
768
768
1024
1024
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
5.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free PQFP
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
256
256
208
256
484
256
484
484
672
141
141
149
193
253
193
317
317
381
I
I
I
I
I
I
I
I
I
LC5256MC
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
LC5512MC LC5512MC-75FN256I
LC5512MC-75FN484I
LC5768MC-75FN256I
LC5768MC
LC5768MC-75FN484I
LC51024MC-75FN484I
LC51024MC
LC51024MC-75FN672I
90
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MB (2.5V) Lead-Free Commercial Devices
Pin/Ball
Count
Device
Part Number
Macrocells Voltage (V)
t
(ns)
Package
I/O
Grade
C
PD
LC5256MB-4FN256C
256
256
256
512
512
512
512
512
512
768
768
768
768
1024
1024
1024
1024
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
4.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free PQFP
Lead-free PQFP
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
256
256
256
208
208
256
256
484
484
256
256
484
484
484
484
672
672
141
141
141
149
149
193
193
253
253
193
193
317
317
317
317
381
381
LC5256MB LC5256MB-5FN256C
LC5256MB-75FN256C
5.0
7.5
4.5
7.5
4.5
7.5
4.5
7.5
5.0
7.5
5.0
7.5
5.2
7.5
5.2
7.5
C
C
LC5512MB-45QN208C
C
LC5512MB-75QN208C
C
LC5512MB-45FN256C
LC5512MB
C
LC5512MB-75FN256C
C
LC5512MB-45FN484C
LC5512MB-75FN484C
LC5768MB-5FN256C
C
C
C
LC5768MB-75FN256C
LC5768MB
C
LC5768MB-5FN484C
C
LC5768MB-75FN484C
LC51024MB-52FN484C
C
C
LC51024MB-75FN484C
LC51024MB
C
LC51024MB-52FN672C
C
LC51024MB-75FN672C
C
ispXPLD 5000MB (2.5V) Lead-Free Industrial Devices
Pin/Ball
Count
Device
Part Number
LC5256MB-5FN256I
LC5256MB-75FN256I
LC5512MB-75QN208I
Macrocells Voltage (V)
t
(ns)
Package
I/O
Grade
PD
256
256
512
512
512
768
768
1024
1024
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
5.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free PQFP
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
256
256
208
256
484
256
484
484
672
141
141
149
193
253
193
317
317
381
I
I
I
I
I
I
I
I
I
LC5256MB
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
LC5512MB LC5512MB-75FN256I
LC5512MB-75FN484I
LC5768MB-75FN256I
LC5768MB
LC5768MB-75FN484I
LC51024MB-75FN484I
LC51024MB
LC51024MB-75FN672I
ispXPLD 5000MV (3.3V) Lead-Free Commercial Devices
Pin/Ball
Count
Device
Part Number
Macrocells Voltage (V)
t
(ns)
Package
I/O
Grade
PD
LC5256MV-4FN256C
256
256
256
512
512
512
512
512
512
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
4.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free PQFP
Lead-free PQFP
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
256
256
256
208
208
256
256
484
484
141
141
141
149
149
193
193
253
253
C
C
C
C
C
C
C
C
C
LC5256MV LC5256MV-5FN256C
LC5256MV-75FN256C
5.0
7.5
4.5
7.5
4.5
7.5
4.5
7.5
LC5512MV-45QN208C
LC5512MV-75QN208C
LC5512MV-45FN256C
LC5512MV
LC5512MV-75FN256C
LC5512MV-45FN484C
LC5512MV-75FN484C
91
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MV (3.3V) Lead-Free Commercial Devices (Continued)
Pin/Ball
Count
Device
Part Number
Macrocells Voltage (V)
t
(ns)
Package
I/O
Grade
PD
LC5768MV-5FN256C
LC5768MV-75FN256C
LC5768MV-5FN484C
LC5768MV-75FN484C
LC51024MV-52FN484C
LC51024MV-75FN484C
LC51024MV-52FN672C
LC51024MV-75FN672C
768
768
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
256
256
484
484
484
484
672
672
193
193
317
317
317
317
381
381
C
C
C
C
C
C
C
C
7.5
5.0
7.5
5.2
7.5
5.2
7.5
LC5768MV
768
768
1024
1024
1024
1024
LC51024MV
ispXPLD 5000MV (3.3V) Lead-Free Industrial Devices
Pin/Ball
Count
Device
Part Number
LC5256MV-5FN256I
LC5256MV-75FN256I
LC5512MV-75QN208I
Macrocells Voltage (V)
t
(ns)
Package
I/O
Grade
PD
256
256
512
512
512
768
768
1024
1024
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free PQFP
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
256
256
208
256
484
256
484
484
672
141
141
149
193
253
193
317
317
381
I
I
I
I
I
I
I
I
I
LC5256MV
7.5
7.5
7.5
7.5
7.5
7.5
7.5
7.5
LC5512MV LC5512MV-75FN256I
LC5512MV-75FN484I
LC5768MV-75FN256I
LC5768MV
LC5768MV-75FN484I
LC51024MV-75FN484I
LC51024MV
LC51024MV-75FN672I
For Further Information
In addition to this data sheet, the following technical notes may be helpful when designing with the ispXPLD
5000MX family:
• sysIO Usage Guidelines for Lattice Devices (TN1000)
• Lattice sysCLOCK PLL Design and Usage Guidelines (TN1003)
• Power Estimation in ispXPLD 5000MX Devices (TN1031)
• Using Memory in ispXPLD 5000MX Devices (TN1030)
• ispXP Configuration Usage Guidelines (TN1026)
92
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