LFECP20E-3F484NI [LATTICE]
Field Programmable Gate Array, 2464 CLBs, 420MHz, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, FPBGA-484;型号: | LFECP20E-3F484NI |
厂家: | LATTICE SEMICONDUCTOR |
描述: | Field Programmable Gate Array, 2464 CLBs, 420MHz, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, FPBGA-484 时钟 栅 可编程逻辑 |
文件: | 总163页 (文件大小:10411K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LatticeECP/EC Family Data Sheet
DS1000 Version 02.8, September 2012
LatticeECP/EC Family Data Sheet
Introduction
September 2012
Data Sheet
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
SSTL 3/2 Class I, II, SSTL18 Class I
HSTL 18 Class I, II, III, HSTL15 Class I, III
PCI
Features
Extensive Density and Package Options
• 1.5K to 32.8K LUT4s
• 65 to 496 I/Os
• Density migration supported
LVDS, Bus-LVDS, LVPECL, RSDS
Dedicated DDR Memory Support
• Implements interface up to DDR400 (200MHz)
sysDSP™ Block (LatticeECP™ Versions)
• High performance multiply and accumulate
• 4 to 8 blocks
sysCLOCK™ PLLs
4 to 8 36x36 multipliers or
– 16 to 32 18x18 multipliers or
32 to 64 9x9 multipliers
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting
System Level Support
Embedded and Distributed Memory
• 18 Kbits to 498 Kbits sysMEM™ Embedded
Block RAM (EBR)
• IEEE Standard 1149.1 Boundary Scan, plus
ispTRACY™ internal logic analyzer capability
• SPI boot flash interface
• Up to 131 Kbits distributed RAM
• Flexible memory resources:
• 1.2V power supply
Low Cost FPGA
Distributed and block memory
• Features optimized for mainstream applications
• Low cost TQFP and PQFP packaging
Flexible I/O Buffer
• Programmable sysI/O™ buffer supports wide
range of interfaces:
Table 1-1. LatticeECP/EC Family Selection Guide
LFEC6/
LFECP6
LFEC10/
LFECP10
LFEC15/
LFECP15
LFEC20/
LFECP20
LFEC33/
LFECP33
Device
PFU/PFF Rows
LFEC1
12
16
192
1.5
6
LFEC3
16
24
32
768
6.1
25
92
10
4
32
40
40
48
44
56
64
64
PFU/PFF Columns
PFUs/PFFs
24
384
3.1
12
1280
10.2
41
1920
15.4
61
2464
19.7
79
4096
32.8
131
498
54
LUTs (K)
Distributed RAM (Kbits)
EBR SRAM (Kbits)
EBR SRAM Blocks
sysDSP Blocks1
18x18 Multipliers1
18
2
55
276
30
350
38
424
46
6
—
—
5
6
7
8
—
—
16
1.2
2
20
24
28
32
VCC Voltage (V)
1.2
2
1.2
2
1.2
4
1.2
4
1.2
4
1.2
4
Number of PLLs
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
1. LatticeECP devices only.
67
97
67
97
97
112
145
160
147
195
224
147
195
288
195
352
360
400
360
496
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
Introduction_01.4
Introduction
LatticeECP/EC Family Data Sheet
Introduction
The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For
maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines an efficient FPGA
fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-
DSP™ (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™
(EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function
blocks to achieve lower cost solutions.
The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical
FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.
Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prev-
alent in cost-sensitive applications.
The ispLEVER® design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP/EC FPGA family. Synthesis library support for LatticeECP/EC is available for popular logic synthesis
tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to
place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
1-2
LatticeECP/EC Family Data Sheet
Architecture
September 2012
Data Sheet
Architecture Overview
The LatticeECP-DSP and LatticeEC architectures contain an array of logic blocks surrounded by Programmable I/
O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR), as
shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks, as shown in
Figure 2-2.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O interfaces. PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeECP/EC architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™
port which allows for serial or parallel device configuration. The LatticeECP/EC devices use 1.2V as their core volt-
age.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
Architecture_02.0
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-1. Simplified Block Diagram, LatticeEC Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (PFU without
RAM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (Fast PFU
without RAM/ROM)
sysDSP Block
sysCLOCK PLL
Programmable
Functional Unit (PFU)
2-2
Architecture
LatticeECP/EC Family Data Sheet
PFU and PFF Blocks
The core of the LatticeECP/EC devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-3. PFU Diagram
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
Slice 3
Slice 0
Slice 1
Slice 2
D
D
D
D
FF/
D
D
FF/
D
D
FF/
FF/
FF/
FF/
FF/
FF/
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
To
Routing
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
2-3
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-4. Slice Diagram
To / From
Different slice / PFU
Slice
OFX1
F1
A1
B1
C1
D1
CO
F
Q1
LUT4 &
D
SUM
FF/
Latch
CARRY
CI
To
Routing
From
Routing
M1
M0
OFX0
LUT
Expansion
Mux
CO
A0
B0
F0
C0
LUT4 &
CARRY
F
D0
OFX0
Q0
SUM
D
FF/
CI
Latch
Control Signals
selected and
inverted per
CE
CLK
LSR
slice in routing
Interslice signals
are not shown
To / From
Different slice / PFU
Table 2-1. Slice Signal Descriptions
Function
Input
Type
Signal Names
Description
Data signal
A0, B0, C0, D0 Inputs to LUT4
A1, B1, C1, D1 Inputs to LUT4
Input
Data signal
Input
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Inter-PFU signal
Data signals
Data signals
Data signals
Data signals
Inter-PFU signal
M0
M1
Multipurpose Input
Input
Multipurpose Input
Clock Enable
Input
CE
Input
LSR
Local Set/Reset
System Clock
Fast Carry In1
Input
CLK
Input
FCIN
F0, F1
Q0, Q1
OFX0
OFX1
FCO
Output
Output
Output
Output
Output
LUT4 output register bypass signals
Register Outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
For the right most PFU the fast carry chain output1
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
2-4
Architecture
LatticeECP/EC Family Data Sheet
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
Table 2-2. Slice Modes
Logic
Ripple
RAM
SPR16x2
N/A
ROM
PFU Slice
PFF Slice
LUT 4x2 or LUT 5x1
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
2-bit Arithmetic Unit
ROM16x1 x 2
ROM16x1 x 2
Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4
can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this
lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup
tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices.
Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol-
lowing functions can be implemented by each Slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Ripple mode multiplier building block
• Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this
configuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are
generated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory.
Through the combination of LUTs and Slices, a variety of different memories can be constructed.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of Slices required to implement different distributed RAM primitives. Figure 2-5 shows the dis-
tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions
as the read-write port. The other companion Slice supports the read-only port. For more information about using
RAM in LatticeECP/EC devices, please see the list of technical documentation at the end of this data sheet.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
SPR16x2
DPR16x2
Number of slices
1
2
Note: SPR = Single Port RAM, DPR = Dual Port RAM
2-5
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-5. Distributed Memory Primitives
SPR16x2
DPR16x2
RAD0
RAD1
RAD2
RAD3
AD0
AD1
AD2
AD3
WAD0
WAD1
WAD2
WAD3
DO0
DO1
DI0
DI1
WRE
RDO0
RDO1
WDO0
WDO1
DI0
DI1
WCK
WRE
CK
ROM16x1
AD0
AD1
AD2
AD3
DO0
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Logic
Ripple
RAM1
ROM
LUT 4x8 or
MUX 2x1 x 8
2-bit Add x 4
SPR16x2 x 4
DPR16x2 x 2
ROM16x1 x 8
LUT 5x4 or
MUX 4x1 x 4
2-bit Sub x 4
2-bit Counter x 4
2-bit Comp x 4
SPR16x4 x 2
DPR16x4 x 1
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1
LUT 6x 2 or
MUX 8x1 x 2
SPR16x8 x 1
LUT 7x1 or
MUX 16x1 x 1
1. These modes are not available in PFF blocks
2-6
Architecture
LatticeECP/EC Family Data Sheet
Routing
There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and
x6 resources are buffered, the routing of both short and long connections between PFUs.
The ispLEVER design tool suite takes the output of the synthesis tool and places and routes the design. Generally,
the place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.
LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There
are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.
Figure 2-6. Primary Clock Sources
From Routing
Clock Input
From Routing
PLL Input
PLL Input
PLL
PLL
20 Primary Clock Sources
To Quadrant Clock Selection
Clock Input
Clock Input
PLL
PLL
PLL Input
PLL Input
From Routing
Clock Input
From Routing
Note: Smaller devices have two PLLs.
2-7
Architecture
LatticeECP/EC Family Data Sheet
Secondary Clock Sources
LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are
tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These
secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7.
Figure 2-7. Secondary Clock Sources
From
From
From
From
Routing
Routing
Routing
Routing
From Routing
From Routing
From Routing
From Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From Routing
From Routing
From Routing
From Routing
From
From
From
From
Routing
Routing
Routing
Routing
Clock Routing
The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock
network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows
this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in
Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in
Figure 2-10.
2-8
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-8. Per Quadrant Primary Clock Selection
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing1
DCS
DCS
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
1. Smaller devices have fewer PLL related lines.
Figure 2-9. Per Quadrant Secondary Clock Selection
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
4 Secondary Clocks per Quadrant
Figure 2-10. Slice Clock Selection
Primary Clock
Secondary Clock
Routing
Clock to
each slice
GND
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nal to the feedback divider: from CLKOP (PLL Internal), from clock net (CLKOP) or from a user clock (PIN or logic).
There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the
sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
2-9
Architecture
LatticeECP/EC Family Data Sheet
grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
adjustment and not relock until the t
parameter has been satisfied. Additionally, the phase and duty cycle block
LOCK
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
quency range. The secondary divider is used to derive lower frequency outputs.
Figure 2-11. PLL Diagram
Dynamic Delay Adjustment
LOCK
Input Clock
Divider
(CLKI)
Post Scalar
Divider
(CLKOP)
Phase/Duty
Select
CLKI
(from routing or
external pin)
Voltage
Controlled
Oscillator
CLKOS
Delay
Adjust
CLKOP
CLKOK
RST
Secondary
Clock
Divider
Feedback
Divider
(CLKFB)
CLKFB
from CLKOP
(PLL internal),
from clock net
(CLKOP) or
(CLKOK)
from a user
clock (PIN or logic)
Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.
Figure 2-12. PLL Primitive
CLKOP
RST
CLKI
CLKI
CLKOP
LOCK
CLKOS
CLKOK
LOCK
EPLLB
CLKFB
CLKFB
DDA MODE
DDAIZR
EHXPLLB
DDAOZR
DDAILAG
DDAOLAG
DDAODEL[2:0]
DDAIDEL[2:0]
2-10
Architecture
LatticeECP/EC Family Data Sheet
Table 2-5. PLL Signal Descriptions
Signal
I/O
Description
CLKI
I
I
Clock input from external pin or routing
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
CLKFB
RST
I
“1” to reset PLL
CLKOS
O
O
O
O
I
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (No phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
CLKOP
CLKOK
LOCK
DDAMODE
DDAIZR
Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag
Dynamic Delay Input
I
DDAILAG
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
I
I
O
O
O
Dynamic Delay Zero Output
Dynamic Delay Lag/Lead Output
Dynamic Delay Output
For more information about the PLL, please see the list of technical documentation at the end of this data sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved regardless of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-13 illustrates
the DCS Block Macro.
Figure 2-13. DCS Block Primitive
CLK0
DCS
CLK1
SEL
DCSOUT
Figure 2-14 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information about the DCS, please see the list of technical documentation at the end of this
data sheet.
2-11
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-14. DCS Waveforms
CLK0
CLK1
SEL
DCSOUT
sysMEM Memory
The LatticeECP/EC devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of a 9-
Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6.
Table 2-6. sysMEM Block Configurations
Memory Mode
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
Single Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
True Dual Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
Pseudo Dual Port
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
2-12
Architecture
LatticeECP/EC Family Data Sheet
Memory Cascading
Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-15 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
Figure 2-15. sysMEM EBR Primitives
ADA[12:0]
DIA[17:0]
CLKA
CEA
RSTA
WEA
CSA[2:0]
DOA[17:0]
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
AD[12:0]
DI[35:0]
CLK
DO[35:0]
CE
EBR
EBR
RST
WE
CS[2:0]
True Dual Port RAM
Single Port RAM
ADW[12:0]
DI[35:0]
CLKW
CEW
ADR[12:0]
DO[35:0]
AD[12:0]
CLK
DO[35:0]
CE
EBR
ROM
EBR
WE
RST
CS[2:0]
CER
RST
CS[2:0]
CLKR
Pseudo-Dual Port RAM
The EBR memory supports three forms of write behavior for single port or dual port operation:
1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through – a copy of the input data appears at the output of the same port during a write cycle. This
mode is supported for all data widths.
3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.
This mode is supported for x9, x18 and x36 data widths.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associ-
ated resets for both ports are as shown in Figure 2-16.
2-13
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-16. Memory Core Reset
Q
Memory Core
Port A[17:0]
LCLR
Output Data
Latches
D
Q
Port B[17:0]
LCLR
RSTA
RSTB
GSRN
Programmable Disable
For further information about sysMEM EBR block, please see the the list of technical documentation at the end of
this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-17. The GSR input to the
EBR is always asynchronous.
Figure 2-17. EBR Asynchronous Reset (Including GSR) Timing Diagram
Reset
Clock
Clock
Enable
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
(EBR clock). The reset
MAX
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becomes active.
These instructions apply to all EBR RAM and ROM implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.
sysDSP Block
The LatticeECP-DSP family provides a sysDSP block, making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response
(FIR) filters; Fast Fourier Transforms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and
2-14
Architecture
LatticeECP/EC Family Data Sheet
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compared to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput. Their throughput is increased by
higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing an appropriate level of parallelism. Figure 2-18 compares the serial and the
parallel implementations.
Figure 2-18. Comparison of General DSP and LatticeECP-DSP Approaches
Operand
A
Operand
A
Operand
A
Operand
B
Operand
B
Operand
B
Operand
A
Operand
B
Multiplier 0
x
x
x
m/k
loops
Multiplier 1
Multiplier
(k-1)
M loops
Single
Multiplier
x
Accumulator
Σ
Accumulator
Σ
Function implemented in
General purpose DSP
Output
Function implemented
in LatticeECP
sysDSP Block Capabilities
The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but
not mixed within a function element. Similarly, the operand widths cannot be mixed within a block.
The resources in each sysDSP block can be configured to support the following four elements:
• MULT
(Multiply)
• MAC
• MULTADD
(Multiply, Accumulate)
(Multiply, Addition/Subtraction)
• MULTADDSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available in each block depends on the width selected from the three available options x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-1 shows the capabilities of the block.
2-15
Architecture
LatticeECP/EC Family Data Sheet
Table 2-7. Maximum Number of Elements in a Block
Width of Multiply
MULT
x9
8
x18
4
x36
1
MAC
2
2
—
—
—
MULTADD
MULTADDSUM
4
2
2
1
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift registers from previous operand registers. In addition by selecting “dynamic operation” in the
‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly
by selecting ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and
subtraction on every cycle.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-19 shows the MULT sysDSP element.
Figure 2-19. MULT sysDSP Element
Shift Register B In
Multiplicand
Shift Register A In
m
m
m
Multiplier
n
n
Multiplier
Input Data
Register A
m
n
m+n
(default)
m+n
n
x
Output
Input Data
Register B
Pipeline
Register
m
n
Signed
Input
Register
To
Multiplier
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
MAC sysDSP Element
In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. A registered overflow
signal is also available. The overflow conditions are provided later in this document. Figure 2-20 shows the MAC
sysDSP element.
2-16
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-20. MAC sysDSP Element
Shift Register B In
Shift Register A In
m
Multiplicand
Multiplier
m
Accumulator
m
n
m+n+16 bits
(default)
n
Multiplier
m
n
Input Data
Register A
n
Output
m+n+16 bits
(default)
x
m+n
(default)
Input Data
Register B
Pipeline
Register
n
n
SignedAB
Addn
Input
Register
Pipeline
Register
Overflow
signal
To
Accumulator
Input
Register
Pipeline
Register
To
Accumulator
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
Accumsload
Input
Register
Pipeline
Register
To
Accumulator
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
MULTADD sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-21
shows the MULTADD sysDSP element.
Figure 2-21. MULTADD
Shift Register B In
Shift Register A In
m
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
Multiplicand A0
m
RST(RST0,RST1,RST2,RST3)
m
n
Multiplier B0
n
Multiplier
Input Data
Register A
m
n
n
x
m+n
Input Data
Register B
(default)
Pipeline
Register
m
Add/Sub
n
Multiplicand A1
Multiplier B1
m
Output
m+n+1
(default)
m+n+1
(default)
m
n
Multiplier
m+n
(default)
Input Data
Register A
m
n
n
x
Input Data
Register B
Pipeline
Register
m
n
Signed
Addn
Input
Register
Pipeline
Register
To Add/Sub
To Add/Sub
Input
Pipeline
Register
Register
Shift Register B Out
Shift Register A Out
2-17
Architecture
LatticeECP/EC Family Data Sheet
MULTADDSUM sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/
subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction
are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-22 shows
the MULTADDSUM sysDSP element.
Figure 2-22. MULTADDSUM
Shift Register B In
Shift Register A In
m
Multiplicand A0
m
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
m
n
Multiplier B0
n
Multiplier
Input Data
Register A
m
n
RST(RST0,RST1,RST2,RST3)
m+n
(default)
n
x
Input Data
Register B
Pipeline
Register
m
Add/Sub0
n
Multiplicand A1
Multiplier B1
m
m+n
(default)
m
n
Multiplier
Input Data
Register A
n
n
m+n+1
n
x
Input Data
Register B
SUM
Pipeline
Register
Output
Multiplicand A2
Multiplier B2
m
m
m
m+n+2
m+n+2
n
n
Multiplier
m
n
Input Data
Register A
m+n
(default)
n
x
m+n+1
Input Data
Register B
Pipeline
Register
m
Add/Sub1
n
Multiplicand A3
Multiplier B3
m
m+n
(default)
m
n
Multiplier
Input Data
Register A
m
n
n
x
Input Data
Register B
Pipeline
Register
m
n
Signed
Addn0
Addn1
Input
Register
Pipeline
Register
To Add/Sub0, Add/Sub1
To Add/Sub0
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
To Add/Sub1
Shift Register B Out
Shift Register A Out
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset
and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)
one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and
Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)
at each input register, pipeline register and output register.
2-18
Architecture
LatticeECP/EC Family Data Sheet
Signed and Unsigned with Different Widths
The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-8 provides an example of this.
Table 2-8. An Example of Sign Extension
Unsigned
9-bit
Unsigned
18-bit
Two’s Complement
Signed 9-Bits
Two’s Complement
Signed 18-bits
Number Unsigned
Signed
0101
+5
-6
0101
0110
000000101 000000000000000101
000000110 000000000000000110
000000101
111111010
000000000000000101
111111111111111010
1010
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two
unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and
overflow signal is indicated. When two positive numbers are added with a negative sum and when two negative
numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an overflow
signal is indicated. Note when overflow occurs the overflow flag is present for only one cycle. By counting these
overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow signals for signed
and unsigned operands are listed in Figure 2-23.
Figure 2-23. Accumulator Overflow/Underflow Conditions
000000011
000000010
000000001
000000000
3
2
1
0101111100
0101111101 253
252
Carry signal is generated for
one cycle when this
254
255
256
0101111110
0101111111
1010000000
0
boundary is crossed
111111111
111111110
111111101
511
510
509
1010000001 257
1010000010
258
Unsigned Operation
000000011
+3
+2
+1
0
-1
-2
-3
0101111100
0101111101 253
0101111110
0101111111
252
000000010
000000001
000000000
111111111
111111110
111111101
Overflow signal is generated
for one cycle when this
boundary is crossed
254
255
1010000000
1010000001
1010000010
256
255
254
Signed Operation
2-19
Architecture
LatticeECP/EC Family Data Sheet
IPexpress™
The user can access the sysDSP block via the IPexpress configuration tool, included with the ispLEVER design
tool suite. IPexpress has options to configure each DSP module (or group of modules) or through direct HDL
instantiation. Additionally Lattice has partnered Mathworks to support instantiation in the Simulink tool, which is a
Graphical Simulation Environment. Simulink works with ispLEVER and dramatically shortens the DSP design cycle
in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Cor-
relators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo
Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available
DSP IPs.
Resources Available in the LatticeECP Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP family. Table 2-10 shows
the maximum available EBR RAM Blocks in each of the LatticeECP family. EBR blocks, together with Distributed
RAM can be used to store variables locally for the fast DSP operations.
Table 2-9. Number of DSP Blocks in LatticeECP Family
Device
LFECP6
LFECP10
LFECP15
LFECP20
LFECP33
DSP Block
9x9 Multiplier
18x18 Multiplier
36x36 Multiplier
4
5
6
7
8
32
40
48
56
64
16
20
24
28
32
4
5
6
7
8
Table 2-10. Embedded SRAM in LatticeECP Family
Total EBR SRAM
(Kbits)
Device
LFECP6
LFECP10
LFECP15
LFECP20
LFECP33
EBR SRAM Block
10
30
38
46
54
92
276
350
424
498
DSP Performance of the LatticeECP Family
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP family.
Table 2-11. DSP Block Performance of LatticeECP Family
DSP Performance
Device
LFECP6
LFECP10
LFECP15
LFECP20
LFECP33
DSP Block
MMAC
3680
4600
5520
6440
7360
4
5
6
7
8
2-20
Architecture
LatticeECP/EC Family Data Sheet
For further information about the sysDSP block, please see the list of technical information at the end of this data
sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O Buffers which are then connected to the PADs as
shown in Figure 2-24. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysI/O
buffer, and receives input from the buffer.
Figure 2-24. PIC Diagram
PIO A
TD
D0
D1
TD
OPOS1
ONEG1
IOLT0
DDRCLK
Tristate
Register Block
(2 Flip Flops)
PADA
"T"
D0
D1
OPOS0
ONEG0
DDRCLK
IOLD0
Output
Register Block
(2 Flip Flops)
sysIO
Buffer
INCK
INDD
INFF
IPOS0
IPOS1
INCK
INDD
INFF
IPOS0
IPOS1
DI
Control
Muxes
Input
Register Block
(5 Flip Flops)
CLKO
CEO
LSR
CLK
CE
LSR
GSRN
GSR
CLKI
CEI
DQS
DDRCLKPOL
PADB
"C"
PIO B
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25.
The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device
can be configured as LVDS transmit/receive pairs.
One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds
the DQS bus which spans the set of 16 PIOs. Figure 2-25 shows the assignment of DQS pins in each set of 16
PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table at the end of this data
sheet. Additional detail is provided in the Signal Descriptions table at the end of this data sheet. The DQS signal
from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed
for memories that support one DQS strobe per eight bits of data.
2-21
Architecture
LatticeECP/EC Family Data Sheet
Table 2-12. PIO Signal List
Name
Type
Description
CE0, CE1
CLK0, CLK1
LSR
Control from the core
Control from the core
Control from the core
Control from routing
Input to the core
Clock enables for input and output block FFs.
System clocks for input and output blocks.
Local Set/Reset.
GSRN
Global Set/Reset (active low).
INCK
Input to Primary Clock Network or PLL reference inputs.
DQS signal from logic (routing) to PIO.
DQS
Input to PIO
INDD
Input to the core
Unregistered data input to core.
INFF
Input to the core
Registered input on positive edge of the clock (CLK0).
DDRX registered inputs to the core.
IPOS0, IPOS1
ONEG0
OPOS0,
OPOS1 ONEG1
TD
Input to the core
Control from the core
Control from the core
Tristate control from the core
Tristate control from the core
Output signals from the core for SDR and DDR operation.
Output signals from the core for DDR operation
Signals to Tristate Register block for DDR operation.
Tristate signal from the core used in SDR operation.
DDRCLKPOL
Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block.
Figure 2-25. DQS Routing
PADA "T"
LVDS Pair
PIO A
PIO B
PIO A
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
Assigned
DQS Pin
PADA "T"
sysIO
Buffer
DQS
Delay
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PADA "T"
LVDS Pair
PADB "C"
PIO A
PIO B
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
2-22
Architecture
LatticeECP/EC Family Data Sheet
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-26 shows the diagram of the input register block.
Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first
passes through an optional delay block. This delay, if selected, reduces input-register hold-time requirement when
using a global clock.
The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Figure 2-27 shows the input register waveforms for DDR operation and Figure 2-28 shows the design tool primi-
tives. The SDR/SYNC registers have reset and clock enable available.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,
see the DDR Memory section of this data sheet.
Figure 2-26. Input Register Diagram
DI
(From sysIO
Buffer)
INCK
INDD
Delay Block
Fixed Delay
SDR & Sync
Registers
DDR Registers
D0
D2
To Routing
Q
D
Q
D
D
IPOS0
IPOS1
D-Type
/LATCH
D-Type
D1
Q
D
Q
Q
D
D-Type
/LATCH
D-Type
D-Type
DQS Delayed
(From DQS
Bus)
CLK0
(From Routing)
DDRCLKPOL
(From DDR
Polarity Control Bus)
2-23
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-27. Input Register DDR Waveforms
DI
F
A
B
C
D
E
(In DDR Mode)
DQS
DQS
Delayed
B
A
D
C
D0
D2
Figure 2-28. INDDRXB Primitive
D
ECLK
QA
QB
LSR
SCLK
IDDRXB
CE
DDRCLKPOL
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysI/O buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-29 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-30 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
2-24
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-29. Output Register Block
OUTDDN
Q
D
D-Type
/LATCH
ONEG0
0
DO
0
1
From
Routing
1
To sysIO
Buffer
OPOS0
Q
D
Latch
LE*
CLK1
Programmed
Control
*Latch is transparent when input is low.
Figure 2-30. ODDRXB Primitive
DA
DB
ODDRXB
Q
CLK
LSR
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
2-25
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-31. Tristate Register Block
TD
OUTDDN
Q
D
D-Type
/LATCH
ONEG1
0
TO
0
1
From
Routing
1
To sysIO
Buffer
OPOS1
Q
D
Latch
LE*
CLK1
Programmed
Control
*Latch is transparent when input is low.
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is
selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from
the programmable DQS pin. The clock can optionally be inverted.
The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate
signal is passed through this block.
DDR Memory Support
Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input
(for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeEC
devices provide this capability. In addition to these registers, the LatticeEC devices contain two elements to simplify
the design of input structures for read operations: the DQS delay block and polarity control logic.
DLL Calibrated DQS Delay Block
Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment. However in DDR memories the clock
(referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS routing
resource. The DQS signal also feeds polarity control logic, which controls the polarity of the clock to the sync regis-
ters in the input register blocks. Figures 2-32 and 2-33 show how the DQS transition signals are routed to the PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of
the device as shown in Figure 2-33. The DLL loop is compensated for temperature, voltage and process variations
by the system clock and feedback loop.
2-26
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-32. DQS Local Bus.
PIO
Delay
Control
Bus
DDR
Datain
PAD
sysIO
Buffer
Input
Register Block
( 5 Flip Flops)
Polarity
Control
Bus
To Sync.
Reg.
DI
GSR
CLKI
CEI
DQS
Bus
To DDR
Reg.
DQS
DQS
PIO
DQS
Strobe
PAD
sysIO
Buffer
Polarity Control
Logic
DI
DQS
DQSDEL
Calibration Bus
from DLL
Figure 2-33. DLL Calibration Bus and DQS/DQS Transition Distribution
Delay Control Bus
Polarity Control Bus
DQS Bus
DLL
DLL
2-27
Architecture
LatticeECP/EC Family Data Sheet
Polarity Control Logic
In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system Clock (during the READ cycle) is unknown.
The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup
and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
sysI/O Buffer
Each I/O is associated with a flexible buffer referred to as a sysI/O buffer. These buffers are arranged around the
periphery of the device in eight groups referred to as Banks. The sysI/O buffers allow users to implement the wide
variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysI/O Buffer Banks
LatticeECP/EC devices have eight sysI/O buffer banks; each is capable of supporting multiple I/O standards. Each
sysI/O bank has its own I/O supply voltage (V
), and two voltage references V
and V
resources allow-
CCIO
REF1
REF2
ing each bank to be completely independent from each other. Figure 2-34 shows the eight banks and their associ-
ated supplies.
In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-
X) are powered using V
LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold
CCIO.
input independent of V
In addition to the bank V
supplies, the LatticeECP/EC devices have a V core logic
CCIO.
CCIO CC
power supply, and a V
supply that power all differential and referenced buffers.
CCAUX
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be configured to be a
reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference volt-
ages.
2-28
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-34. LatticeECP/EC Banks
TOP
Bank 0
Bank 1
VCCIO7
VCCIO2
VREF1(2)
VREF2(2)
GND
VREF1(7)
VREF2(7)
GND
VCCIO6
VCCIO3
VREF1(6)
VREF2(6)
VREF1(3)
VREF2(3)
GND
GND
Bank 5
Bank 4
BOTTOM
LatticeECP/EC devices contain two types of sysI/O buffer pairs.
1. Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only)
The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers
and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also
be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have programmable PCI clamps. These I/O banks also support hot
socketing with IDK less than 1mA. Note that the PCI clamp is enabled after V , V
and V
are at valid
CC CCAUX
CCIO
operating levels and the device has been configured.
2. Left and Right sysI/O Buffer Pairs (Differential and Single-Ended Outputs)
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Only the left and right banks have LVDS differential output drivers. See the I specification for I/O leakage cur-
DK
rent during power-up.
2-29
Architecture
LatticeECP/EC Family Data Sheet
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when V and V
have reached satisfactory levels.
CCAUX
CC
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all other V banks are active with valid input logic levels to properly control the output logic states of all the
CCIO
I/O banks that are critical to the application. For more information about controlling the output logic state with valid
input logic levels during power-up in LatticeECP/EC devices, see the list of technical documentation at the end of
this data sheet.
The V and V
supply the power to the FPGA core fabric, whereas the V
supplies power to the I/O buf-
CC
CCAUX
CCIO
fers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended
that the I/O buffers be powered-up prior to the FPGA core fabric. V supplies should be powered-up before or
CCIO
together with the V and V
supplies.
CC
CCAUX
Supported Standards
The LatticeECP/EC sysI/O buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2,
1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable
options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain.
Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS,
BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards
(together with their supply and reference voltages) supported by the LatticeECP/EC devices. For further informa-
tion about utilizing the sysI/O buffer to support a variety of standards please see the the list of technical information
at the end of this data sheet.
Table 2-13. Supported Input Standards
Input Standard
Single Ended Interfaces
LVTTL
LVCMOS332
LVCMOS252
VREF (Nom.)
VCCIO1 (Nom.)
—
—
—
—
—
1.8
1.5
—
3.3
—
—
—
—
—
—
—
—
LVCMOS18
—
LVCMOS15
LVCMOS122
—
—
PCI
—
HSTL18 Class I, II
HSTL18 Class III
0.9
1.08
0.75
0.9
1.5
1.25
0.9
HSTL15 Class I
HSTL15 Class III
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I
Differential Interfaces
Differential SSTL18 Class I
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I, III
Differential HSTL18 Class I, II, III
LVDS, LVPECL, BLVDS, RSDS
—
—
—
—
—
—
—
—
—
—
—
—
1. When not specified VCCIO can be set anywhere in the valid operating range.
2. JTAG inputs do not have a fixed threshold option and always follow VCCJ.
2-30
Architecture
LatticeECP/EC Family Data Sheet
Table 2-14. Supported Output Standards
Output Standard
Single-ended Interfaces
LVTTL
Drive
VCCIO (Nom.)
4mA, 8mA, 12mA, 16mA, 20mA
3.3
3.3
2.5
1.8
1.5
1.2
—
LVCMOS33
4mA, 8mA, 12mA 16mA, 20mA
LVCMOS25
4mA, 8mA, 12mA, 16mA, 20mA
LVCMOS18
4mA, 8mA, 12mA, 16mA
LVCMOS15
4mA, 8mA
LVCMOS12
2mA, 6mA
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
—
4mA, 8mA, 12mA 16mA
—
4mA, 8mA
2mA, 6mA
N/A
—
—
3.3
1.8
1.5
3.3
2.5
1.8
HSTL18 Class I, II, III
HSTL15 Class I, III
SSTL3 Class I, II
N/A
N/A
N/A
SSTL2 Class I, II
N/A
SSTL18 Class I
N/A
Differential Interfaces
Differential SSTL3, Class I, II
Differential SSTL2, Class I, II
Differential SSTL18, Class I
Differential HSTL18, Class I, II, III
Differential HSTL15, Class I, III
LVDS
BLVDS1
LVPECL1
RSDS1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
2.5
1.8
1.8
1.5
2.5
2.5
3.3
2.5
1. Emulated with external resistors.
Hot Socketing
The LatticeECP/EC devices have been carefully designed to ensure predictable behavior during power-up and
power-down. Power supplies can be sequenced in any order. During power up and power-down sequences, the
I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition,
leakage into I/O pins is controlled within specified limits, this allows for easy integration with the rest of the sys-
tem. These capabilities make the LatticeECP/EC ideal for many multiple power supply and hot-swap applica-
tions.
Configuration and Testing
The following section describes the configuration and testing features of the LatticeECP/EC devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test
access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
2-31
Architecture
LatticeECP/EC Family Data Sheet
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
V
and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
CCJ
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeECP/EC devices contain two possible ports that can be used for device configuration. The test access
port (TAP), which supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial
configuration.
The TAP supports both the IEEE Std. 1149.1 Boundary Scan specification and the IEEE Std. 1532 In-System Con-
figuration specification. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and
the rest being dual-use pins (please refer to TN1053 for more information about using the dual-use pins as general
purpose I/O). There are four configuration options for LatticeECP/EC devices:
1. Industry standard SPI memories.
2. Industry standard byte wide flash and ispMACH 4000 for control/addressing.
3. Configuration from system microprocessor via the configuration bus or TAP.
4. Industry standard FPGA board memory.
On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a
configuration port is selected, that port is locked and another configuration port cannot be activated until the next
power-up sequence.
For more information about device configuration, please see the list of technical documentation at the end of this
data sheet.
Internal Logic Analyzer Capability (ispTRACY)
All LatticeECP/EC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide
capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace
memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at com-
pile time.
For more information about ispTRACY, please see information regarding additional technical documentation at the
end of this data sheet.
External Resistor
LatticeECP/EC devices require a single external, 10K ohm +/- 1% value between the XRES pin and ground. Device
configuration will not be completed if this resistor is missing. There is no boundary scan register on the external
resistor pad.
2-32
Architecture
LatticeECP/EC Family Data Sheet
Oscillator
Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master clock for configura-
tion. The oscillator and the master clock run continuously. The default value of the master clock is 2.5MHz. Table 2-
15 lists all the available Master Clock frequencies. When a different Master Clock is selected during the design pro-
cess, the following sequence takes place:
1. User selects a different Master Clock frequency.
2. During configuration the device starts with the default (2.5MHz) Master Clock frequency.
3. The clock configuration settings are contained in the early configuration bit stream.
4. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
For further information about the use of this oscillator for configuration, please see the list of technical documenta-
tion at the end of this data sheet.
Table 2-15. Selectable Master Clock (CCLK) Frequencies During Configuration
CCLK (MHz)
CCLK (MHz)
CCLK (MHz)
2.5*
4.3
13
15
20
26
30
34
41
45
51
55
60
130
—
5.4
6.9
8.1
9.2
10.0
—
Density Shifting
The LatticeECP/EC family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design
targeted for a high-density device to a lower density device. However, the exact details of the final resource utiliza-
tion will impact the likely success in each case.
2-33
LatticeECP/EC Family Data Sheet
DC and Switching Characteristics
September 2012
Data Sheet
Absolute Maximum Ratings1, 2, 3
Supply Voltage V . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V
CC
Supply Voltage V
Supply Voltage V
. . . . . . . . . . . . . . . . -0.5 to 3.75V
CCAUX
. . . . . . . . . . . . . . . . . . -0.5 to 3.75V
CCJ
Output Supply Voltage V
. . . . . . . . . . . -0.5 to 3.75V
CCIO
Dedicated Input Voltage Applied4 . . . . . . . . -0.5 to 4.25V
I/O Tristate Voltage Applied 4 . . . . . . . . . . . . -0.5 to 3.75V
Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C
Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . +125°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.
Recommended Operating Conditions
Symbol
VCC
VCCAUX
VCCPLL
Parameter
Min.
1.14
3.135
1.14
1.140
1.140
0
Max.
1.26
3.465
1.26
3.465
3.465
85
Units
V
Core Supply Voltage
3
Auxiliary Supply Voltage
V
PLL Supply Voltage for ECP/EC33
I/O Driver Supply Voltage
V
1, 2
VCCIO
V
1
VCCJ
Supply Voltage for IEEE 1149.1 Test Access Port
Junction Commercial Operation
Junction Industrial Operation
V
tJCOM
tJIND
°C
°C
-40
100
1. If VCCIO or VCCJ is set to 1.2V, they must be connected to the same power supply as VCC. If VCCIO or VCCJ is set to 3.3V, they must be con-
nected to the same power supply as VCCAUX
.
2. See recommended voltages by I/O standard in subsequent table.
3. VCCAUX ramp rate must not exceed 3mV/µs for commercial and 0.6 mV/µs for industrial device operations during power up when transition-
ing between 0.8V and 1.8V.
Hot Socketing Specifications1, 2, 3, 4
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
Top and Bottom General Purpose sysI/Os (Banks 0, 1, 4 and 5), JTAG and Dedicated sysCONFIG Pins
IDK_TB
Input or I/O Leakage Current
0 ð VIN ð VIH (MAX.)
—
—
+/-1000
µA
Left and Right General Purpose sysI/Os (Banks 2, 3, 6 and 7)
VIN ð VCCIO
—
—
—
+/-1000
—
µA
IDK_LR
Input or I/O Leakage Current
VIN > VCCIO
35
mA
1. Insensitive to sequence of VCC, VCCAUX and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX and VCCIO.
2. 0 ð VCC ð VCC (MAX), 0 ð VCCIO ð VCCIO (MAX) or 0 ð VCCAUX ð VCCAUX (MAX).
3. IDK is additive to IPU, IPW or IBH
4. LVCMOS and LVTTL only.
.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
3-1
DC and Switching_02.0
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Input or I/O Leakage
Condition
0 ð VIN ð (VCCIO - 0.2V)
(VCCIO - 0.2V) ð VIH ð 3.6V
0 ð VIN ð 0.7 VCCIO
Min.
Typ.
—
—
—
—
—
—
—
—
—
Max.
10
Units
µA
µA
µA
µA
µA
µA
µA
µA
V
1
I
IL, IIH
—
—
1, 3
IIH
Input or I/O High Leakage
I/O Active Pull-up Current
I/O Active Pull-down Current
40
IPU
-30
-150
150
IPD
VIL (MAX) ð VIN ð VIH (MAX)
30
IBHLS
IBHHS
IBHLO
IBHLH
VBHT
Bus Hold Low sustaining current VIN = VIL (MAX)
Bus Hold High sustaining current VIN = 0.7VCCIO
Bus Hold Low Overdrive current 0 ð VIN ð VIH (MAX)
Bus Hold High Overdrive current 0 ð VIN ð VIH (MAX)
30
—
-30
—
—
150
—
-150
VIH (MIN)
Bus Hold trip Points
I/O Capacitance2
0 ð VIN ð VIH (MAX)
VIL (MAX)
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
C1
C2
—
—
8
6
—
—
pf
pf
VCC = 1.2V, VIO = 0 to VIH (MAX)
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
CC = 1.2V, VIO = 0 to VIH (MAX)
Dedicated Input Capacitance2
V
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. TA 25oC, f = 1.0MHz
3. For top and bottom general purpose I/O pins, when VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a
peak current of 6mA can occur on the high-to-low transition. For left and right I/O banks, VIH must be less than or equal to VCCIO
.
3-2
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Supply Current (Standby)1, 2, 3, 4
Over Recommended Operating Conditions
Symbol
Parameter
Device
Typ.5
6
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
LFEC1
LFEC3
10
15
25
35
60
85
15
5
LFECP6/LFEC6
LFECP10/LFEC10
LFECP15/LFEC15
LFECP20/LFEC20
LFECP33/LFEC33
ICC
Core Power Supply Current
ICCAUX Auxiliary Power Supply Current
ICCPLL
ICCIO
ICCJ
PLL Power Supply Current
Bank Power Supply Current6
VCCJ Power Supply Current
2
5
1. For further information about supply current, please see the list of technical documentation at the end of this data sheet.
2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
3. Frequency 0MHz.
4. Pattern represents a “blank” configuration data file.
5. TJ=25oC, power supplies at nominal voltage.
6. Per bank.
3-3
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Initialization Supply Current1, 2, 3, 4, 5, 6
Over Recommended Operating Conditions
Symbol
Parameter
Devices
Typ.6
25
40
50
60
70
150
220
30
30
30
35
35
40
40
12
4
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
LFEC1
LFEC3
LFECP6/LFEC6
LFECP10/LFEC10
LFECP15/LFEC15
LFECP20/LFEC20
LFECP33/LFEC33
LFEC1
ICC
Core Power Supply Current
LFEC3
LFECP6/LFEC6
ICCAUX Auxiliary Power Supply Current LFECP10/LFEC10
LFECP15/LFEC15
LFECP20/LFEC20
LFECP33/LFEC33
ICCPLL
ICCIO
ICCJ
PLL Power Supply Current
Bank Power Supply Current7
VCCJ Power Supply Current
LFEC1
LFEC3
5
LFECP6/LFEC6
LFECP10/LFEC10
LFECP15/LFEC15
LFECP20/LFEC20
LFECP33/LFEC33
6
6
7
8
8
20
1. Until DONE signal is active.
2. For further information about supply current, please see the list of technical documentation at the end of this data sheet.
3. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the VCCIO or GND.
4. Frequency 0MHz.
5. Pattern represents typical design with 65% logic, 55% EBR, 10% routing utilization.
6. TJ=25oC, power supplies at nominal voltage.
7. Per bank.
3-4
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
sysI/O Recommended Operating Conditions
VCCIO
VREF (V)
Standard
LVCMOS 3.3
Min.
3.135
2.375
1.71
Typ.
3.3
2.5
1.8
1.5
1.2
3.3
3.3
1.8
2.5
3.3
1.5
1.5
1.8
1.8
2.5
3.3
2.5
2.5
Max.
3.465
2.625
1.89
Min.
—
Typ.
—
Max.
—
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
LVTTL
—
—
—
—
—
—
1.425
1.14
1.575
1.26
—
—
—
—
—
—
3.135
3.135
1.71
3.465
3.465
1.89
—
—
—
PCI
—
—
—
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL15 Class III
HSTL 18 Class I, II
HSTL 18 Class III
LVDS
0.833
1.15
1.3
0.68
—
0.90
1.25
1.5
0.75
0.9
0.9
1.08
—
0.969
1.35
1.7
0.9
—
2.375
3.135
1.425
1.425
1.71
2.625
3.465
1.575
1.575
1.89
—
—
1.71
1.89
—
—
2.375
3.135
2.375
2.375
2.625
3.465
2.625
2.625
—
—
LVPECL1
BLVDS1
RSDS1
—
—
—
—
—
—
—
—
—
1. Outputs are implemented with the addition of external resistors. VCCIO applies to outputs only.
3-5
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
sysI/O Single-Ended DC Electrical Characteristics
VIL
VIH
Min. (V)
1
1
Input/Output
Standard
VOL Max.
(V)
VOH Min.
(V)
IOL
IOH
Min. (V) Max. (V)
Max. (V)
(mA)
(mA)
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.4
0.2
0.4
0.2
0.4
V
CCIO - 0.4
VCCIO - 0.2
VCCIO - 0.4
LVCMOS 3.3
LVTTL
-0.3
-0.3
-0.3
0.8
0.8
0.7
2.0
2.0
1.7
3.6
0.1
-0.1
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
3.6
3.6
V
V
CCIO - 0.2
CCIO - 0.4
0.1
-0.1
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
LVCMOS 2.5
0.2
0.4
VCCIO - 0.2
0.1
-0.1
-16, -12, -8, -4
-0.1
VCCIO - 0.4 16, 12, 8, 4
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
-0.3
-0.3
-0.3
0.35VCCIO
0.35VCCIO
0.65VCCIO
0.65VCCIO
0.65VCC
3.6
3.6
3.6
0.2
V
CCIO - 0.2
VCCIO - 0.4
CCIO - 0.2
0.1
8, 4
0.1
6, 2
0.1
1.5
8
0.4
-8, -4
-0.1
0.2
V
0.4
VCCIO - 0.4
VCCIO - 0.2
0.9VCCIO
-6, -2
-0.1
0.35VCC
0.3VCCIO
0.2
PCI
-0.3
-0.3
-0.3
-0.3
-0.3
0.5VCCIO
VREF + 0.2
VREF + 0.2
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.1VCCIO
0.7
-0.5
SSTL3 class I
SSTL3 class II
SSTL2 class I
SSTL2 class II
SSTL18 class I
HSTL15 class I
HSTL15 class III
HSTL18 class I
HSTL18 class II
HSTL18 class III
V
REF - 0.2
VCCIO - 1.1
VCCIO - 0.9
VCCIO - 0.62
VCCIO - 0.43
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
-8
VREF - 0.2
0.5
16
-16
V
V
REF - 0.18 VREF + 0.18
REF - 0.18 VREF + 0.18
0.54
0.35
0.4
7.6
15.2
6.7
8
-7.6
-15.2
-6.7
-0.3 VREF - 0.125 VREF + 0.125
-0.3
-0.3
-0.3
-0.3
-0.3
V
V
REF - 0.1
REF - 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
0.4
-8
0.4
24
-8
VREF - 0.1
0.4
9.6
16
-9.6
V
V
REF - 0.1
REF - 0.1
0.4
-16
0.4
24
-8
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
3-6
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
sysI/O Differential Electrical Characteristics
LVDS
Over Recommended Operating Conditions
Parameter
Symbol
Parameter Description
Input voltage
Test Conditions
Min.
0
Typ.
—
Max.
2.4
Units
V
VINP, VINM
VTHD
Differential input threshold
Input common mode voltage
Input current
+/-100
VTHD/2
VTHD/2
VTHD/2
—
—
—
mV
V
100mV ð VTHD
1.2
1.2
1.2
—
1.8
VCM
200mV ð VTHD
1.9
V
350mV ð VTHD
2.0
V
IIN
Power on or power off
+/-10
1.60
—
µA
V
VOH
VOL
VOD
Output high voltage for VOP or VOM RT = 100 Ohm
Output low voltage for VOP or VOM RT = 100 Ohm
—
1.38
1.03
350
0.9V
250
V
Output voltage differential
(VOP - VOM), RT = 100 Ohm
450
mV
Change in VOD between high and
low
VOD
—
—
50
mV
VOS
Output voltage offset
(VOP + VOM)/2, RT = 100 Ohm
1.125
—
1.25
—
1.375
50
V
VOS
Change in VOS between H and L
mV
VOD = 0V Driver outputs
shorted
IOSD
Output short circuit current
—
—
6
mA
3-7
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
LVDS25E
The top and bottom side of LatticeECP/EC devices support LVDS outputs via emulated complementary LVCMOS
outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in
Figure 3-1 is one possible solution for point-to-point signals.
Figure 3-1. LVDS25E Output Termination Example
Bourns
CAT16-LV4F12
VCCIO = 2.5V ( 5ꢀ%
RS=165 ohms
( 1ꢀ%
+
-
RD = 140 ohms
( 1ꢀ%
RD = 100 ohms
( 1ꢀ%
VCCIO = 2.5V ( 5ꢀ%
RS=165 ohms
( 1ꢀ%
Transmission line, Zo = 100 ohm differential
ON-chip
ON-chip
OFF-chip
OFF-chip
Table 3-1. LVDS25E DC Conditions
Parameter
Description
Output high voltage
Output low voltage
Typical
1.42
1.08
0.35
1.25
Units
VOH
VOL
V
V
V
V
¾
VOD
VCM
ZBACK
Output differential voltage
Output common mode voltage
Back impedance
100
3-8
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
BLVDS
The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS
outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when
multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one
possible solution for bi-directional multi-point differential signals.
Figure 3-2. BLVDS Multi-point Output Example
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
2.5V
2.5V
2.5V
100
100
45-90 ohms, +/- 1%
45-90 ohms, +/- 1%
100
100
. . .
+
-
+
-
2.5V
100
2.5V
100
2.5V
100
2.5V
100
Table 3-2. BLVDS DC Conditions1
Over Recommended Operating Conditions
Typical
Parameter
Description
Zo = 45 Zo = 90
Units
ohm
ohm
ohm
V
ZOUT
RTLEFT
RTRIGHT
VOH
Output impedance
100
45
100
90
Left end termination
Right end termination
Output high voltage
45
90
1.375
1.125
0.25
1.25
11.2
1.48
1.02
0.46
1.25
10.2
VOL
Output low voltage
V
VOD
Output differential voltage
Output common mode voltage
DC output current
V
VCM
V
IDC
mA
1. For input buffer, see LVDS table.
3-9
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LVPECL
The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard
is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for
point-to-point signals.
Figure 3-3. Differential LVPECL
3.3V
100 ohms
+
~150 ohms
100 ohms
3.3V
-
100 ohms
Off-chip
Transmission line, Zo = 100 ohm differential
Table 3-3. LVPECL DC Conditions1
Over Recommended Operating Conditions
Parameter
ZOUT
Description
Output impedance
Typical
100
Units
ohm
ohm
ohm
V
RP
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
150
RT
100
VOH
VOL
VOD
VCM
ZBACK
IDC
2.03
1.27
0.76
1.65
85.7
12.7
V
Output differential voltage
Output common mode voltage
Back impedance
V
V
ohm
mA
DC output current
1. For input buffer, see LVDS table.
For further information about LVPECL, BLVDS and other differential interfaces please see the list of technical infor-
mation at the end of this data sheet.
3-10
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
RSDS
The LatticeECP/EC devices support differential RSDS standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-
ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS
standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in
Figure 3-4 are industry standard values for 1% resistors.
Figure 3-4. RSDS (Reduced Swing Differential Standard)
VCCIO = 2.5V
294
Zo = 100
+
VCCIO = 2.5V
121
100
-
294
On-chip
Off-chip
Emulated
RSDS Buffer
Table 3-4. RSDS DC Conditions
Parameter
ZOUT
RS
Description
Typical
20
Units
ohm
ohm
ohm
ohm
V
Output impedance
Driver series resistor
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
294
RP
121
RT
100
VOH
1.35
1.15
0.20
1.25
101.5
3.66
VOL
V
VOD
Output differential voltage
Output common mode voltage
Back impedance
V
VCM
ZBACK
IDC
V
ohm
mA
DC output current
3-11
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Typical Building Block Function Performance
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Function
Basic Functions
-5 Timing
Units
16-bit decoder
32-bit decoder
64-bit decoder
4:1 MUX
5.5
6.9
7.1
4.3
4.7
5.0
5.5
ns
ns
ns
ns
ns
ns
ns
8:1 MUX
16:1 MUX
32:1 MUX
Register-to-Register Performance1
Function
Basic Functions
-5 Timing
Units
16 bit decoder
410
283
272
613
565
526
442
363
353
196
414
317
216
178
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
32 bit decoder
64 bit decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
8-bit adder
16-bit adder
64-bit adder
16-bit counter
32-bit counter
64-bit counter
64-bit accumulator
Embedded Memory Functions
256x36 Single Port RAM
512x18 True-Dual Port RAM
Distributed Memory Functions
16x2 Single Port RAM
64x2 Single Port RAM
128x4 Single Port RAM
32x2 Pseudo-Dual Port RAM
64x4 Pseudo-Dual Port RAM
DSP Function2
280
280
MHz
MHz
460
375
294
392
332
MHz
MHz
MHz
MHz
MHz
9x9 Pipelined Multiply/Accumulate
18x18 Pipelined Multiply/Accumulate
36x36 Pipelined Multiply
242
238
235
MHz
MHz
MHz
1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with design and tool version. The tool
uses internal parameters that have been characterized but are not tested on every device.
2. Applies to LatticeECP devices only.
Timing v.G 0.30
3-12
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Derating Timing Tables
Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case
numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be
much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and
voltage multiply the noted numbers with the derating factors provided below.
The junction temperature for the FPGA depends on the power dissipation by the device, the package thermal char-
acteristics ( ), and the ambient temperature, as calculated with the following equation:
JA
T
= T
+ (Power * )
JMAX
AMAX JA
The user must determine this temperature and then use it to determine the derating factor based on the following
derating tables: T °C.
J
Table 3-5. Delay Derating Table for Internal Blocks
Power Supply Voltage
TJ °C
TJ °C
Commercial
Industrial
1.14V
0.82
0.82
0.89
0.93
1.00
1.2V
0.77
0.76
0.83
0.87
0.94
1.26V
0.71
0.71
0.78
0.81
0.89
—
—
0
-40
-25
20
25
85
45
105
3-13
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC External Switching Characteristics
Over Recommended Operating Conditions
-5
-4
-3
Parameter
Description
Device
Min.
Max.
Min.
Max.
Min.
Max.
Units
General I/O Pin Parameters (Using Primary Clock without PLL)1
LFEC1
—
5.09
5.71
5.60
5.47
5.67
5.89
6.19
—
—
6.11
6.85
6.72
6.57
6.81
7.07
7.42
—
—
7.13
7.99
7.84
7.66
7.94
8.25
8.66
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Output - PIO Output
Register
7
tCO
LFEC10
LFEC15
LFEC20
LFEC33
LFEC1
—
—
—
—
—
—
—
—
—
—
—
—
-0.08
-0.70
-0.63
-0.43
-0.70
-0.88
-1.12
2.19
2.80
2.69
2.56
2.76
2.99
3.28
3.36
2.74
2.81
3.01
2.74
2.56
2.32
-1.31
-0.70
-0.80
-0.93
-0.73
-0.51
-0.22
-0.10
-0.84
-0.76
-0.52
-0.84
-1.06
-1.34
2.62
3.36
3.23
3.08
3.32
3.58
3.93
4.03
3.29
3.37
3.61
3.29
3.07
2.79
-1.57
-0.83
-0.96
-1.12
-0.88
-0.61
-0.26
-0.12
-0.98
-0.89
-0.61
-0.98
-1.24
-1.56
3.06
3.92
3.77
3.59
3.87
4.18
4.59
4.70
3.84
3.93
4.21
3.83
3.58
3.25
-1.83
-0.97
-1.12
-1.30
-1.02
-0.71
-0.30
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Data Setup - PIO Input
Register
7
tSU
LFEC10
LFEC15
LFEC20
LFEC33
LFEC1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Data Hold - PIO Input
Register
7
tH
LFEC10
LFEC15
LFEC20
LFEC33
LFEC1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Data Setup - PIO Input
Register with Data Input Delay
7
tSU_DEL
LFEC10
LFEC15
LFEC20
LFEC33
LFEC1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Data Hold - PIO Input
Register with Input Data Delay
tH_DEL7
LFEC10
LFEC15
LFEC20
LFEC33
—
—
—
—
—
—
—
—
—
—
—
—
Clock Frequency of I/O and PFU
Register
2
fMAX_IO
All
—
420
—
378
—
340
Mhz
DDR I/O Pin Parameters3, 4, 5
tDVADQ Data Valid After DQS (DDR Read) All
tDVEDQ Data Hold After DQS (DDR Read) All
—
0.19
—
—
0.19
—
—
0.19
—
UI
UI
0.67
0.67
0.67
3-14
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC External Switching Characteristics (Continued)
Over Recommended Operating Conditions
-5
-4
-3
Parameter
tDQVBS
Description
Data Valid Before DQS
Data Valid After DQS
DDR Clock Frequency
Device
All
Min.
0.20
0.20
95
Max.
—
Min.
0.20
0.20
95
Max.
—
Min.
0.20
0.20
95
Max.
—
Units
UI
tDQVAS
All
All
—
—
—
UI
fMAX_DDR
200
166
133
MHz
Primary and Secondary Clock6
2
fMAX_PRI
Frequency for Primary Clock Tree All
—
420
—
—
378
—
—
340
—
MHz
ns
Clock Pulse Width for Primary
tW_PRI
All
1.19
1.19
1.19
Clock
Primary Clock Skew within an I/O
Bank
tSKEW_PRI
All
—
250
—
300
—
350
ps
1. General timing numbers based on LVCMOS2.5V, 12 mA. Loading of 0 pF.
2. Using LVDS I/O standard.
3. DDR timing numbers based on SSTL I/O.
4. DDR specifications are characterized but not tested.
5. UI is average bit period.
6. Based on a single primary clock.
7. These timing numbers were generated using ispLEVER design tool. Exact performance may vary with design and tool version. The tool
uses internal parameters that have been characterized but are not tested on every device.
Timing v.G 0.30
Figure 3-5. DDR Timings
DQ and DQS Read Timings
DQS
DQ
tDVADQ
tDVEDQ
DQ and DQS Write Timings
DQS
DQ
tDQVBS
tDQVAS
3-15
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC Internal Switching Characteristics
Over Recommended Operating Conditions
-5
-4
-3
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
PFU/PFF Logic Mode Timing
tLUT4_PFU
tLUT6_PFU
tLSR_PFU
tSUM_PFU
tHM_PFU
LUT4 Delay (A to D Inputs to F Output)
LUT6 Delay (A to D Inputs to OFX Output)
Set/Reset to Output of PFU
—
—
0.25
0.40
0.81
—
—
—
0.31
0.48
0.98
—
—
—
0.36
0.56
1.14
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
Clock to Mux (M0,M1) Input Setup Time
Clock to Mux (M0,M1) Input Hold Time
Clock to D Input Setup Time
0.12
-0.05
0.12
-0.03
—
0.14
-0.06
0.14
-0.03
—
0.16
-0.06
0.16
-0.04
—
—
—
—
tSUD_PFU
tHD_PFU
—
—
—
Clock to D Input Hold time
—
—
—
tCK2Q_PFU
tLE2Q_PFU
tLD2Q_PFU
Clock to Q Delay, D-type Register Configuration
Clock to Q Delay Latch Configuration
D to Q Throughput Delay when Latch is Enabled
0.36
0.48
0.50
0.44
0.58
0.60
0.51
0.68
0.69
—
—
—
—
—
—
PFU Dual Port Memory Mode Timing
tCORAM_PFU
tSUDATA_PFU
tHDATA_PFU
Clock to Output
—
0.36
—
—
0.44
—
—
0.51
—
ns
ns
ns
ns
ns
ns
ns
Data Setup Time
-0.20
0.26
-0.51
0.64
-0.24
0.30
-0.24
0.31
-0.62
0.77
-0.29
0.36
-0.28
0.36
-0.72
0.90
-0.34
0.42
Data Hold Time
—
—
—
tSUADDR_PFU
tHADDR_PFU
tSUWREN_PFU
tHWREN_PFU
PIC Timing
Address Setup Time
Address Hold Time
—
—
—
—
—
—
Write/Read Enable Setup Time
Write/Read Enable Hold Time
—
—
—
—
—
—
PIO Input/Output Buffer Timing
tIN_PIO
Input Buffer Delay
Output Buffer Delay
—
—
0.56
1.92
—
—
0.67
2.31
—
—
0.78
2.69
ns
ns
tOUT_PIO
IOLOGIC Input/Output Timing
tSUI_PIO
Input Register Setup Time (Data Before Clock)
0.90
0.62
—
—
—
1.08
0.74
—
—
—
1.26
0.87
—
—
—
ns
ns
ns
ns
ns
ns
ns
tHI_PIO
Input Register Hold Time (Data after Clock)
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
tCOO_PIO
0.33
—
0.40
—
0.46
—
tSUCE_PIO
tHCE_PIO
-0.10
0.12
0.18
-0.15
-0.12
0.14
0.21
-0.18
-0.14
0.17
0.25
-0.21
—
—
—
tSULSR_PIO
tHLSR_PIO
EBR Timing
tCO_EBR
—
—
—
Set/Reset Hold Time
—
—
—
Clock to Output from Address or Data
Clock to Output from EBR output Register
Setup Data to EBR Memory
—
3.64
0.74
—
—
4.37
0.88
—
—
5.10
1.03
—
ns
ns
ns
ns
ns
ns
ns
ns
tCOO_EBR
tSUDATA_EBR
tHDATA_EBR
tSUADDR_EBR
tHADDR_EBR
tSUWREN_EBR
tHWREN_EBR
—
—
—
-0.29
0.37
-0.29
0.37
-0.18
0.23
-0.35
0.44
-0.35
0.45
-0.22
0.28
-0.41
0.52
-0.41
0.52
-0.26
0.33
Hold Data to EBR Memory
—
—
—
Setup Address to EBR Memory
—
—
—
Hold Address to EBR Memory
—
—
—
Setup Write/Read Enable to EBR Memory
Hold Write/Read Enable to EBR Memory
—
—
—
—
—
—
3-16
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC Internal Switching Characteristics (Continued)
Over Recommended Operating Conditions
-5
-4
-3
Parameter
tSUCE_EBR
Description
Min. Max. Min. Max. Min. Max. Units
Clock Enable Setup Time to EBR Output
0.18
—
—
0.21
-0.17
—
—
—
0.25
-0.20
—
—
—
ns
ns
ns
Register
tHCE_EBR
Clock Enable Hold Time to EBR Output Register -0.14
Reset To Output Delay Time from EBR Output
tRSTO_EBR
—
1.47
1.76
2.05
Register
PLL Parameters
tRSTREC
Reset Recovery to Rising Clock
Reset Signal Setup Time
1.00
1.00
—
—
1.00
1.00
—
—
1.00
1.00
—
—
ns
ns
tRSTSU
DSP Block Timing2, 3
tSUI_DSP Input Register Setup Time
tHI_DSP
-0.38
0.71
3.31
0.71
5.54
0.71
—
—
—
-0.30
0.86
3.98
0.86
6.64
0.86
—
—
—
-0.23
1.00
4.64
1.00
7.75
1.00
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Input Register Hold Time
tSUP_DSP
tHP_DSP
tSUO_DSP
Pipeline Register Setup Time
Pipeline Register Hold Time
—
—
—
—
—
—
4
Output Register Setup Time
—
—
—
4
tHO_DSP
Output Register Hold Time
—
—
—
4
tCOI_DSP
Input Register Clock to Output Time
Pipeline Register Clock to Output Time
Output Register Clock to Output Time
AdSub Input Register Setup Time
AdSub Input Register Hold Time
7.50
4.66
1.47
—
9.00
5.60
1.77
—
10.50
6.53
2.06
—
4
tCOP_DSP
tCOO_DSP
tSUADSUB
tHADSUB
—
—
—
—
—
—
-0.38
0.71
-0.30
0.86
-0.23
1.00
—
—
—
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
3. DSP Block is configured in Multiply Add/Sub 18 x 18 Mode.
4. These parameters include the Adder Subtractor block in the path.
Timing v.G 0.30
3-17
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Timing Diagrams
PFU Timing Diagrams
Figure 3-6. Slice Single/Dual Port Write Cycle Timing
CK
WRE
AD
AD[3:0]
D
DI[1:0]
DO[1:0]
Old Data
D
Figure 3-7. Slice Single /Dual Port Read Cycle Timing
WRE
AD
AD[3:0]
DO[1:0]
Old Data
D
3-18
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
EBR Memory Timing Diagrams
Figure 3-8. Read/Write Mode (Normal)
CLKA
CSA
WEA
ADA
DIA
A0
A1
D1
A0
A1
A0
tSU tH
D0
tCO_EBR
tCO_EBR
tCO_EBR
D0
D0
D1
DOA
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-9. Read/Write Mode with Input and Output Registers
CLKA
CSA
WEA
ADA
A1
A0
A1
D1
A0
A0
t
t
H
SU
DIA
D0
t
t
COO_EBR
COO_EBR
DOA (Regs)
D1
D0
Mem(n) data from previous read
output is only updated during a read cycle
3-19
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Figure 3-10. Read Before Write (SP Read/Write on Port A, Input Registers Only)
CLKA
CSA
WEA
ADA
A0
A1
D1
A0
A1
A0
t
t
H
SU
D2
D3
D1
D0
DIA
t
t
t
t
t
ACCESS
ACCESS
ACCESS
ACCESS
ACCESS
old A0 Data
old A1 Data
D0
D1
DOA
D2
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-11. Write Through (SP Read/Write On Port A, Input Registers Only)
CLKA
CSA
WEA
Three consecutive writes to A0
ADA
A0
A1
D1
A0
t
t
H
SU
D2
D3
D2
D4
D0
DIA
t
t
t
t
ACCESS
ACCESS
ACCESS
ACCESS
Data from Prev Read
or Write
D0
D1
D3
DOA
D4
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
3-20
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC Family Timing Adders1, 2, 3
Over Recommended Operating Conditions
Buffer Type
Input Adjusters
LVDS25
Description
-5
-4
-3
Units
LVDS
0.41
0.41
0.50
0.41
0.41
0.41
0.37
0.37
0.37
0.40
0.40
0.37
0.37
0.46
0.46
0.39
0.39
0.43
0.43
0.38
0.38
0.40
0.37
0.07
0.07
0.00
0.07
0.24
1.27
0.07
0.50
0.50
0.60
0.49
0.49
0.49
0.44
0.44
0.44
0.48
0.48
0.44
0.44
0.55
0.55
0.47
0.47
0.51
0.51
0.45
0.45
0.48
0.44
0.09
0.09
0.00
0.09
0.29
1.52
0.09
0.58
0.58
0.70
0.57
0.57
0.57
0.52
0.52
0.52
0.56
0.56
0.51
0.51
0.64
0.64
0.55
0.55
0.60
0.60
0.53
0.53
0.56
0.51
0.10
0.10
0.00
0.10
0.33
1.77
0.10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLVDS25
BLVDS
LVPECL33
HSTL18_I
LVPECL
HSTL_18 class I
HSTL_18 class II
HSTL18_II
HSTL18_III
HSTL18D_I
HSTL18D_II
HSTL18D_III
HSTL15_I
HSTL_18 class III
Differential HSTL 18 class I
Differential HSTL 18 class II
Differential HSTL 18 class III
HSTL_15 class I
HSTL15_III
HSTL15D_I
HSTL15D_III
SSTL33_I
HSTL_15 class III
Differential HSTL 15 class I
Differential HSTL 15 class III
SSTL_3 class I
SSTL33_II
SSTL33D_I
SSTL33D_II
SSTL25_I
SSTL_3 class II
Differential SSTL_3 class I
Differential SSTL_3 class II
SSTL_2 class I
SSTL25_II
SSTL25D_I
SSTL25D_II
SSTL18_I
SSTL_2 class II
Differential SSTL_2 class I
Differential SSTL_2 class II
SSTL_18 class I
SSTL18D_I
LVTTL33
Differential SSTL_18 class I
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
PCI
Output Adjusters
LVDS25E
LVDS 2.5 E
0.12
-0.44
0.33
0.20
-0.10
0.06
0.15
-0.10
0.06
0.15
0.08
0.14
-0.53
0.40
0.24
-0.12
0.07
0.19
-0.12
0.07
0.19
0.10
0.17
-0.62
0.46
0.28
-0.14
0.08
0.22
-0.14
0.08
0.22
0.11
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDS25
LVDS 2.5
BLVDS25
BLVDS 2.5
LVPECL33
HSTL18_I
LVPECL 3.3
HSTL_18 class I
HSTL_18 class II
HSTL_18 class III
Differential HSTL 18 class I
Differential HSTL 18 class II
Differential HSTL 18 class III
HSTL_15 class I
HSTL18_II
HSTL18_III
HSTL18D_I
HSTL18D_II
HSTL18D_III
HSTL15_I
3-21
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC Family Timing Adders1, 2, 3 (Continued)
Over Recommended Operating Conditions
Buffer Type
HSTL15_II
Description
HSTL_15 class II
-5
-4
-3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.10
0.10
0.08
0.10
-0.05
0.40
-0.05
0.40
0.05
0.25
0.05
0.25
0.01
0.01
0.09
0.07
-0.03
0.36
0.28
0.09
0.07
-0.03
0.36
0.28
0.18
0.10
0.00
0.22
0.14
0.15
0.06
0.01
0.16
0.26
0.04
0.36
0.08
0.36
1.05
0.12
0.12
0.10
0.12
-0.06
0.48
-0.06
0.48
0.07
0.30
0.07
0.30
0.01
0.01
0.11
0.08
-0.04
0.43
0.33
0.11
0.08
-0.04
0.43
0.33
0.21
0.12
0.00
0.26
0.16
0.18
0.08
0.01
0.19
0.31
0.04
0.43
0.10
0.43
1.26
0.14
0.14
0.11
0.14
-0.07
0.56
-0.07
0.56
0.08
0.35
0.08
0.35
0.01
0.01
0.13
0.09
-0.05
0.51
0.39
0.13
0.09
-0.05
0.51
0.39
0.25
0.14
0.00
0.31
0.19
0.21
0.09
0.01
0.22
0.36
0.05
0.50
0.11
0.50
1.46
HSTL15_III
HSTL_15 class III
HSTL15D_I
Differential HSTL 15 class I
Differential HSTL 15 class III
SSTL_3 class I
HSTL15D_III
SSTL33_I
SSTL33_II
SSTL_3 class II
SSTL33D_I
Differential SSTL_3 class I
Differential SSTL_3 class II
SSTL_2 class I
SSTL33D_II
SSTL25_I
SSTL25_II
SSTL_2 class II
SSTL25D_I
Differential SSTL_2 class I
Differential SSTL_2 class II
SSTL_1.8 class I
SSTL25D_II
SSTL18_I
SSTL18D_I
Differential SSTL_1.8 class I
LVTTL 4mA drive
LVTTL33_4mA
LVTTL33_8mA
LVTTL33_12mA
LVTTL33_16mA
LVTTL33_20mA
LVCMOS33_4mA
LVCMOS33_8mA
LVTTL 8mA drive
LVTTL 12mA drive
LVTTL 16mA drive
LVTTL 20mA drive
LVCMOS 3.3 4mA drive
LVCMOS 3.3 8mA drive
LVCMOS33_12mA LVCMOS 3.3 12mA drive
LVCMOS33_16mA LVCMOS 3.3 16mA drive
LVCMOS33_20mA LVCMOS 3.3 20mA drive
LVCMOS25_4mA
LVCMOS25_8mA
LVCMOS 2.5 4mA drive
LVCMOS 2.5 8mA drive
LVCMOS25_12mA LVCMOS 2.5 12mA drive
LVCMOS25_16mA LVCMOS 2.5 16mA drive
LVCMOS25_20mA LVCMOS 2.5 20mA drive
LVCMOS18_4mA
LVCMOS18_8mA
LVCMOS 1.8 4mA drive
LVCMOS 1.8 8mA drive
LVCMOS18_12mA LVCMOS 1.8 12mA drive
LVCMOS18_16mA LVCMOS 1.8 16mA drive
LVCMOS15_4mA
LVCMOS15_8mA
LVCMOS12_2mA
LVCMOS12_6mA
LVCMOS12_4mA
PCI33
LVCMOS 1.5 4mA drive
LVCMOS 1.5 8mA drive
LVCMOS 1.2 2mA drive
LVCMOS 1.2 6mA drive
LVCMOS 1.2 4mA drive
PCI33
1. Timing adders are characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Conditions table of this document.
3. All other standards according to the appropriate specification.
Timing v.G 0.30
3-22
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter
fIN
Description
Conditions
Min.
25
Typ.
—
Max.
420
420
210
840
—
Units
MHz
MHz
MHz
MHz
MHz
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
fOUT
fOUT2
fVCO
fPFD
25
—
0.195
420
25
—
—
Phase Detector Input Frequency
—
AC Characteristics
Default Duty Cycle
Elected3
tDT Output Clock Duty Cycle
45
50
55
%
4
tPH
Output Phase Accuracy
Output Clock Period Jitter
—
—
—
—
—
—
—
—
250
—
—
—
—
—
0.05
+/- 125
0.02
+/- 200
—
UI
ps
fOUT >= 100MHz
1
tOPJIT
fOUT < 100MHz
—
UIPP
ps
tSK
tW
tLOCK
tPA
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Divider ratio = integer
At 90% or 10%3
—
1
ns
2
—
150
µs
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width
100
—
450
ps
tIPJIT
+/- 200
10
ps
tFBKDLY
tHI
—
ns
90% to 90%
10% to 10%
0.5
0.5
10
—
ns
tLO
—
ns
tRST
—
ns
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. Relative to CLKOP.
Timing v.G 0.30
3-23
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC sysCONFIG Port Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Units
sysCONFIG Byte Data Flow
tSUCBDI
tHCBDI
tCODO
tSUCS
tHCS
Byte D[0:7] Setup Time to CCLK
Byte D[0:7] Hold Time to CCLK
7
1
—
—
12
—
—
—
—
12
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock to Dout in Flowthrough Mode
CS[0:1] Setup Time to CCLK
CS[0:1] Hold Time to CCLK
Write Signal Setup Time to CCLK
Write Signal Hold Time to CCLK
CCLK to BUSY Delay Time
—
7
1
tSUWD
tHWD
7
1
tDCB
—
—
tCORD
Clock to Out for Read Data
sysCONFIG Byte Slave Clocking
tBSCH
Byte Slave Clock Minimum High Pulse
6
9
—
—
—
—
—
12
ns
ns
ns
ns
ns
ns
tBSCL
Byte Slave Clock Minimum Low Pulse
Byte Slave Clock Cycle Time
tBSCYC
tSUSCDI
tHSCDI
tCODO
15
7
Din Setup time to CCLK Slave Mode
Din Hold Time to CCLK Slave Mode
Clock to Dout in Flowthrough Mode
1
—
sysCONFIG Serial (Bit) Data Flow
tSUMCDI Din Setup time to CCLK Master Mode
tHMCDI Din Hold Time to CCLK Master Mode
sysCONFIG Serial Slave Clocking
tSSCH Serial Slave Clock Minimum High Pulse
tSSCL Serial Slave Clock Minimum Low Pulse
sysCONFIG POR, Initialization and Wake Up
7
1
—
—
ns
ns
6
6
—
—
ns
ns
tICFG
Minimum Vcc to INIT High
—
—
—
25
—
—
—
—
50
2
ms
us
ns
ns
ms
ns
ns
ns
tVMC
Time from tICFG to Valid Master Clock
Program Pin Pulse Rejection
tPRGMRJ
tPRGM
tDINIT
8
PROGRAMN Low Time to Start Configuration
INIT Low Time
—
1
tDPPINIT
tDINITD
tIODISS
Delay Time from PROGRAMN Low to INIT Low
Delay Time from PROGRAMN Low to DONE Low
User I/O Disable from PROGRAMN Low
37
37
35
User I/O Enabled Time from CCLK Edge During Wake Up
Sequence
tIOENSS
—
25
ns
tMWC
Additional Wake Master Clock Signals after Done Pin High
CFG to INITN Setup Time
120
100
100
—
—
—
cycles
ns
tSUCFG
tHCFG
CFG to INITN Hold Time
ns
sysCONFIG SPI Port
tCFGX
Init High to CCLK Low
—
—
0
80
2
ns
us
ns
ns
tCSSPI
Init High to CSSPIN Low
tCSCCLK
tSOCDO
CCLK Low Before CSSPIN Low
CCLK Low to Output Valid
-
—
15
3-24
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC sysCONFIG Port Timing Specifications (Continued)
Over Recommended Operating Conditions
Parameter
tSOE
Description
Min.
Typ.
Max.
Units
ns
CSSPIN Active Setup Time
300
—
600+6cyc
25
tCSPID
CSSPIN Low to First Clock Edge Setup Time
Max Frequency for SPI
300+3cyc
ns
fMAXSPI
tSUSPI
—
7
MHz
ns
SOSPI Data Setup Time Before CCLK
SOSPI Data Hold Time After CCLK
—
tHSPI
1
—
ns
Timing v.G 0.30
Master Clock
Clock Mode
2.5MHz
Min.
1.75
3.78
7
Typ.
2.5
5.4
10
15
20
26
30
34
41
45
51
55
60
—
Max.
3.25
7.02
13
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
5 MHz
10 MHz
15 MHz
10.5
14
19.5
26
20 MHz
25 MHz
18.2
21
33.8
39
30 MHz
35 MHz
23.8
28.7
31.5
35.7
38.5
42
44.2
53.3
58.5
66.3
71.5
78
40 MHz
45 MHz
50 MHz
55 MHz
60 MHz
Duty Cycle
Timing v.G 0.30
40
60
3-25
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Figure 3-12. sysCONFIG Parallel Port Read Cycle
tBSCYC
tBSCH
tBSCL
CCLK1
tSUCS
tHCS
CS1N
CSN
tSUWD
tHWD
WRITEN
BUSY
tDCB
tCORD
Byte 1
Byte 0
Byte 2
Byte n
D[0:7]
1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK.
Figure 3-13. sysCONFIG Parallel Port Write Cycle
tBSCYC
tBSCH
tBSCL
CCLK 1
CS1N
tSUCS
tHCS
CSN
tSUWD
tHWD
WRITEN
tDCB
BUSY
D[0:7]
tHCBDI
Byte 1
tSUCBDI
Byte 0
Byte 2
Byte n
1. In Master Parallel Mode the FPGA provides CCLK. In Slave Parallel Mode the external device provides CCLK.
3-26
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Figure 3-14. sysCONFIG Master Serial Port Timing
CCLK (output%
tHMCDI
tSUMCDI
DIN
tCODO
DOUT
Figure 3-15. sysCONFIG Slave Serial Port Timing
tSSCL
tSSCH
CCLK (input%
tHSCDI
tSUSCDI
DIN
tCODO
DOUT
Figure 3-16. Power-On-Reset (POR) Timing
1
V
/V
CC CCAUX
tICFG
INITN
DONE
CCLK 2
tVMC
tHCFG
tSUCFG
CFG[2:0] 3
Valid
1. Time taken from V
or V
, whichever is the last to reach its V
.
CC
CCAUX
MIN
2. Device is in a Master Mode.
3. The CFG pins are normally static (hard wired%.
3-27
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Figure 3-17. Configuration from PROGRAMN Timing
tPRGMRJ
PROGRAMN
tDPPINIT
tDINIT
INITN
tDINITD
DONE
CCLK
tHCFG
tSUCFG
Valid
CFG[2:0]
tIODISS
USER I/O
1. The CFG pins are normally static (hard wired%
Figure 3-18. Wake-Up Timing
PROGRAMN
INITN
Wake-Up
DONE
tMWC
CCLK
tIOENSS
USER I/O
Figure 3-19. sysCONFIG SPI Port Sequence
Capture
CFGx
Capture
OPCODE
Clock 127
Clock 128
t
ICFG
VCC
t
PRGM
PROGRAMN
t
DINITD
DONE
INITN
t
DPPINIT
t
DINIT
t
t
CSPID
CSSPI
t
CSSPIN
CCLK
CFGX
0
1
2
3
4
5
6
7
t
CSCCLK
t
t
SOCDO
SOE
D6
SISPI/BUSY
D7/SPID0
D7
D5 D4 D3 D2 D1 D0
0
Valid Bitstream
XXX
3-28
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
JTAG Port Timing Specifications
Over Recommended Operating Conditions
Symbol
fMAX
Parameter
Min
—
40
20
20
8
Max
25
—
Units
MHz
ns
TCK clock frequency
tBTCP
TCK [BSCAN] clock pulse width
tBTCPH
tBTCPL
TCK [BSCAN] clock pulse width high
—
ns
TCK [BSCAN] clock pulse width low
—
ns
tBTS
TCK [BSCAN] setup time
—
ns
tBTH
TCK [BSCAN] hold time
10
50
—
—
—
8
—
ns
tBTRF
TCK [BSCAN] rise/fall time
—
mV/ns
ns
tBTCO
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
10
10
10
—
tBTCODIS
tBTCOEN
tBTCRS
tBTCRH
tBUTCO
tBTUODIS
tBTUPOEN
Timing v.G 0.30
ns
ns
ns
BSCAN test capture register hold time
25
—
—
—
—
ns
BSCAN test update register, falling edge of clock to valid output
BSCAN test update register, falling edge of clock to valid disable
BSCAN test update register, falling edge of clock to valid enable
25
25
25
ns
ns
ns
Figure 3-20. JTAG Port Timing Waveforms
TMS
TDI
t
BTS
t
BTH
t
t
t
BTCP
BTCPL
BTCPH
TCK
TDO
t
t
BTCODIS
t
BTCO
BTCOEN
Valid Data
Valid Data
t
BTCRH
t
BTCRS
Data to be
captured
from I/O
Data Captured
t
t
t
BTUPOEN
BUTCO
BTUODIS
Data to be
driven out
to I/O
Valid Data
Valid Data
3-29
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Switching Test Conditions
Figure 3-21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 3-6.
Figure 3-21. Output Test Load, LVTTL and LVCMOS Standards
VT
R1
DUT
Test Point
CL*
*CL Includes Test Fixture and Probe Capacitance
Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
R1
CL
Timing Ref.
LVCMOS 3.3 = 1.5V
VT
—
LVCMOS 2.5 = VCCIO/2
LVCMOS 1.8 = VCCIO/2
LVCMOS 1.5 = VCCIO/2
LVCMOS 1.2 = VCCIO/2
—
LVTTL and other LVCMOS settings (L -> H, H -> L)
0pF
—
—
—
LVCMOS 2.5 I/O (Z -> H)
LVCMOS 2.5 I/O (Z -> L)
LVCMOS 2.5 I/O (H -> Z)
LVCMOS 2.5 I/O (L -> Z)
V
CCIO/2
VOL
VOH
VOL
VOH
VCCIO/2
188¾
0pF
VOH - 0.15
VOL + 0.15
Note: Output test conditions for all other interfaces are determined by the respective standards.
3-30
LatticeECP/EC Family Data Sheet
Pinout Information
September 2012
Data Sheet
Signal Descriptions
Signal Name
I/O
Description
General Purpose
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify
Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected.
P[Edge] [Row/Column Number*]_[A/B]
I/O
Some of these user-programmable pins are shared with special function
pins. These pin when not used as special purpose pins can be programmed
as I/Os for user logic.
During configuration the user-programmable I/Os are tri-stated with an inter-
nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-
age pin), it is also tri-stated with an internal pull-up resistor enabled after
configuration.
GSRN
NC
I
Global RESET signal (active low). Any I/O pin can be GSRN.
No connect.
—
—
—
GND
VCC
Ground. Dedicated pins.
Power supply pins for core logic. Dedicated pins.
Auxiliary power supply pin. It powers all the differential and referenced input
buffers. Dedicated pins.
VCCAUX
VCCIOx
REF1_x, VREF2_x
—
—
—
Power supply pins for I/O bank x. Dedicated pins.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as VREF inputs. When not used, they may be used as I/O pins.
V
XRES
—
—
10K ohm +/-1% resistor must be connected between this pad and ground.
Power supply pin for PLL.þApplicable to ECP/EC33 device.
VCCPLL
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_PLL[T, C]_IN_A
[LOC][num]_PLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
I
I
I
I
Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
function number. Any pad can be configured to be output.
[LOC]DQS[num]
Test and Programming (Dedicated pins)
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during configuration.
TMS
I
I
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
TCK
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
4-1
Pinout Information_02.6
Pinout Information
LatticeECP/EC Family Data Sheet
Signal Descriptions (Cont.)
Signal Name
I/O
Description
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
TDI
I
TDO
VCCJ
O
Output pin. Test Data out pin used to shift data out of device using 1149.1.
VCCJ - The power supply pin for JTAG Test Access Port.
—
Configuration Pads (used during sysCONFIG)
Mode pins used to specify configuration modes values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
CFG[2:0]
I
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
INITN
I/O
I
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
PROGRAMN
DONE
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
I/O
CCLK
I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
I/O Read control command in SPI3 or SPIX mode.
BUSY/SISPI
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
CSN
I
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
CS1N
I
WRITEN
I
Write Data on Parallel port (Active low).
D[7:0]/SPID[0:7]
I/O sysCONFIG Port Data I/O.
Output for serial configuration data (rising edge of CCLK) when using sys-
CONFIG port.
DOUT/CSON
O
Input for serial configuration data (clocked with CCLK) when using sysCON-
I/O FIG port. During configuration, a pull-up is enabled. Output when used in
SPI/SPIX modes.
DI/CSSPIN
4-2
Pinout Information
LatticeECP/EC Family Data Sheet
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated
with DQS Strobe
DDR Strobe (DQS) and
Data (DQ) Pins
PIO Within PIC
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DQ
DQ
P[Edge] [n-4]
DQ
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
DQ
DQ
DQ
DQ
DQ
[Edge]DQSn
DQ
DQ
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
DQ
DQ
DQ
DQ
DQ
Notes:
1. “n” is a Row/Column PIC number
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of
data. In some packages, all the potential DDR data (DQ) pins may not be available.
3. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descrip-
tions table.
4-3
Pinout Information
LatticeECP/EC Family Data Sheet
Pin Information Summary
LFEC1
LFEC3
LFECP6/EC6
LFECP/EC10
100- 144- 208- 100- 144- 208- 256- 144- 208- 256- 484- 208- 256- 484-
TQFP TQFP PQFP TQFP TQFP PQFP fpBGA TQFP PQFP fpBGA fpBGA PQFP fpBGA fpBGA
Pin Type
Single Ended User
67
29
97
46
112
56
67
29
97
46
145
72
160
80
97
46
147
72
195
97
224
112
147
72
195
97
288
144
I/O
Differential Pair User
I/O
Dedicated 13
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
48
5
13
56
5
13
56
5
13
56
5
Configu-
ration
Muxed
48
5
TAP
Dedicated (total
without supplies)
80
110
160
80
110
160
208
110
160
208
373
160
208
373
VCC
2
2
0
1
1
1
1
1
1
1
1
8
0
3
2
3
2
2
4
0
1
1
2
1
1
1
1
2
8
0
3
4
3
4
10
4
4
2
4
4
10
2
20
12
0
6
4
10
2
20
12
0
VCCAUX
VCCPLL
Bank0
Bank1
Bank2
0
0
0
0
0
0
0
0
0
0
2
2
2
3
2
2
3
2
4
3
2
4
2
2
2
2
2
2
2
2
4
2
2
4
1
1
2
2
2
1
2
2
4
2
2
4
Bank3
VCCIO
2
2
2
2
2
2
2
2
4
2
2
4
Bank4
2
2
2
2
2
2
2
2
4
2
2
4
Bank5
Bank6
2
2
2
2
2
2
3
2
4
3
2
4
2
2
2
2
2
2
2
2
4
2
2
4
Bank7
1
1
2
2
2
1
2
2
4
2
2
4
GND, GND0-GND7
NC
13
2
13
51
13
2
16
9
20
35
14
0
18
4
20
0
44
139
20
0
20
0
44
75
Bank 0
11/5 14/7 16/8 11/5 14/7 26/13 32/16 14/7 26/13 32/16 32/16 26/13 32/16 48/24
11/5 13/6 16/8 11/5 13/6 16/8 16/8 13/6 17/8 18/9 32/16 17/8 18/9 32/16
Bank 1
Single
Ended/
Differen-
tial I/O
Pair per
Bank
Bank 2
3/1
8/4 13/6 16/8
12/4 14/6 16/8 12/4 14/6 16/8 16/8 14/6 17/8 17/8 32/16 17/8 17/8 32/16
8/4
8/4
3/1
8/4
14/7 16/8
8/4
14/7 16/8 16/8 14/7 16/8 32/16
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
8/4 13/6 16/8 16/8 13/6 16/8 32/16 32/16 16/8 32/16 32/16
9/4 13/6 16/8
5/2 14/7 16/8
9/4 13/6 26/13 32/16 13/6 26/13 32/16 32/16 26/13 32/16 48/24
5/2 14/7 16/8 16/8 14/7 16/8 32/16 32/16 16/8 32/16 32/16
8/4
1
8/4
1
8/4
1
8/4
1
8/4
1
15/7 16/8
8/4
1
15/7 16/8 16/8 15/7 16/8 32/16
VCCJ
1
1
1
1
1
1
1
1
Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not
bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
4-4
Pinout Information
LatticeECP/EC Family Data Sheet
Pin Information Summary (Cont.)
LFECP/EC15
LFECP20/EC20
LFECP/EC33
Pin Type
Single Ended User I/O
Differential Pair User I/O
256-fpBGA
484-fpBGA
484-fpBGA
672-fpBGA
484-fpBGA
672-fpBGA
195
97
352
176
13
360
180
13
400
200
13
360
180
13
496
248
13
Dedicated
Muxed
13
Configuration
TAP
56
56
56
56
56
56
5
5
5
5
5
5
Dedicated (total without supplies)
208
10
373
20
373
20
509
32
373
16
509
28
VCC
VCCAUX
VCCPLL
Bank0
Bank1
Bank2
2
12
12
20
12
20
0
0
0
0
4
4
2
4
4
6
4
6
2
4
4
6
4
6
2
4
4
6
4
6
Bank3
2
4
4
6
4
6
VCCIO
Bank4
2
4
4
6
4
6
Bank5
2
4
4
6
4
6
Bank6
2
4
4
6
4
6
Bank7
2
4
4
6
4
6
GND, GND0-GND7
20
44
44
63
44
63
NC
0
11
3
96
3
0
Bank0
Bank1
Bank2
32/16
18/9
16/8
32/16
17/8
32/16
32/16
16/8
1
48/24
48/24
40/20
40/20
48/24
48/24
40/20
40/20
1
48/24
48/24
40/20
44/22
48/24
48/24
44/22
40/20
1
64/32
48/24
40/20
48/24
48/24
64/32
48/24
40/20
1
48/24
48/24
40/20
44/22
48/24
48/24
44/22
40/20
1
64/32
64/32
56/28
64/32
64/32
64/32
64/32
56/28
1
Single Ended/
Differential I/O
Pair per Bank
Bank3
Bank4
Bank5
Bank6
Bank7
VCCJ
Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not
bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
4-5
Pinout Information
LatticeECP/EC Family Data Sheet
Power Supply and NC Connections
Signals
100 TQFP
144 TQFP
208 PQFP
256 fpBGA
VCC
12, 64
EC1, EC3: 13, 92, 99
ECP/EC6: 11, 13, 92, 99 ECP/EC6: 24, 26, 128,
EC1, EC3: 26, 128, 135 E12, E5, E8, M12, M5,
M9, F6, F11, L11, L6
135
ECP/EC10: 5, 24, 26,
128, 135, 152
F7, F8
VCCIO0
100
136, 143
EC1: 187, 208
EC3, ECP/EC6, ECP/
EC10: 187, 197, 208
F9, F10
VCCIO1
VCCIO2
86
73
110, 125
108
157, 176
G11, H11
EC1: 155
EC3, ECP/EC6, ECP/
EC10: 145, 155
J11, K11
L9, L10
L7, L8
VCCIO3
VCCIO4
VCCIO5
56
38
26
73, 84
55, 71
38, 44
106, 120
85, 104
EC1: 53, 74
EC2, ECP/EC6, ECP/
EC10: 53, 64, 74
J6, K6
VCCIO6
VCCIO7
24
2
24, 36
1
37, 51
G6, H6
EC1: 2
EC3, ECP/EC6, ECP/
EC10: 2, 13
L4
VCCJ
18
19
32
B15, R2
VCCAUX
37, 87
54, 126
EC1: 84, 177
EC3, ECP/EC6, ECP/
EC10: 22, 84, 136, 177
—
VCCPLL
—
—
—
A1, A16, G10, G7, G8,
G9, H10, H7, H8, H9,
J10, J7, J8, J9, K10, K7,
K8, K9, T1, T16
GND, GND0-GND7 1, 14, 25, 35, 51, 68, 74, EC1, EC3: 15, 28, 37,
EC1: 1, 28, 41, 52, 82,
93, 105, 116, 132, 134,
156, 168, 179
EC3: 1, 28, 41, 52, 72,
82, 93, 105, 116, 132,
89
52, 63, 72, 80, 96, 98,
109, 117, 128, 144
ECP/EC6: 12, 15, 28,
37, 52, 63, 72, 80, 96,
98, 109, 117, 128, 144 134, 138, 156, 168, 179,
189
ECP/EC6: 1, 18, 25, 28,
41, 52, 72, 82, 93, 105,
116, 132, 134, 138, 156,
168, 179, 189
ECP/EC10: 1, 6, 18, 25,
28, 41, 52, 72, 82, 93,
105, 116, 132, 134, 138,
151, 156, 168, 179, 189
EC3: G5, H5, F2, F1, H4,
H3, G2, G1, J4, J3, J5,
K5, H2, H1, J2, J1, R12,
H16, H15, G16, G15,
NC
—
EC1, EC3: 11, 12
ECP6/EC6: None
EC1: 5, 6, 7, 8, 9, 10, 11,
12, 13, 14, 18, 22, 24,
25, 54, 55, 56, 57, 58,
59, 60, 61, 62, 63, 64,
72, 103, 136, 138, 144, K12, J12, J14, J15, F16,
F15, J13, H13, H14, G14,
E16, E15, B13, C13
ECP/EC10: None
145, 146, 147, 148, 149,
150, 151, 152, 158, 189,
197, 198, 199, 200, 201,
202, 203, 204, 205, 206,
207
ECP/EC15: None
EC3: 5, 6, 18, 24, 25,
103, 151, 152, 158
ECP/EC6: 5, 6, 151, 152
ECP/EC10: None
4-6
Pinout Information
LatticeECP/EC Family Data Sheet
Power Supply and NC Connections (Cont.)
Signals
484 fpBGA
672 fpBGA
VCC
J16, J7, K16, K17, K6, K7, L17, L6, M17, M6, N16, H10, H11, H16, H17, H18, H19, H8, H9, J18, J9,
N17, N6, N7, P16, P7, J6, J17, P6, P17
K8, L19, M19, N7, R20, R7, T19, V18, V8, V9,
W10, W11, W16, W17, W18, W19, W8, W9, K19,
L8, U19, U8
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCJ
G11, H10, H11, H9
G12, H12, H13, H14
J15, K15, L15, L16
M15, M16, N15, P15
R12, R13, R14, T12
R10, R11, R9, T11
M7, M8, N8, P8
J8, K8, L7, L8
H12, H13, J10, J11, J12, J13
H14, H15, J14, J15, J16, J17
K17, K18, L18, M18, N18, N19
P18, P19, R18, R19, T18, U18
V14, V15, V16, V17, W14, W15
V10, V11, V12, V13, W12, W13
P8, P9, R8, R9, T9, U9
K9, L9, M8, M9, N8, N9
U6
U2
VCCAUX
G15, G16, G7, G8, H16, H7, R16, R7, T15, T16, G13, H20, H7, J19, J8, K7, L20, M20, M7, N20,
T7, T8
P20, P7, T20, T7, T8, V19, V7, W20, Y13, Y7
VCCPLL
ECP/EC20: None
ECP/EC33: J6, J17, P6, P17
ECP/EC20: None
ECP/EC33: K19, L8, U19, U8
GND, GND0-GND7 A1, A22, AB1, AB22, H15, H8, J10, J11, J12, J13, K10, K11, K12, K13, K14, K15, K16, L10, L11,
J14, J9, K10, K11, K12, K13, K14, K9, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12,
L12, L13, L14, L9, M10, M11, M12, M13, M14, M9, M13, M14, M15, M16, M17, N10, N11, N12, N13,
N10, N11, N12, N13, N14, N9, P10, P11, P12,
P13, P14, P9, R15, R8
N14, N15, N16, N17, P10, P11, P12, P13, P14,
P15, P16, P17, R10, R11, R12, R13, R14, R15,
R16, R17, T10, T11, T12, T13, T14, T15, T16,
T17, U10, U11, U12, U13, U14, U15, U16, U17
NC
ECP/EC6: C3, B2, E5, F5, D3, C2, F4, G4, E3, D2, ECP/EC20: E5, D5, F4, F5, C3, D3, C2, B2, H6,
B1, C1, F3, E2, G5, H6, G3, H4, J5, H5, F2, F1,
E1, D1, R6, P5, P3, P4, R1, R2, R5, R4, T1, T2,
R3, T3, V7, T6, V8, U7, W5, U6, AA3, AB3, Y6,
J7, G5, H5, H3, J3, H2, J2, AA2, AA3, W5, Y5, Y6,
W7, AA4, AB3, AC2, AC3, AA5, AB5, AD3, AD2,
AE1, AD1, AD19, AD20, AC19, AB19, AD21,
V6, AA5, W6, Y5, Y4, AA4, AB4, W16, U15, V16, AC20, AF25, AE25, AB21, AB20, AE24, AD23,
U16, Y17, V17, AB20, AA19, Y16, W17, AA20,
Y19, Y18, W18, T17, U17, T18, R17, R19, R18,
U22, T22, R21, R22, P20, N20, P19, P18, E21,
D22, G21, G20, J18, H19, J19, H20, H17, H18,
D21, C22, G19, G18, F20, F19, E20, D20, C21,
C20, F18, E18, B22, B21, G17, F17, D18, C18,
C19, B20, D17, C16, B19, A20, E17, C17, F16,
E16, F15, D16, A4, B4, C4, C5, D6, B5, E6, C6,
A3, B3, F6, D5, F7, E8, G6, E7, A2, AB2, A21
ECP/EC10: G5, H6, G3, H4, J5, H5, F2, F1, R6,
P5, P3, P4, R2, R1, R5, R4, T1, T2, R3, T3, W16,
U15, V16, U16, Y17, V17, AB20, AA19, Y16, W17,
AA20, Y19, Y18, W18, T17, U17, T18, R17, R19,
R18, U22, T22, R21, R22, P20, N20, P19, P18,
G21, G20, J18, H19, J19, H20, H17, H18, G17,
F17, D18, C18, C19, B20, D17, C16, B19, A20,
E17, C17, F16, E16, F15, D16, A2, AB2, A21
ECP/EC15: T1, T2, R3, T3, T18, R17, R19, R18,
A2, AB2, A21
AD22, AC21, AC22, AB22, AD24, AD25, AE26,
AD26, Y20, Y19, AA23, AA22, AB23, AB24, Y21,
AA21, Y23, Y22, AA24, Y24, J21, J22, J23, H22,
G26, F26, E26, E25, F24, F23, E24, D24, E22,
F22, E21, D22, G20, F20, D21, C21, C23, C22,
B23, C24, D20, E19, B25, B24, B26, A25, C20,
C19
ECP/EC33: None
ECP/EC20: A2, AB2, A21
ECP/EC33: A2, AB2, A21
4-7
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3 Logic Signal Connections: 100 TQFP
LFEC1
LFEC3
LVDS
Pin
Number
Pin
Function
Pin
Function
Bank
LVDS
Dual Function
Bank
Dual Function
GND0
GND7
GND0
GND7
1*
-
-
2
VCCIO7
PL2A
PL2B
PL3A
PL3B
PL4A
PL4B
PL5A
PL5B
XRES
VCC
7
7
7
7
7
7
7
7
7
6
-
VCCIO7
PL2A
PL2B
PL7A
PL7B
PL8A
PL8B
PL9A
PL9B
XRES
VCC
7
7
7
7
7
7
7
7
7
6
-
3
T
C
T
VREF2_7
VREF1_7
T
C
T
VREF2_7
VREF1_7
4
5
6
C
T
C
T
7
8
C
T
C
T
9
PCLKT7_0
PCLKC7_0
PCLKT7_0
PCLKC7_0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C
C
TCK
6
-
TCK
6
-
GND
GND
TDI
6
6
6
6
6
6
6
6
6
6
TDI
6
6
6
6
6
6
6
6
6
6
TMS
TMS
TDO
TDO
VCCJ
PL7A
PL7B
PL8A
PL8B
PL14A
VCCIO6
VCCJ
PL11A
PL11B
PL12A
PL12B
PL18A
VCCIO6
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
VREF1_6
T
C
T
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
LUM0_PLLC_FB_A
VREF1_6
C
C
GND5
GND6
GND5
GND6
25*
-
-
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VCCIO5
PB2A
5
5
5
5
5
5
5
5
5
5
5
-
VCCIO5
PB10A
PB10B
PB11A
PB11B
PB14A
PB16A
PB16B
PB17A
GND5
5
5
5
5
5
5
5
5
5
5
5
-
T
C
T
T
C
T
PB2B
PB3A
PB3B
C
C
PB6A
BDQS6
VREF2_5
VREF1_5
PCLKT5_0
BDQS14
VREF2_5
VREF1_5
PCLKT5_0
PB8A
T
C
T
T
C
T
PB8B
PB9A
GND5
PB9B
C
PCLKC5_0
PB17B
VCCAUX
VCCIO4
PB18A
PB18B
C
PCLKC5_0
VCCAUX
VCCIO4
PB10A
PB10B
4
4
4
4
4
4
T
WRITEN
CS1N
T
WRITEN
CS1N
C
C
4-8
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3 Logic Signal Connections: 100 TQFP (Cont.)
LFEC1
LFEC3
Pin
Number
Pin
Function
Pin
Function
Bank
LVDS
Dual Function
VREF1_4
CSN
Bank
LVDS
Dual Function
VREF1_4
CSN
41
42
43
44
45
46
47
48
49
50
PB11A
PB11B
PB12B
PB13A
PB13B
PB14A
PB14B
PB15B
PB16B
PB17B
4
4
4
4
4
4
4
4
4
4
T
PB19A
PB19B
PB20B
PB21A
PB21B
PB22A
PB22B
PB23B
PB24B
PB25B
4
4
4
4
4
4
4
4
4
4
T
C
C
D0/SPID7
D2/SPID5
D1/SPID6
BDQS14
D0/SPID7
D2/SPID5
D1/SPID6
BDQS22
T
C
T
T
C
T
C
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
C
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
GND3
GND4
GND3
GND4
51*
-
-
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
PR10B
PR10A
PR9B
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
C
T
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
PR14B
PR14A
PR13B
PR13A
VCCIO3
PR12B
PR12A
PR11B
PR11A
CFG2
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
C
T
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
PR9A
VCCIO3
PR8B
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
PR8A
PR7B
PR7A
CFG2
CFG1
CFG1
CFG0
CFG0
VCC
VCC
PROGRAMN
CCLK
3
3
3
-
PROGRAMN
CCLK
3
3
3
-
INITN
INITN
GND
GND
DONE
PR5B
3
2
2
2
2
2
1
1
1
1
1
1
1
DONE
PR9B
3
2
2
2
2
2
1
1
1
1
1
1
1
C
T
PCLKC2_0
PCLKT2_0
VREF1_2
C
T
PCLKC2_0
PCLKT2_0
VREF1_2
PR5A
PR9A
PR2B
PR2B
VCCIO2
GND2
PT17B
PT17A
PT14B
PT14A
PT13A
PT12B
PT12A
VCCIO2
GND2
C
T
C
T
PT25B
PT25A
PT22B
PT22A
PT21A
PT20B
PT20A
C
T
C
T
TDQS14
TDQS22
C
T
C
T
4-9
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3 Logic Signal Connections: 100 TQFP (Cont.)
LFEC1
LFEC3
Pin
Number
Pin
Function
Pin
Function
Bank
LVDS
Dual Function
VREF2_1
Bank
LVDS
Dual Function
VREF2_1
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PT11B
PT11A
PT10B
PT10A
VCCIO1
VCCAUX
PT9B
1
1
1
1
1
-
C
T
C
T
PT19B
PT19A
PT18B
PT18A
VCCIO1
VCCAUX
PT17B
GND0
1
1
1
1
1
-
C
T
C
T
VREF1_1
VREF1_1
0
0
0
0
0
0
0
0
0
0
0
0
0
C
PCLKC0_0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
PCLKC0_0
GND0
PT9A
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
PT17A
PT16B
PT16A
PT15B
PT14B
PT14A
PT12B
PT12A
PT10B
PT10A
VCCIO0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
PT8B
PT8A
PT7B
PT6B
C
T
C
T
C
T
C
T
C
T
C
T
PT6A
TDQS6
TDQS14
PT4B
PT4A
PT2B
PT2A
VCCIO0
*Double bonded to the pin.
4-10
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP
LFEC1
LFEC3
LFECP6/EC6
Pin
LVD
S
LVD
S
LVD
S
Number Pin Function Bank
Dual Function
Pin Function Bank
Dual Function
Pin Function Bank
Dual Function
1
VCCIO7
PL2A
PL2B
PL3A
PL3B
PL4A
PL4B
PL5A
PL5B
XRES
NC
7
7
7
7
7
7
7
7
7
6
-
VCCIO7
PL2A
PL2B
PL7A
PL7B
PL8A
PL8B
PL9A
PL9B
XRES
NC
7
7
7
7
7
7
7
7
7
6
-
VCCIO7
PL2A
7
7
7
7
7
7
7
7
7
6
-
2
T
C
T
VREF2_7
VREF1_7
T
C
T
VREF2_7
VREF1_7
T
C
T
VREF2_7
VREF1_7
3
PL2B
4
PL7A
5
C
T
C
T
PL7B
C
T
6
PL8A
7
C
T
C
T
PL8B
C
T
8
PCLKT7_0
PCLKC7_0
PCLKT7_0
PCLKC7_0
PL9A
PCLKT7_0
PCLKC7_0
9
C
C
PL9B
C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
XRES
VCC
NC
-
NC
-
GND
-
VCC
-
VCC
-
VCC
-
TCK
6
-
TCK
6
-
TCK
6
-
GND
GND
GND
TDI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TDI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TDI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TMS
TMS
TMS
TDO
TDO
TDO
VCCJ
PL7A
PL7B
PL8A
PL8B
VCCIO6
PL9A
PL9B
PL10A
GND6
PL10B
PL11A
PL11B
PL12A
PL12B
PL14A
PL14B
VCCIO6
VCCJ
PL11A
PL11B
PL12A
PL12B
VCCIO6
PL13A
PL13B
PL14A
GND6
PL14B
PL15A
PL15B
PL16A
PL16B
PL18A
PL18B
VCCIO6
VCCJ
PL20A
PL20B
PL21A
PL21B
VCCIO6
PL22A
PL22B
PL23A
GND6
PL23B
PL24A
PL24B
PL25A
PL25B
PL27A
PL27B
VCCIO6
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
C
C
C
T
C
T
T
C
T
T
C
T
C
T
C
T
C
T
LDQS11
LDQS15
LDQS24
C
T
C
T
C
T
C
T
C
T
C
T
VREF1_6
VREF2_6
VREF1_6
VREF2_6
VREF1_6
VREF2_6
C
C
C
GND5
GND6
GND5
GND6
GND5
GND6
37*
-
-
-
38
39
40
41
42
43
44
45
46
47
48
49
VCCIO5
PB2A
PB2B
PB3A
PB3B
PB5B
VCCIO5
PB6A
PB6B
PB7A
PB7B
PB8A
5
5
5
5
5
5
5
5
5
5
5
5
VCCIO5
PB10A
PB10B
PB11A
PB11B
PB13B
VCCIO5
PB14A
PB14B
PB15A
PB15B
PB16A
5
5
5
5
5
5
5
5
5
5
5
5
VCCIO5
PB10A
PB10B
PB11A
PB11B
PB13B
VCCIO5
PB14A
PB14B
PB15A
PB15B
PB16A
5
5
5
5
5
5
5
5
5
5
5
5
T
C
T
T
C
T
T
C
T
C
C
C
T
C
T
C
T
BDQS6
T
C
T
C
T
BDQS14
VREF2_5
T
C
T
C
T
BDQS14
VREF2_5
VREF2_5
4-11
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP (Cont.)
LFEC1
LFEC3
LFECP6/EC6
Pin
LVD
S
LVD
S
LVD
Number Pin Function Bank
Dual Function
VREF1_5
Pin Function Bank
Dual Function
VREF1_5
Pin Function Bank
S
C
T
Dual Function
VREF1_5
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
PB8B
PB9A
5
5
5
5
-
C
T
PB16B
PB17A
GND5
5
5
5
5
-
C
T
PB16B
PB17A
GND5
5
5
5
5
-
PCLKT5_0
PCLKT5_0
PCLKT5_0
GND5
PB9B
C
PCLKC5_0
PB17B
VCCAUX
VCCIO4
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
C
PCLKC5_0
PB17B
VCCAUX
VCCIO4
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
C
PCLKC5_0
VCCAUX
VCCIO4
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
T
C
T
C
T
C
T
WRITEN
CS1N
T
C
T
C
T
C
T
WRITEN
CS1N
T
C
T
C
T
C
T
WRITEN
CS1N
VREF1_4
CSN
VREF1_4
CSN
VREF1_4
CSN
VREF2_4
D0/SPID7
D2/SPID5
VREF2_4
D0/SPID7
D2/SPID5
VREF2_4
D0/SPID7
D2/SPID5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16B
PB17B
VCCIO4
C
T
D1/SPID6
BDQS14
D3/SPID4
PB21B
PB22A
PB22B
PB23A
PB23B
PB24B
PB25B
VCCIO4
C
T
D1/SPID6
BDQS22
D3/SPID4
PB21B
PB22A
PB22B
PB23A
PB23B
PB24B
PB25B
VCCIO4
C
T
D1/SPID6
BDQS22
D3/SPID4
C
T
C
T
C
T
C
D4/SPID3
D5/SPID2
D6/SPID1
C
D4/SPID3
D5/SPID2
D6/SPID1
C
D4/SPID3
D5/SPID2
D6/SPID1
GND3
GND4
GND3
GND4
GND3
GND4
72*
-
-
-
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
VCCIO3
PR14A
PR12B
PR12A
PR11B
PR11A
PR10B
GND3
PR10A
PR9B
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
VCCIO3
PR18A
PR16B
PR16A
PR15B
PR15A
PR14B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
VCCIO3
PR27A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
VREF1_3
VREF1_3
VREF1_3
C
T
C
T
C
T
C
T
C
T
C
T
RDQS11
RDQS15
RDQS24
C
RLM0_PLLC_FB_A
C
RLM0_PLLC_FB_A
C
RLM0_PLLC_FB_A
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
PR14A
PR13B
PR13A
VCCIO3
PR12B
PR12A
PR11B
PR11A
CFG2
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
PR23A
PR22B
PR22A
VCCIO3
PR21B
PR21A
PR20B
PR20A
CFG2
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
PR9A
VCCIO3
PR8B
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
PR8A
PR7B
PR7A
CFG2
CFG1
CFG1
CFG1
CFG0
CFG0
CFG0
VCC
VCC
VCC
PROGRAMN
CCLK
3
3
3
-
PROGRAMN
CCLK
3
3
3
-
PROGRAMN
CCLK
3
3
3
-
INITN
INITN
INITN
GND
GND
GND
DONE
GND
3
-
DONE
GND
3
-
DONE
GND
3
-
4-12
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP (Cont.)
LFEC1
LFEC3
LFECP6/EC6
Pin
LVD
S
LVD
S
LVD
S
Number Pin Function Bank
Dual Function
Pin Function Bank
Dual Function
Pin Function Bank
Dual Function
99
VCC
PR5B
PR5A
PR4B
PR4A
PR3B
PR3A
PR2B
PR2A
VCCIO2
-
VCC
PR9B
PR9A
PR8B
PR8A
PR7B
PR7A
PR2B
PR2A
VCCIO2
-
VCC
PR9B
PR9A
PR8B
PR8A
PR7B
PR7A
PR2B
PR2A
VCCIO2
-
100
101
102
103
104
105
106
107
108
2
2
2
2
2
2
2
2
2
C
T
C
T
C
T
C
T
PCLKC2_0
PCLKT2_0
2
2
2
2
2
2
2
2
2
C
T
C
T
C
T
C
T
PCLKC2_0
PCLKT2_0
2
2
2
2
2
2
2
2
2
C
T
C
T
C
T
C
T
PCLKC2_0
PCLKT2_0
VREF1_2
VREF2_2
VREF1_2
VREF2_2
VREF1_2
VREF2_2
GND1
GND2
GND1
GND2
GND1
GND2
109*
-
-
-
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
VCCIO1
PT17B
PT17A
PT15A
PT14B
PT14A
PT13B
GND1
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
VCCIO1
VCCAUX
PT9B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
VCCIO1
PT25B
PT25A
PT23A
PT22B
PT22A
PT21B
GND1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
VCCIO1
PT25B
PT25A
PT23A
PT22B
PT22A
PT21B
GND1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
C
T
C
T
C
T
C
T
C
T
C
T
TDQS14
TDQS22
TDQS22
C
C
C
T
C
T
C
T
C
T
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
VCCIO1
VCCAUX
PT17B
GND0
T
C
T
C
T
C
T
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
VCCIO1
VCCAUX
PT17B
GND0
T
C
T
C
T
C
T
VREF2_1
VREF1_1
VREF2_1
VREF1_1
VREF2_1
VREF1_1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
PCLKC0_0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
PCLKC0_0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
PCLKC0_0
GND0
PT9A
T
C
T
C
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
VCCIO0
PT13B
PT13A
PT12B
PT12A
PT10B
PT10A
VCCIO0
T
C
T
C
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
VCCIO0
PT13B
PT13A
PT12B
PT12A
PT10B
PT10A
VCCIO0
T
C
T
C
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
PT8B
PT8A
PT7B
PT7A
PT6B
PT6A
TDQS6
TDQS14
TDQS14
VCCIO0
PT5B
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
PT5A
PT4B
PT4A
PT2B
PT2A
VCCIO0
GND0
GND7
GND0
GND7
GND0
GND7
144*
-
-
-
*Double bonded to the pin.
4-13
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3 Logic Signal Connections: 208 PQFP
LFEC1
Pin Number Pin Function Bank LVDS
GND0
LFEC3
Dual Function
Pin Function Bank LVDS
Dual Function
GND0
-
1*
-
GND7
VCCIO7
PL2A
PL2B
NC
GND7
2
7
7
7
-
VCCIO7
PL2A
PL2B
NC
7
7
7
-
3
T
VREF2_7
VREF1_7
T
VREF2_7
VREF1_7
4
C
C
5
6
NC
-
NC
-
7
NC
-
PL3B
PL4A
PL4B
PL5A
PL5B
PL6A
VCCIO7
PL6B
PL7A
PL7B
PL8A
NC
7
7
7
7
7
7
7
7
7
7
7
-
8
NC
-
T
C
T
C
T
9
NC
-
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
-
NC
-
NC
-
LDQS6
NC
-
NC
-
C
T
C
T
PL3A
PL3B
PL4A
NC
7
7
7
-
T
C
T
PL4B
PL5A
PL5B
NC
7
7
7
-
C
T
PL8B
PL9A
PL9B
VCCAUX
XRES
NC
7
7
7
-
C
T
PCLKT7_0
PCLKC7_0
PCLKT7_0
PCLKC7_0
C
C
XRES
NC
6
-
6
-
NC
-
NC
-
VCC
TCK
GND
TDI
-
VCC
-
6
-
TCK
6
-
GND
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TDI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TMS
TDO
VCCJ
PL7A
PL7B
PL8A
PL8B
VCCIO6
PL9A
PL9B
PL10A
GND6
PL10B
TMS
TDO
VCCJ
PL11A
PL11B
PL12A
PL12B
VCCIO6
PL13A
PL13B
PL14A
GND6
PL14B
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
C
C
T
C
T
T
C
T
C
C
4-14
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.)
LFEC1
LFEC3
Pin Number Pin Function Bank LVDS
Dual Function
Pin Function Bank LVDS
Dual Function
43
44
45
46
47
48
49
50
51
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL14B
VCCIO6
6
6
6
6
6
6
6
6
6
T
C
T
LDQS11
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
PL18B
VCCIO6
6
6
6
6
6
6
6
6
6
T
C
T
LDQS15
C
T
C
T
C
T
C
T
VREF1_6
VREF2_6
VREF1_6
VREF2_6
C
C
GND5
GND6
GND5
GND6
52*
-
-
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VCCIO5
NC
5
-
VCCIO5
PB2A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
T
C
T
C
T
C
T
C
T
C
NC
-
PB2B
NC
-
PB3A
NC
-
PB3B
NC
-
PB4A
NC
-
PB4B
NC
-
PB5A
NC
-
PB5B
NC
-
PB6A
BDQS6
NC
-
PB6B
NC
-
VCCIO5
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
VCCIO5
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
PB17B
VCCAUX
PB2A
PB2B
PB3A
PB3B
PB4A
PB4B
PB5A
NC
5
5
5
5
5
5
5
-
T
C
T
C
T
C
T
T
C
T
C
T
C
T
PB5B
VCCIO5
PB6A
PB6B
PB7A
PB7B
PB8A
PB8B
PB9A
GND5
PB9B
VCCAUX
5
5
5
5
5
5
5
5
5
5
5
-
C
C
T
C
T
C
T
C
T
BDQS6
T
C
T
C
T
C
T
BDQS14
VREF2_5
VREF1_5
PCLKT5_0
VREF2_5
VREF1_5
PCLKT5_0
C
PCLKC5_0
C
PCLKC5_0
4-15
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.)
LFEC1
LFEC3
Pin Number Pin Function Bank LVDS
Dual Function
Pin Function Bank LVDS
Dual Function
85
86
VCCIO4
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
VCCIO4
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
T
C
T
C
T
C
T
WRITEN
CS1N
T
C
T
C
T
C
T
WRITEN
CS1N
87
88
VREF1_4
CSN
VREF1_4
CSN
89
90
VREF2_4
D0/SPID7
D2/SPID5
VREF2_4
D0/SPID7
D2/SPID5
91
92
93
94
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
PB17B
NC
C
T
D1/SPID6
BDQS14
D3/SPID4
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB25B
NC
C
T
D1/SPID6
BDQS22
D3/SPID4
95
96
C
T
C
T
97
98
C
T
D4/SPID3
D5/SPID2
D6/SPID1
C
T
D4/SPID3
D5/SPID2
D6/SPID1
99
100
101
102
103
104
C
T
C
T
C
C
VCCIO4
4
VCCIO4
4
GND3
GND4
GND3
GND4
105*
-
-
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
VCCIO3
PR14B
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR10B
GND3
PR10A
PR9B
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VCCIO3
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
C
T
VREF2_3
VREF1_3
C
T
VREF2_3
VREF1_3
C
T
C
T
C
T
C
T
C
T
C
T
RDQS11
RDQS15
C
RLM0_PLLC_FB_A
C
RLM0_PLLC_FB_A
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
PR14A
PR13B
PR13A
VCCIO3
PR12B
PR12A
PR11B
PR11A
CFG2
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
PR9A
VCCIO3
PR8B
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
PR8A
PR7B
PR7A
CFG2
CFG1
CFG1
4-16
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.)
LFEC1
LFEC3
Pin Number Pin Function Bank LVDS
Dual Function
Pin Function Bank LVDS
Dual Function
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
CFG0
VCC
3
-
CFG0
VCC
3
-
PROGRAMN
CCLK
INITN
GND
DONE
GND
VCC
3
3
3
-
PROGRAMN
CCLK
INITN
GND
3
3
3
-
3
-
DONE
GND
3
-
-
VCC
-
NC
-
VCCAUX
PR9B
GND2
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
VCCIO2
PR6A
PR5B
PR5A
PR4B
PR4A
NC
-
PR5B
NC
2
-
C
PCLKC2_0
PCLKT2_0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
C
PCLKC2_0
PCLKT2_0
PR5A
PR4B
PR4A
PR3B
PR3A
NC
2
2
2
2
2
-
T
C
T
C
T
T
C
T
C
T
C
NC
-
NC
-
T
C
T
C
T
RDQS6
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
PR2B
PR2A
VCCIO2
2
2
2
C
T
VREF1_2
VREF2_2
PR2B
PR2A
VCCIO2
2
2
2
C
T
VREF1_2
VREF2_2
GND1
GND2
GND1
GND2
156*
-
-
157
158
159
160
161
162
163
164
165
166
167
168
VCCIO1
NC
1
-
VCCIO1
NC
1
-
PT17B
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND1
1
1
1
1
1
1
1
1
1
1
C
T
PT25B
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND1
1
1
1
1
1
1
1
1
1
1
C
T
C
T
C
T
C
T
C
T
C
T
C
T
TDQS14
TDQS22
C
C
4-17
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC1, LFEC3 Logic Signal Connections: 208 PQFP (Cont.)
LFEC1
LFEC3
Pin Number Pin Function Bank LVDS
Dual Function
Pin Function Bank LVDS
Dual Function
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
VCCIO1
VCCAUX
PT9B
GND0
PT9A
PT8B
PT8A
PT7B
PT7A
PT6B
PT6A
VCCIO0
PT5B
NC
1
1
1
1
1
1
1
1
-
T
C
T
C
T
C
T
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
VCCIO1
VCCAUX
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
VCCIO0
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
VCCIO0
PT6B
1
1
1
1
1
1
1
1
-
T
C
T
C
T
C
T
VREF2_1
VREF1_1
VREF2_1
VREF1_1
0
0
0
0
0
0
0
0
0
0
0
-
C
PCLKC0_0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
PCLKC0_0
T
C
T
C
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
T
C
T
C
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
TDQS6
TDQS14
C
C
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
PT2A
NC
0
0
0
0
0
0
0
-
T
C
T
C
T
C
T
T
C
T
C
T
C
T
NC
-
C
T
C
T
C
T
C
T
C
T
NC
-
PT6A
TDQS6
NC
-
PT5B
NC
-
PT5A
NC
-
PT4B
NC
-
PT4A
NC
-
PT3B
NC
-
PT3A
NC
-
PT2B
NC
-
PT2A
VCCIO0
0
VCCIO0
* Double bonded to the pin.
4-18
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP
LFECP6/LFEC6
Pin Number Pin Function Bank LVDS
GND0
LFECP10/LFEC10
Dual Function
Pin Function Bank LVDS
Dual Function
GND0
GND7
1*
-
-
GND7
VCCIO7
PL2A
PL2B
NC
2
7
7
7
-
VCCIO7
PL2A
7
7
7
-
3
T
VREF2_7
VREF1_7
T
VREF2_7
VREF1_7
4
C
PL2B
C
5
VCC
6
NC
-
GND
-
7
PL3B
PL4A
PL4B
PL5A
PL5B
PL6A
VCCIO7
PL6B
PL7A
PL7B
PL8A
GND7
PL8B
PL9A
PL9B
VCCAUX
XRES
VCC
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
PL12B
PL13A
PL13B
PL14A
PL14B
PL15A
VCCIO7
PL15B
PL16A
PL16B
PL17A
GND7
PL17B
PL18A
PL18B
VCCAUX
XRES
VCC
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
8
T
C
T
C
T
T
C
T
C
T
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
LDQS6
LDQS15
C
T
C
T
C
T
C
T
C
T
C
T
PCLKT7_0
PCLKC7_0
PCLKT7_0
PCLKC7_0
C
C
6
-
6
-
GND
-
GND
-
VCC
-
VCC
-
TCK
6
-
TCK
6
-
GND
GND
TDI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TDI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TMS
TMS
TDO
TDO
VCCJ
PL20A
PL20B
PL21A
PL21B
VCCIO6
PL22A
PL22B
PL23A
GND6
PL23B
VCCJ
PL29A
PL29B
PL30A
PL30B
VCCIO6
PL31A
PL31B
PL32A
GND6
PL32B
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
C
C
T
C
T
T
C
T
C
C
4-19
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
Pin Number Pin Function Bank LVDS
Dual Function
Pin Function Bank LVDS
Dual Function
43
44
45
46
47
48
49
50
51
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
PL27B
VCCIO6
6
6
6
6
6
6
6
6
6
T
C
T
LDQS24
PL33A
PL33B
PL34A
PL34B
PL35A
PL35B
PL36A
PL36B
VCCIO6
6
6
6
6
6
6
6
6
6
T
C
T
LDQS33
C
T
C
T
C
T
C
T
VREF1_6
VREF2_6
VREF1_6
VREF2_6
C
C
GND5
GND6
GND5
GND6
52*
-
-
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VCCIO5
PB2A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
VCCIO5
PB2A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
PB2B
PB2B
PB3A
PB3A
PB3B
PB3B
PB4A
PB4A
PB4B
PB4B
PB5A
PB5A
PB5B
PB5B
PB6A
BDQS6
PB6A
BDQS6
PB6B
PB6B
VCCIO5
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
VCCIO5
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
PB17B
VCCAUX
VCCIO5
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND5
PB21B
VCCIO5
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND5
PB25B
VCCAUX
T
C
T
C
T
C
T
T
C
T
C
T
C
T
C
C
T
C
T
C
T
C
T
BDQS14
T
C
T
C
T
C
T
BDQS22
VREF2_5
VREF1_5
PCLKT5_0
VREF2_5
VREF1_5
PCLKT5_0
C
PCLKC5_0
C
PCLKC5_0
4-20
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
Pin Number Pin Function Bank LVDS
Dual Function
Pin Function Bank LVDS
Dual Function
85
86
VCCIO4
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
VCCIO4
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
T
C
T
C
T
C
T
WRITEN
CS1N
T
C
T
C
T
C
T
WRITEN
CS1N
87
88
VREF1_4
CSN
VREF1_4
CSN
89
90
VREF2_4
D0/SPID7
D2/SPID5
VREF2_4
D0/SPID7
D2/SPID5
91
92
93
94
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB25B
PB33A
VCCIO4
C
T
D1/SPID6
BDQS22
D3/SPID4
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
PB33B
PB41A
VCCIO4
C
T
D1/SPID6
BDQS30
D3/SPID4
95
96
C
T
C
T
97
98
C
T
D4/SPID3
D5/SPID2
D6/SPID1
C
T
D4/SPID3
D5/SPID2
D6/SPID1
99
100
101
102
103
104
C
T
C
T
C
C
GND3
GND4
GND3
GND4
105*
-
-
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
VCCIO3
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VCCIO3
PR36B
PR36A
PR35B
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
C
T
VREF2_3
VREF1_3
C
T
VREF2_3
VREF1_3
C
T
C
T
C
T
C
T
C
T
C
T
RDQS24
RDQS33
C
RLM0_PLLC_FB_A
C
RLM0_PLLC_FB_A
PR23A
PR22B
PR22A
VCCIO3
PR21B
PR21A
PR20B
PR20A
CFG2
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
PR32A
PR31B
PR31A
VCCIO3
PR30B
PR30A
PR29B
PR29A
CFG2
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
CFG1
CFG1
4-21
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
Pin Number Pin Function Bank LVDS
Dual Function
Pin Function Bank LVDS
Dual Function
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
CFG0
VCC
3
-
CFG0
VCC
3
-
PROGRAMN
CCLK
INITN
GND
3
3
3
-
PROGRAMN
CCLK
3
3
3
-
INITN
GND
DONE
GND
3
-
DONE
GND
3
-
VCC
-
VCC
-
VCCAUX
PR9B
GND2
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
VCCIO2
PR6A
PR5B
PR5A
PR4B
PR4A
NC
-
VCCAUX
PR18B
GND2
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
C
PCLKC2_0
PCLKT2_0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
C
PCLKC2_0
PCLKT2_0
T
C
T
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
VCCIO2
PR15A
PR14B
PR14A
PR13B
PR13A
GND
T
C
T
C
T
C
T
C
C
T
C
T
C
T
RDQS6
T
C
T
C
T
RDQS15
NC
-
VCC
-
PR2B
PR2A
VCCIO2
2
2
2
C
T
VREF1_2
VREF2_2
PR2B
2
2
2
C
T
VREF1_2
VREF2_2
PR2A
VCCIO2
GND1
GND2
GND1
GND2
156*
-
-
157
158
159
160
161
162
163
164
165
166
167
168
VCCIO1
PT33A
PT25B
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND1
1
1
1
1
1
1
1
1
1
1
1
1
VCCIO1
PT41A
PT33B
PT33A
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND1
1
1
1
1
1
1
1
1
1
1
1
1
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
TDQS22
TDQS30
C
C
4-22
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10 Logic Signal Connections: 208 PQFP (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
Pin Number Pin Function Bank LVDS
Dual Function
Pin Function Bank LVDS
Dual Function
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
VCCIO1
VCCAUX
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
VCCIO0
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
VCCIO0
PT6B
1
1
1
1
1
1
1
1
-
T
C
T
C
T
C
T
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
VCCIO1
VCCAUX
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
VCCIO0
PT21B
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
VCCIO0
PT6B
1
1
1
1
1
1
1
1
-
T
C
T
C
T
C
T
VREF2_1
VREF1_1
VREF2_1
VREF1_1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
PCLKC0_0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
PCLKC0_0
T
C
T
C
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
T
C
T
C
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
TDQS14
TDQS22
C
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
PT6A
TDQS6
PT6A
TDQS6
PT5B
PT5B
PT5A
PT5A
PT4B
PT4B
PT4A
PT4A
PT3B
PT3B
PT3A
PT3A
PT2B
PT2B
PT2A
PT2A
VCCIO0
VCCIO0
*Double bonded to the pin.
4-23
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA
LFEC3
LFECP6/LFEC6
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
GND
D4
D3
C3
C2
B1
C1
E3
E4
F4
F5
G4
G3
D2
D1
E1
GND
E2
F3
G5
H5
F2
F1
H4
H3
G2
-
GND7
PL2A
PL2B
PL3A
PL3B
PL4A
PL4B
PL5A
PL5B
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
GND7
PL9B
XRES
NC
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
-
GND7
PL2A
PL2B
PL3A
PL3B
PL4A
PL4B
PL5A
PL5B
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
GND7
PL9B
XRES
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
GND6
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND6
PL18B
TCK
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
VREF2_7
VREF1_7
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
VREF2_7
VREF1_7
LDQS6
LDQS6
PCLKT7_0
PCLKC7_0
PCLKT7_0
PCLKC7_0
C
C
T
C
T
C
T
C
T
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
-
-
G1
J4
NC
-
C
T
C
T
C
T
C
T
NC
-
LDQS15
J3
NC
-
J5
NC
-
K5
H2
H1
J2
NC
-
NC
-
NC
-
NC
-
-
-
-
J1
NC
-
C
K4
K3
L3
TCK
TDI
6
6
6
6
6
TDI
TMS
TDO
VCCJ
TMS
L5
TDO
L4
VCCJ
4-24
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.)
LFEC3
LFECP6/LFEC6
Ball
Number
Ball Function Bank LVDS
Dual Function
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
Ball Function Bank LVDS
Dual Function
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
K2
K1
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
GND6
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
PL18B
GND6
GND5
PB2A
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
T
C
T
C
T
C
T
PL20A
PL20B
PL21A
PL21B
PL22A
PL22B
PL23A
GND6
PL23B
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
PL27B
GND6
GND5
PB2A
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
T
C
T
C
T
C
T
L2
L1
M2
M1
N1
GND
N2
M4
M3
P1
C
T
C
T
LDQS15
LDQS24
C
T
C
T
R1
P2
C
T
C
T
P3
C
T
C
T
N3
N4
GND
GND
P4
VREF1_6
VREF2_6
VREF1_6
VREF2_6
C
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
N5
P5
PB2B
PB2B
PB3A
PB3A
P6
PB3B
PB3B
R4
R3
T2
PB4A
PB4A
PB4B
PB4B
PB5A
PB5A
T3
PB5B
PB5B
R5
R6
T4
PB6A
BDQS6
PB6A
BDQS6
PB6B
PB6B
PB7A
PB7A
T5
PB7B
PB7B
N6
M6
T6
PB8A
PB8A
PB8B
PB8B
PB9A
PB9A
GND
T7
GND5
PB9B
GND5
PB9B
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
P7
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
N7
R7
R8
M7
M8
T8
4-25
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.)
LFEC3
LFECP6/LFEC6
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
GND
T9
GND5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
-
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
GND5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
P8
BDQS14
BDQS14
N8
R9
R10
P9
VREF2_5
VREF1_5
PCLKT5_0
VREF2_5
VREF1_5
PCLKT5_0
N9
T10
GND
T11
T12
T13
P10
N10
T14
T15
M10
GND
M11
R11
P11
R13
R14
P12
P13
N11
-
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
VREF1_4
CSN
VREF1_4
CSN
VREF2_4
D0/SPID7
D2/SPID5
VREF2_4
D0/SPID7
D2/SPID5
C
T
C
T
C
T
C
T
D1/SPID6
BDQS22
D3/SPID4
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS22
D3/SPID4
D4/SPID3
D5/SPID2
D4/SPID3
D5/SPID2
N12
R12
GND
-
PB25B
NC
4
-
C
D6/SPID1
PB25B
PB26A
GND4
C
D6/SPID1
GND4
-
4
-
GND4
GND
N13
N14
P14
P15
R15
R16
M13
M14
P16
GND
GND3
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND3
3
3
3
3
3
3
3
3
3
3
3
GND3
C
T
VREF2_3
VREF1_3
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
C
T
VREF2_3
VREF1_3
C
T
C
T
C
T
C
T
C
T
C
T
RDQS15
RDQS24
C
RLM0_PLLC_FB_A
C
RLM0_PLLC_FB_A
4-26
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.)
LFEC3
LFECP6/LFEC6
Ball
Number
Ball Function Bank LVDS
Dual Function
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
DI/CSSPIN
Ball Function Bank LVDS
Dual Function
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
DI/CSSPIN
N16
N15
M15
M16
L16
K16
J16
L12
L14
L13
K13
L15
K15
K14
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
CFG2
CFG1
CFG0
PROGRAMN
CCLK
INITN
DONE
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
T
C
T
C
T
C
T
PR23A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
CFG2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
T
C
T
C
T
C
T
DOUT/CSON
DOUT/CSON
BUSY/SISPI
BUSY/SISPI
D7/SPID0
D7/SPID0
CFG1
CFG0
PROGRAMN
CCLK
INITN
DONE
GND3
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND3
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
H16
H15
G16
G15
K12
J12
J14
J15
F16
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
RDQS15
NC
-
C
-
-
F15
J13
H13
H14
G14
E16
E15
H12
GND
G12
G13
F13
F12
E13
D16
D15
F14
E14
NC
-
T
C
T
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
PR9B
GND2
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
PR5B
PR5A
2
2
2
2
2
2
2
2
2
2
2
C
PCLKC2_0
PCLKT2_0
C
PCLKC2_0
PCLKT2_0
GND2
PR9A
T
C
T
C
T
C
T
C
T
2
2
2
2
2
2
2
2
2
T
C
T
C
T
C
T
C
T
PR8B
PR8A
PR7B
PR7A
PR6B
RDQS6
PR6A
RDQS6
PR5B
PR5A
4-27
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.)
LFEC3
LFECP6/LFEC6
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
C16
B16
C15
C14
D14
D13
GND
GND
-
PR4B
PR4A
PR3B
PR3A
PR2B
PR2A
GND2
GND1
-
2
2
2
2
2
2
2
1
-
C
T
C
T
C
T
PR4B
PR4A
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
T
C
T
C
T
PR3B
PR3A
VREF1_2
VREF2_2
PR2B
VREF1_2
VREF2_2
PR2A
GND2
GND1
GND1
PT26B
PT26A
PT25B
GND1
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND1
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
B13
C13
C12
-
NC
-
C
T
NC
-
PT25B
-
1
-
C
C
D12
A15
B14
D11
C11
E10
E11
A14
GND
A13
D10
C10
A12
B12
A11
B11
A10
GND
B10
C9
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND1
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
C
T
T
C
T
C
T
C
T
C
T
C
T
TDQS22
TDQS22
C
C
T
C
T
T
C
T
C
T
VREF2_1
VREF1_1
C
T
VREF2_1
VREF1_1
C
T
C
T
C
PCLKC0_0
C
PCLKC0_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
B9
E9
C
T
C
T
D9
D8
C
T
C
T
C8
TDQS14
TDQS14
A9
C
C
GND
A8
T
C
T
T
C
T
B8
B7
4-28
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.)
LFEC3
LFECP6/LFEC6
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
D7
C7
A7
PT11B
PT11A
PT10B
PT10A
PT9B
GND0
PT9A
PT8B
PT8A
PT7B
PT7A
PT6B
PT6A
PT5B
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
PT2A
GND0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
T
PT11B
PT11A
PT10B
PT10A
PT9B
GND0
PT9A
PT8B
PT8A
PT7B
PT7A
PT6B
PT6A
PT5B
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
PT2A
GND0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
T
C
T
C
T
A6
E7
C
C
GND
E6
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
D6
C6
B6
B5
A5
A4
TDQS6
TDQS6
A3
A2
B2
B3
D5
C5
C4
B4
GND
A1
A16
G10
G7
G8
G9
H10
H7
H8
H9
J10
J7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J8
-
-
J9
-
-
K10
K7
-
-
-
-
K8
-
-
K9
-
-
T1
-
-
T16
E12
-
-
-
-
4-29
Pinout Information
LatticeECP/EC Family Data Sheet
LFEC3 and LFECP/EC6 Logic Signal Connections: 256 fpBGA (Cont.)
LFEC3
LFECP6/LFEC6
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
E5
E8
VCC
VCC
-
-
VCC
VCC
-
-
M12
M5
M9
B15
R2
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCC
-
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCC
-
-
-
F7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
-
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
-
F8
F10
F9
G11
H11
J11
K11
L10
L9
L7
L8
J6
K6
G6
H6
F6
F11
L11
L6
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
4-30
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA
LFECP10/LFEC10
LFECP15/LFEC15
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
GND
D4
D3
GND
C3
C2
B1
GND7
PL2A
7
7
7
7
7
7
7
7
7
7
-
GND7
PL2A
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T
VREF2_7
VREF1_7
T
VREF2_7
VREF1_7
PL2B
C
PL2B
C
GND7
PL12A
PL12B
PL13A
PL13B
PL14A
GND7
-
GND7
PL16A
PL16B
PL17A
PL17B
PL18A
GND7
GND7
PL18B
PL19A
PL19B
PL20A
PL20B
PL21A
PL21B
PL22A
GND7
PL22B
XRES
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
GND6
PL27B
PL28A
PL28B
PL29A
PL29B
PL30A
PL30B
PL31A
GND6
PL31B
TCK
T
C
T
C
T
T
C
T
C
T
C1
E3
GND
-
E4
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND7
PL18B
XRES
PL20A
PL20B
PL21A
PL21B
PL22A
PL22B
PL23A
GND6
PL23B
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
GND6
PL27B
TCK
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
F4
LDQS15
LDQS19
F5
G4
G3
D2
D1
E1
PCLKT7_0
PCLKC7_0
PCLKT7_0
PCLKC7_0
GND
E2
C
C
F3
G5
H5
F2
T
C
T
C
T
C
T
T
C
T
C
T
C
T
F1
H4
H3
G2
GND
G1
J4
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
LDQS24
LDQS28
J3
J5
K5
H2
H1
J2
GND
J1
C
C
K4
K3
TDI
TDI
4-31
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA (Cont.)
LFECP10/LFEC10
LFECP15/LFEC15
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
L3
L5
TMS
6
6
6
6
6
6
6
6
6
6
6
-
TMS
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
TDO
TDO
L4
VCCJ
VCCJ
K2
PL29A
PL29B
PL30A
PL30B
PL31A
PL31B
PL32A
GND6
-
T
C
T
C
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
PL37A
PL37B
PL38A
PL38B
PL39A
PL39B
PL40A
GND6
GND6
PL40B
PL41A
PL41B
PL42A
PL42B
PL43A
PL43B
PL44A
PL44B
GND6
GND5
GND5
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
PB17B
PB18A
T
C
T
C
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
K1
L2
L1
M2
M1
N1
GND
-
N2
M4
M3
P1
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
PL35B
PL36A
PL36B
GND6
GND5
GND5
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
PB17B
PB18A
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
C
T
C
T
LDQS33
LDQS41
C
T
C
T
R1
P2
C
T
C
T
P3
C
T
C
T
N3
N4
GND
GND
GND
P4
VREF1_6
VREF2_6
VREF1_6
VREF2_6
C
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
N5
P5
P6
R4
R3
T2
GND
T3
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
R5
R6
T4
BDQS14
BDQS14
T5
N6
M6
T6
GND
T7
C
T
C
T
P7
4-32
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA (Cont.)
LFECP10/LFEC10
LFECP15/LFEC15
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
N7
R7
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND5
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND5
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND4
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GND4
PB33B
PB34A
GND4
GND4
-
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
C
T
C
T
C
T
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND5
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND5
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND4
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GND4
PB33B
PB34A
GND4
GND4
GND4
GND4
GND3
PR44B
PR44A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
C
T
C
T
C
T
R8
M7
M8
T8
GND
T9
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
P8
BDQS22
BDQS22
N8
R9
R10
P9
VREF2_5
VREF1_5
PCLKT5_0
VREF2_5
VREF1_5
PCLKT5_0
N9
T10
GND
T11
T12
T13
P10
N10
T14
T15
M10
GND
M11
R11
P11
R13
R14
P12
P13
N11
GND
N12
R12
GND
GND
-
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
VREF1_4
CSN
VREF1_4
CSN
VREF2_4
D0/SPID7
D2/SPID5
VREF2_4
D0/SPID7
D2/SPID5
C
T
C
T
C
T
C
T
D1/SPID6
BDQS30
D3/SPID4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS30
D3/SPID4
D4/SPID3
D5/SPID2
D4/SPID3
D5/SPID2
C
D6/SPID1
C
D6/SPID1
-
-
-
GND
N13
N14
GND3
PR36B
PR36A
3
3
3
C
T
VREF2_3
VREF1_3
C
T
VREF2_3
VREF1_3
4-33
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA (Cont.)
LFECP10/LFEC10
LFECP15/LFEC15
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
P14
P15
R15
R16
M13
M14
P16
GND
N16
N15
M15
M16
L16
K16
J16
PR35B
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
PR40B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
C
T
C
T
C
T
C
T
C
T
RDQS33
RDQS41
C
RLM0_PLLC_FB_A
C
RLM0_PLLC_FB_A
PR32A
PR31B
PR31A
PR30B
PR30A
PR29B
PR29A
CFG2
T
C
T
C
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
DI/CSSPIN
PR40A
PR39B
PR39A
PR38B
PR38A
PR37B
PR37A
CFG2
T
C
T
C
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
DI/CSSPIN
DOUT/CSON
DOUT/CSON
BUSY/SISPI
BUSY/SISPI
D7/SPID0
D7/SPID0
L12
L14
L13
K13
L15
K15
K14
GND
H16
-
CFG1
CFG1
CFG0
CFG0
PROGRAMN
CCLK
PROGRAMN
CCLK
INITN
INITN
DONE
GND3
DONE
GND3
PR27B
-
C
PR31B
GND3
C
H15
G16
G15
K12
J12
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
T
C
T
PR31A
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
GND3
T
C
T
C
T
C
T
J14
C
T
C
T
J15
RDQS24
RDQS28
F16
GND
F15
J13
C
C
PR23A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR18B
GND2
T
C
T
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR22B
GND2
T
C
T
H13
H14
G14
E16
E15
H12
GND
C
T
C
T
C
T
C
T
C
PCLKC2_0
4-34
C
PCLKC2_0
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA (Cont.)
LFECP10/LFEC10
LFECP15/LFEC15
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
G12
G13
F13
F12
E13
D16
D15
F14
GND
E14
C16
B16
C15
C14
GND
-
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND2
PR14A
PR13B
PR13A
PR12B
PR12A
GND2
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
T
C
T
PCLKT2_0
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR18B
GND2
PR18A
PR17B
PR17A
PR16B
PR16A
GND2
GND2
PR2B
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T
C
T
PCLKT2_0
C
T
C
T
C
T
C
T
RDQS19
C
C
T
C
T
C
T
T
C
T
C
T
D14
D13
GND
GND
GND
-
PR2B
PR2A
GND2
GND1
GND1
-
2
2
2
1
1
-
C
T
VREF1_2
VREF2_2
C
T
VREF1_2
VREF2_2
PR2A
GND2
GND1
GND1
GND1
GND1
PT34B
PT34A
PT33B
GND1
PT33A
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND1
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
-
-
-
B13
C13
C12
GND
D12
A15
B14
D11
C11
E10
E11
A14
GND
A13
D10
C10
A12
B12
A11
B11
PT34B
PT34A
PT33B
GND1
PT33A
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND1
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
T
C
T
C
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
TDQS30
TDQS30
C
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
VREF2_1
VREF1_1
VREF2_1
VREF1_1
4-35
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA (Cont.)
LFECP10/LFEC10
LFECP15/LFEC15
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
A10
GND
B10
C9
B9
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
GND0
GND0
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
PCLKC0_0
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
GND0
GND0
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
PCLKC0_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
E9
C
T
C
T
D9
D8
C8
A9
C
T
C
T
TDQS22
TDQS22
C
C
GND
A8
T
C
T
T
C
T
B8
B7
D7
C7
A7
C
T
C
T
C
T
C
T
A6
E7
C
C
GND
E6
T
C
T
T
C
T
D6
C6
B6
C
T
C
T
B5
A5
C
T
C
T
A4
TDQS14
TDQS14
A3
C
C
-
A2
T
C
T
C
T
C
T
T
C
T
C
T
C
T
B2
B3
D5
C5
C4
B4
GND
GND
A1
A16
G10
G7
G8
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
4-36
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC10 and LFECP/EC15 Logic Signal Connections: 256 fpBGA (Cont.)
LFECP10/LFEC10
LFECP15/LFEC15
Ball
Number
Ball Function Bank LVDS
Dual Function
Ball Function Bank LVDS
Dual Function
G9
H10
H7
H8
H9
J10
J7
GND
GND
-
-
GND
GND
-
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
J8
GND
-
GND
-
J9
GND
-
GND
-
K10
K7
GND
-
GND
-
GND
-
GND
-
K8
GND
-
GND
-
K9
GND
-
GND
-
T1
GND
-
GND
-
T16
E12
E5
GND
-
GND
-
VCC
-
VCC
-
VCC
-
VCC
-
E8
VCC
-
VCC
-
M12
M5
M9
B15
R2
F7
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCC
-
VCCAUX
VCCAUX
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCC
-
-
-
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
-
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
-
F8
F10
F9
G11
H11
J11
K11
L10
L9
L7
L8
J6
K6
G6
H6
F6
F11
L11
L6
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
4-37
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Number Function Bank LVDS
GND
D4
E4
C3
B2
E5
F5
GND7
PL2A
PL2B
NC
7
7
7
-
GND
D4
E4
C3
B2
E5
F5
GND7
PL2A
PL2B
PL3A
PL3B
PL4A
PL4B
PL5A
PL5B
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
GND7
PL9B
NC
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
GND
D4
E4
C3
B2
E5
F5
GND7
PL2A
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
T
VREF2_7
VREF1_7
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
VREF2_7
VREF1_7
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
VREF2_7
VREF1_7
C
PL2B
PL3A
NC
-
PL3B
NC
-
PL4A
NC
-
PL4B
D3
C2
F4
NC
-
D3
C2
F4
D3
C2
F4
PL5A
NC
-
PL5B
NC
-
LDQS6
PL6A
LDQS6
G4
E3
D2
B1
C1
F3
NC
-
G4
E3
D2
B1
C1
F3
G4
E3
D2
B1
C1
F3
PL6B
NC
-
PL7A
NC
-
PL7B
NC
-
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
PL8A
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
NC
-
PL8B
NC
-
PL9A
GND
E2
G5
H6
G3
H4
J5
-
-
GND
E2
G5
H6
G3
H4
J5
GND
E2
G5
H6
G3
H4
J5
GND7
PL9B
NC
-
C
LUM0_PLLC_FB_A
C
T
C
T
C
T
C
T
LUM0_PLLC_FB_A
NC
-
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
GND7
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND7
PL18B
PL19A
PL19B
PL20A
PL20B
PL21A
PL21B
PL22A
GND7
PL22B
XRES
PL24A
PL24B
PL25A
PL25B
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
H5
F2
NC
-
H5
F2
NC
-
H5
F2
NC
-
NC
-
GND
F1
-
-
GND
F1
-
-
GND
F1
NC
-
NC
-
C
T
C
T
C
T
C
T
E1
D1
H3
G2
H2
G1
J4
NC
-
E1
D1
H3
G2
H2
G1
J4
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
GND7
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND7
PL18B
XRES
PL20A
PL20B
PL21A
PL21B
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
T
C
T
C
T
C
T
E1
D1
H3
G2
H2
G1
J4
NC
-
PL3A
PL3B
PL4A
PL4B
PL5A
-
7
7
7
7
7
-
T
C
T
C
T
GND
J3
GND
J3
GND
J3
PL5B
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
GND7
PL9B
XRES
PL11A
PL11B
PL12A
PL12B
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
J2
LDQS6
J2
LDQS15
J2
LDQS19
H1
K4
K5
K3
K2
J1
H1
K4
K5
K3
K2
J1
H1
K4
K5
K3
K2
J1
PCLKT7_0
PCLKC7_0
PCLKT7_0
PCLKC7_0
PCLKT7_0
PCLKC7_0
GND
K1
L3
GND
K1
L3
GND
K1
L3
C
C
C
L4
T
C
T
L4
T
C
T
L4
T
C
T
L5
L5
L5
L2
L2
L2
L1
C
L1
C
L1
C
4-38
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
M4
M5
M1
GND
M2
N3
PL13A
PL13B
PL14A
GND6
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND6
PL18B
NC
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
T
C
T
M4
M5
M1
GND
M2
N3
M3
N5
N4
N1
N2
P1
PL22A
PL22B
PL23A
GND6
PL23B
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
GND6
PL27B
NC
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
T
C
T
M4
M5
M1
GND
M2
N3
PL26A
PL26B
PL27A
GND6
PL27B
PL28A
PL28B
PL29A
PL29B
PL30A
PL30B
PL31A
GND6
PL31B
PL32A
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
GND6
PL35B
NC
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
LDQS15
LDQS24
LDQS28
M3
N5
M3
N5
N4
N4
N1
N1
N2
N2
P1
P1
GND
P2
GND
P2
GND
P2
C
C
C
T
C
T
C
T
C
T
R6
R6
P5
R6
P5
NC
-
NC
-
P5
P3
NC
-
P3
NC
-
P3
P4
NC
-
P4
NC
-
P4
R1
NC
-
R1
R2
R5
-
NC
-
R1
R2
NC
-
NC
-
R2
R5
NC
-
NC
-
R5
GND
R4
-
-
-
-
GND
R4
NC
-
R4
T1
NC
-
C
T1
NC
-
NC
-
T1
T2
NC
-
T2
NC
-
T2
NC
-
R3
NC
-
R3
T3
NC
-
R3
NC
-
T3
NC
-
NC
-
T3
NC
-
T5
TCK
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T5
TCK
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T5
TCK
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
U5
TDI
U5
T4
TDI
U5
TDI
T4
TMS
TMS
T4
TMS
U1
TDO
U1
U2
V1
TDO
U1
TDO
U2
VCCJ
PL20A
PL20B
PL21A
PL21B
PL22A
PL22B
PL23A
GND6
PL23B
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
PL27B
GND6
VCCJ
PL29A
PL29B
PL30A
PL30B
PL31A
PL31B
PL32A
GND6
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
PL35B
PL36A
PL36B
GND6
U2
VCCJ
PL37A
PL37B
PL38A
PL38B
PL39A
PL39B
PL40A
GND6
PL40B
PL41A
PL41B
PL42A
PL42B
PL43A
PL43B
PL44A
PL44B
GND6
V1
T
C
T
C
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
T
C
T
C
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
V1
T
C
T
C
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
V2
V2
V2
U3
U3
V3
U3
V3
V3
U4
U4
V5
U4
V5
V5
W1
GND
W2
Y1
W1
GND
W2
Y1
W1
GND
W2
Y1
C
T
C
T
C
T
LDQS24
LDQS33
LDQS41
Y2
C
T
Y2
C
T
Y2
C
T
AA1
AA2
W4
V4
AA1
AA2
W4
V4
AA1
AA2
W4
V4
C
T
C
T
C
T
C
T
C
T
C
T
W3
Y3
VREF1_6
VREF2_6
W3
Y3
VREF1_6
VREF2_6
W3
Y3
VREF1_6
VREF2_6
C
C
C
GND
GND
GND
4-39
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
GND
V7
GND5
NC
5
-
GND
V7
GND5
PB2A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
GND
V7
GND5
PB2A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
T6
NC
-
T6
PB2B
T6
PB2B
V8
NC
-
V8
PB3A
V8
PB3A
U7
NC
-
U7
PB3B
U7
PB3B
W5
NC
-
W5
PB4A
W5
PB4A
U6
NC
-
U6
PB4B
U6
PB4B
AA3
AB3
Y6
NC
-
AA3
AB3
Y6
PB5A
AA3
AB3
Y6
PB5A
NC
-
PB5B
PB5B
NC
-
PB6A
BDQS6
PB6A
BDQS6
V6
NC
-
V6
PB6B
V6
PB6B
AA5
W6
NC
-
AA5
W6
PB7A
AA5
W6
PB7A
NC
-
PB7B
PB7B
Y5
NC
-
Y5
PB8A
Y5
PB8A
Y4
NC
-
Y4
PB8B
Y4
PB8B
AA4
GND
AB4
Y7
NC
-
AA4
GND
AB4
Y7
PB9A
AA4
GND
AB4
Y7
PB9A
-
-
GND5
PB9B
GND5
PB9B
NC
-
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
PB2A
PB2B
PB3A
PB3B
PB4A
PB4B
PB5A
-
5
5
5
5
5
5
5
-
T
C
T
C
T
C
T
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND5
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND5
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
W8
W8
W8
W7
W7
W7
U8
U8
U8
W9
W9
W9
U9
U9
U9
Y8
Y8
Y8
GND
Y9
GND
Y9
GND
Y9
PB5B
PB6A
PB6B
PB7A
PB7B
PB8A
PB8B
PB9A
GND5
PB9B
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
V9
BDQS6
V9
BDQS14
V9
BDQS14
T9
T9
T9
W10
U10
V10
T10
AA6
GND
AB5
AA8
AA7
AB6
AB7
Y10
W11
AB8
GND
AB9
AA10
AA9
Y11
AA11
V11
W10
U10
V10
T10
AA6
GND
AB5
AA8
AA7
AB6
AB7
Y10
W11
AB8
GND
AB9
AA10
AA9
Y11
AA11
V11
W10
U10
V10
T10
AA6
GND
AB5
AA8
AA7
AB6
AB7
Y10
W11
AB8
GND
AB9
AA10
AA9
Y11
AA11
V11
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
BDQS14
VREF2_5
BDQS22
VREF2_5
BDQS22
VREF2_5
4-40
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
V12
AB10
GND
AB11
Y12
PB16B
PB17A
GND5
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND4
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND4
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
-
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
C
T
VREF1_5
V12
AB10
GND
AB11
Y12
PB24B
PB25A
GND5
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND4
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GND4
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GND4
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
-
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
C
T
VREF1_5
V12
AB10
GND
AB11
Y12
PB24B
PB25A
GND5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
C
T
VREF1_5
PCLKT5_0
PCLKT5_0
PCLKT5_0
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND4
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
U11
U11
U11
W12
U12
VREF1_4
CSN
W12
U12
VREF1_4
CSN
W12
U12
VREF1_4
CSN
W13
U13
VREF2_4
D0/SPID7
D2/SPID5
W13
U13
VREF2_4
D0/SPID7
D2/SPID5
W13
U13
VREF2_4
D0/SPID7
D2/SPID5
AA12
GND
AB12
T13
AA12
GND
AB12
T13
AA12
GND
AB12
T13
C
T
C
T
C
T
C
T
D1/SPID6
BDQS22
D3/SPID4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS30
D3/SPID4
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GND4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS30
D3/SPID4
V13
V13
V13
W14
U14
W14
U14
W14
U14
D4/SPID3
D5/SPID2
D4/SPID3
D5/SPID2
D4/SPID3
D5/SPID2
Y13
Y13
Y13
V14
V14
V14
AA13
GND
AB13
AA14
Y14
AA13
GND
AB13
AA14
Y14
AA13
GND
AB13
AA14
Y14
C
T
C
T
C
T
C
T
D6/SPID1
C
T
C
T
C
T
C
T
D6/SPID1
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GND4
C
T
C
T
C
T
C
T
D6/SPID1
Y15
Y15
Y15
W15
V15
W15
V15
W15
V15
T14
T14
T14
AB14
GND
AB15
AB16
AA15
AB17
AA16
AB18
AA17
AB19
GND
AA18
W16
U15
AB14
GND
AB15
AB16
AA15
AB17
AA16
AB18
AA17
AB19
GND
AA18
W16
U15
AB14
GND
AB15
AB16
AA15
AB17
AA16
AB18
AA17
AB19
GND
AA18
W16
U15
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
GND4
C
T
C
T
C
T
C
T
BDQS30
BDQS38
BDQS38
PB33B
NC
4
-
C
PB41B
NC
4
-
C
PB41B
PB42A
PB42B
PB43A
PB43B
PB44A
PB44B
PB45A
GND4
C
T
C
T
C
T
C
T
NC
-
NC
-
V16
NC
-
V16
NC
-
V16
U16
NC
-
U16
NC
-
U16
Y17
NC
-
Y17
NC
-
Y17
V17
NC
-
V17
NC
-
V17
AB20
GND
AA19
Y16
NC
-
AB20
GND
AA19
Y16
NC
-
AB20
GND
AA19
Y16
-
-
-
-
NC
-
NC
-
PB45B
PB46A
C
T
NC
-
NC
-
BDQS46
4-41
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
W17
AA20
Y19
Y18
W18
T17
NC
NC
-
-
W17
AA20
Y19
NC
-
-
W17
AA20
Y19
Y18
W18
T17
PB46B
PB47A
PB47B
PB48A
PB48B
PB49A
PB49B
GND4
GND3
PR44B
PR44A
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
PR40B
GND3
PR40A
PR39B
PR39A
PR38B
PR38A
PR37B
PR37A
CFG2
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
NC
NC
-
NC
-
C
T
NC
-
Y18
NC
-
NC
-
W18
T17
NC
-
C
T
NC
-
NC
-
U17
GND
GND
W20
Y20
AA21
AB21
W19
V19
Y21
AA22
V20
GND
U20
W21
Y22
V21
W22
U21
V22
T19
NC
-
U17
NC
-
U17
GND
GND
W20
Y20
AA21
AB21
W19
V19
Y21
AA22
V20
GND
U20
W21
Y22
V21
W22
U21
V22
T19
C
GND4
GND3
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
PR23A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
CFG2
CFG1
CFG0
PROGRAMN
CCLK
INITN
DONE
NC
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
GND
GND
W20
Y20
GND4
GND3
PR36B
PR36A
PR35B
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
GND3
PR32A
PR31B
PR31A
PR30B
PR30A
PR29B
PR29A
CFG2
CFG1
CFG0
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
VREF2_3
VREF1_3
C
T
VREF2_3
VREF1_3
C
T
VREF2_3
VREF1_3
C
T
AA21
AB21
W19
V19
C
T
C
T
C
T
C
T
C
T
C
T
Y21
C
T
C
T
RDQS24
AA22
RDQS33
RDQS41
C
RLM0_PLLC_FB_A V20
GND
C
RLM0_PLLC_FB_A
C
RLM0_PLLC_FB_A
T
C
T
C
T
C
T
RLM0_PLLT_FB_A
U20
T
C
T
C
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
DI/CSSPIN
T
C
T
C
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
DI/CSSPIN
RLM0_PLLC_IN_A W21
RLM0_PLLT_IN_A
DI/CSSPIN
Y22
V21
W22
U21
V22
T19
U19
U18
DOUT/CSON
BUSY/SISPI
D7/SPID0
DOUT/CSON
DOUT/CSON
BUSY/SISPI
BUSY/SISPI
D7/SPID0
D7/SPID0
U19
U18
V18
T20
U19
U18
V18
T20
CFG1
CFG0
V18 PROGRAMN
PROGRAMN
CCLK
T20
T21
R20
T18
R17
R19
R18
U22
GND
T22
R21
R22
P20
N20
P19
P18
P21
GND
P22
N21
CCLK
INITN
DONE
NC
T21
T21
INITN
R20
T18
R20
T18
DONE
NC
R17
R19
R18
U22
GND
T22
NC
-
NC
-
R17
R19
R18
U22
GND
T22
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
PR35B
GND3
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
GND3
PR31A
PR30B
3
3
3
3
3
3
3
3
3
3
3
3
3
C
-
-
-
-
NC
-
NC
-
T
C
T
R21
R22
P20
N20
P19
P18
P21
GND
P22
N21
NC
-
NC
-
R21
R22
P20
N20
P19
P18
P21
GND
P22
N21
NC
-
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
PR18B
GND3
PR18A
PR17B
3
3
3
3
C
PR27B
GND3
PR27A
PR26B
3
3
3
3
C
C
T
T
T
C
C
C
4-42
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
N22
N19
N18
M21
L20
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND3
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
GND2
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
PR5B
-
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
-
T
C
T
N22
N19
N18
M21
L20
L21
GND
M20
M18
M19
M22
L22
K22
K21
J22
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
PR23A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
PR18B
GND2
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND2
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
NC
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
T
C
T
N22
N19
N18
M21
L20
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
GND3
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR22B
GND2
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR18B
GND2
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND2
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
T
C
T
C
T
C
T
C
T
RDQS15
RDQS24
RDQS28
L21
C
C
L21
C
GND
M20
M18
M19
M22
L22
GND
M20
M18
M19
M22
L22
T
C
T
T
C
T
T
C
T
C
T
C
T
C
T
K22
K21
J22
C
T
C
T
K22
K21
J22
C
T
C
PCLKC2_0
PCLKT2_0
C
PCLKC2_0
PCLKT2_0
C
PCLKC2_0
PCLKT2_0
GND
J21
GND
J21
GND
J21
T
C
T
T
C
T
T
C
T
H22
H21
L19
H22
H21
L19
L18
K20
J20
H22
H21
L19
C
T
C
T
C
T
L18
L18
K20
J20
C
T
C
T
K20
J20
C
T
RDQS6
RDQS15
RDQS19
K19
GND
K18
G22
F22
F21
E22
E21
D22
G21
G20
GND
J18
C
K19
GND
K18
G22
F22
F21
E22
E21
D22
G21
G20
-
C
K19
GND
K18
G22
F22
F21
E22
E21
D22
G21
GND
G20
J18
C
PR5A
PR4B
PR4A
PR3B
PR3A
NC
2
2
2
2
2
-
T
C
T
C
T
T
C
T
C
T
C
T
T
C
T
C
T
C
T
NC
-
NC
-
C
NC
-
NC
-
-
-
-
-
T
C
T
NC
-
J18
NC
-
H19
J19
NC
-
H19
J19
NC
-
H19
J19
NC
-
NC
-
C
T
H20
H17
H18
D21
GND
C22
G19
G18
F20
F19
E20
D20
NC
-
H20
H17
H18
D21
GND
C22
G19
G18
F20
F19
E20
D20
NC
-
H20
H17
H18
D21
GND
C22
G19
G18
F20
F19
E20
D20
NC
-
NC
-
C
T
NC
-
NC
-
NC
-
PR9B
GND2
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
2
2
2
2
2
2
2
2
2
C
RUM0_PLLC_FB_A
C
RUM0_PLLC_FB_A
-
-
GND2
PR9A
NC
-
T
C
T
C
T
C
T
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
T
C
T
C
T
C
T
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
NC
-
PR8B
NC
-
PR8A
NC
-
PR7B
NC
-
PR7A
NC
-
PR6B
NC
-
RDQS6
PR6A
RDQS6
4-43
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
C21
C20
F18
E18
B22
B21
E19
D19
GND
GND
G17
F17
D18
C18
C19
B20
D17
C16
B19
GND
A20
E17
C17
F16
E16
F15
D16
B18
GND
A19
B17
A18
B16
A17
B15
A16
A15
GND
A14
G14
E15
D15
C15
C14
B14
A13
GND
B13
E14
C13
NC
NC
-
-
C21
C20
F18
E18
B22
B21
E19
D19
GND
GND
G17
F17
D18
C18
C19
B20
D17
C16
B19
GND
A20
E17
C17
F16
E16
F15
D16
B18
GND
A19
B17
A18
B16
A17
B15
A16
A15
GND
A14
G14
E15
D15
C15
C14
B14
A13
GND
B13
E14
C13
PR5B
PR5A
PR4B
PR4A
PR3B
PR3A
PR2B
PR2A
GND2
GND1
NC
2
2
2
2
2
2
2
2
2
1
-
C
T
C
T
C
T
C
T
C21
C20
F18
E18
B22
B21
E19
D19
GND
GND
G17
F17
D18
C18
C19
B20
D17
C16
B19
GND
A20
E17
C17
F16
E16
F15
D16
B18
GND
A19
B17
A18
B16
A17
B15
A16
A15
GND
A14
G14
E15
D15
C15
C14
B14
A13
GND
B13
E14
C13
PR5B
PR5A
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
T
C
T
C
T
C
T
NC
-
PR4B
NC
-
PR4A
NC
-
PR3B
NC
-
PR3A
PR2B
PR2A
GND2
GND1
NC
2
2
2
1
-
C
T
VREF1_2
VREF2_2
VREF1_2
VREF2_2
PR2B
VREF1_2
VREF2_2
PR2A
GND2
GND1
PT49B
PT49A
PT48B
PT48A
PT47B
PT47A
PT46B
PT46A
PT45B
GND1
PT45A
PT44B
PT44A
PT43B
PT43A
PT42B
PT42A
PT41B
GND1
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
GND1
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
GND1
PT33A
PT32B
PT32A
C
T
NC
-
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
TDQS46
NC
-
NC
-
C
-
-
-
-
NC
-
NC
-
T
C
T
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
PT33B
-
1
-
C
PT41B
-
1
-
C
C
PT33A
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND1
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
PT25B
GND1
PT25A
PT24B
PT24A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T
C
T
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
GND1
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
GND1
PT33A
PT32B
PT32A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
TDQS30
TDQS38
TDQS38
C
C
C
T
C
T
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
C
C
T
C
T
T
C
T
T
C
T
4-44
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
F14
D14
E13
G13
A12
GND
B12
F13
D13
F12
D12
F11
C12
A11
GND
A10
E12
E11
B11
C11
B9
PT23B
PT23A
PT22B
PT22A
PT21B
GND1
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
PT9B
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
T
F14
D14
E13
G13
A12
GND
B12
F13
D13
F12
D12
F11
C12
A11
GND
A10
E12
E11
B11
C11
B9
PT31B
PT31A
PT30B
PT30A
PT29B
GND1
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
GND0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
T
F14
D14
E13
G13
A12
GND
B12
F13
D13
F12
D12
F11
C12
A11
GND
A10
E12
E11
B11
C11
B9
PT31B
PT31A
PT30B
PT30A
PT29B
GND1
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
GND0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
T
C
T
C
T
C
T
TDQS22
TDQS30
TDQS30
C
C
C
T
C
T
T
C
T
T
C
T
C
T
VREF2_1
VREF1_1
C
T
VREF2_1
VREF1_1
C
T
VREF2_1
VREF1_1
C
T
C
T
C
T
C
PCLKC0_0
C
PCLKC0_0
C
PCLKC0_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
C
T
C
T
C
T
C
T
C
T
C
T
B10
A9
TDQS14
B10
A9
TDQS22
B10
A9
TDQS22
C
C
C
GND
A8
GND
A8
GND
A8
T
C
T
T
C
T
T
C
T
D11
C10
A7
D11
C10
A7
D11
C10
A7
C
T
C
T
C
T
A6
A6
A6
B7
C
T
B7
C
T
B7
C
T
B8
B8
B8
A5
C
A5
C
A5
C
GND
B6
GND0
PT9A
GND
B6
GND
B6
T
C
T
T
C
T
T
C
T
G10
E10
F10
D10
G9
PT8B
G10
E10
F10
D10
G9
G10
E10
F10
D10
G9
PT8A
PT7B
C
T
C
T
C
T
PT7A
PT6B
C
T
C
T
C
T
E9
PT6A
TDQS6
E9
TDQS14
E9
TDQS14
C9
PT5B
C
C9
C
C9
C
GND
C8
-
GND
C8
GND
C8
PT5A
0
0
0
0
0
0
0
0
T
C
T
C
T
C
T
T
C
T
C
T
C
T
T
C
T
C
T
C
T
F9
PT4B
F9
F9
D9
PT4A
D9
D9
F8
PT3B
F8
F8
D7
PT3A
D7
D7
D8
PT2B
D8
D8
C7
PT2A
C7
C7
GND
GND0
GND
GND
4-45
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
A4
B4
NC
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A4
B4
PT9B
PT9A
PT8B
PT8A
PT7B
PT7A
PT6B
PT6A
PT5B
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
PT2A
GND0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
A4
B4
PT9B
PT9A
PT8B
PT8A
PT7B
PT7A
PT6B
PT6A
PT5B
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
PT2A
GND0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C4
NC
C4
C4
C5
NC
C5
C5
D6
NC
D6
D6
B5
NC
B5
B5
E6
NC
E6
E6
C6
NC
C6
TDQS6
C6
TDQS6
A3
NC
A3
A3
B3
NC
B3
B3
F6
NC
F6
F6
D5
NC
D5
D5
F7
NC
F7
F7
E8
NC
E8
E8
G6
NC
G6
G6
E7
NC
E7
E7
GND
A1
-
GND
A1
GND
A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A22
AB1
AB22
H15
H8
A22
AB1
AB22
H15
H8
-
A22
AB1
AB22
H15
H8
-
-
-
-
-
-
-
-
-
J10
J11
J12
J13
J14
J9
J10
J11
J12
J13
J14
J9
-
J10
J11
J12
J13
J14
J9
-
-
-
-
-
-
-
-
-
-
-
K10
K11
K12
K13
K14
K9
K10
K11
K12
K13
K14
K9
-
K10
K11
K12
K13
K14
K9
-
-
-
-
-
-
-
-
-
-
-
L10
L11
L12
L13
L14
L9
L10
L11
L12
L13
L14
L9
-
L10
L11
L12
L13
L14
L9
-
-
-
-
-
-
-
-
-
-
-
M10
M11
M12
M13
M14
M9
M10
M11
M12
M13
M14
M9
-
M10
M11
M12
M13
M14
M9
-
-
-
-
-
-
-
-
-
-
-
N10
N11
N12
N10
N11
N12
-
N10
N11
N12
-
-
-
-
-
4-46
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
N13
N14
N9
GND
GND
-
-
N13
N14
N9
GND
GND
-
-
N13
N14
N9
GND
GND
-
-
GND
-
GND
-
GND
-
P10
P11
P12
P13
P14
P9
GND
-
P10
P11
P12
P13
P14
P9
GND
-
P10
P11
P12
P13
P14
P9
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
R15
R8
GND
-
R15
R8
GND
-
R15
R8
GND
-
GND
-
GND
-
GND
-
J16
J7
VCC
-
J16
J7
VCC
-
J16
J7
VCC
-
VCC
-
VCC
-
VCC
-
K16
K17
K6
VCC
-
K16
K17
K6
VCC
-
K16
K17
K6
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
K7
VCC
-
K7
VCC
-
K7
VCC
-
L17
L6
VCC
-
L17
L6
VCC
-
L17
L6
VCC
-
VCC
-
VCC
-
VCC
-
M17
M6
VCC
-
M17
M6
VCC
-
M17
M6
VCC
-
VCC
-
VCC
-
VCC
-
N16
N17
N6
VCC
-
N16
N17
N6
VCC
-
N16
N17
N6
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
N7
VCC
-
N7
VCC
-
N7
VCC
-
P16
P7
VCC
-
P16
P7
VCC
-
P16
P7
VCC
-
VCC
-
VCC
-
VCC
-
G11
H10
H11
H9
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
G11
H10
H11
H9
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
G11
H10
H11
H9
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
G12
H12
H13
H14
J15
K15
L15
L16
M15
M16
N15
P15
R12
R13
R14
T12
R10
R11
R9
G12
H12
H13
H14
J15
K15
L15
L16
M15
M16
N15
P15
R12
R13
R14
T12
R10
R11
R9
G12
H12
H13
H14
J15
K15
L15
L16
M15
M16
N15
P15
R12
R13
R14
T12
R10
R11
R9
4-47
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
LFECP6/LFEC6
LFECP10/LFEC10
LFECP/LFEC15
Ball
Number
Ball
Dual
Function
Ball
Ball
Dual
Function
Ball
Number
Ball
Function Bank LVDS
Dual
Function
Function Bank LVDS
Number Function Bank LVDS
T11
M7
M8
N8
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCC
5
6
6
6
6
7
7
7
7
-
T11
M7
M8
N8
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCC
5
6
6
6
6
7
7
7
7
-
T11
M7
M8
N8
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCC
5
6
6
6
6
7
7
7
7
-
P8
P8
P8
J8
J8
J8
K8
K8
K8
L7
L7
L7
L8
L8
L8
G15
G16
G7
G8
H16
H7
G15
G16
G7
G8
H16
H7
G15
G16
G7
G8
H16
H7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R16
R7
-
R16
R7
-
R16
R7
-
-
-
-
T15
T16
T7
-
T15
T16
T7
-
T15
T16
T7
-
-
-
-
-
-
-
T8
-
T8
-
T8
-
J6
-
J6
-
J6
-
J17
P6
VCC
-
J17
P6
VCC
-
J17
P6
VCC
-
VCC
-
VCC
-
VCC
-
P17
A2
VCC
-
P17
A2
VCC
-
P17
A2
VCC
-
NC
-
NC
-
NC
-
AB2
A21
NC
-
AB2
A21
NC
-
AB2
A21
NC
-
NC
-
NC
-
NC
-
4-48
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA
LFECP20/LFEC20
LFECP/LFEC33
LVD
S
LVD
S
Ball Number Ball Function Bank
Dual Function
Ball Number Ball Function Bank
Dual Function
GND
D4
E4
GND7
PL2A
PL2B
-
7
7
7
-
GND
D4
E4
GND7
PL2A
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
T
VREF2_7
VREF1_7
T
VREF2_7
VREF1_7
C
PL2B
C
GND
C3
B2
GND
C3
B2
GND7
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
GND7
PL14A
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
GND7
PL17B
GND7
PL23A
PL23B
PL24A
PL24B
PL25A
PL25B
PL26A
GND7
PL26B
PL27A
PL27B
PL28A
PL28B
PL29A
PL29B
PL30A
GND7
PL30B
PL31A
PL31B
PL32A
PL32B
PL3A
PL3B
PL4A
PL4B
PL5A
PL5B
-
7
7
7
7
7
7
-
T
C
T
T
C
T
E5
E5
F5
C
T
F5
C
T
D3
C2
GND
F4
D3
C2
GND
F4
C
C
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
GND7
PL9B
-
7
7
7
7
7
7
7
7
7
-
T
C
T
C
T
C
T
LDQS6
T
C
T
C
T
C
T
LDQS14
G4
E3
G4
E3
D2
B1
D2
B1
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
C1
F3
C1
F3
GND
E2
GND
E2
C
LUM0_PLLC_FB_A
C
LUM0_PLLC_FB_A
LDQS23
GND
G5
H6
G3
H4
J5
GND
G5
H6
G3
H4
J5
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
GND7
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND7
PL18B
PL19A
PL19B
PL20A
PL20B
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
T
C
T
C
T
C
T
T
C
T
C
T
C
T
H5
F2
H5
F2
GND
F1
GND
F1
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
E1
E1
D1
H3
G2
H2
G1
J4
D1
H3
G2
H2
G1
J4
GND
J3
GND
J3
C
T
C
T
J2
LDQS19
J2
LDQS31
H1
K4
C
T
H1
K4
C
T
K5
C
K5
C
4-49
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
LVD
Ball Number Ball Function Bank
S
Dual Function
Ball Number Ball Function Bank
S
T
C
T
Dual Function
K3
K2
PL21A
PL21B
PL22A
GND7
PL22B
XRES
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
GND6
PL27B
PL28A
PL28B
PL29A
PL29B
PL30A
PL30B
PL31A
GND6
PL31B
PL32A
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
GND6
PL35B
PL36A
PL36B
PL37A
PL37B
GND6
TCK
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T
C
T
K3
K2
PL33A
PL33B
PL34A
GND7
PL34B
XRES
PL36A
PL36B
PL37A
PL37B
PL38A
PL38B
PL39A
GND6
PL39B
PL40A
PL40B
PL41A
PL41B
PL42A
PL42B
PL43A
GND6
PL43B
PL44A
PL44B
PL45A
PL45B
PL46A
PL46B
PL47A
GND6
PL47B
PL48A
PL48B
PL49A
PL49B
GND6
TCK
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
J1
PCLKT7_0
PCLKC7_0
J1
PCLKT7_0
PCLKC7_0
GND
K1
GND
K1
C
C
L3
L3
L4
T
C
T
C
T
C
T
L4
T
C
T
C
T
C
T
L5
L5
L2
L2
L1
L1
M4
M5
M1
GND
M2
N3
M3
N5
N4
N1
N2
P1
M4
M5
M1
GND
M2
N3
M3
N5
N4
N1
N2
P1
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
LDQS28
LDQS40
GND
P2
GND
P2
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
R6
P5
R6
P5
P3
P3
P4
P4
R1
R2
R5
GND
R4
T1
R1
R2
R5
GND
R4
T1
C
T
C
T
LDQS36
LDQS48
T2
C
T
T2
C
T
R3
T3
R3
T3
C
C
GND
T5
GND
T5
U5
T4
TDI
U5
T4
TDI
TMS
TMS
U1
U2
V1
TDO
U1
U2
V1
TDO
VCCJ
PL41A
VCCJ
PL53A
T
LLM0_PLLT_IN_A
T
LLM0_PLLT_IN_A
4-50
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
LVD
Ball Number Ball Function Bank
S
Dual Function
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
Ball Number Ball Function Bank
S
C
T
C
T
C
T
Dual Function
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
V2
U3
PL41B
PL42A
PL42B
PL43A
PL43B
PL44A
GND6
PL44B
PL45A
PL45B
PL46A
PL46B
PL47A
PL47B
PL48A
PL48B
GND6
GND5
-
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
C
T
C
T
C
T
V2
U3
PL53B
PL54A
PL54B
PL55A
PL55B
PL56A
GND6
PL56B
PL57A
PL57B
PL58A
PL58B
PL59A
PL59B
PL68A
PL68B
GND6
GND6
GND6
GND5
GND5
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
V3
V3
U4
U4
V5
V5
W1
GND
W2
Y1
W1
GND
W2
Y1
C
T
C
T
LDQS45
LDQS57
Y2
C
T
Y2
C
T
AA1
AA2
W4
V4
AA1
AA2
W4
V4
C
T
C
T
C
T
C
T
W3
Y3
VREF1_6
VREF2_6
W3
Y3
VREF1_6
VREF2_6
C
C
GND
GND
GND
GND
GND
V7
GND
GND
GND
GND
GND
V7
-
GND5
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
T
C
T
C
T
C
T
T
C
T
C
T
C
T
T6
T6
V8
V8
U7
U7
W5
U6
W5
U6
AA3
GND
AB3
Y6
AA3
GND
AB3
Y6
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
BDQS14
BDQS14
V6
V6
AA5
W6
Y5
AA5
W6
Y5
Y4
Y4
AA4
GND
AB4
Y7
AA4
GND
AB4
Y7
C
T
C
T
C
T
C
T
C
T
C
T
W8
W7
U8
W8
W7
U8
W9
W9
4-51
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
LVD
Ball Number Ball Function Bank
S
Dual Function
Ball Number Ball Function Bank
S
C
T
Dual Function
U9
Y8
PB20B
PB21A
GND5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
C
T
U9
Y8
PB20B
PB21A
GND5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
GND
Y9
GND
Y9
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND5
C
T
C
T
C
T
C
T
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND5
C
T
C
T
C
T
C
T
V9
BDQS22
V9
BDQS22
T9
T9
W10
U10
V10
T10
W10
U10
V10
T10
AA6
GND
AB5
AA8
AA7
AB6
AB7
Y10
W11
AB8
GND
AB9
AA10
AA9
Y11
AA11
V11
V12
AB10
GND
AB11
Y12
U11
W12
U12
W13
U13
AA12
GND
AB12
T13
AA6
GND
AB5
AA8
AA7
AB6
AB7
Y10
W11
AB8
GND
AB9
AA10
AA9
Y11
AA11
V11
V12
AB10
GND
AB11
Y12
U11
W12
U12
W13
U13
AA12
GND
AB12
T13
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND5
C
T
C
T
C
T
C
T
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND5
C
T
C
T
C
T
C
T
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GND5
C
T
C
T
C
T
C
T
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GND5
C
T
C
T
C
T
C
T
BDQS30
BDQS30
VREF2_5
VREF1_5
PCLKT5_0
VREF2_5
VREF1_5
PCLKT5_0
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GND4
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GND4
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
VREF1_4
CSN
VREF1_4
CSN
VREF2_4
D0/SPID7
D2/SPID5
VREF2_4
D0/SPID7
D2/SPID5
PB37B
PB38A
PB38B
PB39A
PB39B
C
T
D1/SPID6
BDQS38
D3/SPID4
PB37B
PB38A
PB38B
PB39A
PB39B
C
T
D1/SPID6
BDQS38
D3/SPID4
V13
W14
U14
C
T
V13
W14
U14
C
T
C
D4/SPID3
C
D4/SPID3
4-52
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
LVD
Ball Number Ball Function Bank
S
Dual Function
Ball Number Ball Function Bank
S
T
C
T
Dual Function
Y13
V14
PB40A
PB40B
PB41A
GND4
PB41B
PB42A
PB42B
PB43A
PB43B
PB44A
PB44B
PB45A
GND4
PB45B
PB46A
PB46B
PB47A
PB47B
PB48A
PB48B
PB49A
GND4
PB49B
PB50A
PB50B
PB51A
PB51B
PB52A
PB52B
PB53A
GND4
PB53B
PB54A
PB54B
PB55A
PB55B
PB56A
PB56B
PB57A
PB57B
-
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
T
C
T
Y13
V14
PB40A
PB40B
PB41A
GND4
PB41B
PB42A
PB42B
PB43A
PB43B
PB44A
PB44B
PB45A
GND4
PB45B
PB46A
PB46B
PB47A
PB47B
PB48A
PB48B
PB49A
GND4
PB49B
PB50A
PB50B
PB51A
PB51B
PB52A
PB52B
PB53A
GND4
PB53B
PB54A
PB54B
PB55A
PB55B
PB56A
PB56B
PB57A
PB57B
GND4
GND4
GND4
GND3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
D5/SPID2
D5/SPID2
AA13
GND
AB13
AA14
Y14
AA13
GND
AB13
AA14
Y14
C
T
C
T
C
T
C
T
D6/SPID1
C
T
C
T
C
T
C
T
D6/SPID1
Y15
Y15
W15
V15
W15
V15
T14
T14
AB14
GND
AB15
AB16
AA15
AB17
AA16
AB18
AA17
AB19
GND
AA18
W16
U15
AB14
GND
AB15
AB16
AA15
AB17
AA16
AB18
AA17
AB19
GND
AA18
W16
U15
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
BDQS46
BDQS46
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
V16
V16
U16
U16
Y17
Y17
V17
V17
AB20
GND
AA19
Y16
AB20
GND
AA19
Y16
C
T
C
T
BDQS54
BDQS54
W17
AA20
Y19
C
T
W17
AA20
Y19
C
T
C
T
C
T
Y18
Y18
W18
T17
C
T
W18
T17
C
T
U17
C
U17
C
GND
GND
GND
GND
GND
GND
GND
GND
GND4
GND3
-
4
3
-
4-53
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
LVD
Ball Number Ball Function Bank
S
Dual Function
VREF2_3
Ball Number Ball Function Bank
S
C
T
Dual Function
VREF2_3
W20
Y20
GND
GND
AA21
AB21
W19
V19
Y21
AA22
V20
GND
U20
W21
Y22
V21
W22
U21
V22
T19
PR48B
PR48A
-
3
3
-
C
T
W20
Y20
GND
GND
AA21
AB21
W19
V19
Y21
AA22
V20
GND
U20
W21
Y22
V21
W22
U21
V22
T19
PR68B
PR68A
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VREF1_3
VREF1_3
-
-
GND3
PR47B
PR47A
PR46B
PR46A
PR45B
PR45A
PR44B
GND3
PR44A
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
CFG2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
C
T
PR59B
PR59A
PR58B
PR58A
PR57B
PR57A
PR56B
GND3
C
T
C
T
C
T
C
T
C
T
RDQS45
RDQS57
C
RLM0_PLLC_IN_A
C
RLM0_PLLC_IN_A
T
C
T
C
T
C
T
RLM0_PLLT_IN_A
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
DI/CSSPIN
PR56A
PR55B
PR55A
PR54B
PR54A
PR53B
PR53A
CFG2
T
C
T
C
T
C
T
RLM0_PLLT_IN_A
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
DI/CSSPIN
DOUT/CSON
DOUT/CSON
BUSY/SISPI
BUSY/SISPI
D7/SPID0
D7/SPID0
U19
U18
V18
T20
CFG1
U19
U18
V18
T20
CFG1
CFG0
CFG0
PROGRAMN
CCLK
PROGRAMN
CCLK
T21
INITN
T21
INITN
R20
GND
T18
DONE
GND3
PR37B
PR37A
PR36B
PR36A
PR35B
GND3
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
GND3
PR31A
PR30B
R20
GND
T18
DONE
GND3
C
T
PR49B
PR49A
PR48B
PR48A
PR47B
GND3
C
T
R17
R19
R18
U22
GND
T22
R17
R19
R18
U22
GND
T22
C
T
C
T
RDQS36
RDQS48
C
C
T
C
T
PR47A
PR46B
PR46A
PR45B
PR45A
PR44B
PR44A
PR43B
GND3
T
C
T
R21
R22
P20
N20
P19
P18
P21
GND
P22
N21
R21
R22
P20
N20
P19
P18
P21
GND
P22
N21
C
T
C
T
C
T
C
T
C
C
T
PR43A
PR42B
T
C
C
4-54
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
LVD
Ball Number Ball Function Bank
S
Dual Function
Ball Number Ball Function Bank
S
T
C
T
C
T
C
Dual Function
N22
N19
N18
M21
L20
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
GND3
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR22B
GND2
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR18B
GND2
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
PR14A
GND2
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
T
C
T
N22
N19
N18
M21
L20
PR42A
PR41B
PR41A
PR40B
PR40A
PR39B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C
T
RDQS28
RDQS40
L21
C
L21
GND
M20
M18
M19
M22
L22
GND
M20
M18
M19
M22
L22
T
C
T
PR39A
PR38B
PR38A
PR37B
PR37A
PR36B
PR36A
PR34B
GND2
T
C
T
C
T
C
T
K22
K21
J22
C
T
K22
K21
J22
C
T
C
PCLKC2_0
PCLKT2_0
C
PCLKC2_0
PCLKT2_0
GND
J21
GND
J21
T
C
T
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
PR31A
PR30B
GND2
T
C
T
H22
H21
L19
H22
H21
L19
C
T
C
T
L18
L18
K20
J20
C
T
K20
J20
C
T
RDQS19
RDQS31
K19
GND
K18
G22
F22
F21
E22
E21
D22
G21
G20
GND
J18
C
K19
GND
K18
G22
F22
F21
E22
E21
D22
G21
G20
GND
J18
C
T
C
T
C
T
C
T
C
T
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
PR27A
PR26B
PR26A
GND2
T
C
T
C
T
C
T
C
T
C
T
PR25B
PR25A
PR24B
PR24A
PR23B
PR23A
PR17B
GND2
C
T
H19
J19
H19
J19
C
T
C
T
H20
H17
H18
D21
GND
GND
H20
H17
H18
D21
GND
GND
C
T
C
T
RDQS23
C
RUM0_PLLC_FB_A
C
RUM0_PLLC_FB_A
GND2
-
GND2
4-55
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
LVD
Ball Number Ball Function Bank
S
Dual Function
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
Ball Number Ball Function Bank
S
T
C
T
C
T
C
T
C
Dual Function
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
C22
G19
G18
F20
F19
E20
D20
C21
GND
C20
F18
E18
B22
B21
GND
E19
D19
GND
GND
GND
G17
GND
F17
D18
C18
C19
B20
D17
C16
B19
GND
A20
E17
C17
F16
E16
F15
D16
B18
GND
A19
B17
A18
B16
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
PR5B
-
2
2
2
2
2
2
2
2
-
T
C
T
C22
G19
G18
F20
F19
E20
D20
C21
GND
C20
F18
E18
B22
B21
GND
E19
D19
GND
GND
GND
G17
GND
F17
D18
C18
C19
B20
D17
C16
B19
GND
A20
E17
C17
F16
E16
F15
D16
B18
GND
A19
B17
A18
B16
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
PR14A
PR13B
GND2
PR13A
PR12B
PR12A
PR11B
PR11A
GND2
PR2B
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
T
C
T
RDQS6
RDQS14
C
PR5A
PR4B
PR4A
PR3B
PR3A
-
2
2
2
2
2
-
T
C
T
C
T
T
C
T
C
T
PR2B
PR2A
GND2
GND1
-
2
2
2
1
-
C
T
VREF1_2
VREF2_2
C
T
VREF1_2
VREF2_2
PR2A
GND2
GND1
GND1
PT57B
GND1
PT57A
PT56B
PT56A
PT55B
PT55A
PT54B
PT54A
PT53B
GND1
PT53A
PT52B
PT52A
PT51B
PT51A
PT50B
PT50A
PT49B
GND1
PT49A
PT48B
PT48A
PT47B
PT57B
-
1
-
C
C
PT57A
PT56B
PT56A
PT55B
PT55A
PT54B
PT54A
PT53B
GND1
PT53A
PT52B
PT52A
PT51B
PT51A
PT50B
PT50A
PT49B
GND1
PT49A
PT48B
PT48A
PT47B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T
C
T
T
C
T
C
T
C
T
C
T
C
T
TDQS54
TDQS54
C
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
C
T
C
T
T
C
T
C
C
4-56
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
LVD
S
T
Ball Number Ball Function Bank
S
Dual Function
Ball Number Ball Function Bank
Dual Function
A17
B15
A16
A15
GND
A14
G14
E15
D15
C15
C14
B14
A13
GND
B13
E14
C13
F14
D14
E13
G13
A12
GND
B12
F13
D13
F12
D12
F11
C12
A11
GND
A10
E12
E11
B11
C11
B9
PT47A
PT46B
PT46A
PT45B
GND1
PT45A
PT44B
PT44A
PT43B
PT43A
PT42B
PT42A
PT41B
GND1
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
GND1
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
GND0
PT33A
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND0
PT29A
PT28B
PT28A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
C
T
A17
B15
A16
A15
GND
A14
G14
E15
D15
C15
C14
B14
A13
GND
B13
E14
C13
F14
D14
E13
G13
A12
GND
B12
F13
D13
F12
D12
F11
C12
A11
GND
A10
E12
E11
B11
C11
B9
PT47A
PT46B
PT46A
PT45B
GND1
PT45A
PT44B
PT44A
PT43B
PT43A
PT42B
PT42A
PT41B
GND1
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
GND1
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
GND0
PT33A
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND0
PT29A
PT28B
PT28A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
T
TDQS46
TDQS46
C
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
TDQS38
TDQS38
C
C
T
C
T
T
C
T
C
T
VREF2_1
VREF1_1
C
T
VREF2_1
VREF1_1
C
T
C
T
C
PCLKC0_0
C
PCLKC0_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
C
T
C
T
C
T
C
T
B10
A9
TDQS30
B10
A9
TDQS30
C
C
GND
A8
GND
A8
T
C
T
T
C
T
D11
C10
D11
C10
4-57
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
LVD
Ball Number Ball Function Bank
S
Dual Function
Ball Number Ball Function Bank
S
C
T
Dual Function
A7
A6
PT27B
PT27A
PT26B
PT26A
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
GND0
PT17B
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
GND0
GND0
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
T
A7
A6
PT27B
PT27A
PT26B
PT26A
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
GND0
PT17B
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
GND0
GND0
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
B7
C
T
B7
C
T
B8
B8
A5
C
A5
C
GND
B6
GND
B6
T
C
T
T
C
T
G10
E10
F10
D10
G9
E9
G10
E10
F10
D10
G9
E9
C
T
C
T
C
T
C
T
TDQS22
TDQS22
C9
C
C9
C
GND
C8
GND
C8
T
C
T
C
T
C
T
T
C
T
C
T
C
T
F9
F9
D9
D9
F8
F8
D7
D7
D8
D8
C7
C7
GND
A4
GND
A4
C
T
C
T
B4
B4
C4
C
T
C4
C
T
C5
C5
D6
C
T
D6
C
T
B5
B5
E6
C
T
E6
C
T
C6
TDQS14
C6
TDQS14
A3
C
A3
C
GND
B3
GND
B3
T
C
T
C
T
C
T
T
C
T
C
T
C
T
F6
F6
D5
D5
F7
F7
E8
E8
G6
E7
G6
E7
GND
GND
A1
GND
GND
A1
A22
GND
-
A22
GND
-
4-58
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
S
LVD
S
Ball Number Ball Function Bank
Dual Function
Ball Number Ball Function Bank
Dual Function
AB1
AB22
H15
H8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AB1
AB22
H15
H8
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
J10
J11
J12
J13
J14
J9
J10
J11
J12
J13
J14
J9
K10
K11
K12
K13
K14
K9
K10
K11
K12
K13
K14
K9
L10
L11
L12
L13
L14
L9
L10
L11
L12
L13
L14
L9
M10
M11
M12
M13
M14
M9
M10
M11
M12
M13
M14
M9
N10
N11
N12
N13
N14
N9
N10
N11
N12
N13
N14
N9
P10
P11
P12
P13
P14
P9
P10
P11
P12
P13
P14
P9
R15
R8
R15
R8
J16
J7
J16
J7
4-59
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
S
LVD
S
Ball Number Ball Function Bank
Dual Function
Ball Number Ball Function Bank
Dual Function
K16
K17
K6
VCC
-
-
K16
K17
K6
VCC
-
-
VCC
VCC
VCC
-
VCC
-
K7
VCC
-
K7
VCC
-
L17
L6
VCC
-
L17
L6
VCC
-
VCC
-
VCC
-
M17
M6
VCC
-
M17
M6
VCC
-
VCC
-
VCC
-
N16
N17
N6
VCC
-
N16
N17
N6
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
N7
VCC
-
N7
VCC
-
P16
P7
VCC
-
P16
P7
VCC
-
VCC
-
VCC
-
G11
H10
H11
H9
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
G11
H10
H11
H9
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
G12
H12
H13
H14
J15
K15
L15
L16
M15
M16
N15
P15
R12
R13
R14
T12
R10
R11
R9
G12
H12
H13
H14
J15
K15
L15
L16
M15
M16
N15
P15
R12
R13
R14
T12
R10
R11
R9
T11
M7
T11
M7
M8
M8
N8
N8
P8
P8
J8
J8
K8
K8
4-60
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20 and LFECP/EC33 Logic Signal Connections: 484 fpBGA (Cont.)
LFECP20/LFEC20
LFECP/LFEC33
LVD
S
LVD
S
Ball Number Ball Function Bank
Dual Function
Ball Number Ball Function Bank
Dual Function
L7
VCCIO7
VCCIO7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCC1
7
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L7
L8
VCCIO7
VCCIO7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCPLL
VCCPLL
VCCPLL
VCCPLL
NC
7
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L8
G15
G15
G16
G7
G16
G7
G8
G8
H16
H16
H7
H7
R16
R16
R7
R7
T15
T15
T16
T7
T16
T7
T8
T8
J6
J6
J17
VCC1
VCC1
VCC1
J17
P6
P6
P17
P17
A2
A2
AB2
NC
NC
AB2
A21
NC
A21
NC
NC
1. Tied to VCCPLL.
4-61
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
GND
E3
E4
E5
D5
F4
F5
C3
D3
C2
-
GND7
PL2A
PL2B
NC
7
7
7
-
GND
E3
E4
E5
D5
F4
GND7
PL2A
7
T
VREF2_7
VREF1_7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
T
C
T
C
T
C
T
C
T
VREF2_7
VREF1_7
LDQS6
C
PL2B
PL6A
NC
-
PL6B
NC
-
PL7A
NC
-
F5
PL7B
NC
-
C3
D3
C2
GND
B2
B1
C1
F3
PL8A
NC
-
PL8B
NC
-
PL9A
-
-
GND7
PL9B
B2
B1
C1
F3
G3
D2
E2
-
NC
-
C
T
PL3A
PL3B
PL4A
PL4B
PL5A
PL5B
-
7
7
7
7
7
7
-
T
C
T
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
GND7
PL14A
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
GND7
PL17B
PL19A
PL19B
PL20A
PL20B
PL21A
PL21B
PL22A
GND7
PL22B
PL23A
PL23B
PL24A
PL24B
PL25A
C
T
C
T
G3
D2
E2
GND
D1
E1
F2
C
T
C
C
D1
E1
F2
G2
F6
G6
H4
GND
G4
H6
J7
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
PL9A
GND7
PL9B
NC
7
7
7
7
7
7
7
7
7
-
T
C
T
C
T
C
T
LDQS6
T
C
T
C
T
C
T
LDQS14
G2
F6
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
G6
H4
GND
G4
H6
J7
C
LUM0_PLLC_FB_A
C
T
C
T
C
T
C
T
LUM0_PLLC_FB_A
NC
-
G5
H5
H3
J3
NC
-
G5
H5
H3
J3
NC
-
NC
-
NC
-
H2
-
NC
-
H2
GND
J2
-
-
J2
NC
-
C
T
C
T
C
T
J4
PL11A
PL11B
PL12A
PL12B
PL13A
7
7
7
7
7
T
C
T
C
T
J4
LDQS23
J5
J5
K4
K5
J6
K4
K5
J6
4-62
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
K6
F1
PL13B
PL14A
GND7
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND7
PL18B
PL19A
PL19B
PL20A
PL20B
PL21A
PL21B
PL22A
GND7
PL22B
XRES
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
GND6
PL27B
PL28A
PL28B
PL29A
PL29B
PL30A
PL30B
PL31A
GND6
PL31B
PL32A
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
C
T
K6
F1
PL25B
PL26A
GND7
PL26B
PL27A
PL27B
PL28A
PL28B
PL29A
PL29B
PL30A
GND7
PL30B
PL31A
PL31B
PL32A
PL32B
PL33A
PL33B
PL34A
GND7
PL34B
XRES
PL36A
PL36B
PL37A
PL37B
PL38A
PL38B
PL39A
GND6
PL39B
PL40A
PL40B
PL41A
PL41B
PL42A
PL42B
PL43A
GND6
PL43B
PL44A
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
C
T
GND
G1
H1
J1
GND
G1
H1
J1
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
K2
K2
K1
K1
K3
K3
L3
L3
L2
L2
GND
L1
GND
L1
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
M3
M4
M1
M2
L4
LDQS19
M3
M4
M1
M2
L4
LDQS31
L5
L5
N2
GND
N1
N3
P1
PCLKT7_0
PCLKC7_0
N2
GND
N1
N3
P1
PCLKT7_0
PCLKC7_0
C
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
P2
P2
L7
L7
L6
L6
N4
N5
R1
GND
R2
P4
N4
N5
R1
GND
R2
P4
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
LDQS28
LDQS40
P3
P3
M5
M6
T1
M5
M6
T1
T2
T2
R4
GND
R3
N6
R4
GND
R3
N6
C
T
C
T
4-63
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
P5
P6
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
GND6
PL35B
PL36A
PL36B
PL37A
PL37B
PL38A
PL38B
PL39A
GND6
PL39B
TCK
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
C
T
C
T
C
T
P5
P6
PL44B
PL45A
PL45B
PL46A
PL46B
PL47A
GND6
PL47B
PL48A
PL48B
PL49A
PL49B
PL50A
PL50B
PL51A
GND6
PL51B
TCK
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
C
T
C
T
C
T
R5
R5
U1
U1
U2
U2
T3
T3
GND
T4
GND
T4
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
R6
LDQS36
R6
LDQS48
T5
T5
T6
T6
U5
U5
U3
U3
U4
U4
V1
V1
GND
V2
GND
V2
C
C
U7
U7
V4
TDI
V4
TDI
V5
TMS
V5
TMS
V3
TDO
V3
TDO
U6
VCCJ
PL41A
PL41B
PL42A
PL42B
PL43A
PL43B
PL44A
GND6
PL44B
PL45A
PL45B
PL46A
PL46B
PL47A
PL47B
NC
U6
VCCJ
W1
W2
V6
T
C
T
C
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
W1
W2
V6
PL53A
PL53B
PL54A
PL54B
PL55A
PL55B
PL56A
GND6
PL56B
PL57A
PL57B
PL58A
PL58B
PL59A
PL59B
PL60A
GND6
PL60B
PL61A
PL61B
T
C
T
C
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
W6
Y1
W6
Y1
Y2
Y2
W3
GND
W4
AA1
AB1
Y4
W3
GND
W4
AA1
AB1
Y4
C
T
C
T
C
T
C
T
C
T
LDQS45
LDQS57
C
T
Y3
C
T
Y3
AC1
AB2
AA2
-
AC1
AB2
AA2
GND
AA3
W5
Y5
C
-
-
AA3
W5
Y5
NC
-
C
T
NC
-
NC
-
C
4-64
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
Y6
W7
NC
NC
-
-
Y6
W7
PL62A
PL62B
PL63A
PL63B
PL64A
GND6
PL64B
PL65A
PL65B
PL66A
PL66B
PL67A
PL67B
PL68A
PL68B
GND6
GND5
PB2A
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
T
C
T
C
T
AA4
AB3
AC2
-
NC
-
AA4
AB3
AC2
GND
AC3
AA5
AB5
AD3
AD2
AE1
AD1
AB4
AC4
GND
GND
AB6
AA6
AC7
Y8
NC
-
NC
-
-
-
AC3
AA5
AB5
AD3
AD2
AE1
AD1
AB4
AC4
GND
GND
AB6
AA6
AC7
Y8
NC
-
C
T
NC
-
LDQS65
NC
-
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
T
PL48A
PL48B
GND6
GND5
PB2A
PB2B
PB3A
PB3B
PB4A
PB4B
PB5A
PB5B
PB6A
PB6B
PB7A
PB7B
PB8A
PB8B
PB9A
GND5
PB9B
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
T
VREF1_6
VREF2_6
VREF1_6
VREF2_6
C
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
PB2B
PB3A
PB3B
AB7
AA7
AC6
AC5
AB8
AC8
AE2
AA8
AF2
Y9
AB7
AA7
AC6
AC5
AB8
AC8
AE2
AA8
AF2
Y9
PB4A
PB4B
PB5A
PB5B
BDQS6
PB6A
BDQS6
PB6B
PB7A
PB7B
PB8A
PB8B
AD5
GND
AD4
AD8
AC9
AE3
AB9
AF3
AD9
AE4
GND
AD5
GND
AD4
AD8
AC9
AE3
AB9
AF3
AD9
AE4
GND
PB9A
GND5
PB9B
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
4-65
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
AF4
AE5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
C
T
C
T
C
T
C
T
AF4
AE5
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
C
T
C
T
C
T
C
T
BDQS14
BDQS14
AA9
AA9
AF5
AF5
Y10
Y10
AD6
AD6
AC10
AF6
AC10
AF6
GND
AE6
GND
AE6
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND5
C
T
C
T
C
T
C
T
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND5
C
T
C
T
C
T
C
T
AF7
AF7
AB10
AE7
AB10
AE7
AD10
AD7
AD10
AD7
AA10
AF8
AA10
AF8
GND
AF9
GND
AF9
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND5
C
T
C
T
C
T
C
T
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND5
C
T
C
T
C
T
C
T
AD11
Y11
BDQS22
AD11
Y11
BDQS22
AE8
AE8
AC11
AF10
AB11
AE10
GND
AE9
AC11
AF10
AB11
AE10
GND
AE9
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND5
C
T
C
T
C
T
C
T
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND5
C
T
C
T
C
T
C
T
AA11
Y12
AA11
Y12
AE11
AF11
AF12
AE12
AD12
GND
AC12
AA12
AB12
AE13
AF13
AD13
AE11
AF11
AF12
AE12
AD12
GND
AC12
AA12
AB12
AE13
AF13
AD13
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
C
T
C
T
C
T
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
C
T
C
T
C
T
BDQS30
VREF2_5
BDQS30
VREF2_5
4-66
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
VREF1_5
Number Function
Bank LVDS
AC13
AF14
GND
AE14
AA13
AB13
AD14
AA14
AC14
AB14
AF15
GND
AE15
AD15
AC15
AF16
Y14
PB32B
PB33A
GND5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
C
T
AC13
AF14
GND
AE14
AA13
AB13
AD14
AA14
AC14
AB14
AF15
GND
AE15
AD15
AC15
AF16
Y14
PB32B
PB33A
GND5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
C
T
VREF1_5
PCLKT5_0
PCLKT5_0
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GND4
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GND4
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
VREF1_4
CSN
VREF1_4
CSN
VREF2_4
D0/SPID7
D2/SPID5
VREF2_4
D0/SPID7
D2/SPID5
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
GND4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS38
D3/SPID4
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
GND4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS38
D3/SPID4
D4/SPID3
D5/SPID2
D4/SPID3
D5/SPID2
AE16
AB15
AF17
GND
AE17
Y15
AE16
AB15
AF17
GND
AE17
Y15
PB41B
PB42A
PB42B
PB43A
PB43B
PB44A
PB44B
PB45A
GND4
C
T
C
T
C
T
C
T
D6/SPID1
PB41B
PB42A
PB42B
PB43A
PB43B
PB44A
PB44B
PB45A
GND4
C
T
C
T
C
T
C
T
D6/SPID1
AA15
AD17
Y16
AA15
AD17
Y16
AD18
AC16
AE18
GND
AF18
AD16
AB16
AF19
AA16
AA17
Y17
AD18
AC16
AE18
GND
AF18
AD16
AB16
AF19
AA16
AA17
Y17
PB45B
PB46A
PB46B
PB47A
PB47B
PB48A
PB48B
PB49A
GND4
C
T
C
T
C
T
C
T
PB45B
PB46A
PB46B
PB47A
PB47B
PB48A
PB48B
PB49A
GND4
C
T
C
T
C
T
C
T
BDQS46
BDQS46
AF21
GND
AF20
AE21
AC17
AF21
GND
AF20
AE21
AC17
PB49B
PB50A
PB50B
C
T
PB49B
PB50A
PB50B
C
T
C
C
4-67
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
AF22
AB17
AE22
AA18
AE19
GND
AE20
AA19
Y18
PB51A
PB51B
PB52A
PB52B
PB53A
GND4
PB53B
PB54A
PB54B
PB55A
PB55B
PB56A
PB56B
PB57A
-
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
T
C
T
C
T
AF22
AB17
AE22
AA18
AE19
GND
AE20
AA19
Y18
PB51A
PB51B
PB52A
PB52B
PB53A
GND4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
T
C
T
C
T
C
T
C
T
C
T
C
T
PB53B
PB54A
PB54B
PB55A
PB55B
PB56A
PB56B
PB57A
GND4
C
T
C
T
C
T
C
T
BDQS54
BDQS54
AF23
AA20
AC18
AB18
AF24
-
AF23
AA20
AC18
AB18
AF24
GND
AE23
AD19
AD20
AC19
AB19
AD21
AC20
AF25
GND
AE25
AB21
AB20
AE24
AD23
AD22
AC21
AC22
AB22
GND
GND
AC23
AC24
AD24
AD25
AE26
AD26
Y20
AE23
AD19
AD20
AC19
AB19
AD21
AC20
AF25
-
PB57B
NC
4
-
C
PB57B
PB58A
PB58B
PB59A
PB59B
PB60A
PB60B
PB61A
GND4
C
T
C
T
C
T
C
T
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
-
-
AE25
AB21
AB20
AE24
AD23
AD22
AC21
AC22
AB22
GND
GND
AC23
AC24
AD24
AD25
AE26
AD26
Y20
NC
-
PB61B
PB62A
PB62B
PB63A
PB63B
PB64A
PB64B
PB65A
PB65B
GND4
C
T
NC
-
BDQS62
NC
-
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
GND4
GND3
PR48B
PR48A
NC
4
3
3
3
-
GND3
C
T
VREF2_3
VREF1_3
PR68B
PR68A
PR67B
PR67A
PR66B
PR66A
PR65B
C
T
VREF2_3
VREF1_3
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
4-68
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
Y19
AA23
-
NC
NC
-
-
Y19
AA23
GND
AA22
AB23
AB24
Y21
PR65A
PR64B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
T
RDQS65
C
-
-
AA22
AB23
AB24
Y21
NC
-
PR64A
PR63B
PR63A
PR62B
PR62A
PR61B
PR61A
PR60B
GND3
T
C
T
NC
-
NC
-
NC
-
C
T
AA21
Y23
NC
-
AA21
Y23
NC
-
C
T
Y22
NC
-
Y22
AA24
-
NC
-
AA24
GND
Y24
C
-
-
Y24
NC
-
PR60A
PR59B
PR59A
PR58B
PR58A
PR57B
PR57A
PR56B
GND3
T
C
T
AC25
AC26
AB25
AA25
AB26
AA26
W23
GND
W24
W22
W21
Y25
PR47B
PR47A
PR46B
PR46A
PR45B
PR45A
PR44B
GND3
PR44A
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
CFG2
CFG1
CFG0
PROGRAMN
CCLK
INITN
DONE
PR39B
GND3
PR39A
PR38B
PR38A
PR37B
PR37A
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
C
T
AC25
AC26
AB25
AA25
AB26
AA26
W23
GND
W24
W22
W21
Y25
C
T
C
T
C
T
C
T
RDQS45
RDQS57
C
RLM0_PLLC_IN_A
C
RLM0_PLLC_IN_A
T
C
T
C
T
C
T
RLM0_PLLT_IN_A
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
DI/CSSPIN
PR56A
PR55B
PR55A
PR54B
PR54A
PR53B
PR53A
CFG2
T
C
T
C
T
C
T
RLM0_PLLT_IN_A
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
DI/CSSPIN
Y26
DOUT/CSON
Y26
DOUT/CSON
W25
W26
V24
BUSY/SISPI
W25
W26
V24
BUSY/SISPI
D7/SPID0
D7/SPID0
V21
V21
CFG1
V23
V23
CFG0
V22
V22
PROGRAMN
CCLK
V20
V20
V25
V25
INITN
U20
V26
U20
DONE
PR51B
GND3
C
V26
C
GND
U26
U24
U25
U23
U22
GND
U26
T
C
T
C
T
PR51A
PR50B
PR50A
PR49B
PR49A
T
C
T
C
T
U24
U25
U23
U22
4-69
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
U21
T21
T25
GND
T26
T22
T23
T24
R23
R25
R24
R26
GND
P26
R21
R22
P25
P24
P23
P22
N26
GND
M26
N21
P21
N23
N22
N25
N24
L26
PR36B
PR36A
PR35B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
C
T
U21
T21
T25
GND
T26
T22
T23
T24
R23
R25
R24
R26
GND
P26
R21
R22
P25
P24
P23
P22
N26
GND
M26
N21
P21
N23
N22
N25
N24
L26
PR48B
PR48A
PR47B
GND3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
C
T
RDQS36
RDQS48
C
C
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
GND3
T
C
T
PR47A
PR46B
PR46A
PR45B
PR45A
PR44B
PR44A
PR43B
GND3
T
C
T
C
T
C
T
C
T
C
T
C
C
PR31A
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
GND3
T
C
T
PR43A
PR42B
PR42A
PR41B
PR41A
PR40B
PR40A
PR39B
GND3
T
C
T
C
T
C
T
C
T
C
T
RDQS28
RDQS40
C
C
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR22B
GND2
T
C
T
PR39A
PR38B
PR38A
PR37B
PR37A
PR36B
PR36A
PR34B
GND2
T
C
T
C
T
C
T
C
T
C
T
C
PCLKC2_0
PCLKT2_0
C
PCLKC2_0
PCLKT2_0
GND
K26
M22
M23
M25
M24
M21
L21
GND
K26
M22
M23
M25
M24
M21
L21
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR18B
GND2
T
C
T
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
PR31A
PR30B
GND2
T
C
T
C
T
C
T
C
T
C
T
RDQS19
RDQS31
L22
C
L22
C
GND
L23
GND
L23
PR18A
PR17B
T
PR30A
PR29B
T
L25
C
L25
C
4-70
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
L24
K25
J25
J26
H26
H25
GND
J24
K21
K22
K20
J20
K23
K24
J21
-
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND2
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
NC
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
T
C
T
L24
K25
J25
PR29A
PR28B
PR28A
PR27B
PR27A
PR26B
GND2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
T
C
T
C
T
J26
C
T
H26
H25
GND
J24
C
C
T
C
T
C
T
C
T
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
PR23A
PR22B
GND2
T
C
T
K21
K22
K20
J20
C
T
K23
K24
J21
C
T
RDQS23
C
-
-
GND
J22
J22
J23
H22
G26
F26
E26
E25
F25
GND
G25
H23
H24
H21
G21
D26
D25
F21
-
NC
-
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR17B
GND2
T
C
T
NC
-
J23
NC
-
H22
G26
F26
E26
E25
F25
GND
G25
H23
H24
H21
G21
D26
D25
F21
GND
G22
G24
G23
C26
C25
F24
GND
F23
NC
-
C
T
NC
-
NC
-
C
T
NC
-
PR9B
GND2
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
PR5B
-
2
2
2
2
2
2
2
2
2
2
-
C
RUM0_PLLC_FB_A
C
RUM0_PLLC_FB_A
T
C
T
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
PR14A
PR13B
GND2
T
C
T
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
C
T
C
T
C
T
C
T
RDQS6
RDQS14
C
C
G22
G24
G23
C26
C25
F24
-
PR5A
PR4B
PR4A
PR3B
PR3A
NC
2
2
2
2
2
-
T
C
T
C
T
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
T
C
T
C
T
C
-
-
GND2
F23
NC
-
PR9A
T
4-71
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
E24
D24
E22
F22
E21
D22
E23
D23
GND
GND
G20
F20
D21
C21
C23
C22
B23
C24
D20
-
NC
NC
-
-
E24
D24
E22
F22
E21
D22
E23
D23
GND
GND
G20
F20
D21
C21
C23
C22
B23
C24
D20
GND
E19
B25
B24
B26
A25
C20
C19
A24
GND
A23
E18
D19
F19
B22
G19
B21
D18
GND
C18
F18
A22
G18
PR8B
PR8A
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
T
C
T
C
T
C
T
NC
-
PR7B
NC
-
PR7A
NC
-
PR6B
NC
-
PR6A
RDQS6
VREF1_2
VREF2_2
PR2B
PR2A
GND2
GND1
NC
2
2
2
1
-
C
T
VREF1_2
VREF2_2
PR2B
PR2A
GND2
GND1
PT65B
PT65A
PT64B
PT64A
PT63B
PT63A
PT62B
PT62A
PT61B
GND1
PT61A
PT60B
PT60A
PT59B
PT59A
PT58B
PT58A
PT57B
GND1
PT57A
PT56B
PT56A
PT55B
PT55A
PT54B
PT54A
PT53B
GND1
PT53A
PT52B
PT52A
PT51B
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
TDQS62
NC
-
C
-
-
E19
B25
B24
B26
A25
C20
C19
A24
-
NC
-
T
C
T
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
PT57B
-
1
-
C
C
A23
E18
D19
F19
B22
G19
B21
D18
GND
C18
F18
A22
G18
PT57A
PT56B
PT56A
PT55B
PT55A
PT54B
PT54A
PT53B
GND1
PT53A
PT52B
PT52A
PT51B
1
1
1
1
1
1
1
1
1
1
1
1
1
T
C
T
T
C
T
C
T
C
T
C
T
C
T
TDQS54
TDQS54
C
C
T
C
T
T
C
T
C
C
4-72
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
A21
E17
B17
C17
GND
D17
F17
E20
G17
B20
E16
A20
A19
GND
B19
D16
C16
F16
A18
G16
B18
A17
GND
A16
D15
B16
E15
C15
F15
G15
B15
GND
A15
E14
G14
D14
E13
F14
C14
B14
GND
A14
PT51A
PT50B
PT50A
PT49B
GND1
PT49A
PT48B
PT48A
PT47B
PT47A
PT46B
PT46A
PT45B
GND1
PT45A
PT44B
PT44A
PT43B
PT43A
PT42B
PT42A
PT41B
GND1
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
GND1
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
GND0
PT33A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
T
C
T
A21
E17
B17
C17
GND
D17
F17
E20
G17
B20
E16
A20
A19
GND
B19
D16
C16
F16
A18
G16
B18
A17
GND
A16
D15
B16
E15
C15
F15
G15
B15
GND
A15
E14
G14
D14
E13
F14
C14
B14
GND
A14
PT51A
PT50B
PT50A
PT49B
GND1
PT49A
PT48B
PT48A
PT47B
PT47A
PT46B
PT46A
PT45B
GND1
PT45A
PT44B
PT44A
PT43B
PT43A
PT42B
PT42A
PT41B
GND1
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
GND1
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
GND0
PT33A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
T
C
T
C
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
TDQS46
TDQS46
C
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
TDQS38
TDQS38
C
C
T
C
T
T
C
T
C
T
VREF2_1
VREF1_1
C
T
VREF2_1
VREF1_1
C
T
C
T
C
PCLKC0_0
PCLKT0_0
C
PCLKC0_0
PCLKT0_0
T
T
4-73
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
VREF1_0
Number Function
Bank LVDS
D13
C13
A13
B13
F13
F12
A12
GND
B12
A11
B11
D12
C12
B10
A10
G12
GND
A9
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND0
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
T
D13
C13
A13
B13
F13
F12
A12
GND
B12
A11
B11
D12
C12
B10
A10
G12
GND
A9
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND0
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
T
VREF1_0
VREF2_0
VREF2_0
C
T
C
T
C
T
C
T
TDQS30
TDQS22
TDQS14
TDQS30
TDQS22
TDQS14
C
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
C
T
C
T
T
C
T
E12
B9
E12
B9
F11
A8
C
T
F11
A8
C
T
D11
C11
B8
C
T
D11
C11
B8
C
T
C
C
GND
B7
GND
B7
T
C
T
T
C
T
E11
A7
E11
A7
G11
C7
C
T
G11
C7
C
T
G10
C6
C
T
G10
C6
C
T
C10
GND
D10
F10
A6
C
C10
GND
D10
F10
A6
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
E10
C9
E10
C9
G9
G9
D9
D9
4-74
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
A5
GND
A4
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
PT9B
GND0
PT9A
PT8B
PT8A
PT7B
PT7A
PT6B
PT6A
PT5B
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
PT2A
GND0
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
A5
GND
A4
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
PT9B
GND0
PT9A
PT8B
PT8A
PT7B
PT7A
PT6B
PT6A
PT5B
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
PT2A
GND0
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
C
T
C
T
T
C
T
F9
F9
B6
B6
E9
C
T
E9
C
T
C8
C8
G8
C
T
G8
C
T
B5
B5
A3
C
A3
C
GND
A2
GND
A2
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
F8
F8
B4
B4
E8
E8
B3
B3
D8
D8
G7
TDQS6
G7
TDQS6
C4
C4
C5
C5
E7
E7
D4
D4
F7
F7
D6
D6
D7
D7
E6
E6
GND
K10
K11
K12
K13
K14
K15
K16
L10
L11
L12
L13
L14
L15
L16
L17
GND
K10
K11
K12
K13
K14
K15
K16
L10
L11
L12
L13
L14
L15
L16
L17
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
4-75
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
M10
M11
M12
M13
M14
M15
M16
M17
N10
N11
N12
N13
N14
N15
N16
N17
P10
P11
P12
P13
P14
P15
P16
P17
R10
R11
R12
R13
R14
R15
R16
R17
T10
T11
T12
T13
T14
T15
T16
T17
U10
U11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
M10
M11
M12
M13
M14
M15
M16
M17
N10
N11
N12
N13
N14
N15
N16
N17
P10
P11
P12
P13
P14
P15
P16
P17
R10
R11
R12
R13
R14
R15
R16
R17
T10
T11
T12
T13
T14
T15
T16
T17
U10
U11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4-76
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
U12
U13
U14
U15
U16
U17
H10
H11
H16
H17
H18
H19
H8
GND
GND
-
-
U12
U13
U14
U15
U16
U17
H10
H11
H16
H17
H18
H19
H8
GND
GND
-
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
GND
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
H9
VCC
-
H9
VCC
-
J18
J9
VCC
-
J18
J9
VCC
-
VCC
-
VCC
-
K8
VCC
-
K8
VCC
-
L19
M19
N7
VCC
-
L19
M19
N7
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
R20
R7
VCC
-
R20
R7
VCC
-
VCC
-
VCC
-
T19
V18
V8
VCC
-
T19
V18
V8
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
V9
VCC
-
V9
VCC
-
W10
W11
W16
W17
W18
W19
W8
VCC
-
W10
W11
W16
W17
W18
W19
W8
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
W9
VCC
-
W9
VCC
-
H12
H13
J10
J11
J12
J13
H14
H15
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
0
0
0
0
0
0
1
1
H12
H13
J10
J11
J12
J13
H14
H15
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
0
0
0
0
0
0
1
1
4-77
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
J14
J15
J16
J17
K17
K18
L18
M18
N18
N19
P18
P19
R18
R19
T18
U18
V14
V15
V16
V17
W14
W15
V10
V11
V12
V13
W12
W13
P8
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCAUX
VCCAUX
1
1
1
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
-
J14
J15
J16
J17
K17
K18
L18
M18
N18
N19
P18
P19
R18
R19
T18
U18
V14
V15
V16
V17
W14
W15
V10
V11
V12
V13
W12
W13
P8
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCAUX
VCCAUX
1
1
1
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
4
4
5
5
5
5
5
5
6
6
6
6
6
6
7
7
7
7
7
7
-
P9
P9
R8
R8
R9
R9
T9
T9
U9
U9
K9
K9
L9
L9
M8
M8
M9
M9
N8
N8
N9
N9
G13
H20
G13
H20
-
-
4-78
Pinout Information
LatticeECP/EC Family Data Sheet
LFECP/EC20, LFECP/EC33 Logic Signal Connections: 672 fpBGA (Cont.)
LFEC20/LFECP20
LFECP/EC33
Ball
Ball
Ball
Ball
Dual
Function
Number Function Bank LVDS
Dual Function
Number Function
Bank LVDS
H7
J19
J8
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCC1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H7
J19
J8
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCPLL
VCCPLL
VCCPLL
VCCPLL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K7
K7
L20
M20
M7
N20
P20
P7
L20
M20
M7
N20
P20
P7
T20
T7
T20
T7
T8
T8
V19
V7
V19
V7
W20
Y13
Y7
W20
Y13
Y7
K19
L8
K19
L8
VCC1
VCC1
VCC1
U19
U8
U19
U8
1. Tied to VCCPLL.
4-79
Pinout Information
LatticeECP/EC Family Data Sheet
Thermal Management
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal
characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.
Designers must complete a thermal analysis of their specific design to ensure that the device and package do not
exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package
specific thermal values.
For Further Information
For further information regarding Thermal Management, refer to the following located on the Lattice website at
www.latticesemi.com.
• Thermal Management document
• Technical Note TN1052 - Power Estimation and Management for LatticeECP/EC and LatticeXP Devices
• Power Calculator tool included with Lattice’s ispLEVER design tool, or as a standalone download from
www.latticesemi.com/software
4-80
LatticeECP/EC Family Data Sheet
Ordering Information
September 2012
Data Sheet
Part Number Description
LFXXX XX X – X XXXX X
Device Family
Grade
C = Commercial
I = Industrial
Lattice EC (FPGA)
Lattice ECP (EC FPGA + DSP Blocks)
Logic Capacity
1* = 1.5K LUTs
3* = 3K LUTs
6 = 6K LUTs
Package
T100 = 100-pin TQFP*
T144 = 144-pin TQFP
Q208 = 208-pin PQFP
F256 = 256-ball fpBGA
F484 = 484-ball fpBGA
F672 = 672-ball fpBGA
10 = 10K LUTs
15 = 15K LUTs
20 = 20K LUTs
33 = 33K LUTs
TN100 = 100-pin Lead-free TQFP*
TN144 = 144-pin Lead-free TQFP
QN208 = 208-pin Lead-free PQFP
FN256 = 256-ball Lead-free fpBGA
FN484 = 484-ball Lead-free fpBGA
FN672 = 672-ball Lead-free fpBGA
Supply Voltage
E = 1.2V
Speed
3 = Slowest
4
*Not available in the LatticeECP Family.
5 = Fastest
Ordering Information
Note:þLatticeECP/EC devices are dual marked. For example, the commercial speed grade LFEC20E-4F484C is
also marked with industrial grade -3I (LFEC20E-3F484I). The commercial grade is one speed grade faster than the
associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings.
The markings appear as follows:
EC
LFEC20E-
4F484C-3I
Datecode
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
5-1
Order Info_02.4
Ordering Information
LatticeECP/EC Family Data Sheet
Conventional Packaging
LatticeEC Commercial
Part Number
LFEC1E-3Q208C
LFEC1E-4Q208C
LFEC1E-5Q208C
LFEC1E-3T144C
LFEC1E-4T144C
LFEC1E-5T144C
LFEC1E-3T100C
LFEC1E-4T100C
LFEC1E-5T100C
I/Os
112
112
112
97
Grade
-3
Package
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
208
144
144
144
100
100
100
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
-4
-5
-3
97
-4
97
-5
67
-3
67
-4
67
-5
Part Number
LFEC3E-3F256C
LFEC3E-4F256C
LFEC3E-5F256C
LFEC3E-3Q208C
LFEC3E-4Q208C
LFEC3E-5Q208C
LFEC3E-3T144C
LFEC3E-4T144C
LFEC3E-5T144C
LFEC3E-3T100C
LFEC3E-4T100C
LFEC3E-5T100C
I/Os
160
160
160
145
145
145
97
Grade
-3
Package
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
Pins
256
256
256
208
208
208
144
144
144
100
100
100
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
-4
-5
-3
-4
-5
-3
97
-4
97
-5
67
-3
67
-4
67
-5
Part Number
LFEC6E-3F484C
LFEC6E-4F484C
LFEC6E-5F484C
LFEC6E-3F256C
LFEC6E-4F256C
LFEC6E-5F256C
LFEC6E-3Q208C
LFEC6E-4Q208C
LFEC6E-5Q208C
LFEC6E-3T144C
LFEC6E-4T144C
LFEC6E-5T144C
I/Os
224
224
224
195
195
195
147
147
147
97
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
Pins
484
484
484
256
256
256
208
208
208
144
144
144
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
-4
-5
-3
-4
-5
-3
-4
-5
-3
97
-4
97
-5
Part Number
LFEC10E-3F484C
LFEC10E-4F484C
LFEC10E-5F484C
LFEC10E-3F256C
I/Os
288
288
288
195
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
484
256
Temp.
COM
COM
COM
COM
LUTs
10.2K
10.2K
10.2K
10.2K
-4
-5
-3
5-2
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeEC Commercial (Continued)
Part Number
LFEC10E-4F256C
LFEC10E-5F256C
LFEC10E-3Q208C
LFEC10E-4Q208C
LFEC10E-5Q208C
I/Os
195
195
147
147
147
Grade
-4
Package
fpBGA
fpBGA
PQFP
Pins
256
256
208
208
208
Temp.
COM
COM
COM
COM
COM
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
-5
-3
-4
PQFP
-5
PQFP
Part Number
LFEC15E-3F484C
LFEC15E-4F484C
LFEC15E-5F484C
LFEC15E-3F256C
LFEC15E-4F256C
LFEC15E-5F256C
I/Os
352
352
352
195
195
195
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
484
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
LUTs
15.3K
15.3K
15.3K
15.3K
15.3K
15.3K
-4
-5
-3
-4
-5
Part Number
LFEC20E-3F672C
LFEC20E-4F672C
LFEC20E-5F672C
LFEC20E-3F484C
LFEC20E-4F484C
LFEC20E-5F484C
I/Os
400
400
400
360
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
672
484
484
484
Temp.
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
-4
-5
-3
-4
-5
Part Number
LFEC33E-3F672C
LFEC33E-4F672C
LFEC33E-5F672C
LFEC33E-3F484C
LFEC33E-4F484C
LFEC33E-5F484C
I/Os
496
496
496
360
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
672
484
484
484
Temp.
COM
COM
COM
COM
COM
COM
LUTs
32.8K
32.8K
32.8K
32.8K
32.8K
32.8K
-4
-5
-3
-4
-5
5-3
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeECP Commercial
Part Number
LFECP6E-3F484C
LFECP6E-4F484C
LFECP6E-5F484C
LFECP6E-3F256C
LFECP6E-4F256C
LFECP6E-5F256C
LFECP6E-3Q208C
LFECP6E-4Q208C
LFECP6E-5Q208C
LFECP6E-3T144C
LFECP6E-4T144C
LFECP6E-5T144C
I/Os
224
224
224
195
195
195
147
147
147
97
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
Pins
484
484
484
256
256
256
208
208
208
144
144
144
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
-4
-5
-3
-4
-5
-3
-4
-5
-3
97
-4
97
-5
Part Number
LFECP10E-3F484C
LFECP10E-4F484C
LFECP10E-5F484C
LFECP10E-3F256C
LFECP10E-4F256C
LFECP10E-5F256C
LFECP10E-3Q208C
LFECP10E-4Q208C
LFECP10E-5Q208C
I/Os
288
288
288
195
195
195
147
147
147
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
Pins
484
484
484
256
256
256
208
208
208
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFECP15E-3F484C
LFECP15E-4F484C
LFECP15E-5F484C
LFECP15E-3F256C
LFECP15E-4F256C
LFECP15E-5F256C
I/Os
352
352
352
195
195
195
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
484
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
LUTs
15.3K
15.3K
15.3K
15.3K
15.3K
15.3K
-4
-5
-3
-4
-5
Part Number
LFECP20E-3F672C
LFECP20E-4F672C
LFECP20E-5F672C
LFECP20E-3F484C
LFECP20E-4F484C
LFECP20E-5F484C
I/Os
400
400
400
360
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
672
484
484
484
Temp.
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
-4
-5
-3
-4
-5
Part Number
LFECP33E-3F672C
LFECP33E-4F672C
LFECP33E-5F672C
I/Os
496
496
496
Grade
-3
Package
fpBGA
fpBGA
fpBGA
Pins
672
672
672
Temp.
COM
COM
COM
LUTs
32.8K
32.8K
32.8K
-4
-5
5-4
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeECP Commercial (Continued)
Part Number
LFECP33E-3F484C
LFECP33E-4F484C
LFECP33E-5F484C
I/Os
360
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
Pins
484
484
484
Temp.
COM
COM
COM
LUTs
32.8K
32.8K
32.8K
-4
-5
LatticeEC Industrial
Part Number
LFEC1E-3Q208I
LFEC1E-4Q208I
LFEC1E-3T144I
LFEC1E-4T144I
LFEC1E-3T100I
LFEC1E-4T100I
I/Os
112
112
97
Grade
-3
Package
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
144
144
100
100
Temp.
IND
IND
IND
IND
IND
IND
LUTs
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
-4
-3
97
-4
67
-3
67
-4
Part Number
LFEC3E-3F256I
LFEC3E-4F256I
LFEC3E-3Q208I
LFEC3E-4Q208I
LFEC3E-3T144I
LFEC3E-4T144I
LFEC3E-3T100I
LFEC3E-4T100I
I/Os
160
160
145
145
97
Grade
-3
Package
fpBGA
fpBGA
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
Pins
256
256
208
208
144
144
100
100
Temp.
IND
IND
IND
IND
IND
IND
IND
IND
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
-4
-3
-4
-3
97
-4
67
-3
67
-4
Part Number
LFEC6E-3F484I
LFEC6E-4F484I
LFEC6E-3F256I
LFEC6E-4F256I
LFEC6E-3Q208I
LFEC6E-4Q208I
LFEC6E-3T144I
LFEC6E-4T144I
I/Os
224
224
195
195
147
147
97
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
TQFP
Pins
484
484
256
256
208
208
144
144
Temp.
IND
IND
IND
IND
IND
IND
IND
IND
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
-4
-3
-4
-3
-4
-3
97
-4
TQFP
Part Number
LFEC10E-3F484I
LFEC10E-4F484I
LFEC10E-3F256I
LFEC10E-4F256I
LFEC10E-3 P208I
LFEC10E-4 P208I
I/Os
288
288
195
195
147
147
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
Pins
484
484
256
256
208
208
Temp.
IND
IND
IND
IND
IND
IND
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
-4
-3
-4
-3
-4
PQFP
5-5
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeEC Industrial (Continued)
Part Number
LFEC15E-3F484I
LFEC15E-4F484I
LFEC15E-3F256I
LFEC15E-4F256I
I/Os
352
352
195
195
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
256
256
Temp.
IND
LUTs
15.3K
15.3K
15.3K
15.3K
-4
IND
-3
IND
-4
IND
Part Number
LFEC20E-3F672I
LFEC20E-4F672I
LFEC20E-3F484I
LFEC20E-4F484I
I/Os
400
400
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
484
484
Temp.
IND
LUTs
19.7K
19.7K
19.7K
19.7K
-4
IND
-3
IND
-4
IND
Part Number
LFEC33E-3F672I
LFEC33E-4F672I
LFEC33E-3F484I
LFEC33E-4F484I
I/Os
496
496
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
484
484
Temp.
IND
LUTs
32.8
32.8
32.8
32.8
-4
IND
-3
IND
-4
IND
LatticeECP Industrial
Part Number
LFECP6E-3F484I
LFECP6E-4F484I
LFECP6E-3F256I
LFECP6E-4F256I
LFECP6E-3Q208I
LFECP6E-4Q208I
LFECP6E-3T144I
LFECP6E-4T144I
I/Os
224
224
195
195
147
147
97
Grade
Package
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
TQFP
Pins
Temp.
IND
IND
IND
IND
IND
IND
IND
IND
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
-3
-4
-3
-4
-3
-4
-3
-4
484
484
256
256
208
208
144
144
97
TQFP
Part Number
LFECP10E-3F484I
LFECP10E-4F484I
LFECP10E-3F256I
LFECP10E-4F256I
LFECP10E-3Q208I
LFECP10E-4Q208I
I/Os
288
288
195
195
147
147
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
Pins
484
484
256
256
208
208
Temp.
IND
IND
IND
IND
IND
IND
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
-4
-3
-4
-3
-4
PQFP
Part Number
LFECP15E-3F484I
LFECP15E-4F484I
LFECP15E-3F256I
LFECP15E-4F256I
I/Os
352
352
195
195
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
256
256
Temp.
IND
LUTs
15.3K
15.3K
15.3K
15.3K
-4
IND
-3
IND
-4
IND
5-6
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeECP Industrial (Continued)
Part Number
LFECP20E-3F672I
LFECP20E-4F672I
LFECP20E-3F484I
LFECP20E-4F484I
I/Os
400
400
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
484
484
Temp.
IND
LUTs
19.7K
19.7K
19.7K
19.7K
-4
IND
-3
IND
-4
IND
Part Number
LFECP33E-3F672I
LFECP33E-4F672I
LFECP33E-3F484I
LFECP33E-4F484I
I/Os
496
496
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
484
484
Temp.
IND
LUTs
32.8K
32.8K
32.8K
32.8K
-4
IND
-3
IND
-4
IND
5-7
Ordering Information
LatticeECP/EC Family Data Sheet
Lead-Free Packaging
LatticeEC Commercial
Part Number
LFEC1E-3QN208C
LFEC1E-4QN208C
LFEC1E-5QN208C
LFEC1E-3TN144C
LFEC1E-4TN144C
LFEC1E-5TN144C
LFEC1E-3TN100C
LFEC1E-4TN100C
LFEC1E-5TN100C
I/Os
Grade
Package
Pins/Balls
208
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
112
112
112
97
-3
-4
-5
-3
-4
-5
-3
-4
-5
Lead-Free PQFP
Lead-Free PQFP
Lead-Free PQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
208
208
144
97
144
97
144
67
100
67
100
67
100
Part Number
LFEC3E-3FN256C
LFEC3E-4FN256C
LFEC3E-5FN256C
LFEC3E-3QN208C
LFEC3E-4QN208C
LFEC3E-5QN208C
LFEC3E-3TN144C
LFEC3E-4TN144C
LFEC3E-5TN144C
LFEC3E-3TN100C
LFEC3E-4TN100C
LFEC3E-5TN100C
I/Os
160
160
160
145
145
145
97
Grade
-3
Package
Pins/Balls
256
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
Lead-Free PQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
-4
256
-5
256
-3
208
-4
208
-5
208
-3
144
97
-4
144
97
-5
144
67
-3
100
67
-4
100
67
-5
100
Part Number
LFEC6E-3FN484C
LFEC6E-4FN484C
LFEC6E-5FN484C
LFEC6E-3FN256C
LFEC6E-4FN256C
LFEC6E-5FN256C
LFEC6E-3QN208C
LFEC6E-4QN208C
LFEC6E-5QN208C
LFEC6E-3TN144C
LFEC6E-4TN144C
LFEC6E-5TN144C
I/Os
224
224
224
195
195
195
147
147
147
97
Grade
-3
Package
Pins/Balls
484
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
Lead-Free PQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
-4
484
-5
484
-3
256
-4
256
-5
256
-3
208
-4
208
-5
208
-3
144
97
-4
144
97
-5
144
Part Number
I/Os
288
288
288
195
Grade
-3
Package
Pins/Balls
484
Temp.
COM
COM
COM
COM
LUTs
10.2K
10.2K
10.2K
10.2K
LFEC10E-3FN484C
LFEC10E-4FN484C
LFEC10E-5FN484C
LFEC10E-3FN256C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
484
-5
484
-3
256
5-8
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeEC Commercial (Continued)
Part Number
I/Os
195
195
147
147
147
Grade
-4
Package
Pins/Balls
256
Temp.
COM
COM
COM
COM
COM
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
LFEC10E-4FN256C
LFEC10E-5FN256C
LFEC10E-3QN208C
LFEC10E-4QN208C
LFEC10E-5QN208C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
Lead-Free PQFP
-5
256
-3
208
-4
208
-5
208
Part Number
I/Os
352
352
352
195
195
195
Grade
-3
Package
Pins/Balls
484
Temp.
COM
COM
COM
COM
COM
COM
LUTs
15.3K
15.3K
15.3K
15.3K
15.3K
15.3K
LFEC15E-3FN484C
LFEC15E-4FN484C
LFEC15E-5FN484C
LFEC15E-3FN256C
LFEC15E-4FN256C
LFEC15E-5FN256C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
484
-5
484
-3
256
-4
256
-5
256
Part Number
I/Os
400
400
400
360
360
360
Grade
-3
Package
Pins/Balls
672
Temp.
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
LFEC20E-3FN672C
LFEC20E-4FN672C
LFEC20E-5FN672C
LFEC20E-3FN484C
LFEC20E-4FN484C
LFEC20E-5FN484C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
672
-5
672
-3
484
-4
484
-5
484
Part Number
I/Os
496
496
496
360
360
360
Grade
-3
Package
Pins/Balls
672
Temp.
COM
COM
COM
COM
COM
COM
LUTs
32.8K
32.8K
32.8K
32.8K
32.8K
32.8K
LFEC33E-3FN672C
LFEC33E-4FN672C
LFEC33E-5FN672C
LFEC33E-3FN484C
LFEC33E-4FN484C
LFEC33E-5FN484C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
672
-5
672
-3
484
-4
484
-5
484
5-9
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeECP Commercial
Part Number
I/Os
224
224
224
195
195
195
147
147
147
97
Grade
Package
Pins/Balls
484
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
LFECP6E-3FN484C
LFECP6E-4FN484C
LFECP6E-5FN484C
LFECP6E-3FN256C
LFECP6E-4FN256C
LFECP6E-5FN256C
LFECP6E-3QN208C
LFECP6E-4QN208C
LFECP6E-5QN208C
LFECP6E-3TN144C
LFECP6E-4TN144C
LFECP6E-5TN144C
-3
-4
-5
-3
-4
-5
-3
-4
-5
-3
-4
-5
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
Lead-Free PQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
484
484
256
256
256
208
208
208
144
97
144
97
144
Part Number
I/Os
288
288
288
195
195
195
147
147
147
Grade
-3
Package
Pins/Balls
484
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
LFECP10E-3FN484C
LFECP10E-4FN484C
LFECP10E-5FN484C
LFECP10E-3FN256C
LFECP10E-4FN256C
LFECP10E-5FN256C
LFECP10E-3QN208C
LFECP10E-4QN208C
LFECP10E-5QN208C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
Lead-Free PQFP
-4
484
-5
484
-3
256
-4
256
-5
256
-3
208
-4
208
-5
208
Part Number
I/Os
352
352
352
195
195
195
Grade
-3
Package
Pins/Balls
484
Temp.
COM
COM
COM
COM
COM
COM
LUTs
15.3K
15.3K
15.3K
15.3K
15.3K
15.3K
LFECP15E-3FN484C
LFECP15E-4FN484C
LFECP15E-5FN484C
LFECP15E-3FN256C
LFECP15E-4FN256C
LFECP15E-5FN256C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
484
-5
484
-3
256
-4
256
-5
256
Part Number
I/Os
400
400
400
400
400
400
Grade
-3
Package
Pins/Balls
672
Temp.
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
LFECP20E-3FN672C
LFECP20E-4FN672C
LFECP20E-5FN672C
LFECP20E-3FN484C
LFECP20E-4FN484C
LFECP20E-5FN484C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
672
-5
672
-3
484
-4
484
-5
484
Part Number
I/Os
496
496
496
Grade
-3
Package
Pins/Balls
672
Temp.
COM
COM
COM
LUTs
32.8K
32.8K
32.8K
LFECP33E-3FN672C
LFECP33E-4FN672C
LFECP33E-5FN672C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
672
-5
672
5-10
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeECP Commercial (Continued)
Part Number
I/Os
360
360
360
Grade
-3
Package
Pins/Balls
484
Temp.
COM
COM
COM
LUTs
32.8K
32.8K
32.8K
LFECP33E-3FN484C
LFECP33E-4FN484C
LFECP33E-5FN484C
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
484
-5
484
LatticeEC Industrial
Part Number
LFEC1E-3QN208I
LFEC1E-4QN208I
LFEC1E-3TN144I
LFEC1E-4TN144I
LFEC1E-3TN100I
LFEC1E-4TN100I
I/Os
112
112
97
Grade
-3
Package
Pins/Balls
208
Temp.
IND
IND
IND
IND
IND
IND
LUTs
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
Lead-Free PQFP
Lead-Free PQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
-4
208
-3
144
97
-4
144
67
-3
100
67
-4
100
Part Number
LFEC3E-3FN256I
LFEC3E-4FN256I
LFEC3E-3QN208I
LFEC3E-4QN208I
LFEC3E-3TN144I
LFEC3E-4TN144I
LFEC3E-3TN100I
LFEC3E-4TN100I
I/Os
160
160
145
145
97
Grade
-3
Package
Pins/Balls
256
Temp.
IND
IND
IND
IND
IND
IND
IND
IND
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
Lead-Free TQFP
-4
256
-3
208
-4
208
-3
144
97
-4
144
67
-3
100
67
-4
100
Part Number
LFEC6E-3FN484I
LFEC6E-4FN484I
LFEC6E-3FN256I
LFEC6E-4FN256I
LFEC6E-3QN208I
LFEC6E-4QN208I
LFEC6E-3TN144I
LFEC6E-4TN144I
I/Os
224
224
195
195
147
147
97
Grade
-3
Package
Pins/Balls
484
Temp.
IND
IND
IND
IND
IND
IND
IND
IND
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
Lead-Free TQFP
Lead-Free TQFP
-4
484
-3
256
-4
256
-3
208
-4
208
-3
144
97
-4
144
Part Number
LFEC10E-3FN484I
LFEC10E-4FN484I
LFEC10E-3FN256I
LFEC10E-4FN256I
LFEC10E-3QN208I
LFEC10E-4QN208I
I/Os
288
288
195
195
147
147
Grade
-3
Package
Pins/Balls
484
Temp.
IND
IND
IND
IND
IND
IND
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
-4
484
-3
256
-4
256
-3
208
-4
208
5-11
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeEC Industrial (Continued)
Part Number
LFEC15E-3FN484I
LFEC15E-4FN484I
LFEC15E-3FN256I
LFEC15E-4FN256I
I/Os
352
352
195
195
Grade
-3
Package
Pins/Balls
484
Temp.
IND
LUTs
15.3K
15.3K
15.3K
15.3K
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
484
IND
-3
256
IND
-4
256
IND
Part Number
LFEC20E-3FN672I
LFEC20E-4FN672I
LFEC20E-3FN484I
LFEC20E-4FN484I
I/Os
400
400
400
400
Grade
-3
Package
Pins/Balls
672
Temp.
IND
LUTs
19.7K
19.7K
19.7K
19.7K
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
672
IND
-3
484
IND
-4
484
IND
Part Number
LFEC33E-3FN672I
LFEC33E-4FN672I
LFEC33E-3FN484I
LFEC33E-4FN484I
I/Os
496
496
360
360
Grade
-3
Package
Pins/Balls
672
Temp.
IND
LUTs
32.8K
32.8K
32.8K
32.8K
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
672
IND
-3
484
IND
-4
484
IND
LatticeECP Industrial
Part Number
LFECP6E-3FN484I
LFECP6E-4FN484I
LFECP6E-3FN256I
LFECP6E-4FN256I
LFECP6E-3QN208I
LFECP6E-4QN208I
LFECP6E-3TN144I
LFECP6E-4TN144I
I/Os
224
224
195
195
147
147
97
Grade
Package
Pins/Balls
484
Temp.
IND
IND
IND
IND
IND
IND
IND
IND
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
-3
-4
-3
-4
-3
-4
-3
-4
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
Lead-Free TQFP
Lead-Free TQFP
484
256
256
208
208
144
97
144
Part Number
I/Os
288
288
195
195
147
147
Grade
-3
Package
Pins/Balls
484
Temp.
IND
IND
IND
IND
IND
IND
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
LFECP10E-3FN484I
LFECP10E-4FN484I
LFECP10E-3FN256I
LFECP10E-4FN256I
LFECP10E-3QN208I
LFECP10E-4QN208I
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free PQFP
Lead-Free PQFP
-4
484
-3
256
-4
256
-3
208
-4
208
Part Number
I/Os
352
352
195
195
Grade
-3
Package
Pins/Balls
484
Temp.
IND
LUTs
15.3K
15.3K
15.3K
15.3K
LFECP15E-3FN484I
LFECP15E-4FN484I
LFECP15E-3FN256I
LFECP15E-4FN256I
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
484
IND
-3
256
IND
-4
256
IND
5-12
Ordering Information
LatticeECP/EC Family Data Sheet
LatticeECP Industrial (Continued)
Part Number
I/Os
400
400
400
400
Grade
-3
Package
Pins/Balls
672
Temp.
IND
LUTs
19.7K
19.7K
19.7K
19.7K
LFECP20E-3FN672I
LFECP20E-4FN672I
LFECP20E-3FN484I
LFECP20E-4FN484I
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
672
IND
-3
484
IND
-4
484
IND
Part Number
I/Os
496
496
360
360
Grade
-3
Package
Pins/Balls
672
Temp.
IND
LUTs
32.8K
32.8K
32.8K
32.8K
LFECP33E-3FN672I
LFECP33E-4FN672I
LFECP33E-3FN484I
LFECP33E-4FN484I
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
-4
672
IND
-3
484
IND
-4
484
IND
5-13
LatticeECP/EC Family Data Sheet
Supplemental Information
Data Sheet
September 2012
For Further Information
A variety of technical notes for the LatticeECP/EC family are available on the Lattice web site at www.latticesemi.com.
• LatticeECP/EC sysIO Usage Guide (TN1056)
• LatticeECP/EC sysCLOCK PLL Design and Usage Guide (TN1049)
• Memory Usage Guide for LatticeECP/EC Devices (TN1051)
• LatticeECP/EC DDR Usage Guide (TN1050)
• Power Estimation and Management for LatticeECP/EC and LatticeXP Devices (TN1052)
• LatticeECP-DSP sysDSP Usage Guide (TN1057)
• LatticeECP/EC sysCONFIG Usage Guide (TN1053)
• IEEE 1149.1 Boundary Scan Testability in Lattice Devices
For further information about interface standards refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• PCI: ww.pcisig.com
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
6-1
Further Info_01.4
LatticeECP/EC Family Data Sheet
Revision History
September 2012
Data Sheet DS1000
Revision History
Date
Version
01.0
Section
Change Summary
June 2004
August 2004
—
Initial release.
01.1
Introduction
Architecture
Added new device LFECP/LFEC33 in Table 1-1.
Added New device LFECP/LFEC33 in Tables 2-9, 2-10 and 2-11.
Added New device LFECP/LFEC33 on Supply current (Standby) tables.
DC & Switching
Characteristics
Added New device LFECP/LFEC33 on Initialization Supply current
tables.
Ordering Information Added 33K Logic Capacity Device in Part Number Description section.
Added EC33, ECP33 device: Industrial and Commercial to Part Number
table.
Corrected I/O counts in the part number tables for 100/144 TQFP and
208 PQFP packages to match Table 1-1 on page 1.
November 2004
01.3
Introduction
Architecture
Changed DDR333 (166MHz) to DDR400 (200MHz)
Added “RSDS” offering to the Features list: Flexible I/O Buffer
Added information about Secondary Clock Sources
Added information about DCS
Added a section on “Recommended Power-up Sequence”
Updated Figure 2-24 “DQS Routing”
Added DSP Block performance numbers to Table 2-11
Added another row for RSDS in Table 2-13 and Table 2-14
Updated new timing numbers
DC & Switching
Characteristics
Added numbers to derating table
Added DC conditions to RSDS table
Changed LVDS Max. VCCIO to 2.625
Added a row for RSDS in “Operating Condition” table
Updated standby and initialization current table
Added figure 3-12: sysConfig SPI port sequence
Added DDR Timing Table and DDR Timings Figure 3-6
Added LFECP/EC6 to Pin Information
Pinout Information
Added LFECP/EC6 to Power Supply and NC Connections
Added LFECP/EC6 144 TQFP Logic Signal Connections
Added LFECP/EC6 208 PQFP Logic Signal Connections
Added LFECP/EC6 256 fpBGA Logic Signal Connections
Added LFECP/EC6 484 fpBGA Logic Signal Connections
Ordering Information Added 33K Logic Capacity Device in Part Number Description section.
Added Part Number table for Commercial EC33.
Added Part Number table for Commercial ECP33.
Added Part Number table for Industrial EC33.
Added Part Number table for Industrial ECP33.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
7-1
Revision History
LatticeECP/EC Family Data Sheet
Date
Version
Section
Architecture
Change Summary
December 2004
01.4
Updated Hot Socketing Recommended Power Up Sequence section.
Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Pin Information
Pinout Information
Added LFEC1, LFEC3, LFECP/EC10, LFECP/EC15 to Power Supply
and NC Connections
Added LFEC1 and LFEC3 100 TQFP Pinout
Added LFEC1 and LFEC3 144 TQFP Pinout
Added LFEC1, LFEC3 and LFECP/EC10 208 PQFP Pinout
Added LFEC3, LFECP/EC10 and LFECP/EC15 256 fpBGA Pinout
Added LFECP/EC10 and LFECP/EC15 484 fpBGA Pinout
Ordering Information Added Lead-Free Package Designators
Added Lead-Free Ordering Part Numbers
Supplemental
Information
Updated list of technical notes.
April 2005
01.5
Architecture
EBR memory support section has been updated with clarification.
Updated sysIO buffer pair section.
DC & Switching
Characteristics
Hot Socketing Specification has been updated.
DC Electrical Characteristics table (IIL, IIH) has been updated.
Supply Current (Standby) table has been updated.
Initialization Supply Current table has been updated.
External Switching Characteristics section has been updated.
Removed tRSTW spec. from PLL Parameter table.
t
RST specifications have been updated.
sysCONFIG Port Timing Specifications (tBSCL, tIODISS, PRGMRJ) have
t
been updated.
Pinout Information
Added LFECP/EC33 Pinout Information
Pin Information Summary table has been updated.
Power Supply and NC Connection table has been updated.
484-fpBGA logic connection has been updated (Ball # J6, J17, P6 and
P17 for ECP/EC33 are now called VCCPLL).
672-fpBGA logic connection has been updated (Ball # K19, L8, U19, U8
for ECP/EC33 are now called VCCPLL).
May 2005
01.6
Introduction
Architecture
ECP/EC33 EBR SRAM Bits and Blocks have been updated to 498K and
54 respectively.
Table 2-10 has been updated (ECP/EC33 EBR SRAM Bits and Blocks
have been updated to 498K and 54 respectively.)
Recommended Power Up Sequence section has been removed.
Supply Current (Standby) table has been updated.
DC & Switching
Characteristics
Initialization Supply Current table has been updated.
Vos test condition has been updated to (VOP+VOM)/2.
Register-to-Register performance table has been updated (rev. G 0.27).
External switching characteristics have been updated (rev. G 0.27).
Internal timing parameters have been updated (rev. G 0.27).
Timing adders have been updated (rev. G 0.27).
sysCONFIG port timing specifications have been updated.
Pin Information Summary table has been updated.
Pinout Information
Power Supply and NC Connection table has been updated.
Ordering Information OPN list has been updated.
7-2
Revision History
LatticeECP/EC Family Data Sheet
Date
Version
Section
Change Summary
September 2005
02.0
Architecture
sysIO section has been updated.
Recommended Operating Conditions has been updated with VCCPLL
DC & Switching
Characteristics
.
DC Electrical Characteristics table has been updated
Removed 5V Tolerant Input Buffer section.
Register-to-Register performance table has been updated (rev. G 0.28).
LatticeECP/EC External Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Internal Switching Characteristics table has been
updated (rev. G 0.28).
LatticeECP/EC Family Timing Adders have been updated (rev. G 0.28).
sysCLOCK PLL timing table has been updated (rev. G 0.28)
LatticeECP/EC sysCONFIG Port Timing specification table has been
updated (rev. G 0.28).
Master Clock table has been updated (rev. G 0.28).
JTAG Port Timing specification table has been updated (rev. G 0.28).
Pinout Information
Signal Description table has been updated with VCCPLL.
November 2005
02.1
DC & Switching
Characteristics
Pin-to-Pin Performance table has been updated (G 0.30)
- 4:1MUX, 8:1MUX, 16:1MUX, 32:1MUX
Register-to-Register Performance (G 0.30) - No timing number
changes.
External Switching Characteristics (G 0.30) - No timing number
changes.
Internal Switching Characteristics (G 0.30)
-tSUP_DSP, tHP_DSP, tSUO_DSP, HO_DSP, COI_DSP
t
t
, tCOD_DSP numbers
have been updated.
Family Timing Adders (G 0.30) - No timing number changes.
sysCLOCK PLL Timing (G 0.30) - No timing number changes.
sysCONFIG Port Timing Specifications (G 0.30) - No timing number
changes.
Master Clock (G 0.30) - No timing number changes.
JTAG Port Timing Specification (G 0.30) - No timing number changes.
Ordering Information Added 208-PQFP lead-free part numbers.
March 2006
02.2
DC & Switching
Characteristics
Added footnote 3. to VCCAUX in the Recommended Operating Condi-
tions table.
January 2007
February 2007
02.3
02.4
Architecture
Architecture
EBR Asynchronous Reset section added.
Updated EBR Asynchronous Reset section.
Updated Maximum Number of Elements in a Block table - MAC value for
x9 changed to 2.
May 2007
02.5
02.6
Architecture
Updated text in Ripple Mode section.
Added JTAG Port Waveforms diagram.
November 2007
DC & Switching
Characteristics
Updated tRST timing information in the sysCLOCK PLL Timing table.
Added Thermal Management text section.
Updated title list.
Pinout Information
Supplemental
Information
February 2008
02.7
02.8
DC & Switching
Characteristics
Read/Write Mode (Normal) and Read/Write Mode with Input and Output
Registers waveforms in the EBR Memory Timing Diagrams section
have been updated.
September 2012
All
Updated document with new corporate logo.
7-3
相关型号:
©2020 ICPDF网 联系我们和版权申明