LFECP20E-5T100I [LATTICE]
LatticeECP/EC Family Data Sheet; 的LatticeECP / EC系列数据手册型号: | LFECP20E-5T100I |
厂家: | LATTICE SEMICONDUCTOR |
描述: | LatticeECP/EC Family Data Sheet |
文件: | 总117页 (文件大小:540K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LatticeECP/EC Family Data Sheet
Version 01.3
LatticeECP/EC Family Data Sheet
Introduction
November 2004
Preliminary Data Sheet
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− SSTL 3/2 Class I, II, SSTL18 Class I
− HSTL 18 Class I, II, III, HSTL15 Class I, III
− PCI
Features
■ Extensive Density and Package Options
• 1.5K to 41K LUT4s
• 65 to 576 I/Os
• Density migration supported
− LVDS, Bus-LVDS, LVPECL, RSDS
■ Dedicated DDR Memory Support
• Implements interface up to DDR400 (200MHz)
■ sysDSP™ Block (LatticeECP™ Versions)
• High performance multiply and accumulate
• 4 to 10 blocks
■ sysCLOCK™ PLLs
− 4 to 10 36x36 multipliers or
– 16 to 40 18x18 multipliers or
− 32 to 80 9x9 multipliers
• Up to 4 analog PLLs per device
• Clock multiply, divide and phase shifting
■ System Level Support
■ Embedded and Distributed Memory
• 18 Kbits to 645 Kbits sysMEM™ Embedded
Block RAM (EBR)
• IEEE Standard 1149.1 Boundary Scan, plus
ispTRACY™ internal logic analyzer capability
• SPI boot flash interface
• Up to 163 Kbits distributed RAM
• Flexible memory resources:
• 1.2V power supply
■ Low Cost FPGA
− Distributed and block memory
• Features optimized for mainstream applications
• Low cost TQFP and PQFP packaging
■ Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
Table 1-1. LatticeECP/EC Family Selection Guide
LFEC6/
LFEC10/ LFEC15/ LFEC20/ LFEC33/ LFEC40/
Device
PFU/PFF Rows
LFEC1
12
16
192
1.5
6
LFEC3
16
LFECP6 LFECP10 LFECP15 LFECP20 LFECP33 LFECP40
24
32
768
6.1
25
92
10
4
32
40
40
48
44
56
64
64
64
80
PFU/PFF Columns
PFUs/PFFs
24
384
3.1
12
1280
10.2
41
1920
15.4
61
2464
19.7
79
4096
32.8
131
535
58
5120
41.0
164
645
70
LUTs (K)
Distributed RAM (Kbits)
EBR SRAM (Kbits)
EBR SRAM Blocks
sysDSP Blocks1
18x18 Multipliers1
18
2
55
277
30
350
38
424
46
6
—
—
5
6
7
8
10
—
—
16
1.2
2
20
24
28
32
40
V
Voltage (V)
1.2
2
1.2
2
1.2
4
1.2
4
1.2
4
1.2
4
1.2
4
CC
Number of PLLs
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
144-pin TQFP (20 x 20 mm)
67
97
67
97
97
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
1. LatticeECP devices only.
112
145
160
147
195
224
147
195
288
195
352
360
400
360
496
496
576
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
Introduction_01.2
Introduction
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Introduction
The LatticeECP/EC family of FPGA devices has been optimized to deliver mainstream FPGA features at low cost.
For maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an efficient FPGA
fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-DSP
(EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™ (ECon-
omy) family supports all the general purpose features of LatticeECP devices without dedicated function blocks to
achieve lower cost solutions.
The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical
FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.
Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prev-
alent in cost-sensitive applications.
The ispLEVER® design tool from Lattice allows large complex designs to be efficiently implemented using the Latti-
ceECP/EC family of FPGA devices. Synthesis library support for LatticeECP/EC is available for popular logic syn-
thesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning
tools to place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the
routing and back-annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
1-2
LatticeECP/EC Family Data Sheet
Architecture
November 2004
Preliminary Data Sheet
Architecture Overview
The LatticeECP™-DSP and LatticeEC™ architectures contain an array of logic blocks surrounded by Programma-
ble I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM
(EBR) as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks as
shown in Figure 2-2.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks
are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic Blocks are
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the
clocks. The LatticeECP/EC architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™
port which allows for serial or parallel device configuration. The LatticeECP/EC devices use 1.2V as their core volt-
age.
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1
Architecture_01.3
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-1. Simplified Block Diagram, LatticeECP/EC Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (PFU without
RAM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
JTAG Port
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (Fast PFU
without RAM/ROM)
sysDSP Block
sysCLOCK PLL
Programmable
Functional Unit (PFU)
2-2
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
PFU and PFF Blocks
The core of the LatticeECP/EC devices consists of PFU and PFF blocks.The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-
tions to and from PFU blocks are from routing.There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-3. PFU Diagram
From
Routing
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
Slice 3
Slice 0
Slice 1
Slice 2
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
To
Routing
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice.
The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated
with each slice.
2-3
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-4. Slice Diagram
To / From
Different slice / PFU
Slice
OFX1
F1
A1
CO
F
B1
C1
D1
Q1
LUT4 &
D
SUM
FF/
Latch
CARRY
CI
To
Routing
From
Routing
M1
M0
OFX0
LUT
Expansion
Mux
CO
A0
B0
F0
C0
LUT4 &
CARRY
F
D0
OFX0
Q0
SUM
D
FF/
Latch
CI
Control Signals
selected and
inverted per
CE
CLK
LSR
slice in routing
Interslice signals
are not shown
To / From
Different slice / PFU
Table 2-1. Slice Signal Descriptions
Function
Input
Type
Signal Names
Description
Data signal
A0, B0, C0, D0 Inputs to LUT4
A1, B1, C1, D1 Inputs to LUT4
Input
Data signal
Input
Multi-purpose
Multi-purpose
Control signal
Control signal
Control signal
Inter-PFU signal
Data signals
Data signals
Data signals
Data signals
Inter-PFU signal
M0
M1
Multipurpose Input
Input
Multipurpose Input
Clock Enable
Input
CE
Input
LSR
Local Set/Reset
System Clock
Fast Carry In1
Input
CLK
Input
FCIN
F0, F1
Q0, Q1
OFX0
OFX1
FCO
Output
Output
Output
Output
Output
LUT4 output register bypass signals
Register Outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
For the right most PFU the fast carry chain output1
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
2-4
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
Table 2-2. Slice Modes
Logic
Ripple
RAM
SPR16x2
N/A
ROM
PFU Slice
PFF Slice
LUT 4x2 or LUT 5x1
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
2-bit Arithmetic Unit
ROM16x1 x 2
ROM16x1 x 2
Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables. A LUT4
can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this
lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup
tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices.
Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the fol-
lowing functions can be implemented by each Slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/Subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Ripple mode multiplier building block
• Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating Slices.
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory.
Through the combination of LUTs and Slices, a variety of different memories can be constructed.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of Slices required to implement different distributed RAM primitives. Figure 2-5 shows the dis-
tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions
as the read-write port. The other companion Slice supports the read-only port. For more information on using RAM
in LatticeECP/EC devices, please see details of additional technical documentation at the end of this data sheet.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
SPR16x2
DPR16x2
Number of slices
1
2
Note: SPR = Single Port RAM, DPR = Dual Port RAM
2-5
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-5. Distributed Memory Primitives
SPR16x2
DPR16x2
RAD0
RAD1
RAD2
RAD3
AD0
AD1
AD2
AD3
WAD0
WAD1
WAD2
WAD3
DO0
DO1
DI0
DI1
WRE
RDO0
RDO1
WDO0
WDO1
DI0
DI1
WCK
WRE
CK
ROM16x1
AD0
AD1
AD2
AD3
DO0
ROM Mode:The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Logic
Ripple
RAM1
ROM
LUT 4x8 or
MUX 2x1 x 8
2-bit Add x 4
SPR16x2 x 4
DPR16x2 x 2
ROM16x1 x 8
LUT 5x4 or
MUX 4x1 x 4
2-bit Sub x 4
2-bit Counter x 4
2-bit Comp x 4
SPR16x4 x 2
DPR16x4 x 1
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1
LUT 6x 2 or
MUX 8x1 x 2
SPR16x8 x 1
LUT 7x1 or
MUX 16x1 x 1
1. These modes are not available in PFF blocks
2-6
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Routing
There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and
x6 resources are buffered allowing both short and long connections routing between PFUs.
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.
LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There
are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.
Figure 2-6. Primary Clock Sources
From Routing
Clock Input
From Routing
PLL Input
PLL Input
PLL
PLL
20 Primary Clock Sources
To Quadrant Clock Selection
Clock Input
Clock Input
PLL
PLL
PLL Input
PLL Input
From Routing
Clock Input
From Routing
Note: Smaller devices have two PLLs.
2-7
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Secondary Clock Sources
LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are
tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These
secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7.
Figure 2-7. Secondary Clock Sources
From
From
From
From
Routing
Routing
Routing
Routing
From Routing
From Routing
From Routing
From Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From Routing
From Routing
From Routing
From Routing
From
From
From
From
Routing
Routing
Routing
Routing
Clock Routing
The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock
network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows
this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in
Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in
Figure 2-10.
2-8
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-8. Per Quadrant Primary Clock Selection
1
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing
DCS
DCS
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
1. Smaller devices have fewer PLL related lines.
Figure 2-9. Per Quadrant Secondary Clock Selection
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
4 Secondary Clocks per Quadrant
Figure 2-10. Slice Clock Selection
Primary Clock
4
3
Secondary Clock
Routing
Clock to Slice
GND
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nal to the feedback divider: from the CLKOP, from the clock net, or from an external pin. There is a PLL_LOCK sig-
nal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
2-9
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
adjustment and not relock until the t
parameter has been satisfied. Additionally, the phase and duty cycle block
LOCK
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal.The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
quency range. The secondary divider is used to derive lower frequency outputs.
Figure 2-11. PLL Diagram
Dynamic Delay Adjustment
LOCK
Input Clock
Divider
(CLKI)
Post Scalar
Divider
(CLKOP)
Phase/Duty
Select
CLKI
(from routing or
external pin)
Voltage
Controlled
Oscillator
CLKOS
Delay
Adjust
CLKOP
CLKOK
RST
Secondary
Clock
Divider
Feedback
Divider
(CLKFB)
CLKFB
(from CLKOP,
clock net or
external pin)
(CLKOK)
Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.
Figure 2-12. PLL Primitive
CLKOP
RST
CLKI
CLKI
CLKOP
LOCK
CLKOS
CLKOK
LOCK
EPLLB
CLKFB
CLKFB
DDA MODE
DDAIZR
EHXPLLB
DDAOZR
DDAILAG
DDAOLAG
DDAODEL[2:0]
DDAIDEL[2:0]
2-10
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Table 2-5. PLL Signal Descriptions
Signal
I/O
I
Description
CLKI
Clock input from external pin or routing
CLKFB
I
PLL feedback input from CLKOP, clocknet, or external pin
“1” to reset PLL
RST
I
CLKOS
O
O
O
O
I
PLL output clock to clock tree (phase shifted/duty cycle changed)
PLL output clock to clock tree (No phase shift)
PLL output to clock tree through secondary clock divider
“1” indicates PLL LOCK to CLKI
CLKOP
CLKOK
LOCK
DDAMODE
DDAIZR
Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag
Dynamic Delay Input
I
DDAILAG
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
I
I
O
O
O
Dynamic Delay Zero Output
Dynamic Delay Lag/Lead Output
Dynamic Delay Output
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-13 illustrates
the DCS Block Macro.
Figure 2-13. DCS Block Primitive
CLK0
DCS
CLK1
SEL
DCSOUT
Figure 2-14 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
2-11
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-14. DCS Waveforms
CLK0
CLK1
SEL
DCSOUT
sysMEM Memory
The LatticeECP/EC family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR con-
sists of a 9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6.
Table 2-6. sysMEM Block Configurations
Memory Mode
Configurations
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
Single Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
True Dual Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
Pseudo Dual Port
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
2-12
Architecture
Lattice Semiconductor
Memory Cascading
LatticeECP/EC Family Data Sheet
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual and Pseudo-Dual Port Modes
Figure 2-15 shows the four basic memory configurations and their input/output names. In all the sysMEM RAM
modes the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the output.
Figure 2-15. sysMEM EBR Primitives
ADA[12:0]
DIA[17:0]
CLKA
CEA
RSTA
WEA
CSA[2:0]
DOA[17:0]
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
AD[12:0]
DI[35:0]
CLK
DO[35:0]
CE
EBR
EBR
RST
WE
CS[2:0]
True Dual Port RAM
Single Port RAM
ADW[12:0]
DI[35:0]
CLKW
CEW
ADR[12:0]
DO[35:0]
AD[12:0]
CLK
DO[35:0]
CE
EBR
ROM
EBR
WE
RST
CS[2:0]
CER
RST
CS[2:0]
CLKR
Pseudo-Dual Port RAM
The EBR memory supports three forms of write behavior for single port or dual port operation:
1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current
address) does not appear on the output.
2. Write Through – a copy of the input data appears at the output of the same port, during a write cycle.
3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B respectively.The Global Reset (GSRN) signal resets both ports.The output data latches and associated
resets for both ports are as shown in Figure 2-16.
2-13
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-16. Memory Core Reset
Q
Memory Core
Port A[17:0]
LCLR
Output Data
Latches
D
Q
Port B[17:0]
LCLR
RSTA
RSTB
GSRN
Programmable Disable
For further information on sysMEM EBR block, please see the details of additional technical documentation at the
end of this data sheet.
sysDSP Block
The LatticeECP-DSP family provides a sysDSP block making it ideally suited for low cost, high performance Digital
Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response
(FIR) filters; Fast Fourier Transforms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and
decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-
tiply-accumulators.
sysDSP Block Approach Compare to General DSP
Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with
fixed data-width multipliers; this leads to limited parallelism and limited throughput.Their throughput is increased by
higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.
This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the
DSP performance vs. area by choosing appropriate level of parallelism. Figure 2-17 compares the serial and the
parallel implementations.
2-14
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-17. Comparison of General DSP and LatticeECP-DSP Approaches
Operand
A
Operand
A
Operand
A
Operand
B
Operand
B
Operand
B
Operand
A
Operand
B
Multiplier 0
x
x
x
m/k
loops
Multiplier 1
Multiplier
(k-1)
M loops
Single
Multiplier
x
Accumulator
Σ
Accumulator
Σ
Function implemented in
General purpose DSP
Output
Function implemented
in LatticeECP
sysDSP Block Capabilities
The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but
not mixed within a function element. Similarly, the operand widths cannot be mixed within a block.
The resources in each sysDSP block can be configured to support the following four elements:
• MULT
(Multiply)
• MAC
• MULTADD
(Multiply, Accumulate)
(Multiply, Addition/Subtraction)
• MULTADDSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available in each block depends in the width selected from the three available options x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-1 shows the capabilities of the block.
Table 2-7. Maximum Number of Elements in a Block
Width of Multiply
MULT
x9
8
x18
4
x36
1
MAC
4
2
—
—
—
MULTADD
MULTADDSUM
4
2
2
1
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift register from previous operand registers. In addition by selecting ‘dynamic operation’ in the ‘Signed/
Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly by select-
ing ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction
on every cycle.
2-15
Architecture
Lattice Semiconductor
MULT sysDSP Element
LatticeECP/EC Family Data Sheet
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-18 shows the MULT sysDSP element.
Figure 2-18. MULT sysDSP Element
Shift Register B In
Multiplicand
Shift Register A In
m
m
m
Multiplier
n
n
Multiplier
Input Data
Register A
m
n
m+n
(default)
m+n
n
x
Output
Input Data
Register B
Pipeline
Register
m
n
Signed
Input
Register
To
Multiplier
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
MAC sysDSP Element
In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. A registered overflow
signal is also available. The overflow conditions are provided later in this document. Figure 2-19 shows the MAC
sysDSP element.
Figure 2-19. MAC sysDSP Element
Shift Register B In
Shift Register A In
m
Multiplicand
m
Accumulator
m
n
m+n+16 bits
(default)
Multiplier
n
Multiplier
m
n
Input Data
Register A
n
Output
m+n+16 bits
(default)
x
m+n
(default)
Input Data
Register B
Pipeline
Register
n
n
SignedAB
Addn
Input
Register
Pipeline
Register
Overflow
signal
To
Accumulator
Input
Register
Pipeline
Register
To
Accumulator
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
Accumsload
Input
Register
Pipeline
Register
To
Accumulator
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
2-16
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
MULTADD sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-20
shows the MULTADD sysDSP element.
Figure 2-20. MULTADD
Shift Register B In
Shift Register A In
m
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
Multiplicand A0
m
RST(RST0,RST1,RST2,RST3)
m
n
Multiplier B0
n
Multiplier
Input Data
Register A
m
n
n
x
m+n
(default)
Input Data
Register B
Pipeline
Register
m
Add/Sub
n
Multiplicand A1
Multiplier B1
m
Output
m+n+1
(default)
m+n+1
(default)
m
n
Multiplier
m+n
(default)
Input Data
Register A
m
n
n
x
Input Data
Register B
Pipeline
Register
m
n
Signed
Addn
Input
Register
Pipeline
Register
To Add/Sub
To Add/Sub
Input
Pipeline
Register
Register
Shift Register B Out
Shift Register A Out
MULTADDSUM sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/
subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction
are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-21 shows
the MULTADDSUM sysDSP element.
2-17
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-21. MULTADDSUM
Shift Register B In
Shift Register A In
m
Multiplicand A0
m
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
m
n
Multiplier B0
n
Multiplier
Input Data
Register A
m
n
RST(RST0,RST1,RST2,RST3)
m+n
(default)
n
x
Input Data
Register B
Pipeline
Register
m
Add/Sub0
n
Multiplicand A1
Multiplier B1
m
m+n
(default)
m
n
Multiplier
Input Data
Register A
n
n
m+n+1
n
x
Input Data
Register B
SUM
Pipeline
Register
Output
Multiplicand A2
Multiplier B2
m
m
m
m+n+2
m+n+2
n
n
Multiplier
m
n
Input Data
Register A
m+n
(default)
n
x
m+n+1
Input Data
Register B
Pipeline
Register
m
Add/Sub1
n
Multiplicand A3
Multiplier B3
m
m+n
(default)
m
n
Multiplier
Input Data
Register A
m
n
n
x
Input Data
Register B
Pipeline
Register
m
n
Signed
Addn0
Addn1
Input
Register
Pipeline
Register
To Add/Sub0, Add/Sub1
To Add/Sub0
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
To Add/Sub1
Shift Register B Out
Shift Register A Out
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset
and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)
one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and
Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)
at each input register, pipeline register and output register.
Signed and Unsigned with Different Widths
The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-8 provides an example of this.
2-18
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Table 2-8. An Example of Sign Extension
Unsigned
9-bit
Unsigned
18-bit
Two’s Complement
Signed 9-Bits
Two’s Complement
Signed 18-bits
Number Unsigned
Signed
0101
+5
-6
0101
0110
000000101 000000000000000101
000000110 000000000000000110
000000101
111111010
000000000000000101
111111111111111010
1010
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two
unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and
overflow signal is indicated. When two positive numbers are added with a negative sum and when two negative
numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an overflow
signal is indicated. Note when overflow occurs the overflow flag is present for only one cycle. By counting these
overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow signal for signed
and unsigned operands are listed in Figure 2-22.
Figure 2-22. Accumulator Overflow/Underflow Conditions
000000011
000000010
000000001
000000000
3
2
1
0101111100
0101111101 253
252
Carry signal is generated for
one cycle when this
254
255
256
0101111110
0101111111
1010000000
1010000001 257
1010000010
0
boundary is crossed
111111111
111111110
111111101
511
510
509
258
Unsigned Operation
000000011
+3
+2
+1
0
-1
-2
-3
0101111100
0101111101 253
0101111110
0101111111
252
000000010
000000001
000000000
111111111
111111110
111111101
Overflow signal is generated
for one cycle when this
boundary is crossed
254
255
1010000000
1010000001
1010000010
256
255
254
Signed Operation
ispLEVER Module Manager
The user can access the sysDSP block via the ispLEVER Module Manager, which has options to configure each
DSP module (or group of modules) or through direct HDL instantiation. Additionally Lattice has partnered Math-
works to support instantiation in the Simulink tool, which is a Graphical Simulation Environment. Simulink works
with ispLEVER and dramatically shortens the DSP design cycle in Lattice FPGAs.
2-19
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Cor-
relators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo
Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available
DSP IPs.
Resources Available in the LatticeECP Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP family. Table 2-10 shows
the maximum available EBR RAM Blocks in each of the LatticeECP family. EBR blocks, together with Distributed
RAM can be used to store variables locally for the fast DSP operations.
Table 2-9. Number of DSP Blocks in LatticeECP Family
Device
DSP Block
9x9 Multiplier
18x18 Multiplier
36x36 Multiplier
LFECP6
4
5
32
40
48
56
64
80
16
20
24
28
32
40
4
5
LFECP10
LFECP15
LFECP20
LFECP33
LFECP40
6
6
7
7
8
8
10
10
Table 2-10. Embedded SRAM in LatticeECP Family
Total EBR SRAM
(Kbits)
Device
EBR SRAM Block
LFECP6
10
30
38
46
58
70
92
LFECP10
LFECP15
LFECP20
LFECP33
LFECP40
276
350
424
535
645
DSP Performance of the LatticeECP Family
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP family.
Table 2-11. DSP Block Performance of LatticeECP Family
DSP Performance
Device
DSP Block
MMAC
3680
4600
5520
6440
7360
9200
LFECP6
4
5
LFECP10
LFECP15
LFECP20
LFECP33
LFECP40
6
7
8
10
For further information on the sysDSP block, please see details of additional technical information at the end of this
data sheet.
2-20
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as
shown in Figure 2-23. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO
buffer, and receives input from the buffer.
Figure 2-23. PIC Diagram
PIO A
TD
D0
D1
TD
OPOS1
ONEG1
IOLT0
DDRCLK
Tristate
Register Block
(2 Flip Flops)
PADA
"T"
D0
D1
OPOS0
ONEG0
DDRCLK
IOLD0
Output
Register Block
(2 Flip Flops)
sysIO
Buffer
INCK
INDD
INFF
IPOS0
IPOS1
INCK
INDD
INFF
IPOS0
IPOS1
DI
Control
Muxes
Input
Register Block
(5 Flip Flops)
CLKO
CEO
LSR
CLK
CE
LSR
GSRN
GSR
CLKI
CEI
DQS
DDRCLKPOL
PADB
"C"
PIO B
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-24.
The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device
can be configured as LVDS transmit/receive pairs.
One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds
the DQS bus which spans the set of 16 PIOs. Figure 2-24 shows the assignment of DQS pins in each set of 16
PIOs.The exact DQS pins are shown in a dual function in the Logic Signal Connections table at the end of this data
sheet. Additional detail is provided in the Signal Descriptions table at the end of this data sheet. The DQS signal
from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed
for memories that support one DQS strobe per eight bits of data.
2-21
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Table 2-12. PIO Signal List
Name
Type
Description
CE0, CE1
CLK0, CLK1
LSR
Control from the core
Control from the core
Control from the core
Control from routing
Input to the core
Clock enables for input and output block FFs.
System clocks for input and output blocks.
Local Set/Reset.
GSRN
Global Set/Reset (active low).
INCK
Input to Primary Clock Network or PLL reference inputs.
DQS signal from logic (routing) to PIO.
DQS
Input to PIO
INDD
Input to the core
Unregistered data input to core.
INFF
Input to the core
Registered input on positive edge of the clock (CLK0).
DDRX registered inputs to the core.
IPOS0, IPOS1
ONEG0
OPOS0,
OPOS1 ONEG1
TD
Input to the core
Control from the core
Control from the core
Tristate control from the core
Tristate control from the core
Output signals from the core for SDR and DDR operation.
Output signals from the core for DDR operation
Signals to Tristate Register block for DDR operation.
Tristate signal from the core used in SDR operation.
DDRCLKPOL
Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block.
Figure 2-24. DQS Routing
PADA "T"
LVDS Pair
PIO A
PIO B
PIO A
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
Assigned
DQS Pin
PADA "T"
sysIO
Buffer
DQS
Delay
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PADA "T"
LVDS Pair
PADB "C"
PIO A
PIO B
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
2-22
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-25 shows the diagram of the input register block.
Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first
passes through an optional delay block. This delay, if selected, reduces input-register hold-time requirement when
using a global clock.
The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Figure 2-26 shows the input register waveforms for DDR operation and Figure 2-27 shows the design tool primi-
tives. The SDR/SYNC registers have reset and clock enable available.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,
see the DDR Memory section of this data sheet.
Figure 2-25. Input Register Diagram
DI
(From sysIO
Buffer)
INCK
INDD
Delay Block
Fixed Delay
SDR & Sync
Registers
DDR Registers
D0
D2
To Routing
Q
D
Q
D
D
IPOS0
IPOS1
D-Type
/LATCH
D-Type
D1
Q
D
Q
Q
D
D-Type
/LATCH
D-Type
D-Type
DQS Delayed
(From DQS
Bus)
CLK0
(From Routing)
DDRCLKPOL
(From DDR
Polarity Control Bus)
2-23
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-26. Input Register DDR Waveforms
DI
F
A
B
C
D
E
(In DDR Mode)
DQS
DQS
Delayed
B
A
D
C
D0
D2
Figure 2-27. INDDRXB Primitive
D
ECLK
QA
QB
LSR
SCLK
IDDRXB
CE
DDRCLKPOL
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for
DDR operation. Figure 2-28 shows the diagram of the Output Register Block.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Figure 2-29 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.
The additional register for DDR operation does not have reset or clock enable available.
2-24
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-28. Output Register Block
OUTDDN
Q
D
D-Type
/LATCH
ONEG0
0
DO
0
1
From
Routing
1
To sysIO
Buffer
OPOS0
Q
D
Latch
LE*
CLK1
Programmed
Control
*Latch is transparent when input is low.
Figure 2-29. ODDRXB Primitive
DA
DB
ODDRXB
Q
CLK
LSR
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-30 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
2-25
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-30. Tristate Register Block
TD
OUTDDN
Q
D
D-Type
/LATCH
ONEG1
0
TO
0
1
From
Routing
1
To sysIO
Buffer
OPOS1
Q
D
Latch
LE*
CLK1
Programmed
Control
*Latch is transparent when input is low.
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock is
selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from
the programmable DQS pin. The clock can optionally be inverted.
The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate
signal is passed through this block.
DDR Memory Support
Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input
(for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the EC devices
provide this capability. In addition to these registers, the EC devices contain two elements to simplify the design of
input structures for read operations: the DQS delay block and polarity control logic.
DLL Calibrated DQS Delay Block
Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment, however in DDR memories the clock
(referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS rout-
ing resource. The DQS signal also feeds polarity control logic which controls the polarity of the clock to the sync
registers in the input register blocks. Figures 2-31 and 2-32 show how the DQS transition signals are routed to the
PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration
(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of
the device as shown in Figure 2-32. The DLL loop is compensated for temperature, voltage and process variations
by the system clock and feedback loop.
2-26
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-31. DQS Local Bus.
PIO
Delay
Control
Bus
DDR
Datain
PAD
sysIO
Buffer
Input
Register Block
( 5 Flip Flops)
Polarity
Control
Bus
To Sync.
Reg.
DI
GSR
CLKI
CEI
DQS
Bus
To DDR
Reg.
DQS
DQS
PIO
DQS
Strobe
PAD
sysIO
Buffer
Polarity Control
Logic
DI
DQS
DQSDEL
Calibration Bus
from DLL
Figure 2-32. DLL Calibration Bus and DQS/DQS Transition Distribution
Delay Control Bus
Polarity Control Bus
DQS Bus
DLL
DLL
2-27
Architecture
Lattice Semiconductor
Polarity Control Logic
LatticeECP/EC Family Data Sheet
In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the
internal system Clock (during the READ cycle) is unknown.
The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup
and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is
used. This changes the edge on which the data is registered in the synchronizing registers in the input register
block. This requires evaluation at the start of each READ cycle for the correct clock polarity.
Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device
drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to
control the polarity of the clock to the synchronizing registers.
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in eight groups referred to as Banks. The sysIO buffers allow users to implement the wide
variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeECP/EC devices have eight sysIO buffer banks; each is capable of supporting multiple I/O standards. Each
sysIO bank has its own I/O supply voltage (V
), and two voltage references V
and V
resources allow-
CCIO
REF1
REF2
ing each bank to be completely independent from each other. Figure 2-33 shows the eight banks and their associ-
ated supplies.
In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-
X) are powered using V
LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold
CCIO.
input independent of V
In addition to the bank V
supplies, the LatticeECP/EC devices have a V core logic
CCIO.
CCIO CC
power supply, and a V
supply that power all differential and referenced buffers.
CCAUX
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be configured to be a
reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference volt-
ages.
2-28
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Figure 2-33. LatticeECP/EC Banks
Bank 0
Bank 1
VCCIO7
VCCIO2
VREF1(2)
VREF2(2)
GND
VREF1(7)
VREF2(7)
GND
VCCIO6
VCCIO3
VREF1(6)
VREF2(6)
VREF1(3)
VREF2(3)
GND
GND
M
Bank 5
Bank 4
Note: N and M are the maximum number of I/Os per bank.
LatticeECP/EC devices contain two types of sysIO buffer pairs.
1. Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)
The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be
configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have PCI clamp.
2. Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Only the left and right banks have LVDS differential output drivers.
Supported Standards
The LatticeECP/EC sysIO buffer supports both single-ended and differential standards. Single-ended standards
can be further subdivided into LVCMOS, LVTTL and other standards.The buffers support the LVTTL, LVCMOS 1.2,
1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable
2-29
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain.
Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS,
BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards
(together with their supply and reference voltages) supported by the LatticeECP/EC devices. For further informa-
tion on utilizing the sysIO buffer to support a variety of standards please see the details of additional technical infor-
mation at the end of this data sheet.
Table 2-13. Supported Input Standards
Input Standard
Single Ended Interfaces
LVTTL
LVCMOS332
LVCMOS252
V
(Nom.)
V
1 (Nom.)
CCIO
REF
—
—
—
—
—
—
—
—
—
—
LVCMOS18
1.8
1.5
—
LVCMOS15
LVCMOS122
PCI
3.3
—
HSTL18 Class I, II
HSTL18 Class III
0.9
1.08
0.75
0.9
—
HSTL15 Class I
—
HSTL15 Class III
—
SSTL3 Class I, II
1.5
—
SSTL2 Class I, II
1.25
0.9
—
SSTL18 Class I
—
Differential Interfaces
Differential SSTL18 Class I
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I, III
Differential HSTL18 Class I, II, III
LVDS, LVPECL, BLVDS, RSDS
—
—
—
—
—
—
—
—
—
—
—
—
1. When not specified V
can be set anywhere in the valid operating range.
CCIO
2. JTAG inputs do not have a fixed threshold option and always follow V
CCJ.
2-30
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Table 2-14. Supported Output Standards
Output Standard
Single-ended Interfaces
LVTTL
Drive
V
(Nom.)
CCIO
4mA, 8mA, 12mA, 16mA, 20mA
3.3
LVCMOS33
4mA, 8mA, 12mA 16mA, 20mA
3.3
2.5
1.8
1.5
1.2
—
LVCMOS25
4mA, 8mA, 12mA, 16mA, 20mA
LVCMOS18
4mA, 8mA, 12mA, 16mA
LVCMOS15
4mA, 8mA
LVCMOS12
2mA, 6mA
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
—
4mA, 8mA, 12mA 16mA
—
4mA, 8mA
2mA, 6mA
N/A
—
—
3.3
1.8
1.5
3.3
2.5
1.8
HSTL18 Class I, II, III
HSTL15 Class I, III
SSTL3 Class I, II
N/A
N/A
N/A
SSTL2 Class I, II
N/A
SSTL18 Class I
N/A
Differential Interfaces
Differential SSTL3, Class I, II
Differential SSTL2, Class I, II
Differential SSTL18, Class I
Differential HSTL18, Class I, II, III
Differential HSTL15, Class I, III
LVDS
BLVDS1
LVPECL1
RSDS1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
2.5
1.8
1.8
1.5
2.5
2.5
3.3
2.5
1. Emulated with external resistors.
Hot Socketing
The LatticeECP/EC devices have been carefully designed to ensure predictable behavior during power-up and
power-down. Power supplies can be sequenced in any order. During power up and power-down sequences, the
I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition,
leakage into I/O pins is controlled to within specified limits, this allows for easy integration with the rest of the
system. These capabilities make the LatticeECP/EC ideal for many multiple power supply and hot-swap applica-
tions.
Recommended Power Up Sequence: As described in the previous paragraph, the supplies can be sequenced
in any order. However, once internal power good is achieved (determined by VCC, VCCAUX, VCCIO bank 5) the
part releases I/Os from tri-state and the management of I/Os becomes the designers responsibility. To simplify a
system design it is therefore recommended that supplies be sequenced VCCIO, VCC, VCCAUX.
2-31
Architecture
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Configuration and Testing
The following section describes the configuration and testing features of the LatticeECP/EC family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test
access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification.The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
V
and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
CCJ
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeECP/EC devices contain two possible ports that can be used for device configuration. The test access
port (TAP), which supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial
configuration.
The TAP supports both the IEEE Std. 1149.1 Boundary Scan specification and the IEEE Std. 1532 In-System Con-
figuration specification. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and
the rest being dual-use pins. When sysCONFIG mode is not used, these dual-use pins are available for general
purpose I/O. There are four configuration options for LatticeECP/EC devices:
1. Industry standard SPI memories.
2. Industry standard byte wide flash and ispMACH 4000 for control/addressing.
3. Configuration from system microprocessor via the configuration bus or TAP.
4. Industry standard FPGA board memory.
On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a
configuration port is selected, that port is locked and another configuration port cannot be activated until the next
power-up sequence.
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
Internal Logic Analyzer Capability (ispTRACY)
All LatticeECP/EC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide
capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace
memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at com-
pile time.
For more information on ispTRACY, please see information regarding additional technical documentation at the
end of this data sheet.
External Resistor
LatticeECP/EC devices require a single external, 10K ohm +/- 1% value between the XRES pin and ground.
Device configuration will not be completed if this resistor is missing. There is no boundary scan register on the
external resistor pad.
2-32
Architecture
Lattice Semiconductor
Oscillator
LatticeECP/EC Family Data Sheet
Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master serial clock for con-
figuration. The oscillator and the master serial clock run continuously. The default value of the master serial clock is
2.5MHz. Table 2-15 lists all the available Master Serial Clock frequencies. When a different Master Serial Clock is
selected during the design process, the following sequence takes place:
1. User selects a different Master Serial Clock frequency.
2. During configuration the device starts with the default (2.5MHz) Master Serial Clock frequency.
3. The clock configuration settings are contained in the early configuration bit stream.
4. The Master Serial Clock frequency changes to the selected frequency once the clock configuration bits are
received.
For further information on the use of this oscillator for configuration, please see details of additional technical docu-
mentation at the end of this data sheet.
Table 2-15. Selectable Master Serial Clock (CCLK) Frequencies During Configuration
CCLK (MHz)
CCLK (MHz)
CCLK (MHz)
2.5*
4.3
13
15
20
26
30
34
41
45
51
55
60
130
—
5.4
6.9
8.1
9.2
10.0
—
Density Shifting
The LatticeECP/EC family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design
targeted for a high-density device to a lower density device. However, the exact details of the final resource utiliza-
tion will impact the likely success in each case.
2-33
LatticeECP/EC Family Data Sheet
DC and Switching Characteristics
November 2004
Preliminary Data Sheet
Absolute Maximum Ratings1, 2, 3
Supply Voltage V . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V
CC
Supply Voltage V
Supply Voltage V
. . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V
CCAUX
. . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V
CCJ
Output Supply Voltage V
. . . . . . . . . . . . . . . . -0.5 to 3.75V
CCIO
Input Voltage Applied4 . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.25V
I/O Tristate Voltage Applied 4 . . . . . . . . . . . . . . . . . -0.5 to 3.75V
Storage Temperature (Ambient) . . . . . . . . . . . . . . -65 to 150°C
Junction Temp. (Tj) +125°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (V
+ 2) volts is permitted for a duration of <20ns.
IHMAX
Recommended Operating Conditions
Symbol
Parameter
Min.
1.14
3.135
1.140
1.140
0
Max.
1.26
Units
V
V
V
V
V
Core Supply Voltage
CC
Auxiliary Supply Voltage
I/O Driver Supply Voltage
3.465
3.465
3.465
+85
V
CCAUX
1, 2
CCIO
V
1
Supply Voltage for IEEE 1149.1 Test Access Port
Junction Commercial Operation
V
CCJ
t
t
°C
°C
JCOM
JIND
Junction Industrial Operation
-40
100
1. If V
or V
is set to 1.2V, they must be connected to the same power supply as V
If V
or V
is set to 3.3V, they must be con-
CCJ
CCIO
CCJ
CC.
CCIO
nected to the same power supply as V
.
CCAUX
2. See recommended voltages by I/O standard in subsequent table.
Hot Socketing Specifications1, 2, 3, 4
Symbol
Parameter
Condition
Min.
Typ.
Max
Units
I
Input or I/O leakage Current
0 ≤ V ≤ V (MAX)
—
—
+/-1000
µA
DK
IN
IH
1. Insensitive to sequence of V
V
and V
. However, assumes monotonic rise/fall rates for V
V
and V
CC, CCAUX
CCIO
CC, CCAUX CCIO.
2. 0 ≤ V ≤ V (MAX), 0 ≤ V
≤ V
(MAX) or 0 ≤ V
≤ V
(MAX).
CC
CC
CCIO
CCIO
CCAUX
CCAUX
3. I is additive to I
I
or I
.
DK
PU, PW
BH
4. LVCMOS and LVTTL only.
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
3-1
DC and Switching_01.2
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
- 0.2V)
CCIO
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
Max.
10
Units
µA
µA
µA
µA
µA
µA
µA
µA
V
0 ≤ V ≤ (V
IN
1
I
I
Input or I/O Low leakage
IL, IH
(V
- 0.2V) ≤ V ≤ 3.6V
—
40
CCIO
IN
CCIO
I
I
I
I
I
I
I/O Active Pull-up Current
0 ≤ V ≤ 0.7 V
30
150
-150
—
PU
IN
I/O Active Pull-down Current
Bus Hold Low sustaining current
Bus Hold High sustaining current
V
V
V
(MAX) ≤ V ≤ V (MAX)
-30
30
PD
IL
IN
IH
= V (MAX)
BHLS
BHHS
BHLO
BHLH
IN
IN
IL
= 0.7V
-30
—
—
CCIO
Bus Hold Low Overdrive current 0 ≤ V ≤ V (MAX)
150
-150
IN
IH
Bus Hold High Overdrive current 0 ≤ V ≤ V (MAX)
—
IN
IH
V
Bus Hold trip Points
I/O Capacitance2
0 ≤ V ≤ V (MAX)
V
(MAX)
V
(MIN)
IH
BHT
IN
IH
IL
V
V
= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
CCIO
C1
C2
—
8
6
—
—
pf
pf
= 1.2V, V = 0 to V (MAX)
CC
IO
IH
V
V
= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
Dedicated Input Capacitance2
—
CCIO
= 1.2V, V = 0 to V (MAX)
CC
IO
IH
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. T 25oC, f = 1.0MHz
A
3-2
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Supply Current (Standby)1, 2, 3, 4
Over Recommended Operating Conditions
Symbol
Parameter
Devices
Typ.5
Max.
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
LFEC1
LFEC3
LFECP6/LFEC6
LFECP10/LFEC10
LFECP15/LFEC15
LFECP20/LFEC20
LFECP33/LFEC33
LFECP40/LFEC40
LFEC1
I
Core Power Supply Current
CC
100
LFEC3
LFECP6/LFEC6
LFECP10/LFEC10
LFECP15/LFEC15
LFECP20/LFEC20
LFECP33/LFEC33
LFECP40/LFEC40
I
I
Auxiliary Power Supply Current
CCAUX
15
8
LFEC1, LFEC3, LFEC6, LFECP6, LFECP10,
LFECP15, LFECP20, LFECP33, LFECP40,
LFEC10, LFEC15, LFEC20, LFEC33, LFEC40,
PLL Power Supply Current
(per PLL)
mA
CCPLL
I
I
Bank Power Supply Current6
2
5
mA
mA
CCIO
CCJ
V
Power Supply Current
CCJ
1. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.
2. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the V
3. Frequency 0MHz.
or GND.
CCIO
4. Pattern represents typical design with 65% logic, 55% EBR, 10% routing utilization.
5. T =25oC, power supplies at nominal voltage.
J
6. Per bank.
3-3
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Initialization Supply Current1,2,3,4,5,6
Over Recommended Operating Conditions
Symbol
Parameter
Devices
Typ.6
Max.
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
LFEC1
LFEC3
LFECP6/LFEC6
LFECP10/LFEC10
LFECP15/LFEC15
LFECP20/LFEC20
LFECP33/LFEC33
LFECP40/LFEC40
LFEC1
I
Core Power Supply Current
CC
150
LFEC3
LFECP6/LFECP6
LFECP10/LFEC10
LFECP15/LFEC15
LFECP20/LFEC20
LFECP33/LFEC33
LFECP40/LFEC40
I
I
Auxiliary Power Supply Current
CCAUX
25
12
LFEC1, LFEC3, LFEC6, LFECP6, LFECP10,
LFECP15, LFECP20, LFECP33, LFECP40,
LFEC10, LFEC15, LFEC20, LFEC33, LFEC40,
PLL Power Supply Current
(per PLL)
mA
CCPLL
I
I
Bank Power Supply Current7
5
mA
mA
CCIO
CCJ
V
Power Supply Current
10
CCJ
1. Until DONE signal is active.
2. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.
3. Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at the V
4. Frequency 0MHz.
or GND.
CCIO
5. Pattern represents typical design with 65% logic, 55% EBR, 10% routing utilization.
6. T =25oC, power supplies at nominal voltage.
J
7. Per bank.
3-4
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
sysIO Recommended Operating Conditions
V
V
(V)
REF
CCIO
Standard
LVCMOS 3.3
Min.
3.135
2.375
1.71
Typ.
3.3
2.5
1.8
1.5
1.2
3.3
3.3
2.5
2.5
3.3
1.5
1.5
1.8
1.8
2.5
3.3
2.5
2.5
Max.
3.465
2.625
1.89
Min.
—
Typ.
—
Max.
—
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
LVTTL
—
—
—
—
—
—
1.425
1.14
1.575
1.26
—
—
—
—
—
—
3.135
3.135
1.71
3.465
3.465
1.89
—
—
—
PCI
—
—
—
SSTL18 Class I
SSTL2 Class I, II
SSTL3 Class I, II
HSTL15 Class I
HSTL15 Class III
HSTL 18 Class I, II
HSTL 18 Class III
LVDS
1.15
1.15
1.3
0.68
—
1.25
1.25
1.5
0.75
0.9
0.9
1.08
—
1.35
1.35
1.7
0.9
—
2.375
3.135
1.425
1.425
1.71
2.625
3.465
1.575
1.575
1.89
—
—
1.71
1.89
—
—
2.375
3.135
2.375
2.375
2.625
3.465
2.625
2.625
—
—
LVPECL1
BLVDS1
RSDS1
—
—
—
—
—
—
—
—
—
1. Inputs on chip. Outputs are implemented with the addition of external resistors.
3-5
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
sysIO Single-Ended DC Electrical Characteristics
V
V
IH
1
1
IL
Input/Output
Standard
V
Max.
(V)
V
Min.
(V)
I
I
OH
OL
OH
OL
Min. (V) Max. (V)
Min. (V)
Max. (V)
(mA)
(mA)
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.4
0.2
0.4
0.2
0.4
V
V
V
V
V
- 0.4
- 0.2
- 0.4
- 0.2
- 0.4
- 0.2
CCIO
CCIO
CCIO
CCIO
CCIO
LVCMOS 3.3
LVTTL
-0.3
-0.3
-0.3
0.8
0.8
0.7
2.0
2.0
1.7
3.6
0.1
-0.1
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
3.6
3.6
0.1
-0.1
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
LVCMOS 2.5
0.2
0.4
0.2
0.4
0.2
0.4
0.2
V
V
V
V
V
V
V
0.1
-0.1
-16, -12, -8, -4
-0.1
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
- 0.4 16, 12, 8, 4
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
-0.3
-0.3
-0.3
0.35V
0.65V
3.6
3.6
3.6
CCIO
CCIO
CCIO
- 0.2
- 0.4
- 0.2
- 0.4
- 0.2
0.1
8, 4
0.1
6, 2
0.1
1.5
8
-8, -4
-0.1
0.35V
0.65V
CCIO
-6, -2
-0.1
0.35V
0.65V
CC
CC
PCI
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
0.3V
0.5V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.1V
0.9V
-0.5
CCIO
CCIO
CCIO
CCIO
SSTL3 class I
SSTL3 class II
SSTL2 class I
SSTL2 class II
SSTL18 class I
HSTL15 class I
HSTL15 class III
HSTL18 class I
HSTL18 class II
HSTL18 class III
V
- 0.2
V
+ 0.2
0.7
V
- 1.1
- 0.9
- 0.62
- 0.43
- 0.4
- 0.4
- 0.4
- 0.4
- 0.4
- 0.4
-8
REF
REF
REF
REF
CCIO
CCIO
V
- 0.2
- 0.18
- 0.18
V
+ 0.2
+ 0.18
+ 0.18
+ 0.125
0.5
0.54
0.35
0.4
V
16
-16
V
V
V
V
V
V
7.6
15.2
6.7
8
-7.6
REF
REF
REF
REF
REF
CCIO
CCIO
-15.2
-6.7
V
- 0.125 V
V
REF
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
V
V
V
V
V
- 0.1
- 0.1
- 0.1
- 0.1
- 0.1
V
V
V
V
V
+ 0.1
+ 0.1
+ 0.1
+ 0.1
+ 0.1
0.4
V
-8
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
0.4
V
V
V
V
24
-8
0.4
9.6
16
-9.6
0.4
-16
0.4
24
-8
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
Rev F 0.17
3-6
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
sysIO Differential Electrical Characteristics
LVDS
Over Recommended Operating Conditions
Parameter
Symbol
Parameter Description
Input voltage
Test Conditions
Min.
0
Typ.
—
Max.
2.4
Units
V
V
V
V
INP, INM
Differential input threshold
Input common mode voltage
Input current
+/-100
—
—
mV
V
THD
100mV ≤ V
V
V
V
/2
/2
/2
1.2
1.2
1.2
—
1.8
THD
THD
THD
THD
THD
V
200mV ≤ V
350mV ≤ V
1.9
V
CM
2.0
V
THD
I
Power on or power off
R = 100 Ohm
—
+/-10
1.60
—
µA
V
IN
V
V
V
Output high voltage for V or V
—
1.38
1.03
350
OH
OL
OD
OP
OM
T
Output low voltage for V or V
R = 100 Ohm
0.9V
250
V
OP
OM
T
Output voltage differential
(V - V ), R = 100 Ohm
450
mV
OP
OM
T
Change in V between high and
low
OD
∆V
—
—
50
mV
OD
V
Output voltage offset
(V - V )/2, R = 100 Ohm
1.125
—
1.25
—
1.375
50
V
OS
OP
OM
T
∆V
Change in V between H and L
mV
OS
OS
V
= 0V Driver outputs
OD
I
Output short circuit current
—
—
6
mA
OSD
shorted
3-7
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
BLVDS
The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS
outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when
multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-1 is one
possible solution for bi-directional multi-point differential signals.
Figure 3-1. BLVDS Multi-point Output Example
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
2.5V
2.5V
2.5V
80
80
45-90 ohms
45-90 ohms
80
80
80
80
80
. . .
+
-
+
-
-
-
2.5V
2.5V
2.5V
2.5V
Table 3-1. BLVDS DC Conditions1
Over Recommended Operating Conditions
Typical
Parameter
Description
Output impedance
Zo = 45 Zo = 90
Units
ohm
ohm
ohm
V
Z
100
45
100
90
OUT
R
R
Left end termination
Right end termination
Output high voltage
TLEFT
TRIGHT
OH
45
90
V
V
V
V
1.375
1.125
0.25
1.25
11.2
1.48
1.02
0.46
1.25
10.2
Output low voltage
V
OL
Output differential voltage
Output common mode voltage
DC output current
V
OD
V
CM
I
mA
DC
1. For input buffer, see LVDS table.
3-8
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LVPECL
The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in
Figure 3-2 is one possible solution for point-to-point signals.
Figure 3-2. Differential LVPECL
3.3V
100 ohms
+
~150 ohms
100 ohms
3.3V
-
100 ohms
Off-chip
Transmission line, Zo = 100 ohm differential
Table 3-2. LVPECL DC Conditions1
Over Recommended Operating Conditions
Parameter
Description
Output impedance
Typical
100
Units
ohm
ohm
ohm
V
Z
OUT
R
R
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
150
P
100
T
V
V
V
V
2.03
1.27
0.76
1.65
85.7
12.7
OH
OL
OD
CM
BACK
V
Output differential voltage
Output common mode voltage
Back impedance
V
V
Z
ohm
mA
I
DC output current
DC
1. For input buffer, see LVDS table.
For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni-
cal information at the end of this data sheet.
3-9
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
RSDS
The LatticeECP/EC devices support differential RSDS standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-3
is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for
RSDS operation. Resistor values in Figure 3-3 are industry standard values for 1% resistors.
Figure 3-3. RSDS (Reduced Swing Differential Standard)
VCCIO = 2.5V
294
Zo = 100
+
VCCIO = 2.5V
121
100
-
294
On-chip
Off-chip
Emulated
RSDS Buffer
Table 3-3. RSDS DC Conditions
Parameter
Description
Typical
20
Units
ohm
ohm
ohm
ohm
V
Z
Output impedance
OUT
R
R
R
Driver series resistor
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
294
S
121
P
100
T
V
V
V
V
1.35
1.15
0.20
1.25
101.5
3.66
OH
OL
OD
CM
BACK
V
Output differential voltage
Output common mode voltage
Back impedance
V
V
Z
ohm
mA
I
DC output current
DC
5V Tolerant Input Buffer
The input buffers of the LatticeECP/EC family of devices can support 5V signals by using a PCI Clamp and an
external series resistor as shown in Figure 3-4.
Figure 3-4. 5 V Tolerant Input Buffer
VCCIO
5V Signals from
Legacy Systems
External
Resistor
3-10
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Figure 3-5. Typical PCI Clamp Current
400
350
300
250
200
150
100
50
0
0
1
2
3
4
5
6
7
8
Voltage (V)
3-11
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Typical Building Block Function Performance
Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Function
Basic Functions
-5 Timing
Units
16 bit decoder
32 bit decoder
64 bit decoder
4:1 MUX
6.2
7.2
7.7
4.8
5.1
6.1
6.5
5.3
ns
ns
ns
ns
ns
ns
ns
ns
8:1 MUX
16:1 MUX
32:1 MUX
Combinatorial (pin to LUT to pin)
Register-to-Register Performance
Function
Basic Functions
-5 Timing
Units
16 bit decoder
331
277
240
727
482
439
382
391
337
190
410
315
215
155
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
32 bit decoder
64 bit decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
8-bit adder
16-bit adder
64-bit adder
16-bit counter
32-bit counter
64-bit counter
64-bit accumulator
Embedded Memory Functions
256x36 Single Port RAM
512x18 True-Dual Port RAM
Distributed Memory Functions
16x2 Single Port RAM
64x2 Single Port RAM
128x4 Single Port RAM
32x2 Pseudo-Dual Port RAM
64x4 Pseudo-Dual Port RAM
DSP Function1
280
280
MHz
MHz
549
259
205
360
301
MHz
MHz
MHz
MHz
MHz
9x9 Pipelined Multiply/Accumulate
18x18 Pipelined Mutiply/Accumulate
36x36 Pipelined Mutiply
1. Applies to LatticeECP devices only.
250
230
210
MHz
MHz
MHz
2. The above timing numbers were generated using ispLEVER tool, exact performance may vary with design and tool version. The tool uses
internal parameters that have been characterized but are not tested on every device.
3-12
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Derating Timing Tables
Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case
numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be
much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and
voltage multiply the noted numbers with the derating factors provided below.
The junction temperature for the FPGA depends on the power dissipation by the device, the package thermal char-
acteristics (Θ ), and the ambient temperature, as calculated with the following equation:
JA
T
= T
+ (Power * Θ )
JMAX
AMAX JA
The user must determine this temperature and then use it to determine the derating factor based on the following
derating tables: T °C.
J
Table 3-4. Delay Derating Table for Internal Blocks
Power Supply Voltage
T °C
T °C
J
J
Commercial
Industrial
1.14V
0.82
0.82
0.89
0.93
1.00
1.00
1.00
1.02
1.2V
0.77
0.76
0.83
0.87
0.94
0.95
0.95
0.96
1.26V
0.71
0.71
0.78
0.81
0.89
0.90
0.90
0.91
—
—
-40
-25
0
20
25
45
85
105
115
—
100
110
125
—
3-13
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC External Switching Characteristics
Over Recommended Operating Conditions
-5
-4
-3
Parameter
Description
Device
Min. Max. Min. Max. Min. Max. Units
General I/O Pin Parameters (Using Primary Clock without PLL)1
t
t
t
Clock to Output - PIO Output Register
Clock to Data Setup - PIO Input Register
Clock to Data Hold - PIO Input Register
LFEC20
LFEC20
LFEC20
—
5.71
—
—
6.85
—
—
7.99
—
ns
ns
ns
CO
SU
H
0.00
3.41
0.00
4.09
0.00
4.77
—
—
—
Clock to Data Setup - PIO Input Register
with data input delay
t
LFEC20
3.84
—
4.62
—
5.38
—
ns
SU_DEL
Clock to Data Hold - PIO Input Register
with Input Data Delay
t
f
LFEC20
LFEC20
-0.44
—
—
-0.54
—
—
-0.61
—
—
ns
H_DEL
LVDS I/O Buffer Frequency
420
378
340
MHz
MAX_IO
DDR I/O Pin Parameters2, 3
4
t
t
t
t
f
Data Valid After DQS (DDR Read)
Data Hold After DQS (DDR Read)
Data Valid Before DQS
LFEC20
LFEC20
LFEC20
LFEC20
LFEC20
—
0.668
0.2
0.192
—
—
0.668
0.2
0.192
—
—
0.668
0.2
0.192
—
UI
UI
DVADQ
DVEDQ
DQVBS
DQVAS
4
—
—
—
UI
Data Valid After DQS
0.2
—
0.2
—
0.2
—
UI
DDR Clock Frequency
95
200
95
166
95
133
MHz
MAX_DDR
Primary and Secondary Clock
f
t
t
Frequency for Primary Clock Tree
Clock Pulse Width for Primary Clock
Primary Clock Skew within an I/O Bank
LFEC20
LFEC20
LFEC20
—
1.19
—
420
—
—
1.19
—
378
—
—
1.19
—
340
—
MHz
ns
MAX_PRI
W_PRI
250
300
350
ps
SKEW_PRI
1. General timing numbers based on LVCMOS2.5V, 12 mA.
2. DDR timing numbers based on SSTL I/O.
3. DDR specifications are characterized but not tested.
4. UI is average bit period.
Rev F 0.17
Figure 3-6. DDR Timings
DQ and DQS Read Timings
DQS
DQ
tDVADQ
tDVEDQ
DQ and DQS Write Timings
DQS
DQ
tDQVBS
tDQVAS
3-14
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC Internal Timing Parameters1
Over Recommended Operating Conditions
-5
-4
-3
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
PFU/PFF Logic Mode Timing
t
t
t
t
t
t
t
LUT4 delay (A to D inputs to F output)
LUT6 delay (A to D inputs to OFX output)
Set/Reset to output of PFU
-
-
0.25
-
-
0.31
-
-
0.36
ns
ns
ns
ns
ns
ns
ns
LUT4_PFU
LUT6_PFU
LSR_PFU
SUM_PFU
HM_PFU
0.55
0.66
0.77
-
0.81
-
0.98
-
1.14
Clock to Mux (M0,M1) input setup time
Clock to Mux (M0,M1) input hold time
Clock to D input setup time
0.08
-0.06
0.11
-0.04
-
-
0.10
-0.07
0.14
-0.04
-
-
0.11
-0.08
0.16
-0.05
-
-
-
-
-
-
-
-
-
-
-
SUD_PFU
HD_PFU
Clock to D input hold time
Clock to Q delay, D-type register configura-
tion
0.43
0.51
0.60
t
t
t
ns
ns
ns
CK2Q_PFU
LE2Q_PFU
LD2Q_PFU
Clock to Q delay latch configuration
-
-
0.54
0.50
-
-
0.65
0.60
-
-
0.76
0.69
D to Q throughput delay when latch is
enabled
PFU Memory Mode Timing
t
t
t
t
t
t
t
Clock to Output
-
0.43
-
0.51
-
0.60
ns
ns
ns
ns
ns
ns
ns
CORAM_PFU
SUDATA_PFU
HDATA_PFU
Data Setup Time
-0.25
-0.06
-0.66
-0.27
-0.30
-0.21
-
-
-
-
-
-
-0.30
-0.07
-0.79
-0.33
-0.36
-0.25
-
-
-
-
-
-
-0.34
-0.08
-0.92
-0.38
-0.42
-0.29
-
-
-
-
-
-
Data Hold Time
Address Setup Time
Address Hold Time
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
Write/Read Enable Setup Time
Write/Read Enable Hold Time
PIC Timing
PIO Input/Output Buffer Timing
t
t
Input Buffer Delay
Output Buffer Delay
-
-
0.56
2.07
-
-
0.67
2.49
-
-
0.78
2.90
ns
ns
IN_PIO
OUT_PIO
IOLOGIC Input/Output Timing
Input Register Setup Time (Data Before
Clock)
-
0.12
-
0.14
-
0.17
t
ns
SUI_PIO
t
t
t
t
t
t
Input Register Hold Time (Data after Clock)
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
-
-0.09
0.82
-0.02
0.12
-
-
-0.11
0.98
-0.02
0.14
-
-
-0.13
1.15
-0.03
0.17
-
ns
ns
ns
ns
ns
ns
HI_PIO
-
-
-
-
-
-
COO_PIO
SUCE_PIO
HCE_PIO
SULSR_PIO
HLSR_PIO
-
-
-
0.10
-0.24
0.12
-0.29
0.14
-0.34
Set/Reset Hold Time
-
-
-
EBR Timing
t
t
t
t
t
t
t
Clock to output from Address or Data
Clock to output from EBR output Register
Setup Data to EBR Memory
-
3.82
-
4.58
-
5.34
ns
ns
ns
ns
ns
ns
ns
CO_EBR
-
0.74
-
0.88
-
1.03
COO_EBR
-0.34
0.37
-0.34
0.37
-0.22
-
-
-
-
-
-0.41
0.44
-0.41
0.45
-0.26
-
-
-
-
-
-0.48
0.52
-0.48
0.52
-0.30
-
-
-
-
-
SUDATA_EBR
HDATA_EBR
SUADDR_EBR
HADDR_EBR
SUWREN_EBR
Hold Data to EBR Memory
Setup Address to EBR Memory
Hold Address to EBR Memory
Setup Write/Read Enable to PFU Memory
3-15
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC Internal Timing Parameters1 (Continued)
Over Recommended Operating Conditions
-5
-4
-3
Parameter
Description
Min.
0.23
0.28
Max.
Min.
0.28
0.34
Max.
Min.
0.33
0.40
Max.
Units
t
t
Hold Write/Read Enable to PFU Memory
-
-
-
-
-
-
ns
HWREN_EBR
Clock Enable Setup Time to EBR Output
Register
ns
ns
ns
SUCE_EBR
HCE_EBR
RSTO_EBR
Clock Enable Hold Time to EBR Output
Register
-0.24
-
-
-0.29
-
-
-0.34
-
-
t
t
Reset To Output Delay Time from EBR Out-
put Register
1.00
1.20
1.40
PLL Parameters
t
t
t
Reset Recovery to Rising Clock
Reset Signal Setup Time
Reset Signal Pulse Width
-
-
-
ns
ns
ns
RSTREC
RSTSU
RSTW
-
-
-
-
-
-
10.0
10.0
10.0
DSP Block Timing2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Input Register Setup Time
Input Register Hold Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-0.44
0.80
3.31
0.80
6.72
0.80
8.33
4.80
1.47
1.47
3.31
0.71
3.31
0.80
3.31
0.80
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-0.35
0.96
3.98
0.96
8.07
0.96
10.35
5.89
1.77
1.77
3.98
0.86
3.98
0.96
3.98
0.96
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-0.27
1.12
4.64
1.12
9.41
1.12
12.07
6.87
2.06
2.06
4.64
1.00
4.64
1.12
4.64
1.12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUI_DSP
HI_DSP
Pipeline Register Setup Time
Pipeline Register Hold Time
Output Register Setup Time
Output Register Hold Time
Input Register Clock to Output Time
Pipeline Register Clock to Output Time
Output Register Clock to Output Time
Overflow Register Clock to Output Time
AdSub Setup Time
SUP_DSP
HP_DSP
SUO_DSP
HO_DSP
COI_DSP
COP_DSP
COO_DSP
COOVRFL_DSP
SUADSUB
HADSUB
AdSub Hold Time
Sign Setup Time
SUSIGN
Sign Hold Time
HSIGN
Accumulator Load Setup Time
Accumulator Load Hold Time
SUACCSLOAD
HACCSLOAD
1. Internal parameters are characterized but not tested on every device.
2. These parameters apply to LatticeECP devices only.
Rev F 0.17
3-16
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Timing Diagrams
PFU Timing Diagrams
Figure 3-7. Slice Single/Dual Port Write Cycle Timing
CK
WRE
AD
AD[3:0]
D
DI[1:0]
DO[1:0]
Old Data
D
Figure 3-8. Slice Single /Dual Port Read Cycle Timing
WRE
AD
AD[3:0]
DO[1:0]
Old Data
D
3-17
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
EBR Memory Timing Diagrams
Figure 3-9. Read/Write Mode (Normal)
CLKA
CSA
WEA
ADA
DIA
A0
A1
D1
A0
A1
A0
tSU tH
D0
tACCESS
tACCESS
D0
D0
D1
DOA
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-10. Read/Write Mode with Input and Output Registers
CLKA
CSA
WEA
ADA
DIA
A1
A0
A1
D1
A0
A0
t
t
H
SU
D0
D1
DOA
D0
Mem(n) data from previous read
D0
DOA
t
t
ACCESS
ACCESS
DOA (Regs)
D1
D0
Mem(n) data from previous read
output is only updated during a read cycle
3-18
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Figure 3-11. Read Before Write (SP Read/Write on Port A, Input Registers Only)
CLKA
CSA
WEA
ADA
A0
A1
D1
A0
A1
A0
t
t
H
SU
D2
D3
D1
D0
DIA
t
t
t
t
t
ACCESS
ACCESS
ACCESS
ACCESS
ACCESS
old A0 Data
old A1 Data
D0
D1
DOA
D2
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-12. Write Through (SP Read/Write On Port A, Input Registers Only)
CLKA
CSA
WEA
Three consecutive writes to A0
ADA
A0
A1
D1
A0
t
t
H
SU
D2
D3
D2
D4
D0
DIA
t
t
t
t
ACCESS
ACCESS
ACCESS
ACCESS
Data from Prev Read
or Write
D0
D1
D3
DOA
D4
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
3-19
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC Family Timing Adders1, 2, 3
Over Recommended Operating Conditions
Buffer Type
Input Adjusters
Description
-5
-4
-3
Units
LVDS25
LVDS
0.41
0.41
0.50
0.41
0.41
0.41
0.37
0.37
0.37
0.40
0.40
0.37
0.37
0.46
0.46
0.39
0.39
0.43
0.43
0.38
0.38
0.40
0.37
0.07
0.07
0.00
0.07
0.24
1.27
0.07
0.50
0.50
0.60
0.49
0.49
0.49
0.44
0.44
0.44
0.48
0.48
0.44
0.44
0.55
0.55
0.47
0.47
0.51
0.51
0.45
0.45
0.48
0.44
0.09
0.09
0.00
0.09
0.29
1.52
0.09
0.58
0.58
0.70
0.57
0.57
0.57
0.52
0.52
0.52
0.56
0.56
0.51
0.51
0.64
0.64
0.55
0.55
0.60
0.60
0.53
0.53
0.56
0.51
0.10
0.10
0.00
0.10
0.33
1.77
0.10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLVDS25
BLVDS
LVPECL
LVPECL33
HSTL18_I
HSTL18_II
HSTL18_III
HSTL18D_I
HSTL18D_II
HSTL18D_III
HSTL15_I
HSTL15_III
HSTL15D_I
HSTL15D_III
SSTL33_I
HSTL_18 class I
HSTL_18 class II
HSTL_18 class III
Differential HSTL 18 class I
Differential HSTL 18 class II
Differential HSTL 18 class III
HSTL_15 class I
HSTL_15 class III
Differential HSTL 15 class I
Differential HSTL 15 class III
SSTL_3 class I
SSTL33_II
SSTL33D_I
SSTL33D_II
SSTL25_I
SSTL_3 class II
Differential SSTL_3 class I
Differential SSTL_3 class II
SSTL_2 class I
SSTL25_II
SSTL25D_I
SSTL25D_II
SSTL18_I
SSTL_2 class II
Differential SSTL_2 class I
Differential SSTL_2 class II
SSTL_18 class I
SSTL18D_I
LVTTL33
Differential SSTL_18 class I
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
LVCMOS 1.5
LVCMOS 1.2
PCI
Output Adjusters
LVDS25E
LVDS 2.5 E
-0.03
-0.59
0.18
-0.04
-0.71
0.22
-0.04
-0.83
0.26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDS25
LVDS 2.5
BLVDS25
BLVDS 2.5
LVPECL33
HSTL18_I
HSTL18_II
HSTL18_III
HSTL18D_I
HSTL18D_II
HSTL18D_III
LVPECL 3.3
0.05
0.06
0.07
HSTL_18 class I
HSTL_18 class II
HSTL_18 class III
Differential HSTL 18 class I
Differential HSTL 18 class II
Differential HSTL 18 class III
-0.25
-0.09
0.00
-0.30
-0.11
0.01
-0.35
-0.13
0.01
-0.25
-0.09
0.00
-0.30
-0.11
0.01
-0.35
-0.13
0.01
3-20
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC Family Timing Adders1, 2, 3 (Continued)
Over Recommended Operating Conditions
Buffer Type
HSTL15_I
Description
HSTL_15 class I
-5
-4
-3
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-0.07
0.00
-0.05
-0.07
-0.05
-0.20
0.25
-0.20
0.25
-0.10
0.10
-0.10
0.10
-0.14
-0.14
-0.06
-0.05
-0.06
-0.05
-0.07
-0.06
-0.05
-0.06
-0.05
-0.07
0.04
0.03
0.00
0.03
-0.05
0.07
0.07
0.06
0.07
0.12
0.11
0.22
0.21
0.22
2.00
-0.08
0.00
-0.06
-0.08
-0.06
-0.24
0.30
-0.24
0.30
-0.11
0.12
-0.11
0.12
-0.17
-0.17
-0.07
-0.07
-0.07
-0.07
-0.09
-0.07
-0.07
-0.07
-0.07
-0.09
0.05
0.03
0.00
0.03
-0.06
0.08
0.08
0.07
0.08
0.14
0.13
0.26
0.25
0.26
2.40
-0.09
0.00
-0.07
-0.09
-0.07
-0.28
0.35
-0.28
0.35
-0.13
0.14
-0.13
0.14
-0.20
-0.20
-0.09
-0.08
-0.08
-0.08
-0.10
-0.09
-0.08
-0.08
-0.08
-0.10
0.05
0.04
0.00
0.04
-0.07
0.10
0.09
0.09
0.09
0.16
0.15
0.31
0.29
0.31
2.80
HSTL15_II
HSTL_15 class II
HSTL15_III
HSTL_15 class III
HSTL15D_I
Differential HSTL 15 class I
Differential HSTL 15 class III
SSTL_3 class I
HSTL15D_III
SSTL33_I
SSTL33_II
SSTL_3 class II
SSTL33D_I
Differential SSTL_3 class I
Differential SSTL_3 class II
SSTL_2 class I
SSTL33D_II
SSTL25_I
SSTL25_II
SSTL_2 class II
SSTL25D_I
Differential SSTL_2 class I
Differential SSTL_2 class II
SSTL_1.8 class I
SSTL25D_II
SSTL18_I
SSTL18D_I
Differential SSTL_1.8 class I
LVTTL 4mA drive
LVTTL33_4mA
LVTTL33_8mA
LVTTL33_12mA
LVTTL33_16mA
LVTTL33_20mA
LVCMOS33_4mA
LVCMOS33_8mA
LVCMOS33_12mA
LVCMOS33_16mA
LVCMOS33_20mA
LVCMOS25_4mA
LVCMOS25_8mA
LVCMOS25_12mA
LVCMOS25_16mA
LVCMOS25_20mA
LVCMOS18_4mA
LVCMOS18_8mA
LVCMOS18_12mA
LVCMOS18_16mA
LVCMOS15_4mA
LVCMOS15_8mA
LVCMOS12_2mA
LVCMOS12_6mA
LVCMOS12_4mA
PCI33
LVTTL 8mA drive
LVTTL 12mA drive
LVTTL 16mA drive
LVTTL 20mA drive
LVCMOS 3.3 4mA drive
LVCMOS 3.3 8mA drive
LVCMOS 3.3 12mA drive
LVCMOS 3.3 16mA drive
LVCMOS 3.3 20mA drive
LVCMOS 2.5 4mA drive
LVCMOS 2.5 8mA drive
LVCMOS 2.5 12mA drive
LVCMOS 2.5 16mA drive
LVCMOS 2.5 20mA drive
LVCMOS 1.8 4mA drive
LVCMOS 1.8 8mA drive
LVCMOS 1.8 12mA drive
LVCMOS 1.8 16mA drive
LVCMOS 1.5 4mA drive
LVCMOS 1.5 8mA drive
LVCMOS 1.2 2mA drive
LVCMOS 1.2 6mA drive
LVCMOS 1.2 4mA drive
PCI33
1. Timing adders are characterized but not tested on every device.
2. LVCMOS timing measured with the load specified in Switching Test Conditions table.
3. All other standards according to the appropriate specification.
Rev F 0.17
3-21
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Parameter
Descriptions
Conditions
Min.
25
Typ.
—
Max.
420
420
210
840
—
Units
MHz
MHz
MHz
MHz
MHz
f
f
f
f
f
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
IN
25
—
OUT
OUT2
VCO
PFD
0.195
420
25
—
—
Phase Detector Input Frequency
—
AC Characteristics
t
t
Output Clock Duty Cycle
Default duty cycle elected3
45
—
50
—
—
—
—
—
—
250
—
—
—
—
—
55
TBD
+/- 125
0.02
+/- 200
—
%
UI
DT
PH
4
Output Phase Accuracy
Fout >= 100MHz
Fout < 100MHz
—
ps
1
t
Output Clock Period Jitter
OPJIT
—
UIPP
ps
t
t
t
t
t
t
t
t
t
Input Clock to Output Clock skew
Output Clock Pulse Width
PLL Lock-in Time
Divider ratio = integer
At 90% or 10%3
—
SK
1
ns
W
2
—
150
us
LOCK
Programmable Delay Unit
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width
100
—
400
ps
PA
+/- 200
10
ps
IPJIT
—
ns
FBKDLY
HI
90% to 90%
10% to 10%
0.5
0.5
10
—
ns
—
ns
LO
—
ns
RST
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.
2. Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
3. Using LVDS output buffers.
4. Relative to CLKOP.
Rev F 0.17
3-22
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC sysCONFIG Port Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min
Max
Units
sysCONFIG Byte Data Flow
t
t
t
t
t
t
t
t
t
Byte D[0:7] Setup Time to CCLK
7
1
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
SUCBDI
HCBDI
CODO
SUCS
HCS
Byte D[0:7] Hold Time to CCLK
Clock to Dout in Flowthrough Mode
CS[0:1] Setup Time to CCLK
CS[0:1] Hold Time to CCLK
Write Signal Setup Time to CCLK
Write Signal Hold Time to CCLK
CCLK to BUSY Delay Time
—
7
TBD
—
1
—
7
—
SUWD
HWD
1
—
—
—
12
12
DCB
Clock to out for read Data
CORD
sysCONFIG Byte Slave Clocking
t
t
t
Byte Slave Clock Minimum High Pulse
Byte Slave Clock Minimum Low Pulse
Byte Slave Clock Cycle Time
6
6
—
—
—
ns
ns
ns
BSCH
BSCL
15
BSCYC
sysCONFIG Serial (Bit) Data Flow
t
t
t
t
t
Din Setup Time to CCLK Slave Mode
Din Hold Time to CCLK Slave Mode
Clock to Dout in Flowthrough Mode
Din Setup Time to CCLK Master Mode
Din Hold Time to CCLK Master Mode
7
1
—
—
12
—
—
ns
ns
ns
ns
ns
SUSCDI
HSCDI
CODO
—
7
SUMCDI
HMCDI
1
sysCONFIG Serial Slave Clocking
t
t
Serial Slave Clock Minimum High Pulse
Serial Slave Clock Minimum Low Pulse
6
6
—
—
ns
ns
SSCH
SSCL
sysCONFIG POR, Initialization and Wake Up
t
t
t
t
t
t
t
t
t
t
Minimum Vcc to INIT High
Time from t to valid Master Clock
—
—
50
2
ms
us
ICFG
VMC
ICFG
PROGRAMB Pin Pulse Rejection
—
10
—
1
ns
PRGMRJ
PRGM
PROGRAMB Low Time to Start Configuration
PROGRAMB High to INIT High Delay
25
—
ns
ms
ns
DINIT
Delay Time from PROGRAMB Low to INIT Low
Delay Time from PROGRAMB Low to DONE Low
User I/O Disable from PROGRAMB Low
—
37
37
25
25
—
DPPINIT
DPPDONE
IODISS
IOENSS
MWC
—
ns
—
ns
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
Additional Wake Master Clock Signals after Done Pin High
—
ns
120
cycles
sysCONFIG SPI Port
t
t
t
t
t
t
f
Init High to CCLK Low
—
1
µs
us
CFGX
Init High to CSSPIN Low
—
2
CSSPI
CSCCLK
SOCDO
SOE
CCLK Low before CSSPIN Low
CCLK Low to Output Valid
CSSPIN Active Setup Time
CSSPIN Low to First Clock Edge Setup Time
Max Frequency for SPI
0
—
-
15
ns
ns
300
—
ns
300+3cyc
—
600+6cyc
20
ns
CSPID
MAXSPI
MHz
3-23
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC sysCONFIG Port Timing Specifications (Continued)
Over Recommended Operating Conditions
Parameter
Description
SOSPI Data Setup Time Before CCLK
SOSPI Data Hold Time After CCLK
Min
Max
—
Units
ns
t
7
2
SUSPI
HSPI
t
—
ns
Selected
value -30% value +30%
Selected
Master Clock Frequency
Duty Cycle
MHz
%
40
60
Rev F 0.18
Figure 3-13. sysCONFIG SPI Port Sequence
Capture
CFGx
Capture
OPCODE
Clock 127
Clock 128
t
ICFG
VCC
t
PRGM
PROGRAMN
t
t
DPPDONE
DPPINT
DONE
INITN
t
DINT
t
t
CSPID
CSSPI
t
CSSPIN
CCLK
CFGX
0
1
2
3
4
5
6
7
t
CSCCLK
t
t
SOCDO
SOE
D6
SISPI/BUSY
D7/SPID0
D7
D5 D4 D3 D2 D1 D0
0
Valid Bitstream
XXX
3-24
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
JTAG Port Timing Specifications
Over Recommended Operating Conditions
Symbol
Parameter
Min.
-
Max.
Units
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK Clock Frequency
25
-
MAX
TCK [BSCAN] clock pulse width
40
20
20
8
BTCP
TCK [BSCAN] clock pulse width high
-
ns
BTCPH
BTCPL
BTS
TCK [BSCAN] clock pulse width low
-
ns
TCK [BSCAN] setup time
-
ns
TCK [BSCAN] hold time
10
50
-
-
ns
BTH
TCK [BSCAN] rise/fall time
-
mV/ns
ns
BTRF
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
BSCAN test capture register hold time
10
10
10
-
BTCO
-
ns
BTCODIS
BTCOEN
BTCRS
BTCRH
BUTCO
BTUODIS
BTUPOEN
-
ns
8
ns
25
-
-
ns
BSCAN test update register, falling edge of clock to valid output
BSCAN test update register, falling edge of clock to valid disable
BSCAN test update register, falling edge of clock to valid enable
25
25
25
ns
-
ns
-
ns
Rev F 0.17
3-25
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Switching Test Conditions
Figure 3-14 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 3-5.
Figure 3-14. Output Test Load, LVTTL and LVCMOS Standards
VT
R1
DUT
Test Point
CL*
*CL Includes Test Fixture and Probe Capacitance
Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
R
C
Timing Ref.
V
T
1
L
LVCMOS 3.3 = 1.5V
—
—
—
—
—
LVCMOS 2.5 = V
LVCMOS 1.8 = V
LVCMOS 1.5 = V
LVCMOS 1.2 = V
/2
/2
/2
/2
CCIO
CCIO
CCIO
CCIO
LVTTL and other LVCMOS settings (L -> H, H -> L)
0pF
∞
LVCMOS 2.5 I/O (Z -> H)
LVCMOS 2.5 I/O (Z -> L)
LVCMOS 2.5 I/O (H -> Z)
LVCMOS 2.5 I/O (L -> Z)
V
V
V
V
/2
/2
V
OL
CCIO
CCIO
V
OH
188Ω
0pF
- 0.15
+ 0.15
V
OL
OH
OL
V
OH
Note: Output test conditions for all other interfaces are determined by the respective standards.
3-26
LatticeECP/EC Family Data Sheet
Pinout Information
November 2004
Preliminary Data Sheet
Signal Descriptions
Signal Name
I/O
Descriptions
General Purpose
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify
Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected.
P[Edge] [Row/Column Number*]_[A/B]
I/O
Some of these user-programmable pins are shared with special function
pins. These pin when not used as special purpose pins can be programmed
as I/Os for user logic.
During configuration the user-programmable I/Os are tri-stated with an inter-
nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-
age pin), it is also tri-stated with an internal pull-up resistor enabled after
configuration.
GSRN
NC
I
Global RESET signal (active low). Any I/O pin can be GSRN.
No connect.
—
—
—
GND
Ground. Dedicated pins.
V
V
V
V
Power supply pins for core logic. Dedicated pins.
CC
Auxiliary power supply pin. It powers all the differential and referenced input
buffers. Dedicated pins.
—
—
—
—
CCAUX
CCIOx
Power supply pins for I/O bank x. Dedicated pins.
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
V
REF1_x, REF2_x
as assigned V
inputs. When not used, they may be used as I/O pins.
REF
XRES
10K ohm +/-1% resistor must be connected between this pad and ground.
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_PLL[T, C]_IN_A
[LOC][num]_PLL[T, C]_FB_A
PCLK[T, C]_[n:0]_[3:0]
I
I
I
I
Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
function number. Any pad can be configured to be output.
[LOC]DQS[num]
Test and Programming (Dedicated pins)
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during configuration.
TMS
I
I
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
TCK
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
4-1
Pinout Information_01.2
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Signal Descriptions (Cont.)
Signal Name
I/O
Descriptions
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
TDI
I
TDO
O
Output pin. Test Data out pin used to shift data out of device using 1149.1.
V
—
V
- The power supply pin for JTAG Test Access Port.
CCJ
CCJ
Configuration Pads (used during sysCONFIG)
Mode pins used to specify configuration modes values latched on rising edge
of INITN. During configuration, a pull-up is enabled. These are dedicated
pins.
CFG[2:0]
I
Open Drain pin. Indicates the FPGA is ready to be configured. During config-
uration, a pull-up is enabled. It is a dedicated pin.
INITN
I/O
I
Initiates configuration sequence when asserted low. This pin always has an
active pull-up. This is a dedicated pin.
PROGRAMN
DONE
Open Drain pin. Indicates that the configuration sequence is complete, and
the startup sequence is in progress. This is a dedicated pin.
I/O
CCLK
I/O Configuration Clock for configuring an FPGA in sysCONFIG mode.
BUSY/SISPI
I/O Read control command in SPI3 or SPIX mode.
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
CSN
I
sysCONFIG chip select (Active low). During configuration, a pull-up is
enabled.
CS1N
I
WRITEN
I
Write Data on Parallel port (Active low).
D[7:0]/SPID[0:7]
I/O sysCONFIG Port Data I/O.
Output for serial configuration data (rising edge of CCLK) when using
sysCONFIG port.
DOUT/CSON
DI/CSSPIN
O
Input for serial configuration data (clocked with CCLK) when using sysCON-
FIG port. During configuration, a pull-up is enabled.
I
4-2
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin
PICs Associated
with DQS Strobe
DDR Strobe (DQS) and
Data (DQ) Pins
PIO Within PIC
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DQ
DQ
P[Edge] [n-4]
DQ
P[Edge] [n-3]
P[Edge] [n-2]
P[Edge] [n-1]
P[Edge] [n]
DQ
DQ
DQ
DQ
DQ
[Edge]DQSn
DQ
DQ
P[Edge] [n+1]
P[Edge] [n+2]
P[Edge] [n+3]
DQ
DQ
DQ
DQ
DQ
Notes:
1. “n” is a Row/Column PIC number
2. The DDR interface is designed for memories that support one DQS strobe per eight bits of
data. In some packages, all the potential DDR data (DQ) pins may not be available.
3. PIC numbering definitions are provided in the “Signal Names” column of the Signal Descrip-
tions table.
4-3
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Pin Information Summary
LFECP6/EC6
LFECP20/EC20
Pin Type
Single Ended User I/O
Differential Pair User I/O
144-TQFP
208-PQFP
256-fpBGA 484-fpBGA 484-fpBGA 672-fpBGA
97
72
13
48
5
147
97
13
48
5
195
97
13
48
5
224
112
13
48
5
360
180
13
56
5
400
200
13
56
5
Dedicated
Muxed
Configuration
TAP
Dedicated (total without supplies)
110
4
160
4
208
10
2
373
20
12
4
373
20
12
4
509
32
20
6
V
V
CC
2
4
CCAUX
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
2
3
2
2
2
2
4
4
6
1
2
2
4
4
6
2
2
2
4
4
6
V
CCIO
2
2
2
4
4
6
2
3
2
4
4
6
2
2
2
4
4
6
1
2
2
4
4
6
GND, GND0-GND7
NC
14
0
18
4
20
0
44
139
32
32
16
32
32
32
32
16
1
44
3
63
96
64
48
40
48
48
64
48
40
1
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
14
13
8
26
17
14
16
17
26
16
15
1
32
18
16
32
17
32
32
16
1
48
48
40
44
48
48
44
40
1
Single Ended/
Differential I/O
per Bank
13
14
13
14
8
V
1
CCJ
Note: During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not
bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
4-4
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Power Supply and NC Connections
Signals
144 TQFP
11, 13, 92, 99
208 PQFP
256 fpBGA
VCC
24, 26, 128, 135
E12, E5, E8, M12, M5, M9,
F6, F11, L11, L6
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCJ
136, 143
110, 125
108
187, 197, 208
157, 176
145, 155
106, 120
85, 104
F7, F8
F9, F10
G11, H11
J11, K11
L9, L10
L7, L8
73, 84
55, 71
38, 44
24, 36
1
53, 64, 74
37, 51
J6, K6
2, 13
G6, H6
L4
19
32
VCCAUX
54, 126
22, 84, 136, 177
B15, R2
GND, GND0-GND7
12, 15, 28, 37, 52, 63, 72, 80, 1, 18, 25, 28, 41, 52, 72, 82, A1, A16, G10, G7, G8, G9,
96, 98, 109, 117, 128, 144
-
93, 105, 116, 132, 134, 138, H10, H7, H8, H9, J10, J7, J8,
156, 168, 179, 189
J9, K10, K7, K8, K9, T1, T16
NC
-
-
4-5
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Power Supply and NC Connections
Signals
484 fpBGA
672 fpBGA
VCC
J6, J7, J16, J17, K6, K7, K16, K17, L6, H8, H9, H10, H11, H16, H17, H18, H19,
L17, M6, M17, N6, N7, N16, N17, P6, P7, J9, J18, K8, K19, L8, L19, M19, N7, R7,
P16, P17
R20, T19, U8, U19, V8, V18, V9, W8, W9,
W10, W11, W16, W17, W18, W19
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCJ
G11, H9, H10, H11
G12, H12, H13, H14
J15, K15, L15, L16
M15, M16, N15, P15
R12, R13, R14, T12
R9, R10, R11, T11
M7, M8, N8, P8
J8, K8, L7, L8
H12, H13, J10, J11, J12, J13
H14, H15, J14, J15, J16, J17
K17, K18, L18, M18, N18, N19
P18, P19, R18, R19, T8, U18
V14, V15, V16, V17, W14, W15
V10, V11, V12, V13, W12, W13
P8, P9, R8, R9, T9, U9
K9, L9, M8, M9, N8, N9
U6
U2
VCCAUX
G7, G8, G15, G16, H7, H16, R7, R16,
T7, T8, T15, T16
G13, H7, H20, J8, J19, K7, L20, M7,
M20, N20, P7, P20, T7, T8, T20, V7, V19,
W20, Y7, Y13
GND, GND0-GND7
A1, A22, AB1, AB22, H8, H15, J9, J10, K10, K11, K12, K13, K14, K15, K16, L10,
J11, J12, J13, J14, K9, K10, K11, K12, L11, L12, L13, L14, L15, L16, L17, M10,
K13, K14, L9, L10, L11, L12, L13, L14, M11, M12, M13, M14, M15, M16, M17,
M9, M10, M11, M12, M13, M14, N9, N10, N10, N11, N12, N13, N14, N15, N16,
N11, N12, N13, N14, P9, P10, P11, P12, N17, P10, P11, P12, P13, P14, P15,
P13, P14, R8, R15
P16, P17, R10, R11, R12, R13, R14,
R15, R16, R17, T10, T11, T12, T13, T14,
T15, T16, T17, U10, U11, U12, U13, U14,
U15, U16, U17
NC
ECP6/EC6: C3, B2, E5, F5, D3, C2, F4, A25, B2, B23, B24, B25, B26, C2, C3,
G4, E3, D2, B1, C1, F3, E2, G5, H6, G3, C19, C20, C21, C22, C23, C24, D3, D5,
H4, J5, H5, F2, F1, E1, D1, R6, P5, P3, D20, D21, D22, D24, E5, E19, E21, E22,
P4, R1, R2, R5, R4, T1, T2, R3, T3, A2, E24, E25, E26, F4, F5, F20, F22, F23,
AB2, A21
F24, F26, G5, G20, G26, H2, H3, H5, H6,
H22, J2, J3, J7, J21, J22, J23, W5, W7,
Y5, Y6, Y19, Y20, Y21, Y22, Y23, Y24,
AA2, AA3, AA4, AA5, AA21, AA22,
AA23, AA24, AB3, AB5, AB19, AB20,
AB21, AB22, AB23, AB24, AC2, AC3,
AC19, AC20, AC21, AC22, AD1, AD2,
AD3, AD19, AD20, AD21, AD22, AD23,
AD24, AD25, AD26, AE1, AE24, AE25,
AE26, AF25
ECP/EC20: A2, AB2, A21
4-6
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 144 TQFP
Pin Number
Pin Function
VCCIO7
PL2A
Bank
7
7
7
7
7
7
7
7
7
6
-
LVDS
Dual Function
1
2
T
C
T
VREF2_7
VREF1_7
3
PL2B
4
PL7A
5
PL7B
C
T
6
PL8A
7
PL8B
C
T
8
PL9A
PCLKT7_0
PCLKC7_0
9
PL9B
C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37*
38
39
40
41
42
43
XRES
VCC
GND
-
VCC
-
TCK
6
-
GND
TDI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TMS
TDO
VCCJ
PL20A
PL20B
PL21A
PL21B
VCCIO6
PL22A
PL22B
PL23A
GND6
PL23B
PL24A
PL24B
PL25A
PL25B
PL27A
PL27B
VCCIO6
GND5, GND6
VCCIO5
PB10A
PB10B
PB11A
PB11B
PB13B
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
C
T
C
T
C
T
LDQS24
C
T
C
T
VREF1_6
VREF2_6
C
5
5
5
5
5
5
T
C
T
C
4-7
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 144 TQFP (Cont.)
Pin Number
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72*
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Pin Function
VCCIO5
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
Bank
LVDS
Dual Function
5
5
T
C
T
C
T
C
T
BDQS14
5
5
5
5
VREF2_5
VREF1_5
PCLKT5_0
5
5
5
PB17B
VCCAUX
VCCIO4
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
5
C
PCLKC5_0
-
4
4
T
C
T
C
T
C
T
WRITEN
CS1N
4
4
VREF1_4
CSN
4
4
VREF2_4
D0/SPID7
D2/SPID5
4
4
4
PB21B
PB22A
PB22B
PB23A
PB23B
PB24B
PB25B
VCCIO4
GND3, GND4
VCCIO3
PR27A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
4
C
T
D1/SPID6
BDQS22
D3/SPID4
4
4
C
T
4
4
C
D4/SPID3
D5/SPID2
D6/SPID1
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
VREF1_3
C
T
C
T
RDQS24
C
RLM0_PLLC_FB_A
PR23A
PR22B
PR22A
VCCIO3
PR21B
PR21A
PR20B
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
C
4-8
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 144 TQFP (Cont.)
Pin Number
Pin Function
PR20A
CFG2
Bank
LVDS
Dual Function
88
3
3
3
3
-
T
D7/SPID0
89
90
CFG1
91
CFG0
92
VCC
93
PROGRAMN
CCLK
3
3
3
-
94
95
INITN
96
GND
97
DONE
GND
3
-
98
99
VCC
-
100
101
102
103
104
105
106
107
108
109*
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
PR9B
2
2
2
2
2
2
2
2
2
C
T
C
T
C
T
C
T
PCLKC2_0
PCLKT2_0
PR9A
PR8B
PR8A
PR7B
PR7A
PR2B
VREF1_2
VREF2_2
PR2A
VCCIO2
GND1, GND2
VCCIO1
PT25B
PT25A
PT23A
PT22B
PT22A
PT21B
GND1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
-
C
T
C
T
TDQS22
C
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
VCCIO1
VCCAUX
PT17B
GND0
T
C
T
C
T
C
T
VREF2_1
VREF1_1
0
0
0
0
0
C
PCLKC0_0
PT17A
PT16B
PT16A
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
4-9
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 144 TQFP (Cont.)
Pin Number
Pin Function
Bank
LVDS
Dual Function
132
PT15B
0
0
0
0
0
0
0
0
0
0
0
0
C
T
C
T
133
PT15A
134
PT14B
135
PT14A
TDQS14
136
VCCIO0
PT13B
137
C
T
C
T
C
T
138
PT13A
139
PT12B
140
PT12A
141
PT10B
142
PT10A
143
144*
VCCIO0
GND0, GND7
* Double bonded to the pin.
4-10
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 208 PQFP
Pin Number
Pin Function
GND0, GND7
VCCIO7
PL2A
Bank
LVDS
Dual Function
1*
2
7
7
7
-
3
T
VREF2_7
VREF1_7
4
PL2B
C
5
NC
6
NC
-
7
PL3B
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
8
PL4A
T
C
T
C
T
9
PL4B
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
PL5A
PL5B
PL6A
LDQS6
VCCIO7
PL6B
C
T
C
T
PL7A
PL7B
PL8A
GND7
PL8B
C
T
PL9A
PCLKT7_0
PCLKC7_0
PL9B
C
VCCAUX
XRES
VCC
6
-
GND
-
VCC
-
TCK
6
-
GND
TDI
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
TMS
TDO
VCCJ
PL20A
PL20B
PL21A
PL21B
VCCIO6
PL22A
PL22B
PL23A
GND6
PL23B
PL24A
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
C
T
C
T
C
T
LDQS24
4-11
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 208 PQFP (Cont.)
Pin Number
44
45
46
47
48
49
50
51
52*
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
Pin Function
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
PL27B
VCCIO6
GND5, GND6
VCCIO5
PB2A
Bank
LVDS
Dual Function
6
6
6
6
6
6
6
6
C
T
C
T
C
T
VREF1_6
VREF2_6
C
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
T
C
T
PB2B
PB3A
PB3B
C
T
PB4A
PB4B
C
T
PB5A
PB5B
C
T
PB6A
BDQS6
PB6B
C
VCCIO5
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
T
C
T
C
T
C
T
PB13B
VCCIO5
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
C
T
C
T
C
T
C
T
BDQS14
VREF2_5
VREF1_5
PCLKT5_0
PB17B
VCCAUX
VCCIO4
PB18A
PB18B
C
PCLKC5_0
4
4
4
T
WRITEN
CS1N
C
4-12
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 208 PQFP (Cont.)
Pin Number
Pin Function
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
Bank
LVDS
Dual Function
VREF1_4
CSN
88
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
T
C
T
C
T
89
90
VREF2_4
D0/SPID7
D2/SPID5
91
92
93
94
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB25B
PB33A
VCCIO4
GND3, GND4
VCCIO3
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
C
T
D1/SPID6
BDQS22
D3/SPID4
95
96
C
T
97
98
C
T
D4/SPID3
D5/SPID2
D6/SPID1
99
100
101
102
103
104
105*
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
C
T
C
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
C
T
VREF2_3
VREF1_3
C
T
C
T
C
T
RDQS24
C
RLM0_PLLC_FB_A
PR23A
PR22B
PR22A
VCCIO3
PR21B
PR21A
PR20B
PR20A
CFG2
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
C
T
C
T
DI/CSSPIN
DOUT/CSON
BUSY/SISPI
D7/SPID0
CFG1
CFG0
VCC
PROGRAMN
CCLK
3
3
3
INITN
4-13
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 208 PQFP (Cont.)
Pin Number
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156*
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
Pin Function
Bank
LVDS
Dual Function
GND
-
DONE
GND
3
-
VCC
-
VCCAUX
PR9B
-
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
C
PCLKC2_0
PCLKT2_0
GND2
PR9A
T
C
T
PR8B
PR8A
PR7B
C
T
PR7A
PR6B
C
VCCIO2
PR6A
T
C
T
C
T
RDQS6
PR5B
PR5A
PR4B
PR4A
NC
NC
-
PR2B
2
2
2
C
T
VREF1_2
VREF2_2
PR2A
VCCIO2
GND1, GND2
VCCIO1
PT33A
PT25B
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND1
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
T
C
T
C
T
C
T
TDQS22
C
T
C
T
C
T
C
T
VREF2_1
VREF1_1
4-14
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 208 PQFP (Cont.)
Pin Number
Pin Function
VCCIO1
VCCAUX
PT17B
GND0
Bank
1
-
LVDS
Dual Function
176
177
178
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
PCLKC0_0
179
180
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
VCCIO0
PT13B
GND0
T
C
T
C
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
181
182
183
184
185
186
TDQS14
187
188
C
189
190
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
VCCIO0
PT6B
T
C
T
C
T
C
T
191
192
193
194
195
196
197
198
C
T
C
T
C
T
C
T
C
T
199
PT6A
TDQS6
200
PT5B
201
PT5A
202
PT4B
203
PT4A
204
PT3B
205
PT3A
206
PT2B
207
208
PT2A
VCCIO0
* Double bonded to the pin.
4-15
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA
Ball Number
GND
D4
Ball Function
GND7
PL2A
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
LVDS
Dual Function
T
C
T
C
T
C
T
C
T
C
T
C
T
VREF2_7
VREF1_7
D3
PL2B
C3
PL3A
C2
PL3B
B1
PL4A
C1
PL4B
E3
PL5A
E4
PL5B
F4
PL6A
LDQS6
F5
PL6B
G4
G3
D2
PL7A
PL7B
PL8A
GND
D1
GND7
PL8B
C
T
E1
PL9A
PCLKT7_0
PCLKC7_0
E2
PL9B
C
F3
XRES
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
GND6
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND6
PL18B
TCK
G5
H5
T
C
T
C
T
C
T
F2
F1
H4
H3
G2
GND
G1
J4
C
T
C
T
C
T
C
T
LDQS15
J3
J5
K5
H2
H1
J2
GND
J1
C
K4
K3
TDI
L3
TMS
L5
TDO
L4
VCCJ
PL20A
K2
T
LLM0_PLLT_IN_A
4-16
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.)
Ball Number
Ball Function
PL20B
PL21A
PL21B
PL22A
PL22B
PL23A
GND6
PL23B
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
PL27B
GND6
GND5
PB2A
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
LVDS
Dual Function
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
K1
C
T
C
T
C
T
L2
L1
M2
M1
N1
GND
N2
C
T
M4
M3
P1
LDQS24
C
T
R1
C
T
P2
P3
C
T
N3
VREF1_6
VREF2_6
N4
C
GND
GND
P4
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
N5
PB2B
P5
PB3A
P6
PB3B
R4
PB4A
R3
PB4B
T2
PB5A
T3
PB5B
R5
PB6A
BDQS6
R6
PB6B
T4
PB7A
T5
PB7B
N6
PB8A
M6
T6
PB8B
PB9A
GND
T7
GND5
PB9B
C
T
C
T
C
T
C
T
P7
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
N7
R7
R8
M7
M8
T8
GND
T9
C
4-17
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.)
Ball Number
Ball Function
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
Bank
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
LVDS
Dual Function
P8
T
C
T
C
T
C
T
BDQS14
N8
R9
R10
P9
VREF2_5
VREF1_5
PCLKT5_0
N9
T10
GND
T11
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
T12
T13
P10
N10
T14
VREF1_4
CSN
VREF2_4
D0/SPID7
D2/SPID5
T15
M10
GND
M11
R11
P11
R13
R14
P12
P13
N11
GND
N12
R12
GND
GND
GND
N13
N14
P14
P15
R15
R16
M13
M14
P16
GND
N16
N15
M15
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS22
D3/SPID4
D4/SPID3
D5/SPID2
PB25B
PB26A
GND4
C
D6/SPID1
GND4
GND3
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
C
T
VREF2_3
VREF1_3
C
T
C
T
C
T
RDQS24
C
RLM0_PLLC_FB_A
PR23A
PR22B
PR22A
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
4-18
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.)
Ball Number
M16
L16
Ball Function
PR21B
PR21A
PR20B
PR20A
CFG2
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
LVDS
Dual Function
DI/CSSPIN
C
T
C
T
DOUT/CSON
BUSY/SISPI
D7/SPID0
K16
J16
L12
L14
CFG1
L13
CFG0
K13
L15
PROGRAMN
CCLK
K15
K14
H16
GND
H15
G16
G15
K12
J12
INITN
DONE
PR18B
GND3
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND3
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
C
T
C
T
C
T
J14
C
T
J15
RDQS15
F16
GND
F15
J13
C
T
C
T
H13
H14
G14
E16
E15
H12
GND
G12
G13
F13
F12
E13
D16
D15
F14
E14
C16
B16
C15
C14
C
T
C
T
C
PCLKC2_0
PCLKT2_0
GND2
PR9A
T
C
T
C
T
C
T
C
T
C
T
C
T
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
RDQS6
PR5B
PR5A
PR4B
PR4A
PR3B
PR3A
4-19
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.)
Ball Number
D14
D13
GND
GND
GND
B13
C13
GND
C12
D12
A15
B14
D11
C11
E10
E11
A14
GND
A13
D10
C10
A12
B12
A11
B11
A10
GND
B10
C9
Ball Function
Bank
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LVDS
Dual Function
VREF1_2
PR2B
C
T
PR2A
VREF2_2
GND2
GND1
GND1
PT26B
PT26A
GND1
PT25B
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND1
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
PT9B
C
T
C
T
C
T
C
T
C
T
TDQS22
C
T
C
T
C
T
VREF2_1
VREF1_1
C
T
C
PCLKC0_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
B9
E9
C
T
D9
D8
C
T
C8
TDQS14
A9
C
GND
A8
T
C
T
B8
B7
D7
C
T
C7
A7
C
T
A6
E7
C
4-20
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.)
Ball Number
GND
E6
Ball Function
GND0
PT9A
PT8B
PT8A
PT7B
PT7A
PT6B
PT6A
PT5B
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
PT2A
GND0
GND
Bank
LVDS
Dual Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
D6
C6
B6
B5
A5
A4
TDQS6
A3
A2
B2
B3
D5
C5
C4
B4
GND
A1
A16
G10
G7
GND
-
GND
-
GND
-
G8
GND
-
G9
GND
-
H10
H7
GND
-
GND
-
H8
GND
-
H9
GND
-
J10
J7
GND
-
GND
-
J8
GND
-
J9
GND
-
K10
K7
GND
-
GND
-
K8
GND
-
K9
GND
-
T1
GND
-
T16
E12
E5
GND
-
VCC
-
VCC
-
E8
VCC
-
M12
M5
M9
B15
VCC
-
VCC
-
VCC
-
VCCAUX
-
4-21
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6 Logic Signal Connections: 256 fpBGA (Cont.)
Ball Number
Ball Function
VCCAUX
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCC
Bank
LVDS
Dual Function
R2
-
F7
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
-
F8
F10
F9
G11
H11
J11
K11
L10
L9
L7
L8
J6
K6
G6
H6
F6
F11
L11
L6
VCC
-
VCC
-
VCC
-
4-22
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
GND
D4
E4
C3
B2
E5
F5
D3
C2
F4
G4
E3
D2
B1
C1
F3
-
GND7
PL2A
PL2B
NC
7
7
7
-
GND
D4
E4
C3
B2
E5
F5
GND7
PL2A
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
T
VREF2_7
VREF1_7
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
VREF2_7
VREF1_7
C
PL2B
PL3A
NC
-
PL3B
NC
-
PL4A
NC
-
PL4B
NC
-
D3
C2
F4
PL5A
NC
-
PL5B
NC
-
PL6A
LDQS6
NC
-
G4
E3
D2
B1
C1
F3
PL6B
NC
-
PL7A
NC
-
PL7B
NC
-
PL8A
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
NC
-
PL8B
NC
-
PL9A
-
-
GND
E2
G5
H6
G3
H4
J5
GND7
PL9B
E2
G5
H6
G3
H4
J5
NC
-
C
T
C
T
C
T
C
T
LUM0_PLLC_FB_A
NC
-
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
GND7
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND7
PL18B
PL19A
PL19B
PL20A
PL20B
PL21A
PL21B
NC
-
NC
-
NC
-
NC
-
H5
F2
-
NC
-
H5
F2
NC
-
-
-
GND
F1
F1
E1
D1
H3
G2
H2
G1
J4
NC
-
C
T
C
T
C
T
C
T
NC
-
E1
D1
H3
G2
H2
G1
J4
NC
-
PL3A
PL3B
PL4A
PL4B
PL5A
-
7
7
7
7
7
-
T
C
T
C
T
-
GND
J3
J3
PL5B
PL6A
PL6B
PL7A
PL7B
PL8A
PL8B
7
7
7
7
7
7
7
C
T
C
T
J2
LDQS6
J2
LDQS19
H1
K4
K5
K3
K2
C
T
H1
K4
K5
K3
K2
C
T
C
T
C
T
C
C
4-23
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
J1
GND
K1
L3
PL9A
GND7
PL9B
XRES
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
GND6
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND6
PL18B
NC
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
T
PCLKT7_0
J1
GND
K1
PL22A
GND7
PL22B
XRES
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
GND6
PL27B
PL28A
PL28B
PL29A
PL29B
PL30A
PL30B
PL31A
GND6
PL31B
PL32A
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
GND6
PL35B
PL36A
PL36B
PL37A
PL37B
PL38A
PL38B
PL39A
GND6
PL39B
TCK
7
7
7
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
T
PCLKT7_0
C
PCLKC7_0
C
PCLKC7_0
L3
L4
T
C
T
C
T
C
T
L4
T
C
T
C
T
C
T
L5
L5
L2
L2
L1
L1
M4
M5
M1
GND
M2
N3
M3
N5
N4
N1
N2
P1
GND
P2
R6
P5
P3
P4
R1
R2
R5
-
M4
M5
M1
GND
M2
N3
M3
N5
N4
N1
N2
P1
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
LDQS15
LDQS28
GND
P2
C
C
T
C
T
C
T
C
T
R6
P5
NC
-
NC
-
P3
NC
-
P4
NC
-
R1
R2
R5
GND
R4
T1
NC
-
NC
-
-
-
R4
T1
NC
-
C
T
C
T
C
T
C
T
NC
-
LDQS36
T2
NC
-
T2
R3
T3
NC
-
R3
T3
NC
-
-
-
-
GND
C
T5
U5
TCK
TDI
6
6
T5
U5
TDI
4-24
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
T4
U1
TMS
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
T4
U1
TMS
TDO
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
TDO
U2
VCCJ
U2
VCCJ
PL41A
PL41B
PL42A
PL42B
PL43A
PL43B
PL44A
GND6
PL44B
PL45A
PL45B
PL46A
PL46B
PL47A
PL47B
PL48A
PL48B
GND6
GND5
PB2A
PB2B
PB3A
PB3B
PB4A
PB4B
PB5A
PB5B
PB6A
PB6B
PB7A
PB7B
PB8A
PB8B
PB9A
GND5
PB9B
PB10A
PB10B
PB11A
V1
PL20A
PL20B
PL21A
PL21B
PL22A
PL22B
PL23A
GND6
PL23B
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
PL27B
GND6
GND5
T
C
T
C
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
V1
T
C
T
C
T
C
T
LLM0_PLLT_IN_A
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
V2
V2
U3
U3
V3
V3
U4
U4
V5
V5
W1
GND
W2
Y1
W1
GND
W2
Y1
C
T
C
T
LDQS24
LDQS45
Y2
C
T
Y2
C
T
AA1
AA2
W4
V4
AA1
AA2
W4
V4
C
T
C
T
C
T
C
T
W3
Y3
VREF1_6
VREF2_6
W3
Y3
VREF1_6
VREF2_6
C
C
GND
GND
GND
GND
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
-
-
-
GND
C
T
C
T
V7
T6
V8
NC
NC
NC
-
-
-
V7
T6
V8
4-25
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
U7
W5
U6
NC
NC
-
-
U7
W5
PB11B
PB12A
PB12B
PB13A
GND5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
C
T
C
T
NC
-
U6
AA3
-
NC
-
AA3
GND
AB3
Y6
-
-
AB3
Y6
NC
-
PB13B
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
C
T
C
T
C
T
C
T
NC
-
BDQS14
V6
NC
-
V6
AA5
W6
Y5
NC
-
AA5
W6
NC
-
NC
-
Y5
Y4
NC
-
Y4
AA4
-
NC
-
AA4
GND
AB4
Y7
-
-
AB4
Y7
NC
-
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND5
C
T
C
T
C
T
C
T
PB2A
PB2B
PB3A
PB3B
PB4A
PB4B
PB5A
-
5
5
5
5
5
5
5
-
T
C
T
C
T
C
T
W8
W7
U8
W8
W7
U8
W9
U9
W9
U9
Y8
Y8
-
GND
Y9
Y9
PB5B
PB6A
PB6B
PB7A
PB7B
PB8A
PB8B
PB9A
GND5
PB9B
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND5
PB13B
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
C
T
C
T
C
T
C
T
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND5
C
T
C
T
C
T
C
T
V9
BDQS6
V9
BDQS22
T9
T9
W10
U10
V10
T10
AA6
GND
AB5
AA8
AA7
AB6
AB7
Y10
W11
AB8
GND
AB9
W10
U10
V10
T10
AA6
GND
AB5
AA8
AA7
AB6
AB7
Y10
W11
AB8
GND
AB9
C
T
C
T
C
T
C
T
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND5
C
T
C
T
C
T
C
T
C
PB29B
C
4-26
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
AA10
AA9
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
T
C
T
C
T
C
T
BDQS14
AA10
AA9
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GND5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
T
C
T
C
T
C
T
BDQS30
Y11
Y11
AA11
V11
AA11
V11
VREF2_5
VREF1_5
PCLKT5_0
VREF2_5
VREF1_5
PCLKT5_0
V12
V12
AB10
GND
AB11
Y12
AB10
GND
AB11
Y12
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND4
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GND4
C
T
C
T
C
T
C
T
PCLKC5_0
WRITEN
CS1N
U11
U11
W12
U12
VREF1_4
CSN
W12
U12
VREF1_4
CSN
W13
U13
VREF2_4
D0/SPID7
D2/SPID5
W13
U13
VREF2_4
D0/SPID7
D2/SPID5
AA12
GND
AB12
T13
AA12
GND
AB12
T13
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS22
D3/SPID4
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
GND4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS38
D3/SPID4
V13
V13
W14
U14
W14
U14
D4/SPID3
D5/SPID2
D4/SPID3
D5/SPID2
Y13
Y13
V14
V14
AA13
GND
AB13
AA14
Y14
AA13
GND
AB13
AA14
Y14
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND4
C
T
C
T
C
T
C
T
D6/SPID1
PB41B
PB42A
PB42B
PB43A
PB43B
PB44A
PB44B
PB45A
GND4
C
T
C
T
C
T
C
T
D6/SPID1
Y15
Y15
W15
V15
W15
V15
T14
T14
AB14
GND
AB15
AB16
AA15
AB17
AA16
AB18
AA17
AB14
GND
AB15
AB16
AA15
AB17
AA16
AB18
AA17
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
C
T
PB45B
PB46A
PB46B
PB47A
PB47B
PB48A
PB48B
C
T
BDQS30
BDQS46
C
T
C
T
C
T
C
T
C
C
4-27
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
AB19
-
PB33A
-
4
-
T
AB19
GND
AA18
W16
U15
V16
PB49A
GND4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
T
AA18
W16
U15
V16
U16
Y17
V17
AB20
-
PB33B
NC
4
-
C
PB49B
PB50A
PB50B
PB51A
PB51B
PB52A
PB52B
PB53A
GND4
C
T
C
T
C
T
C
T
NC
-
NC
-
NC
-
U16
Y17
NC
-
NC
-
V17
NC
-
AB20
GND
AA19
Y16
-
-
AA19
Y16
W17
AA20
Y19
Y18
W18
T17
NC
-
PB53B
PB54A
PB54B
PB55A
PB55B
PB56A
PB56B
PB57A
PB57B
GND4
C
T
NC
-
BDQS54
NC
-
W17
AA20
Y19
C
T
NC
-
NC
-
C
T
NC
-
Y18
NC
-
W18
T17
C
T
NC
-
U17
GND
GND
W20
Y20
AA21
AB21
W19
V19
Y21
AA22
V20
GND
U20
W21
Y22
V21
W22
U21
V22
T19
NC
-
U17
GND
GND
W20
Y20
C
GND4
GND3
PR27B
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR23B
GND3
PR23A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
CFG2
CFG1
CFG0
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
GND3
C
T
VREF2_3
VREF1_3
PR48B
PR48A
PR47B
PR47A
PR46B
PR46A
PR45B
PR45A
PR44B
GND3
C
T
VREF2_3
VREF1_3
C
T
AA21
AB21
W19
V19
C
T
C
T
C
T
C
T
Y21
C
T
RDQS24
AA22
V20
RDQS45
C
RLM0_PLLC_FB_A
C
RLM0_PLLC_IN_A
GND
U20
W21
Y22
T
C
T
C
T
C
T
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
DI/CSSPIN
PR44A
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
CFG2
T
C
T
C
T
C
T
RLM0_PLLT_IN_A
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
DI/CSSPIN
V21
DOUT/CSON
W22
U21
V22
DOUT/CSON
BUSY/SISPI
BUSY/SISPI
D7/SPID0
D7/SPID0
T19
U19
U18
U19
U18
CFG1
CFG0
4-28
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
V18
PRO-
GRAMN
3
V18
PRO-
GRAMN
3
T20
T21
R20
CCLK
INITN
DONE
3
3
3
T20
T21
R20
CCLK
INITN
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
DONE
PR39B
GND3
C
-
-
-
GND
PR39A
PR38B
PR38A
PR37B
PR37A
PR36B
PR36A
PR35B
GND3
T
C
T
T18
R17
R19
R18
U22
-
NC
NC
-
-
T18
R17
R19
R18
U22
GND
T22
R21
R22
P20
N20
P19
P18
P21
GND
P22
N21
N22
N19
N18
M21
L20
C
T
NC
-
C
T
NC
-
RDQS36
NC
-
C
-
-
T22
R21
R22
P20
N20
P19
P18
P21
GND
P22
N21
N22
N19
N18
M21
L20
L21
GND
M20
M18
M19
M22
L22
K22
K21
J22
NC
-
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
GND3
T
C
T
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
PR18B
GND3
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
GND3
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
C
C
T
C
T
PR31A
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
GND3
T
C
T
C
T
C
T
C
T
C
T
RDQS15
RDQS28
C
L21
C
GND
M20
M18
M19
M22
L22
T
C
T
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR22B
T
C
T
C
T
C
T
C
T
K22
K21
J22
C
T
C
PCLKC2_0
C
PCLKC2_0
4-29
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
GND
J21
H22
H21
L19
L18
K20
J20
K19
-
GND2
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
PR5B
-
2
2
2
2
2
2
2
2
2
-
GND
J21
GND2
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR18B
GND2
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR14B
PR14A
GND2
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
T
C
T
PCLKT2_0
T
C
T
PCLKT2_0
H22
H21
L19
L18
K20
J20
C
T
C
T
C
T
C
T
RDQS6
RDQS19
C
K19
GND
K18
G22
F22
F21
E22
E21
D22
G21
G20
GND
J18
C
K18
G22
F22
F21
E22
E21
D22
G21
G20
-
PR5A
PR4B
PR4A
PR3B
PR3A
NC
2
2
2
2
2
-
T
C
T
C
T
T
C
T
C
T
C
T
C
T
NC
-
NC
-
NC
-
-
-
J18
H19
J19
H20
H17
H18
D21
-
NC
-
C
T
NC
-
H19
J19
NC
-
C
T
NC
-
H20
H17
H18
D21
GND
C22
G19
G18
F20
F19
E20
D20
C21
C20
F18
E18
B22
B21
E19
NC
-
C
T
NC
-
NC
-
C
RUM0_PLLC_FB_A
-
-
GND2
PR9A
C22
G19
G18
F20
F19
E20
D20
C21
C20
F18
E18
B22
B21
E19
NC
-
T
C
T
C
T
C
T
C
T
C
T
C
T
C
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
NC
-
PR8B
NC
-
PR8A
NC
-
PR7B
NC
-
PR7A
NC
-
PR6B
NC
-
PR6A
RDQS6
NC
-
PR5B
NC
-
PR5A
NC
-
PR4B
NC
-
PR4A
NC
-
PR3B
NC
-
PR3A
PR2B
2
C
VREF1_2
PR2B
VREF1_2
4-30
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
D19
GND
GND
G17
F17
D18
C18
C19
B20
D17
C16
B19
-
PR2A
GND2
GND1
NC
2
2
1
-
T
VREF2_2
D19
GND
GND
G17
F17
D18
C18
C19
B20
D17
C16
B19
GND
A20
E17
C17
F16
E16
F15
D16
B18
GND
A19
B17
A18
B16
A17
B15
A16
A15
GND
A14
G14
E15
D15
C15
C14
B14
A13
GND
B13
E14
PR2A
GND2
GND1
PT57B
PT57A
PT56B
PT56A
PT55B
PT55A
PT54B
PT54A
PT53B
GND1
PT53A
PT52B
PT52A
PT51B
PT51A
PT50B
PT50A
PT49B
GND1
PT49A
PT48B
PT48A
PT47B
PT47A
PT46B
PT46A
PT45B
GND1
PT45A
PT44B
PT44A
PT43B
PT43A
PT42B
PT42A
PT41B
GND1
PT41A
PT40B
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T
VREF2_2
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
TDQS54
NC
-
C
-
-
A20
E17
C17
F16
E16
F15
D16
B18
-
NC
-
T
C
T
NC
-
NC
-
NC
-
C
T
NC
-
NC
-
C
T
NC
-
PT33B
-
1
-
C
C
A19
B17
A18
B16
A17
B15
A16
A15
GND
A14
G14
E15
D15
C15
C14
B14
A13
GND
B13
E14
PT33A
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND1
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
PT25B
GND1
PT25A
PT24B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T
C
T
T
C
T
C
T
C
T
C
T
C
T
TDQS30
TDQS46
C
C
T
C
T
T
C
T
C
T
C
T
C
T
C
T
C
C
T
T
C
C
4-31
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
C13
F14
D14
E13
G13
A12
GND
B12
F13
D13
F12
D12
F11
C12
A11
GND
A10
E12
E11
B11
C11
B9
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND1
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND0
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
PT9B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
C
T
C13
F14
D14
E13
G13
A12
GND
B12
F13
D13
F12
D12
F11
C12
A11
GND
A10
E12
E11
B11
C11
B9
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
GND1
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
GND0
PT33A
PT32B
PT32A
PT31B
PT31A
PT30B
PT30A
PT29B
GND0
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
PT25B
GND0
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
C
T
C
T
C
T
TDQS22
TDQS38
C
C
T
C
T
T
C
T
C
T
VREF2_1
VREF1_1
C
T
VREF2_1
VREF1_1
C
T
C
T
C
PCLKC0_0
C
PCLKC0_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
C
T
C
T
C
T
C
T
B10
A9
TDQS14
B10
A9
TDQS30
C
C
GND
A8
GND
A8
T
C
T
T
C
T
D11
C10
A7
D11
C10
A7
C
T
C
T
A6
A6
B7
C
T
B7
C
T
B8
B8
A5
C
A5
C
GND
B6
GND0
PT9A
GND
B6
T
C
T
T
C
T
G10
E10
F10
D10
G9
PT8B
G10
E10
F10
D10
G9
PT8A
PT7B
C
T
C
T
PT7A
PT6B
C
T
C
T
E9
PT6A
TDQS6
E9
TDQS22
C9
PT5B
C
C9
C
4-32
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
-
C8
F9
D9
F8
D7
D8
C7
GND
A4
B4
C4
C5
D6
B5
E6
C6
A3
-
-
-
0
0
0
0
0
0
0
0
-
GND
C8
F9
GND0
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
GND0
PT17B
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND0
PT13A
PT12B
PT12A
PT11B
PT11A
PT10B
PT10A
PR9B
GND0
PT9A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
PT2A
GND0
NC
T
C
T
C
T
C
T
T
C
T
C
T
C
T
D9
F8
D7
D8
C7
GND
A4
C
T
NC
-
B4
NC
-
C4
C5
D6
B5
C
T
NC
-
NC
-
C
T
NC
-
NC
-
E6
C
T
NC
-
C6
A3
TDQS14
NC
-
C
-
-
GND
B3
B3
F6
D5
F7
E8
G6
E7
NC
-
T
C
T
C
T
C
T
NC
-
F6
NC
-
D5
F7
NC
-
NC
-
E8
NC
-
G6
E7
NC
-
-
-
-
GND
T
C
T
C
T
C
T
C
T
C
T
C
T
C
PR8B
PT8A
PT7B
PT7A
PT6A
PT6A
PT5B
PT5A
PT4B
PT4A
PT3B
PT3A
PT2B
4-33
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
PT2A
GND0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND
A1
A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A22
AB1
AB22
H15
H8
A22
AB1
AB22
H15
H8
J10
J11
J12
J13
J14
J9
J10
J11
J12
J13
J14
J9
K10
K11
K12
K13
K14
K9
K10
K11
K12
K13
K14
K9
L10
L11
L12
L13
L14
L9
L10
L11
L12
L13
L14
L9
M10
M11
M12
M13
M14
M9
M10
M11
M12
M13
M14
M9
N10
N11
N12
N13
N14
N9
N10
N11
N12
N13
N14
N9
P10
P11
P12
P13
P10
P11
P12
P13
4-34
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
P14
P9
GND
GND
-
-
P14
P9
GND
GND
-
-
R15
R8
GND
-
R15
R8
GND
-
GND
-
GND
-
J16
J7
VCC
-
J16
J7
VCC
-
VCC
-
VCC
-
K16
K17
K6
VCC
-
K16
K17
K6
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
K7
VCC
-
K7
VCC
-
L17
L6
VCC
-
L17
L6
VCC
-
VCC
-
VCC
-
M17
M6
VCC
-
M17
M6
VCC
-
VCC
-
VCC
-
N16
N17
N6
VCC
-
N16
N17
N6
VCC
-
VCC
-
VCC
-
VCC
-
VCC
-
N7
VCC
-
N7
VCC
-
P16
P7
VCC
-
P16
P7
VCC
-
VCC
-
VCC
-
G11
H10
H11
H9
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
G11
H10
H11
H9
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO4
VCCIO4
VCCIO4
VCCIO4
VCCIO5
VCCIO5
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
G12
H12
H13
H14
J15
K15
L15
L16
M15
M16
N15
P15
R12
R13
R14
T12
R10
R11
G12
H12
H13
H14
J15
K15
L15
L16
M15
M16
N15
P15
R12
R13
R14
T12
R10
R11
4-35
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP6/LFEC6, LFECP20/LFEC20 Logic Signal Connections: 484 fpBGA
LFEC6/LFECP6
LFEC20/LFECP20
Ball
Number
Ball
Function Bank LVDS
Ball
Number
Ball
Function Bank LVDS
Dual Function
Dual Function
R9
T11
M7
M8
N8
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCC
5
5
6
6
6
6
7
7
7
7
-
R9
T11
M7
M8
N8
VCCIO5
VCCIO5
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO7
VCCIO7
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCC
5
5
6
6
6
6
7
7
7
7
-
P8
P8
J8
J8
K8
K8
L7
L7
L8
L8
G15
G16
G7
G8
H16
H7
G15
G16
G7
G8
H16
H7
-
-
-
-
-
-
-
-
-
-
R16
R7
-
R16
R7
-
-
-
T15
T16
T7
-
T15
T16
T7
-
-
-
-
-
T8
-
T8
-
J6
-
J6
-
J17
P6
VCC
-
J17
P6
VCC
-
VCC
-
VCC
-
P17
A2
VCC
-
P17
A2
VCC
-
NC
-
NC
-
AB2
A21
NC
-
AB2
A21
NC
-
NC
-
NC
-
4-36
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA
Ball Number
Ball Function
Bank
LVDS
Dual Function
VREF2_7
E3
PL2A
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
T
E4
PL2B
C
T
VREF1_7
B1
PL3A
C1
PL3B
C
T
F3
PL4A
G3
D2
PL4B
C
T
PL5A
E2
PL5B
C
T
D1
PL6A
LDQS6
E1
PL6B
C
T
F2
PL7A
G2
F6
PL7B
C
T
PL8A
LUM0_PLLT_IN_A
LUM0_PLLC_IN_A
LUM0_PLLT_FB_A
G6
H4
PL8B
C
T
PL9A
GND
G4
J4
GND07
PL9B
7
7
7
7
7
7
7
7
C
T
C
T
C
T
C
T
LUM0_PLLC_FB_A
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
GND07
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
GND07
PL18B
PL19A
PL19B
PL20A
PL20B
PL21A
PL21B
PL22A
GND07
J5
K4
K5
J6
K6
F1
GND
G1
H1
7
7
7
7
7
7
7
7
C
T
C
T
C
T
C
T
J1
K2
K1
K3
L3
L2
GND
L1
7
7
7
7
7
7
7
7
C
T
C
T
C
T
C
T
M3
M4
M1
M2
L4
LDQS19
L5
N2
PCLKT7_0
GND
4-37
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
Ball Function
PL22B
XRES
Bank
LVDS
Dual Function
N1
7
6
6
6
6
6
6
6
6
C
PCLKC7_0
N3
P1
PL24A
PL24B
PL25A
PL25B
PL26A
PL26B
PL27A
GND06
PL27B
PL28A
PL28B
PL29A
PL29B
PL30A
PL30B
PL31A
GND06
PL31B
PL32A
PL32B
PL33A
PL33B
PL34A
PL34B
PL35A
GND06
PL35B
PL36A
PL36B
PL37A
PL37B
PL38A
PL38B
PL39A
GND06
PL39B
TCK
T
C
T
C
T
C
T
P2
L7
L6
N4
N5
R1
GND
R2
6
6
6
6
6
6
6
6
C
T
C
T
C
T
C
T
P4
LDQS28
P3
M5
M6
T1
T2
R4
GND
R3
6
6
6
6
6
6
6
6
C
T
C
T
C
T
C
T
N6
P5
P6
R5
U1
U2
T3
GND
T4
6
6
6
6
6
6
6
6
C
T
C
T
C
T
C
T
R6
LDQS36
T5
T6
U5
U3
U4
V1
GND
V2
6
6
6
6
6
6
6
C
U7
V4
TDI
V5
TMS
V3
TDO
U6
VCCJ
W1
PL41A
T
LLM0_PLLT_IN_A
4-38
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
Ball Function
PL41B
PL42A
PL42B
PL43A
PL43B
PL44A
GND06
PL44B
PL45A
PL45B
PL46A
PL46B
PL47A
PL47B
PL48A
PL48B
GND06
GND05
PB2A
Bank
LVDS
Dual Function
LLM0_PLLC_IN_A
LLM0_PLLT_FB_A
LLM0_PLLC_FB_A
W2
6
6
6
6
6
6
C
T
C
T
C
T
V6
W6
Y1
Y2
W3
GND
W4
6
6
6
6
6
6
6
6
6
C
T
AA1
AB1
Y4
LDQS45
C
T
Y3
C
T
AC1
AB2
AB4
AC4
GND
GND
AB6
AA6
AC7
Y8
C
T
VREF1_6
VREF2_6
C
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
PB2B
PB3A
PB3B
AB7
AA7
AC6
AC5
AB8
AC8
AE2
AA8
AF2
Y9
PB4A
PB4B
PB5A
PB5B
PB6A
BDQS6
PB6B
PB7A
PB7B
PB8A
PB8B
AD5
GND
AD4
AD8
AC9
AE3
AB9
AF3
AD9
AE4
GND
AF4
PB9A
GND05
PB9B
5
5
5
5
5
5
5
5
C
T
C
T
C
T
C
T
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
GND05
PB13B
5
C
4-39
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
Ball Function
PB14A
PB14B
PB15A
PB15B
PB16A
PB16B
PB17A
GND05
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
GND05
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
GND05
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
GND05
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
GND05
Bank
LVDS
Dual Function
AE5
5
5
5
5
5
5
5
T
C
T
C
T
C
T
BDQS14
AA9
AF5
Y10
AD6
AC10
AF6
GND
AE6
5
5
5
5
5
5
5
5
C
T
C
T
C
T
C
T
AF7
AB10
AE7
AD10
AD7
AA10
AF8
GND
AF9
5
5
5
5
5
5
5
5
C
T
C
T
C
T
C
T
AD11
Y11
BDQS22
AE8
AC11
AF10
AB11
AE10
GND
AE9
5
5
5
5
5
5
5
5
C
T
C
T
C
T
C
T
AA11
Y12
AE11
AF11
AF12
AE12
AD12
GND
AC12
AA12
AB12
AE13
AF13
AD13
AC13
AF14
GND
5
5
5
5
5
5
5
5
C
T
C
T
C
T
C
T
BDQS30
VREF2_5
VREF1_5
PCLKT5_0
4-40
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
AE14
AA13
AB13
AD14
AA14
AC14
AB14
AF15
GND
AE15
AD15
AC15
AF16
Y14
Ball Function
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
GND04
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
GND04
PB41B
PB42A
PB42B
PB43A
PB43B
PB44A
PB44B
PB45A
GND04
PB45B
PB46A
PB46B
PB47A
PB47B
PB48A
PB48B
PB49A
GND04
PB49B
PB50A
PB50B
PB51A
PB51B
PB52A
PB52B
PB53A
Bank
LVDS
Dual Function
PCLKC5_0
WRITEN
CS1N
5
4
4
4
4
4
4
4
C
T
C
T
C
T
C
T
VREF1_4
CSN
VREF2_4
D0/SPID7
D2/SPID5
4
4
4
4
4
4
4
4
C
T
C
T
C
T
C
T
D1/SPID6
BDQS38
D3/SPID4
D4/SPID3
D5/SPID2
AE16
AB15
AF17
GND
AE17
Y15
4
4
4
4
4
4
4
4
C
T
C
T
C
T
C
T
D6/SPID1
AA15
AD17
Y16
AD18
AC16
AE18
GND
AF18
AD16
AB16
AF19
AA16
AA17
Y17
4
4
4
4
4
4
4
4
C
T
C
T
C
T
C
T
BDQS46
AF21
GND
AF20
AE21
AC17
AF22
AB17
AE22
AA18
AE19
4
4
4
4
4
4
4
4
C
T
C
T
C
T
C
T
4-41
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
GND
AE20
AA19
Y18
Ball Function
GND04
PB53B
PB54A
PB54B
PB55A
PB55B
PB56A
PB56B
PB57A
PB57B
GND04
GND03
PR48B
PR48A
PR47B
PR47A
PR46B
PR46A
PR45B
PR45A
PR44B
GND03
PR44A
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
CFG2
Bank
LVDS
Dual Function
4
4
4
4
4
4
4
4
4
C
T
BDQS54
C
T
AF23
AA20
AC18
AB18
AF24
AE23
GND
GND
AC23
AC24
AC25
AC26
AB25
AA25
AB26
AA26
W23
GND
W24
W22
W21
Y25
C
T
C
T
C
3
3
3
3
3
3
3
3
3
C
T
VREF2_3
VREF1_3
C
T
C
T
C
T
RDQS45
C
RLM0_PLLC_IN_A
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
T
C
T
C
T
C
T
RLM0_PLLT_IN_A
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
DI/CSSPIN
Y26
DOUT/CSON
W25
W26
V24
BUSY/SISPI
D7/SPID0
V21
CFG1
V23
CFG0
V22
PROGRAMN
CCLK
V20
V25
INITN
U20
DONE
V26
PR39B
GND03
PR39A
PR38B
PR38A
PR37B
PR37A
PR36B
C
GND
U26
3
3
3
3
3
3
T
C
T
U24
U25
U23
C
T
U22
U21
C
4-42
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
Ball Function
PR36A
PR35B
GND03
PR35A
PR34B
PR34A
PR33B
PR33A
PR32B
PR32A
PR31B
GND03
PR31A
PR30B
PR30A
PR29B
PR29A
PR28B
PR28A
PR27B
GND03
PR27A
PR26B
PR26A
PR25B
PR25A
PR24B
PR24A
PR22B
GND02
PR22A
PR21B
PR21A
PR20B
PR20A
PR19B
PR19A
PR18B
GND02
PR18A
PR17B
PR17A
PR16B
PR16A
Bank
LVDS
Dual Function
T21
3
3
T
RDQS36
T25
C
GND
T26
3
3
3
3
3
3
3
3
T
C
T
T22
T23
T24
C
T
R23
R25
R24
R26
GND
P26
R21
R22
P25
P24
P23
P22
N26
GND
M26
N21
P21
N23
N22
N25
N24
L26
C
T
C
3
3
3
3
3
3
3
3
T
C
T
C
T
C
T
RDQS28
C
3
3
3
3
3
3
3
2
T
C
T
C
T
C
T
C
PCLKC2_0
PCLKT2_0
GND
K26
M22
M23
M25
M24
M21
L21
2
2
2
2
2
2
2
2
T
C
T
C
T
C
T
RDQS19
L22
C
GND
L23
2
2
2
2
2
T
C
T
C
T
L25
L24
K25
J25
4-43
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
Ball Function
PR15B
PR15A
PR14B
PR14A
GND02
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
PR9B
Bank
LVDS
Dual Function
J26
2
2
2
2
C
T
C
T
H26
H25
J24
GND
K21
K22
K20
J20
2
2
2
2
2
2
2
C
T
C
T
K23
K24
F25
C
T
C
RUM0_PLLC_FB_A
GND
G25
H23
H24
H21
G21
D26
D25
F21
GND02
PR9A
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
RUM0_PLLT_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_IN_A
PR8B
PR8A
PR7B
PR7A
PR6B
PR6A
RDQS6
PR5B
G22
G24
G23
C26
C25
E23
D23
GND
GND
A24
A23
E18
D19
F19
PR5A
PR4B
PR4A
PR3B
PR3A
PR2B
VREF1_2
VREF2_2
PR2A
GND02
GND01
PT57B
PT57A
PT56B
PT56A
PT55B
PT55A
PT54B
PT54A
PT53B
GND01
PT53A
PT52B
PT52A
PT51B
1
1
1
1
1
1
1
1
1
C
T
C
T
C
T
B22
G19
B21
D18
GND
C18
F18
C
T
TDQS54
C
1
1
1
1
T
C
T
A22
G18
C
4-44
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
A21
E17
B17
C17
GND
D17
F17
Ball Function
PT51A
PT50B
PT50A
PT49B
GND01
PT49A
PT48B
PT48A
PT47B
PT47A
PT46B
PT46A
PT45B
GND01
PT45A
PT44B
PT44A
PT43B
PT43A
PT42B
PT42A
PT41B
GND01
PT41A
PT40B
PT40A
PT39B
PT39A
PT38B
PT38A
PT37B
GND01
PT37A
PT36B
PT36A
PT35B
PT35A
PT34B
PT34A
PT33B
GND01
PT33A
PT32B
PT32A
Bank
LVDS
Dual Function
1
1
1
1
T
C
T
C
1
1
1
1
1
1
1
1
T
C
T
E20
G17
B20
E16
A20
A19
GND
B19
D16
C16
F16
C
T
C
T
TDQS46
C
1
1
1
1
1
1
1
1
T
C
T
C
T
A18
G16
B18
A17
GND
A16
D15
B16
E15
C15
F15
C
T
C
1
1
1
1
1
1
1
1
T
C
T
C
T
C
T
G15
B15
GND
A15
E14
G14
D14
E13
F14
TDQS38
C
1
1
1
1
1
1
1
0
T
C
T
C
T
VREF2_1
VREF1_1
C
T
C14
B14
GND
A14
D13
C13
C
PCLKC0_0
0
0
0
T
C
T
PCLKT0_0
VREF1_0
VREF2_0
4-45
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
A13
B13
F13
F12
A12
GND
B12
A11
B11
D12
C12
B10
A10
G12
GND
A9
Ball Function
PT31B
PT31A
PT30B
PT30A
PT29B
GND00
PT29A
PT28B
PT28A
PT27B
PT27A
PT26B
PT26A
PT25B
GND00
PT25A
PT24B
PT24A
PT23B
PT23A
PT22B
PT22A
PT21B
GND00
PT21A
PT20B
PT20A
PT19B
PT19A
PT18B
PT18A
PT17B
GND00
PT17A
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT13B
GND00
PT13A
PT12B
Bank
LVDS
Dual Function
0
0
0
0
0
C
T
C
T
TDQS30
C
0
0
0
0
0
0
0
0
T
C
T
C
T
C
T
C
0
0
0
0
0
0
0
0
T
C
T
E12
B9
F11
A8
C
T
D11
C11
B8
C
T
TDQS22
C
GND
B7
0
0
0
0
0
0
0
0
T
C
T
E11
A7
G11
C7
C
T
G10
C6
C
T
C10
GND
D10
F10
A6
C
0
0
0
0
0
0
0
0
T
C
T
E10
C9
C
T
G9
C
T
D9
TDQS14
A5
C
GND
A4
0
0
T
F9
C
4-46
Pinout Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LFECP20/LFEC20 Logic Signal Connections: 672 fpBGA (Cont.)
Ball Number
Ball Function
PT12A
PT11B
PT11A
PT10B
PT10A
PT9B
Bank
LVDS
Dual Function
B6
0
0
0
0
0
0
T
C
T
E9
C8
G8
C
T
B5
A3
C
GND
A2
GND00
PT9A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
F8
PT8B
B4
PT8A
E8
PT7B
B3
PT7A
D8
PT6B
G7
PT6A
TDQS6
C4
PT5B
C5
PT5A
E7
PT4B
D4
PT4A
F7
PT3B
D6
PT3A
D7
PT2B
E6
PT2A
GND
GND00
4-47
LatticeECP/EC Family Data Sheet
Ordering Information
October 2004
Preliminary Data Sheet
Part Number Description
LFXXX XX X – X XXXX X
Device Family
Grade
Lattice EC (FPGA)
C = Commercial
Lattice ECP (EC FPGA + DSP Blocks)
I = Industrial
Logic Capacity
1* = 1.5K LUTs
3* = 3K LUTs
6 = 6K LUTs
Package
T100 = 100-pin TQFP*
T144 = 144-pin TQFP
Q208 = 208-pin PQFP
F256 = 256-ball fpBGA
F484 = 484-ball fpBGA
F672 = 672-ball fpBGA
F900 = 900-ball fpBGA
10 = 10K LUTs
15 = 15K LUTs
20 = 20K LUTs
33 = 33K LUTs
40 = 40K LUTs
Speed
Supply Voltage
3 = Slowest
4
5 = Fastest
E = 1.2V
*Not available in the LatticeECP Family.
Ordering Information
Note: LatticeECP/EC devices are dual marked. For example, the commercial speed grade LFEC20E-4F484C is
also marked with industrial grade -3I (LFEC20E-3F484I). The commercial grade is one speed grade faster than the
associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings.
The markings appear as follows:
EC
LFEC20C-
4F484C-3I
Datecode
LatticeEC Commercial
Part Number
LFEC1E-3Q208C
LFEC1E-4Q208C
LFEC1E-5Q208C
LFEC1E-3T144C
LFEC1E-4T144C
LFEC1E-5T144C
LFEC1E-3T100C
I/Os
112
112
112
97
Grade
-3
Package
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
208
144
144
144
100
Temp.
COM
COM
COM
COM
COM
COM
COM
LUTs
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
-4
-5
-3
97
-4
97
-5
67
-3
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
5-1
Order Info_01.1
Ordering Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LatticeEC Commercial (Continued)
Part Number
LFEC1E-4T100C
LFEC1E-5T100C
I/Os
67
Grade
-4
Package
TQFP
Pins
100
100
Temp.
COM
COM
LUTs
1.5K
1.5K
67
-5
TQFP
Part Number
LFEC3E-3F256C
LFEC3E-4F256C
LFEC3E-5F256C
LFEC3E-3Q208C
LFEC3E-4Q208C
LFEC3E-5Q208C
LFEC3E-3T144C
LFEC3E-4T144C
LFEC3E-5T144C
LFEC3E-3T100C
LFEC3E-4T100C
LFEC3E-5T100C
I/Os
160
160
160
145
145
145
97
Grade
-3
Package
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
Pins
256
256
256
208
208
208
144
144
144
100
100
100
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
-4
-5
-3
-4
-5
-3
97
-4
97
-5
67
-3
67
-4
67
-5
Part Number
LFEC6E-3F484C
LFEC6E-4F484C
LFEC6E-5F484C
LFEC6E-3F256C
LFEC6E-4F256C
LFEC6E-5F256C
LFEC6E-3Q208C
LFEC6E-4Q208C
LFEC6E-5Q208C
LFEC6E-3T144C
LFEC6E-4T144C
LFEC6E-5T144C
I/Os
224
224
224
195
195
195
147
147
147
97
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
TQFP
TQFP
Pins
484
484
484
256
256
256
208
208
208
144
144
144
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
-4
-5
-3
-4
-5
-3
-4
-5
-3
97
-4
97
-5
Part Number
LFEC10E-3F484C
LFEC10E-4F484C
LFEC10E-5F484C
LFEC10E-3F256C
LFEC10E-4F256C
LFEC10E-5F256C
LFEC10E-3Q208C
LFEC10E-4Q208C
LFEC10E-5Q208C
I/Os
288
288
288
195
195
195
147
147
147
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
Pins
484
484
484
256
256
256
208
208
208
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
-4
-5
-3
-4
-5
-3
-4
-5
5-2
Ordering Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LatticeEC Commercial (Continued)
Part Number
LFEC15E-3F484C
LFEC15E-4F484C
LFEC15E-5F484C
LFEC15E-3F256C
LFEC15E-4F256C
LFEC15E-5F256C
I/Os
352
352
352
195
195
195
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
484
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
LUTs
15.3K
15.3K
15.3K
15.3K
15.3K
15.3K
-4
-5
-3
-4
-5
Part Number
LFEC20E-3F672C
LFEC20E-4F672C
LFEC20E-5F672C
LFEC20E-3F484C
LFEC20E-4F484C
LFEC20E-5F484C
I/Os
400
400
400
360
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
672
484
484
484
Temp.
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
-4
-5
-3
-4
-5
Part Number
LFEC33E-3F672C
LFEC33E-4F672C
LFEC33E-4F672C
LFEC33E-3F484C
LFEC33E-4F484C
LFEC33E-4F484C
I/Os
496
496
496
360
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
672
484
484
484
Temp.
COM
COM
COM
COM
COM
COM
LUTs
32.8K
32.8K
32.8K
32.8K
32.8K
32.8K
-4
-5
-3
-4
-5
Part Number
LFEC40E-3F900C
LFEC40E-4F900C
LFEC40E-5F900C
LFEC40E-3F672C
LFEC40E-4F672C
LFEC40E-5F672C
I/Os
576
576
576
496
496
496
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
900
900
900
672
672
672
Temp.
COM
COM
COM
COM
COM
COM
LUTs
40.9K
40.9K
40.9K
40.9K
40.9K
40.9K
-4
-5
-3
-4
-5
LatticeECP Commercial
Part Number
LFECP6E-3F484C
LFECP6E-4F484C
LFECP6E-5F484C
LFECP6E-3F256C
LFECP6E-4F256C
LFECP6E-5F256C
LFECP6E-3Q208C
LFECP6E-4Q208C
LFECP6E-5Q208C
LFECP6E-3T144C
I/Os
224
224
224
195
195
195
147
147
147
97
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
TQFP
Pins
484
484
484
256
256
256
208
208
208
144
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
-4
-5
-3
-4
-5
-3
-4
-5
-3
5-3
Ordering Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LatticeECP Commercial (Continued)
Part Number
LFECP6E-4T144C
LFECP6E-5T144C
I/Os
97
Grade
-4
Package
TQFP
Pins
144
144
Temp.
COM
COM
LUTs
6.1K
6.1K
97
-5
TQFP
Part Number
LFECP10E-3F484C
LFECP10E-4F484C
LFECP10E-5F484C
LFECP10E-3F256C
LFECP10E-4F256C
LFECP10E-5F256C
LFECP10E-3Q208C
LFECP10E-4Q208C
LFECP10E-5Q208C
I/Os
288
288
288
195
195
195
147
147
147
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
PQFP
Pins
484
484
484
256
256
256
208
208
208
Temp.
COM
COM
COM
COM
COM
COM
COM
COM
COM
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
-4
-5
-3
-4
-5
-3
-4
-5
Part Number
LFECP15E-3F484C
LFECP15E-4F484C
LFECP15E-5F484C
LFECP15E-3F256C
LFECP15E-4F256C
LFECP15E-5F256C
I/Os
352
352
352
195
195
195
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
484
256
256
256
Temp.
COM
COM
COM
COM
COM
COM
LUTs
15.3K
15.3K
15.3K
15.3K
15.3K
15.3K
-4
-5
-3
-4
-5
Part Number
LFECP20E-3F672C
LFECP20E-4F672C
LFECP20E-5F672C
LFECP20E-3F484C
LFECP20E-4F484C
LFECP20E-5F484C
I/Os
400
400
400
360
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
672
484
484
484
Temp.
COM
COM
COM
COM
COM
COM
LUTs
19.7K
19.7K
19.7K
19.7K
19.7K
19.7K
-4
-5
-3
-4
-5
Part Number
LFECP33E-3F672C
LFECP33E-4F672C
LFECP33E-4F672C
LFECP33E-3F484C
LFECP33E-4F484C
LFECP33E-4F484C
I/Os
496
496
496
360
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
672
484
484
484
Temp.
COM
COM
COM
COM
COM
COM
LUTs
32.8K
32.8K
32.8K
32.8K
32.8K
32.8K
-4
-5
-3
-4
-5
Part Number
LFECP40E-3F900C
LFECP40E-4F900C
LFECP40E-5F900C
LFECP40E-3F672C
I/Os
576
576
576
496
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
900
900
900
672
Temp.
COM
COM
COM
COM
LUTs
40.9K
40.9K
40.9K
40.9K
-4
-5
-3
5-4
Ordering Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LatticeECP Commercial (Continued)
Part Number
LFECP40E-4F672C
LFECP40E-5F672C
I/Os
496
496
Grade
-4
Package
fpBGA
Pins
672
672
Temp.
COM
COM
LUTs
40.9K
40.9K
-5
fpBGA
LatticeEC Industrial
Part Number
LFEC1E-3Q208I
LFEC1E-4Q208I
LFEC1E-3T144I
LFEC1E-4T144I
LFEC1E-3T100I
LFEC1E-4T100I
I/Os
112
112
97
Grade
-3
Package
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
Pins
208
208
144
144
100
100
Temp.
IND
IND
IND
IND
IND
IND
LUTs
1.5K
1.5K
1.5K
1.5K
1.5K
1.5K
-4
-3
97
-4
67
-3
67
-4
Part Number
LFEC3E-3F256I
LFEC3E-4F256I
LFEC3E-3Q208I
LFEC3E-4Q208I
LFEC3E-3T144I
LFEC3E-4T144I
LFEC3E-3T100I
LFEC3E-4T100I
I/Os
160
160
145
145
97
Grade
-3
Package
fpBGA
fpBGA
PQFP
PQFP
TQFP
TQFP
TQFP
TQFP
Pins
256
256
208
208
144
144
100
100
Temp.
IND
IND
IND
IND
IND
IND
IND
IND
LUTs
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
3.1K
-4
-3
-4
-3
97
-4
67
-3
67
-4
Part Number
LFEC6E-3F484I
LFEC6E-4F484I
LFEC6E-3F256I
LFEC6E-4F256I
LFEC6E-3Q208I
LFEC6E-4Q208I
LFEC6E-3T144I
LFEC6E-4T144I
I/Os
224
224
195
195
147
147
97
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
TQFP
Pins
484
484
256
256
208
208
144
144
Temp.
IND
IND
IND
IND
IND
IND
IND
IND
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
-4
-3
-4
-3
-4
-3
97
-4
TQFP
Part Number
LFEC10E-3F484I
LFEC10E-4F484I
LFEC10E-3F256I
LFEC10E-4F256I
LFEC10E-3 P208I
LFEC10E-4 P208I
I/Os
288
288
195
195
147
147
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
Pins
484
484
256
256
208
208
Temp.
IND
IND
IND
IND
IND
IND
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
-4
-3
-4
-3
-4
PQFP
Part Number
LFEC15E-3F484I
LFEC15E-4F484I
I/Os
352
352
Grade
-3
Package
fpBGA
Pins
484
484
Temp.
IND
LUTs
15.3K
15.3K
-4
fpBGA
IND
5-5
Ordering Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LatticeEC Industrial (Continued)
Part Number
LFEC15E-3F256I
LFEC15E-4F256I
I/Os
195
195
Grade
-3
Package
fpBGA
Pins
256
256
Temp.
IND
LUTs
15.3K
15.3K
-4
fpBGA
IND
Part Number
LFEC20E-3F672I
LFEC20E-4F672I
LFEC20E-3F484I
LFEC20E-4F484I
I/Os
400
400
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
484
484
Temp.
IND
LUTs
19.7K
19.7K
19.7K
19.7K
-4
IND
-3
IND
-4
IND
Part Number
LFEC33-3F672I
LFEC33-4F672I
LFEC33-3F484I
LFEC33-4F484I
I/Os
496
496
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
484
484
Temp.
IND
LUTs
32.8
32.8
32.8
32.8
-4
IND
-3
IND
-4
IND
Part Number
LFEC40E-3F900I
LFEC40E-4F900I
LFEC40E-3F672I
LFEC40E-4F672I
I/Os
576
576
496
496
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
900
900
672
672
Temp.
IND
LUTs
40.9K
40.9K
40.9K
40.9K
-4
IND
-3
IND
-4
IND
LatticeECP Industrial
Part Number
LFECP6E-3F484I
LFECP6E-4F484I
LFECP6E-3F256I
LFECP6E-4F256I
LFECP6E-3Q208I
LFECP6E-4Q208I
LFECP6E-3T144I
LFECP6E-4T144I
I/Os
Grade
Package
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
PQFP
TQFP
Pins
Temp.
IND
IND
IND
IND
IND
IND
IND
IND
LUTs
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
6.1K
224
224
195
195
147
147
97
-3
-4
-3
-4
-3
-4
-3
-4
484
484
256
256
208
208
144
144
97
TQFP
Part Number
LFECP10E-3F484I
LFECP10E-4F484I
LFECP10E-3F256I
LFECP10E-4F256I
LFECP10E-3Q208I
LFECP10E-4Q208I
I/Os
288
288
195
195
147
147
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
PQFP
Pins
484
484
256
256
208
208
Temp.
IND
IND
IND
IND
IND
IND
LUTs
10.2K
10.2K
10.2K
10.2K
10.2K
10.2K
-4
-3
-4
-3
-4
PQFP
5-6
Ordering Information
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
LatticeECP Industrial (Continued)
Part Number
LFECP15E-3F484I
LFECP15E-4F484I
LFECP15E-3F256I
LFECP15E-4F256I
I/Os
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
484
484
256
256
Temp.
IND
LUTs
15.3K
15.3K
15.3K
15.3K
352
352
195
195
-4
IND
-3
IND
-4
IND
Part Number
LFECP20E-3F672I
LFECP20E-4F672I
LFECP20E-3F484I
LFECP20E-4F484I
I/Os
400
400
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
484
484
Temp.
IND
LUTs
19.7K
19.7K
19.7K
19.7K
-4
IND
-3
IND
-4
IND
Part Number
LFECP33-3F672I
LFECP33-4F672I
LFECP33-3F484I
LFECP33-4F484I
I/Os
496
496
360
360
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
672
672
484
484
Temp.
IND
LUTs
32.8K
32.8K
32.8K
32.8K
-4
IND
-3
IND
-4
IND
Part Number
LFECP40E-3F900I
LFECP40E-4F900I
LFECP40E-3F672I
LFECP40E-4F672I
I/Os
576
576
496
496
Grade
-3
Package
fpBGA
fpBGA
fpBGA
fpBGA
Pins
900
900
672
672
Temp.
IND
LUTs
40.9K
40.9K
40.9K
40.9K
-4
IND
-3
IND
-4
IND
5-7
LatticeECP/EC Family Data Sheet
Supplemental Information
Preliminary Data Sheet
October 2004
For Further Information
A variety of technical notes for the LatticeECP/EC family are available on the Lattice web site at www.latticesemi.com.
• LatticeECP/EC sysIO Usage Guide (TN1056)
• ispTRACY Internal Logic Analyzer Guide (TN1054)
• LatticeECP/EC sysCLOCK PLL Design and Usage Guide (TN1049)
• Memory Usage Guide for LatticeECP/EC Devices (TN1051)
• LatticeECP/EC DDR Usage Guide (TN1050)
• Estimating Power Using Power Calculator for LatticeECP/EC Devices (TN1052)
• sysDSP/MAC Usage Guide (TN1057)
• LatticeECP/EC sysCONFIG Usage Guide (TN1053)
• IEEE 1149.1 Boundary Scan Testability in Lattice Devices
For further information on interface standards refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
• PCI: ww.pcisig.com
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
6-1
Further Info_01.1
相关型号:
©2020 ICPDF网 联系我们和版权申明