LFECP40E-4F676I_技术文档

LatticeECP/EC Family Data Sheet

Introduction

June 2004

Advance Data Sheet

− LVCMOS 3.3/2.5/1.8/1.5/1.2

− LVTTL

− SSTL 3/2 Class I, II, SSTL18 Class I

− HSTL 18 Class I, II, III, HSTL15 Class I, III

− PCI

Features

■ Extensive Density and Package Options

• 1.5K to 41K LUT4s

• 65 to 576 I/Os

• Density migration supported

− LVDS, Bus-LVDS, LVPECL

■ sysDSP™ Block (LatticeECP™ Versions)

• High performance multiply and accumulate

• 4 to 10 blocks

■ Dedicated DDR Memory Support

• Implements interface up to DDR333 (166MHz)

■ sysCLOCK™ PLLs

− 4 to 10 36x36 multipliers or

– 16 to 40 18x18 multipliers or

− 32 to 80 9x9 multipliers

• Up to 4 analog PLLs per device

• Clock multiply, divide and phase shifting

■ System Level Support

■ Embedded and Distributed Memory

• 18 Kbits to 645 Kbits sysMEM™ Embedded

Block RAM (EBR)

• IEEE Standard 1149.1 Boundary Scan, plus

ispTRACY™ internal logic analyzer capability

• SPI boot ﬂash interface

• Up to 163 Kbits distributed RAM

• Flexible memory resources:

• 1.2V power supply

■ Low Cost FPGA

− Distributed and block memory

• Features optimized for mainstream applications

• Low cost TQFP and PQFP packaging

■ Flexible I/O Buffer

• Programmable sysIO™ buffer supports wide

range of interfaces:

Table 1-1. LatticeECP/EC Family Selection Guide

LFEC6/

LFECP6

LFEC10/

LFEC15/

LFEC20/

LFEC40/

Device

PFU/PFF Rows

LFEC1

12

16

192

1.5

6

LFEC3

16

LFECP10 LFECP15 LFECP20 LFECP40

24

32

768

6.1

25

92

10

4

32

40

48

44

56

64

80

PFU/PFF Columns

PFUs/PFFs

24

384

3.1

12

1280

10.2

41

1920

15.4

61

2464

19.7

79

5120

41.0

164

645

70

LUTs (K)

Distributed RAM (Kbits)

EBR SRAM (Kbits)

EBR SRAM Blocks

sysDSP Blocks¹

18x18 Multipliers¹

18

2

55

277

30

350

38

424

46

6

—

5

6

7

10

—

16

1.2

2

20

24

28

40

V

Voltage (V)

1.2

2

1.2

2

1.2

4

1.2

4

1.2

4

1.2

4

CC

Number of PLLs

Packages and I/O Combinations:

100-pin TQFP (14 x 14 mm)

144-pin TQFP (20 x 20 mm)

208-pin PQFP (28 x 28 mm)

256-ball fpBGA (17 x 17 mm)

484-ball fpBGA (23 x 23 mm)

672-ball fpBGA (27 x 27 mm)

900-ball fpBGA (31 x 31 mm)

1. LatticeECP devices only.

67

97

67

97

112

145

160

147

195

224

147

195

288

195

352

360

400

496

576

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

1-1

Introduction_01

Introduction

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Introduction

The LatticeECP/EC family of FPGA devices has been optimized to deliver mainstream FPGA features at low cost.

For maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an efﬁcient FPGA

fabric with high-speed dedicated functions. Lattice’s ﬁrst family to implement this approach is the LatticeECP-DSP

(EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™ (ECon-

omy) family supports all the general purpose features of LatticeECP devices without dedicated function blocks to

achieve lower cost solutions.

The Lattice-ECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the criti-

cal FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.

Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prev-

alent in cost-sensitive applications.

The ispLEVER^®design tool from Lattice allows large complex designs to be efﬁciently implemented using the Latti-

ceECP/EC family of FPGA devices. Synthesis library support for LatticeECP/EC is available for popular logic syn-

thesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its ﬂoor planning

tools to place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the

routing and back-annotates it into the design for timing veriﬁcation.

Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC

family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their

design, increasing their productivity.

1-2

LatticeECP/EC Family Data Sheet

Architecture

June 2004

Advance Data Sheet

Architecture Overview

The LatticeECP™-DSP and LatticeEC™ architectures contain an array of logic blocks surrounded by Programma-

ble I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM

(EBR) as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DSP blocks as

shown in Figure 2-2.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit

without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-

tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks

are optimized for ﬂexibility allowing complex designs to be implemented quickly and efﬁciently. Logic Blocks are

arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-

side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every

three rows of PFF blocks there is a row of PFU blocks.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and

right edges of the device can be conﬁgured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast

memory blocks. They can be conﬁgured as RAM or ROM.

The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in

Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and

route software tool automatically allocates these routing resources.

At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These

PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the

clocks. The LatticeECP/EC architecture provides up to four PLLs per device.

Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™

port which allows for serial or parallel device conﬁguration. The LatticeECP/EC devices use 1.2V as their core volt-

age.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

2-1

Architecture_01

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-1. Simpliﬁed Block Diagram, LatticeECP/EC Device (Top Level)

Programmable I/O Cell

(PIC) includes sysIO

Interface

sysMEM Embedded

Block RAM (EBR)

JTAG Port

sysCONFIG Programming

Port (includes dedicated

and dual use pins)

PFF (PFU without

RAM)

sysCLOCK PLL

Programmable

Functional Unit (PFU)

Figure 2-2. Simpliﬁed Block Diagram, LatticeECP-DSP Device (Top Level)

Programmable I/O Cell

(PIC) includes sysIO

Interface

sysMEM Embedded

Block RAM (EBR)

JTAG Port

sysCONFIG Programming

Port (includes dedicated

and dual use pins)

PFF (Fast PFU

without RAM/ROM)

sysDSP Block

sysCLOCK PLL

Programmable

Functional Unit (PFU)

2-2

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

PFU and PFF Blocks

The core of the LatticeECP/EC devices consists of PFU and PFF blocks.The PFUs can be programmed to perform

Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform

Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term

PFU to refer to both PFU and PFF blocks.

Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec-

tions to and from PFU blocks are from routing.There are 53 inputs and 25 outputs associated with each PFU block.

Figure 2-3. PFU Diagram

From

Routing

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

Slice 3

Slice 0

Slice 1

Slice 2

D

FF/

Latch

D

FF/

Latch

D

FF/

Latch

D

FF/

Latch

D

FF/

Latch

D

FF/

Latch

D

FF/

Latch

D

FF/

Latch

To

Routing

Slice

Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and

some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and

LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock

select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice.

The registers in the slice can be conﬁgured for positive/negative and edge/level clocks.

There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).

There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated

with each slice.

2-3

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-4. Slice Diagram

To / From

Different slice / PFU

Slice

OFX1

F1

A1

CO

F

B1

C1

D1

Q1

LUT4 &

D

SUM

FF/

Latch

CARRY

CI

To

Routing

From

Routing

M1

M0

OFX0

LUT

Expansion

Mux

CO

A0

B0

F0

C0

LUT4 &

CARRY

F

D0

OFX0

Q0

SUM

D

FF/

Latch

CI

Control Signals

selected and

inverted per

CE

CLK

LSR

slice in routing

Interslice signals

are not shown

To / From

Different slice / PFU

Table 2-1. Slice Signal Descriptions

Function

Input

Type

Signal Names

Description

Data signal

A0, B0, C0, D0 Inputs to LUT4

A1, B1, C1, D1 Inputs to LUT4

Input

Data signal

Input

Multi-purpose

Control signal

Inter-PFU signal

Data signals

Inter-PFU signal

M0

M1

Multipurpose Input

Input

Multipurpose Input

Clock Enable

Input

CE

Input

LSR

Local Set/Reset

System Clock

Fast Carry In¹

Input

CLK

Input

FCIN

F0, F1

Q0, Q1

OFX0

OFX1

FCO

Output

LUT4 output register bypass signals

Register Outputs

Output of a LUT5 MUX

Output of a LUT6, LUT7, LUT8²MUX depending on the slice

For the right most PFU the fast carry chain output¹

1. See Figure 2-3 for connection details.

2. Requires two PFUs.

2-4

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Modes of Operation

Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of

all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.

Table 2-2. Slice Modes

Logic

Ripple

RAM

SPR16x2

N/A

ROM

PFU Slice

PFF Slice

LUT 4x2 or LUT 5x1

2-bit Arithmetic Unit

ROM16x1 x 2

Logic Mode: In this mode, the LUTs in each Slice are conﬁgured as 4-input combinatorial lookup tables. A LUT4

can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this

lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup

tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices.

Ripple Mode: Ripple mode allows the efﬁcient implementation of small arithmetic functions. In ripple mode, the fol-

lowing functions can be implemented by each Slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/Subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Ripple mode multiplier building block

• Comparator functions of A and B inputs

- A greater-than-or-equal-to B

- A not-equal-to B

- A less-than-or-equal-to B

Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast

arithmetic functions to be constructed by concatenating Slices.

RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory.

Through the combination of LUTs and Slices, a variety of different memories can be constructed.

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-

ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3

shows the number of Slices required to implement different distributed RAM primitives. Figure 2-5 shows the dis-

tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions

as the read-write port. The other companion Slice supports the read-only port. For more information on using RAM

in LatticeECP/EC devices, please see details of additional technical documentation at the end of this data sheet.

Table 2-3. Number of Slices Required For Implementing Distributed RAM

SPR16x2

DPR16x2

Number of slices

1

2

Note: SPR = Single Port RAM, DPR = Dual Port RAM

2-5

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-5. Distributed Memory Primatives

SPR16x2

DPR16x2

RAD0

RAD1

RAD2

RAD3

AD0

AD1

AD2

AD3

WAD0

WAD1

WAD2

WAD3

DO0

DO1

DI0

DI1

WRE

RDO0

RDO1

WDO0

WDO1

DI0

DI1

WCK

WRE

CK

ROM16x1

AD0

AD1

AD2

AD3

DO0

ROM Mode:The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is

accomplished through the programming interface during conﬁguration.

PFU Modes of Operation

Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the

functionality possible at the PFU level.

Table 2-4. PFU Modes of Operation

Logic

Ripple

RAM¹

ROM

LUT 4x8 or

MUX 2x1 x 8

2-bit Add x 4

SPR16x2 x 4

DPR16x2 x 2

ROM16x1 x 8

LUT 5x4 or

MUX 4x1 x 4

2-bit Sub x 4

2-bit Counter x 4

2-bit Comp x 4

SPR16x4 x 2

DPR16x4 x 1

ROM16x2 x 4

ROM16x4 x 2

ROM16x8 x 1

LUT 6x 2 or

MUX 8x1 x 2

SPR16x8 x 1

LUT 7x1 or

MUX 16x1 x 1

1. These modes are not available in PFF blocks

Routing

There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with

related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)

segments.

2-6

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).

The x1 and x2 connections provide fast and efﬁcient connections in horizontal and vertical directions. The x2 and

x6 resources are buffered allowing both short and long connections routing between PFUs.

The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the

place and route tool is completely automatic, although an interactive routing editor is available to optimize the

design.

Clock Distribution Network

The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed

through the chip via a clock distribution system.

Primary Clock Sources

LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.

LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There

are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.

Figure 2-6. Clock Sources

From Routing

Clock Input

From Routing

PLL Input

PLL

20 Primary Clock Sources

To Quadrant Clock Selection

Clock Input

PLL

PLL Input

From Routing

Clock Input

From Routing

Note: Smaller devices have two PLLs.

Clock Routing

The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock

network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows

this clock routing. The primary clock lines also feed into a secondary clock network (not shown). The secondary

clock branches are tapped at every PFU. These secondary clock networks can also be used for controls and high

fan out data. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown

in Figure 2-8.

2-7

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-7. Per Quadrant Clock Selection

20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing¹

4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant

1. Smaller devices have fewer PLL related lines.

Figure 2-8. Slice Clock Selection

Primary Clock

4

3

Secondary Clock

Routing

Clock to Slice

GND

sysCLOCK Phase Locked Loops (PLLs)

The PLL clock input, from pin or routing, feeds into an input clock divider. There are four sources of feedback signal

to the feedback divider: from the clock net, from output of the post scalar divider, from the routing or from an exter-

nal pin. There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-9 shows

the sysCLOCK PLL diagram.

The setup and hold times of the device can be improved by programming a delay in the feedback or input path of

the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-

grammed during conﬁguration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after

adjustment and not relock until the t

parameter has been satisﬁed. Additionally, the phase and duty cycle block

LOCK

allows the user to adjust the phase and duty cycle of the CLKOS output.

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated

with it: input clock divider, feedback divider, port scalar divider and secondary clock divider. The input clock divider

is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal.The post

scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-

quency range. The secondary divider is used to derive lower frequency outputs.

2-8

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-9. PLL Diagram

Dynamic Delay Adjustment

LOCK

RST

Input Clock

Divider

(CLKI)

Post Scalar

Divider

(CLKOP)

Phase/Duty

Select

Voltage

ConVtCroOlled

Oscillator

CLKOS

Delay

Adjust

CLKI

(from routing or

external pin)

CLKOP

CLKOK

Secondary

Clock

Divider

Feedback

Divider

(CLKFB)

CLKFB

(from Post Scalar

Divider output,

clock net or

external pin

(CLKOK)

Figure 2-10 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.

Figure 2-10. PLL Primitive

CLKOP

RST

CLKI

CLKOP

LOCK

CLKOS

CLKOK

LOCK

EPLLB

CLKFB

DDA MODE

DDAIZR

EHXPLLB

DDAOZR

DDAILAG

DDAOLAG

DDAODEL[2:0]

DDAIDEL[2:0]

Table 2-5. PLL Signal Descriptions

Signal

I/O

I

Description

CLKI

Clock input from external pin or routing

CLKFB

I

PLL feedback input from PLL output, clocknet, routing or external pin

“1” to reset input clock divider

RST

I

CLKOS

O

I

PLL output clock to clock tree (phase shifted/duty cycle changed)

PLL output clock to clock tree (No phase shift)

PLL output to clock tree through secondary clock divider

“1” indicates PLL LOCK to CLKI

CLKOP

CLKOK

LOCK

DDAMODE

DDAIZR

Dynamic Delay Enable. “1” Pin control (dynamic), “0”: Fuse Control (static)

Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on

Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead

Dynamic Delay Input

I

DDAILAG

DDAIDEL[2:0]

DDAOZR

DDAOLAG

DDAODEL[2:0]

I

O

Dynamic Delay Zero Output

Dynamic Delay Lag/Lead Output

Dynamic Delay Output

2-9

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

For more information on the PLL, please see details of additional technical documentation at the end of this data

sheet.

sysMEM Memory

The LatticeECP/EC family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR con-

sists of a 9-Kbit RAM, with dedicated input and output registers.

sysMEM Memory Block

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in

a variety of depths and widths as shown in Table 2-6.

Table 2-6. sysMEM Block Conﬁgurations

Memory Mode

Conﬁgurations

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

Single Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

True Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

Pseudo Dual Port

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device conﬁguration. By preloading the RAM block

during the chip conﬁguration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

Memory Cascading

Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on speciﬁc design inputs.

Single, Dual and Pseudo-Dual Port Modes

Figure 2-11 shows the four basic memory conﬁgurations and their input/output names. In all the sysMEM RAM

modes the input data and address for the ports are registered at the input of the memory array. The output data of

the memory is optionally registered at the output.

2-10

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-11. sysMEM EBR Primitives

ADA[12:0]

DIA[17:0]

CLKA

CEA

RSTA

WEA

CSA[2:0]

DOA[17:0]

ADB[12:0]

DIB[17:0]

CEB

CLKB

RSTB

WEB

CSB[2:0]

DOB[17:0]

AD[12:0]

DI[35:0]

CLK

DO[35:0]

CE

EBR

RST

WE

CS[2:0]

True Dual Port RAM

Single Port RAM

ADW[12:0]

DI[35:0]

CLKW

CEW

ADR[12:0]

DO[35:0]

AD[12:0]

CLK

DO[35:0]

CE

EBR

ROM

EBR

WE

RST

CS[2:0]

CER

RST

CS[2:0]

CLKR

Pseudo-Dual Port RAM

The EBR memory supports three forms of write behavior for single port or dual port operation:

1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current

address) does not appear on the output.

2. Write Through – a copy of the input data appears at the output of the same port, during a write cycle.

3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A

and Port B respectively.The Global Reset (GSRN) signal resets both ports.The output data latches and associated

resets for both ports are as shown in Figure 2-12.

2-11

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-12. Memory Core Reset

SET

D

Q

Memory Core

Port A[17:0]

L_CLR

Output Data

Latches

SET

D

Q

Port B[17:0]

L_CLR

RSTA

RSTB

GSRN

Programmable Disable

For further information on sysMEM EBR block, please see the details of additional technical documentation at the

end of this data sheet.

sysDSP Block

The LatticeECP-DSP family provides a sysDSP block making it ideally suited for low cost, high performance Digital

Signal Processing (DSP) applications. Typical functions used in these applications are Finite Impulse Response

(FIR) ﬁlters; Fast Fourier Transforms (FFT) functions, correlators, Reed-Solomon/Turbo/Convolution encoders and

decoders. These complex signal processing functions use similar building blocks such as multiply-adders and mul-

tiply-accumulators.

sysDSP Block Approach Compare to General DSP

Conventional general-purpose DSP chips typically contain one to four (Multiply and Accumulate) MAC units with

ﬁxed data-width multipliers; this leads to limited parallelism and limited throughput.Their throughput is increased by

higher clock speeds. The LatticeECP, on the other hand, has many DSP blocks that support different data-widths.

This allows the designer to use highly parallel implementations of DSP functions. The designer can optimize the

DSP performance vs. area by choosing appropriate level of parallelism. Figure 2-13 compares the serial and the

parallel implementations.

2-12

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-13. Comparison of General DSP and LatticeECP-DSP Approaches

Operand

A

Operand

A

Operand

A

Operand

B

Operand

B

Operand

B

Operand

A

Operand

B

Multiplier 0

x

m/k

loops

Multiplier 1

Multiplier

(k-1)

M loops

Single

Multiplier

x

Accumulator

Σ

Accumulator

Σ

Function implemented in

General purpose DSP

Output

Function implemented

in LatticeECP

sysDSP Block Capabilities

The sysDSP block in the LatticeECP-DSP family supports four functional elements in three 9, 18 and 36 data path

widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)

of its operands. The operands in the LatticeECP-DSP family sysDSP Blocks can be either signed or unsigned but

not mixed within a function element. Similarly, the operand widths cannot be mixed within a block.

The resources in each sysDSP block can be conﬁgured to support the following four elements:

• MULT

(Multiply)

• MAC

• MULTADD

(Multiply, Accumulate)

(Multiply, Addition/Subtraction)

• MULTADDSUM (Multiply, Addition/Subtraction, Accumulate)

The number of elements available in each block depends in the width selected from the three available options x9,

x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.

Table 2-1 shows the capabilities of the block.

Table 2-7. Maximum Number of Elements in a Block

Width of Multiply

MULT

x9

8

x18

4

x36

1

MAC

2

1

—

MULTADD

MULTADDSUM

4

2

4

2

Some options are available in four elements. The input register in all the elements can be directly loaded or can be

loaded as shift register from previous operand registers. In addition by selecting ‘dynamic operation’ in the ‘Signed/

Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly by select-

ing ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction

on every cycle.

2-13

Architecture

Lattice Semiconductor

MULT sysDSP Element

LatticeECP/EC Family Data Sheet

This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,

are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.

Figure 2-14 shows the MULT sysDSP element.

Figure 2-14. MULT sysDSP Element

Shift Register B In

Multiplicand

Shift Register A In

m

Multiplier

n

Multiplier

Input Data

Register A

m

n

m+n

(default)

m+n

n

x

Output

Input Data

Register B

Pipeline

Register

m

n

Signed

Input

Register

Pipeline

Register

To

Multiplier

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

RST(RST0,RST1,RST2,RST3)

Shift Register B Out

Shift Register A Out

MAC sysDSP Element

In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.

This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-

put register is always enabled. The output register is used to store the accumulated value. A registered overﬂow

signal is also available. The overﬂow conditions are provided later in this document. Figure 2-15 shows the MAC

sysDSP element.

2-14

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-15. MAC sysDSP Element

Shift Register B In

Shift Register A In

m

Multiplicand

Multiplier

m

Accumulator

m

n

m+n+16 bits

(default)

n

Multiplier

m

n

Input Data

Register A

n

Output

m+n+16 bits

(default)

x

m+n

(default)

Input Data

Register B

Pipeline

Register

n

SignedAB

Addn

Input

Register

Pipeline

Register

Overflow

signal

To

Multiplier

Input

Register

Pipeline

Register

To

Accumulator

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

Accumsload

Input

Register

Pipeline

Register

To

Accumulator

RST(RST0,RST1,RST2,RST3)

Shift Register B Out

Shift Register A Out

MULTADD sysDSP Element

In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-16

shows the MULTADD sysDSP element.

Figure 2-16. MULTADD

Shift Register B In

Shift Register A In

m

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

Multiplicand A0

m

RST(RST0,RST1,RST2,RST3)

m

n

Multiplier B0

n

Multiplier

Input Data

Register A

m

n

x

m+n

(default)

Input Data

Register B

Pipeline

Register

m

Add/Sub

n

Multiplicand A1

Multiplier B1

m

Output

m+n+1

(default)

m+n+1

(default)

m

n

Multiplier

m+n

(default)

Input Data

Register A

m

n

x

Input Data

Register B

Pipeline

Register

m

n

Signed

Addn

Input

Register

Pipeline

Pipe

Register

Reg

To

Multiplier

Input

Pipeline

Pipe

To

Register

Reg

Accumulator

Shift Register B Out

Shift Register A Out

2-15

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

MULTADDSUM sysDSP Element

In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-

plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/

subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction

are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-17 shows

the MULTADDSUM sysDSP element.

Figure 2-17. MULTADDSUM

Shift Register B In

Shift Register A In

m

Multiplicand A0

m

CLK (CLK0,CLK1,CLK2,CLK3)

CE (CE0,CE1,CE2,CE3)

m

n

Multiplier B0

n

Multiplier

Input Data

Register A

m

n

RST(RST0,RST1,RST2,RST3)

m+n

(default)

n

x

Input Data

Register B

Pipeline

Register

m

Add/Sub0

n

Multiplicand A1

Multiplier B1

m

m+n

(default)

m

n

Multiplier

Input Data

Register A

n

m+n+1

n

x

Input Data

Register B

SUM

Pipeline

Register

Output

Multiplicand A2

Multiplier B2

m

m+n+2

n

Multiplier

m

n

Input Data

Register A

m+n

(default)

n

x

m+n+1

Input Data

Register B

Pipeline

Register

m

Add/Sub1

n

Multiplicand A3

Multiplier B3

m

m+n

(default)

m

n

Multiplier

Input Data

Register A

m

n

x

Input Data

Register B

Pipeline

Register

m

n

Signed

Addn0

Addn1

Input

Register

Pipeline

Register

To Multiplier

To Add/Sub0

To Add/Sub1

Input

Register

Pipeline

Register

Input

Register

Pipeline

Register

Shift Register B Out

Shift Register A Out

Clock, Clock Enable and Reset Resources

Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset

and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)

one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and

2-16

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)

at each input register, pipeline register and output register.

Signed and Unsigned with Different Widths

The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For

unsigned operands, unused upper data bits should be ﬁlled to create a valid x9, x18 or x36 operand. For signed

two’s complement operands, sign extension of the most signiﬁcant bit should be performed until x9, x18 or x36

width is reached. Table 2-8 provides an example of this.

Table 2-8. An Example of Sign Extension

Unsigned

9-bit

Unsigned

18-bit

Two’s Complement

Signed 9-Bits

Two’s Complement

Signed 18-bits

Number Unsigned

Signed

0101

+5

-6

0101

0110

00000101

00000110

00000000 00000101

00000000 00000110

00000101

11111010

00000000 00000101

11111111 11111010

1010

OVERFLOW Flag from MAC

The sysDSP block provides an overﬂow output to indicate that the accumulator has overﬂowed. When two

unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and

overﬂow signal is indicated. When two positive numbers are added with a negative sum and when two negative

numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an overﬂow

signal is indicated. Note when overﬂow occurs the overﬂow ﬂag is present for only one cycle. By counting these

overﬂow pulses in FPGA logic, larger accumulators can be constructed. The conditions overﬂow signal for signed

and unsigned operands are listed in Figure 2-18.

Figure 2-18. Accumulator Overﬂow/Underﬂow Conditions

00000011

00000010

00000001

00000000

3

2

1

01111100

01111101

01111110

01111111

10000000

10000001

10000010

124

125

126

127

128

129

Carry signal is generated for

one cycle when this

0

boundary is crossed

11111111

11111110

11111101

255

254

253

130

Unsigned Operation

00000011

+3

+2

+1

0

-1

-2

-3

01111100

124

125

126

00000010

00000001

00000000

11111111

11111110

11111101

01111101

01111110

01111111

Overflow signal is generated

for one cycle when this

boundary is crossed

127

10000000

10000001

10000010

-128

-127

-126

Signed Operation

2-17

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

ispLEVER Module Manager

The user can access the sysDSP block via the ispLEVER Module Manager, which has options to conﬁgure each

DSP module (or group of modules) or through direct HDL instantiation. Additionally Lattice has partnered Math-

works to support instantiation in the Simulink tool, which is a Graphical Simulation Environment. Simulink works

with ispLEVER and dramatically shortens the DSP design cycle in Lattice FPGAs.

Optimized DSP Functions

Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Cor-

relators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo

Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available

DSP IPs.

Resources Available in the LatticeECP Family

Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP family. Table 2-10 shows

the maximum available EBR RAM Blocks in each of the LatticeECP family. EBR blocks, together with Distributed

RAM can be used to store variables locally for the fast DSP operations.

Table 2-9. Number of DSP Blocks in LatticeECP Family

Device

LFECP6

LFECP10

LFECP15

LFECP20

LFECP40

DSP Block

9x9 Multiplier

18x18 Multiplier

36x36 Multiplier

4

5

32

40

48

56

80

16

20

24

28

40

4

5

6

7

10

Table 2-10. Embedded SRAM in LatticeECP family

Total EBR SRAM

(Kbits)

Device

LFECP6

LFECP10

LFECP15

LFECP20

LFECP40

EBR SRAM Block

10

30

38

46

70

92

276

350

424

645

DSP Performance of the LatticeECP Family

Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of

the LatticeECP family.

Table 2-11. DSP Block performance of LatticeECP Family

DSP Performance

Device

LFECP6

LFECP10

LFECP15

LFECP20

LFECP40

DSP Block

MMAC

4

5

6

7

10

For further information on the sysDSP block, please see details of additional technical information at the end of this

data sheet.

2-18

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Programmable I/O Cells (PIC)

Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as

shown in Figure 2-19. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO

buffer, and receives input from the buffer.

Figure 2-19. PIC Diagram

PIO A

TD

D0

D1

TD

OPOS1

ONEG1

IOLT0

DDRCLK

Tristate

Register Block

(2 Flip Flops)

PADA

"T"

D0

D1

OPOS0

ONEG0

DDRCLK

IOLD0

Output

Register Block

(2 Flip Flops)

sysIO

Buffer

INCK

INDD

INFF

IPOS0

IPOS1

INCK

INDD

INFF

IPOS0

IPOS1

DI

Control

Muxes

Input

Register Block

(5 Flip Flops)

CLKO

CEO

LSR

CLK

CE

LSR

GSRN

GSR

CLKI

CEI

DQS

DDRCLKPOL

PADB

"C"

PIO B

Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-20.

The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device

can be conﬁgured as LVDS transmit/receive pairs.

One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds

the DQS bus which spans the set of 16 PIOs.The DQS signal from the bus is used to strobe the DDR data from the

memory into input register blocks. This interface is designed for memories that support one DQS strobe per eight

bits of data.

2-19

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Table 2-12. PIO Signal List

Name

Type

Description

CE0, CE1

CLK0, CLK1

LSR

Control from the core

Control from routing

Input to the core

Clock enables for input and output block FFs.

System clocks for input and output blocks.

Local Set/Reset.

GSRN

Global Set/Reset (active low).

INCK

Input to Primary Clock Network or PLL reference inputs.

DQS signal from logic (routing) to PIO.

DQS

Input to PIO

INDD

Input to the core

Unregistered data input to core.

INFF

Input to the core

Registered input on positive edge of the clock (CLK0).

DDRX registered inputs to the core.

IPOS0, IPOS1

ONEG0

OPOS0,

OPOS1 ONEG1

TD

Input to the core

Control from the core

Tristate control from the core

Output signals from the core for SDR and DDR operation.

Output signals from the core for DDR operation

Signals to Tristate Register block for DDR operation.

Tristate signal from the core used in SDR operation.

DDRCLKPOL

Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block.

Figure 2-20. DQS Routing

PADA "T"

LVDS Pair

PIO A

PIO B

PIO A

PADB "C"

PADA "T"

LVDS Pair

PADB "C"

PIO B

PIO A

PADA "T"

LVDS Pair

PADB "C"

PIO B

PIO A

PADA "T"

LVDS Pair

PADB "C"

PIO B

PIO A

PADA "T"

LVDS Pair

PADB "C"

PIO B

PIO A

Assigned

DQS Pin

PADA "T"

sysIO

Buffer

DQS

Delay

LVDS Pair

PADB "C"

PIO B

PIO A

PADA "T"

LVDS Pair

PADB "C"

PIO B

PIO A

PIO B

PADA "T"

LVDS Pair

PADB "C"

PIO

The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic

block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along

with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-

nals are also included in these blocks.

2-20

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Input Register Block

The input register block contains delay elements and registers that can be used to condition signals before they are

passed to the device core. Figure 2-21 shows the diagram of the input register block.

Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can

bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and

in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal ﬁrst

passes through an optional delay block. This delay, if selected, reduces input-register hold-time requirement when

using a global clock.

The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the

registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used

to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.

These two data streams are synchronized with the system clock before entering the core. Further discussion on

this topic is in the DDR Memory section of this data sheet.

Figure 2-22 shows the input register waveforms for DDR operation and Figure 2-23 shows the design tool primi-

tives. The SDR/SYNC registers have reset and clock enable available.

The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-

quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,

see the DDR Memory section of this data sheet.

Figure 2-21. Input Register Diagram

DI

(From sysIO

Buffer)

INCK

INDD

Delay Block

Fixed Delay

SDR & Sync

Registers

DDR Registers

D0

D2

To Routing

Q

D

Q

D

IPOS0

IPOS1

D-Type

/LATCH

D-Type

D1

Q

D

Q

D

D-Type

/LATCH

D-Type

DQS Delayed

(From DQS

Bus)

CLK0

(From Routing)

DDRCLKPOL

(From DDR

Polarity Control Bus)

2-21

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-22. Input Register DDR Waveforms

DI

F

A

B

C

D

E

(In DDR Mode)

DQS

Delayed

B

A

D

C

D0

D2

Figure 2-23. INDDRXB Primative

D

ECLK

QA

QB

LSR

SCLK

IDDRXB

CE

DDRCLKPOL

2-22

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Output Register Block

The output register block provides the ability to register signals from the core of the device before they are passed

to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for

DDR operation. Figure 2-24 shows the diagram of the Output Register Block.

In SDR mode, ONEG0 feeds one of the ﬂip-ﬂops that then feeds the output. The ﬂip-ﬂop can be conﬁgured a D-

type or latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is

latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).

Figure 2-25 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.

The additional register for DDR operation does not have reset or clock enable available.

Figure 2-24. Output Register Block

OUTDDN

Q

D

D-Type

/LATCH

ONEG0

0

1

DO

0

1

From

To sysIO

Buffer

Routing

OPOS0

Q

D

Latch

LE*

CLK1

Programmed

Control

*Latch is transparent when input is low.

Figure 2-25. ODDRXB Primative

DA

DB

ODDRXB

Q

CLK

LSR

2-23

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Tristate Register Block

The tristate register block provides the ability to register tri-state control signals from the core of the device before

they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for

DDR operation. Figure 2-26 shows the diagram of the Tristate Register Block.

In SDR mode, ONEG1 feeds one of the ﬂip-ﬂops that then feeds the output. The ﬂip-ﬂop can be conﬁgured a D-

type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is

latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).

Figure 2-26. Tristate Register Block

TD

OUTDDN

Q

D

D-Type

/LATCH

ONEG1

0

1

TO

0

1

From

Routing

To sysIO

Buffer

OPOS1

Q

D

Latch

LE*

CLK1

Programmed

Control

*Latch is transparent when input is low.

Control Logic Block

The control logic block allows the selection and modiﬁcation of control signals for use in the PIO block. A clock is

selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from

the programmable DQS pin. The clock can optionally be inverted.

The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate

signal is passed through this block.

DDR Memory Support

Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input

(for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the EC devices

provide this capability. In addition to these registers, the EC devices contain two elements to simplify the design of

input structures for read operations: the DQS delay block and polarity control logic.

DLL Calibrated DQS Delay Block

Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at

the input register. For most interfaces a PLL is used for this adjustment, however in DDR memories the clock

(referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the

required clock alignment for DDR memory interfaces.

2-24

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS rout-

ing resource. The DQS signal also feeds polarity control logic which controls the polarity of the clock to the sync

registers in the input register blocks. Figures 2-27 and 2-28 show how the DQS transition signals are routed to the

PIOs.

The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration

(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of

the device as shown in Figure 2-28. The DLL loop is compensated for temperature, voltage and process variations

by the system clock and feedback loop.

Figure 2-27. DQS Local Bus.

PIO

Delay

Control

Bus

DDR

Datain

PAD

sysIO

Buffer

Input

Register Block

( 5 Flip Flops)

Polarity

Control

Bus

To Sync.

Reg.

DI

GSR

CLKI

CEI

DQS

Bus

To DDR

Reg.

DQS

PIO

DQS

Strobe

PAD

sysIO

Buffer

Polarity Control

Logic

DI

DQS

DQSDEL

Calibration Bus

from DLL

2-25

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-28. DLL Calibration Bus and DQS/DQS Transition Distribution

Delay Control Bus

Polarity Control Bus

DQS Bus

DLL

Polarity Control Logic

In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the

internal system Clock (during the READ cycle) is unknown.

The LatticeECP/EC family contains dedicated circuits to transfer data between these domains. To prevent setup

and hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is

used. This changes the edge on which the data is registered in the synchronizing registers in the input register

block. This requires evaluation at the start of each READ cycle for the correct clock polarity.

Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device

drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to

control the polarity of the clock to the synchronizing registers.

sysIO Buffer

Each I/O is associated with a ﬂexible buffer referred to as a sysIO buffer. These buffers are arranged around the

periphery of the device in eight groups referred to as Banks. The sysIO buffers allow users to implement the wide

variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.

sysIO Buffer Banks

LatticeECP/EC devices have eight sysIO buffer banks; each is capable of supporting multiple I/O standards. Each

sysIO bank has its own I/O supply voltage (V

), and two voltage references V

and V

resources allow-

CCIO

REF1

REF2

ing each bank to be completely independent from each other. Figure 2-29 shows the eight banks and their associ-

ated supplies.

In the LatticeECP/EC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-

X) are powered using V

LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as ﬁxed threshold

CCIO.

2-26

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

input independent of V

In addition to the bank V

supplies, the LatticeECP/EC devices have a V core logic

CCIO.

CCIO CC

power supply, and a V

supply that power all differential and referenced buffers.

CCAUX

Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-

enced input buffers. In the LatticeECP/EC devices, some dedicated I/O pins in a bank can be conﬁgured to be a

reference voltage supply pin. Each I/O is individually conﬁgurable based on the bank’s supply and reference volt-

ages.

Figure 2-29. LatticeECP/EC Banks

Bank 0

Bank 1

V_CCIO7

V_CCIO2

V_REF1(2)

V_REF2(2)

GND

V_REF1(7)

V_REF2(7)

GND

V_CCIO6

V_CCIO3

V_REF1(6)

V_REF2(6)

V_REF1(3)

V_REF2(3)

GND

M

Bank 5

Bank 4

Note: N and M are the maximum number of I/Os per bank.

2-27

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LatticeECP/EC devices contain two types of sysIO buffer pairs.

1. Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)

The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and

two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be

conﬁgured as a differential input.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

Only the I/Os on the top and bottom banks have PCI clamp.

2. Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)

The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two

sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-

enced input buffer can also be conﬁgured as a differential input. In these banks the two pads in the pair are

described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,

and the comp (complementary) pad is associated with the negative side of the differential I/O.

Only the left and right banks have LVDS differential output drivers.

Supported Standards

The LatticeECP/EC sysIO buffer supports both single-ended and differential standards. Single-ended standards

can be further subdivided into LVCMOS, LVTTL and other standards.The buffers support the LVTTL, LVCMOS 1.2,

1.5, 1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually conﬁgurable

options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain.

Other single-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS,

BLVDS, LVPECL, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/O standards (together

with their supply and reference voltages) supported by the LatticeECP/EC devices. For further information on utiliz-

ing the sysIO buffer to support a variety of standards please see the details of additional technical information at

the end of this data sheet.

2-28

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Table 2-13. Supported Input Standards

Input Standard

Single Ended Interfaces

LVTTL

LVCMOS33²

LVCMOS25²

V

(Nom.)

V

¹(Nom.)

CCIO

REF

—

LVCMOS18

1.8

1.5

—

LVCMOS15

LVCMOS12²

PCI

3.3

—

HSTL18 Class I, II

HSTL18 Class III

HSTL15 Class I

0.9

1.08

0.75

0.9

—

HSTL15 Class III

SSTL3 Class I, II

SSTL2 Class I, II

SSTL18 Class I

—

1.5

—

1.25

0.9

—

Differential Interfaces

Differential SSTL18 Class I

Differential SSTL2 Class I, II

Differential SSTL3 Class I, II

Differential HSTL15 Class I, III

Differential HSTL18 Class I, II, III

LVDS, LVPECL

—

BLVDS

1. When not speciﬁed V

can be set anywhere in the valid operating range.

CCIO

2. JTAG inputs do not have a ﬁxed threshold option and always follow V

CCJ.

2-29

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Table 2-14. Supported Output Standards

Output Standard

Single-ended Interfaces

LVTTL

Drive

V

(Nom.)

CCIO

4mA, 8mA, 12mA, 16mA, 20mA

3.3

LVCMOS33

4mA, 8mA, 12mA 16mA, 20mA

3.3

2.5

1.8

1.5

1.2

—

LVCMOS25

4mA, 8mA, 12mA, 16mA, 20mA

LVCMOS18

4mA, 8mA, 12mA, 16mA

LVCMOS15

4mA, 8mA

LVCMOS12

2mA, 6mA

LVCMOS33, Open Drain

LVCMOS25, Open Drain

LVCMOS18, Open Drain

LVCMOS15, Open Drain

LVCMOS12, Open Drain

PCI33

4mA, 8mA, 12mA 16mA, 20mA

—

4mA, 8mA, 12mA 16mA

—

4mA, 8mA

2mA, 6mA

N/A

—

3.3

1.8

1.5

3.3

2.5

1.8

HSTL18 Class I, II, III

HSTL15 Class I, III

SSTL3 Class I, II

N/A

SSTL2 Class I, II

N/A

SSTL18 Class I

N/A

Differential Interfaces

Differential SSTL3, Class I, II

Differential SSTL2, Class I, II

Differential SSTL18, Class I

Differential HSTL18, Class I, II, III

Differential HSTL15, Class I, III

LVDS

N/A

3.3

2.5

1.8

1.5

2.5

3.3

BLVDS¹

LVPECL¹

1. Emulated with external resistors.

Hot Socketing

The LatticeECP/EC devices have been carefully designed to ensure predictable behavior during power-up and

power-down. Power supplies can be sequenced in any order. During power up and power-down sequences, the

I/Os remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition,

leakage into I/O pins is controlled to within speciﬁed limits, this allows for easy integration with the rest of the

system. These capabilities make the LatticeECP/EC ideal for many multiple power supply and hot-swap applica-

tions.

2-30

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Conﬁguration and Testing

The following section describes the conﬁguration and testing features of the LatticeECP/EC family of devices.

IEEE 1149.1-Compliant Boundary Scan Testability

All LatticeECP/EC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test

access port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a

serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to

be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veriﬁcation.The test

access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage

V

and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.

CCJ

For more details on boundary scan test, please see information regarding additional technical documentation at

the end of this data sheet.

Device Conﬁguration

All LatticeECP/EC devices contain two possible ports that can be used for device conﬁguration. The test access

port (TAP), which supports bit-wide conﬁguration, and the sysCONFIG port that supports both byte-wide and serial

conﬁguration.

The TAP supports both the IEEE Std. 1149.1 Boundary Scan speciﬁcation and the IEEE Std. 1532 In-System Con-

ﬁguration speciﬁcation. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins and

the rest being dual-use pins. When sysCONFIG mode is not used, these dual-use pins are available for general

purpose I/O. There are four conﬁguration options for LatticeECP/EC devices:

1. Industry standard SPI memories.

2. Industry standard byte wide ﬂash and ispMACH 4000 for control/addressing.

3. Conﬁguration from system microprocessor via the conﬁguration bus or TAP.

4. Industry standard FPGA board memory.

On power-up, the FPGA SRAM is ready to be conﬁgured with the sysCONFIG port active. The IEEE 1149.1 serial

mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a

conﬁguration port is selected, that port is locked and another conﬁguration port cannot be activated until the next

power-up sequence.

For more information on device conﬁguration, please see details of additional technical documentation at the end

of this data sheet.

Internal Logic Analyzer Capability (ispTRACY)

All LatticeECP/EC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide

capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace

memory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at com-

pile time.

For more information on ispTRACY, please see information regarding additional technical documentation at the

end of this data sheet.

External Resistor

LatticeECP/EC devices require a single external, 10K ohm +/- 1% value between the XRES pin and ground.

Device conﬁguration will not be completed if this resistor is missing. There is no boundary scan register on the

external resistor pad.

2-31

Architecture

Lattice Semiconductor

Oscillator

LatticeECP/EC Family Data Sheet

Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master serial clock for con-

ﬁguration. The oscillator and the master serial clock run continuously. The default value of the master serial clock is

2.5MHz. Table 2-15 lists all the available Master Serial Clock frequencies. When a different Master Serial Clock is

selected during the design process, the following sequence takes place:

1. User selects a different Master Serial Clock frequency.

2. During conﬁguration the device starts with the default (2.5MHz) Master Serial Clock frequency.

3. The clock conﬁguration settings are contained in the early conﬁguration bit stream.

4. The Master Serial Clock frequency changes to the selected frequency once the clock conﬁguration bits are

received.

For further information on the use of this oscillator for conﬁguration, please see details of additional technical docu-

mentation at the end of this data sheet.

Table 2-15. Selectable Master Serial Clock (CCLK) Frequencies During Conﬁguration

CCLK (MHz)

2.5*

4.3

13

15

20

26

30

34

41

45

51

55

60

130

—

5.4

6.9

8.1

9.2

10.0

—

Density Shifting

The LatticeECP/EC family has been designed to ensure that different density devices in the same package have

the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration

from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design

targeted for a high-density device to a lower density device. However, the exact details of the ﬁnal resource utiliza-

tion will impact the likely success in each case.

2-32

LatticeECP/EC Family Data Sheet

DC and Switching Characteristics

June 2004

Advance Data Sheet

Absolute Maximum Ratings^{1, 2, 3}

Supply Voltage V . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V

CC

Supply Voltage V

. . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V

CCAUX

. . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V

CCJ

Output Supply Voltage V

. . . . . . . . . . . . . . . . -0.5 to 3.75V

CCIO

Input Voltage Applied⁴. . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.25V

I/O Tristate Voltage Applied ⁴. . . . . . . . . . . . . . . . . -0.5 to 3.75V

Storage Temperature (Ambient) . . . . . . . . . . . . . . -65 to 150°C

Junction Temp. (Tj) +125°C

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Overshoot and undershoot of -2V to (V

+ 2) volts is permitted for a duration of <20ns.

IHMAX

Recommended Operating Conditions

Symbol

Parameter

Min.

1.14

3.135

1.140

0

Max.

1.26

Units

V

Core Supply Voltage

CC

Auxiliary Supply Voltage

I/O Driver Supply Voltage

3.465

+85

V

CCAUX

1, 2

CCIO

V

1

Supply Voltage for IEEE 1149.1 Test Access Port

Junction Commercial Operation

V

CCJ

t

°C

JCOM

JIND

Junction Industrial Operation

-40

100

1. If V

or V

is set to 1.2V, they must be connected to the same power supply as V

If V

or V

is set to 3.3V, they must be con-

CCIO

CCJ

CC.

CCIO

CCJ

nected to the same power supply as V

.

CCAUX

2. See recommended voltages by I/O standard in subsequent table.

Hot Socketing Speciﬁcations^{1, 2, 3, 4}

Symbol

Parameter

Condition

Min.

Typ.

Max

Units

I

Input or I/O leakage Current

0 ≤ V ≤ V (MAX)

—

+/-1000

µA

DK

IN

IH

1. Insensitive to sequence of V

V

and V

. However, assumes monotonic rise/fall rates for V

V

and V

CC, CCAUX

CCIO

CC, CCAUX CCIO.

2. 0 ≤ V ≤ V (MAX), 0 ≤ V

≤ V

(MAX) or 0 ≤ V

≤ V

(MAX).

CC

CCIO

CCAUX

3. I is additive to I

I

or I

.

DK

PU, PW

BH

4. LVCMOS and LVTTL only.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

3-1

DC and Switching_01

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

- 0.2V)

CCIO

Min.

—

Typ.

—

Max.

10

Units

µA

V

0 ≤ V ≤ (V

IN

1

I

Input or I/O Low leakage

IL, IH

(V

- 0.2V) ≤ V ≤ 3.6V

—

40

CCIO

IN

CCIO

I

I/O Active Pull-up Current

0 ≤ V ≤ 0.7 V

30

150

-150

—

PU

IN

I/O Active Pull-down Current

Bus Hold Low sustaining current

Bus Hold High sustaining current

V

(MAX) ≤ V ≤ V (MAX)

-30

30

PD

IL

IN

IH

= V (MAX)

BHLS

BHHS

BHLO

BHLH

IN

IL

= 0.7V

-30

—

CCIO

Bus Hold Low Overdrive current 0 ≤ V ≤ V (MAX)

150

-150

IN

IH

Bus Hold High Overdrive current 0 ≤ V ≤ V (MAX)

—

IN

IH

V

Bus Hold trip Points

I/O Capacitance²

0 ≤ V ≤ V (MAX)

V

(MAX)

V

(MIN)

IH

BHT

IN

IH

IL

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

CCIO

C1

C2

—

8

6

—

pf

= 1.2V, V = 0 to V (MAX)

CC

IO

IH

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

Dedicated Input Capacitance²

—

CCIO

= 1.2V, V = 0 to V (MAX)

CC

IO

IH

1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tri-stated. It is not measured

with the output driver active. Bus maintenance circuits are disabled.

2. T 25°C, f = 1.0MHz

A

Supply Current (Standby)^{1, 2, 3}

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Typ.

Max.

Units

mA

LFEC1

LFEC3

LFEC6/LFECP6

LFEC10/LFECP10

LFEC15/LFECP15

LFEC20/LFECP20

LFEC40/LFECP40

LFEC1

I

Core Power Supply Current

CC

60

LFEC3

LFEC6/LFECP6

LFEC10/LFECP10

LFEC15/LFECP15

LFEC20/LFECP20

LFEC40/LFECP40

LFEC1, LFEC3, LFEC6, LFECP6

I

Auxiliary Power Supply Current

CCAUX

15

LFEC10, LFEC15, LFEC20, LFEC40,

LFECP10, LFECP15, LFECP20,

LFECP40

PLL Power Supply

CCPLL

mA

I

Bank Power Supply Current

15

1

mA

CCIO

CCJ

V

Power Supply Current

CCJ

1. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.

2. Assumes all outputs are tristated, all inputs are conﬁgured as LVCMOS and held at the V

or GND.

CCIO

3. Frequency 0MHz.

3-2

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

Initialization Supply Current¹

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Typ.

Max.

Units

mA

LFEC1

LFEC3

LFEC6/LFECP6

LFEC10/LFECP10

LFEC15/LFECP15

LFEC20/LFECP20

LFEC40/LFECP40

LFEC1

I

Core Power Supply Current

CC

LFEC3

LFEC6/LFECP6

LFEC10/LFECP10

LFEC15/LFECP15

LFEC20/LFECP20

LFEC40/LFECP40

LFEC1, LFEC3, LFEC6, LFECP6

I

Auxiliary Power Supply Current

CCAUX

LFEC10, LFEC15, LFEC20, LFEC40,

LFECP10, LFECP15, LFECP20,

LFECP40

PLL Power Supply

CCPLL

mA

I

Bank Power Supply Current

mA

CCIO

V

Power Supply Current

CCJ

1. Until DONE signal is active.

sysIO Recommended Operating Conditions

V

(V)

REF

CCIO

Standard

LVCMOS 3.3

Min.

3.135

2.375

1.71

Typ.

3.3

2.5

1.8

1.5

1.2

3.3

2.5

3.3

1.5

1.8

2.5

3.3

2.5

Max.

3.465

2.625

1.89

Min.

—

Typ.

—

Max.

—

LVCMOS 2.5

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

LVTTL

—

1.425

1.14

1.575

1.26

—

3.135

1.71

3.465

1.89

—

PCI

—

SSTL18 Class I

SSTL2 Class I, II

SSTL3 Class I, II

HSTL15 Class I

HSTL15 Class III

HSTL 18 Class I, II

HSTL 18 Class III

LVDS

1.15

1.3

0.68

—

1.25

1.5

0.75

0.9

1.08

—

1.35

1.7

0.9

—

2.375

3.135

1.425

1.71

2.625

3.465

1.575

1.89

—

1.71

1.89

—

2.375

3.135

2.375

3.625

3.465

2.625

—

LVPECL¹

BLVDS¹

—

1. Inputs on chip. Outputs are implemented with the addition of external resisters.

3-3

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

sysIO Single-Ended DC Electrical Characteristics

V

IH

1

IL

Input/Output

Standard

V

Max.

(V)

V

Min.

(V)

I

OH

OL

OH

OL

Min. (V) Max. (V)

Min. (V)

Max. (V)

(mA)

20, 16, 12,

8, 4

-20, -16, -12,

-8, -4

0.4

0.2

0.4

0.2

0.4

V

- 0.4

- 0.2

- 0.4

- 0.2

- 0.4

- 0.2

CCIO

LVCMOS 3.3

LVTTL

-0.3

0.8

0.7

2.0

1.7

3.6

0.1

-0.1

20, 16, 12,

8, 4

-20, -16, -12,

-8, -4

3.6

0.1

-0.1

20, 16, 12,

8, 4

-20, -16, -12,

-8, -4

LVCMOS 2.5

0.2

0.4

0.2

0.4

0.2

0.4

0.2

V

0.1

-0.1

-16, -12, -8, -4

-0.1

CCIO

- 0.4 16, 12, 8, 4

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

-0.3

0.35V

0.65V

3.6

CCIO

- 0.2

- 0.4

- 0.2

- 0.4

- 0.2

0.1

8, 4

0.1

6, 2

0.1

1.5

8

-8, -4

-0.1

0.35V

0.65V

CCIO

-6, -2

-0.1

0.35V

0.65V

CC

PCI

-0.3

0.3V

0.5V

3.6

0.1V

0.9V

-0.5

CCIO

SSTL3 class I

SSTL3 class II

SSTL2 class I

SSTL2 class II

SSTL18 class I

HSTL15 class I

HSTL15 class III

HSTL18 class I

HSTL18 class II

HSTL18 class III

V

- 0.2

V

+ 0.2

0.7

V

- 1.1

- 0.9

- 0.62

- 0.43

- 0.4

-8

REF

CCIO

V

- 0.2

- 0.18

V

+ 0.2

+ 0.18

+ 0.125

0.5

0.54

0.35

0.4

V

16

-16

V

7.6

15.2

6.7

8

-7.6

REF

CCIO

-15.2

-6.7

V

- 0.125 V

V

REF

CCIO

V

- 0.1

V

+ 0.1

0.4

V

-8

REF

0.4

V

24

-8

0.4

9.6

16

-9.6

0.4

-16

0.4

24

-8

1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as

shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or

between the last GND in a bank and the end of a bank.

3-4

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

sysIO Differential Electrical Characteristics

LVDS

Over Recommended Operating Conditions

Parameter

Symbol

Parameter Description

Input voltage

Test Conditions

Min.

0

Typ.

—

Max.

2.4

Units

V

INP, INM

Differential input threshold

Input common mode voltage

Input current

+/-100

—

mV

V

THD

100mV ≤ V

V

/2

1.2

—

1.8

THD

V

200mV ≤ V

350mV ≤ V

1.9

V

CM

2.0

V

THD

I

Power on or power off

R = 100 Ohm

—

+/-10

1.60

—

µA

V

IN

V

Output high voltage for V or V

—

1.38

1.03

350

OH

OL

OD

OP

OM

T

Output low voltage for V or V

R = 100 Ohm

0.9V

250

V

OP

OM

T

Output voltage differential

(V - V ), R = 100 Ohm

450

mV

OP

OM

T

Change in V between high and

low

OD

∆V

—

50

mV

OD

V

Output voltage offset

(V - V )/2, R = 100 Ohm

1.125

—

1.25

—

1.375

50

V

OS

OP

OM

T

∆V

Change in V between H and L

mV

OS

V

= 0V Driver outputs

OD

I

Output short circuit current

—

6

mA

OSD

shorted

3-5

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

Differential HSTL and SSTL

Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-

able single-ended output classes (class I and class II) are supported in this mode.

BLVDS

The LatticeECP/EC devices support BLVDS standard. This standard is emulated using complementary LVCMOS

outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when

multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-1 is one

possible solution for bi-directional multi-point differential signals.

Figure 3-1. BLVDS Multi-point Output Example

Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential

2.5V

80

45-90 ohms

80

. . .

+

-

+

-

2.5V

Table 3-1. BLVDS DC Conditions¹

Over Recommended Operating Conditions

Typical

Parameter

Description

Output impedance

Zo = 45 Zo = 90

Units

ohm

V

Z

100

45

100

90

OUT

R

Left end termination

Right end termination

Output high voltage

TLEFT

TRIGHT

OH

45

90

V

1.375

1.125

0.25

1.25

11.2

1.48

1.02

0.46

1.25

10.2

Output low voltage

V

OL

Output differential voltage

Output common mode voltage

DC output current

V

OD

V

CM

I

mA

DC

1. For input buffer, see LVDS table.

3-6

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

LVPECL

The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complemen-

tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in

Figure 3-2 is one possible solution for point-to-point signals.

Figure 3-2. Differential LVPECL

3.3V

100 ohms

+

~150 ohms

100 ohms

3.3V

-

100 ohms

Off-chip

Transmission line, Zo = 100 ohm differential

Table 3-2. LVPECL DC Conditions¹

Over Recommended Operating Conditions

Parameter

Description

Output impedance

Typical

100

Units

ohm

V

Z

OUT

R

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

150

P

100

T

V

2.03

1.27

0.76

1.65

85.7

12.7

OH

OL

OD

CM

BACK

V

Output differential voltage

Output common mode voltage

Back impedance

V

Z

ohm

mA

I

DC output current

DC

1. For input buffer, see LVDS table.

For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni-

cal information at the end of this data sheet.

3-7

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

RSDS

The LatticeECP/EC devices support differential RSDS standard. This standard is emulated using complementary

LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-3

is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for

RSDS operation. Resistor values in Figure 3-3 are industry standard values for 1% resistors.

Figure 3-3. RSDS (Reduced Swing Differential Standard)

VCCIO = 2.5V

294

Zo = 100

+

VCCIO = 2.5V

121

100

-

294

On-chip

Off-chip

Emulated

RSDS Buffer

Table 3-3. RSDS DC Conditions

Parameter

Description

Typical

Units

ohm

V

Z

Output impedance

OUT

R

Driver series resistor

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

S

P

T

V

OH

OL

OD

CM

BACK

V

Output differential voltage

Output common mode voltage

Back impedance

V

Z

ohm

mA

I

DC output current

DC

5V Tolerant Input Buffer

The input buffers of the LatticeECP/EC family of devices can support 5V signals by using a PCI Clamp and an

external series resistor as shown in Figure 3-4. A suitable resistor can be selected by using the PCI Clamp Charac-

teristic as shown in Figure 3-5.

Figure 3-4. 5 V Tolerant Input Buffer

3.3V

5V Signals from

Legacy Systems

External

Resistor

3-8

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

Figure 3-5. Typical PCI Clamp Current

400

350

300

250

200

150

100

50

0

1

2

3

4

5

6

7

8

Voltage (V)

3-9

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

Typical Building Block Function Performance

Pin-to-Pin Performance (LVCMOS25 12mA Drive)

Function

Basic Functions

-5 Timing

Units

16-bit decoder

6.8

7.8

8.4

5.7

5.9

6.5

6.9

5.3

ns

32-bit decoder

64-bit decoder

4:1 MUX

8:1 MUX

16:1 MUX

32:1 MUX

Combinatorial (pin to LUT to pin)

Embedded Memory Functions

Pin to EBR input register setup

EBR output clock to pin

Distributed PFU RAM

Pin to PFU RAM register setup

PFU RAM clock to pin

0.0

ns

11.3

0.0

6.8

ns

Register-to-Register Performance

Function

Basic Functions

16-bit decoder

-5 Timing

Units

263

230

211

500

375

360

373

314

251

146

360

280

180

125

MHz

32-bit decoder

64-bit decoder

4:1 MUX

8:1 MUX

16:1 MUX

32:1 MUX

8-bit adder

16-bit adder

64-bit adder

16-bit counter

32-bit counter

64-bit counter

64-bit accumulator

Embedded Memory Functions

256x36 Single Port RAM

512x18 True-Dual Port RAM

Distributed Memory Functions

16x2 Single Port RAM

64x2 Single Port RAM

128x4 Single Port RAM

32x2 Pseudo-Dual Port RAM

64x4 Pseudo-Dual Port RAM

305

308

MHz

455

244

196

341

303

MHz

3-10

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

Register-to-Register Performance (Continued)

Function

-5 Timing

Units

DSP Function

9x9 Pipelined Multiply/Accumulate¹

18x18 Pipelined Multiply/Accumulate¹

36x36 Pipelined Multiply¹

265

226

177

MHz

1. Applies to LatticeECP devices only.

Derating Timing Tables

Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case

numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be

much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and

voltage multiply the noted numbers with the derating factors provided below.

The junction temperature for the FPGA depends on the power dissipation by the device, the package thermal char-

acteristics (Θ ), and the ambient temperature, as calculated with the following equation:

JA

T

= T

+ (Power * Θ )

JMAX

AMAX JA

The user must determine this temperature and then use it to determine the derating factor based on the following

derating tables: T °C.

J

Table 3-4. Delay Derating Table for Internal Blocks

Power Supply Voltage

1.2V 1.26V

T °C

Commercial

T °C

Industrial

J

1.14V

—

-40

-25

0

15

25

40

85

100

115

125

—

100

110

125

3-11

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

LatticeECP/EC External Switching Characteristics

Over Recommended Operating Conditions

-5

-4

-3

Parameter

Description

Device

Min. Max. Min. Max. Min. Max. Units

General I/O Pin Parameters (Using Primary Clock without PLL)¹

t

Clock to Output - PIO Output Register

Clock to Data Setup - PIO Input Register

Clock to Data Hold - PIO Input Register

LFEC20

—

6.75

—

-

8.43

—

11.25

—

ns

CO

SU

H

0.00

2.55

0.00

3.19

0.00

4.25

—

Clock to Data Setup - PIO Input Register

with data input delay

t

f

LFEC20

2.85

0.00

—

3.42

0.00

—

3.99

0.00

—

ns

SU_DEL

H_DEL

Clock to Data Hold - PIO Input Register

with Input Data Delay

Clock Frequency of I/O and PFU

Register

Mhz

MAX_IO

DDR I/O Pin Parameters²

t

f

Data Valid Before DQS (DDR Read)

Data Valid After DQS (DDR Read)

Data Skew (DDR Write)

LFEC20

—

ps

DVBDQ

—

DVADQ

—

ps

DQ_SK

DQS Jitter (DDR Write)

ps

DQS_JIT

DDR Clock Frequency

166

MHz

MAX_DDR

1. General timing numbers based on LVCMOS2.5V, 12 mA.

2. DDR timing numbers based on SSTL I/O.

3-12

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

LatticeECP/EC Internal Timing Parameters¹

Over Recommended Operating Conditions

-5

-4

-3

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

PFU/PFF Logic Mode Timing

t

LUT4 delay (A to D inputs to F output)

LUT6 delay (A to D inputs to OFX output)

Set/Reset to output of PFU

—

0.25

0.55

0.81

—

0.31

0.66

0.98

—

0.36

0.77

1.14

—

ns

LUT4_PFU

LUT6_PFU

LSR_PFU

SUM_PFU

HM_PFU

—

Clock to Mux (M0,M1) input setup time

Clock to Mux (M0,M1) input hold time

Clock to D input setup time

0.08

-0.06

0.09

-0.04

0.10

-0.07

0.10

-0.04

0.11

-0.08

0.12

-0.05

—

SUD_PFU

HD_PFU

Clock to D input hold time

—

-

—

Clock to Q delay, D-type register conﬁgura-

tion

t

—

0.43

0.54

0.50

—

0.51

0.65

0.60

—

0.60

0.76

0.69

ns

CK2Q_PFU

LE2Q_PFU

LD2Q_PFU

Clock to Q delay latch conﬁguration

D to Q throughput delay when latch is

enabled

PFU Memory Mode Timing

t

Clock to Output

—

0.43

—

0.51

—

0.60

—

ns

CORAM_PFU

SUDATA_PFU

HDATA_PFU

Data Setup Time

-0.25

-0.06

-0.66

-0.27

-0.30

-0.21

-0.30

-0.07

-0.79

-0.33

-0.36

-0.25

-0.34

-0.08

-0.92

-0.38

-0.42

-0.29

Data Hold Time

—

Address Setup Time

Address Hold Time

—

SUADDR_PFU

HADDR_PFU

SUWREN_PFU

HWREN_PFU

—

Write/Read Enable Setup Time

Write/Read Enable Hold Time

—

PIC Timing

PIO Input/Output Buffer Timing

t

Input Buffer Delay

Output Buffer Delay

—

ns

IN_PIO

OUT_PIO

IOLOGIC Input/Output Timing

Input Register Setup Time (Data Before

Clock)

t

—

0.12

—

0.14

—

0.17

ns

SUI_PIO

t

Input Register Hold Time (Data after Clock)

Output Register Clock to Output Delay

Input Register Clock Enable Setup Time

Input Register Clock Enable Hold Time

Set/Reset Setup Time

—

-0.09

0.75

-0.02

0.12

0.24

-0.10

—

-0.11

0.90

-0.02

0.14

0.29

-0.12

—

-0.13

1.05

-0.03

0.17

0.34

-0.14

ns

HI_PIO

COO_PIO

SUCE_PIO

HCE_PIO

SULSR_PIO

HLSR_PIO

—

0.10

-0.24

0.12

-0.29

0.14

-0.34

Set/Reset Hold Time

EBR Timing

t

Clock to output from Address or Data

Clock to output from EBR output Register

Setup Data to EBR Memory

—

3.80

—

4.55

—

5.31

ns

CO_EBR

—

COO_EBR

tS

-0.34

0.37

-0.34

0.37

-0.22

—

-0.41

0.44

-0.41

0.45

-0.26

—

-0.48

0.52

-0.48

0.52

-0.30

—

UDATA_EBR

HDATA_EBR

t

Hold Data to EBR Memory

Setup Address to EBR Memory

Hold Address to EBR Memory

SUADDR_EBR

HADDR_EBR

SUWREN_EBR

Setup Write/Read Enable to PFU Memory

3-13

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

LatticeECP/EC Internal Timing Parameters¹(Continued)

Over Recommended Operating Conditions

-5

-4

-3

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

t

Hold Write/Read Enable to PFU Memory

0.23

—

0.28

—

0.33

—

ns

HWREN_EBR

Clock Enable Setup Time to EBR Output

Register

0.18

-0.17

—

0.21

-0.20

—

0.25

-0.24

—

ns

SUCE_EBR

HCE_EBR

RSTO_EBR

Clock Enable Hold Time to EBR Output

Register

t

Reset To Output Delay Time from EBR Out-

put Register

1.47

1.76

2.05

PLL Parameters

t

Reset Recovery to Rising Clock

Reset Signal Setup Time

Reset Signal Pulse Width

—

1

—

1

—

1

ns

RSTREC

RSTSU

RSTW

—

1.8

DSP Block Timing²

t

Input Register Setup Time

Input Register Hold Time

—

ns

SUI_DSP

HI_DSP

Pipeline Register Setup Time

Pipeline Register Hold Time

Output Register Setup Time

Output Register Hold Time

Input Register Clock to Output Time

Pipeline Register Clock to Output Time

Output Register Clock to Output Time

Overﬂow Register Clock to Output Time

AdSub Setup Time

SUP_DSP

HP_DSP

SUO_DSP

HO_DSP

COI_DSP

COP_DSP

COO_DSP

COOVRFL_DSP

SUADSUB

HADSUB

AdSub Hold Time

Sign Setup Time

SUSIGN

Sign Hold Time

HSIGN

Accumulator Load Setup Time

Accumulator Load Hold Time

SUACCSLOAD

HACCSLOAD

1. Internal parameters are characterized but not tested on every device.

2. These parameters apply to LatticeECP devices only.

3-14

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

Timing Diagrams

PFU Timing Diagrams

Figure 3-6. Slice Single/Dual Port Write Cycle Timing

CK

WRE

AD

AD[3:0]

D

DI[1:0]

DO[1:0]

Old Data

D

Figure 3-7. Slice Single /Dual Port Read Cycle Timing

WRE

AD

AD[3:0]

DO[1:0]

Old Data

D

3-15

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

EBR Memory Timing Diagrams

Figure 3-8. Read/Write Mode (Normal)

CLKA

CSA

WEA

ADA

DIA

A0

A1

D1

A0

A1

A0

t_SUt_H

D0

t_ACCESS

D0

D1

DOA

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.

Figure 3-9. Read/Write Mode with Input and Output Registers

CLKA

CSA

WEA

ADA

DIA

A1

A0

A1

D1

A0

t

H

SU

D0

D1

DOA

D0

Mem(n) data from previous read

D0

DOA

t

ACCESS

DOA (Regs)

D1

D0

Mem(n) data from previous read

output is only updated during a read cycle

3-16

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

Figure 3-10. Read Before Write (SP Read/Write on Port A, Input Registers Only)

CLKA

CSA

WEA

ADA

A0

A1

D1

A0

A1

A0

t

H

SU

D2

D3

D1

D0

DIA

t

ACCESS

old A0 Data

old A1 Data

D0

D1

DOA

D2

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.

Figure 3-11. Write Through (SP Read/Write On Port A, Input Registers Only)

CLKA

CSA

WEA

Three consecutive writes to A0

ADA

A0

A1

D1

A0

t

H

SU

D2

D3

D2

D4

D0

DIA

t

ACCESS

Data from Prev Read

or Write

D0

D1

D3

DOA

D4

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.

3-17

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

LatticeECP/EC Family Timing Adders¹

Over Recommended Operating Conditions

Buffer Type

Input Adjusters

Description

-5

-4

-3

Units

LVDS25

LVDS

0.41

0.50

0.41

0.37

0.40

0.37

0.46

0.39

0.43

0.38

0.40

0.37

0.07

0.00

0.07

0.24

1.27

0.07

0.50

0.60

0.49

0.44

0.48

0.44

0.55

0.47

0.51

0.45

0.48

0.44

0.09

0.00

0.09

0.29

1.52

0.09

0.58

0.70

0.57

0.52

0.56

0.51

0.64

0.55

0.60

0.53

0.56

0.51

0.10

0.00

0.10

0.33

1.77

0.10

ns

BLVDS25

BLVDS

LVPECL

LVPECL33

HSTL18_I

HSTL18_II

HSTL18_III

HSTL18D_I

HSTL18D_II

HSTL18D_III

HSTL15_I

HSTL15_III

HSTL15D_I

HSTL15D_III

SSTL33_I

HSTL_18 class I

HSTL_18 class II

HSTL_18 class III

Differential HSTL 18 class I

Differential HSTL 18 class II

Differential HSTL 18 class III

HSTL_15 class I

HSTL_15 class III

Differential HSTL 15 class I

Differential HSTL 15 class III

SSTL_3 class I

SSTL33_II

SSTL33D_I

SSTL33D_II

SSTL25_I

SSTL_3 class II

Differential SSTL_3 class I

Differential SSTL_3 class II

SSTL_2 class I

SSTL25_II

SSTL25D_I

SSTL25D_II

SSTL18_I

SSTL_2 class II

Differential SSTL_2 class I

Differential SSTL_2 class II

SSTL_18 class I

SSTL18D_I

LVTTL33

Differential SSTL_18 class I

LVTTL

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

PCI33

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

PCI

Output Adjusters

LVDS25E

LVDS 2.5 E

ns

LVDS25

LVDS 2.5

BLVDS25

BLVDS 2.5

LVPECL33

HSTL18_I

HSTL18_II

HSTL18_III

HSTL18D_I

HSTL18D_II

HSTL18D_III

HSTL15_I

LVPECL 3.3

HSTL_18 class I

HSTL_18 class II

HSTL_18 class III

Differential HSTL 18 class I

Differential HSTL 18 class II

Differential HSTL 18 class III

HSTL_15 class I

3-18

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

LatticeECP/EC Family Timing Adders¹(Continued)

Over Recommended Operating Conditions

Buffer Type

HSTL15_II

Description

HSTL_15 class II

-5

-4

-3

Units

ns

HSTL15_III

HSTL_15 class III

HSTL15D_I

Differential HSTL 15 class I

Differential HSTL 15 class III

SSTL_3 class I

HSTL15D_III

SSTL33_I

SSTL33_II

SSTL_3 class II

SSTL33D_I

Differential SSTL_3 class I

Differential SSTL_3 class II

SSTL_2 class I

SSTL33D_II

SSTL25_I

SSTL25_II

SSTL_2 class II

SSTL25D_I

Differential SSTL_2 class I

Differential SSTL_2 class II

SSTL_1.8 class I

SSTL25D_II

SSTL18_I

SSTL18D_I

Differential SSTL_1.8 class I

LVTTL 4mA drive

LVTTL33_4mA

LVTTL33_8mA

LVTTL33_12mA

LVTTL33_16mA

LVTTL33_20mA

LVCMOS33_4mA

LVCMOS33_8mA

LVCMOS33_12mA

LVCMOS33_16mA

LVCMOS33_20mA

LVCMOS25_4mA

LVCMOS25_8mA

LVCMOS25_12mA

LVCMOS25_16mA

LVCMOS25_20mA

LVCMOS18_4mA

LVCMOS18_8mA

LVCMOS18_12mA

LVCMOS18_16mA

LVCMOS15_4mA

LVCMOS15_8mA

LVCMOS12_2mA

LVCMOS12_6mA

LVCMOS12_4mA

PCI33

LVTTL 8mA drive

LVTTL 12mA drive

LVTTL 16mA drive

LVTTL 20mA drive

LVCMOS 3.3 4mA drive

LVCMOS 3.3 8mA drive

LVCMOS 3.3 12mA drive

LVCMOS 3.3 16mA drive

LVCMOS 3.3 20mA drive

LVCMOS 2.5 4mA drive

LVCMOS 2.5 8mA drive

LVCMOS 2.5 12mA drive

LVCMOS 2.5 16mA drive

LVCMOS 2.5 20mA drive

LVCMOS 1.8 4mA drive

LVCMOS 1.8 8mA drive

LVCMOS 1.8 12mA drive

LVCMOS 1.8 16mA drive

LVCMOS 1.5 4mA drive

LVCMOS 1.5 8mA drive

LVCMOS 1.2 2mA drive

LVCMOS 1.2 6mA drive

LVCMOS 1.2 4mA drive

PCI33

0.00

1. Timing adders are characterized but not tested on every device.

3-19

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

sysCLOCK PLL Timing

Parameter

Over Recommended Operating Conditions

Descriptions

Conditions

Min.

33

Max.

420

210

840

—

Units

MHz

f

Input Clock Frequency (CLKI, CLKFB)

Output Clock Frequency (CLKOP, CLKOS)

K-Divider Output Frequency (CLKOK)

PLL VCO Frequency

IN

33

OUT

OUT2

VCO

PFD

0.258

420

33

Phase Detector Input Frequency

AC Characteristics

t

Output Clock Duty Cycle

Output Clock Period Jitter

default duty cycle selected

45

—

55

+/- 100

0.02

+/- 200

—

%

ps

DT

f

≥ 100MHz

OUT

t

OPJIT

< 100MHz

—

UIPP

ps

t

Input Clock to Output Clock Skew

Output Clock Pulse Width

PLL Lock-in Time

Divider ratio = integer

At 90% or 10%

—

SK

1

ns

W

1

—

150

us

LOCK

Programmable Delay Unit

Input Clock Rise/Fall Time

Input Clock Period Jitter

Input Clock High Time

100

—

400

ps

PA

t /t

10% to 90%

1

ns

R F

t

—

+/- 200

—

ps

IPJIT

HI

90% to 90%

10% to 10%

0.5

ns

Input Clock Low Time

—

ns

LO

1. Output clock is valid after t

for PLL reset and dynamic delay adjustment.

LOCK

3-20

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

LatticeECP/EC sysCONFIG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Parameter

Description

Min.

Typ. Max.

Units

sysCONFIG Byte Data Flow

t

Byte D[0:7] Setup Time to CCLK

12

0

—

ns

SUCBDI

HCBDI

CODO

SUCS

HCS

Byte D[0:7] Hold Time to CCLK

Clock to Dout in Flowthrough Mode

CS[0:1] Setup Time to CCLK

CS[0:1] Hold Time to CCLK

—

12

0

—

Write Signal Setup Time to CCLK

Write Signal Hold Time to CCLK

CCLK to BUSY Delay Time

SUWD

HWD

—

12

DCB

Clock to Out for Read Data

CORD

sysCONFIG Byte Slave Clocking

t

Byte Slave Clock Minimum High Pulse

Byte Slave Clock Minimum Low Pulse

Byte Slave Clock Cycle Time

6

—

ns

BSCH

BSCL

12

5

BSCYC

SUSCDI

HSCDI

CODO

Din Setup time to CCLK Slave Mode

Din Hold Time to CCLK Slave Mode

Clock to Dout in Flowthrough Mode

0

—

12

sysCONFIG Serial (Bit) Data Flow

t

Din Setup Time to CCLK Master Mode

Din Hold Time to CCLK Master Mode

5

0

—

ns

SUMCDI

HMCDI

sysCONFIG Serial Slave Clocking

t

Serial Slave Clock Minimum High Pulse

Serial Slave Clock Minimum Low Pulse

6

—

ns

SSCH

SSCL

sysCONFIG POR, Initialization and Wake Up

t

Initialization time of Internal CONFIG Circuit

Time from t to valid Master Clock

—

5

ms

ICFG

5

us

VMC

ICFG

Program Pin Pulse Rejection

10

25

ns

PRGMRJ

PRGM

DINIT

Low time to Start Conﬁguration

—

ns

INIT Delay Time

ns

Delay Time from Program Low to INIT Low

Delay Time from Program Low to Done Low

User I/O Disable

—

ns

DPPINIT

DINITD

IODISS

IOENSS

MWC

37

ns

User I/O Enabled Time from GOE Being Released During Wake-up

Additional Wake Master Clock Signals After Done Pin High

128

Typical cycle

sysCONFIG SPI Port

t

Init High to Clock Low

—

80

2

ns

CFGX

Init High to CSSPIN Low

Clock Low to CSSPIN Low

Clock Low to Output Valid

Data Setup Time

CSSPI

CSCCLK

SOCDO

SOSU

SOE

0

15

5

—

CSSPIN Active Setup Time

CSSPIN Low to First Clock Edge Setup Time

0

400

CSPID

3-21

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

LatticeECP/EC sysCONFIG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Clock Mode

Master Clock

Min.

Typ.

Max.

Units

5MHz

10MHz

15MHz

20MHz

25MHz

30MHz

35MHz

40MHz

45MHz

50MHz

55MHz

60MHz

Duty Cycle

3.78

7

5.4

10

15

20

26

30

34

41

45

51

55

60

—

7.02

13

MHz

%

10.5

14

19.5

26

18.2

21

33.8

39

23.8

28.7

31.5

35.7

38.5

42

44.2

53.3

58.5

66.3

71.5

78

40

60

3-22

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

JTAG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Symbol

Parameter

Min.

—

40

20

8

Max.

25

—

Units

MHz

ns

f

t

TCK Clock Frequency

MAX

TCK [BSCAN] clock pulse width

BTCP

TCK [BSCAN] clock pulse width high

—

ns

BTCPH

BTCPL

BTS

TCK [BSCAN] clock pulse width low

—

ns

TCK [BSCAN] setup time

—

ns

TCK [BSCAN] hold time

10

50

—

8

—

ns

BTH

TCK [BSCAN] rise/fall time

—

mV/ns

ns

BTRF

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to valid disable

TAP controller falling edge of clock to valid enalbe

BSCAN test capture register setup time

BSCAN test capture register hold time

10

—

BTCO

ns

BTCODIS

BTCOEN

BTCRS

BTCRH

BUTCO

BTUODIS

BTUPOEN

ns

10

—

ns

BSCAN test update register, falling edge of clock to valid output

BSCAN test update register, falling edge of clock to valid disable

BSCAN test update register, falling edge of clock to valid enable

25

ns

3-23

DC and Switching Characteristics

LatticeECP/EC Family Data Sheet

Lattice Semiconductor

Switching Test Conditions

Figure 3-12 shows the output test load that is used for AC testing. The speciﬁc values for resistance, capacitance,

voltage, and other test conditions are shown in Figure 3-5.

Figure 3-12. Output Test Load, LVTTL and LVCMOS Standards

V_T

R1

DUT

Test Point

CL*

*CL Includes Test Fixture and Probe Capacitance

Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

R

C

Timing Ref.

V

T

1

L

LVCMOS 3.3 = 1.5V

—

LVCMOS 2.5 = V

LVCMOS 1.8 = V

LVCMOS 1.5 = V

LVCMOS 1.2 = V

/2

CCIO

LVTTL and other LVCMOS settings (L -> H, H -> L)

0pF

∞

LVCMOS 2.5 I/O (Z -> H)

LVCMOS 2.5 I/O (Z -> L)

LVCMOS 2.5 I/O (H -> Z)

LVCMOS 2.5 I/O (L -> Z)

V

/2

V

OL

CCIO

V

OH

188

0pF

- 0.15

+ 0.15

V

OL

OH

OL

V

OH

Note: Output test conditions for all other interfaces are determined by the respective standards.

3-24

LatticeECP/EC Family Data Sheet

Pinout Information

June 2004

Advance Data Sheet

Signal Descriptions

Signal Name

I/O

Descriptions

General Purpose

[Edge] indicates the edge of the device on which the pad is located. Valid

edge designations are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PFU row or the column of the device on

which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify

Row Number. When Edge is L (Left) or R (Right), only need to specify Col-

umn Number.

[A/B] indicates the PIO within the PIC to which the pad is connected.

P[Edge] [Row/Column Number*]_[A/B]

I/O

Some of these user-programmable pins are shared with special function

pins. These pin when not used as special purpose pins can be programmed

as I/Os for user logic.

During conﬁguration the user-programmable I/Os are tri-stated with an inter-

nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-

age pin), it is also tri-stated with an internal pull-up resistor enabled after

conﬁguration.

GSRN

NC

I

Global RESET signal (active low). Any I/O pin can be GSRN.

No connect.

—

GND

Ground. Dedicated pins.

V

Power supply pins for core logic. Dedicated pins.

CC

Auxiliary power supply pin. It powers all the differential and referenced input

buffers. Dedicated pins.

—

CCAUX

CCIOx

Power supply pins for I/O bank x. Dedicated pins.

Reference supply pins for I/O bank x. Pre-determined pins in each bank are

V

REF1(x), REF2(x)

as assigned V

inputs. When not used, they may be used as I/O pins.

REF

XRES

10K ohm +/-1% resistor must be connected between this pad and ground.

PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)

Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

[LOC][num]_PLL[T, C]_IN_A

[LOC][num]_PLL[T, C]_FB_A

PCLK[T, C]_[n:0]_[3:0]

I

Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A,B,C...at each side.

Primary Clock pads, T = true and C = complement, n per side, indexed by

bank and 0,1,2,3 within bank.

DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball

function number. Any pad can be conﬁgured to be output.

[LOC]DQS[num]

Test and Programming (Dedicated pins)

Test Mode Select input, used to control the 1149.1 state machine. Pull-up is

enabled during conﬁguration.

TMS

I

Test Clock input pin, used to clock the 1149.1 state machine. No pull-up

enabled.

TCK

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

4-1

Pinout Information_01

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Signal Descriptions (Cont.)

Signal Name

I/O

Descriptions

Test Data in pin. Used to load data into device using 1149.1 state machine.

After power-up, this TAP port can be activated for conﬁguration by sending

appropriate command. (Note: once a conﬁguration port is selected it is

locked. Another conﬁguration port cannot be selected until the power-up

sequence). Pull-up is enabled during conﬁguration.

TDI

I

TDO

O

Output pin. Test Data out pin used to shift data out of device using 1149.1.

V

—

V

- The power supply pin for JTAG Test Access Port.

CCJ

Conﬁguration Pads (used during sysCONFIG)

Mode pins used to specify conﬁguration modes values latched on rising edge

of INITN. During conﬁguration, a pull-up is enabled. These are dedicated

pins.

CFG[2:0]

I

Open Drain pin. Indicates the FPGA is ready to be conﬁgured. During conﬁg-

uration, a pull-up is enabled. It is a dedicated pin.

INITN

I/O

I

Initiates conﬁguration sequence when asserted low. This pin always has an

active pull-up. This is a dedicated pin.

PROGRAMN

DONE

Open Drain pin. Indicates that the conﬁguration sequence is complete, and

the startup sequence is in progress. This is a dedicated pin.

I/O

CCLK

BUSY

I/O Conﬁguration Clock for conﬁguring an FPGA in sysCONFIG mode.

I/O Generally not used.

sysCONFIG chip select (Active low). During conﬁguration, a pull-up is

enabled.

CSN

I

sysCONFIG chip select (Active Low). During conﬁguration, a pull-up is

enabled.

CS1N

I

WRITEN

D[7:0]

I

Write Data on Parallel port (Active low).

I/O sysCONFIG Port Data I/O.

Output for serial conﬁguration data (rising edge of CCLK) when using

sysCONFIG port.

DOUT, CSON

DI

O

Input for serial conﬁguration data (clocked with CCLK) when using sysCON-

FIG port. During conﬁguration, a pull-up is enabled.

I

4-2

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Pin Information Summary

Package

Pin Type

484 fpBGA

360

672 fpBGA

Single Ended User I/O

Differential Pair User I/O

400

200

12

56

5

180

12

56

5

Dedicated

Muxed

Conﬁguration

TAP

Dedicated (total without supplies)

V

20

12

4

32

20

6

CC

CCAUX

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

4

6

4

6

4

6

V

CCIO

4

6

4

6

4

6

4

6

GND

NC

44

3

63

96

64

48

40

48

64

48

40

1

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

48

40

44

48

44

40

1

Single Ended/

Differential I/O

per Bank

V

CCJ

Note: During conﬁguration the user-programmable I/Os are tri-stated with an inter-

nal pull-up resistor enabled. If any pin is not used (or not bonded to a package pin),

it is also tri-stated with an internal pull-up resistor enabled after conﬁguration.

4-3

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Power Supply and NC Connections

Signals

VCC

484 fpBGA

672 fpBGA

J6, J7, J16, J17, K6, K7, K16, K17, L6, L17, M6, M17, H8, H9, H10, H11, H16, H17, H18, H19, J9, J18, K8,

N6, N7, N16, N17, P6, P7, P16, P17

K19, L8, L19, M19, N7, R7, R20, T19, U8, U19, V8,

V18, V9, W8, W9, W10, W11, W16, W17, W18, W19

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCJ

G11, H9, H10, H11

G12, H12, H13, H14

J15, K15, L15, L16

M15, M16, N15, P15

R12, R13, R14, T12

R9, R10, R11, T11

M7, M8, N8, P8

J8, K8, L7, L8

H12, H13, J10, J11, J12, J13

H14, H15, J14, J15, J16, J17

K17, K18, L18, M18, N18, N19

P18, P19, R18, R19, T18, U18

V14, V15, V16, V17, W14, W15

V10, V11, V12, V13, W12, W13

P8, P9, R8, R9, T9, U9

K9, L9, M8, M9, N8, N9

U6

U2

VCCAUX

G7, G8, G15, G16, H7, H16, R7, R16, T7, T8, T15,

T16

G13,H7, H20, J8, J19, K7, L20, M7, M20, N20, P7,

P20, T7, T8, T20, V7, V19, W20, Y7, Y13

GND

A1, A22, AB1, AB22, H8, H15, J9, J10, J11, J12, J13, K10, K11, K12, K13, K14, K15, K16, L10, L11, L12,

J14, K9, K10, K11, K12, K13, K14, L9, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14,

L13, L14, M9, M10, M11, M12, M13, M14, N9, N10, M15, M16, M17, N10, N11, N12, N13, N14, N15,

N11, N12, N13, N14, P9, P10, P11, P12, P13, P14, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17,

R8, R15

R10, R11, R12, R13, R14, R15, R16, R17, T10, T11,

T12, T13, T14, T15, T16, T17, U10, U11, U12, U13,

U14, U15, U16, U17

NC

A2, A21, AB2

A25, B2, B23, B24, B25, B26, C2, C3, C19, C20,

C21, C22, C23, C24, D3, D5, D20, D21, D22, D24,

E5, E19, E21, E22, E24, E25, E26, F4, F5, F20, F22,

F23, F24, F26, G5, G20, G26, H2, H3, H5, H6, H22,

J2, J3, J7, J21, J22, J23, W5, W7, Y5, Y6, Y19, Y20,

Y21, Y22, Y23, Y24, AA2, AA3, AA4, AA5, AA21,

AA22, AA23, AA24, AB3, AB5, AB19, AB20, AB21,

AB22, AB23, AB24, AC2, AC3, AC19, AC20, AC21,

AC22, AD1, AD2, AD3, AD19, AD20, AD21, AD22,

AD23, AD24, AD25, AD26, AE1, AE24, AE25, AE26,

AF25

4-4

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA

Ball Function

Bank

7

6

LVDS

Dual Function

484 fpBGA

D4

E4

C3

B2

E5

F5

672 fpBGA

E3

E4

B1

C1

F3

PL2A

T

VREF2_7

PL2B

C

T

VREF1_7

PL3A

PL3B

C

T

PL4A

PL4B

C

T

G3

D2

E2

D1

E1

F2

PL5A

D3

C2

F4

PL5B

C

T

PL6A

LDQS6

PL6B

C

T

G4

E3

D2

B1

C1

F3

PL7A

PL7B

C

T

G2

F6

PL8A

LUM0_PLLT_IN_A

LUM0_PLLC_IN_A

LUM0_PLLT_FB_A

LUM0_PLLC_FB_A

PL8B

C

T

G6

H4

G4

J4

PL9A

PL9B

C

T

E2

G5

H6

G3

H4

J5

PL11A

PL11B

PL12A

PL12B

PL13A

PL13B

PL14A

PL14B

PL15A

PL15B

PL16A

PL16B

PL17A

PL17B

PL18A

PL18B

PL19A

PL19B

PL20A

PL20B

PL21A

PL21B

PL22A

PL22B

XRES

PL24A

PL24B

C

T

J5

K4

K5

J6

C

T

C

T

H5

F2

K6

F1

C

T

F1

G1

H1

J1

E1

D1

H3

G2

H2

G1

J4

C

T

K2

K1

K3

L3

C

T

C

T

L2

C

T

J3

L1

LDQS19

J2

M3

M4

M1

M2

L4

C

T

H1

K4

K5

K3

K2

J1

C

T

C

T

L5

PCLKT7_0

PCLKC7_0

N2

N1

N3

P1

P2

C

K1

L3

T

L4

C

L5

4-5

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA (Cont.)

Ball Function

PL25A

PL25B

PL26A

PL26B

PL27A

PL27B

PL28A

PL28B

PL29A

PL29B

PL30A

PL30B

PL31A

PL31B

PL32A

PL32B

PL33A

PL33B

PL34A

PL34B

PL35A

PL35B

PL36A

PL36B

PL37A

PL37B

PL38A

PL38B

PL39A

PL39B

TCK

Bank

6

LVDS

Dual Function

484 fpBGA

672 fpBGA

T

L2

L7

C

T

L1

L6

M4

M5

M1

M2

N3

M3

N5

N4

N1

N2

P1

N4

N5

R1

R2

P4

C

T

C

T

LDQS28

C

T

P3

M5

M6

T1

C

T

C

T

T2

R4

R3

N6

P5

C

T

P2

R6

P5

C

T

P3

P6

C

T

P4

R5

U1

U2

T3

R1

R2

R5

R4

T1

C

T

C

T

T4

LDQS36

R6

T5

C

T

T2

R3

T3

T6

C

T

U5

U3

U4

V1

C

T

C

V2

T5

U5

T4

U7

V4

TDI

TMS

V5

TDO

U1

U2

V1

V2

U3

V3

U4

V5

W1

W2

Y1

V3

VCCJ

U6

W1

W2

V6

PL41A

PL41B

PL42A

PL42B

PL43A

PL43B

PL44A

PL44B

PL45A

T

C

T

C

T

C

T

C

T

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

LLM0_PLLT_FB_A

LLM0_PLLC_FB_A

W6

Y1

Y2

W3

W4

AA1

LDQS45

4-6

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA (Cont.)

Ball Function

PL45B

PL46A

PL46B

PL47A

PL47B

PL48A

PL48B

PB2A

Bank

6

5

LVDS

C

T

Dual Function

484 fpBGA

672 fpBGA

AB1

Y4

Y2

AA1

AA2

W4

C

T

Y3

AC1

AB2

AB4

AC4

AB6

AA6

AC7

Y8

C

T

V4

VREF1_6

VREF2_6

W3

C

T

Y3

PB2B

C

T

PB3A

PB3B

C

T

PB4A

AB7

AA7

AC6

AC5

AB8

AC8

AE2

AA8

AF2

Y9

PB4B

C

T

PB5A

PB5B

C

T

PB6A

BDQS6

PB6B

C

T

PB7A

PB7B

C

T

PB8A

PB8B

C

T

PB9A

AD5

AD4

AD8

AC9

AE3

AB9

AF3

AD9

AE4

AF4

AE5

AA9

AF5

Y10

AD6

AC10

AF6

AE6

AF7

AB10

AE7

AD10

AD7

PB9B

C

T

PB10A

PB10B

PB11A

PB11B

PB12A

PB12B

PB13A

PB13B

PB14A

PB14B

PB15A

PB15B

PB16A

PB16B

PB17A

PB17B

PB18A

PB18B

PB19A

PB19B

PB20A

V7

T6

C

T

V8

C

T

U7

W5

U6

C

T

AA3

AB3

Y6

C

T

BDQS14

C

T

V6

AA5

W6

Y5

C

T

C

T

Y4

AA4

AB4

Y7

C

T

C

T

W8

W7

U8

C

T

W9

4-7

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA (Cont.)

Ball Function

PB20B

PB21A

PB21B

PB22A

PB22B

PB23A

PB23B

PB24A

PB24B

PB25A

PB25B

PB26A

PB26B

PB27A

PB27B

PB28A

PB28B

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

PB32A

PB32B

PB33A

PB33B

PB34A

PB34B

PB35A

PB35B

PB36A

PB36B

PB37A

PB37B

PB38A

PB38B

PB39A

PB39B

PB40A

PB40B

PB41A

PB41B

PB42A

Bank

5

4

LVDS

C

T

Dual Function

484 fpBGA

672 fpBGA

AA10

AF8

U9

Y8

C

T

Y9

AF9

BDQS22

V9

AD11

Y11

C

T

T9

W10

U10

V10

AE8

C

T

AC11

AF10

AB11

AE10

AE9

C

T

T10

AA6

AB5

AA8

AA7

AB6

AB7

Y10

C

T

AA11

Y12

C

T

AE11

AF11

AF12

AE12

AD12

AC12

AA12

AB12

AE13

AF13

AD13

AC13

AF14

AE14

AA13

AB13

AD14

AA14

AC14

AB14

AF15

AE15

AD15

AC15

AF16

Y14

C

T

C

T

W11

AB8

AB9

AA10

AA9

Y11

C

T

BDQS30

C

T

C

T

AA11

V11

VREF2_5

VREF1_5

PCLKT5_0

PCLKC5_0

WRITEN

CS1N

C

T

V12

AB10

AB11

Y12

C

T

C

T

U11

W12

U12

W13

U13

AA12

AB12

T13

VREF1_4

CSN

C

T

VREF2_4

D7

C

T

D5

C

T

D6

BDQS38

D4

C

T

V13

W14

U14

Y13

C

T

D3

D2

D1

AE16

AB15

AF17

AE17

Y15

C

T

V14

AA13

AB13

AA14

C

T

4-8

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA (Cont.)

Ball Function

PB42B

PB43A

PB43B

PB44A

PB44B

PB45A

PB45B

PB46A

PB46B

PB47A

PB47B

PB48A

PB48B

PB49A

PB49B

PB50A

PB50B

PB51A

PB51B

PB52A

PB52B

PB53A

PB53B

PB54A

PB54B

PB55A

PB55B

PB56A

PB56B

PB57A

PB57B

PR48B

PR48A

PR47B

PR47A

PR46B

PR46A

PR45B

PR45A

PR44B

PR44A

PR43B

PR43A

PR42B

Bank

4

3

LVDS

C

T

Dual Function

484 fpBGA

672 fpBGA

AA15

AD17

Y16

Y14

Y15

C

T

W15

V15

AD18

AC16

AE18

AF18

AD16

AB16

AF19

AA16

AA17

Y17

C

T

T14

AB14

AB15

AB16

AA15

AB17

AA16

AB18

AA17

AB19

AA18

W16

U15

C

T

BDQS46

C

T

C

T

C

T

AF21

AF20

AE21

AC17

AF22

AB17

AE22

AA18

AE19

AE20

AA19

Y18

C

T

C

T

V16

C

T

U16

Y17

C

T

V17

AB20

AA19

Y16

C

T

BDQS54

C

T

W17

AA20

Y19

AF23

AA20

AC18

AB18

AF24

AE23

AC23

AC24

AC25

AC26

AB25

AA25

AB26

AA26

W23

C

T

Y18

C

T

W18

T17

C

T

U17

VREF2_3

VREF1_3

W20

Y20

C

T

AA21

AB21

W19

V19

C

T

C

T

Y21

RDQS45

RLM0_PLLC_IN_A

RLM0_PLLT_IN_A

RLM0_PLLC_FB_A

RLM0_PLLT_FB_A

DI

AA22

V20

C

T

U20

W24

C

T

W21

Y22

W22

W21

C

V21

Y25

4-9

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA (Cont.)

Ball Function

PR42A

PR41B

PR41A

CFG2

Bank

3

2

LVDS

Dual Function

DOUT/CSON

BUSY

484 fpBGA

W22

U21

672 fpBGA

Y26

W25

W26

V24

V21

V23

V22

V20

V25

U20

V26

U26

U24

U25

U23

U22

U21

T21

T25

T26

T22

T23

T24

R23

R25

R24

R26

P26

R21

R22

P25

P24

P23

P22

N26

M26

N21

P21

N23

N22

N25

N24

L26

T

C

T

D0

V22

T19

CFG1

U19

CFG0

U18

PROGRAMN

CCLK

V18

T20

INITN

T21

DONE

R20

PR39B

PR39A

PR38B

PR38A

PR37B

PR37A

PR36B

PR36A

PR35B

PR35A

PR34B

PR34A

PR33B

PR33A

PR32B

PR32A

PR31B

PR31A

PR30B

PR30A

PR29B

PR29A

PR28B

PR28A

PR27B

PR27A

PR26B

PR26A

PR25B

PR25A

PR24B

PR24A

PR22B

PR22A

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

T18

R17

R19

R18

U22

T22

R21

R22

P20

N20

P19

P18

P21

P22

N21

N22

N19

N18

M21

L20

L21

M20

M18

M19

M22

L22

K22

K21

J22

RDQS36

RDQS28

PCLKC2_0

PCLKT2_0

J21

K26

4-10

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA (Cont.)

Ball Function

PR21B

PR21A

PR20B

PR20A

PR19B

PR19A

PR18B

PR18A

PR17B

PR17A

PR16B

PR16A

PR15B

PR15A

PR14B

PR14A

PR13B

PR13A

PR12B

PR12A

PR11B

PR11A

PR9B

Bank

LVDS

C

T

Dual Function

484 fpBGA

H22

H21

L19

672 fpBGA

M22

M23

M25

M24

M21

L21

2

C

T

2

L18

2

C

T

K20

J20

2

RDQS19

2

C

T

K19

K18

G22

F22

L22

2

L23

2

C

T

L25

2

L24

2

C

T

F21

K25

J25

2

E22

E21

D22

G21

G20

J18

2

C

T

J26

2

H26

H25

J24

2

C

T

2

C

T

K21

K22

K20

J20

2

H19

J19

2

C

T

2

H20

H17

H18

D21

2

C

T

K23

K24

F25

2

C

RUM0_PLLC_FB_

A

PR9A

PR8B

PR8A

PR7B

PR7A

PR6B

PR6A

PR5B

PR5A

PR4B

PR4A

PR3B

PR3A

PR2B

PR2A

PT57B

PT57A

PT56B

PT56A

PT55B

2

1

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

RUM0_PLLT_FB_A

RUM0_PLLC_IN_A

RUM0_PLLT_IN_A

C22

G19

G18

F20

F19

E20

D20

C21

C20

F18

E18

B22

B21

E19

D19

G17

F17

D18

C18

C19

G25

H23

H24

H21

G21

D26

D25

F21

G22

G24

G23

C26

C25

E23

D23

A24

A23

E18

D19

F19

RDQS6

VREF1_2

VREF2_2

4-11

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA (Cont.)

Ball Function

PT55A

PT54B

PT54A

PT53B

PT53A

PT52B

PT52A

PT51B

PT51A

PT50B

PT50A

PT49B

PT49A

PT48B

PT48A

PT47B

PT47A

PT46B

PT46A

PT45B

PT45A

PT44B

PT44A

PT43B

PT43A

PT42B

PT42A

PT41B

PT41A

PT40B

PT40A

PT39B

PT39A

PT38B

PT38A

PT37B

PT37A

PT36B

PT36A

PT35B

PT35A

PT34B

PT34A

PT33B

Bank

1

0

LVDS

Dual Function

484 fpBGA

B20

D17

C16

B19

A20

E17

C17

F16

E16

F15

D16

B18

A19

B17

A18

B16

A17

B15

A16

A15

A14

G14

E15

D15

C15

C14

B14

A13

B13

E14

C13

F14

D14

E13

G13

A12

B12

F13

D13

F12

D12

F11

C12

A11

672 fpBGA

B22

G19

B21

D18

C18

F18

A22

G18

A21

E17

B17

C17

D17

F17

E20

G17

B20

E16

A20

A19

B19

D16

C16

F16

A18

G16

B18

A17

A16

D15

B16

E15

C15

F15

G15

B15

A15

E14

G14

D14

E13

F14

C14

B14

T

C

T

TDQS54

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

TDQS46

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

TDQS38

C

T

C

T

C

T

VREF2_1

VREF1_1

C

T

C

PCLKC0_0

4-12

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA (Cont.)

Ball Function

PT33A

PT32B

PT32A

PT31B

PT31A

PT30B

PT30A

PT29B

PT29A

PT28B

PT28A

PT27B

PT27A

PT26B

PT26A

PT25B

PT25A

PT24B

PT24A

PT23B

PT23A

PT22B

PT22A

PT21B

PT21A

PT20B

PT20A

PT19B

PT19A

PT18B

PT18A

PT17B

PT17A

PT16B

PT16A

PT15B

PT15A

PT14B

PT14A

PT13B

PT13A

PT12B

PT12A

PT11B

Bank

0

LVDS

Dual Function

PCLKT0_0

VREF1_0

484 fpBGA

A10

E12

E11

B11

C11

B9

672 fpBGA

A14

D13

C13

A13

B13

F13

F12

A12

B12

A11

B11

D12

C12

B10

A10

G12

A9

T

C

T

VREF2_0

C

T

C

T

TDQS30

TDQS22

TDQS14

B10

A9

C

T

A8

C

T

D11

C10

A7

C

T

A6

C

T

B7

B8

C

T

A5

B6

C

T

G10

E10

F10

D10

G9

E12

B9

C

T

F11

A8

C

T

D11

C11

B8

E9

C

T

C9

C8

B7

C

T

F9

E11

A7

D9

C

T

F8

G11

C7

D7

C

T

D8

G10

C6

C7

C

T

A4

C10

D10

F10

A6

B4

C

T

C4

C5

C

T

D6

E10

C9

B5

C

T

E6

G9

C6

D9

C

T

A3

A5

B3

A4

C

T

F6

F9

D5

B6

C

F7

E9

4-13

Pinout Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LFEC20/LFECP20 Logic Signal Connections: 484 & 672 fpBGA (Cont.)

Ball Function

PT11A

PT10B

PT10A

PT9B

Bank

LVDS

Dual Function

484 fpBGA

672 fpBGA

0

T

E8

G6

E7

C8

0

C

T

G8

B5

0

C

T

A3

PT9A

0

A2

PT8B

0

C

T

F8

PT8A

0

B4

PT7B

0

C

T

E8

PT7A

0

B3

PT6B

0

C

T

D8

PT6A

0

TDQS6

G7

C4

PT5B

0

C

T

PT5A

0

C5

PT4B

0

C

T

E7

PT4A

0

D4

PT3B

0

C

T

F7

PT3A

0

D6

PT2B

0

C

T

D7

PT2A

0

E6

4-14

LatticeECP/EC Family Data Sheet

Ordering Information

June 2004

Advance Data Sheet

Part Number Description

LFXXX XX – X – X XXXXXX X

Device Family

Grade

Lattice EC (FPGA)

C = Commercial

Lattice ECP (EC FPGA + DSP Blocks)

I = Industrial

Logic Capacity

1.5K LUTs = 1*

3K LUTs = 3*

6K LUTs = 6

Package

T100 = 100-pin TQFP*

T144 = 144-pin TQFP

Q208 = 208-pin PQFP

F256 = 256-ball fpBGA

F484 = 484-ball fpBGA

F672 = 672-ball fpBGA

F900 = 900-ball fpBGA

10K LUTs = 10

15K LUTs = 15

20K LUTs = 20

40K LUTs = 40

Supply Voltage

Speed

E = 1.2V

3 = Slowest

4

5 = Fastest

Note: Parts dual marked per table below.

*Not available in the LatticeECP Family.

Ordering Information

LatticeEC Commercial

Part Number

LFEC1E-3 Q208C

LFEC1E-4 Q208C

LFEC1E-5 Q208C

LFEC1E-3 T144C

LFEC1E-4 T144C

LFEC1E-5 T144C

LFEC1E-3 T100C

LFEC1E-4 T100C

LFEC1E-5 T100C

I/Os

112

97

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

COM

LUTs

1.5K

-4

-5

-3

97

-4

97

-5

65

-3

65

-4

65

-5

Part Number

LFEC3E-3 F256C

LFEC3E-4 F256C

LFEC3E-5 F256C

LFEC3E-3 Q208C

LFEC3E-4 Q208C

LFEC3E-5 Q208C

LFEC3E-3 T144C

I/Os

160

145

97

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

256

208

144

Temp.

COM

LUTs

3.1K

-4

-5

-3

-4

-5

-3

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

5-1

Order Info_01

Ordering Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LatticeEC Commercial (Continued)

Part Number

LFEC3E-4 T144C

LFEC3E-5 T144C

LFEC3E-3 T100C

LFEC3E-4 T100C

LFEC3E-5 T100C

LFEC6E-3 F484C

LFEC6E-4 F484C

LFEC6E-5 F484C

LFEC6E-3 F256C

LFEC6E-4 F256C

LFEC6E-5 F256C

LFEC6E-3 Q208C

LFEC6E-4 Q208C

LFEC6E-5 Q208C

LFEC6E-3 T144C

LFEC6E-4 T144C

LFEC6E-5 T144C

I/Os

97

Grade

-4

Package

TQFP

fpBGA

PQFP

TQFP

Pins

144

100

484

256

208

144

Temp.

COM

LUTs

3.1K

6.1K

97

-5

65

-3

65

-4

65

-5

224

192

145

97

-3

-4

-5

-3

-4

-5

-3

-4

-5

-3

97

-4

97

-5

Part Number

LFEC10E-3 F484C

LFEC10E-4 F484C

LFEC10E-5 F484C

LFEC10E-3 F256C

LFEC10E-4 F256C

LFEC10E-5 F256C

LFEC10E-3 Q208C

LFEC10E-4 Q208C

LFEC10E-5 Q208C

I/Os

288

192

145

Grade

-3

Package

fpBGA

PQFP

Pins

484

256

208

Temp.

COM

LUTs

10.2K

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

LFEC15E-3 F484C

LFEC15E-4 F484C

LFEC15E-5 F484C

LFEC15E-3 F256C

LFEC15E-4 F256C

LFEC15E-5 F256C

I/Os

352

192

Grade

-3

Package

fpBGA

Pins

484

256

Temp.

COM

LUTs

15.3K

-4

-5

-3

-4

-5

Part Number

LFEC20E-3 F672C

LFEC20E-4 F672C

LFEC20E-5 F672C

LFEC20E-3 F484C

LFEC20E-4 F484C

LFEC20E-5 F484C

I/Os

400

360

Grade

-3

Package

fpBGA

Pins

672

484

Temp.

COM

LUTs

19.7K

-4

-5

-3

-4

-5

5-2

Ordering Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LatticeEC Commercial (Continued)

Part Number

I/Os

Grade

Package

Pins

Temp.

LUTs

Part Number

LFEC40E-3 F900C

LFEC40E-4 F900C

LFEC40E-5 F900C

LFEC40E-3 F672C

LFEC40E-4 F672C

LFEC40E-5 F672C

I/Os

576

496

Grade

-3

Package

fpBGA

Pins

900

672

Temp.

COM

LUTs

40.9K

-4

-5

-3

-4

-5

LatticeECP Commercial

Part Number

LFECP6E-3 F484C

LFECP6E-4 F484C

LFECP6E-5 F484C

LFECP6E-3 F256C

LFECP6E-4 F256C

LFECP6E-5 F256C

LFECP6E-3 Q208C

LFECP6E-4 Q208C

LFECP6E-5 Q208C

LFECP6E-3 T144C

LFECP6E-4 T144C

LFECP6E-5 T144C

I/Os

Grade

Package

fpBGA

PQFP

TQFP

Pins

Temp.

COM

LUTs

6.1K

224

192

145

97

-3

-4

-5

-3

-4

-5

-3

-4

-5

-3

-4

-5

484

256

208

144

97

Part Number

I/Os

288

192

145

Grade

-3

Package

fpBGA

PQFP

Pins

484

256

208

Temp.

COM

LUTs

10.2K

LFECP10E-3 F484C

LFECP10E-4 F484C

LFECP10E-5 F484C

LFECP10E-3 F256C

LFECP10E-4 F256C

LFECP10E-5 F256C

LFECP10E-3 Q208C

LFECP10E-4 Q208C

LFECP10E-5 Q208C

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

I/Os

352

192

Grade

-3

Package

fpBGA

Pins

484

256

Temp.

COM

LUTs

15.3K

LFECP15E-3 F484C

LFECP15E-4 F484C

LFECP15E-5 F484C

LFECP15E-3 F256C

LFECP15E-4 F256C

LFECP15E-5 F256C

-4

-5

-3

-4

-5

5-3

Ordering Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LatticeECP Commercial (Continued)

Part Number

I/Os

Grade

-3

Package

fpBGA

Pins

676

484

Temp.

COM

LUTs

19.7K

LFECP20E-3 F676C

LFECP20E-4 F676C

LFECP20E-5 F676C

LFECP20E-3 F484C

LFECP20E-4 F484C

LFECP20E-5 F484C

400

360

-4

-5

-3

-4

-5

Part Number

I/Os

576

496

Grade

-3

Package

fpBGA

Pins

896

676

Temp.

COM

LUTs

40.9K

LFECP40E-3 F896C

LFECP40E-4 F896C

LFECP40E-5 F896C

LFECP40E-3 F676C

LFECP40E-4 F676C

LFECP40E-5 F676C

-4

-5

-3

-4

-5

LatticeEC Industrial

Part Number

LFEC1E-3 Q208I

LFEC1E-4 Q208I

LFEC1E-3 T144I

LFEC1E-4 T144I

LFEC1E-3 T100I

LFEC1E-4 T100I

I/Os

112

97

Grade

-3

Package

PQFP

TQFP

Pins

Temp.

IND

LUTs

1.5K

208

144

100

-4

-3

97

-4

65

-3

65

-4

Part Number

LFEC3E-3 F256I

LFEC3E-4 F256I

LFEC3E-3 Q208I

LFEC3E-4 Q208I

LFEC3E-3 T144I

LFEC3E-4 T144I

LFEC3E-3 T100I

LFEC3E-4 T100I

I/Os

160

145

97

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

256

208

144

100

Temp.

IND

LUTs

3.1K

-4

-3

-4

-3

97

-4

65

-3

65

-4

Part Number

LFEC6E-3 F484I

LFEC6E-4 F484I

LFEC6E-3 F256I

LFEC6E-4 F256I

LFEC6E-3 Q208I

LFEC6E-4 Q208I

LFEC6E-3 T144I

I/Os

224

192

145

97

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

484

256

208

144

Temp.

IND

LUTs

6.1K

-4

-3

-4

-3

-4

-3

5-4

Ordering Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LatticeEC Industrial (Continued)

Part Number

LFEC1E-3 Q208I

LFEC1E-4 Q208I

LFEC1E-3 T144I

LFEC1E-4 T144I

LFEC1E-3 T100I

LFEC1E-4 T100I

I/Os

112

97

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

IND

LUTs

1.5K

-4

-3

97

-4

65

-3

65

-4

Part Number

I/Os

Grade

Package

Pins

Temp.

LUTs

LFEC6E-4 T144I

97

-4

TQFP

144

IND

6.1K

Part Number

LFEC10E-3 F484I

LFEC10E-4 F484I

LFEC10E-3 F256I

LFEC10E-4 F256I

LFEC10E-3 P208I

LFEC10E-4 P208I

I/Os

288

192

145

Grade

-3

Package

fpBGA

PQFP

Pins

484

256

208

Temp.

IND

LUTs

10.2K

-4

-3

-4

-3

-4

PQFP

Part Number

LFEC15E-3 F484I

LFEC15E-4 F484I

LFEC15E-3 F256I

LFEC15E-4 F256I

I/Os

352

192

Grade

-3

Package

fpBGA

Pins

484

256

Temp.

IND

LUTs

15.3K

-4

IND

-3

IND

-4

IND

Part Number

LFEC20E-3 F672I

LFEC20E-4 F672I

LFEC20E-3 F484I

LFEC20E-4 F484I

I/Os

400

360

Grade

-3

Package

fpBGA

Pins

672

484

Temp.

IND

LUTs

19.7K

-4

IND

-3

IND

-4

IND

Part Number

LFEC40E-3 F900I

LFEC40E-4 F900I

LFEC40E-3 F672I

LFEC40E-4 F672I

I/Os

576

496

Grade

-3

Package

fpBGA

Pins

900

672

Temp.

IND

LUTs

40.9K

-4

IND

-3

IND

-4

IND

LatticeECP Industrial

Part Number

LFECP6E-3 F484I

LFECP6E-4 F484I

LFECP6E-3 F256I

LFECP6E-4 F256I

LFECP6E-3 Q208I

I/Os

Grade

Package

fpBGA

PQFP

Pins

Temp.

IND

LUTs

6.1K

224

192

145

-3

-4

-3

-4

-3

484

256

208

IND

5-5

Ordering Information

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

LatticeECP Industrial (Continued)

LFECP6E-4 Q208I

LFECP6E-3 T144I

LFECP6E-4 T144I

145

-4

-3

-4

PQFP

TQFP

208

144

IND

6.1K

97

Part Number

LFECP10E-3 F484I

LFECP10E-4 F484I

LFECP10E-3 F256I

LFECP10E-4 F256I

LFECP10E-3 Q208I

LFECP10E-4 Q208I

I/Os

288

192

145

Grade

-3

Package

fpBGA

PQFP

Pins

484

256

208

Temp.

IND

LUTs

10.2K

-4

-3

-4

-3

-4

PQFP

Part Number

LFECP15E-3 F484I

LFECP15E-4 F484I

LFECP15E-3 F256I

LFECP15E-4 F256I

I/Os

352

192

Grade

-3

Package

fpBGA

Pins

484

256

Temp.

IND

LUTs

15.3K

-4

IND

-3

IND

-4

IND

Part Number

LFECP20E-3 F676I

LFECP20E-4 F676I

LFECP20E-3 F484I

LFECP20E-4 F484I

I/Os

400

360

Grade

-3

Package

fpBGA

Pins

676

484

Temp.

IND

LUTs

19.7K

-4

IND

-3

IND

-4

IND

Part Number

LFECP40E-3 F896I

LFECP40E-4 F896I

LFECP40E-3 F676I

LFECP40E-4 F676I

I/Os

576

496

Grade

-3

Package

fpBGA

Pins

896

676

Temp.

IND

LUTs

40.9K

-4

IND

-3

IND

-4

IND

5-6

LatticeECP/EC Family Data Sheet

Supplemental Information

Advance Data Sheet

June 2004

For Further Information

A variety of technical notes for the LatticeECP/EC family are available on the Lattice web site at www.latticesemi.com.

• LatticeECP/EC sysIO Usage Guide (TN1056)

• ispTRACY Internal Logic Analyzer Guide (TN1054)

• LatticeECP/EC sysCLOCK PLL Design and Usage Guide (TN1049)

• Memory Usage Guide for LatticeECP/EC Devices (TN1051)

• LatticeECP/EC DDR Usage Guide (TN1050)

• Estimating Power Using Power Calculator for LatticeECP/EC Devices (TN1052)

• sysDSP/MAC Usage Guide (TN1057)

• LatticeECP/EC sysCONFIG Usage Guide (TN1053)

• IEEE 1149.1 Boundary Scan Testability in Lattice Devices

For further information on interface standards refer to the following web sites:

• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org

• PCI: ww.pcisig.com

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

6-1

Further Info_01


型号：	LFECP40E-4F676I
厂家：	LATTICE SEMICONDUCTOR
描述：	Field Programmable Gate Array, 5120 CLBs, PBGA676, FPBGA-676 栅可编程逻辑
文件：	总80页 (文件大小：577K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LFECP40E-4F676I [LATTICE]

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