LFSCM3GA15KLUTSEP1FF1020C

LatticeSC/M Family Data Sheet

DS1004 Version 02.1, June 2008

LatticeSC/M Family Data Sheet

Introduction

January 2008

Data Sheet DS1004

– 1 to 7.8 Mbits memory

– True Dual Port/Pseudo Dual Port/Single

Port

– Dedicated FIFO logic for all block RAM

– 500MHz performance

Features

■ High Performance FPGA Fabric

• 15K to 115K four input Look-up Tables (LUT4s)

• 139 to 942 I/Os

• 700MHz global clock; 1GHz edge clocks

• Additional 240K to 1.8Mbits distributed RAM

■ 4 to 32 High Speed SERDES and ﬂexiPCS™

(per Device)

■ sysCLOCK™ Network

• Eight analog PLLs per device

– Frequency range from 15MHz to 1GHz

– Spread spectrum support

• Performance ranging from 600Mbps to 3.8Gbps

• Excellent Rx jitter tolerance (0.8UI at

3.125Gbps)

• Low Tx jitter (0.25UI typical at 3.125Gbps)

• Built-in Pre-emphasis and equalization

• Low power (typically 105mW per channel)

• Embedded Physical Coding Sublayer (PCS)

provides pre-engineered implementation for the

following standards:

• 12 DLLs per device with direct control of I/O

delay

– Frequency range from 100MHz to 700MHz

• Extensive clocking network

– 700MHz primary and 325 MHz secondary

clocks

– 1GHz I/O-connected edge clocks

• Precision Clock Divider

– GbE, XAUI, PCI Express, SONET, Serial

RapidIO, 1G Fibre Channel, 2G Fibre Channel

– Phase matched x2 and x4 division of incom-

ing clocks

• Dynamic Clock Select (DCS)

– Glitch free clock MUX

■ 2Gbps High Performance PURESPEED™ I/O

• Supports the following performance bandwidths

– Differential I/O up to 2Gbps DDR

(1GHz Clock)

■ Masked Array for Cost Optimization

(MACO™) Blocks

– Single-ended memory interfaces up to

800Mbps

• On-chip structured ASIC Blocks provide pre-

engineered IP for low power, low cost system

level integration

• 144 Tap programmable Input Delay (INDEL)

block on every I/O dynamically aligns data to

clock for robust performance

– Dynamic bit Adaptive Input Logic (AIL) mon-

itoring and control circuitry per pin that auto-

matically ensures proper set-up and hold

■ High Performance System Bus

• Ties FPGA elements together with a standard

bus framework

– Dynamic bus: uses control bus from DLL

– Static per bit

– Connects to peripheral user interfaces for

run-time dynamic conﬁguration

• Electrical standards supported:

– LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL

– SSTL 3/2/18 I, II; HSTL 18/15 I, II

– PCI, PCI-X

– LVDS, Mini-LVDS, Bus-LVDS, MLVDS,

LVPECL, RSDS, Hypertransport

• Programmable On Die Termination (ODT)

– Includes Thevenin Equivalent and low

■ System Level Support

• IEEE standard 1149.1 Boundary Scan, plus

ispTRACY™ internal logic analyzer

• IEEE Standard 1532 in-system conﬁguration

• 1.2V and 1.0V operation

• Onboard oscillator for initialization and general

use

• Embedded PowerPC microprocessor interface

power V termination options

TT

• Low cost wire-bond and high pin count ﬂip-chip

packaging

• Low cost SPI Flash RAM conﬁguration

■ Memory Intensive FPGA

• sysMEM™ embedded Block RAM

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

1-1

DS1004 Introduction_01.6

Introduction

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Table 1-1. LatticeSC Family Selection Guide

Device

LUT4s (K)

SC15

15

SC25

25

SC40

40

SC80

80

SC115

115

424

7.8

1.84

32

sysMEM Blocks (18Kb)

Embedded Memory (Mbits)

Max. Distributed Memory (Mbits)

Number of 3.8Gbps SERDES (Max.)

DLLs

56

104

1.92

0.41

16

216

3.98

0.65

16

308

5.68

1.28

32

1.03

0.24

8

12

Analog PLLs

8

MACO Blocks

4

6

10

12

Package I/O/SERDES Combinations (1mm ball pitch)

256-ball fpBGA (17 x 17mm)

900-ball fpBGA (31 x 31mm)

1020-ball fcBGA (33 x 33mm)

1152-ball fcBGA (35 x 35mm)

1704-ball fcBGA (42.5 x 42.5mm)

139/4

300/8

378/8

476/16

562/16

604/16

660/16

904/32

660/16

942/32

Note: The information in this preliminary data sheet is by deﬁnition not ﬁnal and subject to change. Please consult the Lat-

tice website and your local Lattice sales manager to ensure you have the latest information regarding the speciﬁcations for

these products as you make critical design decisions.

The LatticeSCM devices add MACO-enabled IP functionality to the base LatticeSC devices. Table 1-2 shows the

type and number of each pre-engineered IP core.

Table 1-2. LatticeSCM Family

Device

ﬂexiMAC Blocks

SCM15

SCM25

SCM40

SCM80

SCM115

• 1GbE Mode

• 10GbE Mode

• PCI Express Mode

1

2

4

2

SPI4.2 Blocks

Memory Controller Blocks

• DDR/DDR2 DRAM Mode

• QDR II/II+ SRAM Mode

• RLDRAM I

1

2

• RLDRAM II CIO/SIO

Low Speed CDR Blocks

0

1

0

2

PCI Express LTSSM (PHY) Blocks

Note: See each IP core user’s guide for more information about support for speciﬁc LatticeSCM devices.

Introduction

The LatticeSC family of FPGA combines a high-performance FPGA fabric, high-speed SERDES, high-perfor-

mance I/Os and large embedded RAM in a single industry leading architecture. This FPGA family is fabricated in a

state of the art technology to provide one of the highest performing FPGAs in the industry.

This family of devices includes features to meet the needs of today’s communication network systems. These fea-

tures include SERDES with embedded advance PCS (Physical Coding sub-layer), up to 7.8 Mbits of sysMEM

embedded block RAM, dedicated logic to support system level standards such as RAPIDIO, HyperTransport,

SPI4.2, SFI-4, UTOPIA, XGMII and CSIX. The devices in this family feature clock multiply, divide and phase shift

PLLs, numerous DLLs and dynamic glitch free clock MUXs which are required in today’s high end system designs.

High speed, high bandwidth I/O make this family ideal for high throughput systems.

1-2

Introduction

LatticeSC/M Family Data Sheet

Lattice Semiconductor

The ispLEVER^®design tool from Lattice allows large complex designs to be efﬁciently implemented using the Lat-

ticeSC family of FPGA devices. Synthesis library support for LatticeSC is available for popular logic synthesis tools.

The ispLEVER tool uses the synthesis tool output along with the constraints from its ﬂoor planning tools to place

and route the design in the LatticeSC device. The ispLEVER tool extracts the timing from the routing and back-

annotates it into the design for timing veriﬁcation.

Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeSC family.

By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,

increasing their productivity.

Innovative high-performance FPGA architecture, high-speed SERDES with PCS support, sysMEM embedded

memory and high performance I/O are combined in the LatticeSC to provide excellent performance for today’s

leading edge systems designs. Table 1-3 details the performance of several common functions implemented within

the LatticeSC.

Table1-3. Speed Performance for Typical Functions¹

Functions

32-bit Address Decoder

Performance (MHz)²

539

517

779

353

768

369

372

375

64-bit Address Decoder

32:1 Multiplexer

64-bit Adder (ripple)

32x8 Distributed Single Port (SP) RAM

64-bit Counter (up or down counter, non-loadable)

True Dual-Port 1024x18 bits

FIFO Port A: x36 bits, B: x9 bits

1. For additional information, see Typical Building BLock Function Performance table

in this data sheet.

2. Advance information (-7 speed grade).

1-3

LatticeSC/M Family Data Sheet

Architecture

June 2008

Data Sheet DS1004

Architecture Overview

The LatticeSC architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR). The upper left and

upper right corners of the devices contain SERDES blocks and their associated PCS blocks, as show in Figure 2-1.

Top left and top right corner of the device contain blocks of SERDES. Each block of SERDES contains four chan-

nels (quad). Each channel contains a single serializer and de-serializer, synchronization and word alignment logic.

The SERDES quad connects with the Physical Coding Sub-layer (PCS) blocks that contain logic to simultaneously

perform alignment, coding, de-coding and other functions. The SERDES quad block has separate supply, ground

and reference voltage pins.

The PICs contain logic to facilitate the conditioning of signals to and from the I/O before they leave or enter the

FPGA fabric. The block provides DDR and shift register capabilities that act as a gearbox between high speed I/O

and the FPGA fabric. The blocks also contain programmable Adaptive Input Logic that adjusts the delay applied to

signals as they enter the device to optimize setup and hold times and ensure robust performance.

sysMEM EBRs are large dedicated fast memory blocks. They can be conﬁgured as RAM, ROM or FIFO. These

blocks have dedicated logic to simplify the implementation of FIFOs.

The PFU, PIC and EBR blocks are arranged in a two-dimensional grid with rows and columns as shown in

Figure 2-1. These blocks are connected with many vertical and horizontal routing channel resources. The place

and route software tool automatically allocates these routing resources.

The corners contain the sysCLOCK Analog Phase Locked Loop (PLL) and Delay Locked Loop (DLL) Blocks. The

PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the

clocks. The LatticeSC architecture provides eight analog PLLs per device and 12 DLLs. The DLLs provide a simple

delay capability and can also be used to calibrate other delays within the device.

Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG™

port which allows for serial or parallel device conﬁguration. The system bus simpliﬁes the connections of the exter-

nal microprocessor to the device for tasks such as SERDES and PCS conﬁguration or interface to the general

FPGA logic. The LatticeSC devices use 1.2V as their core voltage operation with 1.0V operation also possible.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

2-1

DS1004 Architecture_01.9

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-1. Simpliﬁed Block Diagram (Top Level)

Quad SERDES

sysCLOCK

Analog PLLs

Physical Coding

Sublayer (PCS)

sysCLOCK DLLs

Programmable

I/O Cell (PIC) includes

PURESPEED I/O Interface

Structured ASIC

Block (MACO)

Programmable

Function

Unit (PFU)

Each PIC

contains four

Programmable

I/Os (PIO)

sysMEM Embedded

Block RAM (EBR)

Three PICs

per four PFUs

sysCLOCK

Analog PLLs

sysCLOCK DLLs

2-2

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

PFU Blocks

The core of the LatticeSC devices consists of PFU blocks. The PFUs can be programmed to perform Logic, Arith-

metic, Distributed RAM and Distributed ROM functions.

Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-

tions to and from PFU blocks are from routing.There are 53 inputs and 25 outputs associated with each PFU block.

Figure 2-2. PFU Diagram

From

Routing

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

Slice 3

Slice 0

Slice 1

Slice 2

D

FF/

D

FF/

D

FF/

Latch

To

Routing

Slice

Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and

some associated logic that allows the LUTs to be combined to implement 5, 6, 7 and 8 Input LUTs (LUT5, LUT6,

LUT7 and LUT8). There is control logic to perform set/reset functions (programmable as synchronous/asynchro-

nous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic

of the slice. The registers in the slice can be conﬁgured for positive/negative and edge/level clocks.

There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).

There are seven outputs: six to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associ-

ated with each slice.

2-3

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-3. Slice Diagram

FCO from Slice/PFU,

FCI into Different Slice/PFU

Slice

OFX1

F1

A1

CO

F

B1

C1

D1

D

Q1

LUT4 &

CARRY

FF/

Latch

CI

From

Routing

To

Routing

M1

M0

OFX0

LUT

Expansion

Mux

CO

A0

B0

C0

D0

F0

LUT4 &

CARRY

F

D

OFX0

Q0

FF/

Latch

CI

Control Signals

selected and

inverted per

CE

CLK

LSR

slice in routing

FCI into Slice/PFU,

FCO from Different Slice/PFU

Note: some interslice

signals not shown.

Table 2-1. Slice Signal Descriptions

Function

Input

Type

Signal Names

Description

Data signal

A0, B0, C0, D0 Inputs to LUT4

A1, B1, C1, D1 Inputs to LUT4

Input

Data signal

Input

Multi-purpose

Control signal

Inter-PFU signal

Data signals

Inter-PFU signal

M0

M1

Multipurpose Input

Clock Enable

Input

CE

Input

LSR

Local Set/Reset

Input

CLK

System Clock

Fast Carry In¹

Input

FCI

Output

F0, F1

Q0, Q1

OFX0

OFX1

FCO

LUT4 output register bypass signals

Register Outputs

Output of a LUT5 MUX

Output of a LUT6, LUT7, LUT8²MUX depending on the slice

For the right most PFU the fast carry chain output²

1. See Figure 2-2 for connection details.

2. Requires two PFUs.

2-4

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Modes of Operation

Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. Table 2-2 lists the modes and the

capability of the Slice blocks.

Table 2-2. Slice Modes

Logic

Ripple

RAM

ROM

SPR 16x2

DPR 16x2

PFU Slice

LUT 4x2 or LUT 5x1

2-bit Arithmetic Unit

ROM 16x2

Logic Mode

In this mode, the LUTs in each Slice are conﬁgured as combinatorial lookup tables. A LUT4 can have 16 possible

input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since

there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup tables such as LUT6,

LUT7 and LUT8 can be constructed by concatenating other Slices in the PFU.

Ripple Mode

Ripple mode allows the efﬁcient implementation of small arithmetic functions. In ripple mode, the following func-

tions can be implemented by each Slice:

• Addition 2-bit

• Subtraction 2-bit

• Up counter 2-bit

• Down counter 2-bit

• Comparator functions of A and B inputs

- A greater-than-or-equal-to B

- A not-equal-to B

- A less-than-or-equal-to B

Ripple Mode includes an optional conﬁguration that performs arithmetic using fast carry chain methods. In this con-

ﬁguration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-

ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices.

RAM Mode

In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory. Through the combi-

nation of LUTs and Slices, a variety of different memories can be constructed.

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-

ware will construct these using distributed memory primitives that represent the capabilities of the Slice. Table 2-3

shows the number of Slices required to implement different distributed RAM primitives. Dual port memories involve

the pairing of two Slices, one Slice functions as the read-write port. The other companion Slice supports the read-

only port. For more information on RAM mode, please see details of additional technical documentation at the end

of this data sheet.

Table 2-3. Number of Slices Required For Implementing Distributed RAM

SPR16x2

DPR16x2

Number of Slices

1

2

Note: SPR = Single Port RAM, DPR = Dual Port RAM

ROM Mode

The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is accom-

plished through the programming interface during conﬁguration.

2-5

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

PFU Modes of Operation

Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the

functionality possible at the PFU level.

Table 2-4. PFU Modes of Operation

Logic

Ripple

RAM

ROM

LUT 4x8 or

MUX 2x1 x 8

SPR 16x2 x 4

DPR 16x2 x 2

2-bit Add x 4

ROM 16x1 x 8

LUT 5x4 or

MUX 4x1 x 4

SPR 16x4 x 2

DPR 16x4 x 1

2-bit Sub x 4

2-bit Counter x 4

2-bit Comp x 4

ROM 16x2 x 4

ROM 16x4 x 2

ROM 16x8 x1

LUT 6x2 or

MUX 8x1 x 2

SPR 16x8 x 1

LUT 7x1 or

MUX 16x1 x 1

Routing

There are many resources provided in the LatticeSC devices to route signals individually or as busses with related

control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-

ments.

The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU)

resources. The x1 and x2 connections provide fast and efﬁcient connections in horizontal, vertical and diagonal

directions. All connections are buffered to ensure high-speed operation even with long high-fanout connections.

The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the

place and route tool is completely automatic, although an interactive routing editor is available to optimize the

design.

sysCLOCK Network

The LatticeSC devices have three distinct clock networks for use in distributing high-performance clocks within the

device: primary clocks, secondary clocks and edge clocks. In addition to these dedicated clock networks, users are

free to route clocks within the device using the general purpose routing. Figure 2-4 shows the clock resources

available to each slice.

Figure 2-4. Slice Clock Selection

Primary Clock

12

Secondary Clock

6

Clock to Slice

Routing

GND

Note: GND is available to switch off the network.

Primary Clock Sources

LatticeSC devices have a wide variety of primary clock sources available. Primary clocks sources consists of the

following:

• Primary clock input pins

• Edge clock input pins

• Two outputs per DLL

2-6

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

• Two outputs per PLL

• Clock divider outputs

• Digital Clock Select (DCS) block outputs

• Three outputs per SERDES quad

Figure 2-5 shows the arrangement of the primary clock sources.

Figure 2-5. Clock Sources

Edge

Clock

PIOs

Primary/

Edge Clock

PIOs

PLL

SERDES

DCS

Clock Dividers

(3 per SERDES Channel)

DLL

(3 per SERDES Channel)

Primary/

Edge Clock

PIOs

Primary/

Edge Clock

PIOs

4

Edge Clock

PIOs

Edge Clock

PIOs

DCS

Primary Clock Sources

24

DCS

Clock

Dividers

Clock

Dividers

Primary/

Edge Clock

PIOs

Primary/

Edge Clock

PIOs

DLL

8

DLL

PLL

Clock Dividers

DCS

Edge

Clock

PIOs

Primary/

Edge Clock

PIOs

Edge

Clock

PIOs

Primary/

Edge Clock

PIOs

Primary Clock Routing

The clock routing structure in LatticeSC devices consists of 12 Primary Clock lines per quadrant. The primary

clocks are generated from 64:1 MUXs located in each quadrant. Three of the inputs to each 64:1 MUX comes from

local routing, one is connected to GND and rest of the 60 inputs are from the primary clock sources. Figure 2-6

shows this clock routing.

2-7

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-6. Per Quadrant Clock Selection

12 feedlines per quadrants times 4 + 12 feedlines from upper and lower half

60 Primary Clock Sources

From Local

Routing

From Local

Routing

From Local

Routing

60

GND

3

GND

12 Prim1a2ryPrCimloacrkypCelrocQkusadrants

Note: GND is available to switch off the network.

Secondary Clocks

In addition to the primary clock network and edge clocks the LatticeSC devices also contain a secondary clock net-

work. Built of X6 style routing elements this secondary clock network is ideal for routing slower speed clock and

control signals throughout the device preserving high-speed clock networks for the most timing critical signals.

Edge Clocks

LatticeSC devices have a number of high-speed edge clocks that are intended for use with the PIOs in the imple-

mentation of high-speed interfaces. There are eight edge clocks per bank for the top and bottom of the device. The

left and right sides have eight edge clocks per side for both banks located on that side. Figure 2-7 shows the

arrangement of edge clocks.

Edge clock resources can be driven from a variety of sources. Edge clock resources can be driven from:

• Edge clock PIOs in the same bank

• Primary clock PIOs in the same bank

• Routing

• Adjacent PLLs and DLLs

• ELSR output from the clock divider

2-8

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-7. Edge Clock Resources

Bank 1

SERDES

Edge clock

Bank 5

Bank 4

Precision Clock Divider

Each set of edge clocks has four high-speed dividers associated with it.These are intended for generating a slower

speed system clock from the high-speed edge clock. The block operates in a DIV2 or DIV4 mode and maintains a

known phase relationship between the divided down clock and high-speed clock based on the release of its reset

signal. The clock dividers can be fed from selected PIOs, PLLs and routing. The clock divider outputs serve as pri-

mary clock sources. This circuit also generates an edge local set/reset (ELSR) signal which is fed to the PIOs via

the edge clock network and is used for the rest of the I/O gearing logic.

Figure 2-8. Clock Divider Circuit

Divided clock

S/R

Clock derived

from selected

PIOs, PLLs and

routing

ELSR

LSR

Register chain to synchronize LSR to clock input

Dynamic Clock Select (DCS)

The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and

outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is

2-9

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

toggled.There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-9 illustrates the

DCS Block diagram.

Figure 2-9. DCS Block Diagram

CLK0

CLK1

SEL

DCS

DCSOUT

Figure 2-10 shows timing waveforms for one of the DCS operating modes. The DCS block can be programmed to

other modes. For more information on the DCS, please see details of additional technical documentation at the end

of this data sheet.

Figure 2-10. DCS Waveforms

CLK0

CLK1

SEL

DCSOUT

Clock Boosting

There are programmable delays available in the clock signal paths in the PFU, PIC and EBR blocks. These allow

setup and clock-to-output times to be traded to meet critical timing without slowing the system clock. If this feature

is enabled then the design tool automatically uses these delays to improve timing performance.

Global Set/Reset

There is a global set/reset (GSR) network on the device that is distributed to all FFs, PLLs, DLLs and other blocks

on the device. This GSR network can operate in two modes:

a) asynchronous - no clock is required to get into or out of the reset state.

b) synchronous - The global GSR net is synchronized to a user selected clock. In this mode it continues to be

asynchronous to get into the reset state, but is synchronous to get out of the reset state. This allows all reg-

isters on the device to become operational in the same clock period. The synchronous GSR goes out of

reset in two cycles from the clock edge where the setup time of the FF was met (not from the GSR being

released).

sysCLOCK Phase Locked Loops (PLLs)

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated

with it: input clock divider, feedback divider and two clock output dividers. The input divider is used to divide the

input clock signal, while the feedback divider is used to multiply the input clock signal.

2-10

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

The setup and hold times of the device can be improved by programming a delay in the feedback or input path of

the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-

grammed during conﬁguration or can be adjusted dynamically.

The Phase Select block can modify the phase of the clock signal if desired. The Spread Spectrum block supports

the modulation of the PLL output frequency. This reduces the peak energy in the fundamental and its harmonics

providing for lower EMI (Electro Magnetic Interference).

The sysCLOCK PLL can be conﬁgured at power-up and then, if desired, reconﬁgured dynamically through the

serial memory interface bus which connects with the on-chip system bus. For example, the user can select inputs,

loop ﬁlters, divider setting, delay settings and phase shift settings. The user can also directly access the SMI bus

through the routing.

The PLL clock input, from pin or routing, feeds into an input divider.There are four sources of feedback signal to the

feedback divider: from the clock net, directly from the voltage controlled oscillator (VCO) output, from the routing or

from an external pin. The signal from the input clock divider and the feedback divider are passed through the pro-

grammable delay before entering the phase frequency detector (PFD) unit. The output of this PFD is used to con-

trol the voltage controlled oscillator. There is a PLL_LOCK signal to indicate that VCO has locked on to the input

clock signal. Figure 2-11 shows the sysCLOCK PLL diagram.

Figure 2-11. PLL Diagram

CLKOP

CLKI

Div

Prog

Delay

Div

VCO/

Loop Filter

PFD

CLKOS

Phase

Adjust

Prog

Delay

CLKFB

Prog

Delay

Optional Internal Feedback

RSTN

From PFD

LOCK

For more information on the PLL, please see details of additional technical documentation at the end of this data

sheet.

Spread Spectrum Clocking (SSC)

The PLL supports spread spectrum clocking to reduce peak EMI by using “down-spread” modulation. The spread

spectrum operation will vary the output frequency (at 30KHz to 500KHz) in a range that is between its nominal

value, down to a frequency that is a programmable 1%, 2%, or 3% lower than normal.

Digital Locked Loop (DLLs)

In addition to PLLs, the LatticeSC devices have up to 12 DLLs per device. DLLs assist in the management of clocks

and strobes. DLLs are well suited to applications where the clock may be stopped or transferring jitter from input to

output is important, for example forward clocked interfaces. PLLs are good for applications requiring the lowest out-

put jitter or jitter ﬁltering. All DLL outputs are routed as primary/edge clock sources.

The DLL has two independent clock outputs, CLKOP and CLKOS. These outputs can individually select one of the

outputs from the tapped delay line. The CLKOS has optional ﬁne phase shift and divider blocks to allow this output

to be further modiﬁed, if required. The ﬁne phase shift block allows the CLKOS output to phase shifted a further 45,

22.5 or 11.25 degrees relative to its normal position. LOCK output signal is asserted when the DLL is locked. The

ALU HOLD signal setting allows users to freeze the DLL at its current delay setting.

2-11

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

There is a Digital Control (DCNTL) bus available from the DLL block. This Digital Control bus is available to the

delay lines in the PIC blocks in the adjacent banks. The UDDCNTL signal allows the user to latch the current value

on the digital control bus.

Figure 2-12 shows the DLL block diagram of the DLL inputs and outputs. The output of the phase frequency detec-

tor controls an arithmetic logic unit (ALU) to add or subtract one delay tap. The digital output of this ALU is used to

control the delay value of the delay chain and this digital code is transmitted via the DCNTL bus.

The sysCLOCK DLL can be conﬁgured at power-up, then, if desired, reconﬁgured dynamically through the Serial

Memory Interface bus which interfaces with the on-chip Microprocessor Interface (MPI) bus. In addition, users can

drive the SMI interface from routing if desired.

The user can conﬁgure the DLL for many common functions such as clock injection match and single delay cell.

Lattice provides primitives in its design for time reference delay (DDR memory) and clock injection delay removal.

Figure 2-12. DLL Diagram

CLKI

CLKOP

Phase Adj

Duty50

PFD

Delay

Chain

CLKFB

CLKOS

LOCK

ALU

ALUHOLD

DCNTL

Gen

UDDCNTL

RSTN

PLL/DLL Cascading

The LatticeSC devices have been designed to allow certain combinations of PLL and DLL cascading. The allow-

able combinations are as follows:

• PLL to PLL

• PLL to DLL

• DLL to DLL

• DLL to PLL

DLLs are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency

synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL blocks allows applica-

tions to utilize the unique beneﬁts of both DLL and PLLs.

When cascading the DLL to the PLL, the DLL can be used to drive the PLL to create ﬁne phase shifts of an input

clock signal. Figure 2-13 shows a shift of all outputs for CLKOP and CLKOS out in time.

2-12

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-13. DLL to PLL

CLKOP

CLKI

CLKOS

DLL

PLL

CLKOS

SMI Bus

Figure 2-14 shows a shift of only CLKOP out in time.

Figure 2-14. PLL to DLL

CLKI

PLL

CLKOP

DLL

CLKOS

SMI Bus

Figure 2-15 shows a shift of only CLKOS out in time.

Figure 2-15. PLL to DLL

CLKI

PLL

CLKOS

DLL

CLKOS

SMI Bus

For further information on the DLL, please see details of additional technical documentation at the end of this data

sheet.

sysMEM Memory Block

The sysMEM block can implement single port, true dual port, pseudo dual port or FIFO memories. Dedicated FIFO

support logic allows the LatticeSC devices to efﬁciently implement FIFOs without consuming LUTs or routing

resources for ﬂag generation. Each block can be used in a variety of depths and widths as shown in Table 2-5.

Memory with ranges from x1 to x18 in all modes: single port, pseudo-dual port and FIFO also providing x36.

2-13

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Table 2-5. sysMEM Block Conﬁgurations

Memory Mode

Conﬁgurations

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

Single Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

True Dual Port

Pseudo Dual Port

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

16,384 x 1

8,192 x 2

4,096 x 4

2,048 x 9

1,024 x 18

512 x 36

FIFO

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device conﬁguration. By preloading the RAM block

during the chip conﬁguration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

Single, Dual and Pseudo-Dual Port Modes

In all the sysMEM RAM modes the input data and address for the ports are registered at the input of the memory

array. The output data of the memory is optionally registered at the output. A clock is required even in asynchro-

nous read mode.

The EBR memory supports two forms of write behavior for dual port operation:

1. Normal — data on the output appears only during a read cycle. During a write cycle, the data (at the current

address) does not appear on the output.

2. Write Through — a copy of the input data appears at the output of the same port.

FIFO Conﬁguration

The FIFO has a write port with Data-in, WCE, WE and WCLK signals. There is a separate read port with Data-out,

RCE, RE and RCLK signals. The FIFO internally generates Almost Full, Full, Almost Empty, and Empty Flags. The

Full and Almost Full ﬂags are registered with WCLK.The Empty and Almost Empty ﬂags are registered with RCLK.

2-14

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the

reset is applied and released a clock cycle after the low-to-high transition of the reset, as shown in Figure 2-16.

Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram

Reset

Clock

Enable

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f

(EBR clock). The reset

MAX

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

If an EBR is pre-loaded during conﬁguration, the GSR input must be disabled or the release of the GSR during

device Wake Up must occur before the release of the device I/Os becoming active.

These instructions apply to all EBR RAM, ROM, FIFO and shift register implementations. For the EBR FIFO mode,

the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-16. The

reset timing rules apply to the RPReset input vs. the RE input and the RST input vs. the WE and RE inputs. Both

RST and RPReset are always asynchronous EBR inputs. For the EBR shift register mode, the GSR signal is

always enabled and the local RESET pin is always asynchronous.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

For more information about on-chip memory, see TN1094, On-Chip Memory Usage Guide for LatticeSC Devices.

Programmable I/O Cells (PIC)

Each PIC contains four PIOs connected to their respective PURESPEED I/O Buffer which are then connected to

the PADs as shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal

(TO) to PURESPEED I/O buffer, and receives input (DI) from the buffer. The PIO contains advanced capabilities to

allow the support of speeds up to 2Gbps. These include dedicated shift and DDR logic and adaptive input logic.

The dedicated resources simplify the design of robust interfaces.

2-15

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-17. PIC Diagram

PIO A

Tristate

Register Block

TD

IOLT0

DO

TO

OPOS0

ONEG0

OPOS1

ONEG1

OPOS2

ONEG2

OPOS3

ONEG3

PADA

"T"

Output

Register Block

DO

PURESPEED

I/O Buffer

INCK

INDD

INFF

IPOS0

INEG0

IPOS1

INEG1

IPOS2

INEG2

IPOS3

INEG3

DI

Input

Register Block

(including

delay and

RUNAIL

LOCK

AIL elements*)

HCLKOUT

LCLKOUT

CEO

LSRO

GSR

LSRO

HCLKIN

LCLKIN

CLK

CE

LSR

GSRN

ELSR

ECLK

Control

Muxes

Update Block

POS Update

UPDATE

NEG Update

PADB

“C”

PIO B

PIO C

PADC

“T”

PADD

“C”

PIO D

*AIL only on A or C pads located on the left, right and bottom of the device.

The A/B PIOs on the left and the right of the device can be paired to form a differentiated driver. The A/B and C/D

PIOs on all sides of the device can be paired to form differential receivers. Either A or C PIOs on all sides except

the one on top also provide a connection to an adaptive input logic capability that facilitates the implementation of

2-16

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

high-speed interfaces in the LatticeSC devices. Figure 2-18 shows how differential receivers and drivers are

arranged between PIOs.

Figure 2-18. Differential Drivers and Receivers

PADA "T"

PIO A

PADB "C"

PIO B

PADC "T"

PIO C

PADD "C"

PIO D

*Differential Driver only available on right and left of the device.

PIO

The PIO contains ﬁve blocks: an input register block, output register block, tristate register block, update block, and

a control logic block. These blocks contain registers for both single data rate (SDR), double data rate (DDR), and

shift register operation along with the necessary clock and selection logic.

Input Register Block

The input register block contains delay elements and registers that can be used to condition signals before they are

passed to the device core. Figure 2-20 show the diagram of the input register block. The signal from the PURE-

SPEED I/O buffer (DI) enters the input register block and can be used for three purposes, as a source for the com-

binatorial (INDD) and clock outputs (INCK), the input into the SDR register/latch block and the input to the delay

block. The output of the delay block can be used as combinatorial (INDD) and clock (INCK) outputs, an input to the

DDR/Shift Register Block or an input into the SDR register block.

Input SDR Register/Latch Block

The SDR register/latch block has a latch and a register/latch that can be used in a variety of combinations to pro-

vide a registered or latched output (INFF). The latch operates off high-speed input clocks and latches data on the

positive going edge.The register/latch operates off the low-speed input clock and registers/latches data on the pos-

itive going edge. Both the latch and the register/latch have a clock enable input that is driven by the input clock

enable. In addition both have a variety of programmable options for set/reset including, set or reset, asynchronous

or synchronous Local Set Reset LSR (LSR has precedence over CE) and Global Set Reset GSR enable or disable.

The register and latch LSR inputs are driven from LSRI, which is generated from the PIO control MUX. The GSR

inputs are driven from the GSR output of the PIO control MUX, which allows the global set-reset to be disabled on

a PIO basis.

Input Delay Block

The delay block uses 144 tapped delay lines to obtain coarse and ﬁne delay resolution. These delays can be

adjusted during conﬁguration or automatically via DLL or AIL blocks. The Adaptive Input Logic (AIL) uses this delay

block to adjust automatically the delay in the data path to ensure that it has sufﬁcient setup and hold time.

The delay line in this block matches the delay line that is used in the 12 on-chip DLLs. The delay line can be set via

conﬁguration bits or driven from a calibration bus that allows the setting to be controlled either from one of the on-

chip DLLs or user logic. Controlling the delay from one of the on-chip DLLs allow the delay to be calibrated to the

DLL clock and hence compensated for the variations in process, voltage and temperature.

2-17

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Adaptive Input Logic (AIL) Overview

The Adaptive Input Logic (AIL) provides the ability of the input logic to dynamically ﬁnd a solution by monitoring

multiple samples of the input data. The input data signal from the input buffer is run through a delay chain. Data,

transitions, jitter, noise are all contained inside of the delay chain. The AIL will then search the delay chain for a

clean sampling point for data. Once found the AIL will monitor and walk with the data dynamically. This novel

approach of using a delay chain to create multiple copies of the data provides a lower power solution than over-

sampling data with a higher speed clock. Figure 2-19 provides a high level view of the AIL methodology.

Figure 2-19. LatticeSC AIL Delay of Input Data Waveform

Input Data Signal

Delay Chain

AIL Acquisition Window

The AIL slides the acquisition window through the delay chain searching for stable data based solely on data tran-

sitions. A speciﬁc training pattern is not required to perform this bit alignment, simply data transitions. The size of

the acquisition window is user-selectable allowing the AIL to operate over the full range of the PURESPEED I/O

range. Based on dynamic user control the AIL can either continuously adjust the window location based on data

edge detection or it can be locked to a speciﬁc delay.

The AIL operates on single data and double data rate interfaces and is available on most FPGA input pins on the

LatticeSC device and all buffer types. The AIL block is low power using only 0.003 mW/MHz typical (6 mW @ 2

Gbps) for PRBS 2⁷data. Multiple AIL inputs can be used to create a bus with a FPGA circuit to realign the bus to a

common clock cycle. The FPGA circuit to realign the bus is required and is provided by Lattice as a reference

design.

For more information on the LatticeSC AIL please refer to the LatticeSC AIL User’s Guide.

Input DDR/Shift Block

The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the

high-speed clock and the associated transfer to the low-speed clock domain. It functions as a gearbox allowing

high-speed incoming data to be passed into the FPGA fabric. Each PIO supports DDR and x2 shift functions. If

desired PIOs A and B or C and D can be combined to form x4 shift functions. The PIOs A and C on the left, right

and bottom of the device also contain an optional Adaptive Input Logic (AIL) element. This logic automatically

aligns incoming data with the clock allowing for easy design of high-speed interfaces. Figure 2-21 shows a simpli-

ﬁed block diagram of the shift register block. The shift block in conjunction with the update and clock divider blocks

automatically handles the hand off between the low-speed and high-speed clock domains.

2-18

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-20. Input Register Block¹

CLKENABLE

CLKDISABLE

INDD

INCK

SDR Register/Latch Block

INFF

D-Type/

Latch

To

Routing

DDR/Shift Register Block

• DDR

• DDR + half clock

• DDR + shift x1

• DDR + shift x2

• DDR + shift x4³

• Shift x1

Delay

Block

IPOS0

DI

(from

PURESPEED

I/O Buffer)

IPOS1

INEG0

INEG1

Optional

Adaptive

Input

2

Logic

LCLKIN (ECLK/SCLK)

HCLKIN (ECLK/SCLK)

• Shift x2

• Shift x4³

LOCK

RUNAIL

DCNTL[0:8]

(From DLL)

1. UPDATE, Set and Reset not shown for clarity

2. Adaptive input logic is only available in selected PIO

3. By four shift modes utilize DDR/shift register block from paired PIO.

4. CLKDISABLE is used to block the transitions on the DQS pin during post-amble. Its main use is to

disable DQS (typically found in DDR memory interfaces) or other clock signals. It can also be used

to disable any/all input signals to save power.

2-19

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-21. Input DDR/Shift Register Block

From paired PIO

for wide muxing

To paired PIO

for wide muxing

Bypass used for DDR

IPOS0

(Can act as IPOS2

when paired)

Data Input

(From Delay Block)

IPOS1

(Can act as IPOS3

when paired)

HCLKIN

LCLKIN

POS Update

NEG Update

Bypass used for DDR

INEG0

(Can act as INEG2

when paired)

Used for DDR with

Half Clock Transfer

INEG1

(Can act as INEG3

when paired)

From paired PIO

for wide muxing

To paired PIO

for wide muxing

Output Register Block

The output register block provides the ability to register signals from the core of the device before they are passed

to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of registers for DDR

and shift register operation. The output signal (DO) can be derived directly from one of the inputs (bypass mode),

the SDR register or the DDR/shift register block. Figure 2-22 shows the diagram of the Output Register Block.

Output SDR Register/Latch Block

The SDR register operates on the positive edge of the high-speed clock. It has clock enable that is driven by the

clock enable output signal generated by the control MUX. In addition it has a variety of programmable options for

set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR (LSR has precedence over

CE) and Global Set Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated

from the PIO control MUX.The GSR inputs is driven from the GSR output of the PIO control MUX, which allows the

global set-reset to be disabled on a PIO basis.

Output DDR/Shift Block

The DDR/Shift block contains registers and associated logic that support DDR and shift register functions using the

high-speed clock and the associated transfer from the low-speed clock domain. It functions as a gearbox allowing

low-speed parallel data from the FPGA fabric be output as a higher speed serial stream. Each PIO supports DDR

and x2 shift functions. If desired PIOs A and B or C and D can be combined to form x4 shift functions. Figure 2-22

shows a simpliﬁed block diagram of the shift register block.

2-20

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-22. Output Register Block¹

To

Tri-state

Block

SDR

Register

DDR/Shift Register Block

• DDR

OPOS0

From

Routing

ONEG0

OPOS1

ONEG1

DO

• DDR + half clock

• DDR + shift x2

(to PURESPEED

I/O Buffer)

2

• DDR + shift x4

• Shift x2

• Shift x4

From

Control

MUX

LCLKOUT

HCLKOUT

2

Notes:

1. CE, Update, Set and Reset not shown for clarity.

2. By four shift modes utilizes DDR/Shift register block from paired PIO.

3. DDR/Shift register block shared with tristate block.

Figure 2-23. Output/Tristate DDR/Shift Register Block

From paired PIO

( x4 shift modes)

To paired PIO

(x4 shift modes)

Bypass Used for

DDR/DDRX Modes

OPOS0

(Can act as OPOS2

when paired)

Shift x2 / x4

Output

OPOS1

(Can act as OPOS3

when paired)

LCLKOUT

TSDDR/DDRX

HCLKOUT

POS Update

NEG Update

ODDR/DDR/

X2/X4

To paired PIO

(x4 shift modes)

From paired PIO

( x4 shift modes)

Bypass Used for

DDR/DDRX Modes

ONEG0

(Can act as ONEG2

when paired)

ONEG1

(Can act as ONEG3

when paired)

2-21

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Tristate Register Block

The tristate register block provides the ability to register tri-state control signals from the core of the device before

they are passed to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of

three registers for DDR and shift register operation. The output signal tri-state control signal (TO) can be derived

directly from one of the inputs (bypass mode), the SDR shift register, the DDR registers or the data associated with

the buffer (for open drain emulation). Figure 2-24 shows the diagram of the Tristate Register Block.

Tristate SDR Register/Latch Block

The SDR register operates on the positive edge of the high-speed clock. In it has a variety of programmable

options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR and Global Set

Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated from the PIO control

MUX. The GSR input is driven from the GSR output of the PIO control MUX, which allows the global set-reset to be

disabled on a PIO basis.

Tristate DDR/Shift Register Block

The DDR/Shift block is shared with the output block allowing DDR support using the high-speed clock and the

associated transfer from the low-speed clock domain. It functions as a gearbox allowing low–speed parallel data

from the FPGA fabric to provide a high-speed tri-state control stream.

There is a special mode for DDR-II memory interfaces where the termination is controlled by the output tristate sig-

nal. During WRITE cycle when the FPGA is driving the lines, the parallel terminations are turned off. During READ

cycle when the FPGA is receiving data, the parallel terminations are turned on.

Figure 2-24. Tristate Register Block¹

TD

VCC

GND

DDR/Shift Register Block²

• DDR

From

Routing

OPOS1

ONEG1

TO

• DDR + half clock

(To PURESPEED

I/O Buffer)

From

Control

MUX

LCLKOUT

HCLKOUT

Notes:

1. CE, Update, Set and Reset not shown for clarity.

2. DDR/Shift Register Block shared with output register block.

From Output

I/O Architecture Rules

Table 2-6 shows the PIO usage for x1, x2, x4 gearing. The checkmarks in the columns show the speciﬁc PIOs that

are used for each gearing mode. When using x2 or x4 gearing, any PIO which is not used for gearing can still be

used as an output.

2-22

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Table 2-6. Input/Output/Tristate Gearing Resource Rules

Input/Output Logic

Tri-State/Bidi

PIO

A

x1

✓

x2

x4

x1

✓

x2/x4

N/A

✓

B

No I/O Logic No I/O Logic

No I/O Logic

No I/O Logic No I/O Logic

N/A

C

✓

N/A

D

N/A

Note: Pin can still be used without I/O logic.

Control Logic Block

The control logic block allows the modiﬁcation of control signals selected by the routing before they are used in the

PIO. It can optionally invert all signals passing through it except the Global Set/Reset. Global Set/Reset can be

enabled or disabled. It can route either the edge clock or the clock to the high-speed clock nets. The clock provided

to the PIO by routing is used as the slow-speed clocks. In addition this block contains delays that can be inserted in

the clock nets to enable Lattice’s unique cycle boosting capability.

Update Block

The update block is used to generate the POS update and NEG update signals used by the DDR/Shift register

blocks within the PIO. Note the update block is only required in shift modes. This is required in order to do the high

speed to low speed handoff. One of these update signals is also selected and output from the PIC as the signal

UPDATE. It consists of a shift chain that operates off either the high-speed input or output clock.The values of each

register in the chain are set or reset depending on the desired mode of operation. The set/reset signal is generated

from either the edge reset ELSR or the local reset LSR. These signals are optionally inverted by the Control Logic

Block and provided to the update block as ELSRUP and LSRUP. The Lattice design tools automatically conﬁgure

and connect the update block when one of the DDR or shift register primitives is used.

Figure 2-25. Update Block

POS Update

÷1/2/4

NEG Update

HCLKUP

ESLRUP

LSRUP

UPDATE

LCLKUP

PURESPEED I/O Buffer

Each I/O is associated with a ﬂexible buffer referred to as PURESPEED I/O buffer. These buffers are arranged

around the periphery of the device in seven groups referred to as Banks. The PURESPEED I/O buffers allow users

to implement the wide variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL,

LVDS and LVPECL. The availability of programmable on-chip termination for both input and output use, further

enhances the utility of these buffers.

2-23

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

PURESPEED I/O Buffer Banks

LatticeSC devices have seven PURESPEED I/O buffer banks; each is capable of supporting multiple I/O stan-

dards. Each PURESPEED I/O bank has its own I/O supply voltage (V ), and two voltage references V and

CCIO

REF1

V

resources allowing each bank to be completely independent from each other. Figure 2-26 shows the seven

REF2

banks and their associated supplies. Table 2-7 lists the maximum number of I/Os per bank for the whole LatticeSC

family.

In the LatticeSC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI33 and PCIX33)

are powered using V

. In addition to the bank V

supplies, the LatticeSC devices have a V core logic power

CCIO

CCIO CC

supply, and a V

supply that power all differential and referenced buffers. VCCAUX also powers a predriver of

CCAUX

single-ended output buffers to enhance buffer performance.

Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-

enced input buffers. In the LatticeSC devices any I/O pin in a bank can be conﬁgured to be a dedicated reference

voltage supply pin. Each I/O is individually conﬁgurable based on the bank’s supply and reference voltages.

Differential drivers have user selectable internal or external bias. External bias is brought in by the VREF1 pin in the

bank. External bias for differential buffers is needed for applications that requires tighter than standard output com-

mon mode range.

Since a bank can have only one external bias circuit for differential drivers, LVDS and RSDS differential outputs can

be mixed in a bank but not with HYPT (HyperTransport).

If a differential driver is conﬁgured in a bank, one pin in that bank becomes a DIFFR pin. This DIFFR pin must be

connected to ground via an external 1K +/-1% ohm resistor. Note that differential drivers are not supported in

banks 1, 4 and 5.

In addition, there are dedicated Terminating Supply (V ) pins to be used as terminating voltage for one of the two

TT

ways to perform parallel terminations. These V pins are available in banks 2-7, these pins are not available in

TT

some packages. When VTT termination is not required, or used to provide the common mode termination voltage

(VCMT), these pins can be left unconnected on the device. If the internal or external VCMT function for differential

input termination is used, the VTT pins should be unconnected and allowed to ﬂoat.

There are further restrictions on the use of V pins, for additional details refer to technical information at the end of

TT

this data sheet.

2-24

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-26. LatticeSC Banks

SERDES

Bank 1

V

CCIO7

V

CCIO2

REF1[7]

REF1[2]

TT7

TT2

REF2[7]

REF2[2]

GND

V

CCIO6

V

CCIO3

REF1[6]

REF1[3]

TT6

TT[3]

REF2[6]

REF2[3]

GND

Bank 5

Bank 4

Table 2-7. Maximum Number of I/Os Per Bank in LatticeSC Family

Device

Bank1

LFSC/M15

LFSC/M25

LFSC/M40

LFSC/M80

80

LFSC/M115

136

104

28

60

72

60

28

80

36

136

60

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

96

136

84

96

132

156

100

84

124

96

184

208

184

208

132

156

36

60

96

136

Note: Not all the I/Os of the Banks are available in all the packages

The LatticeSC devices contain three types of PURESPEED I/O buffers:

1. Left and Right Sides (Banks 2, 3, 6 and 7)

These buffers can support LVCMOS standards up to 2.5V. A differential output driver (for LVDS, RSDS, and

HYPT) is provided on all primary PIO pairs (A and B) and differential receivers are available on all pairs. Com-

plimentary drivers are available. Adaptive input logic is available on PIOs A or C.

2. Top Side (Bank 1)

These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential

receivers are provided on all PIO pairs but differential drivers for LVDS, RSDS, and HYPT are not available.

Adaptive input logic is not available on this side. Complimentary output drivers are available.

2-25

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

3. Bottom Side (Banks 4 and 5)

These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential

receivers are provided on all PIO pairs but true HLVDS, RSDS, and HYPT differential drivers are not available.

Adaptive input logic is available on PIOs A or C.

Table 2-8 lists the standards supported by each side.

Table 2-8. I/O Standards Supported by Different Banks

Top Side

Banks 1

Right Side

Banks 2-3

Bottom Side

Banks 4-5

Left Side

Description

I/O Buffer Type

Banks 6-7

Single-ended,

Differential Receiver

Single-ended, Differen- Single-ended,

tial Receiver and Driver Differential Receiver

Single-ended, Differen-

tial Receiver and Driver

Output Standards

Supported

LVTTL

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

LVTTL

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

SSTL18_I, II

SSTL25_ I, II

SSTL33_ I, II

HSTL15_I, II, III¹, IV¹

HSTL18_I, II,III¹, IV¹

SSTL18D_I, II

SSTL25D_I, II

SSTL33D_I, II

HSTL15D_I, II

HSTL18D_I, II

PCI33

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

SSTL18_I, II

SSTL25_ I, II

SSTL33_ I, II

HSTL15_I, II, III¹, IV¹

HSTL18_I, II,III¹, IV¹

SSTL18D_I, II

SSTL25D_I, II

SSTL33D_I, II

HSTL15D_I, II

HSTL18D_I, II

PCI33

SSTL18_I, II

SSTL25_ I, II

HSTL15_I,III

HSTL18_I,II,III

PCIX15

SSTL18D_I, II

SSTL25D_I, II

HSTL15D_I, II

HSTL18D_I, II

LVDS/RSDS/HYPT

Mini-LVDS

SSTL18_I, II

SSTL25_ I, II

HSTL15_I,III

HSTL18_I,II,III

PCIX15

SSTL18D_I, II

SSTL25D_I, II

HSTL15D_I, II

HSTL18D_I, II

LVDS/RSDS/HYPT

Mini-LVDS

MLVDS/BLVDS

GTL², GTL+²

PCIX15

PCIX33

PCIX15

PCIX33

AGP1X33

AGP2X33

AGP1X33

AGP2X33

MLVDS/BLVDS

GTL², GTL+²

Input Standards

Supported

Single-ended,

Differential

Single-ended,

Differential

Single-ended,

Differential

Single-ended,

Differential

Clock Inputs

Single-ended,

Differential

Single-ended,

Differential

Single-ended,

Differential

Single-ended,

Differential

Differential Output

Support via Emulation LVPECL

LVDS/MLVDS/BLVDS/ MLVDS/BLVDS/

LVPECL

AIL Support

1. Input only.

No

Yes

2. Input only. Outputs supported by bussing multiple outputs together.

Supported Standards

The LatticeSC PURESPEED I/O buffer supports both single-ended and differential standards. Single-ended stan-

dards can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVC-

MOS 12, 15, 18, 25 and 33 standards. In the LVCMOS and LVTTL modes, the buffer has individually conﬁgurable

options for drive strength, termination resistance, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper

latch) and open drain. Other single-ended standards supported include SSTL, HSTL, GTL (input only), GTL+ (input

only), PCI33, PCIX33, PCIX15, AGP-1X33 and AGP-2X33. Differential standards supported include LVDS, RSDS,

BLVDS, MLVDS, LVPECL, HyperTransport, differential SSTL and differential HSTL. Tables 12 and 13 show the I/O

standards (together with their supply and reference voltages) supported by the LatticeSC devices. The tables also

provide the available internal termination schemes. For further information on utilizing the PURESPEED I/O buffer

to support a variety of standards please see details of additional technical documentation at the end of this data

sheet.

2-26

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Table 2-9. Supported Input Standards

Input Standard

Single Ended Interfaces

LVTTL33³

LVCMOS 33, 25, 18, 15, 12³

PCI33, PCIX33, AGP1X33³

PCIX15

V

(Nom.)

V

¹(Nom.)

CCIO

On-chip Termination

REF

—

3.3

None

3.3/2.5/1.8/1.5/1.2 None

3.3

1.5²

None

0.75

1.32

0.9

None / V

None

/ 2: 50, 60/ V : 60, 75, 120, 210

CCIO

TT

AGP2X33

—

1.8²

1.5²

HSTL18_I, II

None / V

None

/ 2: 50, 60/ V : 60, 75, 120, 210

CCIO

TT

HSTL18_III, IV

HSTL15_I, II

1.08

0.75

0.9

: 50

/ 2: 50, 60/ V : 60, 75, 120, 210

TT

HSTL15_III, IV

SSTL33_I, II

1.5²

: 50

1.5

3.3

SSTL25_I, II

1.25

0.9

2.5²

1.8²

1.5 / 1.2²

None / V

/ 2: 50, 60/ V : 60, 75, 120, 210

CCIO

TT

SSTL18_I, II

/ 2: 50, 60/ V : 60, 75, 120, 210

TT

GTL+, GTL

1.0 / 0.8

: 50

Differential Interfaces

SSTL18D_I, II

—

1.8²

2.5²

None / Diff: 120, 150, 220, 420/ Diff to V

: 120, 150,

CMT

220, 420 / V

/ 2: 50, 60/ V : 60, 75, 120, 210

CCIO

TT

SSTL25D_I, II

None / Diff: 120, 150, 220, 420/ Diff to V

: 120, 150,

CMT

220, 420 / V

/ 2: 50, 60/ V : 60, 75, 120, 210

CCIO

TT

SSTL33D_I, II

HSTL15D_I, II

—

3.3

1.5²

None

None / Diff: 120, 150, 220, 420/ Diff to V

220, 420 / V

: 120, 150,

/ 2: 50, 60/ V : 60, 75, 120, 210

CMT

CCIO

TT

HSTL18D_I, II

LVDS

—

1.8²

—

None / Diff: 120, 150, 220, 420/ Diff to V

: 120, 150,

CMT

220, 420 / V

/ 2: 50, 60/ V : 60, 75, 120, 210

CCIO

TT

None / Diff: 120, 150, 220, 240/ Diff to V

220, 240

: 120, 150,

CMT

Mini-LVDS

—

None / Diff: 120, 150 / Diff to V

: 120, 150

CMT

BLVDS25

None

MLVDS25

HYPT (Hyper Transport)

None / Diff: 120, 150, 220, 240/ Diff to V

220, 240

: 120, 150,

CMT

RSDS

—

None / Diff: 120, 150, 220, 240/ Diff to V

220, 240

LVPECL33

≤2.5

None / Diff: 120, 150, 220, 240/ Diff to V

220, 240

1. When not speciﬁed V

can be set anywhere in the valid operating range.

CCIO

2. V

needed for on-chip termination to V

/2 or V

only. V

is not speciﬁed for off-chip termination or V termination.

CCIO

CCIO TT

3. All ratioed input buffers and dedicated pin input buffers include hysteresis with a typical value of 50mV.

2-27

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Table 2-10. Supported Output Standards⁴

Output Standard

Single-ended Interfaces

LVTTL/D¹

LVCMOS33/D¹

LVCMOS25/D^{1, 2}

LVCMOS18/D^{1, 2}

LVCMOS15/D^{1, 2}

LVCMOS12/D^{1, 2}

PCIX15

Drive

V

(Nom)

On-chip Output Termination

CCIO

8mA, 16mA, 24mA

4mA, 8mA, 12mA, 16mA,

2mA, 4mA, 8mA, 12mA

N/A

3.3

None.

3.3

2.5

1.8

1.5

1.2

1.5

None

None, series: 25, 33, 50, 100

None

PCI33, PCIX33, AGP1X33,

AGP2X33

N/A

3.3

1.8

1.5

None

HSTL18_I

HSTL18_II

HSTL15_I

HSTL15_II

None, series: 50

None, series: 25, series + parallel to V

25 + 60

/2:

CCIO

None, series: 50

None, series: 25, series + parallel to V

25 + 60

CCIO

SSTL33_I

SSTL33_II

SSTL25_I

N/A

3.3

2.5

None

None, series: 50

None, series: 33, series + parallel to V

33+ 60

/2:

CCIO

SSTL25_II

SSTL18_ I

SSTL18_II

N/A

2.5

1.8

None, series: 33

None, series: 33, series + parallel to V

33+ 60

CCIO

Differential Interfaces

SSTL18D_I

N/A

1.8

2.5

None, series: 33

None, series: 50

SSTL25D_I

None, series: 33, series + parallel to V

33+ 60

/2:

CCIO

SSTL18D_II, SSTL25D_II

N/A

1.2/2.5/3.3

SSTL33D_I, II

N/A

3.3

None

HSTL15D_I, HSTL18D_I

1.5/1.8

None, series: 50

None, series: 25, series + parallel to V

25 + 60

CCIO

HST15D_II, HSTL18D_II

N/A

1.5/1.8

LVDS

2mA, 3.5mA, 4mA, 6mA

3.5mA, 4mA, 6mA

N/A

3.3

None

Mini-LVDS

BLVDS25

MLVDS25

LVPECL33³

N/A

HYPT (Hyper Transport)

RSDS

3.5mA, 4mA, 6mA

2mA, 3.5mA, 4mA, 6mA

N/A

1. D refers to open drain capability.

2. User can select either drive current or driver impedances but not both.

3. Emulated with external resistors.

4. No GTL or GTL+ support.

2-28

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

PCI Clamp

A programmable PCI clamp is available on the top and bottom banks of the device. The PCI clamp can be turned

“ON” or “OFF” on each pin independently.The PCI clamp is used when implementing a 3.3V PCI interface.The PCI

Speciﬁcation, Revision 2.2 requires the use of clamping diodes for 3.3V operation. For more information on the PCI

interface, please refer to the PCI Speciﬁcation, Revision 2.2.

Programmable Slew Rate Control

All output and bidirectional buffers have an optional programmable output slew rate control that can be conﬁgured

for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows

designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling

edges.

Programmable Termination

Many of the I/O standards supported by the LatticeSC devices require termination at the transmitter, receiver or both.

The SC devices provide the capability to implement many kinds of termination on-chip, minimizing stub lengths and

hence improving performance. Utilizing this feature also has the beneﬁt of reducing the number of discrete compo-

nents required on the circuit board. The termination schemes can be split into two categories single-ended and differ-

ential.

Single Ended Termination

Single Ended Outputs: The SC devices support a number of different terminations for single ended outputs:

• Series

• Parallel to V

or GND

/2

/2 combined with series

CCIO

Figure 2-27 shows the single ended output schemes that are supported. The nominal values of the termination resis-

tors are shown in Table 2-10.

2-29

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-27. Output Termination Schemes

Termination Type

Discrete Off-Chip Solution

Lattice On-Chip Solution

Zo

Series termination

(controlled output

impedance)

Zo

ON-chip

OFF-chip

ON-chip

OFF-chip

VCCIO or GND

Zo

VCCIO or GND

Zo

Parallel termination to

V_CCIO,or parallel

driving end

Zo

ON-chip

OFF-chip

ON-chip

OFF-chip

VCCIO

2Zo

VCCIO/2

Zo

Parallel termination to

V_CCIO/2 driving end

Zo

2Zo

ON-chip

OFF-chip

GND

ON-chip

OFF-chip

VCCIO/2

Zo

VCCIO/2

Zo

Combined series +

parallel termination to

Rs

Zo

V_CCIO/2 at driving end

(only series termination

moved on-chip)

ON-chip

OFF-chip

ON-chip

OFF-chip

VCCIO

2Zo

VCCIO/2

Rs

Zo

Combined series +

parallel to V_CCIO/2

driving end

Rs

Zo

2Zo

GND

ON-chip

OFF-chip

ON-chip

OFF-chip

2-30

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Single Ended Inputs: The SC devices support a number of different termination schemes for single ended inputs:

• Parallel to V

or GND

/2

CCIO

TT

Figure 2-28 shows the single ended input schemes that are supported. The nominal values of the termination resis-

tors are shown in Table 2-9.

Figure 2-28. Input Termination Schemes

Termination Type

Discrete Off-Chip Solution

Lattice On-Chip Solution

VCCIO or GND

Zo

VCCIO or GND

Zo

Parallel termination to

to V_CCIO, or parallel to

GND receiving end

Zo

OFF-chip

ON-chip

OFF-chip

ON-chip

VCCIO

VCCIO2

Zo

2Zo

Zo

Parallel termination to

Zo

V

_CCIO/2 receiving end

2Zo

GND

OFF-chip

ON-chip

OFF-chip

ON-chip

VTT

Zo

VTT

Zo

Parallel termination to

V_TTat receiving end

Zo

OFF-chip

ON-chip

OFF-chip

ON-chip

In many situations designers can chose whether to use Thevenin or parallel to V termination. The Thevenin

TT

approach has the beneﬁt of not requiring a termination voltage to be applied to the device. The parallel to V

approach consumes less power.

TT

VTT Termination Resources

Each I/O bank, except bank 1, has a number of V pins that must be connected if V is used. Note V pins can

TT

sink or source current and the power supply they are connected to must be able to handle the relatively high currents

associated with the termination circuits. Note: V is not available in all package styles.

TT

On-chip parallel termination to V is supported at the receiving end only. On-chip parallel output termination to V is

TT

not supported.

The V internal bus is also connected to the internal V

node. Thus in one bank designers can implement either

CMT

TT

V

termination or V

termination for differential inputs.

TT

CMT

DDRII/RLDRAMII Termination Support

The DDR II memory and RLDRAMII (in Bidirection Data mode) standards require that the on-chip termination to V

TT

be turned on when a pin is an input and off when the pin is an output. The LatticeSC devices contain the required cir-

cuitry to support this behavior. For additional detail refer to technical information at the end of the data sheet.

2-31

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Differential Input Termination

The LatticeSC device allows two types of differential termination. The ﬁrst is a single resistor across the differential

inputs. The second is a center-tapped system where each input is terminated to the on-chip termination bus V

.

CMT

The V

bus is DC-coupled through an internal capacitor to ground.

CMT

Figure 2-29 shows the differential termination schemes and Table 2-9 shows the nominal values of the termination

resistors.

Figure 2-29. Differential Termination Scheme

Termination Type

Discrete Off-Chip Solution

Lattice On-Chip Solution

Zo

+

-

+

-

2Zo

Differential termination

Zo

OFF-chip

ON-chip

OFF-chip

ON-chip

Zo

GND

Zo

Differential and common

mode termination

VCMT

GND

+

-

+

-

OFF-chip

ON-chip

OFF-chip

ON-chip

Calibration

There are two calibration sources that are associated with the termination scheme used in the LatticeSC devices:

• DIFFR – This pin occurs in each bank that supports differential drivers and must be connected through a

1K+/-1% resistor to ground if differential outputs are used. Note that differential drivers are not supported in

banks 1, 4 and 5.

• XRES – There is one of these pins per device. It is used for several functions including calibrating on-chip

termination. This pin should always be connected through a 1K+/-1% resistor to ground.

The LatticeSC devices support two modes of calibration:

• Continuous – In this mode the SC devices continually calibrate the termination resistances. Calibration hap-

pens several times a second. Using this mode ensures that termination resistances remain calibrated as

the silicon junction temperature changes.

• User Request – In this mode the calibration circuit operates continuously. However, the termination resistor

values are only updated on the assertion of the calibration_update signal available to the core logic.

For more information on calibration, refer to the details of additional technical documentation at the end of this data

sheet.

Hot Socketing

The LatticeSC devices have been carefully designed to ensure predictable behavior during power-up and power-

down. To ensure proper power sequencing, care must be taken during power-up and power-down as described

below. During power-up and power-down sequences, the I/Os remain in tristate until the power supply voltage is

high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled to within speciﬁed limits,

2-32

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

this allows for easy integration with the rest of the system. These capabilities make the LatticeSC ideal for many

multiple power supply and hot-swap applications. The maximum current during hot socketing is 4mA. See Hot

Socketing Speciﬁcations in Chapter 3 of this data sheet.

Power-Up Requirements

To prevent high power supply and input pin currents, each VCC, VCC12, VCCAUX, VCCIO and VCCJ power sup-

plies must have a monotonic ramp up time of 75 ms or less to reach its minimum operating voltage. Apart from VCC

and VCC12, which have an additional requirement, and VCCIO and VCCAUX, which also have an additional

requirement, the VCC, VCC12, VCCAUX, VCCIO and VCCJ power supplies can ramp up in any order, with no

restriction on the time between them. However, the ramp time for each must be 75 ms or less. Conﬁguration of the

device will not proceed until the last power supply has reached its minimum operating voltage.

Additional Requirement for VCC and VCC12:

VCC12 must always be higher than VCC. This condition must be maintained at ALL times, including during power-

up and power-down. Note that for 1.2V only operation, it is advisable to source both of these supplies from the

same power supply.

Additional Requirement for VCCIO and VCCAUX:

If any VCCIOs are 1.2/1.5/1.8V, then VCCAUX MUST be applied before them. If any VCCIO is 1.2/1.5/1.8V and is

powered up before VCCAUX, then when VCCAUX is powered up, it may drag VCCIO up with it as it crosses

through the VCCIO value. (Note: If the VCCIO supply is capable of sinking current, as well as the more usual sourc-

ing capability, this behavior is eliminated. However, the amount of current that the supply needs to sink is unknown

and is likely to be in the hundreds of milliamps range).

Power-Down Requirements

To prevent high power supply and input pin currents, power must be removed monotonically from either VCC or

VCCAUX (and must reach the power-down trip point of 0.5V for VCC, 0.95V for VCCAUX) before power is removed

monotonically from VCC12, any of the VCCIOs, or VCCJ. Note that VCC12 can be removed at the same time as

VCC, but it cannot be removed earlier. In many applications, VCC and VCC12 will be sourced from the same power

supply and so will be removed together. For systems where disturbance of the user pins is a don't care condition,

the power supplies can be removed in any order as long as they power down monotonically within 200ms of each

other.

Additionally, if any banks have VCCIO=3.3V nominal (potentially banks 1, 4, 5) then VCCIO for those banks must

not be lower than VCCAUX during power-down. The normal variation in ramp-up times of power supplies and volt-

age regulators is not a concern here.

Note: The SERDES power supplies are NOT included in these requirements and have no speciﬁc sequencing

requirements. However, when using the SERDES with VDDIB or VDDOB that is greater than 1.2V (1.5V nominal

for example), the SERDES should not be left in a steady state condition with the 1.5V power applied and the 1.2V

power not applied. Both the 1.2V and 1.5V power should be applied to the SERDES at nominally the same time.

The normal variation in the ramp-up times of power supplies and voltage regulators is not a concern here.

SERDES Power Supply Sequencing Requirements

When using the SERDES with 1.5V VDDIB or VDDOB supplies, the SERDES should not be left in a steady state

condition with the 1.5V power applied and the 1.2V power not applied. Both the 1.2V and the 1.5V power should be

applied to the SERDES at nominally the same time. The normal variation in ramp-up times of power supples and

voltage regulators is not a concern.

Additional Requirement for SERDES Power Supply

All VCC12 pins need to be connected on all devices independent of functionality used on the device. This analog

supply is used by both the RX and TX portions of the SERDES and is used to control the core SERDES logic

regardless of the SERDES being used in the design. VDDIB and VDDOB are used as supplies for the terminations

on the CML input and output buffers. If a particular channel is not used, these can be UNCONNECTED (ﬂoating).

2-33

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

VDDAX25 needs to be connected independent of the use of the SERDES. This supply is used to control the SER-

DES CML I/O regardless of the SERDES being used in the design.

Supported Source Synchronous Interfaces

The LatticeSC devices contain a variety of hardware, such as delay elements, DDR registers and PLLs, to simplify

the implementation of Source Synchronous interfaces. Table 2-11 lists Source Synchronous and DDR/QDR stan-

dards supported in the LatticeSC. For additional detail refer to technical information at the end of the data sheet.

Table 2-11. Source Synchronous Standards Table¹

Source Synchronous Standard

RapidIO

HyperTransport²

Clocking

DDR

Speeds (MHz)

Data Rate (Mbps)

500

800

500

1000

1600

1000

667

DDR

SPI4.2 (POS-PHY4)/NPSI

DDR

SDR

334

667

SFI4/XSBI

XGMII

DDR

SDR

DDR

156.25

250

312

250

600

480

667

800

CSIX

QDRII/QDRII+ memory interface

DDR memory interface

DDRII memory interface

RLDRAM memory interface

300

240

333

400

1. Memory width is dependent on the system design and limited by the number of I/Os in the device.

2. Tested using non-coupled, six-inch traces fed directly into an edge clock resource.

ﬂexiPCS™ (Physical Coding Sublayer Block)

ﬂexiPCS Functionality

The LatticeSC family combines a high-performance FPGA fabric, high-performance I/Os and large embedded

RAM in a single industry leading architecture. LatticeSC devices also feature up to 32 channels of embedded SER-

DES with associated Physical Coding Sublayer (PCS) logic. The ﬂexiPCS logic can be conﬁgured to support

numerous industry standard high-speed data transfer protocols.

Each channel of ﬂexiPCS logic contains dedicated transmit and receive SERDES for high-speed, full-duplex serial

data transfers at data rates up to 3.8 Gbps.The PCS logic in each channel can be conﬁgured to support an array of

popular data protocols including SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support of 10 Gbps or

above), Gigabit Ethernet (compliant to the IEEE 1000BASE-X speciﬁcation), 1.02 or 2.04 Gbps Fibre Channel,

PCI-Express, and Serial RapidIO. In addition, the protocol based logic can be fully or partially bypassed in a num-

ber of conﬁgurations to allow users ﬂexibility in designing their own high-speed data interface.

Protocols requiring data rates above 3.8 Gbps can be accommodated by dedicating either one pair or all four chan-

nels in one ﬂexiPCS quad block to one data link. One quad can support full-duplex serial data transfers at data

rates up to 15.2 Gbps. A single ﬂexiPCS quad can be conﬁgured to support 10Gb Ethernet (with a fully compliant

XAUI interface), 10Gb Fibre Channel, and x4 PCI-Express and 4x RapidIO.

The ﬂexiPCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the

FPGA logic which can also be geared to run at 1/2 speed for a 16-bit or 20-bit interface to the FPGA logic. Each

SERDES pin can be DC coupled independently and can allow for both high-speed and low-speed operation down

to DC rates on the same SERDES pin, as required by some Serial Digital Video applications.

The ispLEVER design tools from Lattice support all modes of the ﬂexiPCS. Most modes are dedicated to applica-

tions associated with a speciﬁc industry standard data protocol. Other more general purpose modes allow a user to

2-34

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

deﬁne their own operation. With ispLEVER, the user can deﬁne the mode for each quad in a design. Nine modes

are currently supported by the ispLEVER design ﬂow:

• 8-bit SERDES Only

• 10-bit SERDES Only

• SONET (STS-12/STS-48)

• Gigabit Ethernet

• Fibre Channel

• XAUI

• Serial RapidIO

• PCI-Express

• Generic 8b10b

ﬂexiPCS Quad

The ﬂexiPCS logic is arranged in quads containing logic for four independent full-duplex data channels. Each

device in the LatticeSC family has up to eight quads of ﬂexiPCS logic. The LatticeSC Family Selection Guide table

on the ﬁrst page of this data sheet contains the number of ﬂexiPCS channels present on the chip. Note that in

some packages (particularly lower pin count packages), not all channels from all quads on a given device may be

bonded to package pins.

Each quad supports up to four channels of full-duplex data and can be programmed into any one of several proto-

col based modes. Each quad requires its own reference clock which can be sourced externally or from the FPGA

logic. The user can utilize between one and four channels in a quad, depending on the application.

Figure 2-30 shows an example of four ﬂexiPCS quads in a LatticeSC device. Quads are labeled according to the

address of their software controlled registers.

Figure 2-30. LatticeSC ﬂexiPCS

flexiPCS

Quad 360

High Speed

Serial Data

flexiPCS

Quad 361

High Speed

Serial Data

flexiPCS

Quad 3E1

High Speed

Serial Data

flexiPCS

Quad 3E0

High Speed

Serial Data

SERDES Interface

FPGA Logic I/Os

FPGA Logic

flexiPCS

Quad 360

PCS/FPGA

Interface

flexiPCS

Quad 361

PCS/FPGA

Interface

flexiPCS

Quad 3E1

PCS/FPGA

Interface

flexiPCS

Quad 3E0

PCS/FPGA

Interface

FPGA Logic I/Os

2-35

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Since each quad has its own reference clock, different quads can support different standards on the same chip.

This feature makes the LatticeSC family of devices ideal for bridging between different standards.

ﬂexiPCS quads are not dedicated solely to industry standard protocols. Each quad (and each channel within a

quad) can be programmed for many user deﬁned data manipulation modes. For example, modes governing user-

deﬁned word alignment and multi-channel alignment can be programmed for non-standard protocol applications.

For more information on the functions and use of the ﬂexiPCS, refer to the LatticeSC ﬂexiPCS Data Sheet.

System Bus

Each LatticeSC device connects the FPGA elements with a standardized bus framework referred to as a System

Bus. Multiple bus masters optimize system performance by sharing resources between different bus masters such

as the MPI and conﬁguration logic. The wide data bus conﬁguration of 32 bits with 4-bit parity supports high-band-

width, data intensive applications.

There are two types of interfaces on the System Bus, master and slave. A master interface has the ability to per-

form actions on the bus, such as writes and reads to and from a speciﬁc address. A slave interface responds to the

actions of a master by accepting data and address on a write and providing data on a read. The System Bus has a

memory map which describes each of the slave peripherals that is connected on the bus. Using the addresses

listed in the memory map, a master interface can access each of the slave peripherals on the System Bus. Any and

all peripherals on the System Bus can be used at the same time. Table 2-12 list all of the available user peripherals

on the System Bus after device power-up.

Table 2-12. System Bus User Peripherals

Peripheral

Micro Processor Interface

Name

MPI

Interface Type

Master

Slave

User Master Interface

UMI

USI

User Slave Interface

Serial Management Interface (PLL, DLL, User Logic)

Physical Coding Sublayer

SMI

Slave

PCS

DFA

Slave

Direct FPGA Access

Slave

The peripherals listed in Table 2-12 can be added when the System Bus module is created using Module IP/Man-

ager (ispLEVER Module/IP Manager).

Figure 2-31 also lists the existing peripherals on the System Bus. The gray boxes are available only during conﬁgu-

ration. Refer to Lattice technical note TN1080, LatticeSC sysCONFIG Usage Guide, for conﬁguration options. The

Status and Conﬁg box refers to internal System Bus registers. This document presents all the interfaces listed in

Table 2-12 in detail to help the user utilize the desired functions of the System Bus.

2-36

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-31. LatticeSC System Bus Interfaces

DFA

(Direct Access

from MPI)

SMI

(PLL, DLL,

USER LOGIC)

STATUS and

CONFIG

(SYS REG)

CONFIG

(MASTER)

USI

(SLAVE)

System Bus

PCS (LEFT, RIGHT

and INTER-QUAD)

(SLAVE)

MPI

(MASTER)

EBR INIT

(WRITE)

UMI

(MASTER)

Several interfaces exist between the System Bus and other FPGA elements. The MPI interface acts as a bridge

between the external microprocessor bus and System Bus. The MPI may work in an independent clock domain

from the System Bus if the System Bus clock is not sourced from the external microprocessor clock. Pipelined

operation allows high-speed memory interface to the EBR and peripheral access without the requirement for addi-

tional cycles on the bus. Burst transfers allow optimal use of the memory interface by giving advance information of

the nature of the transfers.

Details for the majority of the peripherals can be found in the associated technical documentation, see details at

the end of this data sheet. Additional details of the MPI are provided below.

Microprocessor Interface (MPI)

The LatticeSC family devices have a dedicated synchronous MPI function block.The MPI is programmable to oper-

ate with PowerPC/PowerQUICC MPC860/MPC8260 series microprocessors. The MPI implements an 8-, 16-, or

32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor (PowerPC) that can be used for conﬁguration

and read-back of the FPGA as well as for user-deﬁned data processing and general monitoring of FPGA functions.

The control portion of the MPI is available following power-up of the FPGA if the mode pins specify MPI mode, even

if the FPGA is not yet conﬁgured.The width of the data port is selectable among 8-, 16-, or 32-bit and the parity bus

can be 1-, 2-, or 4-bit. In conﬁguration mode the data and parity bus width are related to the state of the M[0:3]

mode pins. For post-conﬁguration use, the MPI must be included in the conﬁguration bit stream by using an MPI

library element in your design from the ispLEVER primitive library, or by setting the bit of the MPI conﬁguration con-

trol register prior to the start of conﬁguration. The user can also enable and disable the parity bus through the con-

ﬁguration bit stream. These pads can be used as general I/O when they are not needed for MPI use.

The MPI block also provides the capability to interface directly to the FPGA fabric with a databus after conﬁgura-

tion.The bus protocol is still handled by the MPI block but the direct FPGA access allows high-speed block data

transfers such as DMA transactions. Figure 2-32 shows one of the ways a PowerPC is connected to MPI.

2-37

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 2-32. PowerPCI and MPI Schematic

PowerPC

LatticeSC FPGA

TSZ[0:1]

RETRY

TEA

MPI_TSZ[0:1]

MPI_RTRY

MPI_TEA

BURST

MPI_BURST

1, 2, 4

DP[0:m]

To Daisy-

Chained

Devices

DOUT

CCLK

8, 16, 32

D[0:n]

A[14:31]

CLKOUT

RD/WR

TA

D[0:n]

PPC_A[14:31]

MPI_CLK

MPI_RW

MPI_ACK

MPI_BDIP

MPI_IRQ

MPI_STRB

CS0

BDIP

IRQx

TS

DONE

INIT

HDC

LDC

CS1

Bus

Controller

Conﬁguration and Testing

The following section describes the conﬁguration and testing features of the LatticeSC family of devices.

IEEE 1149.1-Compliant Boundary Scan Testability

All LatticeSC devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access

port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan

path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in

and loaded directly onto test nodes, or test data to be captured and shifted out for veriﬁcation. The test access port

consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage V

and can

CCJ

operate with LVCMOS33, 25 and 18 standards. For additional detail refer to technical information at the end of the

data sheet.

Device Conﬁguration

All LatticeSC devices contain three possible ports that can be used for device conﬁguration. The serial port, which

supports bit-wide conﬁguration, and the sysCONFIG port that supports both byte-wide and serial conﬁguration.

The MPI port supports 8-bit, 16-bit or 32-bit conﬁguration.

The serial port supports both the IEEE Std. 1149.1 Boundary Scan speciﬁcation and the IEEE Std. 1532 In-System

Conﬁguration speciﬁcation. The sysCONFIG port is a 20-pin interface with six of the I/Os used as dedicated pins

and the rest being dual-use pins. When sysCONFIG mode is not used, these dual-use pins are available for gen-

eral purpose I/O. All I/Os for the sysCONFIG and MPI ports are in I/O bank #1.

On power-up, the FPGA SRAM is ready to be conﬁgured with the sysCONFIG port active. The IEEE 1149.1 serial

mode can be activated any time after power-up by sending the appropriate command through the TAP port. Once a

conﬁguration port is selected, that port is locked and another conﬁguration port cannot be activated until the next

re-initialization sequence. For additional detail refer to technical information at the end of the data sheet.

2-38

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Internal Logic Analyzer Capability (ispTRACY)

All LatticeSC devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabil-

ities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace mem-

ory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile

time. For additional detail refer to technical information at the end of the data sheet.

Temperature Sensing

Lattice provides a way to monitor the die temperature by using a temperature-sensing diode that is designed into

every LatticeSC device. The difference in V of the diode at two different forward currents varies with temperature.

BE

This relationship is shown in Figure 2-33. The accuracy of the temperature-sensing diode is typically +/- 10°C.

On packages that include PROBE_GND, the most accurate measurements will occur between the TEMP pin and

the PROBE_GND pin. On packages that do not include PROBE_GND, measurements should be made between

the TEMP pin and board ground.

This temperature-sensing diode is designed to work with an external temperature sensor such as the Maxim

1617A. The Maxim 1617A is conﬁgured to measure difference in V (of the temperature-sensing diode) at 10µA

BE

and at 100µA. This difference in V voltage varies with temperature at approximately 1.64 mV/°C. A typical device

BE

with a 85°C junction temperature will measure approximately 593mV. For additional detail refer to the temperature-

sensing diode technical note, TN1115.

Figure 2-33. Sensing Diode Typical Characteristics

0.88

0.80

100μA

0.75

0.70

0.65

0.55

0.50

10μA

V_BEdifference

increases with

temperature

-50

-25

0

25

50

75

100

125

Junction Temperature (°C)

Oscillator

Every LatticeSC device has an internal CMOS oscillator, which is used as a master serial clock for conﬁguration

and is also available as a potential general purpose clock (MCK) for the FPGA core. There is a K divider (divide by

2/4/8/16/32/64/128) available with this oscillator to get lower MCK frequencies. This clock is available as a general

purpose clock signal to the software routing tool. For additional detail refer to technical information at the end of the

data sheet.

2-39

Architecture

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Density Shifting

The LatticeSC family has been designed to ensure that different density devices in the same package have the

same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from

lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design tar-

geted for a high-density device to a lower density device. However, the exact details of the ﬁnal resource utilization

will impact the likely success in each case.

2-40

LatticeSC/M Family Data Sheet

DC and Switching Characteristics

Data Sheet DS1004

June 2008

Absolute Maximum Ratings

Supply Voltage V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.6V

CC, CC12, DDIB, DDOB

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V

CCAUX, DDAX25, TT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V

CCJ

(Banks 1, 4, 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V

(Banks 2, 3, 6, 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.75V

CCIO

Input or I/O Tristate Voltage Applied (Banks 1, 4, 5) . . . . . . . . . . . . . . . . . . . -0.5 to 3.6V

Input or I/O Tristate Voltage Applied (Banks 2, 3, 6, 7) . . . . . . . . . . . . . . . . -0.5 to 2.75V

Storage Temperature (Ambient). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C

Junction Temperature Under Bias (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Notes:

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. Undershoot and overshoot of -2V to (VIHMAX +2) volts is permitted for a duration of <20ns.

Recommended Operating Conditions

Symbol

Parameter

Min.

0.95

2.375

1.14

Max.

1.26

Units

5

V

Core Supply Voltage (Nominal 1.2V Operation)

Programmable I/O Auxiliary Supply Voltage

V

CC

6

2.625

3.45

CCAUX

1, 2, 5, 6

Programmable I/O Driver Supply Voltage (Banks 1, 4, 5)

Programmable I/O Driver Supply Voltage (Banks 2, 3, 6, 7)

CCIO

1, 2, 5, 6

2.625

Internal 1.2V Power Supply Voltage for Conﬁguration Logic and

FPGA PLL, SERDES PLL Power Supply Voltage and SERDES

Analog Supply Voltage

4, 5

V

1.14

1.26

V

CC12

V

SERDES Input Buffer Supply Voltage

1.14

2.375

1.71

0.5

1.575

2.625

3.45

V

C

DDIB

SERDES Output Buffer Supply Voltage

DDOB

SERDES Termination Auxiliary Supply Voltage

Supply Voltage for IEEE 1149.1 Test Access Port

Programmable I/O Termination Power Supply

Junction Temperature, Commercial Operation

Junction Temperature, Industrial Operation

DDAX25

1, 5

CCJ

2, 3

V

- 0.5

TT

CCAUX

t

0

+85

105

JCOM

JIND

-40

1. If V

or V

is set to 2.5V, they must be connected to the same power supply as V

.

CCAUX

CCIO

CCJ

2. See recommended voltages by I/O standard in subsequent table.

3. When V termination is not required, or used to provide the common mode termination voltage (V

), these pins can be left unconnected

CMT

TT

on the device.

4. V

cannot be lower than V at any time. For 1.2V operation, it is recommended that the V and V

supplies be tied together with

CC12

CC

proper noise decoupling between the digital VCC and analog VCC12 supplies.

5. V (all banks), V and V must reach their minimum values before conﬁguration will proceed.

V

CC, CCIO

CC12

CCJ

6. If V

for a bank is nominally 1.2V/1.5V/1.8V, then V

must always be higher than V

during power up.

CCIO

CCAUX

CCIO

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

3-1

DS1004 DC and Switching_01.9

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Power Supply Ramp Rates

Symbol

Parameter

Condition

Min.

3.45

—

Typ.

—

Max

—

Units

mV/µs

ms

Over process, voltage,

temperature

t

Power supply ramp rates for all power supplies

RAMP

—

75

1. See the Power-up and Power-Down requirements section for more details on power sequencing.

2. From 0.5V to minimum operating voltage.

Hot Socketing Speciﬁcations¹

Symbol

Parameter

Condition

0 <= V <= V (MAX)

Min.

Typ.

Max

Units

Programmable and dedicated Input or I/O leakage

current^{2, 3, 4, 5, 6}

I

—

1500

µA

DK

IN

IH

SERDES average input current when device powered

down and inputs driven⁷

I

—

4

mA

HDIN

1. See Hot Socket power up/down information in Chapter 2 of this document.

2. Assumes monotonic rise/fall rates for all power supplies.

3. Sensitive to power supply sequencing as described in hot socketing section.

4. Assumes power supplies are between 0 and maximum recommended operations conditions.

5. IDK is additive to I , I or I

.

BH

PU PD

6. Represents DC conditions. For the ﬁrst 20ns after hot insertion, current speciﬁcation is 8 mA.

7. Assumes that the device is powered down with all supplies grounded, both P and N inputs driven by a CML driver with maximum allowed

VDDOB of 1.575V, 8b/10b data and internal AC coupling.

DC Electrical Characteristics⁵

Over Recommended Operating Conditions

Symbol

Parameter

Condition

Min.³

—

Typ.

—

Max.

10

Units

µA

1

I

Input or I/O Low leakage 0 ≤ V ≤ V (MAX)

IL, IH

IN

IH

I/O Active Pull-up Current 0 ≤ V ≤ 0.7 V

-30

—

-210

µA

PU

PD

IN

CCIO

I/O Active Pull-down Cur-

I

V

(MAX) ≤ V ≤ V (MAX)

30

-30

—

210

—

µA

IL

IN

IH

rent

Bus Hold Low Sustaining

Current

= V (MAX)

BHLS

BHHS

BHLO

IN

IL

Bus Hold High Sustaining

Current

= 0.7V

—

CCIO

Bus Hold Low Overdrive

Current

0 ≤ V ≤ V (MAX)

210

IN

IH

Bus Hold High Overdrive

Current

I

0 ≤ V ≤ V (MAX)

—

-210

—

µA

mA

V

BHLH

IN

IH

PCI Low Clamp Current -3 < V ≤ -1

-25 + (V + 1)/0.015

IN

CL

IN

25 + (V - V -1)/

IN

CC

PCI High Clamp Current

Bus Hold trip Points

V

+ 4 > V ≥ V + 1

—

CH

CC

IN

CC

0.015

V

0 ≤ V ≤ V (MAX)

V

(MAX)

V

(MIN)

IH

BHT

IN

IH

IL

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

CCIO

CC

C1

I/O Capacitance²

= 1.2V, V

= 1.2V,

—

8

6

—

pf

CCIP2

= 2.5, V = 0 to V (MAX)

CCAUX

IO

IH

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

CCIO

CC

Dedicated Input

Capacitance²

C3²

= 1.2V, V

= 1.2V,

—

CCIP2

= 2.5, V = 0 to V (MAX)

CCAUX

IO

IH

1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tri-stated. It is not measured

with the output driver active. Bus maintenance circuits are disabled.

2. T 25°C, f = 1.0MHz

A

3. I

I

, I

and I

have minimum values of 15 or -15µA if V

is set to 1.2V nominal.

CCIO

PU, PD BHLS

BHHS

4. This table does not apply to SERDES pins.

5. For programmable I/Os.

3-2

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Initialization and Standby Supply Current

The table below indicates initialization and standby supply current while operating at 85°C junction temperature

(T ), which is the high end of the commercial temperature range, and 105°C, which is the high end of the industrial

J

temperature range. This data assumes all outputs are tri-stated and all inputs are conﬁgured as LVCMOS and held

at V

or GND. The remaining SERDES supply current for V

and V

is detailed in the SERDES section

CCIO

DDIB

DDOB

of this data sheet. For power at your design temperature, it is recommended to use the Power Calculator tool which

is accessible in ispLEVER or can be used as a standalone tool. For more information on supply current, see the

reference to additional technical documentation available at the end of this data sheet.

Over Recommended Operating Conditions

25°C

Typ.¹

85°C

105°C

Max.²

Max.²Units

Symbol

Condition

Parameter

Device

LFSC/M15

LFSC/M25

LFSC/M40

LFSC/M80

All

65

-5, -6

-7

678

1255

2006

3827

—

-5, -6

449

798

1178

2122

3376

312

554

818

1473

2344

39

755

1343

1981

3569

5679

524

933

1375

2478

3943

35

mA

113

159

276

Core Operating Power Supply

Current

(VCC = 1.2V +/- 5%)

LFSC/M115 454

I

CC

LFSC/M15

LFSC/M25

LFSC/M40

LFSC/M80

45

79

471

872

1393

2658

—

Core Operating Power Supply

Current

(VCC = 1.0V +/- 5%)

110

191

LFSC/M115 315

LFSC/M15

LFSC/M25

LFSC/M40

LFSC/M80

LFSC/M115

LFSC/M15

LFSC/M25

LFSC/M40

LFSC/M80

LFSC/M115

LFSC/M15

LFSC/M25

LFSC/M40

LFSC/M80

LFSC/M115

23

25

31

50

65

7

59

1.2V Power Supply Current for

Conﬁguration Logic, FPGA PLL,

SERDES PLL and SERDES

Analog Supplies

50

78

56

I

78

133

195

—

89

CC12

108

131

12

123

154

14

19

9

16

25

18

Auxiliary Operating Power Supply

Current

12

13

16

0.1

0.3

0.4

0.5

0.7

23

39

25

CCAUX

25

45

23

27

—

26

0.2

0.3

1.0

1.5

2.1

—

0.2

0.6

0.7

I

and

Bank Power Supply Current

(per bank)

CCIO

CCJ

0.9

1.0

1.1

1.3

1.5

1.8

1. I is speciﬁed at T = 25°C and typical V .

CC

J

2. I is speciﬁed at the respective commercial and industrial maximum T and V limits.

CC

J

CC

3-3

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

PURESPEED I/O Recommended Operating Conditions

V

(V)

V

(V)

CCIO

REF

Standard

LVCMOS 33

Min.

3.135

2.375

1.71

1.425

1.14

3.135

1.425

3.135

1.71

2.375

3.135

1.425

1.71

—

Typ.

3.3

2.5

1.8

1.5

1.2

3.3

1.5

3.3

1.8

2.5

3.3

1.5

1.8

—

Max.

3.465

2.625

1.89

1.575

1.26

3.465

1.575

3.465

1.89

2.625

3.465

1.575

1.89

—

Min.

—

Typ.

—

Max.

—

LVCMOS 25

—

LVCMOS 18

—

LVCMOS 15

—

LVCMOS 12

—

LVTTL

—

PCI33

—

PCIX33

—

PCIX15

0.49V

0.5V

0.51V

CCIO

AGP1X33

—

AGP2X33

0.39V

0.4V

0.41V

CCIO

SSTL18_I, II³

SSTL25_I, II³

SSTL33_I, II³

HSTL15_I, II³

HSTL15_III^{1, 3}and IV^{1, 3}

HSTL 18_I³, II³

HSTL 18_ III^{1, 3}, IV^{1, 3}

GTL12^{1, 3}, GTLPLUS15^{1, 3}

LVDS

0.833

0.9

0.969

1.15

1.3

0.68

0.816

0.882

—

1.25

1.5

0.75

0.9

1.08

1.0

—

1.35

1.7

0.9

1.08

1.122

—

Mini-LVDS

—

RSDS

—

HYPT (Hyper Transport)

LVPECL33 (outputs)²

LVPECL33 (inputs)^{2, 4}

BLVDS25^{2, 3}

—

3.135

—

3.3

≤ 2.5

2.5

1.8

2.5

3.3

1.5

1.8

3.465

—

2.375

1.71

2.375

3.135

1.425

1.71

2.625

1.89

2.625

3.465

1.575

1.89

—

MLVDS25^{2, 3}

—

SSTL18D_I³, II³

SSTL25D_I³, II³

SSTL33D_I³, II³

HSTL15D_I³, II³

HSTL18D_I³, II³

1. Input only.

—

2. Inputs on chip. Outputs are implemented with the addition of external resisters.

3. Input for this standard does not depend on the value of V

.

CCIO

4. Inputs for this standard cannot be in 3.3V VCCIO banks (≤ 2.5V only).

3-4

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

PURESPEED I/O Single-Ended DC Electrical Characteristics

Over Recommended Operating Conditions

V

IH

IL

Input/Output

Standard

V

Max.

V

Min.

I

OH

OL

(V)

OH

(V)

OL

Min. (V)

Max. (V)

Min. (V)

Max. (V)

(mA)

24, 16, 8

0.1

(mA)

-24, -16, -8

-0.1

LVCMOS 33

-0.3

0.8

0.7

2

3.465

0.4

0.2

0.4

0.2

0.4

0.2

0.4

0.2

0.4

0.2

0.3

0.2

2.4

VCCIO - 0.2

2.4

LVTTL

-0.3

2

3.465

2.65

1.5

24, 16, 8

0.1

-24, -16, -8

-0.1

VCCIO - 0.2

LVCMOS 25

LVCMOS 18

LVCMOS 15

LVCMOS 12

1.7

VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4

VCCIO - 0.2 0.1 -0.1

VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4

VCCIO - 0.2 0.1 -0.1

VCCIO - 0.4 16, 12, 8, 4 -16, -12, -8, -4

VCCIO - 0.2 0.1 -0.1

VCCIO - 0.3 12, 8, 4, 2 -12, -8, -4, -2

0.35VCCIO

0.65VCCIO

VCCIO - 0.2

0.1

1.5

8

-0.1

-0.5

-8

PCIX15

-0.3

0.3VCCIO

0.35VCCIO

0.3VCCIO

VREF - 0.2

0.5VCCIO

VREF + 0.2

0.1VCCIO 0.9VCCIO

PCI33

3.465 0.1VCCIO 0.9VCCIO

PCIX33

AGP-1X, AGP-2X

SSTL3_I

3.465

2.65

0.7

0.9

VCCIO - 1.1

VCCIO - 1.3

VCCIO - 0.9

VCCIO - 0.13

VCCIO - 0.62

VCCIO - 0.81

VCCIO - 0.43

VCCIO - 0.81

VCCIO - 0.28

VCCIO - 0.4

N/A

SSTS3_I OST²

SSTL3_II

SSTL3_II OST²

8

-8

0.5

16

-16

0.9

16

-16

SSTL2_I

VREF - 0.18 VREF + 0.18

0.54

0.73

0.35

0.73

0.28

0.4

7.6

15.2

13.4

8

-7.6

-15.2

-13.4

-8

SSTL2_I OST²

SSTL2_II

SSTL2_II OST²

SSTL18_I

-0.3 VREF - 0.125 VREF + 0.125

SSTL18_II

HSTL15_I

-0.3

VREF - 0.1

VREF + 0.1

HSTL15_II

HSTL15_III1

HSTL15_IV1

HSTL18_I

0.4

16

-16

N/A

0.4

N/A

9.6

19.2

N/A

-9.6

-19.2

N/A

VCCIO - 0.4

N/A

HSTL18_II

HSTL18_III1

HSTL18_IV1

0.4

N/A

GTL12¹,

-0.3

VREF - 0.2

VREF + 0.2

N/A

GTLPLUS15¹

1. Input only.

2. Input with on-chip series termination.

3-5

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

PURESPEED I/O Differential Electrical Characteristics

LVDS

Over Recommended Operating Conditions

Parameter

Symbol

Parameter Description

Input voltage

Test Conditions

Min.

0

Typ.

—

Max.

2.4

Units

V

INP, INM

Differential input threshold (Q-Q)

Input common mode voltage

Input current

+/-100

0.05

—

mV

V

THD

CM

1.2

—

2.35

+/-10

1.60

—

I

Power on or power off

µA

V

IN

V

Output high voltage for V or V

R = 100 Ohm

—

1.38

1.03

350

OH

OL

OD

OP

OM

T

Output low voltage for V or V

R = 100 Ohm

0.9V

250

V

OP

OM

T

Output voltage differential

(V - V ), R = 100 Ohm

450

mV

OP

OM

T

Change in V between high and

low

OD

ΔV

—

50

mV

OD

V

Output voltage offset

(V - V )/2, R = 100 Ohm

1.125

—

1.20

—

1.375

50

V

OS

OP

OM

T

ΔV

Change in V between H and L

mV

OS

V

= 0V Driver outputs

OD

I

Output short circuit current

—

12

mA

SAB

shorted

Notes:

1. Data is for 3.5mA differential current drive. Other differential driver current options are available.

2. If the low power mode of the input buffer is used, the minimum V

is 600 mV.

CM

Hyper Transport

Over Recommended Operating Conditions

Parameter Symbol

Description

Min.

500

-15

Typ.

600

—

Max.

700

15

Units

V

Differential output voltage

mV

OD

ΔV

Change in V magnitude

OD

V

Output common mode voltage

560

-15

600

—

640

15

OCM

ΔV

Change in V

magnitude

OCM

V

Input differential voltage

Input common mode voltage

500

-15

600

—

700

15

ID

ΔV

ID

V

500

-15

600

—

700

15

ICM

ΔV

Change in V

magnitude

ICM

Notes:

1. Data is for 6mA differential current drive. Other differential driver current options are available.

2. If the low power mode of the input buffer is used, the minimum V is 600 mV.

CM

3-6

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Mini-LVDS

Over Recommended Operating Conditions

Parameter Symbol

Description

Min.

30

Typ.

50

100

—

Max.

75

Units

ohms

mV

Z

Single-ended PCB trace impedance

Differential termination resistance

O

R

60

150

600

1.4

50

T

V

Output voltage, differential, |V - V |

OM

300

1

OD

OS

OP

Output voltage, common mode, |V + V |/2

1.2

—

V

OP

OM

ΔV

Change in V , between H and L

—

mV

OD

ID

OD

Change in V , between H and L

—

50

mV

OS

V

Input voltage, differential, |V

- V |

INM

200

—

600

mV

THD

CM

INP

Input voltage, common mode, |V

+ V |/2 0.3+(V

/2)

—

2.1-(V

/2)

INP

INM

THD

T , T

Output rise and fall times, 20% to 80%

Output clock duty cycle

—

500

55

ps

%

R

F

T

45

40

—

ODUTY

T

Input clock duty cycle

—

60

IDUTY

Note: Data is for 6mA differential current drive. Other differential driver current options are available.

RSDS

Over Recommended Operating Conditions

Parameter Symbol

Description

Min.

100

0.5

1

Typ.

Max.

Units

mV

V

Output voltage, differential, R = 100 ohms

200

1.2

2

600

1.5

6

OD

OS

T

V

Output voltage, common mode

Differential driver output current

Input voltage differential

I

mA

mV

V

RSDS

V

100

0.3

—

THD

CM

Input common mode voltage

Output rise and fall times, 20% to 80%

Output clock duty cycle

—

1.5

—

T , T

500

50

ps

R

F

T

45

55

%

ODUTY

Note: Data is for 2mA drive. Other differential driver current options are available.

3-7

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Differential HSTL and SSTL

Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-

able single-ended output classes (class I and class II) are supported in this mode.

MLVDS

The LatticeSC devices support the MLVDS standard. This industry standard is emulated using controlled imped-

ance complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs.

MLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The

scheme shown in Figure 3-1 is one possible solution for bi-directional multi-point differential signals.

Figure 3-1. MLVDS Multi-Point Output Example

Heavily loaded backplane, effective Zo ~ 50 to 70 ohms differential

2.5V

50

50-70 ohms, +/- 1%

50

. . .

+

-

+

-

+

2.5V

50

Table 3-1. MLVDS DC Conditions¹

Over Recommended Operating Conditions

Nominal

Symbol

Description

Output impedance

Zo = 50 Zo = 70

Units

ohm

V

Z

50

70

OUT

R

Left end termination

Right end termination

Output high voltage

50

TLEFT

TRIGHT

OH

50

70

V

1.50

1.00

0.50

1.25

20.0

1.575

0.925

0.65

1.25

18.5

Output low voltage

V

OL

Output differential voltage

Output common mode voltage

DC output current

V

OD

V

CM

I

mA

DC

1. For input buffer, see LVDS table.

3-8

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

BLVDS

The LatticeSC devices support BLVDS standard. This standard is emulated using controlled impedance comple-

mentary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is

intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown

in Figure 3-2 is one possible solution for bi-directional multi-point differential signals.

Figure 3-2. BLVDS Multi-point Output Example

Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential

2.5V

100

45-90 ohms, +/- 1%

100

. . .

+

-

+

-

+

2.5V

100

2.5V

100

2.5V

100

2.5V

100

Table 3-2. BLVDS DC Conditions¹

Over Recommended Operating Conditions

Nominal

Symbol

Description

Output impedance

Zo = 45 Zo = 90

Units

ohm

V

Z

100

45

100

90

OUT

R

Left end termination

Right end termination

Output high voltage

TLEFT

TRIGHT

OH

45

90

V

1.375

1.125

0.25

1.25

11.2

1.48

1.02

0.46

1.25

10.2

Output low voltage

V

OL

Output differential voltage

Output common mode voltage

DC output current

V

OD

V

CM

I

mA

DC

1. For input buffer, see LVDS table.

3-9

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LVPECL

The LatticeSC devices support differential LVPECL standard. This standard is emulated using controlled imped-

ance complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs.The scheme

shown in Figure 3-3 is one possible solution for point-to-point signals.

Figure 3-3. Differential LVPECL

3.3V

85 ohms

24mA

~16 ohms

+/-1%

+

150

ohms

100

ohms

Zback

3.3V

-

85 ohms

+/-1%

24mA

~16 ohms

Transmission line, Zo = 100 ohm differential

OFF-chip

ON-chip

Table 3-3. LVPECL DC Conditions¹

Over Recommended Operating Conditions

Symbol

Description

Output impedance

Nominal

16

Units

ohm

V

Z

OUT

R

Driver series resistor

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

85

S

P

T

150

100

V

2.03

1.27

0.76

1.65

86

OH

V

OL

Output differential voltage

Output common mode voltage

Back impedance

V

OD

V

CM

Z

ohm

mA

BACK

I

DC output current

12.6

DC

1. For input buffer, see LVDS table.

For further information on LVPECL, BLVDS, MLVDS and other differential interfaces please see details of additional

technical documentation at the end of this data sheet.

On-die Differential Common Mode Termination

Symbol

Description

Min.

Typ.

Max.

Units

C

Capacitance V to GND

—

40

—

pF

CMT

3-10

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Typical Building Block Function Performance

Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%

Pin to Pin Performance (LVCMOS25 12 mA Drive)

Function

-7*

Units

Basic Functions

32-bit Decoder

6.65

5.58

ns

Combinatorial (Pin to LUT to Pin)

Embedded Memory Functions (Single Port RAM)

Pin to EBR Input Register Setup (Global Clock)

EBR Output Clock to Pin (Global Clock)

Distributed (PFU) RAM (Single Port RAM)

Pin to PFU RAM Register Setup (Global Clock)

PFU RAM Clock to Pin (Global Clock)

*Typical performance per function

1.66

8.54

ns

1.32

6.83

ns

Register-to-Register Performance

Function

-7*

Units

Basic Functions

32-Bit Decoder

64-Bit Decoder

16:1 MUX

539

517

1003

798

672

353

719

369

768

545

MHz

32:1 MUX

16-Bit Adder

64-Bit Adder

16-Bit Counter

64-Bit Counter

32x8 SP RAM (PFU, Output Registered)

128x8 SP RAM (PFU, Output Registered)

Embedded Memory Functions

Single Port RAM (512x36 Bits)

372

326

372

353

375

372

MHz

True Dual Port RAM 1024x18 Bits (No EBR Out Reg)

True dual port RAM 1024x18 Bits (EBR Reg)

FIFO port (A: x36 bits, B: x9 Bits, No EBR Out Reg)

FIFO port (A: x36 bits, B: x9 Bits, EBR Reg)

True DP RAM Width Cascading (1024x72)

DSP Functions

9x9 1-stage Multiplier

209

155

373

314

372

MHz

18x18 1-Stage Multiplier

9x9 3-Stage Pipelined Multiplier

18x18 4-Stage Pipelined Multiplier

9x9 Constant Multiplier

*Typical performance per function

3-11

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Switching Characteristics

All devices are 100% functionally tested. Listed below are representative values of internal and external timing

parameters. For more speciﬁc, more precise, and worst-case guaranteed data at a particular temperature and volt-

age, use the values reported by the static timing analyzer in the ispLEVER design tool from Lattice and back-anno-

tate to the simulation net list.

3-12

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LatticeSC/M External Switching Characteristics³

Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%

-7

-6

-5

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

General I/O Pin Parameters (using Primary Clock without PLL)²

Global Clock Input to Output - PIO Output Reg-

ister

t

2.83

-0.66

1.73

0.86

-0.17

5.74

—

2.83

-0.66

1.95

1.03

-0.17

6.11

—

2.83

-0.66

2.16

1.20

-0.17

6.49

—

ns

CO

Global Clock Input Setup - PIO Input Register

without ﬁxed input delay

SU

Global Clock Input Hold - PIO Input Register

without ﬁxed input delay

—

H

Global Clock Input Setup - PIO Input Register

with input delay

—

SU_IDLY

H_IDLY

Global Clock Input Hold - PIO Input Register

with input delay

—

f

t

Global Clock frequency of PFU register

Global Clock frequency of I/O register

Global Clock skew

—

700

1000

89

—

700

1000

103

—

700

1000

116

MHz

ps

MAX_PFU

MAX_IO

GC_SKEW

General I/O Pin Parameters (using Primary Clock with PLL)^{1, 2}

Global Clock Input to Output - PIO Output Reg-

ister

t

2.25

-0.07

0.80

4.81

—

2.25

-0.07

0.93

5.08

—

2.25

-0.07

1.04

5.37

—

ns

CO

SU

H

Global Clock Input Setup - PIO Input Register

without ﬁxed input delay

Global Clock Input Hold - PIO Input Register

without ﬁxed input delay

—

General I/O Pin Parameters (using Edge Clock without PLL)²

Edge Clock Input to Output - PIO Output Regis-

ter

t

2.38

4.77

2.38

5.04

2.38

5.33

ns

CO

Edge Clock Input Setup - PIO Input Register

without ﬁxed input delay

t

-0.08

0.49

0.81

—

-0.08

0.58

0.97

—

-0.08

0.66

1.12

—

ns

SU

Edge Clock Input Hold - PIO Input Register

H

Edge Clock Input Setup - PIO Input Register

with input delay

SU_IDLY

Edge Clock Input Hold - PIO Input Register with

input delay

t

-0.34

—

-0.34

—

-0.34

—

ns

ps

H_IDLY

Edge Clock skew

28

32

36

EC_SKEW

General I/O Pin Parameters (using Latch FF without PLL)²

Latch FF, Input Setup - PIO Input Register with-

out ﬁxed input delay

t

-0.14

0.58

0.70

-0.30

—

-0.14

0.68

-0.30

—

-0.14

0.77

-0.30

—

ns

SU

Latch FF, Input Hold - PIO Input Register without

ﬁxed input delay

H

Latch FF, Input Setup - PIO Input Register with

input delay

SU_IDLY

Latch FF, Input Hold - PIO Input Register with

input delay

H_IDLY

1. No PLL delay tuning (clock injection removal mode, system clock feedback).

2. Using LVCMOS25 12mA I/O.Timing adders for other supported I/O technologies are speciﬁed in the LatticeSC Family Timing Adders table.

3. Complete Timing Parameters for a user design are incorporated when running ispLEVER. This is a sampling of the key timing parameters.

Timing specs are for non-AIL applications.

3-13

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LatticeSC/M Family Timing Adders

Over Recommended Operating Conditions at VCC = 1.2V +/- 5%

-7

-6

-5

Buffer Type

Input Adjusters

LVDS

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

LVDS

-0.031

-0.02

-0.031

-0.029

-0.031

-0.015

-0.018

0.001

-0.016

-0.015

-0.022

-0.061

0.012

-0.008

0

-0.011

-0.001

-0.011

0.015

0.008

0.029

0.026

0.015

0.001

-0.181

0.034

0.03

-0.011

-0.004

-0.011

0.007

0.003

0.024

-0.001

0.007

-0.009

-0.313

0.028

0.011

0.023

0.007

0.024

-0.05

0.009

0.02

0.009

0.017

0.009

0.029

0.023

0.046

0.014

0.029

0.003

-0.565

0.043

0.03

ns

RSDS

BLVDS

MLVDS

BLVDS25

MLVDS25

HYPT

Hypertransport

LVPECL33

HSTL18_I

HSTL18_II

HSTL18_III

HSTL18_IV

HSTL18D_I

HSTL18D_II

HSTL15_I

HSTL15_II

HSTL15_III

HSTL15_IV

HSTL15D_I

HSTL15D_II

SSTL33_I

SSTL33_II

SSTL33D_I

SSTL33D_II

SSTL25_I

SSTL25_II

SSTL25D_I

SSTL25D_II

SSTL18_I

SSTL18_II

SSTL18D_I

SSTL18D_II

LVTTL33

LVPECL

-0.031

-0.013

-0.016

0.006

-0.005

-0.013

-0.021

-0.036

0.012

0.003

0.006

-0.013

0.006

0.009

0.042

0.032

0.052

0.057

0.042

0.022

-0.326

0.055

0.058

0.056

0.042

0.052

-0.134

0

HSTL_18 class I

HSTL_18 class II

HSTL_18 class III

HSTL_18 class IV

Differential HSTL 18 class I

Differential HSTL 18 class II

HSTL_15 class I

HSTL_15 class II

HSTL_15 class III

HSTL_15 class IV

Differential HSTL 15 class I

Differential HSTL 15 class II

SSTL_3 class I

SSTL_3 class II

Differential SSTL_3 class I

Differential SSTL_3 class II

SSTL_2 class I

SSTL_2 class II

0.03

Differential SSTL_2 class I

Differential SSTL_2 class II

SSTL_18 class I

0.031

0.015

0.029

-0.05

0

0.046

0.029

0.046

-0.134

0

-0.015

0.001

0.034

0

SSTL_18 class II

Differential SSTL_18 class I

Differential SSTL_18 class II 0.006

LVTTL

0.034

0

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

PCI33

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

PCI

-0.05

0

-0.068

-0.131

-0.238

0.034

-0.005

0.034

-0.068

-0.131

-0.238

0.034

-0.016

0.034

-0.087

-0.186

-0.364

-0.05

0.026

-0.05

-0.087

-0.186

-0.364

-0.05

-0.105

-0.241

-0.49

-0.105

-0.241

-0.49

-0.134

0.014

-0.134

0.057

-0.134

PCIX33

PCI-X 3.3

PCI-X 1.5

AGP-1X 3.3

-0.05

PCIX15

-0.001

-0.05

AGP1X33

3-14

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LatticeSC/M Family Timing Adders (Continued)

Over Recommended Operating Conditions at VCC = 1.2V +/- 5%

-7

-6

-5

Buffer Type

AGP2X33

Description

AGP-2X

Min.

Max.

-0.061

-0.017

-0.071

Min.

-0.181

0.012

-0.007

Max.

-0.313

0.004

-0.048

Min.

-0.326

0.037

0.056

Max.

-0.565

0.024

-0.032

Units

ns

-0.036

-0.013

-0.063

GTLPLUS15

GTL12

GTLPLUS15

GTL12

ns

Output Adjusters

LVDS

0.708

-0.129

-0.059

-0.334

0.677

0.132

0.24

0.854

0.05

0.856

-0.136

-0.057

-0.325

0.83

1.021

0.069

0.096

-1.389

1.027

0.24

1.005

-0.136

-0.054

-0.315

0.984

0.175

0.298

0.175

0.298

0.129

0.259

0.129

0.259

0.088

0.156

0.088

0.156

0.264

0.345

0.264

0.345

0.199

0.295

0.199

0.295

-0.646

-0.325

-0.185

-0.646

-0.325

-0.185

-0.215

0

1.189

0.083

0.133

-2.598

1.201

0.272

0.333

0.272

0.333

0.224

0.275

0.224

0.275

0.154

0.258

0.154

0.258

0.331

0.387

0.331

0.387

0.265

0.338

0.265

0.338

-0.428

-0.46

-0.463

-0.428

-0.46

-0.463

0

ns

RSDS

BLVDS25

BLVDS

MLVDS25

MLVDS

0.059

-0.181

0.854

0.209

0.176

0.209

0.176

0.172

0.131

0.172

0.131

0.177

0.247

0.177

0.247

0.125

0.181

0.125

0.181

0.081

0.15

LVPECL33

LVPECL

HYPT

Hypertransport

HSTL18_I

HSTL_18 class I

0.153

0.268

0.153

0.268

0.112

0.233

0.112

0.233

0.11

HSTL18_II

HSTL_18 class II

0.255

0.24

HSTL18D_I

HSTL18D_II

HSTL15_I

Differential HSTL 18 class I

Differential HSTL 18 class II

HSTL_15 class I

0.132

0.24

0.255

0.198

0.203

0.198

0.203

0.166

0.253

0.166

0.253

0.228

0.284

0.228

0.284

0.173

0.244

0.173

0.244

-0.296

-0.32

-0.321

-0.296

-0.32

-0.321

0.002

0

0.096

0.208

0.096

0.208

0.133

0.173

0.133

0.173

0.215

0.277

0.215

0.277

0.16

HSTL15_II

HSTL_15 class II

HSTL15D_I

HSTL15D_II

SSTL33_I

Differential HSTL 15 class I

Differential HSTL 15 class II

SSTL_3 class I

SSTL33_II

SSTL_3 class II

0.164

0.11

SSTL33D_I

SSTL33D_II

SSTL25_I

Differential SSTL_3 class I

Differential SSTL_3 class II

SSTL_2 class I

0.164

0.239

0.311

0.239

0.311

0.179

0.263

0.179

0.263

-0.496

-0.218

-0.099

-0.496

-0.218

-0.099

-0.195

0

SSTL25_II

SSTL_2 class II

SSTL25D_I

SSTL25D_II

SSTL18_I

Differential SSTL_2 class I

Differential SSTL_2 class II

SSTL_2 class I

SSTL18_II

SSTL_2 class II

0.238

0.16

SSTL18D_I

SSTL18D_II

LVTTL33_8mA

LVTTL33_16mA

LVTTL33_24mA

LVCMOS33_8mA

LVCMOS33_16mA

LVCMOS33_24mA

LVCMOS25_4mA

LVCMOS25_8mA

LVCMOS25_12mA

LVCMOS25_16mA

LVCMOS25_OD

Differential SSTL_2 class I

Differential SSTL_2 class II

LVTTL 8mA drive

0.081

0.15

0.238

-0.346

-0.11

-0.012

-0.346

-0.11

-0.012

-0.174

0

-0.165

-0.18

-0.165

-0.18

0.004

0

LVTTL 16mA drive

LVTTL 24mA drive

LVCMOS 3.3 8mA drive

LVCMOS 3.3 16mA drive

LVCMOS 3.3 24mA drive

LVCMOS 2.5 4mA drive

LVCMOS 2.5 8mA drive

LVCMOS 2.5 12mA drive

LVCMOS 2.5 16mA drive

LVCMOS 2.5 open drain

0

0.094

0.145

0.073

-0.025

-0.054

-0.125

0.107

0.162

0.081

0.096

0.063

-0.081

0.12

0.216

0.179

-0.09

0.181

0.091

3-15

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LatticeSC/M Family Timing Adders (Continued)

Over Recommended Operating Conditions at VCC = 1.2V +/- 5%

-7

-6

-5

Buffer Type

LVCMOS18_4mA

LVCMOS18_8mA

LVCMOS18_12mA

LVCMOS18_16mA

LVCMOS18_OD

LVCMOS15_4mA

LVCMOS15_8mA

LVCMOS15_12mA

LVCMOS15_16mA

LVCMOS15_OD

LVCMOS12_2mA

LVCMOS12_4mA

LVCMOS12_8mA

LVCMOS12_12mA

LVCMOS12_OD

PCI33

Description

LVCMOS 1.8 4mA drive

LVCMOS 1.8 8mA drive

LVCMOS 1.8 12mA drive

LVCMOS 1.8 16mA drive

LVCMOS 1.8 open drain

LVCMOS 1.5 4mA drive

LVCMOS 1.5 8mA drive

LVCMOS 1.5 12mA drive

LVCMOS 1.5 16mA drive

LVCMOS 1.5 open drain

LVCMOS 1.2 2mA drive

LVCMOS 1.2 4mA drive

LVCMOS 1.2 8mA drive

LVCMOS 1.2 12mA drive

LVCMOS 1.2 open drain

PCI

Min.

Max.

-0.099

-0.078

-0.106

-0.134

-0.206

-0.164

-0.137

-0.166

-0.195

-0.267

-0.293

-0.239

-0.269

-0.3

Min.

-0.312

-0.078

0.019

0.08

Max.

-0.115

-0.084

-0.004

-0.022

-0.196

-0.186

-0.157

-0.07

Min.

Max.

-0.131

-0.089

0.099

0.089

-0.221

-0.209

-0.176

0.026

0.017

-0.299

-0.34

Units

ns

-0.278

-0.073

0.024

0.074

0.002

-0.344

-0.125

-0.027

0.025

-0.047

-0.473

-0.218

-0.109

-0.054

-0.126

-0.216

0.208

-0.216

-0.345

-0.083

0.016

0.088

-0.002

-0.412

-0.164

-0.059

0.003

-0.087

-0.537

-0.28

0

-0.379

-0.145

-0.043

0.013

-0.067

-0.505

-0.25

-0.089

-0.267

-0.317

-0.271

-0.181

-0.203

-0.398

-1.263

0.312

-0.303

-0.093

-0.106

-0.43

-0.143

-0.085

-0.166

-0.417

0.233

-0.417

-0.176

-0.114

-0.204

-0.618

0.259

-0.618

-0.371

-0.791

0.227

-0.791

-1.735

0.398

-1.735

PCIX33

PCI-X 3.3

PCIX15

PCI-X 1.5

AGP1X33

AGP-1X 3.3

-1.263

AGP2X33

AGP-2X

3-16

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LatticeSC/M Internal Timing Parameters¹

Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%

-7

-6

-5

Parameter

Symbol

Description

Min. Max. Min. Max. Min. Max. Units

PFU Logic Mode Timing

t

CTOF_DEL

LUT4 delay (A to D inputs to F output)

—

0.045

0.152

0.378

—

0.050

0.172

0.426

—

0.054

0.192

0.474

ns

LUT4_PFU

LUT5_PFU

LSR_PFU

MTOOFX_DEL LUT5 delay (inputs to output)

LSR_DEL

Set/Reset to output (asynchronous)

Clock to Mux (M0,M1) input setup

time

t

M_SET

0.113

—

0.131

—

0.148

—

ns

SUM_PFU

t

M_HLD

Clock to Mux (M0,M1) input hold time -0.041

—

-0.046

0.083

-0.032

—

-0.052

0.094

-0.035

—

ns

HM_PFU

SUD_PFU

HD_PFU

DIN_SET

DIN_HLD

Clock to D input setup time

Clock to D input hold time

0.072

-0.028

Clock to Q delay, D-type register

conﬁguration

t

REG_DEL

LTCH_DEL

TLTCH_DEL

—

0.224

0.294

0.300

—

0.252

0.331

0.338

—

0.279

0.367

0.376

ns

CK2Q_PFU

LE2Q_PFU

LD2Q_PFU

Clock to Q delay latch conﬁguration

D to Q throughput delay when latch is

enabled

PFU Memory Mode Timing

t

CLKTOF_DEL Clock to Output

—

0.575

—

0.649

—

0.724

—

ns

CORAM_PFU

SUDATA_PFU

HDATA_PFU

DIN_SET

DIN_HLD

WAD_SET

WAD_HLD

WE_SET

WE_HLD

Data Setup Time

-0.024

0.075

-0.176

0.110

0.014

0.078

-0.026

0.084

-0.196

0.124

0.019

0.086

-0.027

0.094

-0.215

0.138

0.024

0.094

Data Hold Time

—

Address Setup Time

Address Hold Time

—

SUADDR_PFU

HADDR_PFU

SUWREN_PFU

HWREN_PFU

—

Write/Read Enable Setup Time

Write/Read Enable Hold Time

—

PIC Timing

PIO Input/Output Buffer Timing

t

IN_DEL

Input Buffer Delay(LVCMOS25)

—

0.578

2.712

—

0.661

3.027

—

0.744

3.395

ns

IN_PIO

DOPADI_DEL Output Buffer Delay(LVCMOS25)

OUT_PIO

Input Register Setup Time (Data

Before Clock)

t

DIN_SET

-0.156

-0.267

—

-0.175

-0.306

—

-0.194

-0.345

—

ns

SUI_PIO

Input Register Hold Time (Data after

DIN_HLD

Clock)

—

HI_PIO

Output Register Clock to Output

CK_DEL

Delay

0.513

0.000

0.129

0.571

0.000

0.145

0.639

0.000

0.161

COO_PIO

SUCE_PIO

HCE_PIO

Input Register Clock Enable Setup

CE_SET

Time

—

Input Register Clock Enable Hold

CE_HLD

Time

—

t

LSR_SET

LSR_HLD

Set/Reset Setup Time

Set/Reset Hold Time

0.057

—

0.060

—

0.063

—

ns

SULSR_PIO

-0.151

-0.159

-0.169

HLSR_PIO

Input Register Clock to Q delay latch

conﬁguration

t

CK_DEL

DIN_DEL

—

0.335

0.578

—

0.372

0.647

—

0.410

0.717

ns

LE2Q_PIO

LD2Q_PIO

Input Register D to Q throughput

delay when latch is enabled

t

3-17

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LatticeSC/M Internal Timing Parameters¹(Continued)

Over Recommended Commercial Operating Conditions at VCC = 1.2V +/- 5%

-7

-6

-5

Parameter

Symbol

Description

Min. Max. Min. Max. Min. Max. Units

EBR Timing

Clock (Read) to output from Address

or Data

t

CK_Q_DEL

—

1.900

—

2.116

—

2.335

—

ns

CO_EBR

Clock (Write) to output from EBR

output Register

0.390

-0.173

0.444

0.498

COO_EBR

Setup Data to EBR Memory (Write

clk)

t

D_CK_SET

D_CK_HLD

A_CK_SET

—

-0.192

0.305

-0.182

—

-0.210

0.335

-0.200

—

ns

SUDATA_EBR

Hold Data to EBR Memory (Write clk) 0.276

HDATA_EBR

Setup Address to EBR Memory

(Write clk)

-0.165

SUADDR_EBR

Hold Address to EBR Memory (Write

clk)

t

A_CK_HLD

0.269

—

0.298

0.226

0.095

0.269

0.039

—

0.327

0.226

0.116

0.276

0.055

—

ns

HADDR_EBR

SUWREN_EBR

HWREN_EBR

SUCE_EBR

HCE_EBR

Setup Write/Read Enable to EBR

0.225

CE_CK_SET

CE_CK_HLD

CS_CK_SET

CS_CK_HLD

RESET_Q_DEL

Memory (Write/Read clk)

Hold Write/Read Enable to EBR

0.073

—

Memory (write/read clk)

Clock Enable Setup Time to EBR

0.261

—

Output Register (Read clk)

Clock Enable Hold Time to EBR Out-

0.023

—

put Register (Read clk)

Reset To Output Delay Time from

—

0.589

0.673

0.757

RSTO_EBR

EBR Output Register (asynchronous)

Cycle Boosting Timing

Cycle boosting delay 1 applies to

PIO, PFU, EBR

t

DEL1

DEL2

DEL3

—

0.480

0.922

1.366

—

0.524

1.005

1.488

—

0.570

1.090

1.612

ns

DEL1

DEL2

DEL3

Cycle boosting delay 2 applies to

PIO, PFU, EBR

—

Cycle boosting delay 3 applies to

PIO, PFU, EBR

—

1. Complete timing parameters for a user design will be incorporated when running ispLEVER.This is a sampling of the key timing parameters.

3-18

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Input Delay Block/AIL Timing

Parameter

Description

Fine delay time

Min.

Typ.

45

Max.

80

Units

ps

t

35

FDEL

CDEL

Coarse delay time

AIL jitter tolerance

1120

1440

2560

ps

jt

1- ((N¹* t

) / (Clock Period))

FDEL

UI

AIL

1. N = number of ﬁne delays used in a particular AIL setting

GSR Timing

-7

-6

-5

Parameter

Description

VCC

1.14V

0.95V

Min.

—

Max.

438

Min.

—

Max.

Min.

Max. Units

417

355

—

398

337

MHz

Maximum operating frequency for

synchronous GSR

t

SYNC_GSR_MAX

—

378

—

Minimum pulse width of

asynchronous input

—

3.3

—

ns

ASYNC_GSR_MPW

Note: Synchronous GSR goes out of reset in two cycles from the clock edge where the setup time of the FF was met.

Internal System Bus Timing

-7

-6

-5

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max. Units

200 MHz

Maximum operating frequency for internal

system bus HCLK.

t

—

200

—

200

—

HCLK

Note: There is no minimum frequency. If HCLK is sourced from the embedded oscillator, the minimum frequency limitation of the oscillator/

divider is about 0.3 MHz. Refer to the osciallator data for missing conﬁguration modes.

3-19

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Timing Diagrams

PFU Timing Diagrams

Figure 3-4. Slice Single/Dual Port Write Cycle Timing

CK

WRE

AD

D

DI

Old Data

D

DO

Notes:

• Rising Edge for latching WREN, WAD and DATAIN.

• WREN must continue past falling edge clock.

• Data output occurs on negative edge.

Figure 3-5. Slice Single/Dual Port Read Cycle Timing

CK

WRE

AD

DO

Old Data

D

3-20

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

EBR Memory Timing Diagrams

Figure 3-6. Read Mode

CLKA

CSA

WEA

ADA

DIA

A0

A1

D1

A0

A1

A0

t_SUt_H

D0

t_ACCESS

D0

Invalid Data

D1

DOA

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.

Figure 3-7. Read Mode with Input Registers Only

CLKA

CSA

WEA

A0

A1

D1

A0

ADA

DIA

A1

t

H

SU

D0

t

ACCESS

Invalid Data

D0

DOA

D1

output is only updated during a read cycle

3-21

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 3-8. Read Mode with Input and Output Registers

CLKA

CSA

WEA

A1

A0

A1

D1

A0

ADA

DIA

t

H

SU

D0

D1

D0

Mem(n) data from previous read

D0

DOA

t

ACCESS

D1

D0

DOA (Registered)

Mem(n) data from previous read

output is only updated during a read cycle

Figure 3-9. Write Through (SP Read/Write On Port A, Input Registers Only)

CLKA

CSA

WEA

Three consecutive writes to A0

A0

A1

D1

ADA

DIA

A0

t

H

SU

D2

D3

D2

D4

D0

t

ACCESS

Data from Prev Read

or Write

D0

D1

D3

DOA

D4

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.

3-22

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 3-10. FIFO Reset Waveform

Asynchronous RESET, RESET pulse width (t ),

RW

RESET to Flag valid (t

), RESET hold time (t

)

RSF

RSH

t

RW

RST

RE

t

RSH

t

RSU

t

RSF

EF, AE flags

t

RSH

t

RSU

WE

t

RSF

FF, AF flags

DO

Note: RE and WE must be deactivated t

before the Positive FIFO reset edge and enabled t

after the FIFO reset negative edge.

RSH

RSU

Figure 3-11. Read Pointer Reset Waveform

RESET pulse width (t ), RESET to Flag valid (t

RW RSF

),

RESET hold time (t

)

RSH

RST_B

t

RW

t

RSH

RSU

RE

RCLK

t

RSF

t

ACCESS_E

EF, AE flags

t

RSH

RSU

WE

WCLK

t

ACCESS_F

FF, AF flags

Note: RE and WE must be deactivated t

before the Positive FIFO reset edge and enabled t

after the FIFO reset negative edge.

RSH

RSU

3-23

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Figure 3-12. Waveforms First Read after Full Flag

CS

Last Write (FIFO FULL)

WCLK

t

SU1

H1

WE

t

FF (flag)

SKEW

CO

t

CO

RCLK

RE

t

H1

SU1

First Read

Figure 3-13. Waveform First Write after Empty Flag

CS

Last Read (FIFO Empty)

RCLK

RE

t

H1

SU1

t

SKEW

CO

EF (flag)

WCLK

WE

t

CO

t

H1

SU1

First Write

3-24

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

sysCLOCK PLL Timing

Over Recommended Operating Conditions

Parameter

Description

Conditions

Min.

Typ

Max.

Units

f

Input Clock Frequency (CLKI, CLKFB)

2

—

1000

MHz

IN

Output Clock Frequency (CLKOP,

CLKOS)

f

1.5625

—

1000

MHz

OUT

f

PLL VCO Frequency

100

2

—

1000

700

MHz

VCO

Phase Detector Input Frequency

PFD

AC Characteristics

Default duty cycle selected

(at 50% levels)

t

Output Clock Duty Cycle

45

—

55

%

DT

2 MHz ≤ f

≤ 10 MHz

—

200

100

ps

PFD

1

t

Output Clock Period Jitter

OPJIT

f

> 10 MHz

PFD

1

Output Clock Cycle-to-Cycle Jitter

CPJIT

Output Clock-to-Clock Skew (Between

Two Outputs with the Same Phase Set-

ting)

t

—

20

ps

SKEW

t

f

PLL Lock-in Time

—

1

250

—

ms

ps

ns

ps

KHz

%

LOCK

IPJIT

HI

Input Clock Period Jitter

Input Clock High Time

At 80% level

At 20% level

350

100

3

—

Input Clock Low Time

—

LO

Analog Reset Signal Pulse Width

Digital Reset Signal Pulse Width

Timeshift Delay Step Size

Timeshift Delay Range

—

RSWA

RSWD

DEL

—

40

—

80

120

—

+/- 560

—

RANGE

SS

Spread Spectrum Modulation Frequency

30

0.5

-5

500

1.5

5

% Spread Percentage Downspread for SS Mode

VCO Clock Phase Adjustment Accuracy

—

°

1. Values are measured with FPGA logic active, no additional I/Os toggling and REFCLK total jitter = 30 ps

3-25

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

sysCLOCK DLL Timing

Over Recommended Operating Conditions

Parameter

Description

Conditions

Min.

100

25

Typ.

—

Max.

700

Units

MHz

f

Input Clock Frequency (CLKI, CLKFB)

Output Clock Frequency (CLKOP)

Output Clock Frequency (CLKOS)

IN

—

OUTOP

OUTOS

—

AC Characteristics

Output Clock Duty Cycle (at 50%

levels, 50% duty cycle input clock,

duty cycle correction turned off,

time reference delay mode)

t

Output Clock Duty Cycle

38

45

40

—

62

55

60

%

DUTY

Output Clock Duty Cycle (at 50%

levels, arbitrary duty cycle input

clock, duty cycle correction turned

on, time reference delay mode)

DUTYRD

DUTYCIR

Output Clock Duty Cycle (at 50%

levels, arbitrary duty cycle input

clock, duty cycle correction turned

on, clock injection removal mode)

1

t

Output Clock Period Jitter

—

200

ps

OPJIT

1

Output Clock Cycle-to-Cycle Jitter

CPJIT

Output Clock to Clock Skew (Between

Two Outputs with the Same Phase

Setting)

t

—

100

ps

SKEW

t

DLL Lock-in Time

8

35

—

45

18500 cycles

LOCK

IDUTY

IPJIT

HI

Input Clock Duty Cycle

Input Clock Period Jitter

Input Clock High Time

Input Clock Low Time

Reset Signal Pulse Width

Timeshift Delay Step Size

Applies to all operating conditions

65

+/- 250

—

%

ps

ns

ps

At 80% level

At 20% level

500

3

—

LO

—

RSWD

FDEL

35

80

Delay Through the DLL when No Delay

Taps are Chosen but Not in Bypass

Mode.

t

—

760

—

ps

DLL

1. Values are measured with FPGA logic active, no additional I/Os toggling and REFCLK total jitter = 30 ps.

3-26

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LatticeSC/M sysCONFIG Port Timing

Over Recommended Operating Conditions

Parameter

Description

Min.

Max.

Units

General Conﬁguration Timing

t

M[3:0] Setup Time to INITN High

0

—

ns

SMODE

HMODE

M[3:0] Hold Time from INITN High

600

50 (or 100 at

0.95V)

t

RESETN Pulse Width Low to Start Reconﬁguration (1.2 V)

—

ns

RW

50 (or 100 at

0.95V)

t

f

PROGRAMN Pulse Width Low to Start Reconﬁguration (1.2 V)

System Bus ESB_CLK Frequency (No Wait States)

—

ns

PGW

—

133

MHz

ESB_CLK_FRQ

sysCONFIG Master Parallel Conﬁguration Mode

t

D[7:0] Setup Time to RCLK High

D[7:0] Hold Time to RCLK High

6

0

—

ns

SMB

HMB

CCLK

periods

RCLK Low Time (Non-compressed Bitstreams)

RCLK Low Time (Compressed Bitstreams)

RCLK High Time

0.5

7.5

0.5

t

CLMB

CHMB

CCLK

periods

CCLK

periods

t

sysCONFIG SPI Port

t

INITN High to CSCK Low

—

0

80

2

ns

µs

ns

CFGX

CSSPI

SCK

INITN High to CSSPIN Low

CSCK Low before CSSPIN Low

CSCK Low to Output Valid

0

—

15

—

SOCDO

CSPID

CSSPIN Low to CSCK high Setup Time

Max CCLK Frequency - SPI Flash Fast Read Opcode (0x0B)

(SPIFASTN=0)

f

—

50

MHz

MAXSPI

t

SOSPI/D0 Data Setup Time Before CSCK

SOSPI/D0 Data Hold Time After CSCK

7

2

—

ns

SUSPI

HSPI

Selected

value - 30% value + 30%

Selected

Master Clock Frequency

Duty Cycle

MHz

%

40

60

sysCONFIG Master Serial Conﬁguration Mode

t

f

t

DIN Setup Time

4.4

0

—

ns

SMS

HMS

CMS

C_DIV

D

DIN Hold Time

CCLK Frequency (No Divider)

CCLK Frequency (Div 128)

CCLK to DOUT Delay

90

190

1.48

7.5

MHz

ns

0.70

—

sysCONFIG Master Parallel Conﬁguration Mode

t

RCLK to Address Valid

—

6

10

—

ns

AVMP

SMP

D[7:0] Setup Time to RCLK High

D[7:0] Hold Time to RCLK High

0

—

HMP

RCLK Low Time (Non-compressed Bitstream)

RCLK Low Time (Compressed Bitstream)

7.5

0.5

7.5

63.5

CCLK

periods

t

CLMP

CCLK

periods

t

RCLK High Time

CCLK to DOUT

0.5

—

0.5

7.5

CHMP

ns

DMP

3-27

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LatticeSC/M sysCONFIG Port Timing (Continued)

Over Recommended Operating Conditions

Parameter

Description

Min.

Max.

Units

sysCONFIG Asynchronous Peripheral Conﬁguration Mode

t

WRN, CS0N and CS1 Pulse Width

D[7:0] Setup Time

5

-

ns

WRAP

1.5

—

SAP

RDY Delay

8

RDYAP

CCLK

periods

t

RDY Low

1

8

BAP

t

Earliest WRN After RDY Goes High

RDN to D[7:0] Enable/Disable

CCLK to DOUT

0

—

ns

WR2AP

DENAP

DAP

—

7.5

sysCONFIG Slave Serial Conﬁguration Mode

t

f

t

DIN Setup Time

DIN Hold Time

CCLK High Time

CCLK Low Time

CCLK Frequency

CCLK to DOUT

5.2

0

—

ns

SSS

HSS

CHSS

CLSS

CSS

DSS

3.75

—

ns

—

ns

150

7.5

MHz

ns

—

sysCONFIG Slave Parallel Conﬁguration Mode

t

f

CS0N, CS1, WRN Setup Time

CS0N, CS1, WRN Hold Time

D[7:0] Setup Time

5.2

0

—

ns

S1SP

H1SP

S2SP

H2SP

CHSP

CL

5.2

0

—

ns

D[7:0] Hold Time

—

ns

CCLK High Time

3.75

—

ns

CCLK Low Time

—

ns

CCLK Frequency

150

MHz

CSP

sysCONFIG MPI Port

Parameter

-7

-6

-5

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

MPI Control (MPCSTRBN, MPCWRN,

MPCCLK, etc.) to MPCCLK Setup Time

t

4.9

—

5.2

—

5.5

—

ns

MPICTRL_SET

t

MPI Address to MPCCLK Setup Time

MPI Write Data to MPCCLK Setup Time

3.9

4.9

—

4.2

5.2

—

4.5

5.5

—

ns

MPIADR_SET

MPIDAT_SET

MPI Write Parity Data to MPCCLK Setup

Time

t

3.9

0

—

4.2

0

—

4.5

0

—

ns

MPIDPAR_SET

MPI_HLD

All Hold Times

MPCCLK to MPI Control (MPCTA, MPC-

TEA, MPCRETRY)

—

5.6

—

6.7

—

8.7

MPICTRL_DEL

t

f

MPCCLK to MPI Data

MPCCLK to MPI Parity Data

MPCCLK Frequency

—

5.6

4.9

—

6.7

5.7

83

—

8.7

7.7

66

ns

MPIDAT_DEL

MPIDPAR_DEL

MPI_CLK_FRQ

100

MHz

3-28

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

JTAG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Symbol

Parameter

Min.

Max.

25

—

Units

MHz

ns

f

t

—

40

50

—

8

MAX

TCK [BSCAN] Clock Pulse Width

BTCP

TCK [BSCAN] Clock Pulse Width High

TCK [BSCAN] Clock Pulse Width Low

TCK [BSCAN] Setup Time

—

mV/ns

ns

BTCPH

BTCPL

BTS

10

—

ns

TCK [BSCAN] Hold Time

ns

BTH

TCK [BSCAN] Rise/Fall Time

10

20

—

8

—

ns

BTRF

TAP Controller Falling Edge of Clock to Valid Output

TAP Controller Falling Edge of Clock to Valid Disable

TAP Controller Falling Edge of Clock to Valid Enable

BSCAN Test Capture Register Setup Time

BSCAN Test Capture Register Hold Time

—

ns

BTCO

—

ns

BTCODIS

BTCOEN

BTCRS

BTCRH

10

—

ns

10

—

ns

BSCAN Test Update Register, Falling Edge of Clock

to Valid Output

t

—

25

ns

BUTCO

BSCAN Test Update Register, Falling Edge of Clock

to Valid Disable

BTUODIS

BTUPOEN

BSCAN Test Update Register, Falling Edge of Clock

to Valid Enable

Figure 3-14. JTAG Port Timing Waveforms

TMS

TDI

t

BTH

BTS

t

BTCP

BTCPL

BTCPH

TCK

TDO

t

BTCODIS

t

BTCO

BTCOEN

Valid Data

t

BTCRH

t

BTCRS

Data to be

captured

from I/O

Data Captured

t

BTUPOEN

BUTCO

BTUODIS

Data to be

driven out

to I/O

Valid Data

3-29

DC and Switching Characteristics

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Switching Test Conditions

Figure 3-15 shows the output test load that is used for AC testing. The speciﬁc values for resistance, capacitance,

voltage, and other test conditions are shown in Table 3-4.

Figure 3-15. Output Test Load, LVTTL and LVCMOS Standards

DUT

Test Point

CL

Table 3-4. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

C

Timing Ref.

V

T

L

LVCMOS 3.3 = 1.5V

—

LVCMOS 2.5 = V

/2

CCIO

LVTTL and other LVCMOS settings (L -> H, H -> L)

30pF LVCMOS 1.8 = V

LVCMOS 1.5 = V

LVCMOS 1.2 = V

LVCMOS 2.5 I/O (Z -> H)

LVCMOS 2.5 I/O (Z -> L)

LVCMOS 2.5 I/O (H -> Z)

LVCMOS 2.5 I/O (L -> Z)

V

/2

V

OL

CCIO

V

OH

30pF

V

- 0.15

+ 0.15

V

OL

OH

V

OH

OL

Note: Output test conditions for all other interfaces are determined by the respective standards.

3-30

LatticeSC/M Family Data Sheet

Pinout Information

Data Sheet DS1004

January 2008

Signal Descriptions

Signal Name

I/O

Description

General Purpose

[Edge] indicates the edge of the device on which the pad is located.

Valid edge designations are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PIC row or the column of the

device on which the PIC exists. When Edge is T (Top) or (Bottom),

only need to specify Row Number. When Edge is L (Left) or R (Right),

only need to specify Column Number.

[A/B/C/D] indicates the PIO within the PIC to which the pad is con-

nected.

P[Edge] [Row/Column Number*]_[A/B/C/D]

I/O

Some of these user programmable pins are shared with special func-

tion pins. These pin when not used as special purpose pins can be

programmed as I/Os for user logic.

During conﬁguration the user-programmable I/Os are tri-stated with an

internal pull-up resistor enabled. If any pin is not used (or not bonded

to a package pin), it is also tri-stated with an internal pull-up resistor

enabled after conﬁguration.

The reference supply pins for I/O bank x. Any I/O pin in a bank can be

assigned as a reference supply pin, but software defaults use desig-

nated pin.

VREF1_x, VREF2_x

NC

—

No connect. NC pins should not be connected to any active signals,

VCC or GND.

Non-SERDES Power Supplies

VCCIOx

—

VCCIO - The power supply pins for I/O bank x. Dedicated pins.

1.2V supply for conﬁguration logic, PLLs and SERDES Rx, Tx and

PLL. All VCC12 pins must be connected. As VCC12 supplies power

for analog circuitry, VCC12 should be quiet and isolated from noisy

digital board supplies.

VCC12¹

VTT_x

Termination voltage for bank x. When VTT termination is not required,

or used to provide the common mode termination voltage (VCMT),

these pins can be left unconnected on the device. VCMT function is

not used in the bank. If the internal or external VCMT function for dif-

ferential input termination is used, the VTT pins should be uncon-

nected and allowed to ﬂoat.

—

GND - Ground. Dedicated pins. All grounds must be electrically con-

nected at the board level.

GND

VCC

—

VCC - The power supply pins for core logic. Dedicated pins (1.2V/

1.0V).

VCCAUX - Auxiliary power supply pin - powers all differential and

referenced input buffers. Dedicated pins (2.5V).

VCCAUX

VCCJ

—

VCCJ - The power supply pin for JTAG Test Access Port.

VCC signal - Connected to internal VCC node. Can be used for feed-

back to control an external board power converter. Can be uncon-

nected if not used.

PROBE_VCC

—

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

4-1

DS1004 Pinouts_01.8

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Signal Descriptions (Cont.)

Signal Name

I/O

Description

GND signal - Connected to internal VSS node. Can be used for feed-

back to control an external board power converter. Can be uncon-

nected if not used.

PROBE_GND

—

PLL and Clock Functions (Used as user-programmable I/O pins when not in use for PLL, DLL or clock pins.)

PLL feedback input. Pull-ups are enabled on input pins during conﬁgu-

ration. [LOC] indicates the corner the PLL is located in: ULC (upper

left), URC (upper right), LLC (lower left) and LRC (lower right). [T, C]

indicates whether input is true or complement. [A, B] indicates PLL ref-

erence within the corner.

[LOC]_PLL[T, C]_FB_[A/B]

[LOC]_DLL[T, C]_FB_[C, D, E, F]

[LOC]_PLL[T, C]_IN[A/B]

I

DLL feedback input. Pull-ups are enabled on input pins during conﬁgu-

ration. [LOC] indicates the corner the DLL is located in: ULC (upper

left), URC (upper right), LLC (lower left) and LRC (lower right). [T/C]

indicates whether input is true or complement. [C, D, E, F] indicates

DLL reference within a corner. Note: E and F are only available on the

lower corners.

PLL reference clock input. Pull-ups are enabled on input pins during

conﬁguration. [LOC] indicates the corner the PLL is located in: ULC

(upper left corner), URC (upper right corner), LLC (lower left corner)

and LRC (lower right corner). [T, C] indicates whether input is true or

complement.[A, B] indicates PLL reference within the corner.

DLL reference clock inputs. Pull-ups are enabled on input pins during

conﬁguration. [LOC] indicates the corner the DLL is located in: ULC

(upper left corner), URC (upper right corner), LLC (lower left corner)

and LRC (lower right corner). [T/C] indicates whether input is true or

complement. [C, D, E, F] indicates DLL reference within a corner.

Note: E and F are only available on the lower corners. PCKLxy_[0:3]

can drive primary clocks, edge clocks, and CLKDIVs. PCLKxy_[4:7]

can only drive edge clocks.

[LOC]_DLL[T, C]_IN[C, D, E, F]

General clock inputs. x indicates whether T (true) or C (complement).

y indicates the I/O bank the clock is associated with. z indicates the

clock number within a bank.

PCLKxy_z

Test and Programming (Dedicated pins. Pull-up is enabled on input pins during conﬁguration.)

TMS

TCK

I

Test Mode Select input, used to control the 1149.1 state machine.

Test Clock input pin, used to clock the 1149.1 state machine.

Test Data in pin, used to load data into device using 1149.1 state

machine. After power-up, this TAP port can be activated for conﬁgura-

tion by sending appropriate command. (Note: once a conﬁguration

port is selected it is locked. Another conﬁguration port cannot be

selected until the power-up sequence).

TDI

I

Output pin -Test Data out pin used to shift data out of device using

1149.1.

TDO

O

Conﬁguration Pads (Dedicated pins. Used during sysCONFIG.)

Mode pins used to specify conﬁguration modes values latched on ris-

ing edge of INITN.

M[3:0]

I

I/O

I

Open Drain pin - Indicates the FPGA is ready to be conﬁgured. During

conﬁguration, a pull-up is enabled that will pull the I/O above 1.5V.

INITN

Initiates conﬁguration sequence when asserted low. This pin always

has an active pull-up.

PROGRAMN

Open Drain pin - Indicates that the conﬁguration sequence is com-

plete, and the startup sequence is in progress.

DONE

CCLK

I/O

Conﬁguration Clock for conﬁguring an FPGA in sysCONFIG mode.

4-2

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Signal Descriptions (Cont.)

Signal Name

I/O

Description

Reset. (Also sent to general routing). During conﬁguration it resets the

conﬁguration state machine. After conﬁguration this pin can perform

the global set/reset (GSR) functions or can be used as a general input

pin.

RESETN

MPI Interrupt request active low signal is controlled by system bus

interrupt controller and may be sourced from any bus error or MPI con-

ﬁguration error. It can be connected to one of MPC860 IRQ pins.

CFGIRQN

TSALLN

O

I

Tristates all I/O.

Conﬁguration Pads (User I/O if not used. Used during sysCONFIG.)

High During Conﬁguration is output high until conﬁguration is com-

plete. It is used as a control output, indicating that conﬁguration is not

complete.

For SPI modes, this pin is used to download the read command and

initial read address into the Flash memory device on the falling edge

of SCK. This pin will be connected to SI of the memory. If the SPI

mode is used, the 8-bit instruction code 0x03 will be downloaded fol-

lowed by a 24-bit starting address of 0x000000 or a non-zero stat

address for partial reconﬁguration. If the SPIX mode has been

selected, the 8-bit instruction captured on D[7:0] at power-up will be

shifted in and followed by a 32-bit starting address of 0x000000.

HDC/SI

O

Low During Conﬁguration is output low until conﬁguration is complete.

It is used as a control output, indicating that conﬁguration is not com-

plete.

For SPI modes, this is an active low chip select for Flash memories. It

will go active after INITN goes high but before SCK begins. During

power up LDCN will be low. Once INITN goes high, LDCN will go high

for 100ns-200ns after which time it will go back low and conﬁguration

can begin. During the 100ns-200ns period, the read instruction will be

latched for SPIX mode.

LDCN/SCS

O

Serial data output that can drive the D0/DIN of daisy-chained slave

devices.The data-stream from this output will propagate preamble bits

of the bitstream to daisy-chained devices. Data out on DOUT changes

on the rising edge of CCLK.

DOUT

O

During daisy-chaining conﬁguration, QOUT is the serial data output

that can drive the D0/DIN of daisy-chained slave devices that do not

propagate preamble bits. Data out on QOUT changes on the rising

edge of CCLK.

QOUT/CEON

During parallel-chaining conﬁguration, active low CEON enables the

cascaded slave device to receive bitstream data.

Used in the asynchronous peripheral conﬁguration mode. A low on

RDN changes D[7:3] into status outputs.WRN and RDN should not be

used simultaneously. If they are, the write strobe overrides.

RDN

I

When the FPGA is selected, a low on the write strobe, WRN, loads the

data on D[7:0] inputs into an internal data buffer.

WRN

Used in the asynchronous peripheral, slave parallel and MPI modes.

The FPGA is selected when CS0N is low and CS1 is high. During con-

ﬁguration, a pull-up is enabled on both except with MPI DMA access

control.

CS0N CS1

A[21:0]

I

In master parallel mode, A[21:0] is an output and will address the con-

ﬁguration EPROMs up to 4 MB space. For MPI conﬁguration mode,

A[17:0] will be the MPI address MPI_ADDR[31:14], A[19:18] will be

the transfer size and A[21:20] will be the burst mode and burst in pro-

cess.

I/O

4-3

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Signal Descriptions (Cont.)

Signal Name

I/O

Description

In parallel conﬁguration modes, D[7:0] receives conﬁguration data,

and each pin is pull-up enabled. For slave serial mode, D0 is the data

input.

D[7:3] is the output internal status for peripheral mode when RDN is

low.

D[n:0]

I/O

D[7:0] is also the ﬁrst byte of MPI data pins.

In MPI conﬁguration mode, MPI selectable data bus width from 8 and

16-bit. Driven by a bus master in a write transaction. Driven by MPI in

a read transaction.

MPI selectable parity data bus width from 1, 2, and 3-bit DP[0] for

D[7:0], DP[1] for D[15:8], and DP[2] for D[23:16].

DP[m:0]

I/O

During conﬁguration in peripheral mode, high on BUSYN indicates

another byte can be written to the FPGA. If a read operation is done

when the device is selected, the same status is also available on D[7]

in asynchronous peripheral mode.

During conﬁguration in slave parallel mode, low on BUSYN inhibits the

external host from sending new data. The output is used by slave par-

allel and master serial modes only for decompression.

BUSYN/RCLK/SCK

O

During conﬁguration in master parallel and master byte modes, RCLK

is a read clock output signal to an external memory. The RCLK fre-

quency is the same as CCLK when used with uncompressed bit-

streams. RCLK will be 1/8 the frequency of CCLK when the bitstream

is compressed.

During conﬁguration in SPI modes, SCK is generated by the device

and connected to the CLK input of the FLASH memory.

MPI Interface (Dedicated pin)

MPI_IRQ_N

MPI Interrupt request active low signal is controlled by system bus

interrupt controller and may be sourced from any bus error or MPI con-

ﬁguration error. It can be connected to one of MPC860 IRQ pins.

O

MPI Interface (User I/O if MPI is not used.)

MPI chip select pins, active low on MPI_CS0N while active high on

MPI_CS1. Both have to be active during the whole transfer data

phase. During transfer address phase, both can be inactive so that the

decoding for them from address can be slow. If they are active during

address phase, one cycle can be saved for sync read.

MPI_CS0N MPI_CS1

MPI_CLK

I

This is the PowerPC bus clock. It can be a source of the clock for

embedded system bus. If MPI_CLK is used as system bus clock, MPI

will be set into sync mode by default. All of the operation on PowerPC

side of MPI are synchronized to the rising edge of this clock.

Driven by a bus master to indicate the data transfer size for the trans-

action. 01 for byte, 10 for half-word, and 00 for word.

MPI_TSIZ[1:0]

MPI_WR_N

I

Driven high indicates that a read access is in progress. Driven low

indicates that a write access is in process.

Driven active low indicates that a burst transfer is in progress. Driven

high indicates that the current transfer is not a burst.

MPI_BURST

Active low “Burst Data in Process” is driven by a PowerPC processor.

Asserted indicates that the second beat in front of the current one is

requested by the master. Negated before the burst transfer ends to

abort the burst data phase.

MPI_BDIP

I

4-4

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Signal Descriptions (Cont.)

Signal Name

I/O

Description

Driven active low indicates the start of a transaction on the PowerPC

bus. MPI will strobe the address bus at next rising edge of clock.

MPI_STRBN

I

Address bus driven by a PowerPC bus master. Only 18-bit width is

needed. It has to be the least signiﬁcant bit of the PowerPC 32-bit

address A[31:14].

MPI_ADDR[31:14]

MPI_DAT[n:0]

I

Selectable data bus width from 8, and 16-bit. Driven by a bus master

in a write transaction. Driven by MPI in a read transaction.

I/O

Selectable parity bus width from 1, 2, and 3-bit. MPI_DP[0] for

MPI_D[7:0], MPI_DP[1] for MPI_D[15:8] and MPI_DP[2] for

MPI_D[23:16].

MPI_PAR[m:0]

Transfer acknowledge. Driven active low indicates that MPI received

the data on the write cycle or returned data on the read cycle.

MPI_TA

O

Transfer Error Acknowledge. Driven active low indicates that MPI

detects a bus error on the internal system bus for current transaction.

MPI_TEA

MPI_RETRY

Active low MPI Retry requests the MPC860 to relinquish the bus and

retry the cycle.

Multi-chip Alignment (User I/O if not used.)

MCA_DONE_OUT

O

I

Multi-chip alignment done output (to second MCA chip)

Multi-chip alignment done input (from second MCA chip)

Multi-chip alignment clock [1:2] output (sourced by MCA master chip)

Multi-chip alignment clock [1:2] input (from MCA master chip

MCA_DONE_IN

MCA_CLK_P[1:2]_OUT

MCA_CLK_P[1:2]_IN

O

I

Temperature sensing diode pin. Dedicated pin. Accuracy is typically

+/- 10°C.

TEMP

—

Miscellaneous Dedicated Pins

External reference resistor between this pin and ground. The refer-

ence resistor is used to calibrate the programmable terminating resis-

tors used in the I/Os. Dedicated pin. Value: 1K 1% ohm.

XRES

—

Only used if a differential driver is used in a bank. This DIFFRx must

be connected to ground via an external 1K 1% ohm resistor for all

banks that have a differential driver.

DIFFRx

SERDES Block (Dedicated Pins)

[A:D]_HDINPx_[L/R]

High-speed input (positive) channel x on left [L] or right [R] side of

device. PCS quad is deﬁned in the dual function name column of the

Logic Signal Connection table.

I

High-speed input (negative) channel x on left [L] or right [R] side of

device. PCS quad is deﬁned in the dual function name column of the

Logic Signal Connection table.

[A:D]_HDINNx_[L/R]

[A:D]_HDOUTPx_[L/R]

[A:D]_HDOUTNx_[L/R]

I

High-speed output (positive) channel x on left [L] or right [R] side of

device. PCS quad is deﬁned in the dual function name column of the

Logic Signal Connection table.

O

High-speed output (negative) channel x on left [L] or right [R] side of

device. PCS quad is deﬁned in the dual function name column of the

Logic Signal Connection table.

Ref clock input (positive), aux channel on left [L] or right [R] side of

device.

[A:D]_REFCLKP_[L/R]

[A:D]_REFCLKN_[L/R]

I

Ref clock input (negative), aux channel on left [L] or right [R] side of

device.

4-5

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Signal Descriptions (Cont.)

Signal Name

I/O

Description

Calibration resistor to be placed between this pin and either ground or

RESPN_[ULC/URC]. RESPN_[ULC/URC] is available on select pack-

ages. If available, connection of calibration resistor between

RESP_[ULC/URC] and RESPN_[ULC/URC] takes precedence over

connection of calibration resistor between RESP_[ULC/URC] and

ground. Note: only one per side of the device. Value: 4.02K ohm

+/- 1% ohm.

RESP_[ULC/URC]

—

Available on selected packages. If available, calibration resistor should

be placed between RESP_[ULC/URC] and RESPN_[ULC/URC]

instead of between RESP_[ULC/URC] and ground. Note: only one per

side of the device. Value: 4.02K ohm +/- 1% ohm.

RESPN_[ULC/URC]

—

Input buffer power supply for channel x (1.2V/1.5V) on left [L] or right

[R] side of device.

[A:D]_VDDIBx_[L/R]

[A:D]_VDDOBx_[L/R]

[A:D]_VDDAX25_[L/R]

—

Output buffer power supply for channel x (1.2V/1.5V) on left [L] or right

[R] side of device.

Auxiliary power for input and output termination (2.5V) on left [L] or

right [R] side of device.

1. The ispLEVER software tools may specify VDDRX, VDDTX, VDDP and VCCL pins. These pins should be considered VCC12 pins.

Note: Signals listed as Signal A / Signal B deﬁne the same physical pin that is used for different functions based on conﬁguration

mode.

4-6

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Pin Information Summary

256 fpBGA

900 fpBGA

1020 fcBGA

Pin Type

Single Ended User I/O

Differential Pair User I/O

LVDS Output Pairs

LFSC/M15 LFSC/M15 LFSC/M25 LFSC/M25 LFSC/M40

139

60

22

9

300

141

44

378

182

60

476

235

60

562

277

78

Dedicated

11

Conﬁguration

Muxes/MPI sysBus

0

55

72

JTAG (excluding VCCJ)

Dedicated Pins

VCC

4

2

4

10

3

46

40

VCC12

35

36

VCCAUX

36

32

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

18

10

2

14

8

2

15

10

VCCIO

3

15

10

3

15

10

2

15

10

2

16

8

0

2

0

3

0

3

VTT

0

3

0

3

0

2

GND

NC

26

0

177

102

63/30

26/13

43/20

50/22

49/23

43/20

26/13

7

177

24

134

92

134

6

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 2

Bank 3

Bank 6

Bank 7

21/8

15/7

19/8

25/11

19/8

15/7

5

63/30

30/15

62/29

66/32

65/32

62/29

30/15

9

68/32

34/17

84/42

84/41

88/44

84/42

34/17

9

68/32

54/27

94/47

99/48

99/49

94/47

54/27

15

Single Ended User /

Differential I/O per Bank

6

15

21

24

LVDS Output Pairs Per Bank

VCCJ

6

15

21

24

5

7

9

15

1

SERDES (signal + power supply)

Total

28

256

60

108

1020

108

1152

900

4-7

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Pin Information Summary (Cont.)

1152 fcBGA

1704 fcBGA

Pin Type

Single Ended User I/O

Differential Pair User I/O

LVDS Output Pairs

LFSC/M40 LFSC/M80 LFSC/M115 LFSC/M80 LFSC/M115

604

302

78

660

330

102

11

660

330

102

11

904

452

114

11

942

470

132

11

Dedicated

Conﬁguration

11

Muxes/MPI sysBus

72

JTAG (excluding VCCJ)

Dedicated Pins

VCC

4

44

76

VCC12

52

88

VCCAUX

38

52

Bank 1

10

Bank 2

9

12

Bank 3

12

14

VCCIO

Bank 4

Bank 5

Bank 6

Bank 7

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

12

14

12

14

12

14

9

12

3

4

3

4

3

5

VTT

3

5

3

4

3

4

GND

NC

130

62

130

6

130

6

184

52

184

14

Bank 1

Bank 2

Bank 3

Bank 4

Bank 5

Bank 6

Bank 7

Bank 2

Bank 3

Bank 6

Bank 7

80/40

60/30

96/48

106/53

96/48

60/30

15

80/40

76/38

108/54

106/53

108/54

76/38

21

80/40

76/38

108/54

106/53

108/54

76/38

21

80/40

96/48

132/66

184/92

132/66

96/48

24

80/40

103/51

144/72

184/92

144/72

103/51

27

Single Ended User /

Differential I/O per Bank

24

30

33

39

LVDS Output Pairs Per Bank

VCCJ

24

30

33

39

15

21

24

27

1

SERDES (signal + power supply)

Total

108

1152

108

1152

108

1152

212

1704

212

1704

4-8

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15 Logic Signal Connections: 256 fpBGA^1,2

LFSC/M15

Ball Number

E4

B1

C1

D2

F5

Ball Function

A_VDDAX25_L

A_REFCLKP_L

A_REFCLKN_L

RESP_ULC

RESETN

DONE

VCCIO Bank

Dual Function

-

1

7

6

D1

E1

E2

E3

E5

E6

F2

INITN

M0

M1

M2

M3

PL15A

PL15B

PL17A

PL17B

PL18D

PL22A

PL22B

PL22C

PL22D

PL23A

PL23B

PL24A

PL24B

PL24C

PL24D

PL26A

PL26B

PL26C

PL26D

PL28A

PL28B

PL28C

PL28D

PL31C

PL35A

PL35B

PL35D

PL37A

PL37B

PL41D

PL43A

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

VREF2_7

F1

F3

G1

G4

H3

H2

H5

G5

H1

J1

VREF1_7

DIFFR_7

PCLKT7_1

PCLKC7_1

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

J2

J3

H4

H6

J4

K5

J5

J6

K1

L1

L4

PCLKT6_2

PCLKC6_2

VREF1_6

K4

L2

L3

M3

M2

M1

N1

P2

M5

DIFFR_6

VREF2_6

4-9

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15 Logic Signal Connections: 256 fpBGA^1,2(Cont.)

LFSC/M15

Ball Number

M4

P1

Ball Function

PL43B

PL45A

PL45B

XRES

VCCIO Bank

Dual Function

6

-

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

R1

R2

P3

TEMP

6

5

4

R3

PB3A

LLC_PLLT_IN_A/LLC_PLLT_FB_B

LLC_PLLC_IN_A/LLC_PLLC_FB_B

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

VREF1_5

N4

PB3B

T3

PB3C

T2

PB3D

N5

PB5D

P5

PB8A

R5

PB8B

T4

PB9A

T5

PB9B

R6

PB12A

PB12B

PB13C

PB15A

PB15B

PB15D

PB16A

PB16B

PB17A

PB17B

PB20A

PB20B

PB21A

PB21B

PB24A

PB24B

PB28A

PB28B

PB31A

PB31B

PB32A

PB32B

PB35A

PB35B

PB36A

PB36B

PB37A

PB37B

PB37C

PCLKT5_3

PCLKC5_3

T6

L5

P6

PCLKT5_0

PCLKC5_0

VREF2_5

T7

M7

R8

PCLKT5_1

PCLKC5_1

PCLKT5_2

PCLKC5_2

T8

N7

N8

R9

T9

M8

M9

P8

P9

T10

R11

N9

N10

T11

R12

P11

M10

T12

P12

T13

T14

R15

PCLKT4_2

PCLKC4_2

PCLKT4_1

PCLKC4_1

PCLKT4_0

PCLKC4_0

VREF2_4

4-10

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15 Logic Signal Connections: 256 fpBGA^1,2(Cont.)

LFSC/M15

Ball Number

N12

T15

R16

L12

Ball Function

PB39C

PB40A

PB40B

PB43A

PB43B

PB44A

PB44B

PB47C

PB48A

PB48B

PB49A

PB49B

PR45B

PR45A

PR43B

PR43A

PR41D

PR37B

PR37A

PR35D

PR35B

PR35A

PR31C

PR28D

PR28C

PR28B

PR28A

PR26D

PR26C

PR26B

PR26A

PR24D

PR24C

PR24B

PR24A

PR23B

PR23A

PR22D

PR22C

PR22B

PR22A

PR18D

PR17B

VCCIO Bank

Dual Function

4

3

2

PCLKT4_3

PCLKC4_3

M12

P16

N16

R14

P15

M13

N13

P14

M16

L16

VREF1_4

LRC_DLLT_IN_C/LRC_DLLT_FB_D

LRC_DLLC_IN_C/LRC_DLLC_FB_D

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

M14

M15

K16

J16

VREF2_3

DIFFR_3

H16

L13

L14

L15

K12

J13

VREF1_3

PCLKC3_2

PCLKT3_2

K13

H15

F16

J11

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_1

PCLKT2_1

DIFFR_2

J12

J15

J14

E16

D16

H11

H12

H13

H14

G12

G13

F8

VREF1_2

F9

G16

F15

VREF2_2

URC_DLLC_IN_C/URC_DLLC_FB_D

4-11

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15 Logic Signal Connections: 256 fpBGA^1,2(Cont.)

LFSC/M15

Ball Number

F14

E15

E14

D9

Ball Function

PR17A

VCCIO Bank

Dual Function

2

-

URC_DLLT_IN_C/URC_DLLT_FB_D

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

PR15B

PR15A

VCCJ

C16

B15

B16

E13

C14

C15

A15

A14

B14

E12

D13

D12

E10

C11

D10

A13

B12

A12

C12

A11

B11

E9

TDO

-

TDO

TMS

-

TCK

-

TDI

-

PROGRAMN

CCLK

1

-

PT43D

HDC/SI

PT43C

LDCN/SCS

PT41A

CS1

PT39B

CS0N

PT39A

RDN

PT37D

WRN

PT37C

D7

PT37B

D6

D5

PT37A

PT36D

D4

PT36C

D3

PT35B

D2

PT35A

D1

PT33B

D0

PT33A

QOUT/CEON

VREF2_1

DOUT

PT32D

E8

PT32B

D8

PT28C

BUSYN/RCLK/SCK

PCLKC1_0

PCLKT1_0

VREF1_1

A10

C10

E7

PT27B

PT27A

PT21C

C9

A_VDDIB3_L

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

A9

-

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

PCS 360 CH 3 OUT N

B9

-

A8

-

B8

-

C8

-

B7

-

PCS 360 CH 2 OUT N

C7

-

A7

-

PCS 360 CH 2 OUT P

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

B6

-

A6

-

C6

-

4-12

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15 Logic Signal Connections: 256 fpBGA^1,2(Cont.)

LFSC/M15

Ball Number

C5

Ball Function

A_VDDIB1_L

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

A_HDOUTN1_L

A_VDDOB1_L

A_HDOUTN0_L

A_VDDOB0_L

A_HDOUTP0_L

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

GND

VCCIO Bank

Dual Function

-

A5

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

PCS 360 CH 1 OUT N

B5

A4

B4

C4

B3

PCS 360 CH 0 OUT N

C3

A3

PCS 360 CH 0 OUT P

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

B2

A2

C2

A1

A16

B10

C13

D15

D3

GND

E11

F13

G14

G2

GND

G8

GND

H10

J7

GND

K15

K3

GND

K9

GND

M6

GND

N11

N14

N2

GND

P10

P4

GND

R13

R7

GND

G10

G7

VCC

G9

VCC

H7

VCC

H8

VCC

H9

VCC

J10

J8

VCC

4-13

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15 Logic Signal Connections: 256 fpBGA^1,2(Cont.)

LFSC/M15

Ball Number

J9

Ball Function

VCC

VCCIO Bank

Dual Function

-

K8

VCC

F6

VCC12

F11

L11

L6

VCC12

K7

VCC12

K10

F10

F7

VCC12

VCCAUX

GND

T1

G11

K11

L10

L9

VCCAUX

GND

L7

L8

T16

G6

VCCAUX

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCC12

K6

B13

D11

D14

F12

G15

K14

N15

M11

P13

R10

N6

P7

R4

K2

N3

F4

G3

D4

D7

VCC12

D5

VCC12

D6

VCC12

1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement).

2. The LatticeSC/M15 in a 256-pin package does not support an MPI interface.

4-14

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

A_VDDAX25_L

A_REFCLKP_L

A_REFCLKN_L

VCC12

RESP_ULC

VCC12

RESETN

TSALLN

DONE

Dual Function

F7

B1

C1

D5

A2

E5

D4

H5

H6

G6

G5

F5

F6

F4

E4

D3

D2

J6

A_VDDAX25_L

A_REFCLKP_L

A_REFCLKN_L

VCC12

RESP_ULC

VCC12

RESETN

TSALLN

DONE

-

1

7

6

1

7

6

INITN

M0

M1

M2

M3

PL15A

PL15B

PL15C

PL15D

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL18C

PL18D

PL19A

PL19B

PL19C

PL19D

PL22A

PL22B

PL22C

PL22D

PL23A

PL23B

PL24A

PL24B

PL24C

PL24D

PL26A

PL26B

PL26C

PL26D

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

PL16A

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

PL16B

PL16C

PL16D

PL17A

J5

E3

E2

K4

J4

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

ULC_PLLT_IN_B/ULC_PLLT_FB_A

ULC_PLLC_IN_B/ULC_PLLC_FB_A

ULC_DLLT_IN_D/ULC_DLLT_FB_C

ULC_DLLC_IN_D/ULC_DLLC_FB_C

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

ULC_PLLT_IN_B/ULC_PLLT_FB_A

ULC_PLLC_IN_B/ULC_PLLC_FB_A

ULC_DLLT_IN_D/ULC_DLLT_FB_C

ULC_DLLC_IN_D/ULC_DLLC_FB_C

PL17B

PL17C

PL17D

PL18A

F3

G3

K5

K6

F2

F1

E1

D1

K3

L3

PL18B

PL18C

PL18D

PL22A

VREF2_7

PL22B

PL22C

PL22D

PL25A

PL25B

L6

VREF1_7

DIFFR_7

PL25C

PL25D

PL26A

VREF1_7

DIFFR_7

M6

J1

PCLKT7_1

PCLKC7_1

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

PCLKT7_1

PCLKC7_1

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

K1

L1

PL26B

PL27A

M1

P8

R8

N2

N1

R7

R6

PL27B

PL27C

PL27D

PL29A

PL29B

PL29C

PL29D

4-15

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

PL30A

PL30B

PL30C

PL31A

PL31B

PL31C

PL31D

PL34A

PL34B

PL34C

PL34D

PL35A

PL35B

PL38A

PL38B

PL42A

PL42B

PL42D

PL43A

PL43B

PL44A

PL44B

PL48A

PL48B

PL49A

PL49B

PL51A

PL51B

PL51D

PL52A

PL52B

PL55A

PL55B

PL55C

PL55D

PL57A

PL57B

PL57C

PL57D

XRES

Dual Function

N3

P3

PL27A

PL27B

PL27C

PL28A

PL28B

PL28C

PL28D

PL31A

PL31B

PL31C

PL31D

PL32A

PL32B

PL33A

PL33B

PL35A

PL35B

PL35D

PL36A

PL36B

PL37A

PL37B

PL39A

PL39B

PL40A

PL40B

PL41A

PL41B

PL41D

PL43A

PL43B

PL44A

PL44B

PL44C

PL44D

PL45A

PL45B

PL45C

PL45D

XRES

6

-

6

-

P4

PCLKT6_3

P2

R2

T3

PCLKT6_2

PCLKC6_2

PCLKT6_2

PCLKC6_2

R3

P1

R1

R5

VREF1_6

R4

T2

U2

T1

U1

V1

W1

V6

DIFFR_6

V2

W2

Y1

AA1

AB1

AC1

Y5

Y6

AD2

AE2

AB5

AC3

AD3

AF1

AG1

AB6

AC5

AF2

AG2

AC6

AC7

AE4

AG4

AD5

AF5

AH1

AJ1

VREF2_6

LLC_DLLT_IN_E/LLC_DLLT_FB_F

LLC_DLLC_IN_E/LLC_DLLC_FB_F

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

LLC_PLLT_IN_B/LLC_PLLT_FB_A

LLC_PLLC_IN_B/LLC_PLLC_FB_A

LLC_DLLT_IN_E/LLC_DLLT_FB_F

LLC_DLLC_IN_E/LLC_DLLC_FB_F

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

LLC_PLLT_IN_B/LLC_PLLT_FB_A

LLC_PLLC_IN_B/LLC_PLLC_FB_A

VCC12

TEMP

VCC12

PB3A

-

VCC12

TEMP

-

6

-

6

-

VCC12

PB3A

5

LLC_PLLT_IN_A/LLC_PLLT_FB_B

LLC_PLLC_IN_A/LLC_PLLC_FB_B

5

LLC_PLLT_IN_A/LLC_PLLT_FB_B

LLC_PLLC_IN_A/LLC_PLLC_FB_B

PB3B

4-16

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

PB3C

Dual Function

AF4

AE5

PB3C

PB3D

5

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

LLC_DLLT_IN_D/LLC_DLLT_FB_C

LLC_DLLC_IN_D/LLC_DLLC_FB_C

5

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

LLC_DLLT_IN_D/LLC_DLLT_FB_C

LLC_DLLC_IN_D/LLC_DLLC_FB_C

PB3D

AG3

PB4A

AH2

PB4B

AD6

PB4C

AJ2

PB5A

AK2

PB5B

AD7

PB5C

AD8

PB5D

VREF1_5

PB5D

VREF1_5

AH3

PB7A

PB11A

PB11B

PB11C

PB11D

PB12A

PB12B

PB13A

PB13B

PB16A

PB16B

PB20A

PB20B

PB20C

PB20D

PB21A

PB21B

PB21C

PB23A

PB23B

PB23D

PB24A

PB24B

PB25A

PB25B

PB28A

PB28B

PB29A

PB29B

PB31A

PB31B

PB31C

PB31D

PB32A

PB32B

PB33A

PB33B

AJ3

PB7B

AF9

PB7C

AE10

AK3

PB7D

PB8A

AJ4

PB8B

AE11

AF10

AK4

PB9A

PB9B

PB11A

PB11B

PB12A

PB12B

PB12C

PB12D

PB13A

PB13B

PB13C

PB15A

PB15B

PB15D

PB16A

PB16B

PB17A

PB17B

PB19A

PB19B

PB20A

PB20B

PB21A

PB21B

PB21C

PB21D

PB23A

PB23B

PB24A

PB24B

AK5

AH10

AH11

AF13

AE14

AK6

PCLKT5_3

PCLKC5_3

PCLKT5_4

PCLKC5_4

PCLKT5_5

PCLKC5_5

PCLKT5_3

PCLKC5_3

PCLKT5_4

PCLKC5_4

PCLKT5_5

PCLKC5_5

AK7

AF14

AJ11

AJ12

AH13

AK8

PCLKT5_0

PCLKC5_0

VREF2_5

PCLKT5_0

PCLKC5_0

VREF2_5

PCLKT5_1

PCLKC5_1

PCLKT5_2

PCLKC5_2

PCLKT5_1

PCLKC5_1

PCLKT5_2

PCLKC5_2

AK9

AH14

AG14

AK10

AK11

AH15

AG15

AH12

AJ13

AD15

AE15

AK12

AK13

AJ14

AJ15

4-17

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

PB35A

PB35B

PB37A

PB37B

PB38A

PB38B

PB38C

PB39A

PB39B

PB41A

PB41B

PB42A

PB42B

PB42D

PB43A

PB43B

PB46A

PB46B

PB47A

PB47B

PB49A

PB49B

PB49C

PB51A

PB51B

PB51C

PB52A

PB52B

PB52C

PB52D

PB53A

PB53B

PB55A

PB55B

PB56A

PB56B

PB56C

PB60A

PB60B

PB60C

PB67A

PB67B

PB67C

PB67D

PB68A

Dual Function

AK14

AK15

AK16

AK17

AJ16

AJ17

AE16

AH16

AG16

AK18

AK19

AH17

AH18

AG17

AJ18

AJ19

AK20

AK21

AF18

AG18

AJ20

AJ21

AG19

AK22

AK23

AH19

AK24

AK25

AE19

AE20

AE21

AF21

AG21

AG22

AH22

AH23

AH21

AK28

AK29

AE22

AJ28

AH28

AE24

AE25

AJ29

PB25A

PB25B

PB27A

PB27B

PB28A

PB28B

PB28C

PB29A

PB29B

PB31A

PB31B

PB32A

PB32B

PB32D

PB33A

PB33B

PB35A

PB35B

PB36A

PB36B

PB37A

PB37B

PB37C

PB39A

PB39B

PB39C

PB40A

PB40B

PB40C

PB40D

PB41A

PB41B

PB43A

PB43B

PB44A

PB44B

PB44C

PB45A

PB45B

PB45C

PB47A

PB47B

PB47C

PB47D

PB48A

5

4

5

4

PCLKT4_2

PCLKC4_2

PCLKT4_1

PCLKC4_1

PCLKT4_0

PCLKC4_0

VREF2_4

PCLKT4_2

PCLKC4_2

PCLKT4_1

PCLKC4_1

PCLKT4_0

PCLKC4_0

VREF2_4

PCLKT4_5

PCLKC4_5

PCLKT4_5

PCLKC4_5

PCLKT4_3

PCLKC4_3

PCLKT4_4

PCLKC4_4

PCLKT4_3

PCLKC4_3

PCLKT4_4

PCLKC4_4

VREF1_4

LRC_DLLT_IN_C/LRC_DLLT_FB_D

4-18

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

PB68B

PB68C

PB68D

PB69A

PB69B

PB69C

PB69D

VCC12

PROBE_VCC

VCC12

PROBE_GND

PR57D

PR57C

PR57B

PR57A

PR55D

PR55C

PR55B

PR55A

PR52B

PR52A

PR51D

PR51B

PR51A

PR49B

PR49A

PR48B

PR48A

PR44B

PR44A

PR43B

PR43A

PR42D

PR42B

PR42A

PR38B

PR38A

PR35B

PR35A

PR34D

PR34C

PR34B

PR34A

PR31D

PR31C

Dual Function

AH29

AE26

AD25

AJ30

AH30

AG28

AG29

AF26

AD27

AG27

AE28

AC25

AD26

AF28

AF29

AC26

AB26

AG30

AF30

AC28

AB28

AB27

AE30

AD30

AB25

AA25

AA30

Y30

PB48B

PB48C

PB48D

PB49A

PB49B

PB49C

PB49D

VCC12

PROBE_VCC

VCC12

PROBE_GND

PR45D

PR45C

PR45B

PR45A

PR44D

PR44C

PR44B

PR44A

PR43B

PR43A

PR41D

PR41B

PR41A

PR40B

PR40A

PR39B

PR39A

PR37B

PR37A

PR36B

PR36A

PR35D

PR35B

PR35A

PR33B

PR33A

PR32B

PR32A

PR31D

PR31C

PR31B

PR31A

PR28D

PR28C

4

-

LRC_DLLC_IN_C/LRC_DLLC_FB_D

4

-

LRC_DLLC_IN_C/LRC_DLLC_FB_D

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLT_IN_D/LRC_DLLT_FB_C

LRC_DLLC_IN_D/LRC_DLLC_FB_C

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLT_IN_D/LRC_DLLT_FB_C

LRC_DLLC_IN_D/LRC_DLLC_FB_C

-

3

LRC_PLLC_IN_B/LRC_PLLC_FB_A

LRC_PLLT_IN_B/LRC_PLLT_FB_A

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

LRC_DLLC_IN_E/LRC_DLLC_FB_F

LRC_DLLT_IN_E/LRC_DLLT_FB_F

3

LRC_PLLC_IN_B/LRC_PLLC_FB_A

LRC_PLLT_IN_B/LRC_PLLT_FB_A

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

LRC_DLLC_IN_E/LRC_DLLC_FB_F

LRC_DLLT_IN_E/LRC_DLLT_FB_F

VREF2_3

W29

V29

U30

T30

V25

DIFFR_3

W28

V28

R30

P30

N30

M29

U26

T26

VREF1_3

U28

T28

M30

PCLKC3_2

PCLKT3_2

PCLKC3_2

PCLKT3_2

L29

4-19

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

PR31B

PR31A

PR30C

PR30B

PR30A

PR29D

PR29C

PR29B

PR29A

PR27D

PR27C

PR27B

PR27A

PR26B

PR26A

PR25D

PR25C

PR25B

PR25A

PR22D

PR22C

PR22B

PR22A

PR18D

PR18C

PR18B

PR18A

PR17D

PR17C

PR17B

PR17A

PR16D

PR16C

PR16B

PR16A

VCCJ

Dual Function

R29

P29

P27

N29

N28

R25

R26

R28

P28

N27

P26

L30

K30

J30

PR28B

PR28A

PR27C

PR27B

PR27A

PR26D

PR26C

PR26B

PR26A

PR24D

PR24C

PR24B

PR24A

PR23B

PR23A

PR22D

PR22C

PR22B

PR22A

PR19D

PR19C

PR19B

PR19A

PR18D

PR18C

PR18B

PR18A

PR17D

PR17C

PR17B

PR17A

PR15D

PR15C

PR15B

PR15A

VCCJ

3

2

-

3

2

-

PCLKT3_3

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_1

PCLKT2_1

DIFFR_2

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_1

PCLKT2_1

DIFFR_2

H30

M26

M25

G29

F29

H28

J28

VREF1_2

E30

E29

L26

L25

F28

G28

K26

K25

D30

D29

G26

H26

E28

D28

J25

VREF2_2

URC_DLLC_IN_D/URC_DLLC_FB_C

URC_DLLT_IN_D/URC_DLLT_FB_C

URC_PLLC_IN_B/URC_PLLC_FB_A

URC_PLLT_IN_B/URC_PLLT_FB_A

URC_DLLC_IN_C/URC_DLLC_FB_D

URC_DLLT_IN_C/URC_DLLT_FB_D

URC_DLLC_IN_D/URC_DLLC_FB_C

URC_DLLT_IN_D/URC_DLLT_FB_C

URC_PLLC_IN_B/URC_PLLC_FB_A

URC_PLLT_IN_B/URC_PLLT_FB_A

URC_DLLC_IN_C/URC_DLLC_FB_D

URC_DLLT_IN_C/URC_DLLT_FB_D

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

H25

J26

TDO

-

TDO

-

TDO

TMS

-

TMS

-

G25

G24

F26

H24

F25

D27

E26

TCK

-

TCK

-

TDI

-

TDI

-

PROGRAMN

MPIIRQN

CCLK

1

-

PROGRAMN

MPIIRQN

CCLK

1

-

CFGIRQN/MPI_IRQ_N

VCC12

-

4-20

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

RESP_URC

VCC12

Dual Function

A29

D26

C30

B30

F24

D25

C28

B28

B27

E25

A28

C27

A27

C26

A26

D24

A25

B26

B25

E24

C25

D23

C24

B24

B23

E23

A24

C23

A23

C22

A22

D22

A21

B22

B21

E22

C21

G22

F22

B20

B19

A20

A19

D19

D18

RESP_URC

VCC12

-

A_REFCLKN_R

A_REFCLKP_R

A_VDDAX25_R

VCC12

-

A_REFCLKN_R

A_REFCLKP_R

A_VDDAX25_R

VCC12

-

A_VDDIB0_R

A_HDINP0_R

A_HDINN0_R

VCC12

-

A_VDDIB0_R

A_HDINP0_R

A_HDINN0_R

VCC12

-

PCS 3E0 CH 0 IN P

PCS 3E0 CH 0 IN N

-

PCS 3E0 CH 0 IN P

PCS 3E0 CH 0 IN N

-

A_HDOUTP0_R

A_VDDOB0_R

A_HDOUTN0_R

A_VDDOB1_R

A_HDOUTN1_R

VCC12

-

PCS 3E0 CH 0 OUT P

PCS 3E0 CH 0 OUT N

PCS 3E0 CH 1 OUT N

A_HDOUTP0_R

A_VDDOB0_R

A_HDOUTN0_R

A_VDDOB1_R

A_HDOUTN1_R

VCC12

-

PCS 3E0 CH 0 OUT P

PCS 3E0 CH 0 OUT N

PCS 3E0 CH 1 OUT N

-

A_HDOUTP1_R

A_HDINN1_R

A_HDINP1_R

VCC12

-

PCS 3E0 CH 1 OUT P

PCS 3E0 CH 1 IN N

PCS 3E0 CH 1 IN P

A_HDOUTP1_R

A_HDINN1_R

A_HDINP1_R

VCC12

-

PCS 3E0 CH 1 OUT P

PCS 3E0 CH 1 IN N

PCS 3E0 CH 1 IN P

-

A_VDDIB1_R

VCC12

-

A_VDDIB1_R

VCC12

-

A_VDDIB2_R

A_HDINP2_R

A_HDINN2_R

VCC12

-

A_VDDIB2_R

A_HDINP2_R

A_HDINN2_R

VCC12

-

PCS 3E0 CH 2 IN P

PCS 3E0 CH 2 IN N

-

PCS 3E0 CH 2 IN P

PCS 3E0 CH 2 IN N

-

A_HDOUTP2_R

A_VDDOB2_R

A_HDOUTN2_R

A_VDDOB3_R

A_HDOUTN3_R

VCC12

-

PCS 3E0 CH 2 OUT P

PCS 3E0 CH 2 OUT N

PCS 3E0 CH 3 OUT N

A_HDOUTP2_R

A_VDDOB2_R

A_HDOUTN2_R

A_VDDOB3_R

A_HDOUTN3_R

VCC12

-

PCS 3E0 CH 2 OUT P

PCS 3E0 CH 2 OUT N

PCS 3E0 CH 3 OUT N

-

A_HDOUTP3_R

A_HDINN3_R

A_HDINP3_R

VCC12

-

PCS 3E0 CH 3 OUT P

PCS 3E0 CH 3 IN N

PCS 3E0 CH 3 IN P

A_HDOUTP3_R

A_HDINN3_R

A_HDINP3_R

VCC12

-

PCS 3E0 CH 3 OUT P

PCS 3E0 CH 3 IN N

PCS 3E0 CH 3 IN P

-

A_VDDIB3_R

PT43D

-

A_VDDIB3_R

PT49D

-

1

HDC/SI

1

HDC/SI

PT43C

LDCN/SCS

PT49C

LDCN/SCS

PT41B

D8/MPI_DATA8

CS1/MPI_CS1

D9/MPI_DATA9

D10/MPI_DATA10

CS0N/MPI_CS0N

RDN/MPI_STRB_N

PT49B

D8/MPI_DATA8

CS1/MPI_CS1

D9/MPI_DATA9

D10/MPI_DATA10

CS0N/MPI_CS0N

RDN/MPI_STRB_N

PT41A

PT49A

PT40D

PT47D

PT40C

PT47C

PT39B

PT47B

PT39A

PT47A

4-21

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

PT46D

PT46C

PT46B

PT46A

PT45D

PT45C

PT45B

PT45A

PT43B

PT43A

PT42D

PT42B

PT42A

PT41B

PT41A

PT39B

PT39A

PT38D

PT38C

PT38B

PT38A

PT37B

PT37A

PT35D

PT35B

PT35A

PT33D

PT33C

PT33B

PT33A

PT32B

PT32A

PT31C

PT31B

PT31A

PT29B

PT29A

PT28B

PT28A

PT27D

PT27C

PT27B

PT27A

PT25D

PT25C

Dual Function

F19

F18

C18

C17

E17

E16

G18

G17

B18

B17

G16

A18

A17

H18

H17

D17

D16

F17

F16

C16

C15

B16

B15

H16

A16

A15

G15

F15

E15

D15

C14

C13

H14

B14

B13

G14

F14

A14

A13

G13

H13

E14

E13

G12

G11

PT37D

PT37C

PT37B

PT37A

PT36D

PT36C

PT35B

PT35A

PT33B

PT33A

PT32D

PT32B

PT32A

PT31B

PT31A

PT29B

PT29A

PT28D

PT28C

PT28B

PT28A

PT27B

PT27A

PT25D

PT25B

PT25A

PT24D

PT24C

PT24B

PT24A

PT23B

PT23A

PT21C

PT21B

PT21A

PT20B

PT20A

PT19B

PT19A

PT17D

PT17C

PT17B

PT17A

PT15D

PT15C

1

WRN/MPI_WR_N

D7/MPI_DATA7

D6/MPI_DATA6

D5/MPI_DATA5

D4/MPI_DATA4

D3/MPI_DATA3

D2/MPI_DATA2

D1/MPI_DATA1

D0/MPI_DATA0

QOUT/CEON

1

WRN/MPI_WR_N

D7/MPI_DATA7

D6/MPI_DATA6

D5/MPI_DATA5

D4/MPI_DATA4

D3/MPI_DATA3

D2/MPI_DATA2

D1/MPI_DATA1

D0/MPI_DATA0

QOUT/CEON

VREF2_1

DOUT

MCA_DONE_IN

MCA_CLK_P1_OUT

MCA_CLK_P1_IN

MCA_CLK_P2_OUT

MCA_CLK_P2_IN

MCA_DONE_OUT

BUSYN/RCLK/SCK

DP0/MPI_PAR0

MPI_TA

MCA_DONE_IN

MCA_CLK_P1_OUT

MCA_CLK_P1_IN

MCA_CLK_P2_OUT

MCA_CLK_P2_IN

MCA_DONE_OUT

BUSYN/RCLK/SCK

DP0/MPI_PAR0

MPI_TA

PCLKC1_0

PCLKT1_0/MPI_CLK

DP3/PCLKC1_4/MPI_PAR3

MPI_RETRY

PCLKT1_0/MPI_CLK

DP3/PCLKC1_4/MPI_PAR3

MPI_RETRY

A0/MPI_ADDR14

A1/MPI_ADDR15

A2/MPI_ADDR16

A3/MPI_ADDR17

A4/MPI_ADDR18

A5/MPI_ADDR19

A6/MPI_ADDR20

VREF1_1

A0/MPI_ADDR14

A1/MPI_ADDR15

A2/MPI_ADDR16

A3/MPI_ADDR17

A4/MPI_ADDR18

A5/MPI_ADDR19

A6/MPI_ADDR20

VREF1_1

A7/MPI_ADDR21

A8/MPI_ADDR22

A9/MPI_ADDR23

A10/MPI_ADDR24

A11/MPI_ADDR25

A12/MPI_ADDR26

D11/MPI_DATA11

D12/MPI_DATA12

A13/MPI_ADDR27

A14/MPI_ADDR28

A16/MPI_ADDR30

D13/MPI_DATA13

A7/MPI_ADDR21

A8/MPI_ADDR22

A9/MPI_ADDR23

A10/MPI_ADDR24

A11/MPI_ADDR25

A12/MPI_ADDR26

D11/MPI_DATA11

D12/MPI_DATA12

A13/MPI_ADDR27

A14/MPI_ADDR28

A16/MPI_ADDR30

D13/MPI_DATA13

4-22

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

PT25B

Dual Function

D14

D13

F12

F13

B12

B11

E12

D12

G10

G9

C10

E9

PT15B

PT15A

1

-

A15/MPI_ADDR29

A17/MPI_ADDR31

A19/MPI_TSIZ1

A20/MPI_BDIP

A18/MPI_TSIZ0

MPI_TEA

1

-

A15/MPI_ADDR29

A17/MPI_ADDR31

A19/MPI_TSIZ1

A20/MPI_BDIP

A18/MPI_TSIZ0

MPI_TEA

PT25A

PT13D

PT24D

PT13C

PT24C

PT11B

PT24B

PT11A

PT24A

PT10D

D14/MPI_DATA14

DP1/MPI_PAR1

A21/MPI_BURST

D15/MPI_DATA15

PT23D

D14/MPI_DATA14

DP1/MPI_PAR1

A21/MPI_BURST

D15/MPI_DATA15

PT10C

PT23C

PT9B

PT23B

PT9A

PT23A

A_VDDIB3_L

VCC12

A_VDDIB3_L

VCC12

-

B10

B9

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

VCC12

-

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

VCC12

-

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

-

A10

D9

A9

-

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

VCC12

-

PCS 360 CH 3 OUT N

PCS 360 CH 2 OUT N

PCS 360 CH 2 OUT P

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

VCC12

-

PCS 360 CH 3 OUT N

PCS 360 CH 2 OUT N

PCS 360 CH 2 OUT P

C9

A8

-

C8

A7

-

E8

-

B8

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

VCC12

-

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

VCC12

-

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

B7

-

C7

D8

C6

E7

-

A_VDDIB1_L

VCC12

-

A_VDDIB1_L

VCC12

-

B6

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

VCC12

-

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

VCC12

-

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

B5

-

A6

-

D7

A5

-

A_HDOUTN1_L

A_VDDOB1_L

A_HDOUTN0_L

A_VDDOB0_L

A_HDOUTP0_L

VCC12

-

PCS 360 CH 1 OUT N

PCS 360 CH 0 OUT N

PCS 360 CH 0 OUT P

A_HDOUTN1_L

A_VDDOB1_L

A_HDOUTN0_L

A_VDDOB0_L

A_HDOUTP0_L

VCC12

-

PCS 360 CH 1 OUT N

PCS 360 CH 0 OUT N

PCS 360 CH 0 OUT P

C5

A4

-

C4

A3

-

E6

-

B4

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

VCC12

-

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

VCC12

-

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

B3

-

C3

D6

L5

-

NC

-

PL21A

7

M5

G2

NC

-

PL21B

NC

-

PL20A

4-23

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

PL20B

NC

Dual Function

G1

M4

NC

-

7

-

J3

NC

-

P5

NC

-

W5

PL48C

PL35C

PL36A

PL36B

PL39A

PL39B

PL43C

PL42C

PL40A

PL40B

PL43D

PL47A

PL47B

PL47D

PL47C

NC

6

-

T6

U3

V3

T5

T4

V5

U6

U4

U5

V4

Y2

AA2

W3

Y3

AB3

AC4

AD4

AE3

AF3

AF7

AF6

AH4

AG5

AF8

AG8

AG7

AG10

AF12

AH7

AE13

AG13

AH8

AJ5

AJ6

AF15

AJ7

AJ8

AE12

AF16

AF19

PL53A

PL53B

PL56A

PL56B

PB7A

6

5

-

PB7B

PB8A

PB8B

PB9A

PB9B

NC

-

NC

-

PB15A

PB15D

PB23C

PB15B

PB17A

PB17B

PB21D

PB19A

PB19B

PB15C

PB38D

PB49D

5

4

4-24

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

PB51D

NC

Dual Function

AH20

AK27

AJ24

AF17

AH27

AD23

AE23

AH24

AH25

AH26

AF24

AG24

AG25

AF25

AG26

AF27

AD28

AC27

AE29

AD29

AB30

AA28

Y27

NC

-

4

-

NC

-

PB42C

PB61B

PB57A

PB57B

PB59A

PB59B

PB61A

PB63A

PB63B

PB64A

PB64B

PB65A

PB65B

PR56B

PR56A

PR53B

PR53A

NC

4

3

-

NC

-

PR47C

PR47D

PR47A

PR47B

PR43D

PR43C

PR42C

PR40B

PR40A

PR39B

PR39A

PR36B

PR36A

PR35C

PR48C

NC

3

-

W27

V30

W30

W26

V26

U25

T27

R27

V27

U27

U29

T29

T24

Y25

P24

K28

NC

-

P23

NC

-

L28

NC

-

M27

L27

PR21B

PR21A

PR20B

PR20A

2

H27

G27

4-25

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

NC

Dual Function

E19

G21

G20

G19

F9

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

A11

NC

-

NC

-

G7

NC

-

NC

-

AH9

H8

NC

-

NC

-

VCC12

VTT_2

VTT_3

VTT_4

VTT_5

VTT_6

VTT_7

VCC

-

VCC12

VTT_2

VTT_3

VTT_4

VTT_5

VTT_6

VTT_7

VCC

-

T8

-

AB9

AC8

AB22

AC23

R23

H23

H15

L24

-

2

3

4

5

6

7

-

2

3

4

5

6

7

-

T23

AC24

T25

W25

AD24

AE17

AE18

AC15

AD16

AE9

AA6

T7

W6

L7

P7

AA10

AA11

AA12

AA13

AA14

AA17

AA18

AA19

AA20

AA21

AA22

AA9

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

4-26

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

VCC

Dual Function

AB10

AB21

J10

VCC

-

VCC

J21

VCC

K10

K11

K12

K13

K14

K17

K18

K19

K20

K21

K22

K9

VCC

L10

L21

M10

M21

N10

N21

P10

P21

U10

U21

V10

V21

W10

W21

Y10

Y21

H11

H12

H19

H20

M23

M24

N23

N24

U23

U24

V23

V24

W23

VCC

VCCAUX

4-27

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

VCCAUX

VCCIO1

VCCIO2

Dual Function

W24

AC17

AC18

AC19

AD17

AD18

AD19

AC12

AC13

AC14

AD12

AD13

AD14

U7

VCCAUX

VCCIO1

VCCIO2

-

U8

V7

V8

W7

W8

M7

M8

N7

N8

H10

H21

H22

H9

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

J23

J24

K23

K24

L22

L23

M22

N22

4-28

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

Dual Function

P22

R22

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

-

AA23

AA24

AB23

AB24

T22

U22

V22

W22

Y22

Y23

Y24

AB16

AB17

AB18

AB19

AB20

AC20

AC21

AC22

AD20

AD21

AD22

AB11

AB12

AB13

AB14

AB15

AC10

AC11

AC9

AD10

AD11

AD9

AA7

AA8

AB7

AB8

T9

U9

V9

W9

Y7

Y8

4-29

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

VCCIO6

VCCIO7

GND

Dual Function

Y9

J7

VCCIO6

VCCIO7

GND

-

J8

K7

K8

L8

L9

M9

N9

P9

R9

A1

A30

AA15

AA16

AK1

AK30

K15

K16

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

N11

N12

N13

N14

N15

N16

GND

4-30

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

GND

Dual Function

N17

N18

N19

N20

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

R21

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

U11

U12

U13

U14

U15

U16

U17

GND

-

4-31

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

GND

Dual Function

U18

U19

U20

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

H2

GND

-

GND

VCCIO7

VCCIO6

VCCIO5

VCCIO7

VCCIO6

VCCIO5

N4

N6

J2

L2

H4

AB2

AD1

W4

AA4

AE7

AH6

4-32

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

VCCIO5

VCCIO4

VCCIO3

VCCIO2

VCCIO1

GND

Dual Function

AG11

AJ9

VCCIO5

VCCIO4

VCCIO3

VCCIO2

VCCIO1

GND

-

AJ23

AG20

AJ26

AG23

AC29

AA26

Y28

AA29

G30

J29

K27

N25

F20

C19

C12

F11

H1

L4

GND

M3

GND

N5

GND

K2

GND

M2

GND

P6

GND

G4

GND

H3

GND

AC2

AA3

AE1

Y4

GND

AB4

AA5

AE6

AE8

AH5

AG9

AG6

AF11

AG12

AJ10

AK26

AJ22

AF20

AJ25

GND

4-33

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

GND

Dual Function

AJ27

AF23

AF22

AE27

AA27

AB29

Y26

AC30

Y29

F30

E27

F27

P25

H29

K29

R24

M28

J27

GND

NC

-

GND

N26

E20

E21

F21

F23

G23

D21

D20

E18

C20

C11

A12

E11

F8

GND

G8

GND

D11

D10

H7

GND

F10

E10

AC16

J22

GND

NC

VCC

J9

VCC

B2

NC

C2

RESPN_ULC

RESPN_URC

RESPN_ULC

RESPN_URC

C29

4-34

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M15, LFSC/M25 Logic Signal Connections: 900 fpBGA^{1, 2}(Cont.)

LFSC/M15

LFSC/M25

Ball

VCCIO

Bank

VCCIO

Bank

Number Ball Function

Dual Function

Ball Function

Dual Function

B29

NC

-

NC

-

1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement).

2. The LatticeSC/M15 and LatticeSC/M25 in a 900-pin package supports a 16-bit MPI interface.

4-35

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

C28

D28

B28

F28

J21

A_REFCLKP_L

A_REFCLKN_L

VCC12

RESP_ULC

RESETN

TSALLN

DONE

INITN

-

A_REFCLKP_L

A_REFCLKN_L

VCC12

RESP_ULC

RESETN

TSALLN

DONE

INITN

-

1

7

6

1

7

6

J20

K20

K21

K23

J23

M0

M1

J24

M2

K24

K25

J25

M3

PL16A

PL16B

PL16C

PL16D

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL18C

PL18D

PL20A

PL20B

PL20C

PL20D

PL21A

PL21B

PL22A

PL22B

PL22C

PL22D

PL25A

PL25B

PL25C

PL25D

PL26A

PL26B

PL26C

PL26D

PL27A

PL27B

PL27C

PL27D

PL29A

PL29B

PL29C

PL29D

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

PL16A

PL16B

PL16C

PL16D

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL18C

PL18D

PL21A

PL21B

PL21C

PL21D

PL22A

PL22B

PL25A

PL25B

PL25C

PL25D

PL23A

PL23B

PL23C

PL23D

PL35A

PL35B

PL35C

PL35D

PL36A

PL36B

PL36C

PL36D

PL38A

PL38B

PL38C

PL38D

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

K26

K27

D32

D31

M23

N23

E32

E31

J28

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

ULC_PLLT_IN_B/ULC_PLLT_FB_A

ULC_PLLC_IN_B/ULC_PLLC_FB_A

ULC_DLLT_IN_D/ULC_DLLT_FB_C

ULC_DLLC_IN_D/ULC_DLLC_FB_C

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

ULC_PLLT_IN_B/ULC_PLLT_FB_A

ULC_PLLC_IN_B/ULC_PLLC_FB_A

ULC_DLLT_IN_D/ULC_DLLT_FB_C

ULC_DLLC_IN_D/ULC_DLLC_FB_C

K28

F32

F31

L25

L26

G31

G32

J29

VREF2_7

H29

M25

N25

H31

H32

M24

N24

L32

M32

R25

R24

N31

N32

P27

P28

P30

P29

T23

T24

VREF1_7

DIFFR_7

VREF1_7

DIFFR_7

PCLKT7_1

PCLKC7_1

PCLKT7_3

PCLKC7_3

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

PCLKT7_1

PCLKC7_1

PCLKT7_3

PCLKC7_3

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

4-36

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

P32

P31

R28

T28

PL30A

PL30B

PL30C

PL30D

PL31A

PL31B

PL31C

PL31D

PL34A

PL34B

PL34C

PL34D

PL35A

PL35B

PL35C

PL35D

PL36A

PL36B

PL36C

PL36D

PL38A

PL38B

PL38C

PL38D

PL39A

PL39B

PL39C

PL39D

PL40A

PL40B

PL40C

PL40D

PL42A

PL42B

PL42C

PL42D

PL43A

PL43B

PL43C

PL43D

PL44A

PL44B

PL44C

PL44D

PL47A

PL47B

PL47C

PL47D

PL48A

PL48B

6

PL39A

PL39B

PL39C

PL39D

PL40A

PL40B

PL40C

PL40D

PL43A

PL43B

PL43C

PL43D

PL44A

PL44B

PL44C

PL44D

PL45A

PL45B

PL45C

PL45D

PL47A

PL47B

PL47C

PL47D

PL48A

PL48B

PL48C

PL48D

PL49A

PL49B

PL49C

PL49D

PL51A

PL51B

PL51C

PL51D

PL52A

PL52B

PL52C

PL52D

PL53A

PL53B

PL53C

PL53D

PL60A

PL60B

PL60C

PL60D

PL61A

PL61B

6

PCLKT6_3

PCLKC6_3

PCLKT6_3

PCLKC6_3

R30

R29

T25

PCLKT6_2

PCLKC6_2

PCLKT6_2

PCLKC6_2

T26

R31

R32

U23

U24

T31

VREF1_6

T32

T27

U28

U32

U31

U26

U25

V32

V31

V24

V23

V29

V30

U27

V28

W30

W29

V25

W26

W31

Y31

W27

Y27

W28

Y28

Y26

W25

W32

Y32

AB28

AA28

AB32

AA32

AB27

AC27

AD31

AC31

DIFFR_6

4-37

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

Y24

PL48C

PL48D

PL49A

PL49B

PL49C

PL49D

PL51A

PL51B

PL51C

PL51D

PL52A

PL52B

PL52C

PL52D

PL53A

PL53B

PL53C

PL53D

PL55A

PL55B

PL55C

PL55D

PL56A

PL56B

PL56C

PL56D

PL57A

PL57B

PL57C

PL57D

XRES

TEMP

PB3A

6

-

PL61C

PL61D

PL62A

PL62B

PL62C

PL62D

PL65A

PL65B

PL65C

PL65D

PL66A

PL66B

PL66C

PL66D

PL67A

PL67B

PL67C

PL67D

PL69A

PL69B

PL69C

PL69D

PL70A

PL70B

PL70C

PL70D

PL71A

PL71B

PL71C

PL71D

XRES

TEMP

PB3A

6

-

Y23

AD29

AD30

AF28

AE28

AC28

AD28

AB26

AC26

AC32

AD32

AA24

AA23

AE30

AE29

AC25

AB25

AE31

AE32

AE26

AE27

AF32

AF31

AC24

AD25

AG32

AG31

AC23

AD24

AH32

AH31

AJ32

AK32

AF27

AG28

AK31

AL31

AE25

AE24

AK30

AL30

AD23

AE23

AK29

AL29

AF26

AF25

AJ28

AK28

VREF2_6

LLC_DLLT_IN_E/LLC_DLLT_FB_F

LLC_DLLC_IN_E/LLC_DLLC_FB_F

LLC_DLLT_IN_E/LLC_DLLT_FB_F

LLC_DLLC_IN_E/LLC_DLLC_FB_F

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

LLC_PLLT_IN_B/LLC_PLLT_FB_A

LLC_PLLC_IN_B/LLC_PLLC_FB_A

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

LLC_PLLT_IN_B/LLC_PLLT_FB_A

LLC_PLLC_IN_B/LLC_PLLC_FB_A

6

5

6

5

LLC_PLLT_IN_A/LLC_PLLT_FB_B

LLC_PLLC_IN_A/LLC_PLLC_FB_B

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

LLC_DLLT_IN_D/LLC_DLLT_FB_C

LLC_DLLC_IN_D/LLC_DLLC_FB_C

LLC_PLLT_IN_A/LLC_PLLT_FB_B

LLC_PLLC_IN_A/LLC_PLLC_FB_B

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

LLC_DLLT_IN_D/LLC_DLLT_FB_C

LLC_DLLC_IN_D/LLC_DLLC_FB_C

PB3B

PB3C

PB3D

PB4A

PB3C

PB3D

PB4A

PB4B

PB4C

PB4D

PB5A

PB4C

PB4D

PB5A

PB5B

PB5C

PB5D

PB7A

PB5C

PB5D

PB7A

VREF1_5

PB7B

PB7C

PB7D

PB8A

PB7C

PB7D

PB8A

PB8B

4-38

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

AJ31

AH30

AM30

AM29

AH29

AH28

AJ27

AK27

AE22

AF23

AL28

AL27

AC21

AD21

AM28

AM27

AG23

AF22

AG26

AG25

AL26

AM26

AJ24

AK24

AE21

AE20

AJ22

AK22

AG22

AH22

AL23

AL22

AH23

AH24

AJ21

AK21

AE19

AF19

AM23

AM22

AH25

AH26

AL21

AL20

AG20

AG19

AJ19

AK19

AD18

AE18

PB9A

PB9B

5

PB9A

PB9B

5

PB11A

PB11B

PB11C

PB11D

PB12A

PB12B

PB12C

PB12D

PB13A

PB13B

PB13C

PB13D

PB15A

PB15B

PB15C

PB15D

PB16A

PB16B

PB17A

PB17B

PB19A

PB19B

PB19C

PB19D

PB20A

PB20B

PB20C

PB20D

PB21A

PB21B

PB21C

PB21D

PB23A

PB23B

PB23C

PB23D

PB24A

PB24B

PB24C

PB24D

PB25A

PB25B

PB25C

PB25D

PB28A

PB28B

PB28C

PB28D

PB11A

PB11B

PB11C

PB11D

PB13A

PB13B

PB13C

PB13D

PB15A

PB15B

PB15C

PB15D

PB17A

PB17B

PB17C

PB17D

PB19A

PB19B

PB22A

PB22B

PB25A

PB25B

PB25C

PB25D

PB30A

PB30B

PB30C

PB30D

PB31A

PB31B

PB31C

PB31D

PB33A

PB33B

PB33C

PB33D

PB34A

PB34B

PB34C

PB34D

PB35A

PB35B

PB35C

PB35D

PB37A

PB37B

PB37C

PB37D

PCLKT5_3

PCLKC5_3

PCLKT5_4

PCLKC5_4

PCLKT5_5

PCLKC5_5

PCLKT5_3

PCLKC5_3

PCLKT5_4

PCLKC5_4

PCLKT5_5

PCLKC5_5

PCLKT5_0

PCLKC5_0

PCLKT5_0

PCLKC5_0

VREF2_5

PCLKT5_1

PCLKC5_1

PCLKT5_6

PCLKC5_6

PCLKT5_2

PCLKC5_2

PCLKT5_7

PCLKC5_7

VREF2_5

PCLKT5_1

PCLKC5_1

PCLKT5_6

PCLKC5_6

PCLKT5_2

PCLKC5_2

PCLKT5_7

PCLKC5_7

4-39

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

AM21

AM20

AH21

AH20

AJ18

AK18

AH19

AH18

AL19

AM19

AH17

AG17

AL18

AM18

AC17

AD17

AL17

AM17

AE17

AF17

AM16

AL16

AF16

AE16

AM15

AL15

AD16

AC16

AM14

AL14

AG16

AH16

AK15

AJ15

AH15

AH14

AM13

AM12

AH13

AH12

AK14

AJ14

AE15

AD15

AL13

AL12

AG14

AG13

AM11

AM10

PB29A

PB29B

PB29C

PB29D

PB31A

PB31B

PB31C

PB31D

PB32A

PB32B

PB32C

PB32D

PB33A

PB33B

PB33C

PB33D

PB35A

PB35B

PB35C

PB35D

PB37A

PB37B

PB37C

PB37D

PB38A

PB38B

PB38C

PB38D

PB39A

PB39B

PB39C

PB39D

PB41A

PB41B

PB41C

PB41D

PB42A

PB42B

PB42C

PB42D

PB43A

PB43B

PB43C

PB43D

PB46A

PB46B

PB46C

PB46D

PB47A

PB47B

5

4

PB38A

PB38B

PB38C

PB38D

PB39A

PB39B

PB39C

PB39D

PB41A

PB41B

PB41C

PB41D

PB42A

PB42B

PB42C

PB42D

PB43A

PB43B

PB43C

PB43D

PB45A

PB45B

PB45C

PB45D

PB46A

PB46B

PB46C

PB46D

PB47A

PB47B

PB47C

PB47D

PB49A

PB49B

PB49C

PB49D

PB50A

PB50B

PB50C

PB50D

PB51A

PB51B

PB51C

PB51D

PB53A

PB53B

PB53C

PB53D

PB54A

PB54B

5

4

PCLKT4_2

PCLKC4_2

PCLKT4_7

PCLKC4_7

PCLKT4_1

PCLKC4_1

PCLKT4_2

PCLKC4_2

PCLKT4_7

PCLKC4_7

PCLKT4_1

PCLKC4_1

4-40

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

PCLKT4_6

PCLKC4_6

PCLKT4_0

PCLKC4_0

VREF2_4

Ball Function VCCIO Bank

Dual Function

PCLKT4_6

PCLKC4_6

PCLKT4_0

PCLKC4_0

VREF2_4

AH11

AH10

AK12

AJ12

AF14

AE14

AL11

AL10

AH9

AH8

AK11

AJ11

AH7

AH6

AK8

AJ8

PB47C

PB47D

PB49A

PB49B

PB49C

PB49D

PB51A

PB51B

PB51C

PB51D

PB52A

PB52B

PB52C

PB52D

PB53A

PB53B

PB53C

PB55A

PB55B

PB56A

PB56B

PB56C

PB57A

PB57B

PB59A

PB59B

PB60A

PB60B

PB60C

PB60D

PB61A

PB61B

PB63A

PB63B

PB64A

PB64B

PB64C

PB64D

PB65A

PB65B

PB65C

PB65D

PB67A

PB67B

PB67C

PB67D

PB68A

PB68B

PB68C

PB68D

4

PB54C

PB54D

PB55A

PB55B

PB55C

PB55D

PB57A

PB57B

PB57C

PB57D

PB58A

PB58B

PB58C

PB58D

PB67A

PB67B

PB67C

PB69A

PB69B

PB70A

PB70B

PB70C

PB73A

PB73B

PB74A

PB74B

PB75A

PB75B

PB75C

PB75D

PB77A

PB77B

PB78A

PB78B

PB79A

PB79B

PB79C

PB79D

PB81A

PB81B

PB81C

PB81D

PB82A

PB82B

PB82C

PB82D

PB83A

PB83B

PB83C

PB83D

4

PCLKT4_5

PCLKC4_5

PCLKT4_5

PCLKC4_5

PCLKT4_3

PCLKC4_3

PCLKT4_4

PCLKC4_4

PCLKT4_3

PCLKC4_3

PCLKT4_4

PCLKC4_4

AF11

AD12

AE12

AM6

AM5

AC12

AL6

AL5

AG7

AG8

AK6

AJ6

AF10

AE11

AM4

AM3

AH5

AH4

AK5

AJ5

AF8

AF7

AL4

AL3

AG5

AF6

AK3

AJ3

AE10

AD10

AL2

VREF1_4

LRC_DLLT_IN_C/LRC_DLLT_FB_D

LRC_DLLC_IN_C/LRC_DLLC_FB_D

LRC_DLLT_IN_C/LRC_DLLT_FB_D

LRC_DLLC_IN_C/LRC_DLLC_FB_D

AK2

AE9

AE8

4-41

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

AJ1

AK1

AJ2

AH3

AH1

AH2

AD9

AC10

AG2

AG1

AD8

AC9

AF2

AF1

AE6

AE7

AE1

AE2

AB8

AC8

AE4

AE3

AA10

AA9

AD1

AC1

AC7

AB7

AD5

AC5

AE5

AF5

AD3

AD4

Y10

Y9

PB69A

PB69B

PB69C

PB69D

PROBE_VCC

PROBE_GND

PR57D

PR57C

PR57B

PR57A

PR56D

PR56C

PR56B

PR56A

PR55D

PR55C

PR55B

PR55A

PR53D

PR53C

PR53B

PR53A

PR52D

PR52C

PR52B

PR52A

PR51D

PR51C

PR51B

PR51A

PR49D

PR49C

PR49B

PR49A

PR48D

PR48C

PR48B

PR48A

PR47D

PR47C

PR47B

PR47A

PR44D

PR44C

PR44B

PR44A

PR43D

PR43C

PR43B

PR43A

4

-

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLT_IN_D/LRC_DLLT_FB_C

LRC_DLLC_IN_D/LRC_DLLC_FB_C

PB85A

PB85B

PB85C

PB85D

PROBE_VCC

PROBE_GND

PR71D

PR71C

PR71B

PR71A

PR70D

PR70C

PR70B

PR70A

PR69D

PR69C

PR69B

PR69A

PR67D

PR67C

PR67B

PR67A

PR66D

PR66C

PR66B

PR66A

PR65D

PR65C

PR65B

PR65A

PR62D

PR62C

PR62B

PR62A

PR61D

PR61C

PR61B

PR61A

PR60D

PR60C

PR60B

PR60A

PR53D

PR53C

PR53B

PR53A

PR52D

PR52C

PR52B

PR52A

4

-

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLT_IN_D/LRC_DLLT_FB_C

LRC_DLLC_IN_D/LRC_DLLC_FB_C

-

3

LRC_PLLC_IN_B/LRC_PLLC_FB_A

LRC_PLLT_IN_B/LRC_PLLT_FB_A

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

3

LRC_PLLC_IN_B/LRC_PLLC_FB_A

LRC_PLLT_IN_B/LRC_PLLT_FB_A

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

LRC_DLLC_IN_E/LRC_DLLC_FB_F

LRC_DLLT_IN_E/LRC_DLLT_FB_F

LRC_DLLC_IN_E/LRC_DLLC_FB_F

LRC_DLLT_IN_E/LRC_DLLT_FB_F

VREF2_3

AC2

AD2

AC6

AB6

AA1

AB1

AA5

AB5

Y1

W1

W8

Y7

Y5

W5

4-42

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

Y6

W6

Y2

W2

W7

V8

W4

W3

V5

U6

V3

V4

V10

V9

V2

V1

U8

U7

U2

U1

U5

T6

PR42D

PR42C

PR42B

PR42A

PR40D

PR40C

PR40B

PR40A

PR39D

PR39C

PR39B

PR39A

PR38D

PR38C

PR38B

PR38A

PR36D

PR36C

PR36B

PR36A

PR35D

PR35C

PR35B

PR35A

PR34D

PR34C

PR34B

PR34A

PR31D

PR31C

PR31B

PR31A

PR30D

PR30C

PR30B

PR30A

PR29D

PR29C

PR29B

PR29A

PR27D

PR27C

PR27B

PR27A

PR26D

PR26C

PR26B

PR26A

PR25D

PR25C

3

2

DIFFR_3

PR51D

PR51C

PR51B

PR51A

PR49D

PR49C

PR49B

PR49A

PR48D

PR48C

PR48B

PR48A

PR47D

PR47C

PR47B

PR47A

PR45D

PR45C

PR45B

PR45A

PR44D

PR44C

PR44B

PR44A

PR43D

PR43C

PR43B

PR43A

PR40D

PR40C

PR40B

PR40A

PR39D

PR39C

PR39B

PR39A

PR38D

PR38C

PR38B

PR38A

PR36D

PR36C

PR36B

PR36A

PR35D

PR35C

PR35B

PR35A

PR23D

PR23C

3

2

DIFFR_3

T1

T2

U9

U10

R1

R2

T7

VREF1_3

PCLKC3_2

PCLKT3_2

PCLKC3_2

PCLKT3_2

T8

R4

R3

T5

PCLKC3_3

PCLKT3_3

PCLKC3_3

PCLKT3_3

R5

P2

P1

T9

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_3

PCLKT2_3

PCLKC2_1

PCLKT2_1

DIFFR_2

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_3

PCLKT2_3

PCLKC2_1

PCLKT2_1

DIFFR_2

T10

P4

P3

P5

P6

N1

N2

R9

R8

M1

L1

N9

M9

VREF1_2

4-43

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

H1

H2

N8

M8

H4

J4

PR25B

PR25A

2

-

PR23B

PR23A

2

-

PR22D

PR25D

PR22C

PR25C

PR22B

PR25B

PR22A

PR25A

G1

G2

L7

PR21B

PR22B

PR21A

PR22A

PR20D

PR21D

L8

PR20C

PR21C

F2

PR20B

PR21B

F1

PR20A

PR21A

K5

J5

PR18D

VREF2_2

PR18D

VREF2_2

PR18C

E2

E1

N10

M10

D2

D1

K6

K7

J8

PR18B

URC_DLLC_IN_D/URC_DLLC_FB_C

URC_DLLT_IN_D/URC_DLLT_FB_C

URC_PLLC_IN_B/URC_PLLC_FB_A

URC_PLLT_IN_B/URC_PLLT_FB_A

URC_DLLC_IN_C/URC_DLLC_FB_D

URC_DLLT_IN_C/URC_DLLT_FB_D

PR18B

URC_DLLC_IN_D/URC_DLLC_FB_C

URC_DLLT_IN_D/URC_DLLT_FB_C

URC_PLLC_IN_B/URC_PLLC_FB_A

URC_PLLT_IN_B/URC_PLLT_FB_A

URC_DLLC_IN_C/URC_DLLC_FB_D

URC_DLLT_IN_C/URC_DLLT_FB_D

PR18A

PR17D

PR17C

PR17B

PR17A

PR16D

PR16C

PR16B

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

PR16B

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

K8

J10

J9

PR16A

VCCJ

TDO

-

TDO

-

TDO

K9

J12

J13

K12

K13

K10

F5

TMS

-

TMS

-

TCK

-

TCK

-

TDI

-

TDI

-

PROGRAMN

MPIIRQN

CCLK

1

-

PROGRAMN

MPIIRQN

CCLK

1

-

CFGIRQN/MPI_IRQ_N

RESP_URC

VCC12

RESP_URC

VCC12

B5

D5

C5

B2

C1

C2

A3

D3

B3

D4

B4

A4

H5

G5

F4

-

A_REFCLKN_R

A_REFCLKP_R

A_VDDIB0_R

A_HDINP0_R

A_HDINN0_R

A_HDOUTP0_R

A_VDDOB0_R

A_HDOUTN0_R

A_VDDOB1_R

A_HDOUTN1_R

A_HDOUTP1_R

A_HDINN1_R

A_HDINP1_R

A_VDDIB1_R

A_VDDIB2_R

A_HDINP2_R

-

A_REFCLKN_R

A_REFCLKP_R

A_VDDIB0_R

A_HDINP0_R

A_HDINN0_R

A_HDOUTP0_R

A_VDDOB0_R

A_HDOUTN0_R

A_VDDOB1_R

A_HDOUTN1_R

A_HDOUTP1_R

A_HDINN1_R

A_HDINP1_R

A_VDDIB1_R

A_VDDIB2_R

A_HDINP2_R

-

PCS 3E0 CH 0 IN P

PCS 3E0 CH 0 IN N

PCS 3E0 CH 0 OUT P

-

PCS 3E0 CH 0 IN P

PCS 3E0 CH 0 IN N

PCS 3E0 CH 0 OUT P

-

PCS 3E0 CH 0 OUT N

-

PCS 3E0 CH 0 OUT N

-

PCS 3E0 CH 1 OUT N

PCS 3E0 CH 1 OUT P

PCS 3E0 CH 1 IN N

PCS 3E0 CH 1 IN P

-

PCS 3E0 CH 1 OUT N

PCS 3E0 CH 1 OUT P

PCS 3E0 CH 1 IN N

PCS 3E0 CH 1 IN P

-

H6

F6

-

PCS 3E0 CH 2 IN P

-

PCS 3E0 CH 2 IN P

4-44

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

PCS 3E0 CH 2 IN N

PCS 3E0 CH 2 OUT P

Ball Function VCCIO Bank

Dual Function

PCS 3E0 CH 2 IN N

PCS 3E0 CH 2 OUT P

G6

A6

A_HDINN2_R

A_HDOUTP2_R

A_VDDOB2_R

A_HDOUTN2_R

A_VDDOB3_R

A_HDOUTN3_R

A_HDOUTP3_R

A_HDINN3_R

A_HDINP3_R

A_VDDIB3_R

B_VDDIB0_R

B_HDINP0_R

B_HDINN0_R

B_HDOUTP0_R

B_VDDOB0_R

B_HDOUTN0_R

B_VDDOB1_R

B_HDOUTN1_R

B_HDOUTP1_R

B_HDINN1_R

B_HDINP1_R

B_VDDIB1_R

B_VDDIB2_R

B_HDINP2_R

B_HDINN2_R

B_HDOUTP2_R

B_VDDOB2_R

B_HDOUTN2_R

B_VDDOB3_R

B_HDOUTN3_R

B_HDOUTP3_R

B_HDINN3_R

B_HDINP3_R

B_VDDIB3_R

VCC12

-

A_HDINN2_R

A_HDOUTP2_R

A_VDDOB2_R

A_HDOUTN2_R

A_VDDOB3_R

A_HDOUTN3_R

A_HDOUTP3_R

A_HDINN3_R

A_HDINP3_R

A_VDDIB3_R

B_VDDIB0_R

B_HDINP0_R

B_HDINN0_R

B_HDOUTP0_R

B_VDDOB0_R

B_HDOUTN0_R

B_VDDOB1_R

B_HDOUTN1_R

B_HDOUTP1_R

B_HDINN1_R

B_HDINP1_R

B_VDDIB1_R

B_VDDIB2_R

B_HDINP2_R

B_HDINN2_R

B_HDOUTP2_R

B_VDDOB2_R

B_HDOUTN2_R

B_VDDOB3_R

B_HDOUTN3_R

B_HDOUTP3_R

B_HDINN3_R

B_HDINP3_R

B_VDDIB3_R

VCC12

-

D6

-

B6

-

PCS 3E0 CH 2 OUT N

-

PCS 3E0 CH 2 OUT N

D7

-

B7

-

PCS 3E0 CH 3 OUT N

PCS 3E0 CH 3 OUT P

PCS 3E0 CH 3 IN N

PCS 3E0 CH 3 IN P

-

PCS 3E0 CH 3 OUT N

PCS 3E0 CH 3 OUT P

PCS 3E0 CH 3 IN N

PCS 3E0 CH 3 IN P

A7

-

G7

-

F7

-

H7

-

H8

-

F8

-

PCS 3E1 CH 0 IN P

PCS 3E1 CH 0 IN N

PCS 3E1 CH 0 OUT P

-

PCS 3E1 CH 0 IN P

PCS 3E1 CH 0 IN N

PCS 3E1 CH 0 OUT P

G8

-

A8

-

D8

-

B8

-

PCS 3E1 CH 0 OUT N

-

PCS 3E1 CH 0 OUT N

D9

-

B9

-

PCS 3E1 CH 1 OUT N

PCS 3E1 CH 1 OUT P

PCS 3E1 CH 1 IN N

PCS 3E1 CH 1 IN P

-

PCS 3E1 CH 1 OUT N

PCS 3E1 CH 1 OUT P

PCS 3E1 CH 1 IN N

PCS 3E1 CH 1 IN P

A9

-

H10

G10

H9

-

H11

F11

G11

A11

D11

B11

D12

B12

A12

G12

F12

H12

B10

D10

C10

J15

K15

E13

F13

H13

G13

E14

F14

H14

G14

D13

D14

E15

-

PCS 3E1 CH 2 IN P

PCS 3E1 CH 2 IN N

PCS 3E1 CH 2 OUT P

-

PCS 3E1 CH 2 IN P

PCS 3E1 CH 2 IN N

PCS 3E1 CH 2 OUT P

-

PCS 3E1 CH 2 OUT N

-

PCS 3E1 CH 2 OUT N

-

PCS 3E1 CH 3 OUT N

PCS 3E1 CH 3 OUT P

PCS 3E1 CH 3 IN N

PCS 3E1 CH 3 IN P

-

PCS 3E1 CH 3 OUT N

PCS 3E1 CH 3 OUT P

PCS 3E1 CH 3 IN N

PCS 3E1 CH 3 IN P

-

B_REFCLKN_R

B_REFCLKP_R

PT49D

-

B_REFCLKN_R

B_REFCLKP_R

PT61D

-

1

HDC/SI

1

HDC/SI

PT49C

LDCN/SCS

PT61C

LDCN/SCS

PT49B

D8/MPI_DATA8

CS1/MPI_CS1

D9/MPI_DATA9

D10/MPI_DATA10

CS0N/MPI_CS0N

RDN/MPI_STRB_N

WRN/MPI_WR_N

D7/MPI_DATA7

D6/MPI_DATA6

D5/MPI_DATA5

D4/MPI_DATA4

PT59B

D8/MPI_DATA8

CS1/MPI_CS1

D9/MPI_DATA9

D10/MPI_DATA10

CS0N/MPI_CS0N

RDN/MPI_STRB_N

WRN/MPI_WR_N

D7/MPI_DATA7

D6/MPI_DATA6

D5/MPI_DATA5

D4/MPI_DATA4

PT49A

PT59A

PT47D

PT58D

PT47C

PT58C

PT47B

PT57B

PT47A

PT57A

PT46D

PT55D

PT46C

PT55C

PT46B

PT55B

PT46A

PT55A

PT45D

PT54D

4-45

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

D3/MPI_DATA3

D2/MPI_DATA2

D1/MPI_DATA1

D0/MPI_DATA0

QOUT/CEON

VREF2_1

Ball Function VCCIO Bank

Dual Function

D3/MPI_DATA3

D2/MPI_DATA2

D1/MPI_DATA1

D0/MPI_DATA0

QOUT/CEON

VREF2_1

E16

C13

C14

B14

B13

L13

C15

D15

J16

PT45C

PT45B

PT45A

PT43B

PT43A

PT42D

PT42B

PT42A

PT41B

PT41A

PT39D

PT39C

PT39B

PT39A

PT38D

PT38C

PT38B

PT38A

PT37C

PT37B

PT37A

PT35C

PT35B

PT35A

PT33D

PT33C

PT33B

PT33A

PT32D

PT32C

PT32B

PT32A

PT31C

PT31B

PT31A

PT29B

PT29A

PT28B

PT28A

PT27D

PT27C

PT27B

PT27A

PT25D

PT25C

PT25B

PT25A

PT24D

PT24C

PT24B

1

PT54C

PT53B

PT53A

PT51B

PT51A

PT50D

PT50B

PT50A

PT49B

PT49A

PT47D

PT47C

PT47B

PT47A

PT46D

PT46C

PT46B

PT46A

PT45C

PT45B

PT45A

PT43C

PT43B

PT43A

PT42D

PT42C

PT42B

PT42A

PT41D

PT41C

PT41B

PT41A

PT39C

PT39B

PT39A

PT38B

PT38A

PT37B

PT37A

PT35D

PT35C

PT35B

PT35A

PT33D

PT33C

PT33B

PT33A

PT30D

PT30C

PT30B

1

DOUT

MCA_DONE_IN

MCA_CLK_P1_OUT

MCA_CLK_P1_IN

MCA_DONE_IN

MCA_CLK_P1_OUT

MCA_CLK_P1_IN

K16

H15

H16

A14

A13

G16

F16

B16

B15

L16

A16

A15

L17

A17

A18

F17

G17

B17

B18

H17

H18

A19

A20

L20

J17

D21/PCLKC1_1/MPI_DATA21

D22/PCLKT1_1/MPI_DATA22

MCA_CLK_P2_OUT

MCA_CLK_P2_IN

MCA_DONE_OUT

BUSYN/RCLK/SCK

DP0/MPI_PAR0

D21/PCLKC1_1/MPI_DATA21

D22/PCLKT1_1/MPI_DATA22

MCA_CLK_P2_OUT

MCA_CLK_P2_IN

MCA_DONE_OUT

BUSYN/RCLK/SCK

DP0/MPI_PAR0

MPI_TA

DP2/MPI_PAR2

PCLKC1_0

PCLKT1_0/MPI_CLK

D24/PCLKT1_4/MPI_DATA24

MPI_RETRY

PCLKT1_0/MPI_CLK

D24/PCLKT1_4/MPI_DATA24

MPI_RETRY

A0/MPI_ADDR14

A1/MPI_ADDR15

A2/MPI_ADDR16

A3/MPI_ADDR17

A4/MPI_ADDR18

D25/PCLKC1_5/MPI_DATA25

D26/PCLKT1_5/MPI_DATA26

A5/MPI_ADDR19

A6/MPI_ADDR20

VREF1_1

A0/MPI_ADDR14

A1/MPI_ADDR15

A2/MPI_ADDR16

A3/MPI_ADDR17

A4/MPI_ADDR18

D25/PCLKC1_5/MPI_DATA25

D26/PCLKT1_5/MPI_DATA26

A5/MPI_ADDR19

A6/MPI_ADDR20

VREF1_1

A7/MPI_ADDR21

A8/MPI_ADDR22

A9/MPI_ADDR23

A10/MPI_ADDR24

A11/MPI_ADDR25

A12/MPI_ADDR26

D11/MPI_DATA11

D12/MPI_DATA12

A13/MPI_ADDR27

A14/MPI_ADDR28

A16/MPI_ADDR30

D13/MPI_DATA13

A15/MPI_ADDR29

A17/MPI_ADDR31

A19/MPI_TSIZ1

A7/MPI_ADDR21

A8/MPI_ADDR22

A9/MPI_ADDR23

A10/MPI_ADDR24

A11/MPI_ADDR25

A12/MPI_ADDR26

D11/MPI_DATA11

D12/MPI_DATA12

A13/MPI_ADDR27

A14/MPI_ADDR28

A16/MPI_ADDR30

D13/MPI_DATA13

A15/MPI_ADDR29

A17/MPI_ADDR31

A19/MPI_TSIZ1

K17

C18

D18

B19

B20

E17

E18

C20

C19

H19

G19

D20

D19

H20

G20

E19

A20/MPI_BDIP

A18/MPI_TSIZ0

4-46

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

MPI_TEA

Ball Function VCCIO Bank

Dual Function

MPI_TEA

F19

J18

PT24A

1

-

PT30A

1

-

PT23D

D14/MPI_DATA14

DP1/MPI_PAR1

A21/MPI_BURST

D15/MPI_DATA15

PT28D

D14/MPI_DATA14

DP1/MPI_PAR1

A21/MPI_BURST

D15/MPI_DATA15

K18

E20

F20

C23

D23

B23

H21

F21

G21

A21

B21

D21

B22

D22

A22

G22

F22

H22

H24

G23

H23

A24

B24

D24

B25

D25

A25

G25

F25

H25

H26

F26

G26

A26

B26

D26

B27

D27

A27

G27

F27

H27

F29

G28

H28

A29

B29

D29

PT23C

PT28C

PT23B

PT27B

PT23A

PT27A

B_REFCLKP_L

B_REFCLKN_L

VCC12

B_REFCLKP_L

B_REFCLKN_L

VCC12

B_VDDIB3_L

B_HDINP3_L

B_HDINN3_L

B_HDOUTP3_L

B_HDOUTN3_L

B_VDDOB3_L

B_HDOUTN2_L

B_VDDOB2_L

B_HDOUTP2_L

B_HDINN2_L

B_HDINP2_L

B_VDDIB2_L

B_VDDIB1_L

B_HDINP1_L

B_HDINN1_L

B_HDOUTP1_L

B_HDOUTN1_L

B_VDDOB1_L

B_HDOUTN0_L

B_VDDOB0_L

B_HDOUTP0_L

B_HDINN0_L

B_HDINP0_L

B_VDDIB0_L

A_VDDIB3_L

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

A_VDDIB1_L

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

A_HDOUTN1_L

A_VDDOB1_L

B_VDDIB3_L

B_HDINP3_L

B_HDINN3_L

B_HDOUTP3_L

B_HDOUTN3_L

B_VDDOB3_L

B_HDOUTN2_L

B_VDDOB2_L

B_HDOUTP2_L

B_HDINN2_L

B_HDINP2_L

B_VDDIB2_L

B_VDDIB1_L

B_HDINP1_L

B_HDINN1_L

B_HDOUTP1_L

B_HDOUTN1_L

B_VDDOB1_L

B_HDOUTN0_L

B_VDDOB0_L

B_HDOUTP0_L

B_HDINN0_L

B_HDINP0_L

B_VDDIB0_L

A_VDDIB3_L

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

A_VDDIB1_L

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

A_HDOUTN1_L

A_VDDOB1_L

PCS 361 CH 3 IN P

PCS 361 CH 3 IN N

PCS 361 CH 3 OUT P

PCS 361 CH 3 OUT N

PCS 361 CH 3 IN P

PCS 361 CH 3 IN N

PCS 361 CH 3 OUT P

PCS 361 CH 3 OUT N

PCS 361 CH 2 OUT N

PCS 361 CH 2 OUT P

PCS 361 CH 2 IN N

PCS 361 CH 2 IN P

PCS 361 CH 2 OUT P

PCS 361 CH 2 IN N

PCS 361 CH 2 IN P

PCS 361 CH 1 IN P

PCS 361 CH 1 IN N

PCS 361 CH 1 OUT P

PCS 361 CH 1 OUT N

PCS 361 CH 1 IN P

PCS 361 CH 1 IN N

PCS 361 CH 1 OUT P

PCS 361 CH 1 OUT N

PCS 361 CH 0 OUT N

PCS 361 CH 0 OUT P

PCS 361 CH 0 IN N

PCS 361 CH 0 IN P

PCS 361 CH 0 OUT P

PCS 361 CH 0 IN N

PCS 361 CH 0 IN P

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

PCS 360 CH 3 OUT N

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

PCS 360 CH 3 OUT N

PCS 360 CH 2 OUT N

PCS 360 CH 2 OUT P

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

PCS 360 CH 2 OUT P

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

PCS 360 CH 1 OUT N

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

PCS 360 CH 1 OUT N

4-47

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

B30

D30

A_HDOUTN0_L

-

PCS 360 CH 0 OUT N

A_HDOUTN0_L

A_VDDOB0_L

A_HDOUTP0_L

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

PB26A

-

PCS 360 CH 0 OUT N

A_VDDOB0_L

-

A30

A_HDOUTP0_L

PCS 360 CH 0 OUT P

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

-

PCS 360 CH 0 OUT P

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

C31

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

NC

-

C32

-

B31

-

AL25

AL24

AG27

AH27

AM25

AM24

AL9

5

4

7

6

3

NC

PB26B

NC

PB26C

PB26D

PB27A

NC

PB27B

NC

PB62A

AL8

NC

PB62B

AK9

AJ9

NC

PB63A

NC

PB63B

AG10

AG11

J30

NC

PB63C

PB63D

PL26A

NC

H30

NC

PL26B

M28

N28

NC

PL26C

NC

PL26D

J32

NC

PL27A

J31

NC

PL27B

N26

NC

PL27C

N27

NC

PL27D

K31

NC

PL29A

K32

NC

PL29B

P25

NC

PL29C

P26

NC

PL29D

L27

NC

PL22C

L28

NC

PL22D

M29

L29

NC

PL30A

NC

PL30B

M30

L30

NC

PL31A

NC

PL31B

L31

NC

PL34A

M31

AA29

AA30

AB31

AA31

AG30

AG29

AB29

AB30

Y25

NC

PL34B

NC

PL56A

NC

PL56B

NC

PL57A

NC

PL57B

NC

PL57C

NC

PL57D

NC

PL58A

NC

PL58B

NC

PL58C

AA25

AA8

Y8

NC

PL58D

NC

PR58D

PR58C

NC

4-48

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

AB3

AB4

AG4

AG3

AA2

AB2

AA3

AA4

L5

NC

-

PR58B

PR58A

PR57D

PR57C

PR57B

PR57A

PR56B

PR56A

PR22D

PR22C

PR34B

PR34A

PR31B

PR31A

PR30B

PR30A

PR29D

PR29C

PR29B

PR29A

PR27D

PR27C

PR27B

PR27A

PR26D

PR26C

PR26B

PR26A

VDDAX25_R

VDDAX25_L

PB21A

PB21B

PB27C

PB62C

PB66A

PB66B

PB66C

PB66D

PB22C

PB22D

PB61A

PB61B

PB61C

PB61D

VCC12

3

2

-

NC

L6

NC

M2

NC

L2

NC

L3

NC

M3

NC

L4

NC

M4

NC

P7

NC

P8

NC

K1

NC

K2

NC

N6

NC

N7

NC

J2

NC

J1

NC

N5

NC

M5

NC

H3

NC

J3

NC

A5

VDDAX25_R

VDDAX25_L

NC

A28

AJ25

AK25

AF20

AG6

AM7

AL7

AD13

AC13

AC20

AD20

AM9

AM8

AF13

AE13

E30

E29

E27

E26

E25

E24

-

5

4

5

4

-

NC

VCC12

-

4-49

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

E22

E21

VCC12

GND

-

VCC12

GND

-

E3

E4

E6

E7

E8

E9

E11

E12

A23

A31

AA13

AA15

AA18

AA20

AA26

AA6

AB10

AB24

AC14

AC22

AC29

AC3

AD11

AD19

AD27

AD7

AF12

AF18

AF24

AF30

AF4

AG15

AG21

AG9

AJ10

AJ16

AJ20

AJ26

AJ29

AJ4

AK13

AK17

AK23

AK7

AL1

AL32

AM2

AM31

4-50

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

B1

B32

C11

C12

C16

C21

C22

C24

C25

C26

C27

C29

C3

GND

-

GND

-

C30

C4

C6

C7

C8

C9

D17

F18

F3

F30

F9

G15

G24

G29

G3

J14

J22

J26

J6

K11

K19

K30

K4

L23

L9

M13

M15

M18

M20

M27

M7

N12

N14

N19

N21

N29

N3

4-51

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

P10

P13

P15

P18

P20

P24

R12

R14

R16

R17

R19

R21

R26

R6

GND

VCC

-

GND

VCC

-

T15

T18

T30

T4

U15

U18

U29

U3

V12

V14

V16

V17

V19

V21

V27

V7

W13

W15

W18

W20

W23

W9

Y12

Y14

Y19

Y21

Y30

Y4

N13

N15

N16

N17

N18

N20

P14

P16

4-52

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

P17

P19

R13

R15

R18

R20

T13

T14

T16

T17

T19

T20

U13

U14

U16

U17

U19

U20

V13

V15

V18

V20

W14

W16

W17

W19

Y13

Y15

Y16

Y17

Y18

Y20

C17

D16

F15

F24

G18

G9

VCC

-

VCC

-

VCC

VCCIO1

VCCIO2

VCCIO1

VCCIO2

J11

J19

K14

K22

G4

J7

K3

L10

M6

N4

P9

R7

4-53

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

AA7

AB9

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCAUX

-

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCAUX

-

AC4

AD6

AF3

T3

U4

V6

W10

Y3

AC11

AD14

AF15

AF9

AG12

AJ13

AJ7

AK10

AK16

AK4

AC19

AD22

AF21

AG18

AG24

AJ17

AJ23

AJ30

AK20

AK26

AA27

AB23

AC30

AD26

AF29

T29

U30

V26

W24

Y29

G30

J27

K29

L24

M26

N30

P23

R27

AA11

AA12

4-54

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

AA21

AA22

AB11

AB12

AB15

AB16

AB17

AB18

AB21

AB22

L11

VCCAUX

VTT_2

-

VCCAUX

VTT_2

-

L12

-

L14

-

L15

-

L18

-

L19

-

L21

-

L22

-

M11

M12

M21

M22

P11

-

P22

-

R11

R22

V11

-

V22

-

W11

W22

N11

R10

T11

-

2

3

4

5

6

7

-

2

3

4

5

6

7

-

VTT_2

VTT_3

U11

Y11

VTT_3

AB13

AB14

AC15

AB19

AB20

AC18

T22

VTT_4

VTT_5

VTT_6

U22

Y22

VTT_6

N22

R23

M17

M16

T12

VTT_7

VCC12

-

VCC12

-

VCC12

-

VCC12

-

T21

VCC12

-

VCC12

-

4-55

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M25, LFSC/M40 Logic Signal Connections: 1020 fcBGA^{1, 2}(Cont.)

LFSC/M25

LFSC/M40

Ball

Number

Ball Function VCCIO Bank

Dual Function

Ball Function VCCIO Bank

Dual Function

U12

U21

AA16

AA17

M14

P12

W12

AA14

AA19

W21

P21

M19

A2

VCC12

GND

-

VCC12

GND

-

A10

E28

E5

GND

NC

F10

NC

E10

E23

F23

NC

1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement).

2. The LatticeSC/M25 and LatticeSC/M40 in a 1020-pin package support a 16-bit MPI interface.

4-56

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

G27

H27

H25

H26

B33

C34

D34

C33

J27

A_REFCLKP_L

A_REFCLKN_L

VCC12

RESP_ULC

RESETN

TSALLN

DONE

INITN

-

A_REFCLKP_L

A_REFCLKN_L

VCC12

RESP_ULC

RESETN

TSALLN

DONE

INITN

-

1

7

1

7

M0

K27

M26

L26

F30

G30

H28

J28

M1

M2

M3

PL16A

PL16B

PL16C

PL16D

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL18C

PL18D

PL21A

PL21B

PL21C

PL21D

PL22A

PL22B

PL22C

PL22D

PL23A

PL23B

PL23C

PL23D

PL25A

PL25B

PL25C

PL25D

PL26A

PL26B

PL26C

PL26D

PL27A

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

PL16A

PL16B

PL16C

PL16D

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL18C

PL18D

PL20A

PL20B

PL20C

PL20D

PL21A

PL21B

PL21C

PL21D

PL29A

PL29B

PL29C

PL29D

PL31A

PL31B

PL31C

PL31D

PL33A

PL33B

PL33C

PL33D

PL35A

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

F31

G31

N25

P25

D33

E33

H29

J29

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

ULC_PLLT_IN_B/ULC_PLLT_FB_A

ULC_PLLC_IN_B/ULC_PLLC_FB_A

ULC_DLLT_IN_D/ULC_DLLT_FB_C

ULC_DLLC_IN_D/ULC_DLLC_FB_C

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

ULC_PLLT_IN_B/ULC_PLLT_FB_A

ULC_PLLC_IN_B/ULC_PLLC_FB_A

ULC_DLLT_IN_D/ULC_DLLT_FB_C

ULC_DLLC_IN_D/ULC_DLLC_FB_C

VREF2_7

F32

G32

P26

N26

H30

J30

L28

M28

J31

K31

L27

M27

J32

VREF1_7

DIFFR_7

VREF1_7

DIFFR_7

K32

L29

M29

H33

J33

N27

P27

K33

4-57

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

L33

M30

N30

M31

N31

P24

R24

M33

N33

U25

T25

L34

M34

P29

R29

N34

P34

R27

T27

R32

R31

U24

T24

P33

R33

T26

U26

T32

T31

U29

V29

T30

U30

U27

V27

R34

T34

U28

V28

V30

W30

W27

Y27

T33

U33

PL27B

PL27C

PL27D

PL29A

PL29B

PL29C

PL29D

PL30A

PL30B

PL30C

PL30D

PL31A

PL31B

PL31C

PL31D

PL34A

PL34B

PL34C

PL34D

PL35A

PL35B

PL35C

PL35D

PL36A

PL36B

PL36C

PL36D

PL38A

PL38B

PL38C

PL38D

PL39A

PL39B

PL39C

PL39D

PL40A

PL40B

PL40C

PL40D

PL43A

PL43B

PL43C

PL43D

PL44A

PL44B

7

6

PL35B

PL35C

PL35D

PL37A

PL37B

PL37C

PL37D

PL42A

PL42B

PL42C

PL42D

PL43A

PL43B

PL43C

PL43D

PL46A

PL46B

PL46C

PL46D

PL47A

PL47B

PL47C

PL47D

PL48A

PL48B

PL48C

PL48D

PL50A

PL50B

PL50C

PL50D

PL51A

PL51B

PL51C

PL51D

PL52A

PL52B

PL52C

PL52D

PL55A

PL55B

PL55C

PL55D

PL56A

PL56B

7

6

PCLKT7_1

PCLKC7_1

PCLKT7_3

PCLKC7_3

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

PCLKT7_1

PCLKC7_1

PCLKT7_3

PCLKC7_3

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

PCLKT6_3

PCLKC6_3

PCLKT6_3

PCLKC6_3

PCLKT6_2

PCLKC6_2

PCLKT6_2

PCLKC6_2

VREF1_6

4-58

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

V25

W25

U34

PL44C

PL44D

PL45A

PL45B

PL45C

PL45D

PL47A

PL47B

PL47C

PL47D

PL48A

PL48B

PL48C

PL48D

PL49A

PL49B

PL49C

PL49D

PL51A

PL51B

PL51C

PL51D

PL52A

PL52B

PL52C

PL52D

PL53A

PL53B

PL53C

PL53D

PL56A

PL56B

PL56C

PL56D

PL57A

PL57B

PL57C

PL57D

PL58A

PL58B

PL58C

PL58D

PL60A

PL60B

PL60C

6

PL56C

PL56D

PL57A

PL57B

PL57C

PL57D

PL60A

PL60B

PL60C

PL60D

PL63A

PL63B

PL63C

PL63D

PL65A

PL65B

PL65C

PL65D

PL76A

PL76B

PL76C

PL76D

PL77A

PL77B

PL77C

PL77D

PL78A

PL78B

PL78C

PL78D

PL80A

PL80B

PL80C

PL80D

PL81A

PL81B

PL81C

PL81D

PL82A

PL82B

PL82C

PL82D

PL84A

PL84B

PL84C

6

V34

V26

W26

V33

W33

V24

W24

W31

Y31

Y29

AA29

Y33

AA33

Y28

AA28

AB32

AC32

AA26

AA27

AB31

AC31

Y24

DIFFR_6

AA24

AE34

AF34

AB30

AC30

AD33

AE33

AD30

AE30

AE32

AF32

AA25

AB25

AJ34

AK34

AB27

AC27

AF33

AG33

AC29

4-59

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AD29

AE31

AF31

AF30

AF29

AH33

AJ33

AC28

AD28

AH32

AJ32

AD27

AE27

AG34

AH34

AC26

AB26

AK33

AL33

AG30

AH30

AL34

AM34

AJ30

AK30

AJ31

AH31

AD26

AD25

AL32

AL31

AG29

AG28

AF28

AF27

AM33

AN33

AH29

AJ29

AM32

AM31

AG27

AG26

AL29

AL28

PL60D

PL61A

PL61B

PL61C

PL61D

PL62A

PL62B

PL62C

PL62D

PL65A

PL65B

PL65C

PL65D

PL66A

PL66B

PL66C

PL66D

PL67A

PL67B

PL67C

PL67D

PL69A

PL69B

PL69C

PL69D

PL70A

PL70B

PL70C

PL70D

PL71A

PL71B

PL71C

PL71D

XRES

TEMP

PB3A

6

-

PL84D

PL85A

PL85B

PL85C

PL85D

PL86A

PL86B

PL86C

PL86D

PL89A

PL89B

PL89C

PL89D

PL90A

PL90B

PL90C

PL90D

PL91A

PL91B

PL91C

PL91D

PL93A

PL93B

PL93C

PL93D

PL94A

PL94B

PL94C

PL94D

PL95A

PL95B

PL95C

PL95D

XRES

TEMP

PB3A

6

-

VREF2_6

LLC_DLLT_IN_E/LLC_DLLT_FB_F

LLC_DLLC_IN_E/LLC_DLLC_FB_F

LLC_DLLT_IN_E/LLC_DLLT_FB_F

LLC_DLLC_IN_E/LLC_DLLC_FB_F

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

LLC_PLLT_IN_B/LLC_PLLT_FB_A

LLC_PLLC_IN_B/LLC_PLLC_FB_A

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

LLC_PLLT_IN_B/LLC_PLLT_FB_A

LLC_PLLC_IN_B/LLC_PLLC_FB_A

6

5

6

5

LLC_PLLT_IN_A/LLC_PLLT_FB_B

LLC_PLLC_IN_A/LLC_PLLC_FB_B

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

LLC_DLLT_IN_D/LLC_DLLT_FB_C

LLC_DLLC_IN_D/LLC_DLLC_FB_C

LLC_PLLT_IN_A/LLC_PLLT_FB_B

LLC_PLLC_IN_A/LLC_PLLC_FB_B

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

LLC_DLLT_IN_D/LLC_DLLT_FB_C

LLC_DLLC_IN_D/LLC_DLLC_FB_C

PB3B

PB3C

PB3D

PB4A

PB4B

PB4C

PB4D

PB5A

PB5B

4-60

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AH27

AH26

AN32

AP32

AF25

AE25

AN31

AN30

AK29

AK28

AP31

AP30

AD24

AE24

AM29

AM28

AJ27

AJ26

AP29

AP28

AK27

AK26

AN29

AN28

AG25

AG24

AL26

AL25

AG23

AG22

AN27

AN26

AF24

AF23

AP27

AP26

AK25

AK24

AN25

AN24

AE22

AE21

AM26

AM25

AF22

PB5C

PB5D

5

PB5C

PB5D

5

VREF1_5

PB7A

PB7B

PB7C

PB7D

PB8A

PB9A

PB8B

PB9B

PB8C

PB9C

PB8D

PB9D

PB9A

PB11A

PB11B

PB11C

PB11D

PB13A

PB13B

PB13C

PB13D

PB15A

PB15B

PB15C

PB15D

PB17A

PB17B

PB17C

PB17D

PB19A

PB19B

PB19C

PB19D

PB21A

PB21B

PB21C

PB21D

PB24A

PB24B

PB24C

PB24D

PB27A

PB27B

PB27C

PB27D

PB29A

PB29B

PB29C

PB9B

PB9C

PB9D

PB11A

PB11B

PB11C

PB11D

PB13A

PB13B

PB13C

PB13D

PB15A

PB15B

PB15C

PB15D

PB17A

PB17B

PB17C

PB17D

PB19A

PB19B

PB19C

PB19D

PB22A

PB22B

PB22C

PB22D

PB25A

PB25B

PB25C

PB25D

PB26A

PB26B

PB26C

4-61

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AF21

AN23

AN22

AP23

AP22

AG21

AG20

AP25

AP24

AD21

AD20

AL23

AL22

AH24

AH23

AM23

AM22

AJ24

AJ23

AN21

AN20

AE19

AD19

AK21

AK20

AK23

AK22

AL20

AL19

AG19

AF19

AP21

AP20

AH21

AH20

AM20

AM19

AJ21

AJ20

AK19

AK18

AE18

AD18

AN19

AN18

PB26D

PB27A

PB27B

PB29A

PB29B

PB29C

PB29D

PB30A

PB30B

PB30C

PB30D

PB31A

PB31B

PB31C

PB31D

PB33A

PB33B

PB33C

PB33D

PB34A

PB34B

PB34C

PB34D

PB35A

PB35B

PB35C

PB35D

PB37A

PB37B

PB37C

PB37D

PB38A

PB38B

PB38C

PB38D

PB39A

PB39B

PB39C

PB39D

PB41A

PB41B

PB41C

PB41D

PB42A

PB42B

5

PB29D

PB45A

PB45B

PB55A

PB55B

PB55C

PB55D

PB48A

PB48B

PB48C

PB48D

PB49A

PB49B

PB49C

PB49D

PB51A

PB51B

PB51C

PB51D

PB52A

PB52B

PB52C

PB52D

PB53A

PB53B

PB53C

PB53D

PB56A

PB56B

PB56C

PB56D

PB57A

PB57B

PB57C

PB57D

PB59A

PB59B

PB59C

PB59D

PB60A

PB60B

PB60C

PB60D

PB61A

PB61B

5

PCLKT5_3

PCLKC5_3

PCLKT5_4

PCLKC5_4

PCLKT5_5

PCLKC5_5

PCLKT5_3

PCLKC5_3

PCLKT5_4

PCLKC5_4

PCLKT5_5

PCLKC5_5

PCLKT5_0

PCLKC5_0

PCLKT5_0

PCLKC5_0

VREF2_5

PCLKT5_1

PCLKC5_1

PCLKT5_6

PCLKC5_6

PCLKT5_2

PCLKC5_2

PCLKT5_7

PCLKC5_7

VREF2_5

PCLKT5_1

PCLKC5_1

PCLKT5_6

PCLKC5_6

PCLKT5_2

PCLKC5_2

PCLKT5_7

PCLKC5_7

4-62

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AG18

AF18

AP19

AP18

AJ18

AH18

AP17

AP16

AJ17

AH17

AN17

AN16

AE17

AD17

AK17

AK16

AG17

AF17

AM16

AM15

AJ15

AJ14

AL16

AL15

AG16

AF16

AP15

AP14

AH15

AH14

AN15

AN14

AE16

AD16

AK15

AK14

AG15

AG14

AM13

AM12

AJ12

AJ11

AL13

AL12

AH12

PB42C

PB42D

PB43A

PB43B

PB43C

PB43D

PB45A

PB45B

PB45C

PB45D

PB46A

PB46B

PB46C

PB46D

PB47A

PB47B

PB47C

PB47D

PB49A

PB49B

PB49C

PB49D

PB50A

PB50B

PB50C

PB50D

PB51A

PB51B

PB51C

PB51D

PB53A

PB53B

PB53C

PB53D

PB54A

PB54B

PB54C

PB54D

PB55A

PB55B

PB55C

PB55D

PB57A

PB57B

PB57C

5

4

PB61C

PB61D

PB63A

PB63B

PB63C

PB63D

PB65A

PB65B

PB65C

PB65D

PB66A

PB66B

PB66C

PB66D

PB67A

PB67B

PB67C

PB67D

PB69A

PB69B

PB69C

PB69D

PB70A

PB70B

PB70C

PB70D

PB71A

PB71B

PB71C

PB71D

PB74A

PB74B

PB74C

PB74D

PB75A

PB75B

PB75C

PB75D

PB77A

PB77B

PB77C

PB77D

PB79A

PB79B

PB79C

5

4

PCLKT4_2

PCLKC4_2

PCLKT4_7

PCLKC4_7

PCLKT4_1

PCLKC4_1

PCLKT4_6

PCLKC4_6

PCLKT4_0

PCLKC4_0

VREF2_4

PCLKT4_2

PCLKC4_2

PCLKT4_7

PCLKC4_7

PCLKT4_1

PCLKC4_1

PCLKT4_6

PCLKC4_6

PCLKT4_0

PCLKC4_0

VREF2_4

PCLKT4_5

PCLKC4_5

PCLKT4_5

PCLKC4_5

4-63

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AH11

AN13

AN12

AD14

AD15

AP13

AP12

AK13

AK12

AP11

AP10

AN11

AN10

AF14

AF13

AM10

AM9

PB57D

PB58A

PB58B

PB58C

PB58D

PB61A

PB61B

PB61C

PB61D

PB62A

PB62B

PB63A

PB63B

PB63C

PB63D

PB67A

PB67B

PB67C

PB67D

PB69A

PB69B

PB69C

PB69D

PB70A

PB70B

PB70C

PB70D

PB73A

PB73B

PB73C

PB73D

PB74A

PB74B

PB74C

PB74D

PB75A

PB75B

PB75C

PB75D

PB77A

PB77B

PB77C

PB77D

PB78A

PB78B

4

PB79D

PB80A

4

PCLKT4_3

PCLKC4_3

PCLKT4_4

PCLKC4_4

PCLKT4_3

PCLKC4_3

PCLKT4_4

PCLKC4_4

PB80B

PB80C

PB80D

PB73A

PB73B

PB73C

PB73D

PB83A

PB83B

PB99A

PB99B

PB99C

PB99D

PB101A

PB101B

PB101C

PB101D

PB104A

PB104B

PB104C

PB104D

PB107A

PB107B

PB107C

PB107D

PB109A

PB109B

PB109C

PB109D

PB111A

PB111B

PB111C

PB111D

PB113A

PB113B

PB113C

PB113D

PB115A

PB115B

PB115C

PB115D

PB117A

PB117B

AE14

AE13

AP9

AP8

AK11

AK10

AL10

AL9

AF12

AF11

AN9

AN8

AG11

AG10

AP7

AP6

AG13

AG12

AN7

AN6

AK9

AK8

AP5

AP4

AD11

AE11

AM7

AM6

4-64

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AJ9

AJ8

PB78C

PB78D

PB79A

PB79B

PB79C

PB79D

PB81A

PB81B

PB81C

PB81D

PB82A

PB82B

PB82C

PB82D

PB83A

PB83B

PB83C

PB83D

PB85A

PB85B

PB85C

PB85D

PROBE_VCC

PROBE_GND

PR71D

PR71C

PR71B

PR71A

PR70D

PR70C

PR70B

PR70A

PR69D

PR69C

PR69B

PR69A

PR67D

PR67C

PR67B

PR67A

PR66D

PR66C

PR66B

PR66A

PR65D

4

-

PB117C

PB117D

PB119A

PB119B

PB119C

PB119D

PB121A

PB121B

PB121C

PB121D

PB123A

PB123B

PB123C

PB123D

PB124A

PB124B

PB124C

PB124D

PB125A

PB125B

PB125C

PB125D

PROBE_VCC

PROBE_GND

PR95D

4

-

AP3

AN3

AF10

AE10

AL7

AL6

AK7

AK6

AN5

AN4

AH9

AH8

AM3

AM4

AG9

AG8

AN2

AM2

AJ6

VREF1_4

LRC_DLLT_IN_C/LRC_DLLT_FB_D

LRC_DLLC_IN_C/LRC_DLLC_FB_D

LRC_DLLT_IN_C/LRC_DLLT_FB_D

LRC_DLLC_IN_C/LRC_DLLC_FB_D

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLT_IN_D/LRC_DLLT_FB_C

LRC_DLLC_IN_D/LRC_DLLC_FB_C

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLT_IN_D/LRC_DLLT_FB_C

LRC_DLLC_IN_D/LRC_DLLC_FB_C

AH6

AF7

AF8

AG7

AG6

AL4

AL3

AD10

AD9

AH4

AJ4

-

3

LRC_PLLC_IN_B/LRC_PLLC_FB_A

LRC_PLLT_IN_B/LRC_PLLT_FB_A

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

3

LRC_PLLC_IN_B/LRC_PLLC_FB_A

LRC_PLLT_IN_B/LRC_PLLT_FB_A

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

PR95C

PR95B

PR95A

PR94D

PR94C

PR94B

PR94A

AK5

AJ5

LRC_DLLC_IN_E/LRC_DLLC_FB_F

LRC_DLLT_IN_E/LRC_DLLT_FB_F

PR93D

LRC_DLLC_IN_E/LRC_DLLC_FB_F

LRC_DLLT_IN_E/LRC_DLLT_FB_F

PR93C

AM1

AL1

AH5

AG5

AL2

AK2

AB9

AC9

AH1

AG1

AE8

PR93B

PR93A

PR91D

PR91C

PR91B

PR91A

PR90D

PR90C

PR90B

PR90A

VREF2_3

PR89D

VREF2_3

4-65

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AD8

AJ3

AH3

AD7

AC7

AJ2

AH2

AF6

AF5

AF4

AE4

AD6

AC6

AG2

AF2

AC8

AB8

AK1

AJ1

AB10

AA10

AF3

AE3

AE5

AD5

AE2

AD2

AC5

AB5

AF1

AE1

AA11

Y11

AC4

AB4

AA8

AA9

AC3

AB3

AA7

Y7

PR65C

PR65B

PR65A

PR62D

PR62C

PR62B

PR62A

PR61D

PR61C

PR61B

PR61A

PR60D

PR60C

PR60B

PR60A

PR58D

PR58C

PR58B

PR58A

PR57D

PR57C

PR57B

PR57A

PR56D

PR56C

PR56B

PR56A

PR53D

PR53C

PR53B

PR53A

PR52D

PR52C

PR52B

PR52A

PR51D

PR51C

PR51B

PR51A

PR49D

PR49C

PR49B

PR49A

PR48D

PR48C

3

PR89C

PR89B

PR89A

PR86D

PR86C

PR86B

PR86A

PR85D

PR85C

PR85B

PR85A

PR84D

PR84C

PR84B

PR84A

PR82D

PR82C

PR82B

PR82A

PR81D

PR81C

PR81B

PR81A

PR80D

PR80C

PR80B

PR80A

PR78D

PR78C

PR78B

PR78A

PR77D

PR77C

PR77B

PR77A

PR76D

PR76C

PR76B

PR76A

PR65D

PR65C

PR65B

PR65A

PR63D

PR63C

3

DIFFR_3

AA2

Y2

AA6

Y6

4-66

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

Y4

W4

W11

V11

W2

V2

PR48B

PR48A

PR47D

PR47C

PR47B

PR47A

PR45D

PR45C

PR45B

PR45A

PR44D

PR44C

PR44B

PR44A

PR43D

PR43C

PR43B

PR43A

PR40D

PR40C

PR40B

PR40A

PR39D

PR39C

PR39B

PR39A

PR38D

PR38C

PR38B

PR38A

PR36D

PR36C

PR36B

PR36A

PR35D

PR35C

PR35B

PR35A

PR34D

PR34C

PR34B

PR34A

PR31D

PR31C

PR31B

3

2

PR63B

PR63A

PR60D

PR60C

PR60B

PR60A

PR57D

PR57C

PR57B

PR57A

PR56D

PR56C

PR56B

PR56A

PR55D

PR55C

PR55B

PR55A

PR52D

PR52C

PR52B

PR52A

PR51D

PR51C

PR51B

PR51A

PR50D

PR50C

PR50B

PR50A

PR48D

PR48C

PR48B

PR48A

PR47D

PR47C

PR47B

PR47A

PR46D

PR46C

PR46B

PR46A

PR43D

PR43C

PR43B

3

2

W9

V9

V1

U1

W10

V10

U2

T2

Y8

W8

W5

V5

VREF1_3

V7

PCLKC3_2

PCLKT3_2

PCLKC3_2

PCLKT3_2

U7

T1

R1

V8

PCLKC3_3

PCLKT3_3

PCLKC3_3

PCLKT3_3

U8

U5

T5

V6

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_3

PCLKT2_3

PCLKC2_1

PCLKT2_1

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_3

PCLKT2_3

PCLKC2_1

PCLKT2_1

U6

T4

T3

U9

T9

R2

P2

T11

U11

R4

R3

T8

R8

P1

N1

R6

P6

M1

4-67

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

L1

T10

U10

N2

M2

R11

P11

N4

M4

N5

M5

L2

PR31A

PR30D

PR30C

PR30B

PR30A

PR29D

PR29C

PR29B

PR29A

PR27D

PR27C

PR27B

PR27A

PR26D

PR26C

PR26B

PR26A

PR25D

PR25C

PR25B

PR25A

PR23D

PR23C

PR23B

PR23A

PR22D

PR22C

PR22B

PR22A

PR21D

PR21C

PR21B

PR21A

PR18D

PR18C

PR18B

PR18A

PR17D

PR17C

PR17B

PR17A

PR16D

PR16C

PR16B

PR16A

2

PR43A

PR42D

PR42C

PR42B

PR42A

PR37D

PR37C

PR37B

PR37A

PR35D

PR35C

PR35B

PR35A

PR33D

PR33C

PR33B

PR33A

PR31D

PR31C

PR31B

PR31A

PR29D

PR29C

PR29B

PR29A

PR21D

PR21C

PR21B

PR21A

PR20D

PR20C

PR20B

PR20A

PR18D

PR18C

PR18B

PR18A

PR17D

PR17C

PR17B

PR17A

PR16D

PR16C

PR16B

PR16A

2

K2

P8

N8

J2

H2

M6

L6

K3

J3

M8

L8

DIFFR_2

VREF1_2

DIFFR_2

VREF1_2

K4

J4

M7

L7

J5

H5

N9

P9

G3

F3

J6

VREF2_2

H6

E2

D2

P10

N10

G4

F4

URC_DLLC_IN_D/URC_DLLC_FB_C

URC_DLLT_IN_D/URC_DLLT_FB_C

URC_PLLC_IN_B/URC_PLLC_FB_A

URC_PLLT_IN_B/URC_PLLT_FB_A

URC_DLLC_IN_C/URC_DLLC_FB_D

URC_DLLT_IN_C/URC_DLLT_FB_D

URC_DLLC_IN_D/URC_DLLC_FB_C

URC_DLLT_IN_D/URC_DLLT_FB_C

URC_PLLC_IN_B/URC_PLLC_FB_A

URC_PLLT_IN_B/URC_PLLT_FB_A

URC_DLLC_IN_C/URC_DLLC_FB_D

URC_DLLT_IN_C/URC_DLLT_FB_D

J7

H7

G5

F5

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

4-68

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

C2

M9

L9

VCCJ

TDO

-

1

-

VCCJ

TDO

-

1

-

TDO

TMS

D1

C1

J8

TCK

TDI

PROGRAMN

MPIIRQN

PROGRAMN

MPIIRQN

K8

B2

H9

H10

H8

G8

C3

D3

A3

B3

E5

A4

F6

CFGIRQN/MPI_IRQ_N

CCLK

RESP_URC

VCC12

RESP_URC

VCC12

A_REFCLKN_R

A_REFCLKP_R

VCC12

A_REFCLKN_R

A_REFCLKP_R

VCC12

A_VDDIB0_R

A_HDINP0_R

A_HDINN0_R

VCC12

A_VDDIB0_R

A_HDINP0_R

A_HDINN0_R

VCC12

PCS 3E0 CH 0 IN P

PCS 3E0 CH 0 IN N

PCS 3E0 CH 0 IN P

PCS 3E0 CH 0 IN N

A_HDOUTP0_R

A_VDDOB0_R

A_HDOUTN0_R

A_VDDOB1_R

A_HDOUTN1_R

VCC12

PCS 3E0 CH 0 OUT P

PCS 3E0 CH 0 OUT N

PCS 3E0 CH 1 OUT N

A_HDOUTP0_R

A_VDDOB0_R

A_HDOUTN0_R

A_VDDOB1_R

A_HDOUTN1_R

VCC12

PCS 3E0 CH 0 OUT P

PCS 3E0 CH 0 OUT N

PCS 3E0 CH 1 OUT N

B4

F7

B5

E6

A5

B6

A6

C6

D4

C7

D5

A7

B7

E7

A8

F8

A_HDOUTP1_R

A_HDINN1_R

A_HDINP1_R

VCC12

PCS 3E0 CH 1 OUT P

PCS 3E0 CH 1 IN N

PCS 3E0 CH 1 IN P

A_HDOUTP1_R

A_HDINN1_R

A_HDINP1_R

VCC12

PCS 3E0 CH 1 OUT P

PCS 3E0 CH 1 IN N

PCS 3E0 CH 1 IN P

A_VDDIB1_R

VCC12

A_VDDIB1_R

VCC12

A_VDDIB2_R

A_HDINP2_R

A_HDINN2_R

VCC12

A_VDDIB2_R

A_HDINP2_R

A_HDINN2_R

VCC12

PCS 3E0 CH 2 IN P

PCS 3E0 CH 2 IN N

PCS 3E0 CH 2 IN P

PCS 3E0 CH 2 IN N

A_HDOUTP2_R

A_VDDOB2_R

A_HDOUTN2_R

A_VDDOB3_R

A_HDOUTN3_R

VCC12

PCS 3E0 CH 2 OUT P

PCS 3E0 CH 2 OUT N

PCS 3E0 CH 3 OUT N

A_HDOUTP2_R

A_VDDOB2_R

A_HDOUTN2_R

A_VDDOB3_R

A_HDOUTN3_R

VCC12

PCS 3E0 CH 2 OUT P

PCS 3E0 CH 2 OUT N

PCS 3E0 CH 3 OUT N

B8

F9

B9

E8

A9

B10

A10

C10

D6

G10

A_HDOUTP3_R

A_HDINN3_R

A_HDINP3_R

VCC12

PCS 3E0 CH 3 OUT P

PCS 3E0 CH 3 IN N

PCS 3E0 CH 3 IN P

A_HDOUTP3_R

A_HDINN3_R

A_HDINP3_R

VCC12

PCS 3E0 CH 3 OUT P

PCS 3E0 CH 3 IN N

PCS 3E0 CH 3 IN P

A_VDDIB3_R

VCC12

A_VDDIB3_R

VCC12

4-69

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

D7

E10

F10

K10

A11

D10

B11

D11

B12

L10

A12

F11

E11

G11

D8

B_VDDIB0_R

B_HDINP0_R

B_HDINN0_R

VCC12

-

B_VDDIB0_R

B_HDINP0_R

B_HDINN0_R

VCC12

-

PCS 3E1 CH 0 IN P

PCS 3E1 CH 0 IN N

PCS 3E1 CH 0 IN P

PCS 3E1 CH 0 IN N

-

B_HDOUTP0_R

B_VDDOB0_R

B_HDOUTN0_R

B_VDDOB1_R

B_HDOUTN1_R

VCC12

-

PCS 3E1 CH 0 OUT P

PCS 3E1 CH 0 OUT N

PCS 3E1 CH 1 OUT N

B_HDOUTP0_R

B_VDDOB0_R

B_HDOUTN0_R

B_VDDOB1_R

B_HDOUTN1_R

VCC12

-

PCS 3E1 CH 0 OUT P

PCS 3E1 CH 0 OUT N

PCS 3E1 CH 1 OUT N

-

B_HDOUTP1_R

B_HDINN1_R

B_HDINP1_R

VCC12

-

PCS 3E1 CH 1 OUT P

PCS 3E1 CH 1 IN N

PCS 3E1 CH 1 IN P

B_HDOUTP1_R

B_HDINN1_R

B_HDINP1_R

VCC12

-

PCS 3E1 CH 1 OUT P

PCS 3E1 CH 1 IN N

PCS 3E1 CH 1 IN P

-

B_VDDIB1_R

VCC12

-

B_VDDIB1_R

VCC12

-

G12

D9

-

B_VDDIB2_R

B_HDINP2_R

B_HDINN2_R

VCC12

-

B_VDDIB2_R

B_HDINP2_R

B_HDINN2_R

VCC12

-

E12

F12

K11

A13

D12

B13

D13

B14

L11

A14

F13

E13

G13

E9

-

PCS 3E1 CH 2 IN P

PCS 3E1 CH 2 IN N

-

PCS 3E1 CH 2 IN P

PCS 3E1 CH 2 IN N

-

B_HDOUTP2_R

B_VDDOB2_R

B_HDOUTN2_R

B_VDDOB3_R

B_HDOUTN3_R

VCC12

-

PCS 3E1 CH 2 OUT P

PCS 3E1 CH 2 OUT N

PCS 3E1 CH 3 OUT N

B_HDOUTP2_R

B_VDDOB2_R

B_HDOUTN2_R

B_VDDOB3_R

B_HDOUTN3_R

VCC12

-

PCS 3E1 CH 2 OUT P

PCS 3E1 CH 2 OUT N

PCS 3E1 CH 3 OUT N

-

B_HDOUTP3_R

B_HDINN3_R

B_HDINP3_R

VCC12

-

PCS 3E1 CH 3 OUT P

PCS 3E1 CH 3 IN N

PCS 3E1 CH 3 IN P

B_HDOUTP3_R

B_HDINN3_R

B_HDINP3_R

VCC12

-

PCS 3E1 CH 3 OUT P

PCS 3E1 CH 3 IN N

PCS 3E1 CH 3 IN P

-

B_VDDIB3_R

VCC12

-

B_VDDIB3_R

VCC12

-

L13

J11

H11

M15

M16

F14

G14

L15

L14

D14

E14

L16

K16

G15

-

B_REFCLKN_R

B_REFCLKP_R

PT61D

-

B_REFCLKN_R

B_REFCLKP_R

PT77D

-

1

HDC/SI

1

HDC/SI

PT61C

LDCN/SCS

PT77C

LDCN/SCS

PT59B

D8/MPI_DATA8

CS1/MPI_CS1

D9/MPI_DATA9

D10/MPI_DATA10

CS0N/MPI_CS0N

RDN/MPI_STRB_N

WRN/MPI_WR_N

D7/MPI_DATA7

D6/MPI_DATA6

PT77B

D8/MPI_DATA8

CS1/MPI_CS1

D9/MPI_DATA9

D10/MPI_DATA10

CS0N/MPI_CS0N

RDN/MPI_STRB_N

WRN/MPI_WR_N

D7/MPI_DATA7

D6/MPI_DATA6

PT59A

PT77A

PT58D

PT75D

PT58C

PT75C

PT57B

PT75B

PT57A

PT75A

PT55D

PT74D

PT55C

PT74C

PT55B

PT74B

4-70

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

VCCIO

Bank

Ball

VCCIO

Bank

Number

Function

Dual Function

D5/MPI_DATA5

D4/MPI_DATA4

D3/MPI_DATA3

D2/MPI_DATA2

D1/MPI_DATA1

Function

Dual Function

D5/MPI_DATA5

D4/MPI_DATA4

D3/MPI_DATA3

D2/MPI_DATA2

D1/MPI_DATA1

F15

K14

K13

B15

A15

J14

H14

A16

B16

J13

H13

D15

E15

J16

J17

D16

E16

H15

H16

C15

C16

L17

K17

E17

F17

G17

H17

A17

B17

G18

H18

E18

F18

J18

J19

C20

C19

K18

L18

D19

E19

H19

H20

A18

B18

PT55A

PT54D

PT54C

PT53B

PT53A

PT51D

PT51C

PT51B

PT51A

PT50D

PT50C

PT50B

PT50A

PT49D

PT49C

PT49B

PT49A

PT47D

PT47C

PT47B

PT47A

PT46D

PT46C

PT46B

PT46A

PT45D

PT45C

PT45B

PT45A

PT43D

PT43C

PT43B

PT43A

PT42D

PT42C

PT42B

PT42A

PT41D

PT41C

PT41B

PT41A

PT39D

PT39C

PT39B

PT39A

1

PT74A

PT73D

PT73C

PT73B

PT73A

PT71D

PT71C

PT71B

PT71A

PT70D

PT70C

PT70B

PT70A

PT69D

PT69C

PT69B

PT69A

PT67D

PT67C

PT67B

PT67A

PT66D

PT66C

PT66B

PT66A

PT65D

PT65C

PT65B

PT65A

PT63D

PT63C

PT63B

PT63A

PT61D

PT61C

PT61B

PT61A

PT60D

PT60C

PT60B

PT60A

PT59D

PT59C

PT59B

PT59A

1

D16/PCLKC1_3/MPI_DATA16

D17/PCLKT1_3/MPI_DATA17

D0/MPI_DATA0

D16/PCLKC1_3/MPI_DATA16

D17/PCLKT1_3/MPI_DATA17

D0/MPI_DATA0

QOUT/CEON

VREF2_1

D18/MPI_DATA18

DOUT

D18/MPI_DATA18

DOUT

MCA_DONE_IN

D19/PCLKC1_2/MPI_DATA19

D20/PCLKT1_2/MPI_DATA20

MCA_CLK_P1_OUT

MCA_CLK_P1_IN

D21/PCLKC1_1/MPI_DATA21

D22/PCLKT1_1/MPI_DATA22

MCA_CLK_P2_OUT

MCA_CLK_P2_IN

MCA_DONE_OUT

BUSYN/RCLK/SCK

DP0/MPI_PAR0

D19/PCLKC1_2/MPI_DATA19

D20/PCLKT1_2/MPI_DATA20

MCA_CLK_P1_OUT

MCA_CLK_P1_IN

D21/PCLKC1_1/MPI_DATA21

D22/PCLKT1_1/MPI_DATA22

MCA_CLK_P2_OUT

MCA_CLK_P2_IN

MCA_DONE_OUT

BUSYN/RCLK/SCK

DP0/MPI_PAR0

MPI_TA

D23/MPI_DATA23

DP2/MPI_PAR2

D23/MPI_DATA23

DP2/MPI_PAR2

PCLKC1_0

PCLKT1_0/MPI_CLK

DP3/PCLKC1_4/MPI_PAR3

D24/PCLKT1_4/MPI_DATA24

MPI_RETRY

PCLKT1_0/MPI_CLK

DP3/PCLKC1_4/MPI_PAR3

D24/PCLKT1_4/MPI_DATA24

MPI_RETRY

A0/MPI_ADDR14

A1/MPI_ADDR15

A2/MPI_ADDR16

A3/MPI_ADDR17

A4/MPI_ADDR18

D25/PCLKC1_5/MPI_DATA25

D26/PCLKT1_5/MPI_DATA26

A5/MPI_ADDR19

D25/PCLKC1_5/MPI_DATA25

D26/PCLKT1_5/MPI_DATA26

A5/MPI_ADDR19

A6/MPI_ADDR20

D27/MPI_DATA27

VREF1_1

D27/MPI_DATA27

VREF1_1

A7/MPI_ADDR21

A8/MPI_ADDR22

4-71

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

H21

J21

PT38D

PT38C

1

-

D28/PCLKC1_6/MPI_DATA28

D29/PCLKT1_6/MPI_DATA29

A9/MPI_ADDR23

PT57D

PT57C

1

-

D28/PCLKC1_6/MPI_DATA28

D29/PCLKT1_6/MPI_DATA29

A9/MPI_ADDR23

A19

B19

H22

J22

PT38B

PT57B

PT38A

A10/MPI_ADDR24

D30/PCLKC1_7/MPI_DATA30

D31/PCLKT1_7/MPI_DATA31

A11/MPI_ADDR25

A12/MPI_ADDR26

D11/MPI_DATA11

D12/MPI_DATA12

A13/MPI_ADDR27

A14/MPI_ADDR28

A16/MPI_ADDR30

D13/MPI_DATA13

A15/MPI_ADDR29

A17/MPI_ADDR31

A19/MPI_TSIZ1

PT57A

A10/MPI_ADDR24

D30/PCLKC1_7/MPI_DATA30

D31/PCLKT1_7/MPI_DATA31

A11/MPI_ADDR25

A12/MPI_ADDR26

D11/MPI_DATA11

D12/MPI_DATA12

A13/MPI_ADDR27

A14/MPI_ADDR28

A16/MPI_ADDR30

D13/MPI_DATA13

A15/MPI_ADDR29

A17/MPI_ADDR31

A19/MPI_TSIZ1

PT37D

PT56D

PT37C

PT56C

F20

G20

K21

K22

A20

B20

L21

L20

D20

E20

L19

K19

D21

E21

M20

M19

F21

G21

H24

J24

PT37B

PT56B

PT37A

PT56A

PT35D

PT55D

PT35C

PT55C

PT35B

PT55B

PT35A

PT55A

PT33D

PT53D

PT33C

PT53C

PT33B

PT53B

PT33A

PT53A

PT30D

PT52D

PT30C

A20/MPI_BDIP

PT52C

A20/MPI_BDIP

PT30B

A18/MPI_TSIZ0

PT52B

A18/MPI_TSIZ0

PT30A

MPI_TEA

PT52A

MPI_TEA

PT28D

D14/MPI_DATA14

DP1/MPI_PAR1

PT51D

D14/MPI_DATA14

DP1/MPI_PAR1

PT28C

PT51C

PT27B

A21/MPI_BURST

PT51B

A21/MPI_BURST

PT27A

D15/MPI_DATA15

PT51A

D15/MPI_DATA15

B_REFCLKP_L

B_REFCLKN_L

VCC12

B_REFCLKP_L

B_REFCLKN_L

VCC12

-

L22

E26

G22

E22

F22

A21

L24

B21

D22

B22

D23

A22

K24

F23

E23

D26

G23

D27

G24

-

B_VDDIB3_L

VCC12

-

B_VDDIB3_L

VCC12

-

B_HDINP3_L

B_HDINN3_L

B_HDOUTP3_L

VCC12

-

PCS 361 CH 3 IN P

PCS 361 CH 3 IN N

PCS 361 CH 3 OUT P

B_HDINP3_L

B_HDINN3_L

B_HDOUTP3_L

VCC12

-

PCS 361 CH 3 IN P

PCS 361 CH 3 IN N

PCS 361 CH 3 OUT P

-

B_HDOUTN3_L

B_VDDOB3_L

B_HDOUTN2_L

B_VDDOB2_L

B_HDOUTP2_L

VCC12

-

PCS 361 CH 3 OUT N

PCS 361 CH 2 OUT N

PCS 361 CH 2 OUT P

B_HDOUTN3_L

B_VDDOB3_L

B_HDOUTN2_L

B_VDDOB2_L

B_HDOUTP2_L

VCC12

-

PCS 361 CH 3 OUT N

PCS 361 CH 2 OUT N

PCS 361 CH 2 OUT P

-

B_HDINN2_L

B_HDINP2_L

B_VDDIB2_L

VCC12

-

PCS 361 CH 2 IN N

PCS 361 CH 2 IN P

B_HDINN2_L

B_HDINP2_L

B_VDDIB2_L

VCC12

-

PCS 361 CH 2 IN N

PCS 361 CH 2 IN P

-

B_VDDIB1_L

VCC12

-

B_VDDIB1_L

VCC12

-

4-72

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

E24

F24

A23

L25

B23

D24

B24

D25

A24

K25

F25

E25

D28

G25

D29

C25

A25

B25

A26

E27

B26

F26

B27

F27

A27

E28

B28

A28

D30

C28

D31

C29

A29

B29

A30

E29

B30

F28

B31

F29

A31

E30

B32

A32

D32

B_HDINP1_L

B_HDINN1_L

B_HDOUTP1_L

VCC12

-

PCS 361 CH 1 IN P

PCS 361 CH 1 IN N

PCS 361 CH 1 OUT P

B_HDINP1_L

B_HDINN1_L

B_HDOUTP1_L

VCC12

-

PCS 361 CH 1 IN P

PCS 361 CH 1 IN N

PCS 361 CH 1 OUT P

B_HDOUTN1_L

B_VDDOB1_L

B_HDOUTN0_L

B_VDDOB0_L

B_HDOUTP0_L

VCC12

PCS 361 CH 1 OUT N

PCS 361 CH 0 OUT N

PCS 361 CH 0 OUT P

B_HDOUTN1_L

B_VDDOB1_L

B_HDOUTN0_L

B_VDDOB0_L

B_HDOUTP0_L

VCC12

PCS 361 CH 1 OUT N

PCS 361 CH 0 OUT N

PCS 361 CH 0 OUT P

B_HDINN0_L

B_HDINP0_L

B_VDDIB0_L

VCC12

PCS 361 CH 0 IN N

PCS 361 CH 0 IN P

B_HDINN0_L

B_HDINP0_L

B_VDDIB0_L

VCC12

PCS 361 CH 0 IN N

PCS 361 CH 0 IN P

A_VDDIB3_L

VCC12

A_VDDIB3_L

VCC12

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

VCC12

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

VCC12

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

VCC12

PCS 360 CH 3 OUT N

PCS 360 CH 2 OUT N

PCS 360 CH 2 OUT P

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

VCC12

PCS 360 CH 3 OUT N

PCS 360 CH 2 OUT N

PCS 360 CH 2 OUT P

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

VCC12

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

VCC12

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

A_VDDIB1_L

VCC12

A_VDDIB1_L

VCC12

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

VCC12

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

VCC12

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

A_HDOUTN1_L

A_VDDOB1_L

A_HDOUTN0_L

A_VDDOB0_L

A_HDOUTP0_L

VCC12

PCS 360 CH 1 OUT N

PCS 360 CH 0 OUT N

PCS 360 CH 0 OUT P

A_HDOUTN1_L

A_VDDOB1_L

A_HDOUTN0_L

A_VDDOB0_L

A_HDOUTP0_L

VCC12

PCS 360 CH 1 OUT N

PCS 360 CH 0 OUT N

PCS 360 CH 0 OUT P

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

4-73

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

C32

E34

F34

F33

G33

K30

L30

G34

H34

M32

N32

P28

R28

J34

VCC12

NC

-

VCC12

PL22A

PL22B

PL24A

PL24B

PL25A

PL25B

PL26A

PL26B

PL39A

PL39B

PL39C

PL39D

PL41A

PL41B

PL41C

PL41D

PL59A

PL59B

PL61A

PL61B

PL64A

PL64B

PL67A

PL67B

PL68A

PL68B

PL69A

PL69B

PR69B

PR69A

PR68B

PR68A

PR67B

PR67A

PR64B

PR64A

PR61B

PR61A

PR59B

PR59A

PR41D

PR41C

PR41B

PR41A

-

7

6

3

2

K34

P30

R30

W34

Y34

W32

Y32

AA34

AB34

AC34

AD34

Y30

AA30

AB33

AC33

AC2

AB2

AA5

Y5

AD1

AC1

AB1

AA1

Y3

W3

Y1

W1

R5

P5

K1

J1

4-74

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

R7

P7

NC

-

PR39D

PR39C

PR39B

PR39A

PR26B

PR26A

PR25B

PR25A

PR24B

PR24A

PR22B

PR22A

GND

2

-

NC

N3

NC

M3

NC

H1

NC

G1

NC

L5

NC

K5

NC

G2

NC

F2

NC

F1

NC

E1

NC

A2

GND

A33

GND

-

AA15

AA20

AA32

AA4

AB28

AB6

AC11

AC18

AC25

AD23

AD3

AD31

AE12

AE15

AE29

AE7

AE9

AF20

AF26

AG32

AG4

AH13

AH19

AH25

AH7

AJ10

AJ16

AJ22

AJ28

AK3

AK31

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

4-75

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AL11

AL17

AL21

AL27

AL5

AM14

AM18

AM24

AM30

AM8

AN1

AN34

AP2

AP33

B1

GND

-

GND

-

B34

C11

C12

C13

C14

C17

C21

C22

C23

C24

C26

C27

C30

C31

C4

C5

C8

C9

D18

E32

E4

F19

G16

G29

G7

H3

H31

J10

J15

J26

4-76

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

K20

K23

K26

K28

K6

GND

-

GND

-

K9

L12

L32

L4

M10

M17

M24

N29

N7

P15

P20

P3

P31

R10

R14

R16

R19

R21

R26

T15

T17

T18

T20

T28

T6

U16

U19

U23

U32

U4

V12

V16

V19

V3

V31

W15

W17

W18

W20

W29

4-77

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

W7

AA14

AA16

AA17

AA18

AA19

AA21

AB13

AB22

N13

N22

P14

P16

P17

P18

P19

P21

R15

R17

R18

R20

T14

GND

VCC

-

GND

VCC

-

T16

T19

T21

U14

U15

U17

U18

U20

U21

V14

V15

V17

V18

V20

V21

W14

W16

W19

W21

Y15

Y17

Y18

Y20

4-78

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AB15

AB20

N15

VCC12

-

VCC12

-

VCC12

N20

VCC12

R13

VCC12

R22

VCC12

Y13

VCC12

Y22

VCC12

AA12

AA23

AB12

AB16

AB17

AB18

AB19

AB23

AC12

AC13

Y19

VCCAUX

GND

VCCAUX

GND

AC14

AC17

AC21

AC22

AC23

M13

M14

M18

M21

M22

N12

VCCAUX

N16

N17

N18

N19

N23

P12

P23

T13

T22

U12

U13

U22

V13

V22

V23

4-79

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

W13

W22

Y21

Y25

C18

D17

F16

G19

J20

K12

K15

L23

Y9

VCCAUX

GND

-

VCCAUX

GND

-

GND

VCCIO1

GND

VCCIO1

GND

J9

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO1

VCCIO2

VCCIO3

VCCIO4

E3

G6

H4

K7

L3

M11

N6

P4

R9

AA3

AB7

AC10

AD4

AE6

AG3

AK4

T7

U3

V4

W6

Y10

AD12

AF15

AF9

AH10

AH16

AJ13

AJ7

AL14

AL8

AM11

4-80

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AM17

AM5

AE20

AE23

AE26

AH22

AH28

AJ19

AJ25

AL18

AL24

AL30

AM21

AM27

AA31

AB29

AC24

AD32

AE28

AG31

AK32

T29

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO1

VTT_2

-

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO1

VTT_2

-

U31

-

V32

-

W28

Y26

-

E31

-

G28

-

H32

-

K29

-

L31

-

M25

-

N28

-

P32

-

R25

-

J25

-

N11

2

3

4

2

3

4

R12

VTT_2

T12

VTT_2

AB11

W12

Y12

VTT_3

AC15

AC16

AD13

VTT_4

4-81

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M40, LFSC/M80 Logic Signal Connections: 1152 fcBGA^{1, 2}(Cont.)

LFSC/M40

LFSC/M80

Ball

Number

Ball

Function

VCCIO

Bank

Ball

Function

VCCIO

Bank

Dual Function

AC19

AC20

AD22

AB24

W23

Y23

VTT_5

VTT_6

VTT_7

VDDAX25_R

VDDAX25_L

GND

5

6

7

-

VTT_5

VTT_6

VTT_7

VDDAX25_R

VDDAX25_L

GND

5

6

7

-

N24

R23

T23

M12

M23

Y16

-

Y14

GND

-

GND

-

N21

P22

VCC12

NC

-

VCC12

NC

-

AA22

AB21

AB14

AA13

P13

-

N14

G26

G9

-

NC

-

NC

-

J12

NC

-

NC

-

H12

H23

J23

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

1. Differential pair grouping within a PCI is A (True) and B (complement) and C (True) and D (Complement).

2. The LatticeSC/M40 and LatticeSC/M80 in an 1152-pin package support a 32-bit MPI interface.

4-82

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

G27

H27

H25

H26

B33

C34

D34

C33

J27

Ball Function

A_REFCLKP_L

A_REFCLKN_L

VCC12

RESP_ULC

RESETN

TSALLN

DONE

VCCIO Bank

Dual Function

-

1

7

INITN

M0

K27

M26

L26

M1

M2

M3

F30

G30

H28

J28

PL15A

PL15B

PL15C

PL15D

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL18C

PL18D

PL19A

PL19B

PL19C

PL19D

PL26A

PL26B

PL26C

PL26D

PL43A

PL43B

PL43C

PL43D

PL45A

PL45B

PL45C

PL45D

PL47A

PL47B

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

F31

G31

N25

P25

D33

E33

H29

J29

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

ULC_PLLT_IN_B/ULC_PLLT_FB_A

ULC_PLLC_IN_B/ULC_PLLC_FB_A

ULC_DLLT_IN_D/ULC_DLLT_FB_C

ULC_DLLC_IN_D/ULC_DLLC_FB_C

VREF2_7

F32

G32

P26

N26

H30

J30

L28

M28

J31

K31

L27

VREF1_7

DIFFR_7

M27

J32

K32

L29

M29

H33

J33

4-83

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

N27

P27

K33

L33

Ball Function

PL47C

PL47D

PL49A

PL49B

PL49C

PL49D

PL51A

PL51B

PL51C

PL51D

PL56A

PL56B

PL56C

PL56D

PL57A

PL57B

PL57C

PL57D

PL60A

PL60B

PL60C

PL60D

PL61A

PL61B

PL61C

PL61D

PL62A

PL62B

PL62C

PL62D

PL64A

PL64B

PL64C

PL64D

PL65A

PL65B

PL65C

PL65D

PL66A

PL66B

PL66C

PL66D

PL69A

VCCIO Bank

Dual Function

7

6

M30

N30

M31

N31

P24

R24

M33

N33

U25

T25

L34

M34

P29

R29

N34

P34

R27

T27

R32

R31

U24

T24

PCLKT7_1

PCLKC7_1

PCLKT7_3

PCLKC7_3

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

P33

R33

T26

U26

T32

T31

U29

V29

T30

U30

U27

V27

R34

T34

PCLKT6_3

PCLKC6_3

U28

V28

V30

PCLKT6_2

PCLKC6_2

4-84

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

W30

W27

Y27

Ball Function

PL69B

PL69C

PL69D

PL70A

PL70B

PL70C

PL70D

PL71A

PL71B

PL71C

PL71D

PL74A

PL74B

PL74C

PL74D

PL77A

PL77B

PL77C

PL77D

PL79A

PL79B

PL79C

PL79D

PL90A

PL90B

PL90C

PL90D

PL91A

PL91B

PL91C

PL91D

PL92A

PL92B

PL92C

PL92D

PL94A

PL94B

PL94C

PL94D

PL96A

PL96B

PL96C

PL96D

VCCIO Bank

Dual Function

6

VREF1_6

T33

U33

V25

W25

U34

V34

V26

W26

V33

W33

V24

W24

W31

Y31

Y29

AA29

Y33

AA33

Y28

AA28

AB32

AC32

AA26

AA27

AB31

AC31

Y24

DIFFR_6

AA24

AE34

AF34

AB30

AC30

AD33

AE33

AD30

AE30

AE32

AF32

AA25

AB25

4-85

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AJ34

Ball Function

PL98A

VCCIO Bank

Dual Function

6

-

AK34

AB27

AC27

AF33

AG33

AC29

AD29

AE31

AF31

AF30

AF29

AH33

AJ33

PL98B

PL98C

PL98D

PL99A

PL99B

PL99C

PL99D

PL103A

PL103B

PL103C

PL103D

PL104A

PL104B

PL104C

PL104D

PL107A

PL107B

PL107C

PL107D

PL109A

PL109B

PL109C

PL109D

PL112A

PL112B

PL112C

PL112D

PL115A

PL115B

PL115C

PL115D

PL116A

PL116B

PL116C

PL116D

PL117A

PL117B

PL117C

PL117D

XRES

AC28

AD28

AH32

AJ32

AD27

AE27

AG34

AH34

AC26

AB26

AK33

AL33

AG30

AH30

AL34

AM34

AJ30

VREF2_6

LLC_DLLT_IN_E/LLC_DLLT_FB_F

LLC_DLLC_IN_E/LLC_DLLC_FB_F

AK30

AJ31

AH31

AD26

AD25

AL32

AL31

AG29

AG28

AF28

AF27

AM33

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

LLC_PLLT_IN_B/LLC_PLLT_FB_A

LLC_PLLC_IN_B/LLC_PLLC_FB_A

TEMP

6

5

PB3A

LLC_PLLT_IN_A/LLC_PLLT_FB_B

4-86

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AN33

AH29

AJ29

Ball Function

PB3B

VCCIO Bank

Dual Function

5

LLC_PLLC_IN_A/LLC_PLLC_FB_B

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

LLC_DLLT_IN_D/LLC_DLLT_FB_C

LLC_DLLC_IN_D/LLC_DLLC_FB_C

PB3C

PB3D

AM32

AM31

AG27

AG26

AL29

AL28

AH27

AH26

AN32

AP32

AF25

AE25

AN31

AN30

AK29

AK28

AP31

AP30

AD24

AE24

AM29

AM28

AJ27

PB4A

PB4B

PB4C

PB4D

PB5A

PB5B

PB5C

PB5D

VREF1_5

PB7A

PB7B

PB7C

PB7D

PB11A

PB11B

PB11C

PB11D

PB12A

PB12B

PB12C

PB12D

PB15A

PB15B

PB15C

PB15D

PB16A

PB16B

PB16C

PB16D

PB19A

PB19B

PB19C

PB19D

PB20A

PB20B

PB20C

PB20D

PB23A

PB23B

PB23C

PB23D

AJ26

AP29

AP28

AK27

AK26

AN29

AN28

AG25

AG24

AL26

AL25

AG23

AG22

AN27

AN26

AF24

AF23

4-87

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AP27

AP26

AK25

AK24

AN25

AN24

AE22

AE21

AM26

AM25

AF22

AF21

AN23

AN22

AP23

AP22

AG21

AG20

AP25

AP24

AD21

AD20

AL23

AL22

AH24

AH23

AM23

AM22

AJ24

Ball Function

PB26A

PB26B

PB26C

PB26D

PB29A

PB29B

PB29C

PB29D

PB31A

PB31B

PB31C

PB31D

PB47A

PB47B

PB57A

PB57B

PB57C

PB57D

PB50A

PB50B

PB50C

PB50D

PB51A

PB51B

PB51C

PB51D

PB53A

PB53B

PB53C

PB53D

PB54A

PB54B

PB54C

PB54D

PB55A

PB55B

PB55C

PB55D

PB58A

PB58B

PB58C

PB58D

PB61A

VCCIO Bank

Dual Function

5

PCLKT5_3

PCLKC5_3

PCLKT5_4

PCLKC5_4

PCLKT5_5

PCLKC5_5

PCLKT5_0

PCLKC5_0

AJ23

VREF2_5

PCLKT5_1

PCLKC5_1

PCLKT5_6

PCLKC5_6

PCLKT5_2

PCLKC5_2

PCLKT5_7

PCLKC5_7

AN21

AN20

AE19

AD19

AK21

AK20

AK23

AK22

AL20

AL19

AG19

AF19

AP21

4-88

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AP20

AH21

AH20

AM20

AM19

AJ21

Ball Function

PB61B

PB61C

PB61D

PB63A

PB63B

PB63C

PB63D

PB66A

PB66B

PB66C

PB66D

PB69A

PB69B

PB69C

PB69D

PB71A

PB71B

PB71C

PB71D

PB73A

PB73B

PB73C

PB73D

PB75A

PB75B

PB75C

PB75D

PB78A

PB78B

PB78C

PB78D

PB81A

PB81B

PB81C

PB81D

PB83A

PB83B

PB83C

PB83D

PB86A

PB86B

PB86C

PB86D

VCCIO Bank

Dual Function

5

4

AJ20

AK19

AK18

AE18

AD18

AN19

AN18

AG18

AF18

AP19

AP18

AJ18

AH18

AP17

AP16

AJ17

AH17

AN17

AN16

AE17

AD17

AK17

AK16

AG17

AF17

AM16

AM15

AJ15

AJ14

AL16

AL15

AG16

AF16

AP15

AP14

AH15

AH14

4-89

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AN15

AN14

AE16

AD16

AK15

AK14

AG15

AG14

AM13

AM12

AJ12

AJ11

AL13

AL12

AH12

AH11

AN13

AN12

AD14

AD15

AP13

AP12

AK13

AK12

AP11

AP10

AN11

AN10

AF14

AF13

AM10

AM9

Ball Function

PB89A

VCCIO Bank

Dual Function

PCLKT4_2

PCLKC4_2

PCLKT4_7

PCLKC4_7

PCLKT4_1

PCLKC4_1

PCLKT4_6

PCLKC4_6

PCLKT4_0

PCLKC4_0

VREF2_4

4

PB89B

PB89C

PB89D

PB90A

PB90B

PB90C

PB90D

PB91A

PB91B

PB91C

PB91D

PB93A

PCLKT4_5

PCLKC4_5

PB93B

PB93C

PB93D

PB94A

PCLKT4_3

PCLKC4_3

PCLKT4_4

PCLKC4_4

PB94B

PB94C

PB94D

PB87A

PB87B

PB87C

PB87D

PB97A

PB97B

PB113A

PB113B

PB113C

PB113D

PB115A

PB115B

PB115C

PB115D

PB118A

PB118B

PB118C

PB118D

PB121A

PB121B

PB121C

PB121D

PB123A

AE14

AE13

AP9

AP8

AK11

AK10

AL10

AL9

AF12

AF11

AN9

4-90

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AN8

AG11

AG10

AP7

Ball Function

PB123B

PB123C

PB123D

PB125A

PB125B

PB125C

PB125D

PB127A

PB127B

PB127C

PB127D

PB129A

PB129B

PB129C

PB129D

PB131A

PB131B

PB131C

PB131D

PB133A

PB133B

PB133C

PB133D

PB135A

PB135B

PB135C

PB135D

PB138A

PB138B

PB138C

PB138D

PB139A

PB139B

PB139C

PB139D

PB141A

PB141B

PB141C

PB141D

PROBE_VCC

PROBE_GND

PR117D

PR117C

VCCIO Bank

Dual Function

4

-

AP6

AG13

AG12

AN7

AN6

AK9

AK8

AP5

AP4

AD11

AE11

AM7

AM6

AJ9

AJ8

AP3

AN3

AF10

AE10

AL7

AL6

AK7

AK6

AN5

AN4

AH9

AH8

AM3

AM4

AG9

AG8

AN2

AM2

AJ6

VREF1_4

LRC_DLLT_IN_C/LRC_DLLT_FB_D

LRC_DLLC_IN_C/LRC_DLLC_FB_D

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLT_IN_D/LRC_DLLT_FB_C

LRC_DLLC_IN_D/LRC_DLLC_FB_C

AH6

AF7

AF8

-

AG7

AG6

3

LRC_PLLC_IN_B/LRC_PLLC_FB_A

LRC_PLLT_IN_B/LRC_PLLT_FB_A

4-91

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AL4

Ball Function

PR117B

PR117A

PR116D

PR116C

PR116B

PR116A

PR115D

PR115C

PR115B

PR115A

PR112D

PR112C

PR112B

PR112A

PR109D

PR109C

PR109B

PR109A

PR107D

PR107C

PR107B

PR107A

PR104D

PR104C

PR104B

PR104A

PR103D

PR103C

PR103B

PR103A

PR99D

VCCIO Bank

Dual Function

3

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

AL3

AD10

AD9

AH4

AJ4

AK5

AJ5

LRC_DLLC_IN_E/LRC_DLLC_FB_F

LRC_DLLT_IN_E/LRC_DLLT_FB_F

AM1

AL1

AH5

AG5

AL2

AK2

AB9

AC9

AH1

AG1

AE8

AD8

AJ3

VREF2_3

AH3

AD7

AC7

AJ2

AH2

AF6

AF5

AF4

AE4

AD6

AC6

AG2

AF2

AC8

AB8

AK1

AJ1

PR99C

PR99B

PR99A

PR98D

PR98C

PR98B

PR98A

AB10

AA10

AF3

AE3

AE5

PR96D

PR96C

PR96B

PR96A

PR94D

4-92

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AD5

AE2

AD2

AC5

AB5

AF1

AE1

AA11

Y11

AC4

AB4

AA8

AA9

AC3

AB3

AA7

Y7

Ball Function

PR94C

PR94B

PR94A

PR92D

PR92C

PR92B

PR92A

PR91D

PR91C

PR91B

PR91A

PR90D

PR90C

PR90B

PR90A

PR79D

PR79C

PR79B

PR79A

PR77D

PR77C

PR77B

PR77A

PR74D

PR74C

PR74B

PR74A

PR71D

PR71C

PR71B

PR71A

PR70D

PR70C

PR70B

PR70A

PR69D

PR69C

PR69B

PR69A

PR66D

PR66C

PR66B

PR66A

VCCIO Bank

Dual Function

3

DIFFR_3

AA2

Y2

AA6

Y6

Y4

W4

W11

V11

W2

V2

W9

V9

V1

U1

W10

V10

U2

T2

Y8

W8

VREF1_3

W5

V5

V7

PCLKC3_2

PCLKT3_2

U7

T1

R1

4-93

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

V8

Ball Function

PR65D

PR65C

PR65B

PR65A

PR64D

PR64C

PR64B

PR64A

PR62D

PR62C

PR62B

PR62A

PR61D

PR61C

PR61B

PR61A

PR60D

PR60C

PR60B

PR60A

PR57D

PR57C

PR57B

PR57A

PR56D

PR56C

PR56B

PR56A

PR51D

PR51C

PR51B

PR51A

PR49D

PR49C

PR49B

PR49A

PR47D

PR47C

PR47B

PR47A

PR45D

PR45C

PR45B

VCCIO Bank

Dual Function

PCLKC3_3

3

2

U8

PCLKT3_3

U5

T5

V6

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_3

PCLKT2_3

PCLKC2_1

PCLKT2_1

U6

T4

T3

U9

T9

R2

P2

T11

U11

R4

R3

T8

R8

P1

N1

R6

P6

M1

L1

T10

U10

N2

M2

R11

P11

N4

M4

N5

M5

L2

K2

P8

N8

J2

H2

M6

L6

K3

4-94

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

J3

Ball Function

PR45A

VCCIO Bank

Dual Function

2

-

M8

L8

PR43D

DIFFR_2

VREF1_2

PR43C

K4

PR43B

J4

PR43A

M7

L7

PR26D

PR26C

J5

PR26B

H5

N9

P9

PR26A

PR19D

PR19C

G3

F3

PR19B

PR19A

J6

PR18D

VREF2_2

H6

E2

PR18C

PR18B

URC_DLLC_IN_D/URC_DLLC_FB_C

URC_DLLT_IN_D/URC_DLLT_FB_C

URC_PLLC_IN_B/URC_PLLC_FB_A

URC_PLLT_IN_B/URC_PLLT_FB_A

URC_DLLC_IN_C/URC_DLLC_FB_D

URC_DLLT_IN_C/URC_DLLT_FB_D

D2

P10

N10

G4

F4

PR18A

PR17D

PR17C

PR17B

PR17A

J7

PR15D

H7

G5

F5

PR15C

PR15B

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

PR15A

C2

M9

L9

VCCJ

TDO

-

TDO

TMS

-

D1

C1

J8

TCK

-

TDI

-

PROGRAMN

MPIIRQN

CCLK

1

-

K8

CFGIRQN/MPI_IRQ_N

B2

H9

H10

H8

G8

C3

D3

A3

RESP_URC

VCC12

-

A_REFCLKN_R

A_REFCLKP_R

VCC12

-

A_VDDIB0_R

A_HDINP0_R

A_HDINN0_R

VCC12

-

PCS 3E0 CH 0 IN P

PCS 3E0 CH 0 IN N

B3

-

E5

-

A4

A_HDOUTP0_R

-

PCS 3E0 CH 0 OUT P

4-95

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

F6

Ball Function

A_VDDOB0_R

A_HDOUTN0_R

A_VDDOB1_R

A_HDOUTN1_R

VCC12

VCCIO Bank

Dual Function

-

B4

PCS 3E0 CH 0 OUT N

PCS 3E0 CH 1 OUT N

F7

B5

E6

A5

A_HDOUTP1_R

A_HDINN1_R

A_HDINP1_R

VCC12

PCS 3E0 CH 1 OUT P

PCS 3E0 CH 1 IN N

PCS 3E0 CH 1 IN P

B6

A6

C6

D4

A_VDDIB1_R

VCC12

C7

D5

A_VDDIB2_R

A_HDINP2_R

A_HDINN2_R

VCC12

A7

PCS 3E0 CH 2 IN P

PCS 3E0 CH 2 IN N

B7

E7

A8

A_HDOUTP2_R

A_VDDOB2_R

A_HDOUTN2_R

A_VDDOB3_R

A_HDOUTN3_R

VCC12

PCS 3E0 CH 2 OUT P

PCS 3E0 CH 2 OUT N

PCS 3E0 CH 3 OUT N

F8

B8

F9

B9

E8

A9

A_HDOUTP3_R

A_HDINN3_R

A_HDINP3_R

VCC12

PCS 3E0 CH 3 OUT P

PCS 3E0 CH 3 IN N

PCS 3E0 CH 3 IN P

B10

A10

C10

D6

A_VDDIB3_R

VCC12

G10

D7

B_VDDIB0_R

B_HDINP0_R

B_HDINN0_R

VCC12

E10

F10

K10

A11

D10

B11

D11

B12

L10

A12

F11

E11

G11

D8

PCS 3E1 CH 0 IN P

PCS 3E1 CH 0 IN N

B_HDOUTP0_R

B_VDDOB0_R

B_HDOUTN0_R

B_VDDOB1_R

B_HDOUTN1_R

VCC12

PCS 3E1 CH 0 OUT P

PCS 3E1 CH 0 OUT N

PCS 3E1 CH 1 OUT N

B_HDOUTP1_R

B_HDINN1_R

B_HDINP1_R

VCC12

PCS 3E1 CH 1 OUT P

PCS 3E1 CH 1 IN N

PCS 3E1 CH 1 IN P

B_VDDIB1_R

VCC12

G12

4-96

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

D9

Ball Function

B_VDDIB2_R

B_HDINP2_R

B_HDINN2_R

VCC12

VCCIO Bank

Dual Function

-

E12

F12

K11

A13

D12

B13

D13

B14

L11

PCS 3E1 CH 2 IN P

PCS 3E1 CH 2 IN N

-

B_HDOUTP2_R

B_VDDOB2_R

B_HDOUTN2_R

B_VDDOB3_R

B_HDOUTN3_R

VCC12

-

PCS 3E1 CH 2 OUT P

PCS 3E1 CH 2 OUT N

PCS 3E1 CH 3 OUT N

-

A14

F13

E13

G13

E9

B_HDOUTP3_R

B_HDINN3_R

B_HDINP3_R

VCC12

-

PCS 3E1 CH 3 OUT P

PCS 3E1 CH 3 IN N

PCS 3E1 CH 3 IN P

-

B_VDDIB3_R

VCC12

-

L13

-

J11

B_REFCLKN_R

B_REFCLKP_R

PT93D

-

H11

M15

M16

F14

G14

L15

-

1

HDC/SI

LDCN/SCS

PT93C

PT93B

D8/MPI_DATA8

PT93A

CS1/MPI_CS1

PT90D

D9/MPI_DATA9

L14

PT90C

D10/MPI_DATA10

CS0N/MPI_CS0N

RDN/MPI_STRB_N

WRN/MPI_WR_N

D7/MPI_DATA7

D14

E14

L16

PT90B

PT90A

PT89D

K16

G15

F15

K14

K13

B15

A15

J14

PT89C

PT89B

D6/MPI_DATA6

PT89A

D5/MPI_DATA5

PT87D

D4/MPI_DATA4

PT87C

D3/MPI_DATA3

PT87B

D2/MPI_DATA2

PT87A

D1/MPI_DATA1

PT86D

D16/PCLKC1_3/MPI_DATA16

D17/PCLKT1_3/MPI_DATA17

D0/MPI_DATA0

H14

A16

B16

J13

PT86C

PT86B

PT86A

QOUT/CEON

PT83D

VREF2_1

H13

D15

E15

J16

PT83C

D18/MPI_DATA18

DOUT

PT83B

PT83A

MCA_DONE_IN

D19/PCLKC1_2/MPI_DATA19

PT81D

4-97

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

J17

Ball Function

PT81C

PT81B

PT81A

PT78D

PT78C

PT78B

PT78A

PT75D

PT75C

PT75B

PT75A

PT73D

PT73C

PT73B

PT73A

PT71D

PT71C

PT71B

PT71A

PT69D

PT69C

PT69B

PT69A

PT66D

PT66C

PT66B

PT66A

PT63D

PT63C

PT63B

PT63A

PT61D

PT61C

PT61B

PT61A

PT58D

PT58C

PT58B

PT58A

PT57D

PT57C

PT57B

PT57A

VCCIO Bank

Dual Function

D20/PCLKT1_2/MPI_DATA20

MCA_CLK_P1_OUT

MCA_CLK_P1_IN

1

D16

E16

H15

H16

C15

C16

L17

D21/PCLKC1_1/MPI_DATA21

D22/PCLKT1_1/MPI_DATA22

MCA_CLK_P2_OUT

MCA_CLK_P2_IN

MCA_DONE_OUT

BUSYN/RCLK/SCK

DP0/MPI_PAR0

K17

E17

F17

G17

H17

A17

B17

G18

H18

E18

F18

J18

MPI_TA

D23/MPI_DATA23

DP2/MPI_PAR2

PCLKC1_0

PCLKT1_0/MPI_CLK

DP3/PCLKC1_4/MPI_PAR3

D24/PCLKT1_4/MPI_DATA24

MPI_RETRY

A0/MPI_ADDR14

A1/MPI_ADDR15

J19

A2/MPI_ADDR16

C20

C19

K18

L18

A3/MPI_ADDR17

A4/MPI_ADDR18

D25/PCLKC1_5/MPI_DATA25

D26/PCLKT1_5/MPI_DATA26

A5/MPI_ADDR19

D19

E19

H19

H20

A18

B18

H21

J21

A6/MPI_ADDR20

D27/MPI_DATA27

VREF1_1

A7/MPI_ADDR21

A8/MPI_ADDR22

D28/PCLKC1_6/MPI_DATA28

D29/PCLKT1_6/MPI_DATA29

A9/MPI_ADDR23

A19

B19

H22

J22

A10/MPI_ADDR24

D30/PCLKC1_7/MPI_DATA30

D31/PCLKT1_7/MPI_DATA31

A11/MPI_ADDR25

A12/MPI_ADDR26

D11/MPI_DATA11

F20

G20

K21

K22

A20

B20

D12/MPI_DATA12

A13/MPI_ADDR27

A14/MPI_ADDR28

4-98

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

L21

Ball Function

PT55D

VCCIO Bank

Dual Function

A16/MPI_ADDR30

D13/MPI_DATA13

A15/MPI_ADDR29

A17/MPI_ADDR31

A19/MPI_TSIZ1

A20/MPI_BDIP

1

-

L20

PT55C

D20

E20

L19

PT55B

PT55A

PT54D

K19

D21

E21

M20

M19

F21

G21

H24

J24

PT54C

PT54B

A18/MPI_TSIZ0

MPI_TEA

PT54A

PT51D

D14/MPI_DATA14

DP1/MPI_PAR1

A21/MPI_BURST

D15/MPI_DATA15

PT51C

PT51B

PT51A

B_REFCLKP_L

B_REFCLKN_L

VCC12

-

L22

-

E26

G22

E22

F22

A21

L24

B_VDDIB3_L

VCC12

-

B_HDINP3_L

B_HDINN3_L

B_HDOUTP3_L

VCC12

-

PCS 361 CH 3 IN P

PCS 361 CH 3 IN N

PCS 361 CH 3 OUT P

-

B21

D22

B22

D23

A22

K24

F23

E23

D26

G23

D27

G24

E24

F24

A23

L25

B_HDOUTN3_L

B_VDDOB3_L

B_HDOUTN2_L

B_VDDOB2_L

B_HDOUTP2_L

VCC12

-

PCS 361 CH 3 OUT N

PCS 361 CH 2 OUT N

PCS 361 CH 2 OUT P

-

B_HDINN2_L

B_HDINP2_L

B_VDDIB2_L

VCC12

-

PCS 361 CH 2 IN N

PCS 361 CH 2 IN P

-

B_VDDIB1_L

VCC12

-

B_HDINP1_L

B_HDINN1_L

B_HDOUTP1_L

VCC12

-

PCS 361 CH 1 IN P

PCS 361 CH 1 IN N

PCS 361 CH 1 OUT P

-

B23

D24

B24

D25

A24

K25

B_HDOUTN1_L

B_VDDOB1_L

B_HDOUTN0_L

B_VDDOB0_L

B_HDOUTP0_L

VCC12

-

PCS 361 CH 1 OUT N

PCS 361 CH 0 OUT N

PCS 361 CH 0 OUT P

-

4-99

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

F25

E25

D28

G25

D29

C25

A25

B25

A26

E27

B26

F26

B27

F27

A27

E28

B28

A28

D30

C28

D31

C29

A29

B29

A30

E29

B30

F28

B31

F29

A31

E30

B32

A32

D32

C32

E34

F34

F33

G33

K30

L30

Ball Function

B_HDINN0_L

B_HDINP0_L

B_VDDIB0_L

VCC12

VCCIO Bank

Dual Function

PCS 361 CH 0 IN N

PCS 361 CH 0 IN P

-

A_VDDIB3_L

VCC12

-

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

VCC12

-

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

-

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

VCC12

-

PCS 360 CH 3 OUT N

PCS 360 CH 2 OUT N

PCS 360 CH 2 OUT P

-

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

VCC12

-

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

-

A_VDDIB1_L

VCC12

-

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

VCC12

-

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

-

A_HDOUTN1_L

A_VDDOB1_L

A_HDOUTN0_L

A_VDDOB0_L

A_HDOUTP0_L

VCC12

-

PCS 360 CH 1 OUT N

PCS 360 CH 0 OUT N

PCS 360 CH 0 OUT P

-

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

VCC12

-

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

-

PL30A

7

PL30B

PL34A

PL34B

PL38A

PL38B

G34

PL40A

4-100

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

H34

M32

N32

P28

R28

J34

Ball Function

PL40B

PL53A

PL53B

PL53C

PL53D

PL55A

PL55B

PL55C

PL55D

PL73A

PL73B

PL75A

PL75B

PL78A

PL78B

PL81A

PL81B

PL82A

PL82B

PL83A

PL83B

PR83B

PR83A

PR82B

PR82A

PR81B

PR81A

PR78B

PR78A

PR75B

PR75A

PR73B

PR73A

PR55D

PR55C

PR55B

PR55A

PR53D

PR53C

PR53B

PR53A

PR40B

PR40A

VCCIO Bank

Dual Function

7

6

3

2

K34

P30

R30

W34

Y34

W32

Y32

AA34

AB34

AC34

AD34

Y30

AA30

AB33

AC33

AC2

AB2

AA5

Y5

AD1

AC1

AB1

AA1

Y3

W3

Y1

W1

R5

P5

K1

J1

R7

P7

N3

M3

H1

G1

4-101

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

L5

Ball Function

PR38B

PR38A

PR34B

PR34A

PR30B

PR30A

GND

VCCIO Bank

Dual Function

2

-

K5

G2

F2

F1

E1

A2

A33

GND

AA15

AA20

AA32

AA4

GND

AB28

AB6

GND

AC11

AC18

AC25

AD23

AD3

GND

AD31

AE12

AE15

AE29

AE7

GND

AE9

GND

AF20

AF26

AG32

AG4

GND

AH13

AH19

AH25

AH7

GND

AJ10

AJ16

AJ22

AJ28

AK3

GND

AK31

AL11

AL17

AL21

AL27

GND

4-102

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AL5

AM14

AM18

AM24

AM30

AM8

AN1

AN34

AP2

AP33

B1

Ball Function

GND

VCCIO Bank

Dual Function

-

B34

C11

C12

C13

C14

C17

C21

C22

C23

C24

C26

C27

C30

C31

C4

C5

C8

C9

D18

E32

E4

F19

G16

G29

G7

H3

H31

J10

J15

J26

K20

K23

4-103

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

K26

K28

K6

Ball Function

GND

VCCIO Bank

Dual Function

-

K9

L12

L32

L4

M10

M17

M24

N29

N7

P15

P20

P3

P31

R10

R14

R16

R19

R21

R26

T15

T17

T18

T20

T28

T6

U16

U19

U23

U32

U4

V12

V16

V19

V3

V31

W15

W17

W18

W20

W29

4-104

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

W7

Ball Function

GND

VCC

VCCIO Bank

Dual Function

-

AA14

AA16

AA17

AA18

AA19

AA21

AB13

AB22

N13

N22

P14

P16

P17

P18

P19

P21

R15

R17

R18

R20

T14

T16

T19

T21

U14

U15

U17

U18

U20

U21

V14

V15

V17

V18

V20

V21

W14

W16

W19

W21

Y15

Y17

4-105

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

Y18

Ball Function

VCC

VCCIO Bank

Dual Function

-

Y20

VCC

AB15

AB20

N15

VCC12

N20

VCC12

R13

VCC12

R22

VCC12

Y13

VCC12

Y22

VCC12

AA12

AA23

AB12

AB16

AB17

AB18

AB19

AB23

AC12

AC13

Y19

VCCAUX

GND

AC14

AC17

AC21

AC22

AC23

M13

VCCAUX

M14

M18

M21

M22

N12

N16

N17

N18

N19

N23

P12

P23

T13

T22

U12

U13

4-106

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

U22

V13

V22

V23

W13

W22

Y21

Y25

C18

D17

F16

G19

J20

Ball Function

VCCAUX

GND

VCCIO Bank

Dual Function

-

GND

VCCIO1

GND

K12

K15

L23

Y9

J9

VCCIO1

VCCIO2

VCCIO3

VCCIO4

E3

G6

H4

K7

L3

M11

N6

P4

R9

AA3

AB7

AC10

AD4

AE6

AG3

AK4

T7

U3

V4

W6

Y10

AD12

AF15

AF9

AH10

4-107

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

AH16

AJ13

AJ7

Ball Function

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCIO1

VTT_2

VCCIO Bank

Dual Function

-

2

AL14

AL8

AM11

AM17

AM5

AE20

AE23

AE26

AH22

AH28

AJ19

AJ25

AL18

AL24

AL30

AM21

AM27

AA31

AB29

AC24

AD32

AE28

AG31

AK32

T29

U31

V32

W28

Y26

E31

G28

H32

K29

L31

M25

N28

P32

R25

J25

N11

4-108

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M115 Logic Signal Connections: 1152 fcBGA^{1, 2}

LFSC/M115

Ball Number

R12

Ball Function

VTT_2

VTT_3

VTT_4

VTT_5

VTT_6

VTT_7

VDDAX25_R

VDDAX25_L

GND

VCCIO Bank

Dual Function

2

3

4

5

6

7

-

T12

AB11

W12

Y12

AC15

AC16

AD13

AC19

AC20

AD22

AB24

W23

Y23

N24

R23

T23

M12

M23

Y16

-

Y14

GND

-

N21

VCC12

NC

-

P22

-

AA22

AB21

AB14

AA13

P13

-

N14

-

G26

-

G9

NC

-

J12

NC

-

H12

NC

-

H23

NC

-

J23

NC

-

1. Differential pair grouping within a PCI is A (True) and B (complement) and C (True) and D (Complement).

2. The LatticeSC/M115 in an 1152-pin package supports a 32-bit MPI interface.

4-109

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

G34

H34

N30

H33

P25

P26

P31

P23

P30

P22

P24

R22

J37

A_REFCLKP_L

A_REFCLKN_L

VCC12

RESP_ULC

RESETN

TSALLN

DONE

INITN

-

A_REFCLKP_L

A_REFCLKN_L

VCC12

RESP_ULC

RESETN

TSALLN

DONE

INITN

-

1

7

1

7

M0

M1

M2

M3

PL16A

PL16B

PL16C

PL16D

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL18C

PL18D

PL20A

PL20B

PL20C

PL20D

PL21A

PL21B

PL21C

PL21D

PL22A

PL22B

PL22C

PL22D

PL24A

PL24B

PL24C

PL24D

PL25A

PL25B

PL25C

PL25D

PL26A

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

PL15A

PL15B

PL15C

PL15D

PL17A

PL17B

PL17C

PL17D

PL18A

PL18B

PL18C

PL18D

PL19A

PL19B

PL19C

PL19D

PL26A

PL26B

PL26C

PL26D

PL30A

PL30B

PL30C

PL30D

PL34A

PL34B

PL34C

PL34D

PL38A

PL38B

PL38C

PL38D

PL40A

ULC_PLLT_IN_A/ULC_PLLT_FB_B

ULC_PLLC_IN_A/ULC_PLLC_FB_B

J38

P32

R32

G40

H40

N33

P33

G41

H41

T29

U29

G42

H42

M34

M35

K37

L37

N34

P34

K38

L38

T33

R33

J41

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

ULC_PLLT_IN_B/ULC_PLLT_FB_A

ULC_PLLC_IN_B/ULC_PLLC_FB_A

ULC_DLLT_IN_D/ULC_DLLT_FB_C

ULC_DLLC_IN_D/ULC_DLLC_FB_C

ULC_DLLT_IN_C/ULC_DLLT_FB_D

ULC_DLLC_IN_C/ULC_DLLC_FB_D

ULC_PLLT_IN_B/ULC_PLLT_FB_A

ULC_PLLC_IN_B/ULC_PLLC_FB_A

ULC_DLLT_IN_D/ULC_DLLT_FB_C

ULC_DLLC_IN_D/ULC_DLLC_FB_C

VREF2_7

K41

U31

V31

K42

J42

J36

K36

N38

4-110

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

P38

N35

N36

N39

P39

R34

T34

L41

PL26B

PL26C

PL26D

PL29A

PL29B

PL29C

PL29D

PL30A

PL30B

PL30C

PL30D

PL31A

PL31B

PL31C

PL31D

PL33A

PL33B

PL33C

PL33D

PL34A

PL34B

PL34C

PL34D

PL35A

PL35B

PL35C

PL35D

PL37A

PL37B

PL37C

PL37D

PL38A

PL38B

PL38C

PL38D

PL39A

PL39B

PL39C

PL39D

PL41A

PL41B

PL41C

PL41D

PL42A

PL42B

7

PL40B

PL40C

PL40D

PL43A

PL43B

PL43C

PL43D

PL44A

PL44B

PL44C

PL44D

PL45A

PL45B

PL45C

PL45D

PL47A

PL47B

PL47C

PL47D

PL48A

PL48B

PL48C

PL48D

PL49A

PL49B

PL49C

PL49D

PL51A

PL51B

PL51C

PL51D

PL52A

PL52B

PL52C

PL52D

PL53A

PL53B

PL53C

PL53D

PL55A

PL55B

PL55C

PL55D

PL56A

PL56B

7

VREF1_7

DIFFR_7

VREF1_7

DIFFR_7

M41

W29

Y29

L42

M42

U32

V32

R37

T37

M36

M37

P40

N40

R35

T35

N41

P41

V33

U33

R38

T38

R36

T36

N42

P42

Y31

AA31

U37

V37

U34

V34

U39

T39

V35

W35

R41

T41

4-111

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

W33

Y33

PL42C

PL42D

PL43A

PL43B

PL43C

PL43D

PL46A

PL46B

PL46C

PL46D

PL47A

PL47B

PL47C

PL47D

PL48A

PL48B

PL48C

PL48D

PL50A

PL50B

PL50C

PL50D

PL51A

PL51B

PL51C

PL51D

PL52A

PL52B

PL52C

PL52D

PL55A

PL55B

PL55C

PL55D

PL56A

PL56B

PL56C

PL56D

PL57A

PL57B

PL57C

PL57D

PL59A

PL59B

PL59C

7

6

PL56C

PL56D

PL57A

PL57B

PL57C

PL57D

PL60A

PL60B

PL60C

PL60D

PL61A

PL61B

PL61C

PL61D

PL62A

PL62B

PL62C

PL62D

PL64A

PL64B

PL64C

PL64D

PL65A

PL65B

PL65C

PL65D

PL66A

PL66B

PL66C

PL66D

PL69A

PL69B

PL69C

PL69D

PL70A

PL70B

PL70C

PL70D

PL71A

PL71B

PL71C

PL71D

PL73A

PL73B

PL73C

7

6

W37

Y37

Y32

AA32

U38

V38

W34

Y34

T40

PCLKT7_1

PCLKC7_1

PCLKT7_3

PCLKC7_3

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

PCLKT7_1

PCLKC7_1

PCLKT7_3

PCLKC7_3

PCLKT7_0

PCLKC7_0

PCLKT7_2

PCLKC7_2

PCLKT6_0

PCLKC6_0

PCLKT6_1

PCLKC6_1

U40

AA33

AB33

R42

T42

AA34

AB34

U41

V41

V36

W36

U42

V42

AB31

AC31

W38

Y38

PCLKT6_3

PCLKC6_3

PCLKT6_3

PCLKC6_3

AA35

AB35

W39

Y39

PCLKT6_2

PCLKC6_2

PCLKT6_2

PCLKC6_2

AB32

AC32

W40

Y40

VREF1_6

AA36

AB36

W41

Y41

AA37

AB37

W42

Y42

AC33

4-112

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AD33

AA38

AB38

AC29

AD29

AA41

AB41

AC34

AD34

AA42

AB42

AC37

AD37

AC38

AD38

AD36

AE36

AC39

AD39

AD35

AE35

AC40

AD40

AE37

AF37

AC41

AD41

AE34

AF34

AC42

AD42

AE33

AF33

AE38

AF38

AE32

AF32

AE41

AF41

AE31

AF31

AE42

AF42

AG37

AH37

PL59D

PL60A

PL60B

PL60C

PL60D

PL61A

PL61B

PL61C

PL61D

PL63A

PL63B

PL63C

PL63D

PL64A

PL64B

PL64C

PL64D

PL65A

PL65B

PL65C

PL65D

PL67A

PL67B

PL67C

PL67D

PL68A

PL68B

PL68C

PL68D

PL69A

PL69B

PL69C

PL69D

PL72A

PL72B

PL72C

PL72D

PL73A

PL73B

PL73C

PL73D

PL74A

PL74B

PL74C

PL74D

6

PL73D

PL74A

PL74B

PL74C

PL74D

PL75A

PL75B

PL75C

PL75D

PL77A

PL77B

PL77C

PL77D

PL78A

PL78B

PL78C

PL78D

PL79A

PL79B

PL79C

PL79D

PL81A

PL81B

PL81C

PL81D

PL82A

PL82B

PL82C

PL82D

PL83A

PL83B

PL83C

PL83D

PL86A

PL86B

PL86C

PL86D

PL87A

PL87B

PL87C

PL87D

PL88A

PL88B

PL88C

PL88D

6

4-113

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AF40

AG40

AG36

AH36

AF39

AG39

AF29

AG29

AH42

AG42

AG35

AH35

AG41

AH41

AG34

AH34

AJ42

AK42

AG33

AH33

AJ41

AK41

AJ37

AK37

AJ40

AK40

AJ34

AK34

AJ38

AK38

AH32

AJ32

AL42

AM42

AK36

AL36

AL38

AM38

AJ33

AK33

AN42

AP42

AH31

AJ31

AN41

PL76A

PL76B

PL76C

PL76D

PL77A

PL77B

PL77C

PL77D

PL78A

PL78B

PL78C

PL78D

PL80A

PL80B

PL80C

PL80D

PL81A

PL81B

PL81C

PL81D

PL82A

PL82B

PL82C

PL82D

PL84A

PL84B

PL84C

PL84D

PL85A

PL85B

PL85C

PL85D

PL86A

PL86B

PL86C

PL86D

PL89A

PL89B

PL89C

PL89D

PL90A

PL90B

PL90C

PL90D

PL91A

6

PL90A

PL90B

PL90C

PL90D

PL91A

PL91B

PL91C

PL91D

PL92A

PL92B

PL92C

PL92D

PL94A

PL94B

PL94C

PL94D

PL96A

PL96B

PL96C

PL96D

PL98A

PL98B

PL98C

PL98D

PL99A

PL99B

PL99C

PL99D

PL103A

PL103B

PL103C

PL103D

PL104A

PL104B

PL104C

PL104D

PL107A

PL107B

PL107C

PL107D

PL109A

PL109B

PL109C

PL109D

PL112A

6

DIFFR_6

VREF2_6

4-114

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AP41

AK35

AL35

AN38

AP38

AL37

AM37

AR41

AT41

AN37

AP37

AR39

AR40

AN36

AP36

AT40

AU41

AU42

AV42

AL33

AL34

AU38

AV38

AM34

AM33

AV41

AW41

AK30

AK29

AW42

AY42

AR37

AR38

AV40

AV39

AN35

AN34

AW40

AY40

AP34

AP35

AW39

AW38

AL32

AL31

PL91B

PL91C

PL91D

PL93A

PL93B

PL93C

PL93D

PL94A

PL94B

PL94C

PL94D

PL95A

PL95B

PL95C

PL95D

XRES

TEMP

PB3A

PB3B

PB3C

PB3D

PB4A

PB4B

PB4C

PB4D

PB5A

PB5B

PB5C

PB5D

PB7A

PB7B

PB7C

PB7D

PB8A

PB8B

PB8C

PB8D

PB9A

PB9B

PB9C

PB9D

PB11A

PB11B

PB11C

PB11D

6

-

PL112B

PL112C

PL112D

PL115A

PL115B

PL115C

PL115D

PL116A

PL116B

PL116C

PL116D

PL117A

PL117B

PL117C

PL117D

XRES

6

-

LLC_DLLT_IN_E/LLC_DLLT_FB_F

LLC_DLLC_IN_E/LLC_DLLC_FB_F

LLC_DLLT_IN_E/LLC_DLLT_FB_F

LLC_DLLC_IN_E/LLC_DLLC_FB_F

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

LLC_PLLT_IN_B/LLC_PLLT_FB_A

LLC_PLLC_IN_B/LLC_PLLC_FB_A

LLC_DLLT_IN_F/LLC_DLLT_FB_E

LLC_DLLC_IN_F/LLC_DLLC_FB_E

LLC_PLLT_IN_B/LLC_PLLT_FB_A

LLC_PLLC_IN_B/LLC_PLLC_FB_A

6

5

TEMP

PB3A

6

5

LLC_PLLT_IN_A/LLC_PLLT_FB_B

LLC_PLLC_IN_A/LLC_PLLC_FB_B

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

LLC_DLLT_IN_D/LLC_DLLT_FB_C

LLC_DLLC_IN_D/LLC_DLLC_FB_C

LLC_PLLT_IN_A/LLC_PLLT_FB_B

LLC_PLLC_IN_A/LLC_PLLC_FB_B

LLC_DLLT_IN_C/LLC_DLLT_FB_D

LLC_DLLC_IN_C/LLC_DLLC_FB_D

LLC_DLLT_IN_D/LLC_DLLT_FB_C

LLC_DLLC_IN_D/LLC_DLLC_FB_C

PB3B

PB3C

PB3D

PB4A

PB4B

PB4C

PB4D

PB5A

PB5B

PB5C

VREF1_5

PB5D

VREF1_5

PB7A

PB7B

PB7C

PB7D

PB9A

PB9B

PB9C

PB9D

PB11A

PB11B

PB11C

PB11D

PB12A

PB12B

PB12C

PB12D

4-115

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AY41

BA41

AT39

AT38

AV37

AV36

AM31

AM32

BA40

BB40

AM29

AL29

AY39

AY38

AN33

AN32

BA39

BA38

AT37

AT36

AW36

AW35

AM28

AL28

BB38

BB39

AR34

AR33

AV35

AV34

AT33

AT34

BA37

BA36

AP33

AP32

AY36

AY35

AN31

AN30

BB37

BB36

AP31

AP30

AV33

PB12A

PB12B

PB12C

PB12D

PB13A

PB13B

PB13C

PB13D

PB15A

PB15B

PB15C

PB15D

PB16A

PB16B

PB16C

PB16D

PB17A

PB17B

PB17C

PB17D

PB19A

PB19B

PB19C

PB19D

PB20A

PB20B

PB20C

PB20D

PB21A

PB21B

PB21C

PB21D

PB23A

PB23B

PB23C

PB23D

PB24A

PB24B

PB24C

PB24D

PB25A

PB25B

PB25C

PB25D

PB27A

5

PB13A

PB13B

PB13C

PB13D

PB15A

PB15B

PB15C

PB15D

PB16A

PB16B

PB16C

PB16D

PB17A

PB17B

PB17C

PB17D

PB19A

PB19B

PB19C

PB19D

PB20A

PB20B

PB20C

PB20D

PB21A

PB21B

PB21C

PB21D

PB23A

PB23B

PB23C

PB23D

PB25A

PB25B

PB25C

PB25D

PB26A

PB26B

PB26C

PB26D

PB27A

PB27B

PB27C

PB27D

PB29A

5

4-116

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AV32

AU36

AU37

BA35

BA34

AJ26

AJ27

AW33

AW32

AU35

AU34

BB35

BB34

AN29

AP29

AY33

AY32

AR31

AR30

AV31

AV30

AN28

AP28

BA33

BA32

AT30

AT31

BB33

BB32

AM26

AL26

AW30

AW29

AP27

AN27

BA31

BA30

AU32

AU33

BB31

BB30

AR28

AR27

AV29

AV28

PB27B

PB27C

PB27D

PB28A

PB28B

PB28C

PB28D

PB29A

PB29B

PB29C

PB29D

PB31A

PB31B

PB31C

PB31D

PB32A

PB32B

PB32C

PB32D

PB33A

PB33B

PB33C

PB33D

PB35A

PB35B

PB35C

PB35D

PB36A

PB36B

PB36C

PB36D

PB37A

PB37B

PB37C

PB37D

PB39A

PB39B

PB39C

PB39D

PB40A

PB40B

PB40C

PB40D

PB41A

PB41B

5

PB29B

PB29C

PB29D

PB30A

PB30B

PB30C

PB30D

PB31A

PB31B

PB31C

PB31D

PB33A

PB33B

PB33C

PB33D

PB34A

PB34B

PB34C

PB34D

PB35A

PB35B

PB35C

PB35D

PB37A

PB37B

PB37C

PB37D

PB38A

PB38B

PB38C

PB38D

PB39A

PB39B

PB39C

PB39D

PB41A

PB41B

PB41C

PB41D

PB42A

PB42B

PB42C

PB42D

PB43A

PB43B

5

4-117

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AP26

AN26

AY30

AY29

AU30

AU31

AV27

AV26

AT28

AT27

BA29

BA28

AL25

AM25

BB29

BB28

AN25

AP25

AY27

AY26

AT25

AT24

AW27

AW26

AU29

AU28

BB27

BB26

AR25

AR24

BA27

BA26

AP24

AN24

AV25

AV24

AU27

AU26

BA25

BA24

AU24

AU25

BB24

BB25

AM23

PB41C

PB41D

PB43A

PB43B

PB43C

PB43D

PB44A

PB44B

PB44C

PB44D

PB45A

PB45B

PB45C

PB45D

PB47A

PB47B

PB47C

PB47D

PB48A

PB48B

PB48C

PB48D

PB49A

PB49B

PB49C

PB49D

PB51A

PB51B

PB51C

PB51D

PB52A

PB52B

PB52C

PB52D

PB53A

PB53B

PB53C

PB53D

PB55A

PB55B

PB55C

PB55D

PB56A

PB56B

PB56C

5

PB43C

PB43D

PB45A

PB45B

PB45C

PB45D

PB46A

PB46B

PB46C

PB46D

PB47A

PB47B

PB47C

PB47D

PB49A

PB49B

PB49C

PB49D

PB50A

PB50B

PB50C

PB50D

PB51A

PB51B

PB51C

PB51D

PB53A

PB53B

PB53C

PB53D

PB54A

PB54B

PB54C

PB54D

PB55A

PB55B

PB55C

PB55D

PB57A

PB57B

PB57C

PB57D

PB58A

PB58B

PB58C

5

PCLKT5_3

PCLKC5_3

PCLKT5_4

PCLKC5_4

PCLKT5_5

PCLKC5_5

PCLKT5_3

PCLKC5_3

PCLKT5_4

PCLKC5_4

PCLKT5_5

PCLKC5_5

PCLKT5_0

PCLKC5_0

PCLKT5_0

PCLKC5_0

VREF2_5

PCLKT5_1

PCLKC5_1

PCLKT5_6

PCLKC5_6

PCLKT5_2

PCLKC5_2

PCLKT5_7

PCLKC5_7

VREF2_5

PCLKT5_1

PCLKC5_1

PCLKT5_6

PCLKC5_6

PCLKT5_2

PCLKC5_2

PCLKT5_7

PCLKC5_7

4-118

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AL23

AW24

AW23

AN23

AP23

AY23

AY24

AU23

AU22

AV23

AV22

AM22

AL22

BA23

BA22

AN22

AP22

BB23

BB22

AT22

AR22

BB21

BB20

AR21

AT21

BA21

BA20

AP21

AN21

AV21

AV20

AM21

AL21

AY20

AY19

AU21

AU20

AW20

AW19

AP20

AN20

BB19

BB18

AM20

AL20

PB56D

PB57A

PB57B

PB57C

PB57D

PB59A

PB59B

PB59C

PB59D

PB60A

PB60B

PB60C

PB60D

PB61A

PB61B

PB61C

PB61D

PB63A

PB63B

PB63C

PB63D

PB65A

PB65B

PB65C

PB65D

PB66A

PB66B

PB66C

PB66D

PB67A

PB67B

PB67C

PB67D

PB69A

PB69B

PB69C

PB69D

PB70A

PB70B

PB70C

PB70D

PB71A

PB71B

PB71C

PB71D

5

4

PB58D

PB61A

PB61B

PB61C

PB61D

PB63A

PB63B

PB63C

PB63D

PB66A

PB66B

PB66C

PB66D

PB69A

PB69B

PB69C

PB69D

PB71A

PB71B

PB71C

PB71D

PB73A

PB73B

PB73C

PB73D

PB75A

PB75B

PB75C

PB75D

PB78A

PB78B

PB78C

PB78D

PB81A

PB81B

PB81C

PB81D

PB83A

PB83B

PB83C

PB83D

PB86A

PB86B

PB86C

PB86D

5

4

4-119

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

BA19

BA18

AU19

AU18

AV19

AV18

AN19

AP19

BB17

BB16

AT19

AT18

BA17

BA16

AR19

AR18

AY17

AY16

AN18

AP18

AW17

AW16

AU17

AU16

AV17

AV16

AL18

AM18

BB15

BB14

AP17

AN17

BA15

BA14

AT16

AT15

AV15

AV14

AR16

AR15

AY14

AY13

AU15

AU14

BB13

PB73A

PB73B

PB73C

PB73D

PB74A

PB74B

PB74C

PB74D

PB75A

PB75B

PB75C

PB75D

PB77A

PB77B

PB77C

PB77D

PB79A

PB79B

PB79C

PB79D

PB80A

PB80B

PB80C

PB80D

PB81A

PB81B

PB81C

PB81D

PB83A

PB83B

PB83C

PB83D

PB84A

PB84B

PB84C

PB84D

PB85A

PB85B

PB85C

PB85D

PB87A

PB87B

PB87C

PB87D

PB88A

4

PB87A

PB87B

PB87C

PB87D

PB89A

PB89B

PB89C

PB89D

PB90A

PB90B

PB90C

PB90D

PB91A

PB91B

PB91C

PB91D

PB93A

PB93B

PB93C

PB93D

PB94A

PB94B

PB94C

PB94D

PB95A

PB95B

PB95C

PB95D

PB97A

PB97B

PB97C

PB97D

PB98A

PB98B

PB98C

PB98D

PB99A

PB99B

PB99C

PB99D

PB101A

PB101B

PB101C

PB101D

PB102A

4

PCLKT4_2

PCLKC4_2

PCLKT4_7

PCLKC4_7

PCLKT4_1

PCLKC4_1

PCLKT4_6

PCLKC4_6

PCLKT4_0

PCLKC4_0

VREF2_4

PCLKT4_2

PCLKC4_2

PCLKT4_7

PCLKC4_7

PCLKT4_1

PCLKC4_1

PCLKT4_6

PCLKC4_6

PCLKT4_0

PCLKC4_0

VREF2_4

PCLKT4_5

PCLKC4_5

PCLKT4_5

PCLKC4_5

PCLKT4_3

PCLKC4_3

PCLKT4_4

PCLKC4_4

PCLKT4_3

PCLKC4_3

PCLKT4_4

PCLKC4_4

4-120

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

BB12

AM17

AL17

AW14

AW13

AP16

AN16

BA13

BA12

AU13

AU12

BB11

BB10

AP15

AN15

AV13

AV12

AT13

AT12

BA11

BA10

AR13

AR12

AY11

AY10

AP14

AN14

BB9

PB88B

PB88C

PB88D

PB89A

PB89B

PB89C

PB89D

PB91A

PB91B

PB91C

PB91D

PB92A

PB92B

PB92C

PB92D

PB93A

PB93B

PB93C

PB93D

PB95A

PB95B

PB95C

PB95D

PB96A

PB96B

PB96C

PB96D

PB97A

PB97B

PB97C

PB97D

PB99A

PB99B

PB99C

PB99D

PB100A

PB100B

PB100C

PB100D

PB101A

PB101B

PB101C

PB101D

PB103A

PB103B

4

PB102B

PB102C

PB102D

PB103A

PB103B

PB103C

PB103D

PB105A

PB105B

PB105C

PB105D

PB106A

PB106B

PB106C

PB106D

PB107A

PB107B

PB107C

PB107D

PB109A

PB109B

PB109C

PB109D

PB110A

PB110B

PB110C

PB110D

PB111A

PB111B

PB111C

PB111D

PB113A

PB113B

PB113C

PB113D

PB114A

PB114B

PB114C

PB114D

PB115A

PB115B

PB115C

PB115D

PB117A

PB117B

4

BB8

AU11

AU10

AW11

AW10

AJ16

AJ17

BA9

BA8

AM15

AL15

AV11

AV10

AP13

AP12

BB7

BB6

4-121

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AU9

AU8

AY8

PB103C

PB103D

PB104A

PB104B

PB104C

PB104D

PB105A

PB105B

PB105C

PB105D

PB107A

PB107B

PB107C

PB107D

PB108A

PB108B

PB108C

PB108D

PB109A

PB109B

PB109C

PB109D

PB111A

PB111B

PB111C

PB111D

PB112A

PB112B

PB112C

PB112D

PB113A

PB113B

PB113C

PB113D

PB115A

PB115B

PB115C

PB115D

PB116A

PB116B

PB116C

PB116D

PB117A

PB117B

PB117C

4

PB117C

PB117D

PB118A

PB118B

PB118C

PB118D

PB119A

PB119B

PB119C

PB119D

PB121A

PB121B

PB121C

PB121D

PB122A

PB122B

PB122C

PB122D

PB123A

PB123B

PB123C

PB123D

PB125A

PB125B

PB125C

PB125D

PB126A

PB126B

PB126C

PB126D

PB127A

PB127B

PB127C

PB127D

PB129A

PB129B

PB129C

PB129D

PB130A

PB130B

PB130C

PB130D

PB131A

PB131B

PB131C

4

AY7

AU7

AU6

BA7

BA6

AN13

AN12

AV9

AV8

AT10

AT9

AW8

AW7

AP11

AP10

BB5

BB4

AR10

AR9

BA5

BA4

AT7

AT6

BB3

BA3

AM14

AL14

AY5

AY4

AN11

AN10

AV7

AV6

AM12

AM11

AW5

AW4

AT5

AT4

AY2

BA2

AP9

4-122

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AP8

AY3

PB117D

PB119A

PB119B

PB119C

PB119D

PB120A

PB120B

PB120C

PB120D

PB121A

PB121B

PB121C

PB121D

PB123A

PB123B

PB123C

PB123D

PB124A

PB124B

PB124C

PB124D

PB125A

PB125B

PB125C

PB125D

PROBE_VCC

PROBE_GND

PR95D

4

-

PB131D

PB133A

PB133B

PB133C

PB133D

PB134A

PB134B

PB134C

PB134D

PB135A

PB135B

PB135C

PB135D

PB138A

PB138B

PB138C

PB138D

PB139A

PB139B

PB139C

PB139D

PB141A

PB141B

PB141C

PB141D

PROBE_VCC

PROBE_GND

PR117D

PR117C

PR117B

PR117A

PR116D

PR116C

PR116B

PR116A

PR115D

PR115C

PR115B

PR115A

PR112D

PR112C

PR112B

PR112A

PR109D

PR109C

4

-

AW3

AR6

AR5

AU5

AV5

AL12

AL11

AV3

AV4

AN9

AN8

AW1

AY1

AK14

AK13

AV2

AW2

AM10

AM9

AV1

AU1

AL10

AL9

VREF1_4

LRC_DLLT_IN_C/LRC_DLLT_FB_D

LRC_DLLC_IN_C/LRC_DLLC_FB_D

LRC_DLLT_IN_C/LRC_DLLT_FB_D

LRC_DLLC_IN_C/LRC_DLLC_FB_D

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLT_IN_D/LRC_DLLT_FB_C

LRC_DLLC_IN_D/LRC_DLLC_FB_C

LRC_PLLT_IN_A/LRC_PLLT_FB_B

LRC_PLLC_IN_A/LRC_PLLC_FB_B

LRC_DLLT_IN_D/LRC_DLLT_FB_C

LRC_DLLC_IN_D/LRC_DLLC_FB_C

AT3

AU2

AP7

AN7

AR3

AR4

AP6

AN6

AT2

-

3

LRC_PLLC_IN_B/LRC_PLLC_FB_A

LRC_PLLT_IN_B/LRC_PLLT_FB_A

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

3

LRC_PLLC_IN_B/LRC_PLLC_FB_A

LRC_PLLT_IN_B/LRC_PLLT_FB_A

LRC_DLLC_IN_F/LRC_DLLC_FB_E

LRC_DLLT_IN_F/LRC_DLLT_FB_E

PR95C

PR95B

PR95A

PR94D

PR94C

PR94B

AR2

AM6

AL6

PR94A

PR93D

LRC_DLLC_IN_E/LRC_DLLC_FB_F

LRC_DLLT_IN_E/LRC_DLLT_FB_F

LRC_DLLC_IN_E/LRC_DLLC_FB_F

LRC_DLLT_IN_E/LRC_DLLT_FB_F

PR93C

AP5

AN5

AL8

PR93B

PR93A

PR91D

AK8

AP2

AN2

AJ12

AH12

PR91C

PR91B

PR91A

PR90D

PR90C

4-123

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AP1

AN1

AK10

AJ10

AM5

AL5

PR90B

PR90A

PR89D

PR89C

PR89B

PR89A

PR86D

PR86C

PR86B

PR86A

PR85D

PR85C

PR85B

PR85A

PR84D

PR84C

PR84B

PR84A

PR82D

PR82C

PR82B

PR82A

PR81D

PR81C

PR81B

PR81A

PR80D

PR80C

PR80B

PR80A

PR78D

PR78C

PR78B

PR78A

PR77D

PR77C

PR77B

PR77A

PR76D

PR76C

PR76B

PR76A

PR74D

PR74C

PR74B

3

PR109B

PR109A

PR107D

PR107C

PR107B

PR107A

PR104D

PR104C

PR104B

PR104A

PR103D

PR103C

PR103B

PR103A

PR99D

PR99C

PR99B

PR99A

PR98D

PR98C

PR98B

PR98A

PR96D

PR96C

PR96B

PR96A

PR94D

PR94C

PR94B

PR94A

PR92D

PR92C

PR92B

PR92A

PR91D

PR91C

PR91B

PR91A

PR90D

PR90C

PR90B

PR90A

PR88D

PR88C

PR88B

3

VREF2_3

AL7

AK7

AM1

AL1

AJ11

AH11

AK5

AJ5

AK9

AJ9

AK3

AJ3

AK6

AJ6

AK2

AJ2

AH10

AG10

AK1

AJ1

AH9

AG9

AH2

AG2

AH8

AG8

AG1

AH1

AG14

AF14

AG4

AF4

AH7

AG7

AG3

AF3

AH6

AG6

AF1

DIFFR_3

4-124

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AE1

AF12

AE12

AF2

AE2

AF11

AE11

AF5

AE5

AF10

AE10

AD1

AC1

AF9

AE9

AD2

AC2

AF6

AE6

AD3

AC3

AE8

AD8

AD4

AC4

AE7

AD7

AD5

AC5

AD6

AC6

AB1

AA1

AD9

AC9

AB2

AA2

AD14

AC14

AB5

AA5

AD10

AC10

Y1

PR74A

PR73D

PR73C

PR73B

PR73A

PR72D

PR72C

PR72B

PR72A

PR69D

PR69C

PR69B

PR69A

PR68D

PR68C

PR68B

PR68A

PR67D

PR67C

PR67B

PR67A

PR65D

PR65C

PR65B

PR65A

PR64D

PR64C

PR64B

PR64A

PR63D

PR63C

PR63B

PR63A

PR61D

PR61C

PR61B

PR61A

PR60D

PR60C

PR60B

PR60A

PR59D

PR59C

PR59B

PR59A

3

PR88A

PR87D

PR87C

PR87B

PR87A

PR86D

PR86C

PR86B

PR86A

PR83D

PR83C

PR83B

PR83A

PR82D

PR82C

PR82B

PR82A

PR81D

PR81C

PR81B

PR81A

PR79D

PR79C

PR79B

PR79A

PR78D

PR78C

PR78B

PR78A

PR77D

PR77C

PR77B

PR77A

PR75D

PR75C

PR75B

PR75A

PR74D

PR74C

PR74B

PR74A

PR73D

PR73C

PR73B

PR73A

3

W1

4-125

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AB6

AA6

Y2

PR57D

PR57C

PR57B

PR57A

PR56D

PR56C

PR56B

PR56A

PR55D

PR55C

PR55B

PR55A

PR52D

PR52C

PR52B

PR52A

PR51D

PR51C

PR51B

PR51A

PR50D

PR50C

PR50B

PR50A

PR48D

PR48C

PR48B

PR48A

PR47D

PR47C

PR47B

PR47A

PR46D

PR46C

PR46B

PR46A

PR43D

PR43C

PR43B

PR43A

PR42D

PR42C

PR42B

PR42A

PR41D

3

2

PR71D

PR71C

PR71B

PR71A

PR70D

PR70C

PR70B

PR70A

PR69D

PR69C

PR69B

PR69A

PR66D

PR66C

PR66B

PR66A

PR65D

PR65C

PR65B

PR65A

PR64D

PR64C

PR64B

PR64A

PR62D

PR62C

PR62B

PR62A

PR61D

PR61C

PR61B

PR61A

PR60D

PR60C

PR60B

PR60A

PR57D

PR57C

PR57B

PR57A

PR56D

PR56C

PR56B

PR56A

PR55D

3

2

W2

AB7

AA7

Y3

W3

AC11

AB11

Y4

VREF1_3

W4

AB8

AA8

Y5

PCLKC3_2

PCLKT3_2

PCLKC3_2

PCLKT3_2

W5

AC12

AB12

V1

PCLKC3_3

PCLKT3_3

PCLKC3_3

PCLKT3_3

U1

W7

V7

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_3

PCLKT2_3

PCLKC2_1

PCLKT2_1

PCLKC3_1

PCLKT3_1

PCLKC3_0

PCLKT3_0

PCLKC2_2

PCLKT2_2

PCLKC2_0

PCLKT2_0

PCLKC2_3

PCLKT2_3

PCLKC2_1

PCLKT2_1

V2

U2

AB9

AA9

T1

R1

AB10

AA10

U3

T3

Y9

W9

V5

U5

AA11

Y11

Y6

W6

Y10

W10

T2

R2

W8

4-126

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

V8

T4

PR41C

PR41B

PR41A

PR39D

PR39C

PR39B

PR39A

PR38D

PR38C

PR38B

PR38A

PR37D

PR37C

PR37B

PR37A

PR35D

PR35C

PR35B

PR35A

PR34D

PR34C

PR34B

PR34A

PR33D

PR33C

PR33B

PR33A

PR31D

PR31C

PR31B

PR31A

PR30D

PR30C

PR30B

PR30A

PR29D

PR29C

PR29B

PR29A

PR26D

PR26C

PR26B

PR26A

PR25D

PR25C

2

PR55C

PR55B

PR55A

PR53D

PR53C

PR53B

PR53A

PR52D

PR52C

PR52B

PR52A

PR51D

PR51C

PR51B

PR51A

PR49D

PR49C

PR49B

PR49A

PR48D

PR48C

PR48B

PR48A

PR47D

PR47C

PR47B

PR47A

PR45D

PR45C

PR45B

PR45A

PR44D

PR44C

PR44B

PR44A

PR43D

PR43C

PR43B

PR43A

PR40D

PR40C

PR40B

PR40A

PR38D

PR38C

2

U4

V9

U9

V6

U6

AA12

Y12

P1

N1

T7

R7

T5

R5

U10

V10

P2

N2

T8

R8

N3

P3

M6

M7

T6

R6

V11

U11

M1

L1

Y14

W14

M2

L2

T9

DIFFR_2

VREF1_2

DIFFR_2

VREF1_2

R9

P4

N4

N7

N8

P5

N5

K7

J7

4-127

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

J1

K1

PR25B

PR25A

2

-

PR38B

PR38A

2

-

V12

U12

K2

PR24D

PR24C

PR24B

PR34D

PR34C

PR34B

J2

PR24A

PR34A

R10

T10

L5

PR22D

PR22C

PR22B

PR30D

PR30C

PR30B

K5

PR22A

PR30A

P9

PR21D

PR21C

PR21B

PR26D

PR26C

PR26B

N9

L6

K6

PR21A

PR26A

M8

M9

H1

PR20D

PR20C

PR20B

PR19D

PR19C

PR19B

G1

PR20A

PR19A

U14

T14

H2

PR18D

PR18C

PR18B

VREF2_2

PR18D

PR18C

PR18B

VREF2_2

URC_DLLC_IN_D/URC_DLLC_FB_C

URC_DLLT_IN_D/URC_DLLT_FB_C

URC_PLLC_IN_B/URC_PLLC_FB_A

URC_PLLT_IN_B/URC_PLLT_FB_A

URC_DLLC_IN_C/URC_DLLC_FB_D

URC_DLLT_IN_C/URC_DLLT_FB_D

URC_DLLC_IN_D/URC_DLLC_FB_C

URC_DLLT_IN_D/URC_DLLT_FB_C

URC_PLLC_IN_B/URC_PLLC_FB_A

URC_PLLT_IN_B/URC_PLLT_FB_A

URC_DLLC_IN_C/URC_DLLC_FB_D

URC_DLLT_IN_C/URC_DLLT_FB_D

G2

PR18A

P10

N10

H3

PR17D

PR17C

PR17B

PR17D

PR17C

PR17B

G3

PR17A

R11

P11

J5

PR16D

PR16C

PR16B

PR15D

PR15C

PR15B

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

URC_PLLC_IN_A/URC_PLLC_FB_B

URC_PLLT_IN_A/URC_PLLT_FB_B

J6

PR16A

PR15A

P18

P19

R21

P20

P12

P17

P21

P13

H10

N13

H9

VCCJ

TDO

-

TDO

-

TDO

TMS

-

TMS

-

TCK

-

TCK

-

TDI

-

TDI

-

PROGRAMN

MPIIRQN

CCLK

1

-

PROGRAMN

MPIIRQN

CCLK

1

-

CFGIRQN/MPI_IRQ_N

RESP_URC

VCC12

A_REFCLKN_R

A_REFCLKP_R

VCC12

A_VDDIB0_R

A_HDINP0_R

RESP_URC

VCC12

A_REFCLKN_R

A_REFCLKP_R

VCC12

A_VDDIB0_R

A_HDINP0_R

-

G9

-

F2

-

H4

-

C1

-

PCS 3E0 CH 0 IN P

-

PCS 3E0 CH 0 IN P

4-128

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

D1

F1

A_HDINN0_R

VCC12

-

PCS 3E0 CH 0 IN N

PCS 3E0 CH 0 OUT P

PCS 3E0 CH 0 OUT N

PCS 3E0 CH 1 OUT N

A_HDINN0_R

VCC12

-

PCS 3E0 CH 0 IN N

PCS 3E0 CH 0 OUT P

PCS 3E0 CH 0 OUT N

PCS 3E0 CH 1 OUT N

A3

A_HDOUTP0_R

A_VDDOB0_R

A_HDOUTN0_R

A_VDDOB1_R

A_HDOUTN1_R

VCC12

A_HDOUTP0_R

A_VDDOB0_R

A_HDOUTN0_R

A_VDDOB1_R

A_HDOUTN1_R

VCC12

E1

B3

C2

A4

B2

B4

A_HDOUTP1_R

A_HDINN1_R

A_HDINP1_R

VCC12

PCS 3E0 CH 1 OUT P

PCS 3E0 CH 1 IN N

PCS 3E0 CH 1 IN P

A_HDOUTP1_R

A_HDINN1_R

A_HDINP1_R

VCC12

PCS 3E0 CH 1 OUT P

PCS 3E0 CH 1 IN N

PCS 3E0 CH 1 IN P

E3

D3

M10

E2

A_VDDIB1_R

VCC12

A_VDDIB1_R

VCC12

J11

M11

D4

E4

A_VDDIB2_R

A_HDINP2_R

A_HDINN2_R

VCC12

A_VDDIB2_R

A_HDINP2_R

A_HDINN2_R

VCC12

PCS 3E0 CH 2 IN P

PCS 3E0 CH 2 IN N

PCS 3E0 CH 2 IN P

PCS 3E0 CH 2 IN N

K9

A5

A_HDOUTP2_R

A_VDDOB2_R

A_HDOUTN2_R

A_VDDOB3_R

A_HDOUTN3_R

VCC12

PCS 3E0 CH 2 OUT P

PCS 3E0 CH 2 OUT N

PCS 3E0 CH 3 OUT N

A_HDOUTP2_R

A_VDDOB2_R

A_HDOUTN2_R

A_VDDOB3_R

A_HDOUTN3_R

VCC12

PCS 3E0 CH 2 OUT P

PCS 3E0 CH 2 OUT N

PCS 3E0 CH 3 OUT N

D2

B5

L10

B6

G6

A6

A_HDOUTP3_R

A_HDINN3_R

A_HDINP3_R

VCC12

PCS 3E0 CH 3 OUT P

PCS 3E0 CH 3 IN N

PCS 3E0 CH 3 IN P

A_HDOUTP3_R

A_HDINN3_R

A_HDINP3_R

VCC12

PCS 3E0 CH 3 OUT P

PCS 3E0 CH 3 IN N

PCS 3E0 CH 3 IN P

E5

D5

K12

L13

N14

F9

A_VDDIB3_R

VCC12

A_VDDIB3_R

VCC12

B_VDDIB0_R

B_HDINP0_R

B_HDINN0_R

VCC12

B_VDDIB0_R

B_HDINP0_R

B_HDINN0_R

VCC12

D6

E6

PCS 3E1 CH 0 IN P

PCS 3E1 CH 0 IN N

PCS 3E1 CH 0 IN P

PCS 3E1 CH 0 IN N

J8

B7

B_HDOUTP0_R

B_VDDOB0_R

B_HDOUTN0_R

B_VDDOB1_R

B_HDOUTN1_R

VCC12

PCS 3E1 CH 0 OUT P

PCS 3E1 CH 0 OUT N

PCS 3E1 CH 1 OUT N

B_HDOUTP0_R

B_VDDOB0_R

B_HDOUTN0_R

B_VDDOB1_R

B_HDOUTN1_R

VCC12

PCS 3E1 CH 0 OUT P

PCS 3E1 CH 0 OUT N

PCS 3E1 CH 1 OUT N

G4

A7

K8

A8

L9

B8

B_HDOUTP1_R

B_HDINN1_R

B_HDINP1_R

VCC12

PCS 3E1 CH 1 OUT P

PCS 3E1 CH 1 IN N

PCS 3E1 CH 1 IN P

B_HDOUTP1_R

B_HDINN1_R

B_HDINP1_R

VCC12

PCS 3E1 CH 1 OUT P

PCS 3E1 CH 1 IN N

PCS 3E1 CH 1 IN P

E7

D7

F10

K13

B_VDDIB1_R

4-129

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

K14

H11

D8

VCC12

-

VCC12

-

B_VDDIB2_R

B_HDINP2_R

B_HDINN2_R

VCC12

B_VDDIB2_R

B_HDINP2_R

B_HDINN2_R

VCC12

PCS 3E1 CH 2 IN P

PCS 3E1 CH 2 IN N

PCS 3E1 CH 2 IN P

PCS 3E1 CH 2 IN N

E8

G5

B9

B_HDOUTP2_R

B_VDDOB2_R

B_HDOUTN2_R

B_VDDOB3_R

B_HDOUTN3_R

VCC12

PCS 3E1 CH 2 OUT P

PCS 3E1 CH 2 OUT N

PCS 3E1 CH 3 OUT N

B_HDOUTP2_R

B_VDDOB2_R

B_HDOUTN2_R

B_VDDOB3_R

B_HDOUTN3_R

VCC12

PCS 3E1 CH 2 OUT P

PCS 3E1 CH 2 OUT N

PCS 3E1 CH 3 OUT N

L12

A9

C5

A10

H5

B10

E9

B_HDOUTP3_R

B_HDINN3_R

B_HDINP3_R

VCC12

PCS 3E1 CH 3 OUT P

PCS 3E1 CH 3 IN N

PCS 3E1 CH 3 IN P

B_HDOUTP3_R

B_HDINN3_R

B_HDINP3_R

VCC12

PCS 3E1 CH 3 OUT P

PCS 3E1 CH 3 IN N

PCS 3E1 CH 3 IN P

D9

J13

H12

J12

M14

L14

J14

G12

D10

E10

H6

B_VDDIB3_R

VCC12

B_VDDIB3_R

VCC12

B_REFCLKN_R

B_REFCLKP_R

VCC12

B_REFCLKN_R

B_REFCLKP_R

VCC12

C_VDDIB0_R

C_HDINP0_R

C_HDINN0_R

VCC12

C_VDDIB0_R

C_HDINP0_R

C_HDINN0_R

VCC12

PCS 3E2 CH 0 IN P

PCS 3E2 CH 0 IN N

PCS 3E2 CH 0 IN P

PCS 3E2 CH 0 IN N

B11

M12

A11

L11

A12

K11

B12

E11

D11

H13

C6

C_HDOUTP0_R

C_VDDOB0_R

C_HDOUTN0_R

C_VDDOB1_R

C_HDOUTN1_R

VCC12

PCS 3E2 CH 0 OUT P

PCS 3E2 CH 0 OUT N

PCS 3E2 CH 1 OUT N

C_HDOUTP0_R

C_VDDOB0_R

C_HDOUTN0_R

C_VDDOB1_R

C_HDOUTN1_R

VCC12

PCS 3E2 CH 0 OUT P

PCS 3E2 CH 0 OUT N

PCS 3E2 CH 1 OUT N

C_HDOUTP1_R

C_HDINN1_R

C_HDINP1_R

VCC12

PCS 3E2 CH 1 OUT P

PCS 3E2 CH 1 IN N

PCS 3E2 CH 1 IN P

C_HDOUTP1_R

C_HDINN1_R

C_HDINP1_R

VCC12

PCS 3E2 CH 1 OUT P

PCS 3E2 CH 1 IN N

PCS 3E2 CH 1 IN P

C_VDDIB1_R

VCC12

C_VDDIB1_R

VCC12

H15

G13

D12

E12

J9

C_VDDIB2_R

C_HDINP2_R

C_HDINN2_R

VCC12

C_VDDIB2_R

C_HDINP2_R

C_HDINN2_R

VCC12

PCS 3E2 CH 2 IN P

PCS 3E2 CH 2 IN N

PCS 3E2 CH 2 IN P

PCS 3E2 CH 2 IN N

B13

K10

A13

J10

A14

C_HDOUTP2_R

C_VDDOB2_R

C_HDOUTN2_R

C_VDDOB3_R

C_HDOUTN3_R

PCS 3E2 CH 2 OUT P

PCS 3E2 CH 2 OUT N

PCS 3E2 CH 3 OUT N

C_HDOUTP2_R

C_VDDOB2_R

C_HDOUTN2_R

C_VDDOB3_R

C_HDOUTN3_R

PCS 3E2 CH 2 OUT P

PCS 3E2 CH 2 OUT N

PCS 3E2 CH 3 OUT N

4-130

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

F5

VCC12

C_HDOUTP3_R

C_HDINN3_R

C_HDINP3_R

VCC12

-

1

VCC12

C_HDOUTP3_R

C_HDINN3_R

C_HDINP3_R

VCC12

-

1

B14

E13

D13

F12

G14

F11

K15

J15

G15

H16

D14

E14

F6

PCS 3E2 CH 3 OUT P

PCS 3E2 CH 3 IN N

PCS 3E2 CH 3 IN P

PCS 3E2 CH 3 OUT P

PCS 3E2 CH 3 IN N

PCS 3E2 CH 3 IN P

C_VDDIB3_R

VCC12

C_VDDIB3_R

VCC12

C_REFCLKN_R

C_REFCLKP_R

VCC12

C_REFCLKN_R

C_REFCLKP_R

VCC12

D_VDDIB0_R

D_HDINP0_R

D_HDINN0_R

VCC12

D_VDDIB0_R

D_HDINP0_R

D_HDINN0_R

VCC12

PCS 3E3 CH 0 IN P

PCS 3E3 CH 0 IN N

PCS 3E3 CH 0 IN P

PCS 3E3 CH 0 IN N

B15

M13

A15

F8

D_HDOUTP0_R

D_VDDOB0_R

D_HDOUTN0_R

D_VDDOB1_R

D_HDOUTN1_R

VCC12

PCS 3E3 CH 0 OUT P

PCS 3E3 CH 0 OUT N

PCS 3E3 CH 1 OUT N

D_HDOUTP0_R

D_VDDOB0_R

D_HDOUTN0_R

D_VDDOB1_R

D_HDOUTN1_R

VCC12

PCS 3E3 CH 0 OUT P

PCS 3E3 CH 0 OUT N

PCS 3E3 CH 1 OUT N

A16

F7

B16

F15

E15

K17

F13

C14

C15

D16

E16

C11

B17

C9

D_HDOUTP1_R

D_HDINN1_R

D_HDINP1_R

VCC12

PCS 3E3 CH 1 OUT P

PCS 3E3 CH 1 IN N

PCS 3E3 CH 1 IN P

D_HDOUTP1_R

D_HDINN1_R

D_HDINP1_R

VCC12

PCS 3E3 CH 1 OUT P

PCS 3E3 CH 1 IN N

PCS 3E3 CH 1 IN P

D_VDDIB1_R

VCC12

D_VDDIB1_R

VCC12

D_VDDIB2_R

D_HDINP2_R

D_HDINN2_R

VCC12

D_VDDIB2_R

D_HDINP2_R

D_HDINN2_R

VCC12

PCS 3E3 CH 2 IN P

PCS 3E3 CH 2 IN N

PCS 3E3 CH 2 IN P

PCS 3E3 CH 2 IN N

D_HDOUTP2_R

D_VDDOB2_R

D_HDOUTN2_R

D_VDDOB3_R

D_HDOUTN3_R

VCC12

PCS 3E3 CH 2 OUT P

PCS 3E3 CH 2 OUT N

PCS 3E3 CH 3 OUT N

D_HDOUTP2_R

D_VDDOB2_R

D_HDOUTN2_R

D_VDDOB3_R

D_HDOUTN3_R

VCC12

PCS 3E3 CH 2 OUT P

PCS 3E3 CH 2 OUT N

PCS 3E3 CH 3 OUT N

A17

D17

A18

C17

B18

F17

E17

F14

F16

G16

M17

L17

G18

D_HDOUTP3_R

D_HDINN3_R

D_HDINP3_R

VCC12

PCS 3E3 CH 3 OUT P

PCS 3E3 CH 3 IN N

PCS 3E3 CH 3 IN P

D_HDOUTP3_R

D_HDINN3_R

D_HDINP3_R

VCC12

PCS 3E3 CH 3 OUT P

PCS 3E3 CH 3 IN N

PCS 3E3 CH 3 IN P

D_VDDIB3_R

VCC12

D_VDDIB3_R

VCC12

D_REFCLKN_R

D_REFCLKP_R

PT77D

D_REFCLKN_R

D_REFCLKP_R

PT93D

HDC/SI

4-131

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

H18

F18

E18

H19

G19

D19

D18

J20

PT77C

PT77B

PT77A

PT75D

PT75C

PT75B

PT75A

PT74D

PT74C

PT74B

PT74A

PT73D

PT73C

PT73B

PT73A

PT71D

PT71C

PT71B

PT71A

PT70D

PT70C

PT70B

PT70A

PT69D

PT69C

PT69B

PT69A

PT67D

PT67C

PT67B

PT67A

PT66D

PT66C

PT66B

PT66A

PT65D

PT65C

PT65B

PT65A

PT63D

PT63C

PT63B

PT63A

PT61D

PT61C

1

LDCN/SCS

D8/MPI_DATA8

CS1/MPI_CS1

D9/MPI_DATA9

PT93C

PT93B

PT93A

PT90D

PT90C

PT90B

PT90A

PT89D

PT89C

PT89B

PT89A

PT87D

PT87C

PT87B

PT87A

PT86D

PT86C

PT86B

PT86A

PT83D

PT83C

PT83B

PT83A

PT81D

PT81C

PT81B

PT81A

PT78D

PT78C

PT78B

PT78A

PT75D

PT75C

PT75B

PT75A

PT73D

PT73C

PT73B

PT73A

PT71D

PT71C

PT71B

PT71A

PT69D

PT69C

1

LDCN/SCS

D8/MPI_DATA8

CS1/MPI_CS1

D9/MPI_DATA9

D10/MPI_DATA10

CS0N/MPI_CS0N

RDN/MPI_STRB_N

WRN/MPI_WR_N

D7/MPI_DATA7

D10/MPI_DATA10

CS0N/MPI_CS0N

RDN/MPI_STRB_N

WRN/MPI_WR_N

D7/MPI_DATA7

K20

E19

F19

K18

J18

D6/MPI_DATA6

D5/MPI_DATA5

D4/MPI_DATA4

D3/MPI_DATA3

A19

B19

H17

J17

D2/MPI_DATA2

D1/MPI_DATA1

D16/PCLKC1_3/MPI_DATA16

D17/PCLKT1_3/MPI_DATA17

D0/MPI_DATA0

D16/PCLKC1_3/MPI_DATA16

D17/PCLKT1_3/MPI_DATA17

D0/MPI_DATA0

B20

C20

M20

L20

F20

G20

K19

J19

QOUT/CEON

VREF2_1

D18/MPI_DATA18

DOUT

D18/MPI_DATA18

DOUT

MCA_DONE_IN

D19/PCLKC1_2/MPI_DATA19

D20/PCLKT1_2/MPI_DATA20

MCA_CLK_P1_OUT

MCA_CLK_P1_IN

D21/PCLKC1_1/MPI_DATA21

D22/PCLKT1_1/MPI_DATA22

MCA_CLK_P2_OUT

MCA_CLK_P2_IN

MCA_DONE_OUT

BUSYN/RCLK/SCK

DP0/MPI_PAR0

D19/PCLKC1_2/MPI_DATA19

D20/PCLKT1_2/MPI_DATA20

MCA_CLK_P1_OUT

MCA_CLK_P1_IN

D21/PCLKC1_1/MPI_DATA21

D22/PCLKT1_1/MPI_DATA22

MCA_CLK_P2_OUT

MCA_CLK_P2_IN

MCA_DONE_OUT

BUSYN/RCLK/SCK

DP0/MPI_PAR0

D20

E20

H21

G21

B21

C21

M21

L21

A21

A20

J21

MPI_TA

D23/MPI_DATA23

DP2/MPI_PAR2

D23/MPI_DATA23

DP2/MPI_PAR2

K21

E21

F21

G22

H22

A23

A22

L22

M22

PCLKC1_0

PCLKT1_0/MPI_CLK

DP3/PCLKC1_4/MPI_PAR3

D24/PCLKT1_4/MPI_DATA24

MPI_RETRY

PCLKT1_0/MPI_CLK

DP3/PCLKC1_4/MPI_PAR3

D24/PCLKT1_4/MPI_DATA24

MPI_RETRY

A0/MPI_ADDR14

A1/MPI_ADDR15

A2/MPI_ADDR16

A0/MPI_ADDR14

A1/MPI_ADDR15

A2/MPI_ADDR16

4-132

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

B22

B23

K23

J23

PT61B

PT61A

1

-

A3/MPI_ADDR17

A4/MPI_ADDR18

PT69B

PT69A

1

-

A3/MPI_ADDR17

A4/MPI_ADDR18

PT60D

D25/PCLKC1_5/MPI_DATA25

D26/PCLKT1_5/MPI_DATA26

A5/MPI_ADDR19

PT66D

D25/PCLKC1_5/MPI_DATA25

D26/PCLKT1_5/MPI_DATA26

A5/MPI_ADDR19

PT60C

PT66C

D22

E22

K22

J22

PT60B

PT66B

PT60A

A6/MPI_ADDR20

PT66A

A6/MPI_ADDR20

PT59D

D27/MPI_DATA27

VREF1_1

PT63D

D27/MPI_DATA27

VREF1_1

PT59C

PT63C

D23

C23

L23

M23

A24

B24

K25

J25

PT59B

A7/MPI_ADDR21

PT63B

A7/MPI_ADDR21

PT59A

A8/MPI_ADDR22

PT63A

A8/MPI_ADDR22

PT57D

D28/PCLKC1_6/MPI_DATA28

D29/PCLKT1_6/MPI_DATA29

A9/MPI_ADDR23

PT61D

D28/PCLKC1_6/MPI_DATA28

D29/PCLKT1_6/MPI_DATA29

A9/MPI_ADDR23

PT57C

PT61C

PT57B

PT61B

PT57A

A10/MPI_ADDR24

D30/PCLKC1_7/MPI_DATA30

D31/PCLKT1_7/MPI_DATA31

A11/MPI_ADDR25

A12/MPI_ADDR26

D11/MPI_DATA11

D12/MPI_DATA12

A13/MPI_ADDR27

A14/MPI_ADDR28

A16/MPI_ADDR30

D13/MPI_DATA13

A15/MPI_ADDR29

A17/MPI_ADDR31

A19/MPI_TSIZ1

PT61A

A10/MPI_ADDR24

D30/PCLKC1_7/MPI_DATA30

D31/PCLKT1_7/MPI_DATA31

A11/MPI_ADDR25

A12/MPI_ADDR26

D11/MPI_DATA11

D12/MPI_DATA12

A13/MPI_ADDR27

A14/MPI_ADDR28

A16/MPI_ADDR30

D13/MPI_DATA13

A15/MPI_ADDR29

A17/MPI_ADDR31

A19/MPI_TSIZ1

PT56D

PT58D

PT56C

PT58C

F23

F22

J26

PT56B

PT58B

PT56A

PT58A

PT55D

PT57D

K26

E23

E24

G23

G24

F26

F27

H25

H24

C25

C26

K24

J24

PT55C

PT57C

PT55B

PT57B

PT55A

PT57A

PT53D

PT55D

PT53C

PT55C

PT53B

PT55B

PT53A

PT55A

PT52D

PT54D

PT52C

A20/MPI_BDIP

PT54C

A20/MPI_BDIP

PT52B

A18/MPI_TSIZ0

PT54B

A18/MPI_TSIZ0

PT52A

MPI_TEA

PT54A

MPI_TEA

PT51D

D14/MPI_DATA14

DP1/MPI_PAR1

PT51D

D14/MPI_DATA14

DP1/MPI_PAR1

PT51C

F24

F25

L26

M26

G27

C29

F28

D26

E26

B25

D24

A25

E25

PT51B

A21/MPI_BURST

PT51B

A21/MPI_BURST

PT51A

D15/MPI_DATA15

PT51A

D15/MPI_DATA15

D_REFCLKP_L

D_REFCLKN_L

VCC12

D_REFCLKP_L

D_REFCLKN_L

VCC12

-

D_VDDIB3_L

VCC12

-

D_VDDIB3_L

VCC12

-

D_HDINP3_L

D_HDINN3_L

D_HDOUTP3_L

VCC12

-

PCS 363 CH 3 IN P

PCS 363 CH 3 IN N

PCS 363 CH 3 OUT P

D_HDINP3_L

D_HDINN3_L

D_HDOUTP3_L

VCC12

-

PCS 363 CH 3 IN P

PCS 363 CH 3 IN N

PCS 363 CH 3 OUT P

-

D_HDOUTN3_L

D_VDDOB3_L

-

PCS 363 CH 3 OUT N

D_HDOUTN3_L

D_VDDOB3_L

-

PCS 363 CH 3 OUT N

-

4-133

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

A26

C34

B26

C32

E27

D27

G25

F29

H26

F30

D28

E28

B27

F36

A27

F35

A28

M30

B28

F37

E29

D29

H27

G28

J28

D_HDOUTN2_L

D_VDDOB2_L

D_HDOUTP2_L

VCC12

-

PCS 363 CH 2 OUT N

D_HDOUTN2_L

D_VDDOB2_L

D_HDOUTP2_L

VCC12

-

PCS 363 CH 2 OUT N

PCS 363 CH 2 OUT P

D_HDINN2_L

D_HDINP2_L

D_VDDIB2_L

VCC12

PCS 363 CH 2 IN N

PCS 363 CH 2 IN P

D_HDINN2_L

D_HDINP2_L

D_VDDIB2_L

VCC12

PCS 363 CH 2 IN N

PCS 363 CH 2 IN P

D_VDDIB1_L

VCC12

D_VDDIB1_L

VCC12

D_HDINP1_L

D_HDINN1_L

D_HDOUTP1_L

VCC12

PCS 363 CH 1 IN P

PCS 363 CH 1 IN N

PCS 363 CH 1 OUT P

D_HDINP1_L

D_HDINN1_L

D_HDOUTP1_L

VCC12

PCS 363 CH 1 IN P

PCS 363 CH 1 IN N

PCS 363 CH 1 OUT P

D_HDOUTN1_L

D_VDDOB1_L

D_HDOUTN0_L

D_VDDOB0_L

D_HDOUTP0_L

VCC12

PCS 363 CH 1 OUT N

PCS 363 CH 0 OUT N

PCS 363 CH 0 OUT P

D_HDOUTN1_L

D_VDDOB1_L

D_HDOUTN0_L

D_VDDOB0_L

D_HDOUTP0_L

VCC12

PCS 363 CH 1 OUT N

PCS 363 CH 0 OUT N

PCS 363 CH 0 OUT P

D_HDINN0_L

D_HDINP0_L

D_VDDIB0_L

VCC12

PCS 363 CH 0 IN N

PCS 363 CH 0 IN P

D_HDINN0_L

D_HDINP0_L

D_VDDIB0_L

VCC12

PCS 363 CH 0 IN N

PCS 363 CH 0 IN P

C_REFCLKP_L

C_REFCLKN_L

VCC12

C_REFCLKP_L

C_REFCLKN_L

VCC12

K28

F32

G29

C31

D30

E30

B29

F38

A29

J33

C_VDDIB3_L

VCC12

C_VDDIB3_L

VCC12

C_HDINP3_L

C_HDINN3_L

C_HDOUTP3_L

VCC12

PCS 362 CH 3 IN P

PCS 362 CH 3 IN N

PCS 362 CH 3 OUT P

C_HDINP3_L

C_HDINN3_L

C_HDOUTP3_L

VCC12

PCS 362 CH 3 IN P

PCS 362 CH 3 IN N

PCS 362 CH 3 OUT P

C_HDOUTN3_L

C_VDDOB3_L

C_HDOUTN2_L

C_VDDOB2_L

C_HDOUTP2_L

VCC12

PCS 362 CH 3 OUT N

PCS 362 CH 2 OUT N

PCS 362 CH 2 OUT P

C_HDOUTN3_L

C_VDDOB3_L

C_HDOUTN2_L

C_VDDOB2_L

C_HDOUTP2_L

VCC12

PCS 362 CH 3 OUT N

PCS 362 CH 2 OUT N

PCS 362 CH 2 OUT P

A30

K33

B30

J34

F31

E31

G30

H28

C37

H30

C_HDINN2_L

C_HDINP2_L

C_VDDIB2_L

VCC12

PCS 362 CH 2 IN N

PCS 362 CH 2 IN P

C_HDINN2_L

C_HDINP2_L

C_VDDIB2_L

VCC12

PCS 362 CH 2 IN N

PCS 362 CH 2 IN P

C_VDDIB1_L

VCC12

C_VDDIB1_L

VCC12

4-134

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

D32

E32

B31

K32

A31

L32

A32

M31

B32

H37

E33

D33

G31

J29

C_HDINP1_L

C_HDINN1_L

C_HDOUTP1_L

VCC12

-

PCS 362 CH 1 IN P

PCS 362 CH 1 IN N

PCS 362 CH 1 OUT P

C_HDINP1_L

C_HDINN1_L

C_HDOUTP1_L

VCC12

-

PCS 362 CH 1 IN P

PCS 362 CH 1 IN N

PCS 362 CH 1 OUT P

C_HDOUTN1_L

C_VDDOB1_L

C_HDOUTN0_L

C_VDDOB0_L

C_HDOUTP0_L

VCC12

PCS 362 CH 1 OUT N

PCS 362 CH 0 OUT N

PCS 362 CH 0 OUT P

C_HDOUTN1_L

C_VDDOB1_L

C_HDOUTN0_L

C_VDDOB0_L

C_HDOUTP0_L

VCC12

PCS 362 CH 1 OUT N

PCS 362 CH 0 OUT N

PCS 362 CH 0 OUT P

C_HDINN0_L

C_HDINP0_L

C_VDDIB0_L

VCC12

PCS 362 CH 0 IN N

PCS 362 CH 0 IN P

C_HDINN0_L

C_HDINP0_L

C_VDDIB0_L

VCC12

PCS 362 CH 0 IN N

PCS 362 CH 0 IN P

L29

M29

J31

B_REFCLKP_L

B_REFCLKN_L

VCC12

B_REFCLKP_L

B_REFCLKN_L

VCC12

H31

J30

B_VDDIB3_L

VCC12

B_VDDIB3_L

VCC12

D34

E34

B33

H38

A33

C38

A34

L31

B34

G38

E35

D35

H32

K29

K30

F33

D36

E36

B35

L34

A35

K35

A36

G39

B36

J35

B_HDINP3_L

B_HDINN3_L

B_HDOUTP3_L

VCC12

PCS 361 CH 3 IN P

PCS 361 CH 3 IN N

PCS 361 CH 3 OUT P

B_HDINP3_L

B_HDINN3_L

B_HDOUTP3_L

VCC12

PCS 361 CH 3 IN P

PCS 361 CH 3 IN N

PCS 361 CH 3 OUT P

B_HDOUTN3_L

B_VDDOB3_L

B_HDOUTN2_L

B_VDDOB2_L

B_HDOUTP2_L

VCC12

PCS 361 CH 3 OUT N

PCS 361 CH 2 OUT N

PCS 361 CH 2 OUT P

B_HDOUTN3_L

B_VDDOB3_L

B_HDOUTN2_L

B_VDDOB2_L

B_HDOUTP2_L

VCC12

PCS 361 CH 3 OUT N

PCS 361 CH 2 OUT N

PCS 361 CH 2 OUT P

B_HDINN2_L

B_HDINP2_L

B_VDDIB2_L

VCC12

PCS 361 CH 2 IN N

PCS 361 CH 2 IN P

B_HDINN2_L

B_HDINP2_L

B_VDDIB2_L

VCC12

PCS 361 CH 2 IN N

PCS 361 CH 2 IN P

B_VDDIB1_L

VCC12

B_VDDIB1_L

VCC12

B_HDINP1_L

B_HDINN1_L

B_HDOUTP1_L

VCC12

PCS 361 CH 1 IN P

PCS 361 CH 1 IN N

PCS 361 CH 1 OUT P

B_HDINP1_L

B_HDINN1_L

B_HDOUTP1_L

VCC12

PCS 361 CH 1 IN P

PCS 361 CH 1 IN N

PCS 361 CH 1 OUT P

B_HDOUTN1_L

B_VDDOB1_L

B_HDOUTN0_L

B_VDDOB0_L

B_HDOUTP0_L

VCC12

PCS 361 CH 1 OUT N

PCS 361 CH 0 OUT N

PCS 361 CH 0 OUT P

B_HDOUTN1_L

B_VDDOB1_L

B_HDOUTN0_L

B_VDDOB0_L

B_HDOUTP0_L

VCC12

PCS 361 CH 1 OUT N

PCS 361 CH 0 OUT N

PCS 361 CH 0 OUT P

4-135

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

E37

D37

F34

N29

L30

K31

D38

E38

A37

G37

B37

L33

B38

D41

A38

K34

E39

D39

M32

J32

B_HDINN0_L

B_HDINP0_L

B_VDDIB0_L

VCC12

-

PCS 361 CH 0 IN N

PCS 361 CH 0 IN P

B_HDINN0_L

B_HDINP0_L

B_VDDIB0_L

VCC12

-

PCS 361 CH 0 IN N

PCS 361 CH 0 IN P

-

A_VDDIB3_L

VCC12

A_VDDIB3_L

VCC12

-

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

VCC12

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

A_HDINP3_L

A_HDINN3_L

A_HDOUTP3_L

VCC12

-

PCS 360 CH 3 IN P

PCS 360 CH 3 IN N

PCS 360 CH 3 OUT P

-

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

VCC12

PCS 360 CH 3 OUT N

PCS 360 CH 2 OUT N

PCS 360 CH 2 OUT P

A_HDOUTN3_L

A_VDDOB3_L

A_HDOUTN2_L

A_VDDOB2_L

A_HDOUTP2_L

VCC12

-

PCS 360 CH 3 OUT N

PCS 360 CH 2 OUT N

PCS 360 CH 2 OUT P

-

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

VCC12

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

A_HDINN2_L

A_HDINP2_L

A_VDDIB2_L

VCC12

-

PCS 360 CH 2 IN N

PCS 360 CH 2 IN P

-

E41

M33

D40

E40

B39

B41

A39

C41

B40

E42

A40

F42

D42

C42

H39

F41

P16

P27

K39

L39

M38

K40

L40

N37

P37

A_VDDIB1_L

VCC12

A_VDDIB1_L

VCC12

-

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

VCC12

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

A_HDINP1_L

A_HDINN1_L

A_HDOUTP1_L

VCC12

-

PCS 360 CH 1 IN P

PCS 360 CH 1 IN N

PCS 360 CH 1 OUT P

-

A_HDOUTN1_L

A_VDDOB1_L

A_HDOUTN0_L

A_VDDOB0_L

A_HDOUTP0_L

VCC12

PCS 360 CH 1 OUT N

PCS 360 CH 0 OUT N

PCS 360 CH 0 OUT P

A_HDOUTN1_L

A_VDDOB1_L

A_HDOUTN0_L

A_VDDOB0_L

A_HDOUTP0_L

VCC12

-

PCS 360 CH 1 OUT N

PCS 360 CH 0 OUT N

PCS 360 CH 0 OUT P

-

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

VCC12

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

A_HDINN0_L

A_HDINP0_L

A_VDDIB0_L

VCC12

-

PCS 360 CH 0 IN N

PCS 360 CH 0 IN P

-

VDDAX25_R

VDDAX25_L

NC

VDDAX25_R

VDDAX25_L

PL32A

-

7

NC

PL32B

NC

PL35A

NC

PL36A

NC

PL36B

NC

PL39A

NC

PL39B

4-136

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AG38

AH38

AJ39

AK39

AL41

AM41

AN40

AM40

AM39

AN39

AR42

AT42

AT1

NC

-

PL95A

PL95B

PL100A

PL100B

PL105A

PL105B

PL108A

PL108B

PL111A

PL111B

PL113A

PL113B

PR113B

PR113A

PR111B

PR111A

PR108B

PR108A

PR105B

PR105A

PR100B

PR100A

PR95B

PR95A

PR39B

PR39A

PR36B

PR36A

PR35A

PR32B

PR32A

GND

6

3

2

-

NC

AR1

AN4

AM4

AM3

AN3

AM2

AL2

NC

AK4

AJ4

NC

AH5

AG5

P6

NC

N6

NC

L3

NC

K3

NC

M5

NC

L4

NC

K4

NC

A2

GND

A41

GND

-

AA20

AA23

AA3

AA39

AB20

AB23

AB4

AB40

AC17

AC19

AC21

AC22

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

4-137

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AC24

AC26

AC35

AC8

GND

-

GND

-

AD12

AD16

AD18

AD20

AD23

AD25

AD27

AD31

AE17

AE19

AE24

AE26

AE3

AE39

AF18

AF20

AF23

AF25

AF36

AF7

AG11

AG16

AG19

AG24

AG27

AG32

AH15

AH28

AH4

AH40

AJ35

AJ8

AK12

AK31

AL13

AL19

AL24

AL3

AL30

AL39

AM16

4-138

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AM27

AM36

AM7

AP4

GND

-

GND

-

AP40

AR14

AR20

AR23

AR29

AR35

AR8

AT11

AT17

AT26

AT32

AU3

AU39

AW12

AW18

AW22

AW28

AW34

AW6

AY15

AY21

AY25

AY31

AY37

AY9

B1

B42

BA1

BA42

BB2

BB41

C10

C12

C13

C16

C18

C19

C22

C24

C27

C28

4-139

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

C3

C30

C33

C35

C36

C39

C4

GND

-

GND

-

C40

C7

C8

D15

D21

D25

D31

F4

F40

G11

G17

G26

G32

H14

H20

H23

H29

H35

H8

J3

J39

L16

L27

L36

L7

M19

M24

M4

M40

N12

N31

P35

P8

R15

R28

R3

R39

T11

4-140

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

T16

T19

GND

VCC

-

GND

VCC

-

T24

T27

T32

U18

U20

U23

U25

U36

U7

G36

G7

V17

V19

V24

V26

V4

V40

W12

W16

W18

W20

W23

W25

W27

W31

Y17

Y19

Y21

Y22

AA17

AA18

AA19

AA21

AA22

AA24

AA25

AA26

AB17

AB18

AB19

AB21

AB22

AB24

4-141

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AB25

AB26

AC16

AC18

AC20

AC23

AC25

AC27

AD17

AD19

AD21

AD22

AD24

AD26

AE16

AE18

AE20

AE21

AE22

AE23

AE25

AE27

AF17

AF19

AF21

AF22

AF24

AF26

AG18

AG20

AG23

AG25

T18

VCC

-

VCC

-

T20

T23

T25

U17

U19

U21

U22

U24

U26

V16

V18

V20

4-142

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

V21

V22

VCC

-

VCC

-

V23

VCC

V25

VCC

V27

VCC

W17

W19

W21

W22

W24

W26

Y16

VCC

Y18

VCC

Y20

VCC

Y23

VCC

Y25

VCC

Y27

VCC

AG22

AG26

T17

VCC12

VCCAUX

VCC12

VCCAUX

T21

T22

T26

U16

U27

AC15

AC28

AD15

AD28

AE15

AE28

AF15

AF28

AG15

AG28

AH14

AH16

AH17

AH18

AH19

AH20

AH23

AH24

AH25

AH26

4-143

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AH27

AH29

AJ14

AJ15

AJ28

AJ29

P14

P15

P28

P29

R14

R16

R17

R18

R19

R20

R23

R24

R25

R26

R27

R29

T15

T28

U15

U28

V15

V28

W15

W28

Y15

Y28

F3

VCCAUX

VCCIO1

VCCIO2

-

VCCAUX

VCCIO1

VCCIO2

-

F39

G35

G8

L19

L24

M16

M27

N11

N32

AA4

H7

J4

4-144

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

L8

M3

VCCIO2

VCCIO3

VCCIO4

VCCIO5

-

VCCIO2

VCCIO3

VCCIO4

VCCIO5

-

P7

R4

T12

U8

V3

W11

Y7

AB3

AC7

AD11

AE4

AF8

AG12

AH3

AJ7

AK11

AL4

AM8

AP3

AR7

AU4

AL16

AM13

AM19

AR11

AR17

AT14

AT20

AT8

AW15

AW21

AW9

AY12

AY18

AY6

AL27

AM24

AM30

AR26

AR32

AT23

AT29

AT35

4-145

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AW25

AW31

AW37

AY22

AY28

AY34

AB39

AC36

AD32

AE40

AF35

AG31

AH39

AJ36

AK32

AL40

AM35

AP39

AR36

AU40

AA40

H36

VCCIO5

VCCIO6

VCCIO7

VTT_2

-

VCCIO5

VCCIO6

VCCIO7

VTT_2

-

J40

-

L35

-

M39

-

P36

-

R40

-

T31

-

U35

-

V39

-

W32

Y36

-

AA14

AA15

R12

2

3

4

2

3

4

VTT_2

V14

VTT_2

AB14

AB15

AE14

AJ13

AH21

AJ18

AJ19

AJ20

AJ21

VTT_3

VTT_4

4-146

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

LFSC/M80, LFSC/M115 Logic Signal Connections: 1704 fcBGA^{1, 2}(Cont.)

LFSC/M80

LFSC/M115

Ball

Number

Ball

Function

VCCIO

Bank

Dual

Function

Ball

Function

VCCIO

Bank

Dual

Function

AH22

AJ22

AJ23

AJ24

AJ25

AB28

AB29

AE29

AJ30

AA28

AA29

R31

VTT_5

VTT_6

VTT_7

GND

VCC12

NC

5

6

7

-

VTT_5

VTT_6

VTT_7

GND

VCC12

NC

5

6

7

-

V29

Y24

Y26

-

Y8

-

Y35

-

AA16

AA27

AB16

AB27

AF16

AF27

AG17

AG21

G33

G10

M15

L15

-

NC

-

NC

-

NC

-

NC

-

NC

-

NC

-

K16

NC

-

NC

-

J16

NC

-

NC

-

M18

L18

NC

-

NC

-

NC

-

NC

-

M25

L25

NC

-

NC

-

NC

-

NC

-

J27

NC

-

NC

-

K27

NC

-

NC

-

L28

NC

-

NC

-

M28

NC

-

NC

-

1. Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement).

2. The LatticeSC/M80 and LatticeSC/M115 in a 1704-pin package supports a 32-bit MPI interface.

4-147

Pinout Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Thermal Management

Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal

characteristics of a system, Lattice speciﬁes a maximum allowable junction temperature in all device data sheets.

Designers must complete a thermal analysis of their speciﬁc design to ensure that the device and package do not

exceed the junction temperature limits. Refer to the Thermal Management document to ﬁnd the device/package

speciﬁc thermal values.

For Further Information

For further information regarding Thermal Management, refer to the following located on the Lattice website at

www.latticesemi.com.

• Thermal Management document

• Technical Note TN1101 - Power Estimation and Management for LatticeSC Devices

• Power Calculator tool included with Lattice’s ispLEVER design tool, or as a standalone download from

www.latticesemi.com/software

4-148

LatticeSC/M Family Data Sheet

Ordering Information

Data Sheet DS1004

November 2007

Part Number Description

LF XXX XXX XX E PX – X XXXXXX X

LF = Lattice FPGA

Grade

C = Commercial

I = Industrial

Device Family

LatticeSC FPGA

LatticeSCM FPGA

Package¹

SERDES Speed

F256 = 256-ball fpBGA

3GA = 3.8G

F900 = 900-ball fpBGA

FF1020 = 1020-ball Organic fcBGA

FC1152 = 1152-ball Ceramic fcBGA

FC1704 = 1704-ball Ceramic fcBGA

Logic Capacity

15K LUTs

25K LUTs

40K LUTs

FN256 = 256-ball Lead-Free fpBGA

80K LUTs

FN900 = 900-ball Lead-Free fpBGA

115K LUTs

FFN1020 = 1020-ball Lead-Free Organic fcBGA

FCN1152 = 1152-ball Lead-Free Ceramic fcBGA

FCN1704 = 1704-ball Lead-Free Ceramic fcBGA

Supply Voltage

E = 1.2V

Speed Grade

-5 (Slowest)

-6

2

-7 (Fastest)

Predefined Function (LatticeSCM Only)

P1 = Initial MACO Option

1. fpBGA = 1.0mm pitch BGA, fcBGA = 1.0mm flip-chip BGA (organic and ceramic).

2. Not available in the LatticeSC115 and LatticeSCM115 devices.

Ordering Information

Depending on the speed and temperature grade, the device can either be dual marked or single marked. The com-

mercial grade is one speed grade faster than the associated dual marked industrial grade. The slowest commercial

speed grade does not have industrial markings. The markings appear as follows:

LFSC3GA25E

6F900C-5I

XXXXXXXX

LFSC3GA25E

7F900C

XXXXXXXX

or

Temperature Grade

Speed Grade

Single or Dual Mark?

-7

-6

-5

-6

-5

Either OK

Dual Only

Single Only

Either OK

Dual Only

Commercial

Industrial

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

5-1

DS1004 Ordering Information_01.6

Ordering Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Conventional Packaging

Commercial

Part Number

LFSC3GA15E-7F256C

LFSC3GA15E-6F256C

LFSC3GA15E-5F256C

LFSC3GA15E-7F900C

LFSC3GA15E-6F900C

LFSC3GA15E-5F900C

Grade

-7

Package

fpBGA

Balls

256

900

Temp.

COM

LUTs (K)

15.2

-6

15.2

-5

15.2

-7

15.2

-6

15.2

-5

15.2

Part Number

Grade

-7

Package

fpBGA

Balls

256

900

Temp.

COM

LUTs (K)

15.2

LFSCM3GA15EP1-7F256C

LFSCM3GA15EP1-6F256C

LFSCM3GA15EP1-5F256C

LFSCM3GA15EP1-7F900C

LFSCM3GA15EP1-6F900C

LFSCM3GA15EP1-5F900C

-6

15.2

-5

15.2

-7

15.2

-6

15.2

-5

15.2

Part Number

LFSC3GA25E-7F900C

LFSC3GA25E-6F900C

LFSC3GA25E-5F900C

LFSC3GA25E-7FF1020C

LFSC3GA25E-6FF1020C

LFSC3GA25E-5FF1020C

Grade

-7

Package

fpBGA

fcBGA

Balls

900

Temp.

COM

LUTs (K)

25.4

-6

900

25.4

-5

900

25.4

-7

1020

25.4

-6

25.4

-5

25.4

Part Number

Grade

-7

Package

fpBGA

fcBGA

Balls

900

Temp.

COM

LUTs (K)

25.4

LFSCM3GA25EP1-7F900C

LFSCM3GA25EP1-6F900C

LFSCM3GA25EP1-5F900C

LFSCM3GA25EP1-7FF1020C

LFSCM3GA25EP1-6FF1020C

LFSCM3GA25EP1-5FF1020C

-6

900

25.4

-5

900

25.4

-7

1020

25.4

-6

25.4

-5

25.4

Part Number

Grade

-7

Package

fcBGA

Balls

1020

1152

Temp.

COM

LUTs (K)

40.4

LFSC3GA40E-7FF1020C

LFSC3GA40E-6FF1020C

LFSC3GA40E-5FF1020C

LFSC3GA40E-7FC1152C

LFSC3GA40E-6FC1152C

LFSC3GA40E-5FC1152C

-6

40.4

-5

40.4

-7

40.4

-6

40.4

-5

40.4

5-2

Ordering Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Commercial (Cont.)

Part Number

Grade

Package

fcBGA

Balls

1020

1152

Temp.

COM

LUTs (K)

40.4

LFSCM3GA40EP1-7FF1020C

LFSCM3GA40EP1-6FF1020C

LFSCM3GA40EP1-5FF1020C

LFSCM3GA40EP1-7FC1152C

LFSCM3GA40EP1-6FC1152C

LFSCM3GA40EP1-5FC1152C

-7

-6

-5

-7

-6

-5

40.4

Part Number

Grade

-7

Package

fcBGA

Balls

1152

1704

Temp.

COM

LUTs (K)

80.1

LFSC3GA80E-7FC1152C

LFSC3GA80E-6FC1152C

LFSC3GA80E-5FC1152C

LFSC3GA80E-7FC1704C

LFSC3GA80E-6FC1704C

LFSC3GA80E-5FC1704C

-6

80.1

-5

80.1

-7

80.1

-6

80.1

-5

80.1

Part Number

Grade

-7

Package

fcBGA

Balls

1152

1704

Temp.

COM

LUTs (K)

80.1

LFSCM3GA80EP1-7FC1152C

LFSCM3GA80EP1-6FC1152C

LFSCM3GA80EP1-5FC1152C

LFSCM3GA80EP1-7FC1704C

LFSCM3GA80EP1-6FC1704C

LFSCM3GA80EP1-5FC1704C

-6

80.1

-5

80.1

-7

80.1

-6

80.1

-5

80.1

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

COM

LUTs (K)

115.2

LFSC3GA115E-6FC1152C

LFSC3GA115E-5FC1152C

LFSC3GA115E-6FC1704C

LFSC3GA115E-5FC1704C

-5

115.2

-6

115.2

-5

115.2

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

COM

LUTs (K)

115.2

LFSCM3GA115EP1-6FC1152C

LFSCM3GA115EP1-5FC1152C

LFSCM3GA115EP1-6FC1704C

LFSCM3GA115EP1-5FC1704C

-5

115.2

-6

115.2

-5

115.2

5-3

Ordering Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Industrial

Part Number

LFSC3GA15E-6F256I

LFSC3GA15E-5F256I

LFSC3GA15E-6F900I

LFSC3GA15E-5F900I

Grade

-6

Package

fpBGA

Balls

256

900

Temp.

IND

LUTs (K)

15.2

-5

IND

15.2

-6

IND

15.2

-5

IND

15.2

Part Number

Grade

-6

Package

fpBGA

Balls

256

900

Temp.

IND

LUTs (K)

15.2

LFSCM3GA15EP1-6F256I

LFSCM3GA15EP1-5F256I

LFSCM3GA15EP1-6F900I

LFSCM3GA15EP1-5F900I

-5

IND

15.2

-6

IND

15.2

-5

IND

15.2

Part Number

LFSC3GA25E-6F900I

LFSC3GA25E-5F900I

LFSC3GA25E-6FF1020I

LFSC3GA25E-5FF1020I

Grade

-6

Package

fpBGA

fcBGA

Balls

900

Temp.

IND

LUTs (K)

25.4

-5

900

IND

25.4

-6

1020

IND

25.4

-5

IND

25.4

Part Number

Grade

-6

Package

fpBGA

fcBGA

Balls

900

Temp.

IND

LUTs (K)

25.4

LFSCM3GA25EP1-6F900I

LFSCM3GA25EP1-5F900I

LFSCM3GA25EP1-6FF1020I

LFSCM3GA25EP1-5FF1020I

-5

900

IND

25.4

-6

1020

IND

25.4

-5

IND

25.4

Part Number

LFSC3GA40E-6FF1020I

LFSC3GA40E-5FF1020I

LFSC3GA40E-6FC1152I

LFSC3GA40E-5FC1152I

Grade

-6

Package

fcBGA

Balls

1020

1152

Temp.

IND

LUTs (K)

40.4

-5

IND

40.4

-6

IND

40.4

-5

IND

40.4

Part Number

Grade

-6

Package

fcBGA

Balls

1020

1152

Temp.

IND

LUTs (K)

40.4

LFSCM3GA40EP1-6FF1020I

LFSCM3GA40EP1-5FF1020I

LFSCM3GA40EP1-6FC1152I

LFSCM3GA40EP1-5FC1152I

-5

IND

40.4

-6

IND

40.4

-5

IND

40.4

5-4

Ordering Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Industrial (Cont.)

Package

fcBGA

Part Number

LFSC3GA80E-6FC1152I

LFSC3GA80E-5FC1152I

LFSC3GA80E-6FC1704I

LFSC3GA80E-5FC1704I

Grade

-6

Balls

1152

1704

Temp.

IND

LUTs (K)

80.1

-5

fcBGA

IND

80.1

-6

fcBGA

IND

80.1

-5

fcBGA

IND

80.1

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

IND

LUTs (K)

80.1

LFSCM3GA80EP1-6FC1152I

LFSCM3GA80EP1-5FC1152I

LFSCM3GA80EP1-6FC1704I

LFSCM3GA80EP1-5FC1704I

-5

IND

80.1

-6

IND

80.1

-5

IND

80.1

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

IND

LUTs (K)

115.2

LFSC3GA115E-6FC1152I

LFSC3GA115E-5FC1152I

LFSC3GA115E-6FC1704I

LFSC3GA115E-5FC1704I

-5

IND

115.2

-6

IND

115.2

-5

IND

115.2

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

IND

LUTs (K)

115.2

LFSCM3GA115EP1-6FC1152I

LFSCM3GA115EP1-5FC1152I

LFSCM3GA115EP1-6FC1704I

LFSCM3GA115EP1-5FC1704I

-5

IND

115.2

-6

IND

115.2

-5

IND

115.2

5-5

Ordering Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Lead-Free Packaging

Commercial

Part Number

LFSC3GA15E-7FN256C

LFSC3GA15E-6FN256C

LFSC3GA15E-5FN256C

LFSC3GA15E-7FN900C

LFSC3GA15E-6FN900C

LFSC3GA15E-5FN900C

Grade

-7

Package

fpBGA

Balls

256

900

Temp.

COM

LUTs (K)

15.2

-6

15.2

-5

15.2

-7

15.2

-6

15.2

-5

15.2

Part Number

Grade

-7

Package

fpBGA

Balls

256

900

Temp.

COM

LUTs (K)

15.2

LFSCM3GA15EP1-7FN256C

LFSCM3GA15EP1-6FN256C

LFSCM3GA15EP1-5FN256C

LFSCM3GA15EP1-7FN900C

LFSCM3GA15EP1-6FN900C

LFSCM3GA15EP1-5FN900C

-6

15.2

-5

15.2

-7

15.2

-6

15.2

-5

15.2

Part Number

LFSC3GA25E-7FN900C

LFSC3GA25E-6FN900C

LFSC3GA25E-5FN900C

LFSC3GA25E-7FFN1020C

LFSC3GA25E-6FFN1020C

LFSC3GA25E-5FFN1020C

Grade

-7

Package

fpBGA

fcBGA

Balls

900

Temp.

COM

LUTs (K)

25.4

-6

900

25.4

-5

900

25.4

-7

1020

25.4

-6

25.4

-5

25.4

Part Number

Grade

-7

Package

fpBGA

fcBGA

Balls

900

Temp.

COM

LUTs (K)

25.4

LFSCM3GA25EP1-7FN900C

LFSCM3GA25EP1-6FN900C

LFSCM3GA25EP1-5FN900C

LFSCM3GA25EP1-7FFN1020C

LFSCM3GA25EP1-6FFN1020C

LFSCM3GA25EP1-5FFN1020C

-6

900

25.4

-5

900

25.4

-7

1020

25.4

-6

25.4

-5

25.4

Part Number

Grade

-7

Package

fcBGA

Balls

1020

1152

Temp.

COM

LUTs (K)

40.4

LFSC3GA40E-7FFN1020C

LFSC3GA40E-6FFN1020C

LFSC3GA40E-5FFN1020C

LFSC3GA40E-7FCN1152C

LFSC3GA40E-6FCN1152C

LFSC3GA40E-5FCN1152C

-6

40.4

-5

40.4

-7

40.4

-6

40.4

-5

40.4

5-6

Ordering Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Commercial (Cont.)

Part Number

Grade

Package

fcBGA

Balls

1020

1152

Temp.

COM

LUTs (K)

40.4

LFSCM3GA40EP1-7FFN1020C

LFSCM3GA40EP1-6FFN1020C

LFSCM3GA40EP1-5FFN1020C

LFSCM3GA40EP1-7FCN1152C

LFSCM3GA40EP1-6FCN1152C

LFSCM3GA40EP1-5FCN1152C

-7

-6

-5

-7

-6

-5

40.4

Part Number

Grade

-7

Package

fcBGA

Balls

1152

1704

Temp.

COM

LUTs (K)

80.1

LFSC3GA80E-7FCN1152C

LFSC3GA80E-6FCN1152C

LFSC3GA80E-5FCN1152C

LFSC3GA80E-7FCN1704C

LFSC3GA80E-6FCN1704C

LFSC3GA80E-5FCN1704C

-6

80.1

-5

80.1

-7

80.1

-6

80.1

-5

80.1

Part Number

Grade

-7

Package

fcBGA

Balls

1152

1704

Temp.

COM

LUTs (K)

80.1

LFSCM3GA80EP1-7FCN1152C

LFSCM3GA80EP1-6FCN1152C

LFSCM3GA80EP1-5FCN1152C

LFSCM3GA80EP1-7FCN1704C

LFSCM3GA80EP1-6FCN1704C

LFSCM3GA80EP1-5FCN1704C

-6

80.1

-5

80.1

-7

80.1

-6

80.1

-5

80.1

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

COM

LUTs (K)

115.2

LFSC3GA115E-6FCN1152C

LFSC3GA115E-5FCN1152C

LFSC3GA115E-6FCN1704C

LFSC3GA115E-5FCN1704C

-5

115.2

-6

115.2

-5

115.2

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

COM

LUTs (K)

115.2

LFSCM3GA115EP1-6FCN1152C

LFSCM3GA115EP1-5FCN1152C

LFSCM3GA115EP1-6FCN1704C

LFSCM3GA115EP1-5FCN1704C

-5

115.2

-6

115.2

-5

115.2

5-7

Ordering Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Industrial

Part Number

LFSC3GA15E-6FN256I

LFSC3GA15E-5FN256I

LFSC3GA15E-6FN900I

LFSC3GA15E-5FN900I

Grade

-6

Package

fpBGA

Balls

256

900

Temp.

IND

LUTs (K)

15.2

-5

IND

15.2

-6

IND

15.2

-5

IND

15.2

Part Number

Grade

-6

Package

fpBGA

Balls

256

900

Temp.

IND

LUTs (K)

15.2

LFSCM3GA15EP1-6FN256I

LFSCM3GA15EP1-5FN256I

LFSCM3GA15EP1-6FN900I

LFSCM3GA15EP1-5FN900I

-5

IND

15.2

-6

IND

15.2

-5

IND

15.2

Part Number

LFSC3GA25E-6FN900I

LFSC3GA25E-5FN900I

LFSC3GA25E-6FFN1020I

LFSC3GA25E-5FFN1020I

Grade

-6

Package

fpBGA

fcBGA

Balls

900

Temp.

IND

LUTs (K)

25.4

-5

900

IND

25.4

-6

1020

IND

25.4

-5

IND

25.4

Part Number

Grade

-6

Package

fpBGA

fcBGA

Balls

900

Temp.

IND

LUTs (K)

25.4

LFSCM3GA25EP1-6FN900I

LFSCM3GA25EP1-5FN900I

LFSCM3GA25EP1-6FFN1020I

LFSCM3GA25EP1-5FFN1020I

-5

900

IND

25.4

-6

1020

IND

25.4

-5

IND

25.4

Part Number

Grade

-6

Package

fcBGA

Balls

1020

1152

Temp.

IND

LUTs (K)

40.4

LFSC3GA40E-6FFN1020I

LFSC3GA40E-5FFN1020I

LFSC3GA40E-6FCN1152I

LFSC3GA40E-5FCN1152I

-5

IND

40.4

-6

IND

40.4

-5

IND

40.4

Part Number

Grade

-6

Package

fcBGA

Balls

1020

1152

Temp.

IND

LUTs (K)

40.4

LFSCM3GA40EP1-6FFN1020I

LFSCM3GA40EP1-5FFN1020I

LFSCM3GA40EP1-6FCN1152I

LFSCM3GA40EP1-5FCN1152I

-5

IND

40.4

-6

IND

40.4

-5

IND

40.4

5-8

Ordering Information

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Industrial (Cont.)

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

IND

LUTs (K)

80.1

LFSC3GA80E-6FCN1152I

LFSC3GA80E-5FCN1152I

LFSC3GA80E-6FCN1704I

LFSC3GA80E-5FCN1704I

-5

IND

80.1

-6

IND

80.1

-5

IND

80.1

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

IND

LUTs (K)

80.1

LFSCM3GA80EP1-6FCN1152I

LFSCM3GA80EP1-5FCN1152I

LFSCM3GA80EP1-6FCN1704I

LFSCM3GA80EP1-5FCN1704I

-5

IND

80.1

-6

IND

80.1

-5

IND

80.1

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

IND

LUTs (K)

115.2

LFSC3GA115E-6FCN1152I

LFSC3GA115E-5FCN1152I

LFSC3GA115E-6FCN1704I

LFSC3GA115E-5FCN1704I

-5

IND

115.2

-6

IND

115.2

-5

IND

115.2

Part Number

Grade

-6

Package

fcBGA

Balls

1152

1704

Temp.

IND

LUTs (K)

115.2

LFSCM3GA115EP1-6FCN1152I

LFSCM3GA115EP1-5FCN1152I

LFSCM3GA115EP1-6FCN1704I

LFSCM3GA115EP1-5FCN1704I

-5

IND

115.2

-6

IND

115.2

-5

IND

115.2

5-9

LatticeSC/M Family Data Sheet

Supplemental Information

Data Sheet DS1004

January 2008

For Further Information

For further information about the ﬂexiPCS see the LatticeSC/M Family ﬂexiPCS Data Sheet available on the Lattice

Semiconductor website at www.latticesemi.com.

A variety of technical notes for the LatticeSC/M family are also available on the Lattice Semiconductor website at

www.latticesemi.com.

• LatticeSC PURESPEED I/O Usage Guide (TN1088)

• LatticeSC PURESPEED I/O Adaptive Input Logic User Guide (TN1158)

• LatticeSC sysCLOCK and PLL/DLL User’s Guide (TN1098)

• On-Chip Memory Usage Guide for LatticeSC Devices (TN1094)

• LatticeSC DDR/DDR2 SDRAM Memory Interface User’s Guide (TN1099)

• LatticeSC QDRII/QDRII+ SRAM Memory Interface User’s Guide (TN1096)

• LatticeSC sysCONFIG Usage Guide (TN1080)

• LatticeSC MPI/System Bus (TN1085)

• SPI Serial Flash Programming Using ispJTAG in LaticeSC Devices (TN1100)

• Power Estimation and Management for LatticeSC Devices (TN1101)

• LatticeSC SERDES Jitter (TN1084)

• LatticeSC FPGAs: Implementing 3.3V Interfaces in 2.5V VCCIO Banks (TN1110)

• Lattice PCI Express Demo User Guide (TN1123)

• LatticeSC ﬂexiPCS/SERDES Design Guide (TN1145)

• Temperature Sensing Diode in LatticeSC Devices (TN1115)

• SPI4.2 Interoperability with ORSPI4 in LatticeSC Devices (TN1116)

• LatticeSC/M Hold Time Optimization (TN1117)

For further information on Interface standards refer to the following websites:

• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org

• Hyper Transport: www.hypertransport.org

• Optical Interface (SPI-4.2, XSBI, CSIX and XGMII): www.oiforum.com

• RAPIDIO: www.rapidio.org

• PCI/PCIX: ww.pcisig.com

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

6-1

DS 1004 Further Information_01.2

LatticeSC/M Family Data Sheet

Revision History

June 2008

Data Sheet DS1004

Date

Version

01.0

Section

—

Change Summary

Initial release.

February 2006

March 2006

01.1

Introduction

Architecture

SC25 1020 I/O count changed to 476.

Changed ROM 16X4 to ROM 16X2.

Changed “X2 or X4” to “DIV2 or DIV4”.

Added Global Set/Reset Section.

DC and Switching

Characteristics

Added notes 5 and 6 to Recommended Operating Conditions table.

Added Power Supply Ramp Rates table.

Removed -5 and -6 speed grades from Typical Building Block Perfor-

mance table.

Added Input Delay Timing table.

Added Synchronous GSR Timing table.

Pinout Information

Expanded PROBE_VCC and PROBE_GND description.

Removed A-RXREFCLKP_[L/R] from Signal Description table.

Added RESP_[ULC/URC] to Signal Description table.

Added notes 1 and 2 to Signal Description table.

Changed number of NCs to 28.

Changed number of SERDES (signal + power supply) to 74.

Removed RESP balls from NC list (B2, C2, B29, C29).

Added note to VTT table.

Changed RxRefclk (B2 and C2) to NC.

Added RESP_ULC.

Added RESP_URC.

Changed RxRefclk (B29 and C29) to NC.

Changed SERDES min bandwidth from 622 Mbps to 600 Mbps.

Changed max SERDES bandwidth from 3.4 Gbps to 3.8 Gbps.

June 2006

01.2

Introduction

Architecture

Corrected number of package I/Os for the SC80 and SC115 1704 pin

packages.

Updated speed performance for typical functions with ispLEVER 6.0

values.

Changed “When these pins are not used they should be left uncon-

nected.” with “Unused VTT pins should be connected to GND if the

internal or external VCMT function is not used in the bank. If the internal

or external VCMT function for differential input termination is used, the

VTT pins should be unconnected and allowed to ﬂoat.”

Added “SERDES Power Supply Sequencing Requirements” section.

Changed total bandwidth per quad from 13.6 Gbps to 15.2 Gbps.

Added the accuracy of the temperature-sensing diode to be typically +/-

10 °C. Also referred to a temperature-sensing diode application note for

more information.

DC and Switching

Characteristics

Changed “CTAP” to “internal or external VCMT”.

Changed VCC12 parameter to include VDDP, VDDTX and VDDRX.

Changed typical values to match ispLEVER 6.0 Power Calculator.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

7-1

DS 1004 Revision History

Revision History

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Date

Version

Section

Change Summary

June 2006

(cont.)

01.2

(cont.)

DC and Switching

Characteristics (cont.)

Updated Typical Building Block Performance with ispLEVER 6.0 values.

Updated LatticeSC External Switching Characteristics with ispLEVER

6.0 values.

Updated Lattice SC Internal Timing Parameters with ispLEVER 6.0 val-

ues.

Updated Lattice SC Family Timing Adders with ispLEVER 6.0 values

Changed % spread from 1 to 0.5 min and from 3 to 1.5 max.

Changed conditions to refer to “with multiplication” and “without multipli-

cation”.

Changed the formula for t

representation).

with multiplication (same result, different

OPJIT

Pinout Information

Expanded deﬁnition of NC.

Expanded deﬁnition of GND.

Expanded deﬁnition of VTT_x.

Expanded deﬁnition of VCC12.

Added accuracy of TEMP pin.

Added RESPN_[ULC/URC].

Updated Pin Information Summary with additional devices and pack-

ages.

Added additional devices and packages pinouts.

Removed Power Supply and NC connections table

Removed VTT table

Removed LFSC25 Logic Signal Connections: 900-Ball ffBGA1 table

Changed all VDDP, VDDTX and VDDRX to VCC12.

Ordering Information Added dual marking.

Added lead free packaging information to part number description.

August 2006

01.3

Introduction

Added SC40 1152 information to Table 1-1.

Updated Table 1-3 with ispLEVER 6.0 SP1 results.

Added SSTL18 II to Table 2-8.

Architecture

Changed Table 2-10 VCCIO column to “N/A” for LVDS, mini-LVDS,

BLVDS25, MLVDS25, HYPT and RSDS.

Changed Hypertransport performance to 700 MHz (1400 Mbps) in

Table 2-11.

Changed SPI4.2 performance to 500 MHz (1000 Mbps) in Table 2-11

Added “On packages that include PROBE_GND, the most accurate

measurements will occur between the TEMP pin and the PROBE_GND

pin. On packages that do not include PROBE_GND, measurements

should be made between the TEMP pin and board ground.”

Added VCCIO of 2.5 V for LVPECL33 in table 2-9.

DC and Switching

Characteristics

Updated Typical Building Block Performance with ispLEVER 6.0 SP1

results.

Updated Initialization and Standby Supply Current table to break out

ICC and ICC12.

Updated LatticeSC External Switching Characteristics with ispLEVER

6.0 SP1 results.

Updated LatticeSC Internal Timing Parameters with ispLEVER 6.0 SP1

results.

7-2

Revision History

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Date

Version

Section

Change Summary

August 2006

(cont.)

01.3

(cont.)

DC and Switching

Characteristics

(cont.)

Updated LatticeSC Family Timing Adders with ispLEVER 6.0 SP1

results

Updated PLL Timing Parameters based on PDE testing results

Removed RDDATA parameter from sysCONFIG readback timing table

Changed TDO/RDDATA to TDO

Multiple

Pinout Information

Removed all MPI signals from SC15 256 pin package Dual Function

Column

Added note to SC15, SC25 900 pin package that the package supports

a 16 bit MPI

Added note that pin D3 in an SC15 and SC25 900 pin package should

not be used for single-ended outputs

Added note that pin D28 in an SC15 and SC25 900 pin package should

not be used for single-ended outputs

Added note to SC25 1020 pin package that the package supports a 16

bit MPI

Added note to SC80 1152 pin package that the package supports a 32

bit MPI

Added note to SC80 1704 pin package that the package supports a 32

bit MPI

Ordering Information Changed “fcBGA” for the 1020 packages to “ffBGA”

November 2006

01.4

Introduction

LatticeSC Family Selection Guide table – I/O count for SC80 device,

1704 fcBGA package changed to 904/32. I/O count for SC115 device,

1704 fcBGA package changed to 942/32.

DC and Switching

Characteristics

DC Electrical Characteristics table – Updated the initialization and

standby supply current values.

DC Electrical Characteristics table – Updated the sysCONFIG Master

Parallel mode RCLK low and RCLK high time speciﬁcations.

DC Electrical Characteristics table – Updated VCCIO values for

LVPECL33 I/Os.

Pin Information

Pin Information Summary table - Changed number of single ended user

I/Os from 906 to 904 for 1704 fcBGA.

Removed the single-ended only output restriction on pins D3 and D28

in an SC15 and SC25 900 pin package.

Ordering Information Ordering Information tables - Changed number of I/Os from 906 to 904

for 1704 fcBGA.

Added ordering part numbers for LatticeSC/SCM 40K and 115K LUT

devices.

Added lead-free ordering part numbers.

Multiple

Changed number of available SC80 I/O from 906 to 904.

Changed number of available SC115 I/O from 944 to 942.

Added EBR Asynchronous Reset section.

January 2007

February 2007

March 2007

01.4a

01.4b

01.5

Architecture

Updated EBR Asynchronous Reset section.

Added EBR asynchronous reset clariﬁcation

Clariﬁed that differential drivers are not supported in banks 1, 4 and 5

DC and Switching

Characteristics

Added clariﬁcation for the description of the junction temperature speci-

ﬁcation in the Absolute Maximum Ratings section.

Updated Initialization and Standby Current table.

Updated LatticeSC External Switching Characteristics with ispLEVER

6.1 SP1 results.

7-3

Revision History

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Date

Version

Section

Change Summary

March 2007

(cont.)

01.5

(cont.)

DC and Switching

Characteristics (cont.) results.

Updated LatticeSC Internal Timing Parameters with ispLEVER 6.1 SP1

Updated t

and t

speciﬁcations.

FDEL

CDEL

Updated LatticeSC Family Timing Adders with ispLEVER 6.1 SP1

results.

Updated PLL speciﬁcations to expand frequency range down to 2 MHz

and break out jitter for the different ranges.

Added footnote to sysCLOCK PLL Timing table specifying the condi-

tions for the jitter measurements.

Added t

speciﬁcation to sysCLOCK DLL Timing table.

DLL

Added footnote to sysCLOCK DLL Timing table specifying the condi-

tions for the jitter measurements.

Added sysCONFIG Master Parallel Conﬁguration Mode and sysCON-

FIG SPI Port to LatticeSC sysCONFIG Port Timing table.

Pin Information

General

Updated Pin Information Summary with SC40 information.

Updated LFSC25 Logic Signal Connections: FF1020 with SC40 infor-

mation.

Updated LFSC80 Logic Signal Connections: FC1152 with SC40 infor-

mation.

August 2007

01.6

Changed references of "HDC" to "HDC/SI".

Changed references of "LDCN" to "LDCN/SCS".

Changed references of "BUSYN/RCLK" to "BUSYN/RCLK/SCK".

Changed references of "RDCFGN" to "TSALLN".

Changed references of "TDO/RDDATA" to "TDO".

Updated text in Ripple Mode section.

Architecture

Added information to Global Set/Reset.

Added information for Spread Spectrum Clocking

Modiﬁed information for PLL/DLL Cascading. DLL to PLL is now sup-

ported.

Modiﬁed AIL Block text and ﬁgure.

Modiﬁed Figure 2-20 DDR/Shift Register Block.

Added Information to Hot Socketing.

Added new information for I/O Architecture Rules.

Added information to SERDES Power Supply Sequencing Require-

ments.

DC and Switching

Characteristics

Added footnote to Hot Socketing Speciﬁcations table.

Modiﬁed Initialization and Standby Supply Current table.

Modiﬁed GSR Timing table.

Modiﬁed sysCLOCK DLL Timing table to include I

DUTY.

Deleted Readback Timing information from sysCONFIG Port Timing

table.

Modiﬁed data in External Switching Characteristics table.

Pin Information

Added information to the Signal Descriptions table for HDC/SI, LDCN/

SCS.

Added footnote to Signal Descriptions table.

Modiﬁed Description for signal BUSYN/RCLK/SCK.

Modiﬁed data in Pin Information Summary and device-speciﬁc Pinout

Information tables.

7-4

Revision History

LatticeSC/M Family Data Sheet

Lattice Semiconductor

Date

Version

Section

Change Summary

September 2007

01.7

Pinout Information

Added Thermal Management text section.

Updated title list.

Supplemental

Information

November 2007

January 2008

01.8

01.9

Ordering Information Removed -7 speed grade information for 115K LUT devices in the

Ordering Information tables.

Introduction

Architecture

Corrections/Additions to memory controller list (Tables 1-2).

AIL Overview – Modiﬁed power used by AIL block.

PURESPEED I/O Buffer Banks – Modiﬁed VTT termination info. Added

info about complimentary drivers for all banks.

Supported Source Synchronous Interfaces – Modiﬁed data for DDRII in

Table 2-11.

DC and Switching

Characteristics

Recommended Operating Conditions – Changed footnote 3.

Initialization and Standby Supply Current – Inserted a paragraph with

info regarding the table. Also updated the table.

Typical Building Block Function Performance – Added

VCC=1.2V=1.2V+/-5% above Pin to Pin Performance table.

LatticeSC External Switching Characteristics – Added

VCC=1.2V=1.2V+/-5% above table. Reworded footnote 3.

LatticeSC Family Timing Adders – Added VCC=1.2V=1.2V+/-5% above

table.

LatticeSC Internal Timing Parameters – Added VCC=1.2V=1.2V+/-5%

above table. Reworded footnote 1.

GSR Timing – Added a new table for Internal System Bus Timing after

GSR Timing.

LatticeSC sysCONFIG Port Timing – Corrected sysCONFIG SPI Port

information.

Pinout Information

Signal Descriptions – Modiﬁed info for VTT_x, PROBE_VCC, and

PROBE_GND. Modiﬁed info for [LOC]_DLL[T,C]_IN[C,D,E,F].

Supplemental

Information

Updated list of technical notes, added reference to LatticeSC/M

ﬂexiPCS Data Sheet.

March 2008

June 2008

02.0

02.1

DC and Switching

Characteristics

Updated Internal Timing Parameters table.

Updated Read Mode timing diagram.

Updated Read Mode with Input Registers Only timing diagram.

Data sheet status changed from preliminary to ﬁnal.

Removed Read-Before-Write sysMEM EBR mode.

Updated LatticeSC/M External Switching Characteristics table.

—

Architecture

DC and Switching

Characteristics

Updated LatticeSC/M Internal Timing Parameters table.

Removed Read-Before-Write sysMEM EBR mode.

7-5


型号：	LFSCM3GA15KLUTSEP1FF1020C
厂家：	LATTICE SEMICONDUCTOR
描述：	LatticeSC/M Family Data Sheet 的LatticeSC / M系列数据手册
文件：	总237页 (文件大小：2543K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LFSCM3GA15KLUTSEP1FF1020C [LATTICE]

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