LFX125B-03F256C [LATTICE]
Field Programmable Gate Array, 484 CLBs, 139000 Gates, 320MHz, 1936-Cell, CMOS, PBGA256, FPBGA-256;型号: | LFX125B-03F256C |
厂家: | LATTICE SEMICONDUCTOR |
描述: | Field Programmable Gate Array, 484 CLBs, 139000 Gates, 320MHz, 1936-Cell, CMOS, PBGA256, FPBGA-256 栅 可编程逻辑 |
文件: | 总119页 (文件大小:1504K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ispXPGA® Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue select devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
LFX125B
Ordering Part Number
LFX125B-03F256C
LFX125B-03FN256C
LFX125B-04F256C
LFX125B-04FN256C
LFX125B-05F256C
LFX125B-05FN256C
LFX125B-03F516C
LFX125B-04F516C
LFX125B-05F516C
LFX125C-03F256C
LFX125C-03FN256C
LFX125C-04F256C
LFX125C-04FN256C
LFX125C-03F516C
LFX125C-04F516C
LFX200B-03F256C
LFX200B-03FN256C
LFX200B-04F256C
LFX200B-04FN256C
LFX200B-05F256C
LFX200B-05FN256C
LFX200B-03F516C
LFX200B-04F516C
LFX200B-05F516C
LFX200C-03F256C
LFX200C-03FN256C
LFX200C-04F256C
LFX200C-04FN256C
LFX200C-03F516C
LFX200C-04F516C
Product Status
Discontinued
Reference PCN
PCN#09-10
LFX125C
LFX200B
LFX200C
Discontinued
PCN#09-10
Active / Orderable
Discontinued
Discontinued
PCN#09-10
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
LFX500B
Ordering Part Number
LFX500B-03F516C
LFX500B-04F516C
LFX500B-05F516C
LFX500B-03F900C
LFX500B-03FN900C
LFX500B-04F900C
LFX500B-04FN900C
LFX500B-05F900C
LFX500B-05FN900C
LFX500C-03F516C
LFX500C-04F516C
LFX500C-03F900C
LFX500C-03FN900C
LFX500C-04F900C
LFX500C-04FN900C
LFX1200B-03FE680C
LFX1200B-04FE680C
LFX1200B-05FE680C
LFX1200B-03F900C
LFX1200B-04F900C
LFX1200B-05F900C
LFX1200C-03FE680C
LFX1200C-04FE680C
LFX1200C-03F900C
LFX1200C-04F900C
LFX125EB-03F256C
LFX125EB-03FN256C
LFX125EB-04F256C
LFX125EB-04FN256C
LFX125EB-05F256C
LFX125EB-05FN256C
LFX125EB-03F256I
LFX125EB-03FN256I
LFX125EB-04F256I
LFX125EB-04FN256I
LFX125EB-03F516C
LFX125EB-04F516C
LFX125EB-05F516C
LFX125EB-03F516I
LFX125EB-04F516I
LFX125EC-03F256C
LFX125EC-03FN256C
LFX125EC-04F256C
LFX125EC-04FN256C
LFX125EC-03F256I
LFX125EC-03FN256I
Product Status
Discontinued
Reference PCN
PCN#09-10
LFX500C
Discontinued
PCN#09-10
LFX1200B
LFX1200C
Discontinued
Discontinued
PCN#03A-10
PCN#03A-10
Active / Orderable
LFX125EB
Discontinued
Discontinued
PCN#09-10
PCN#09-10
LFX125EC
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
Ordering Part Number
LFX125EC-03F516C
LFX125EC-04F516C
LFX125EC-03F516I
LFX200EB-03F256C
LFX200EB-03FN256C
LFX200EB-04F256C
LFX200EB-04FN256C
LFX200EB-05F256C
LFX200EB-05FN256C
LFX200EB-03F256I
LFX200EB-03FN256I
LFX200EB-04F256I
LFX200EB-04FN256I
LFX200EB-03F516C
LFX200EB-04F516C
LFX200EB-05F516C
LFX200EB-03F516I
LFX200EB-04F516I
LFX200EC-03F256C
LFX200EC-03FN256C
LFX200EC-04F256C
LFX200EC-04FN256C
LFX200EC-03F256I
LFX200EC-03FN256I
LFX200EC-03F516C
LFX200EC-04F516C
LFX200EC-03F516I
LFX500EB-03F516C
LFX500EB-04F516C
LFX500EB-05F516C
LFX500EB-03F516I
LFX500EB-04F516I
LFX500EB-03F900C
LFX500EB-03FN900C
LFX500EB-04F900C
LFX500EB-04FN900C
LFX500EB-05F900C
LFX500EB-05FN900C
LFX500EB-03F900I
LFX500EB-03FN900I
LFX500EB-04F900I
LFX500EB-04FN900I
LFX500EC-03F516C
LFX500EC-04F516C
LFX500EC-03F516I
Product Status
Discontinued
Reference PCN
LFX125EC
(Cont’d)
PCN#09-10
Active / Orderable
LFX200EB
Discontinued
Discontinued
PCN#09-10
PCN#09-10
LFX200EC
LFX500EB
Discontinued
PCN#09-10
LFX500EC
Discontinued
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
Ordering Part Number
LFX500EC-03F900C
LFX500EC-03FN900C
LFX500EC-04F900C
LFX500EC-04FN900C
LFX500EC-03F900I
Product Status
Discontinued
Reference PCN
LFX500EC
(Cont’d)
PCN#09-10
LFX500EC-03FN900I
LFX1200EB-03FE680C
LFX1200EB-04FE680C
LFX1200EB-05FE680C
LFX1200EB-03FE680I
LFX1200EB-04FE680I
LFX1200EB-03F900C
LFX1200EB-04F900C
LFX1200EB-05F900C
LFX1200EB-03F900I
LFX1200EB-04F900I
LFX1200EC-03FE680C
LFX1200EC-04FE680C
LFX1200EC-03FE680I
LFX1200EC-03F900C
LFX1200EC-04F900C
LFX1200EC-03F900I
LFX1200EB
LFX1200EC
Discontinued
Discontinued
PCN#03A-10
PCN#03A-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
®
ispXPGA Family
February 2010
Data Sheet DS1026
• Microprocessor configuratiinterface
Non-volatile, Infinitely Reconfigurable
• Instant-on - Powers up in microseconds via
on-chip E2CMOS® based memory
• Program E2CMOS while perating from SRAM
Eight sysCLOCK™ Phase Lockd Loops
(PLLs) for Clock Management
• True PLL technogy
• No external configuration memory
• Excellent design security, no bit stream to intercept
• Reconfigure SRAM based logic in milliseconds
• 10MHz to 320MHz peratin
• Clock muplication adivision
• Phase austmen
High Logic Density for System-level
Integration
• 139K to 1.25M functional gates
• 160 to 496 I/O
• Shift clocin 250s steps
sysI™ fr High System Perfo
• Hispeememory supprt througTL and
HST
• 1.8V, 2.5V, and 3.3V V operation
CC
• Up to 414Kb sysMEM™ embedded memory
High Performance Programmable Function
Unit (PFU)
• Adced buses supportehrouh PCI, GTL+,
LVDS, BLVDS, and LVECL
• Standard logic upportethrough LVTTL,
LVCMOS 3.3, 2.5 nd 1.
• 5V tolerant I/for LVOS 3.3 and LVTTL
interfa
• Programable drive strength for series termination
• Progmmale bus maintenance
• Four LUT-4 per PFU supports wide and narrow
functions
• Dual flip-flops per LUT-4 for extensive pip
• Dedicated logic for adders, multipliers,
ers, and counters
Flexible Memory Resources
• Multiple sysMEM Embedded M Blocks
– Single port, Dual port, and FIO operation
• 64-bit distributed memoeach PF
– Single port, Doube port, FIFO, and Shift
Register operatio
To Optios Available
• Hgh-performance sysHSI (standard part number)
• Lowcost, no sysHSI (“E-Series”)
ysHSI™ Capability for Ultra Fast Serial
mmunications
Flexible Programming, Reconfiguration,
and Testing
• Up to 800Mbps performance
• Up to 20 channels per device
• Supports IEEE 32 an1149.1
• Built in Clock Data Recovery (CDR) and
Serialization and De-serialization (SERDES)
Table 1. ispXPGA Family Selection Guide
ispXPG125/E
ispXPGA 200/E
ispXPGA 500/E
476K
1764
ispXPGA 1200/E3
Funcnal ates
PUs
19K
484
210K
676
1.25M
3844
15376
30.7K
414K
246K
90
LUT-4s
1936
3.8K
92K
2704
5.4K
111K
43K
7056
ogic F
14.1K
184K
112K
40
syM Memory
Distributed Memor
EBR
30K
20
24
sysHSI Channels1
4
8
12
20
User I/O
160/176
160/208
336
496
Packaging
256 fpBGA
516 fpBGA2
256 fpBGA
516 fpBGA2
516 fpBGA2
900 fpBGA
680 fpSBGA
900 fpBGA
1. “E-Series” does not support sysHSI.
2. FH516 package was converted to F516 via PCN #09A-08.
3. Discontinued via PCN #03A-10.
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1026_15.0
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Family Overview
The ispXPGA family of devices provides the ideal vehicle for the creation of high-performance logic designs that
are both non-volatile and infinitely re-programmable. Other FPGA solutions force a compromise, being either re-
programmable or non-volatile. This family couples this capability with a mainstream architecture containing the fea-
tures required for today’s system-level design.
The ispXPGA family is available in two options. The standard device supports sysHSI capiy for tra fast serial
communications while the lower-cost “E-Series” supports the same high-performance FPGA fabric ithout the sys-
HSI Block.
Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA amily with non-volatile capability.
These allow logic to be functional microseconds after power is applied, allwing easy inerfacing in many applica-
tions. This capability also means that expensive external configuration memries arnot required ant designs
can be secured from unauthorized read back. Internal SRAM cells allw the devicto be infiniteured if
desired. Both the SRAM and E2CMOS cells can be programmed anverid through the IEEE 153stan-
dard. Additionally, the SRAM cells can be configured and read-back rough he sysCONFI™ periphport.
The family spans the density and I/O range required for thmajoritooday’s logic design39K t1.25M func-
tional gates and 160 to 496 I/O. The devices are availabe for operation from 1.8V, 2.5and 3V power supplies,
providing easy integration into the overall system.
System-level design needs are met through torpoton of sysMEduaort memory blocks, sysIO
advanced I/O support, and sysCLOCK Phase ops (PLLs). High-speeserial communications are sup-
ported through multiple sysHSI blocks, which prck data recoverDd serialization/de-serialization
(SERDES).
The ispLEVER™ design tool from Ltticallows easy implemention of digns using the ispXPGA product. Syn-
thesis library support is available for majologic synthesis tools. Te ispLEVER tool takes the output from these
common synthesis packages nd place and routes the dign in thispXPGA product. The tool supports floor
planning and the managemet of other constraints within the device. The tool also provides outputs to common
timing analysis tools for tming nalysi
To increase designerodtivity, Lattice providriety f pre-designed modules referred to as IP cores for the
ispXPGA product. TheIP cors allow desigcentrate on the unique portions of their design while using
pre-designed blocks to iplement standard fuch as bus interfaces, standard communication interfaces,
and memory ntrollers.
Througthe use oavanced technolgy and novative architecture the ispXPGA FPGA devices provide design-
ers wexellent speed performce. Ahougdesign dependent, many typical designs can run at over 150MHz.
Certain signcan run at oer 300MHz. Table 2 details the performance of several building blocks commonly
used by lodesigners.
Table 2spXPGA Speed Pformance for Typical Building Blocks
Function
nch MUX
Performance
150 MHz
125 MHz
225 MHz
290 MHz
360 MHz
Asynch Demultiplexer
8 x 8 2-LL Pipelined Multiplier
32-bit Up/Down Counter
32-bit Shift Register
2
Lattice Semiconductor
ispXPGA Family Data Sheet
Architecture Overview
The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units
(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-
uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO
blocks, each of which includes one input and output buffer. On two sides of the device, betwn the PICs and the
sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture llows signers to eas-
ily implement their designs, since any logic function can be placed in any section of the devi.
The PFUs contain the basic building blocks to create logic, memory, arithmetic, d reister functions. They are
optimized for speed and flexibility allowing complex designs to be implemented quicand efciently.
The PICs interface the PFUs and EBRs to the external pins of the device. hey allow thsignals to be registered
quickly to minimize setup times for high-speed designs. They also allow cnnectiodirectly to the ent logic
elements for fast access to combinatorial functions.
The sysMEM EBRs are large, fast memory elements that can be coigureas RAM, ROMFIFO, aer stor-
age types. They are designed to facilitate both single and dualort mmory for high-speeapplations
These three components of the architecture are interconected via a high-speed, flexie routg aay. The routing
array consists of Variable Length Interconnect (VLI) linbeeen the PICs, PFUs, and BRs. here is additional
routing available to the PFU for feedback and direct routinf sigals to adjacent FUs or Cs.
The sysIO blocks consist of configurable input buffers connected direly to the PICs. These buffers can
be configured to interface with 16 different I/O sThis allows thPGto interface with other devices
without the need for external transceivers.
The sysHSI blocks provide the necsary components to allothe isPGA device to transfer data at up to
800Mbps using the LVDS standard. Thescomponents inclue sealizing, de-serializing, and clock data recovery
(CDR) logic.
The sysCLOCK blocks proviclock ultiplication/divion, clok distribution, delay compensation, and increased
performance through thuse oPLL rcuitry that manipates thglobal clocks. There is one sysCLOCK block for
each global clock trein thdevice.
3
Lattice Semiconductor
ispXPGA Family Data Sheet
Figure 1. ispXPGA Block Diagram
PF
PIC
sysMM Block
sysCLOCK PLL
sysHSI Bl
sIO Bffer
Programmable Function Unit
The Programmable Function Unit (PFU) is the bauilding block f the spXPGA architecture. The PFUs are
arranged in rows and columns in the vice with PFU (1,1) referrng to row column 1). Each PFU consists of
four Configurable Logic Elements (LE, four Configurable Seential Elments (CSEs), and a Wide Logic Gen-
erator (WLG). By utilizing these compones, the PFU can implemnt a variety of functions. Table 3 lists some of
the function capabilities of the FU.
There are 57 inputs to each PU and ne outputs. ThU us 20 inputs for logic, and 37 inputs drive the con-
trol logic from which sicontrol nas are derived for thPFU.
Table 3. Function Caaility oispXPGA PF
unction
Looup table
Capability
LUT-4, LUT-5, LUT-6
ide logic function
Multiplexing
Up 20 input logic functions
2:, 4:1, 8:1
Arithmetic ogic
Singleport RAM
Double-pt RA
giste
Dedicated carry chain and booth multiplication logic
16X1, 16X2, 16X4, 32X1, 32X2, 64X1
16X1, 16X2, 32X1
8-bit shift registers (up to 32-bit shift capability)
4
Lattice Semiconductor
ispXPGA Family Data Sheet
Figure 2. ispXPGA PFU
COUT(r,c)
OE
PFUCLK0
OE
Control
Logic
PFUCLK1
CEB0
CEB1
SR
COUT
4A
WLGW0
WLGW
WLGX0
WL1
WLGY0
WLGY1
WLGZ0
WLGZ1
S
R
WIN0
WIN1
W0
1
X0
X1
Y0
Y1
Z0
Z1
Q
COUT
LUT-4 SUM
S3
LUT-4
WIN2
WIN3
CCG
K/LE
CE
IN
WIN2
WIN3
D
S
R
Q
CLE
CE
SEL0
EL0
D
XIN0
XIN1
XIN2
XIN3
4B
S
Q
COUT
LUT-4 SUM
R
LUT-4
CC
/LE
CE
IN
XIN2
XIN3
D
S
R
Q
CLK/LE
CE
SEL1
EL1
D
YIN0
YIN1
YIN2
YIN3
4C
S1
S
Q
COUT
LUT-4 SUM
SYNC/ASYN
R
LUT
CCG
CLK/LE
CE
C
IN
YIN2
YIN3
D
S
R
Q
CLK/LE
CE
2
SEL2
D
ZIN
N1
ZIN2
ZIN3
4D
S0
S
Q
COUT
LUT-4 SUM
R
UT-4
CCG
CLK/LE
CE
IN
ZIN2
ZIN3
D
S
R
Q
CLK/LE
CE
SEL3
SEL3
CIN(r,c) from
COUT(r-1,c)
5
Lattice Semiconductor
ispXPGA Family Data Sheet
Configurable Logic Element
The CLE is made up of a four-input Look-up Table (LUT-4), a Carry Chain Generator (CCG), and a two-input AND
gate. The LUT-4 creates various combinatorial and memory elements, the CCG creates a single one-bit full adder,
and the two-input AND gate can expand the CCG to incorporate Booth Multiplier capability by feeding the output of
the AND gate to one of the inputs of the CCG.
Of the five inputs that feed each CLE, two are dedicated inputs into each LUT-4 and the eminthree take on
varying functionality. The third and fourth inputs can be used as either inputs to the LUT-4 or as a Fed-Thru to the
CSE via the WLG. The fifth input can be a data port when the LUT is configured s DistibuteMemory, a select
line for multiplexer operation, or a Feed-Thru directly to the CSE via the WLG (Figue 2
Look-Up Table – Combinatorial Mode
In combinatorial mode, the LUT-4 can implement any logic function up to fur inputsBy using the cachain and
the WLG, each LUT-4 can be combined to form the enhanced functionlistein Tabe 3.
Look-Up Table – Distributed Memory Mode
In the distributed memory mode, the LUT functions as a memory ement. The inputs o the LUT nction as
Address and Data. Each PFU is capable of implementing up to SAM bits. Both singad double port RAM
can be performed in the PFU (Table 3). Furthermore, the istributed mmory can be cnfigurd as either synchro-
nous or asynchronous memory. Figure 3 illustrates thLUT while in distributed memormodWhen using any
LUT in the PFU in memory mode, the Set/Reset signal wile usefor Write Enab(WE(S) and the CLK0 signal
will be used as the clock for synchronous read ane.
Figure 3. LUT in Distributed Memory Mode
PFUCLK
E
WE (SR)
DDR[0] (0)
ADD] (IN1)
ADR[2] (IN2)
ADDR[3] (IN3)
DIN (L)
UT-4
DOUT (4A)
Lk-Up abl– Shift Regiser M
In the shift rgister mode, the LUT funons as a 1-bit to 8-bit shift register. This means that each PFU can imple-
ent uo four 8-bit shift risteroany cascaded combination. Figure 4 illustrates the LUT when configured in
shift reister mode.
6
Lattice Semiconductor
ispXPGA Family Data Sheet
Figure 4. LUT in Shift Register Mode
PFUCLK0
CEB0
SEL (SHIFTIN)
LUT-4
SHIFTOUT ()
Carry Chain Generator
The Carry Chain Generator is useful for implementing high-speed arimetic unctions. The CG consf a two-
input XOR gate whose carryout can be cascaded with the int of thadjacent CCG. Ashon in Figure 5, the
carryin signal feeds CLE3 of the PFU and is propagated though CLnd CLE1 before reing CE0. The sum
output of the CCG can be fed to the CSE through the WG. Te carryout must propage to CEfor use outside
the PFU. The carryout from the PFU can feed the W0 inut f CSE0. The CCG aso helps o effectively implement
wider functions by using its logic elements to expand the cabilies of the LUT-4.
Figure 5. Carry Chain Generator
COUT(r,
COUT to
CSE0
SUM3
SUM2
SUM1
SUM0
CLE0
CLE1
CLE2
CLE3
A
COUT
SUM
C
CIN from
Routing
COUT(r+1,c)
Wide Logic Gene
The WLG containnecessary to implement wide gate functions. This is made up of a set of multiplexers
that are located betwCLE and the CSE. The WLG helps in enhancing the wide gating capability of the PFU.
The outputs of each CLcan be cascaded in the WLG to build wide gating functions. Wide multiplexing functions
are also possible with a similar use of the WLG. Figure 6 illustrates the WLG.
7
Lattice Semiconductor
ispXPGA Family Data Sheet
Figure 6. ispXPGA Wide Logic Generator
COUT
WIN2
WIN3
4A
S3
SEL0
WLGW0
WLGW1
4B
XIN2
XIN3
W
WLGX1
S2
SEL1
SEL3
4C
SEL2
4D
YIN2
YIN3
S1
WLGY0
WLGY1
ZIN2
ZN3
WLGZ0
WLGZ1
S0
Confiurable Sequental Element
There are two regach CSE for a total of eight registers in each PFU. This high register count assists in
implementing efficed applications with no utilization penalty. Each register can be configured as a latch
or D type flip-flop witr synchronous or asynchronous set or reset. Figure 2 shows the signals that feed the
register’s D inputs. Feethrough signals in the architecture ensure that registers are efficiently utilized even if the
accompanying LUT is occupied.
Control Logic
The control signals available to the registers in a PFU are Clock, Clock Enable, and Set/Reset. Figure 7 shows the
various options available to generate the clock signal. As can be seen, the clock signal is the output of a 12:1 MUX
with true and compliment versions available from the 12:1 MUX. Each CSE can chose whether it uses the true or
complement form of the clock. Figure 8 shows the Set/Reset selection for each PFU in the ispXPGA. A common
8
Lattice Semiconductor
ispXPGA Family Data Sheet
Set/Reset signal controls all the registers for each PFU. This common Set/Reset signal is composed of the logical
OR term of the Global Set/Reset signal (GSR) and the selected signal from routing. The polarity of this signal is not
controllable inside the PFU. The polarity of the Global Set/Reset signal (GSR) is programmable. Figure 9 shows
the Clock Enable and Output Enable selection for each PFU.
Figure 7. Clock Selection per PFU
CLK0
CLK1
CLK2
CLK3
PFCLK0
CLK4
CLK5
CLK6
CLK7
PFUCLK1
From routing
4
Figure 8. Set/Reset Selection per PFU
8
From routing
Set/Reset
GSR
Figure 9. Clock Enable and Output nable Selection per PU
8
From rout
CEB0
CEB1
OE
rom routing
Programable Input/Otput Cell
The grammable Inpututput Cell PIC) is an essential part of the symmetrical architecture of the ispXPGA
Family. he PICs interface tPFUand EBRs to the sysIO and sysHSI blocks of the device.
Each PIC containrammable Input/Outputs (PIOs) with a total of 21 inputs and 10 outputs. There are 18
inputs from routingts from the sysIO buffers, and the Global Set/Reset signal. Four outputs of the PIC
connect to routing anoutputs are available as Output Enables for the tri-statable Long Lines. The remaining
four outputs feed the sysIO buffers directly (one output enable and one output to each). Each PIC associated with a
sysHSI block has four additional inputs and six additional outputs to support the sysHSI blocks. The four additional
inputs come from the sysHSI block associated with the PIC. The four of the six additional outputs come from the
PIC outputs and feed the sysHSI block, while the remaining two outputs feed routing. Figure 10 shows the block
diagram of the PIC with the sysHSI block inputs and outputs.
9
Lattice Semiconductor
ispXPGA Family Data Sheet
Figure 10. ispXPGA PIC
GSR
sysIO
9
2
From routing
PIO0
To rong
2
2
From sysHSI block
To sysHSI block
routing
Only for PICs
associated with
sysHSI blocks
Onl
asso
ysHSI
To routing
PIC
2
2
From sysHSI block
To sysHSI block
2
9
To routg
O
From routing
sysIO
O1 OE0
Programmable Input/Output
The PIO is the building block f a PICThe PIO has a total of 1 inputs and five outputs. Nine of the 11 inputs are
generated from routing. he iuts frm routing are thIO (IN), Feed-Thru (FT), Clock (CLK), Input Clock
Enable (ICE), Input St/Reset (ISR), Output Clock Enabl(OCEN), Output Set/Reset (OSR), PIO Output Enable
(OEN), and PIO InpEble (IEN). The remuts re the sysIO input buffer signal and the Global Set/
Reset signal. Three of e fivoutputs (OUT0nd OE) feed routing. The last two outputs feed the sysIO
buffer directly as the outpand output enable oIO output buffer.
PIOs assciated ith ssHSI blocks cntain two additional inputs and outputs to support the sysHSI block. The two
inputs ome rom thsysHSI block asciated ith the PIO, and the two outputs feed the sysHSI block. One of the
inputs ues directly through te PIO to rtg, while the other is multiplexed with the Feed-Thru, register bypass,
Q ouut othe register torm OUT1 output of the PIO. The outputs to the sysHSI block are the same sig-
nals the outputs which eed the sysIbuffers (sysIO Output and sysIO Output Enable).
Each PO has an inpegistan output register, and an output enable register as shown in Figure 11. The input
register path of tha ‘dlay’ option, which slows the data-flow. A two-input OR function of the Global Set/
Reset (GSR) and ISR or OSR) signals creates the set/reset term for the respective registers. Each PIO
has two pairs of set/rd clock enable signals. One is exclusive to the input register, whereas the other is com-
mon for both the output and output enable registers. The clock (CLK) is common to all registers in a PIO, and the
polarity of the clock is controllable. The input, output, and the output enable registers can be configured as a latch
or D-type flip-flop. Each PIO is capable of generating an output enable signal, which in turn becomes a PIC output.
10
Lattice Semiconductor
ispXPGA Family Data Sheet
Figure 11. ispXPGA PIO
Only for PIOs associated with sysHSI Blocks
From sysHSI block
From sysHSI block
To Routing
Feed-through (FT)
From sysIO Input
OT0
OUT1
D
Q
R
Delay
CLK/LE
Clock (CLK)
Input Clock Enable (ICEN)
CE
S
Input Set/Reset (ISR)
Global Set/Reset(GSR)
To sysIO
Output
PIO Input (IN)
D
Q
R
To sHSI
ock
CLK/LE
Only for PIOs
Asociated with
sysHSI Blocks
Output Clock Enable (OCEN)
Output Set/Reset (OSR)
CE
S
TysHS
bck
o sysIO
Output
Enable
PIO Output Enable(OEN)
Q
R
LK/LE
CE
S
PIO Input Enable (IEN)
OE
VLI Routing Rsources
The ispXPGA architecte coains a Variableerconnect (VLI) routing technology connecting the PFUs,
PICs, and EBRs in the dee. There are four touting resources, Global Lines, Long Lines, General Inter-
connect, and Lcal Lines forming the lobal routing structure. This allows a signal to be routed to any element in
the devie with thopmal delay.
The Gll Lines consist of glbal clock liand a global set/reset line. These lines are routed to all elements in
e devicThy are specificay degd for high speed, predictable timing regardless of fan-out. The global clock
lines n also be used as edicated ints.
The Log Lines conof Hzontal and Vertical Long Lines (HLL and VLL). The VLL and HLL are tri-statable
lines spanning the vice. These lines allow fast routing for high fan-out nets and general-purpose functions.
The General Interconsists of Double and Deca Lines. The Double Lines connect up to three elements (two
plus the driving elemenwhile the Deca Lines connect up to eleven elements (ten plus the driving element).
The Local Lines are extremely fast routing paths consisting of Feedback and Direct Connect Lines. The Feedback
Lines are internal routing paths from the PFU outputs to the PFU inputs. The Direct Connect Lines connect all adja-
cent elements.
The Common Interface Block (CIB) provides the link between the logic element (PFU, PIC, or EBR) and the VLI
Routing resources. The CIB is a switch matrix that can be programmed to connect virtually any routing resource to
any input or output of the logic element.
11
Lattice Semiconductor
ispXPGA Family Data Sheet
Memory
The ispXPGA architecture provides a large amount of resources for memory intensive applications. Embedded
Block RAMs (EBRs) are available to complement the Distributed Memory that is configured in the PFUs (see Look-
Up Table -Distributed Memory Mode in the PFU section above). Each memory element can be configured as RAM
or ROM. Additionally, the internal logic of the device can be used to configure the memory ements as FIFO and
other storage types. These EBRs are referred to as sysMEM blocks. Refer to Table 1 fomemory resources per
device.
sysMEM Blocks
The sysMEM blocks are organized in columns distributed throughout the device. EaEBR contains 4.6K bits of
dual-port RAM with dedicated control, address, and data lines for each porEach coluof sysMEM blocks has
dedicated address and control lines that can be used by each block separaely or cacaded to form larger memory
elements. The memory cells are symmetrical and contain two sets oideical cotrol signals. has a
read/write clock, clock enable, write enable, and output enable. Figue 1illustrs the sysMEM b
The ispXPGA memory block can operate as single-port or dual-port RAM. Supported confiurations ar
• 512 x 9 bits single-port
• 256 x 18 bits single-port
• 512 x 9 bits dual-port
• 256 x18 bits dual-port
(8 bits data / 1 bit pary)
(16 bits data / 2 bitparit)
(8 bits data / 1 bit pi)
(16 bits data / its paty)
The data widths of “9” and “18” are ideal for apwhere parity is ecessa. This allows 9 data bits, 8 data
bits plus a parity bit, 18 data bits, or 16 data bits pparity bits. The loc for gerating and checking the par-
ity must be customized separately.
Figure 12. sysMEM Block Diagram
ADDR
DATAA
LKA
CE
ADDRB
DATAB
CLKB
CE B
M Block
WEA
WEB
OEA
OEB
Reand Write Operatins
The ispPGA EBR has fullsynconous read and write operations as well as an asynchronous read operation.
Thsoperations averaifferent types of memory to be implemented in the device.
Synchronous Reaock Enable (CE) and Write Enable (WE) signals control the synchronous read opera-
tion. When the CE siglow, the clock is enabled. When the WE signal is low the read operation begins. Once
the address (ADDR) is present, a rising clock edge (or falling edge depending on polarity) causes the stored data
to be available on the DATA port. Figure 13 illustrates the synchronous read timing.
12
Lattice Semiconductor
ispXPGA Family Data Sheet
Figure 13. EBR Synchronous Read Timing Diagram
tEBCPW
CLK
tEBCES
tEBCEH
CE
tEBWES
tEBH
WE
tEBOEDIS
tEBOEEN
OE
Invalid Data
tEEEN
tEBCO
Valid Data
Valid Data
DATA
tEBWEDIS
tEBADDS
ADDR
tEBAD
Synchronous Write: The WE signal controls the synchronous ite peration. When thWsignal is high, the
write operation begins. Once the address and data are prsent and the Output Enable OE) iactiv, a rising clock
edge (or falling edge depending on polarity) causes tdatto be stored into the EBRFigur14 illustrates the
synchronous write timing.
Figure 14. EBR Synchronous Write Timing D
CLK
tEBPW
ES
tEBWEH
WE
DATA
tEBDATAH
tEBADDH
tEBADDS
ADDR
WRITE
Asynchrnous ead: The WE signacontrols the asynchronous read operation. When the WE signal is low, the
read oeration beg. Shortly after thaddress present, the stored data is available on the DATA port. Figure 15
illustras e asynchronous reimingor ore information about the EBR, refer to TN1028 ispXPGA Memory
Uge Gdelines.
Fire 5. EBR Asynchrous Read Timing Diagram
tEBOEDIS
tEBOEEN
OE
DATA
Invalid Data
tEBWEEN
tEBWEDIS
DATA0
DATA1
DATA1
ADDR0
ADDR1
ADDR2
tEBARAD_H
ADDR
tEBARADO
13
Lattice Semiconductor
ispXPGA Family Data Sheet
sysCLOCK PLL Description
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) and the various dividers, reset, and feedback
signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and gener-
ate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are aligned
either at the board level or the device level.
The ispXPGA devices provide up to eight PLLs. Each PLL receives its input clock from its sciatd global clock
pin, and its output is routed to the associated global clock net. For example, PLL0 reeives its clocinput from the
GCLK0 global clock pin and provides output to the CLK0 global clock net. The PLalso as the ability to output a
secondary clock that is a division of the primary clock output. When using the sodary lock, the secondary
clock will be routed to the neighboring global clock net. For example, PLL0 wiive its primary clock output on the
CLK0 global clock net and its secondary clock output will drive the CLK1 lobal clock net. Additionally, each PLL
has a set of PLL_RST, PLL_FBK, and PLL_LOCK signals. The PLL_RST gnal cabe generated routing
or a dedicated dual-function I/O pin. The PLL_FBK signal can be geneted roua dedicated on I/O
pin or internally from the Global Clock net associated with the PLLThe LL_LOCK signal feeds irectly
from the sysCLOCK PLL circuit. Figure 17 illustrates how the PLL_RT and LL_FBK signls are gened.
Each PLL has four dividers associated with it, M, N, V, ad K. Thdivider is used to de thclock signal,
while the N divider is used to multiply the clock signaThe V divider allows the VCfreqny to operate at
higher frequencies than the clock output, thereby increanthe frequency rangeThe K dider is only used when
a secondary clock output is needed. This divider divides thpriary clock output ad feedto the adjacent global
clock net. Different combinations of these dividehe uer to synthesize ock frqencies. Figure 16 shows
the ispXPGA PLL block diagram.
The PLL also has a delay feature that lows the out clock to be dvand or delayed to improve set-up and
clock-to-out times for better performae. This operates by inseting dey on the input or feedback lines of the
PLL. For more information on the PLL, plase refer to TN1003sCLOCK LL Usage and Design Guidelines.
Figure 16. ispXPGA PLL Blok Diagram
PLL_LOCK
CLK_OUT
GLK_IN
put Clock
Prommable
(M) Divider
elay
Post-scalar
÷ 1 to 32
(V) Divider
--------------
PLL (n)
Clock Net
÷
1, 2, 4, 8,
16, 32
mmable
-ay
LL_RST
Clock (K)
Divider
÷
2, 4, 8,
16, 32
To Adjacent_PLL
From
Adjacent_PLL
Feedback
Divider (N)
X 1 to 32
PLL_FBK
14
Lattice Semiconductor
ispXPGA Family Data Sheet
Figure 17. ispXPGA PLL_RST and PLL_FBK Generation
I/O/PLL_RST
From Routing
To PLL
I/O/PLL_FBK
To PLL
From Clock Net
Clock Routing
The Global Clock Lines (GCLK) have two sources, their dedicated pins anthe sysCLOK circuit. Figure 18 illus-
trates the generation of the Global Clock Lines.
Figure 18. Global Clock Line Generation
From Routing
GCLK0
GCLK1
GCLK2
GCLK3
GCLK7
GCLK6
GCLK5
GCLK4
CLK_OUT0
SEC_OUT0
CLK_O7
SEC_OUT7
CLK0
CLK7
PLL0
PLL1
PLL2
P3
PL
PLL6
PLL5
PLL4
From ing
CLK_OUT1
SEC_OUT1
C_OUT6
SECOUT6
CLK6
om Routing
CLK_OUT2
SECUT2
CLK_OUT5
SEC_OUT5
CLK2
CLK5
LK4
From Routin
CLK_OUT
SEC_OUT3
CLK_OUT4
SEC_OUT4
K3
sysIO Capability
All thspXGA devices have eight sysban, where each bank is capable of supporting multiple I/O standards.
Each sO banhas its own I/O supply voltage (V ) and reference voltage (V ) resources allowing each
CCO
REF
ank cometindependence rothe thers. Each I/O is individually configurable based on the bank’s V
and
CCO
V
stings. In addition, ach I/O haconfigurable drive strength, weak pull-up, weak pull-down, or a bus-keeper
F
latch. Tble 4 lists the numbof I/Os supported per bank in each of the ispXPGA devices. In addition, 5V tolerant
inpare specified an I/bank that is connected to V
interfaces.
of 3.0V to 3.6V for LVCMOS 3.3, LVTTL and PCI
CCO
Table 5 lists the sysIO dards with the typical values for V
V
and V
CCO, REF TT.
The TOE, JTAG TAP pins, PROGRAM, CFG0 and DONE pins of the ispXPGA device are the only pins that do not
have the sysIO capabilities. The TOE and CFG0 pins operate off the V of the device, supporting only the LVC-
CC
MOS standard corresponding to the device supply voltage. The TAP pins have a separate supply voltage (V
which determines the LVCMOS standard corresponding to that supply voltage.
),
CCJ
There are three classes of I/O interface standards that are implemented in the ispXPGA devices. The first is the un-
terminated, single-ended interface. It includes the 3.3V LVTTL standard along with the 1.8V, 2.5V, and 3.3V LVC-
MOS interface standards. Additionally, PCI and AGP-1X are subsets of this type of interface.
15
Lattice Semiconductor
ispXPGA Family Data Sheet
The second type of interface implemented is the terminated, single-ended interface standard. This group of inter-
faces includes different versions of SSTL and HSTL interfaces along with CTT, and GTL+. Usage of these particu-
lar I/O interfaces requires an additional V
signal. At the system level a termination voltage, V , is also required.
REF
TT
Typically an output will be terminated to V at the receiving end of the transmission line it is driving.
TT
The third type of interface standards are the differential standards LVDS, BLVDS, and LVCL. The differential
standards require two I/O pins to create the differential pair. The logic level is determined by the ifference in the
two signals. Table 6 lists how these interface standards are implemented in the ispXPGA deces.
For more information on sysIO capability, refer to TN1000, sysIO Usage Guidelinefor Ltice Devices.
Figure 19. sysIO Banks per Device
Bank 7
Bnk 6
I/O 0
I/O
VCCO0
VREF0
VCCO5
VREF5
GND
GND
I/O N
I/O 0
I/O 0
I/O N
VCCO1
VR1
VCCO4
VREF4
G
GND
I/O N
I/O 0
Bank
Bank 3
Table 4. Number of r Bank
Device
Max. Number of I/Os per Bank (N)
XPGA 1200
XPGA 500
XPGA 200
XPGA 125
62
42
26
22
16
Lattice Semiconductor
ispXPGA Family Data Sheet
Table 5. ispXPGA Supported I/O Standards
sysIO Standard
VCCO
3.3V
3.3V
2.5V
1.8V
3.3V
3.3V
3.3V
2.5V
1.5V
1.5V
N/A
VREF
N/A
VTT
N/A
LVTTL
LVCMOS-3.3
LVCMOS-2.5
LVCMOS-1.8
PCI
N/A
N/A
N/A
N/A
N/A
NA
N/A
A
AGP-1X
N/A
N/A
SSTL3, Class I, II
SSTL2, Class I, II
HSTL, Class I
HSTL, Class III
GTL+
1.5V
1.25V
0.75V
0V
1.0V
/A
1.5V
1.25V
0.7
1.
N/A
LVPECL
3.3V
2.5V
2.5V
LVDS1
A
N/A
BLVDS
N/A
N/A
1. VCCO must be 2.5V for high speed serial operations (sysHSI block
Table 6. Differential Interface Standard Supp
sysIO Buffer Not sHSI Block
Supported ith external rstor network
syffer Using sysHSI Block
Driver
Suppted
LVDS
Receiver
Driver
Supportith standard termination
Supported wiexternal resistor netork
pported (may eed terminatio
upportewith external resistor netrk
Spportewith termination
Sported with standard termination
Not supported
BLVDS
LVPECL
Receiver
Driver
Supported (may need termination)
Not supported
Receiver
Supported with termination
1. For more information, fer to N1000, sysIO Usage Guifor Lice Devices.
17
Lattice Semiconductor
ispXPGA Family Data Sheet
High Speed Serial Interface Block (sysHSI Block)1
The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The
ispXPGA devices have multiple sysHSI blocks.
Each sysHSI block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and
Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDEcan be used as a full
duplex channel. The two SERDES in sysHSI blocks share a common clock and must opert the ame nominal
frequency. Figure 20 shows the sysHSI block.
Device features support two data coding modes: 10B/12B and 8B/10B (for use witoter encoding schemes, see
Lattice’s sysHSI technical notes). The encoding and decoding of the 10B/12standd arperformed within the
sysHSI block. For the 8B/10B standard, the symbol boundaries are aligned nternally buthe encoding and decod-
ing are performed outside the sysHSI block.
Each SERDES block receives a single high speed serial data inpustrem (with embedded clockinput,
and provide a low speed 10-bit wide data stream and a recovered cock to he device. For ansmittiERDES
converts a 10-bit wide low-speed data stream to a single high-peed ta stream with emeddeclock for output.
Additionally, multiple sysHSI blocks can be grouped togeer to form a source synchroous inrfae of 1-10 chan-
nels.
For more information on the SERDES/CDR, refer 102ssHSI Usage uidelies.
Figure 20. sysHSI Block Diagram
SEES(HSI#A)
10
SOUT
SIN
TXD
RXD
From PICs
Serializer
10
To PICs
To PICs
RECCLK
Deserializer and Datecovery
SYDT
To PICs
syIO
CDRRST
From PICs
CAL
From PICs
To PICs
CSLOCK
SS_CLKOUT
SS_CLKIN
CSPLL
From Global
Clock Tree
REFCLK
CDRRST
SYDT
From PICs
To PICs
Deserializer and Clock/Data Recovery
RECCLK
To PICs
To PICs
10
RXD
10
TXD
SOUT
Serializer
From PICs
SERDES(HSI#B)
1. “E-Series” does not support sysHSI.
18
Lattice Semiconductor
ispXPGA Family Data Sheet
Configuration and Programming
The ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of
memory, Static RAM and non-volatile E2CMOS cells. The static RAM is used to control the functionality of the
device during normal operation and the E2CMOS memory cells are used to load the SRAM. The E2CMOS memory
module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as tworking configura-
tion memory. There is a one-to-one relationship between SRAM memory and the E2CMOcells. The SRAM can
be configured either from the E2CMOS memory or from an external source, as shown in Fige 21.
Figure 21 shows the different ports and modes that are used in the configuration aproamming of the ispXPGA
devices. There are two possible ports that can be used for configuration of the SRAemor: the ISP port which
supports the IEEE 1149.1 Test Access Port (TAP) Std., accommodates bite congurtion. The sysCONFIG
port allows byte-wide configuration of the SRAM configuration memory. Whn programmng the E2CMOS memory,
only the 1149.1 TAP can be used.
Configuration and programming done through the 1149.1 Test Acess ort (TAP) supports both E Std.
1149.1 Boundary Scan TAP specification and the IEEE Std. 1532 In-ystem Configuration secificatioconfig-
ure or program the device using the 1149.1 TAP the device mube in e ISP mode. To cfiguthe SRAM mem-
ory using the sysCONFIG Port, the device must be in the ysCONFode. Upon power-the dvice’s SRAM
memory can be configured either from the E2CMOS mmory r from an external sourcthroh the sysCONFIG
mode. Additionally, the SRAM can be re-configured frote E2CMOS memory y execung a “REFRESH.” See
TN1026, ispXP Configuration Usage Guidelines, for moin epth information n the ifferent programming
modes, timing and wake-up.
Figure 21. ispXP Block Diagram
IP 19.1 TAP Port
sysNFIG Peheral Port
sysCONFIG
Port
ISP
Mode
CKGND
1532
rogramming
in seconds
Configuration
in milliseconds
Power-up
Refresh
CMOS
Memy Spa
SRAM
Memory Space
Download in
microseconds
MemSpa
Supports IEE49.Boundary Scan Testability
All ispXPGA deviceundary scan cells and supports the IEEE 1149.1 standard. This allows functional test-
ing of the circuit boarwhich the device is mounted through a serial scan path that can access all critical logic
notes. Internal boundary scan registers are linked internally, allowing test data to be shifted in and loaded directly
onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be
linked into a board-level serial scan path for more board level testing.
Security Scheme
A programmable security scheme is provided on the ispXPGA devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, the security scheme prevents read-back of the programmed
19
Lattice Semiconductor
ispXPGA Family Data Sheet
pattern by a device programmer, securing proprietary designs from competitors. The entire device must be erased
in order to erase the security scheme.
Density Shifting
The ispXPGA family has been designed to ensure that different density devices in the same package have the
same pin-out. Furthermore, the architecture ensures a high success rate when performindesign migration from
lower density parts to higher density parts. In many cases, it is possible to shift a lower utzon sign targeted
for a high-density device to a lower density device. However, the exact details of the final resourcutilization will
impact the likely success in each case.
Temperature Sensing Diode
The built-in temperature-sensing diodes allow junction temperature to be masured uring device operation. A pair
of pins (DXp and DXn) are dedicated for monitoring device junction empature. he measureone by
forcing 10 µA and 100 µA current in the forward direction, and themesuring he resulting voltoltage
decreases with increasing temperature at approximately 1.64 mV/°CA typal device with a 5°C junemper-
ature will measure approximately 593 mV.
The temperature-sensing diode works for the entire operting range ashown in Fige 22 Senng Diode Volt-
age-Temperature Relationship. Refer to the Lattice Thmal anagement document for hermcoefficients. Also
refer to TN1043, Power Estimation in ispXPGA Devices.
Figure 22. Sensing Diode Voltage-Temperatonship
0.85
0.80
100 uA
10 uA
.75
0.70
0.65
0.60
55
0
-50
0
25
50
100
125
-25
75
Junction Temperature (°C)
20
Lattice Semiconductor
ispXPGA Family Data Sheet
Absolute Maximum Ratings1, 2, 3
1.8V
2.5V/3.3V
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V
CC
PLL Supply Voltage (V
) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V
CCP
Output Supply Voltage (V
) . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V
CCO
IEEE 1149.1 TAP Supply Voltage (V
). . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5
CCJ
Input Voltage Applied4, 5 . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V . . . . . . . . . .-0.5 to 5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150C. . . . . . . . . -65 to 150C
Junction Temperature (T ) with Power Applied . .-55 to 150C. . . . . . . . . -5 to 150C
J
1. Stress above those listed under the “Absolute Maximum Ratings” may caupernendamage to the ctional
operation of the device at these or any other conditions above those indited ihe operational sectins of ication
is not implied (while programming, following the programming specificatio).
2. Compliance with the Lattice Thermal Management document is requid.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (VIH (MAX) + 2) volts nto xceed 6V is permitted for a duraon of <20ns.
5. A maximum of 64 I/Os per device with VIN > 3.6V is d.
Recommended Operating Condi
Symbol
Parame
Min
1.65
2.3
3.0
1.65
2.3
3.0
1.65
2.3
3.0
0
Max
1.95
2.7
Units
V
Supply Voltage for 1.8dice1
Supply Voltage for 2.5V devi
Supply Voltage r 3.3V device
VCC
V
3.6
V
Supply Voltagor PLL ad sysHSI blocks, 1.8V dees1
Supply Vltage fPLL d sysHSI blocks, V devi
SuppVoltae for PLL and sysHSI 3.3V evices
Supply tage fIEEE 1149.1 TPort for LVCMOS 1.8V
Supply Vogfor IEEE 1149.1 TPort for LVCMOS 2.5V
Supply Voltage for IEEE 49.1 Test Access Port for LVCMOS 3.3V
Juctin Temperature CmmerciaOperation
1.95
2.7
V
VCCP
V
3.6
V
1.95
2.7
V
VCCJ
V
3.6
V
TJ (CO
TJ (IN)
85
C
Junction Temperatue Indrial Oeration
-40
105
C
1. sysHSpecificion is valid for VC and VP = 1.7V to 1.9V.
E2CMOS Erase Reprogram Specifications
Parameter
Erase/Reprogram
Min
Max
Units
1,000
—
Cycles
1. Valid over commerciature range.
Hot Socketing Characteristics1, 2, 3, 4
Symbol
Parameter
Condition
Min
Typ
+/-50
Max
+/-800
Units
IDK
Input or Tristated I/O Leakage Current 0 ð VIN ð 3.0V
—
A
1. Insensitive to sequence of VCC and VCCO when VCCO ð 1.0V. For VCCO > 1.0V, VCC min must be present. However, assumes monotonic
rise/fall rates for VCC and VCCO, provided (VIN - VCCO) ð 3.6V.
2. LVTTL, LVCMOS only.
3. 0 < VCC ð VCC (MAX), 0 < VCCO ð VCCO (MAX).
4. IDK is additive to IPU, IPD or IBH. Device defaults to pull-up until non-volatile cells are active.
21
Lattice Semiconductor
ispXPGA Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
0 ð VIN < (VCCO - 0.2V)
(VCCO - 0.2V) ð VIN ð 3.6V
Min
—
Typ
—
Max
10
Units
A
1
IIL, IIH
Input or I/O Low Leakage
Input High Leakage Current
—
—
300
A
3.6V < VIN ð 5.5V and
3.0V ð VCCO ð 3.6V
2
IIH
—
—
mA
IPU
I/O Active Pull-up Current
0 ð VIN ð 0.7 VCCO
-30
—
—
—
—
—
-150
A
A
A
A
A
A
V
IPD
I/O Active Pull-down Current
VIL (MAX) ð VIN ð VIH (MAX)
30
150
IBHLS
IBHHS
IBHLO
IBHHO
VBHT
Bus Hold Low Sustaining Current VIN = VIL (MAX)
Bus Hold High Sustaining Current VIN = 0.7 VCCO
Bus Hold Low Overdrive Current 0 ð VIN ð VIH (MAX)
Bus Hold High Overdrive Current 0 ð VIN ð VIH (MAX)
Bus Hold Trip Points
30
—
30
—
—
-1
VCCO 0.35
VO * 0.
VCCO = 3.3V, 2.5V, 1.V
I/O Capacitance3
—
—
—
—
—
—
—
—
—
—
—
C1
C2
C3
8
8
6
pf
pf
pf
V
CC = 1.8V, VIO = to V(MAX)
VCCO = 3.3V, 2.51.V
VCC = 1.8V= 0 tVIMAX)
VCCO = 1.8V
Clock Capacitance3
Global Input Capacitance3
VCC = 1.to VIH (MAX)
1. Input or I/O leakage current is measured with tpin configurs an input or as aO withe output driver tri-stated. It is not
measured with the output driver active. Bus intenance circuits are disabled.
2. 5V tolerant inputs and I/Os should be plad ianks where 3.0V ð VCCO ð V. The JTand sysCONFIG ports are not included for the
5V tolerant interface.
3. TA = 25C, f = 1.0MHz.
22
Lattice Semiconductor
ispXPGA Family Data Sheet
Supply Current
Over Recommended Operating Conditions
Symbol
Parameter
Device
Condition
VCC = 3.3V
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
60
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
LFX125
V
V
V
V
V
V
V
V
V
CC = 2.5V
60
CC = 1.8V
CC = 3.3V
CC = 2.5V
CC = 1.8V
CC = 3.3V
CC = 2.5V
CC = 1.
CC 3.3V
0
7
LFX200
LFX500
70
50
1, 2
ICC
Standby Core Operating Power Supply Current
120
120
100
20
220
0
2.
2.0
2.0
2.0
17.0
17.0
15.0
2.0
1.5
1.0
LFX1200 VC = 5V
CC V
V
VCCO = 3.3V
VCO = 2.5V
3
ICCO
Standby Output Power Supply Current
V
CCO = 1.8V
CCO = 1.5V
V
VCCP = 3.3
4
ICCP
Standby PLL Operating Supply Crrent
V
CP = 5V
CP = 1.8
VCC= 3.3V
5
ICCJ
Standby IEEE 1149.1 AP Power Supply Current
V
CCJ = 5V
CCJ = 1.8V
1. TA = 25°C, frequency = 1.MHz, dce coigured with 16-bit couers.
2. ICC varies with specific evice onfiguration and operating ency. or more accurate power calculation, see TN1043, Power Estimation
in ispXPGA Devices.
3. TA = 25°C, per bank, no load, fquency = 0 MHz.
4. TA = 25°C, per PLL, frequen10 MHz.
5. TA = 25°C
23
Lattice Semiconductor
ispXPGA Family Data Sheet
sysIO Recommended Operating Conditions
VCCO (V)1
VREF (V)
Standard
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.82
LVTTL
Min.
3.0
2.3
1.65
3.0
3.0
3.15
2.3
3.0
3.0
2.3
1.4
1.4
-
Typ.
3.3
2.5
1.8
3.3
3.3
3.3
2.5
3.3
3.3
2.5
1.5
1.5
-
Max.
3.6
2.7
1.95
3.6
3.6
3.45
2.7
3.6
3.6
2.7
1.6
1.6
-
Min.
Typ.
Max.
-
-
-
-
-
-
-
-
-
-
-
-
PCI 3.3
-
-
-
AGP-1X
-
1.1
1.3
35
1.3
0.68
-
-
-
1.35
.7
0.9
-
SSTL 2
25
1.5
1.5
1.5
0.5
0.9
.0
-
SSTL 3
CTT 3.3
CTT 2.5
HSTL Class I
HSTL Class III
GTL+
0.882
-
1.122
-
LVDS
2.3
3.0
2.3
2.5
3.3
2.5
3.6
7
LVPECL
-
-
-
BLVDS
-
-
-
1. Inputs independent of VCCO.
2. Design tool default setting.
24
Lattice Semiconductor
ispXPGA Family Data Sheet
sysIO DC Electrical Characteristics
Over Recommended Operating Conditions
VIL
VIH
VOL
Max. (V)
VOH
Min. (V)
Standard
Min. (V)
Max. (V)
Min. (V)
Max. (V)
I(mA)
IOH (mA)
20, 16, 12, -20, -16,-12,
8, 33, -8, -5.33, -4
0.4
0.2
0.4
0.2
0.4
V
CCO - 0.4
VCCO 0.2
VCC- 0
LVCMOS 3.3
-0.3
0.8
2.0
5.5
0.1
-0.1
16, 12, 8, -16, -12, -8,
.33, 4
0.1
12, 81, 5.33,
-5.33, -4
-0.1
-12, -81,
LVCMOS 2.5
LVCMOS 1.81
-0.3
-0.3
0.7
1.7
3.6
3.6
V
CCO - 0
0.683
1.073
VCCO 0.4
4
33, -4
0.35VCC
0.65VCC
0.2
0.4
2
CCO - 0.2
VCCO - 0.4
0.1
4
1
-4
LVTTL
-0.3
-0.3
-0.3
0.8
2.0
5.5
5.5
3.
V
CCO - 0.2
01
-0.1
1.083
0.3VCCO
1.083
1.53
PCI 3.3
AGP-1X
0.1 VCCO
0.1 VCCO
0.9 VCCO
0.9 O
.5
1.5
-0.5
-0.5
0.5 VCCO
1.53
0.3 VCCO
0.5 VC
SSTL 3 Class I
SSTL 3 Class II
SSTL 2 Class I
SSTL 2 Class II
CTT 3.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
3
VREF - 0.2 VREF
REF - 0.2 VREF + 0.
REF - 0.18 VREF + 0.18
VREF - 18 REF + 0.18
.6
3.6
3.6
3.6
3.6
3.6
3.6
.6
3.6
0.7
0.5
VC- 1.1
VCCO 0.9
CO - 0.62
VCCO - 0.43
8
16
7.6
15.2
8
-8
-16
-7.6
-15.2
-8
V
V
0.
0.35
V
R- 0.2 V+ 0.2
REF - 0.2 VREF + 0.2
VF - 0.4 VREF + 0.4
VREF 0.4 VREF + 0.4
CTT 2.5
8
-8
HSTL Class I
HSTL Class III
GTL+
EF - 0.1 VREF + 0.1
0.4
0.4
0.6
VCCO - 0.4
VCCO - 0.4
N/A
8
-8
V
RE- 0VREF + 0.1
REF - 0.2 VREF
24
36
-8
V
N/A
1. Design tool default settin
2. The average DC current draI/Os between adjaceconnections, or between the last GND in an I/O bank and the end of the
I/O bank, as own in the logic signals conneable, exceed n*8mA. Where n is the number of I/Os between bank GND con-
nections r betwn the lat GND in a bank nd the end of a bank
3. Applicble for ispXA devices.
25
Lattice Semiconductor
ispXPGA Family Data Sheet
sysIO Differential Standards DC Electrical Characteristics1
Parameter
LVDS2
VINP, VINM
VTHD
IIN
Description
Test Conditions
Min.
Typ.
Max.
Input voltage
0V
+/-100mV
—
—
—
2.4V
—
Differential input threshold
Input current
0.2V ð VCM ð 1.8V
Power on
—
+/-10uA
1.60V
—
VOH
Output High Voltage for VOP or VOM
Output Low Voltage for VOP or VOM
Output Voltage Differential
Change in VOD between high and low
Output Voltage Offset
RT = 100 Ohm
—
1.38V
1.03V
350mV
—
VOL
RT = 100 Ohm
V
250m
—
VOD
|VOP - VOM|, RT = 100 ohm
450mV
50mV
375V
mV
mA
VOD
VOS
|VOP + VOM|/2, RT = 100 oh
1.1V
—
1.25V
—
VOS
IOSD
Change in VOS between H and L
Output short circuit current
VOD = 0V Driver outts
shorted
—
—
BLVDS1
VINP, VINM
VTHD
IIN
Input voltage
0V
+/100mV
—
—
2.4V
—
Differential input threshold
Input current
0.2V ð ð 1.8V
Per on
—
+/-10uA
1.80V
—
VOH
Output High Voltage for VOP or VOM
Output Low Voltage for VOP or VOM
Output Voltage Differential
Change in VOD Between H d L
Output Voltage Offset
—
1.4V
1.1V
300mV
VOL
V
240mV
VOD
|VVOM|, RT = 27
460mV
27mV
1.5V
VOD
VOS
|VOP + VOM| /, R= 27
1.1V
1.3V
VOS
IOSD
Change in VOS BeteH and L
Output Short Circt Current
27mV
VOD = 0. Drir Outputs
Sho
36mA
65mA
1. Refer to TN1000, sysIO sage Guior Lattice Devices.
2. VOP and VOM are the o outts of the LVDS/BLVDS oer.
LVPECL1
D
Paraete
Parameter Dcripti
Input Voltage High
Min.
Max.
Min.
Max.
Min.
Max.
Units
VCCO
3.0
3.3
3.6
V
V
V
V
V
V
VIH
1.49
0.86
1.8
2.72
2.125
2.11
1.27
—
1.49
0.86
1.92
1.06
0.3
2.72
2.125
2.28
1.43
—
1.49
0.86
2.13
1.3
2.72
2.125
2.41
1.57
—
IL
Input Voltage Lo
VO
VOL
VDIFF
Output Hig
Outpow
Differentthreshold
0.96
0.3
2
0.3
1. These values are valid at e output of the source termination pack as shown above with 100-ohm differential load only (see Figure 23).
The VOH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.
2. Valid for 0.2 ð VCM ð 1.8V.
26
Lattice Semiconductor
ispXPGA Family Data Sheet
Figure 23. LVPECL Driver with Three Resistor Pack
1/4 of Bourns P/N
ispXPLD Emulated
CAT 16-PC4F12
LVPECL Buffer
A
Zo
Zo
Rs
LVPC
differential
receve
Rs
ispXPGA 125B/C & ispXPGA 125EB/EC External Switching Characs
Over Recommended Operating onditns
-51
Min. Max. MinMax. Mi. Max. Units
-4
-3
Parameter
Description
Condition
Global Clock Input to
Output
PIO Output Register
tCO
—
-1.9
2.7
5.3
—
—
-1.8
2.9
5
—
—
-1.5
3.3
6.6
—
ns
ns
PIO Input Rhout put
delay
tS
Global Clock Input Setup
Global Clock Input Hold
PIO Input Regout input
dela
tH
tSINDLY
tHINDLY
tCOPLL
—
—
—
ns
ns
Global Clock Input Setup Input Register with input day 3.1
—
—
3.3
0.0
—
—
3.8
0.0
—
—
Global Clock Input Hold
PIO Iut Register with inpudel0.0
Global Clock Input to
Output
PIO Outt Register usinPLL
without delay
3.6
—
—
—
—
—
0.1
1.0
5.5
-2.8
3.9
—
—
—
—
—
0.3
1.2
6.3
-2.4
4.5
—
—
—
—
ns
ns
ns
ns
PInput Register n
elay using PLL withodelay
tSPLL
Global Clock put Sup
Global CloInut Hold
0
PIO Input Rithounput
0.9
tHPLL
delay usint delay
PIO Input Rinput delay
5.1
tSINDLYPLL Gobal Clock InpSetup
tHINDLYLL Global loInput Hold
usiLL witlay
PO Input Register with input delay
-3.0
ns
ung PLL hout delay
1. Onlvable for ispXPGA 125B apXPG5(2.5V/3.3V) devices.
Timing v.0.3
27
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 125B/C & ispXPGA 125EB/EC PFU Timing Parameters
Over Recommended Operating Conditions
-51
-4
-3
Parameter
Functional Delays
LUTs
Description
Min. Max. Min. Max. Min. Max. Units
tLUT4
tLUT5
tLUT6
4-Input LUT Delay
—
—
—
0.41
0.73
0.8
—
—
0.44
0.79
0.9
—
—
0.51
0.91
1.07
ns
ns
ns
5-Input LUT Delay
6-Input LUT Delay
Shift Register (LUT)
tLSR_S
tLSR_H
tLSR_CO
Shift Register Setup Time
Shift Register Hold Time
Shift Register Clock to Output Delay
-0.64
061
—
-0.6
.63
—
—
—
-0.5
0.7
—
ns
ns
ns
00
0.75
Arithmetic Functions
tLCTHRUR MC (Macro Cell) Carry In to MC Carry Out Delay (ipple)
—
—
—
—
—
0.08
0.05
0.42
0.29
0.36
6
—
—
—
—
0.09
05
0.4
0.
0.39
0.28
—
—
—
—
—
0.10
0.06
0.52
0.36
0.45
0.32
ns
ns
ns
ns
ns
ns
2
tLCTHRUL
tLSTHRU
MC Carry In to MC Carry Out Delay (Look Ahed)
MC Sum In to MC Sum Out Delay
tLSINCOUT
MC Sum In to MC Carry Out Delay
tLCINSOUTR MC Carry In to MC Sum Out Delay (R
tLCINSOUTL MC Carry In to MC Sum Out Delay (Look
Feed-thru
tLFT
PFU Feed-Thru Delay
—
15
—
0.16
—
0.18
ns
Distributed RAM
tLRAM_CO
tLRAMAD_S
tLRAMD_S
Clock to RAM Outut
—
1.24
—
—
1.33
—
—
1.53
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Tie
Data Setup Time
-0.41
0.21
0.45
0.58
0.11
0.12
2.91
—
-0.40
0.22
0.46
0.60
0.11
0.12
3.00
—
-0.34
0.25
0.53
0.69
0.13
0.14
3.45
—
—
—
—
tLRAMWE_S Write Eble Stup Time
—
—
—
tLRAMAD_H
tLRAMD_H
Address HTime
Data Hold Tim
—
—
—
—
—
—
tLRAMWE_We EnablHold Time
tLRAMCW Clock ue Width (High or ow)
tLRAMAO Address to Output D
—
—
—
—
—
—
0.86
0.93
1.07
gisteratch Delays
Regers
tL_CO
tL_S
Register Clock tutpuelay
—
0.58
—
—
0.62
—
—
0.71
—
ns
ns
ns
ns
ns
RegistTime Data before Clock)
Regie (Data after Clock)
Register nable Setup Time
Register Clock Enable Hold Time
0.14
-0.12
-0.11
0.11
0.14
-0.12
-0.11
0.11
0.16
-0.10
-0.09
0.13
tL_H
—
—
—
tLCE_S
tLCE_H
Latches
tL_GO
tLL_S
—
—
—
—
—
—
Latch Gate to Output Delay
Latch Setup Time
—
0.14
-0.12
—
0.09
—
—
0.14
-0.12
—
0.10
—
—
0.16
-0.10
—
0.12
—
ns
ns
ns
ns
tLL_H
Latch Hold Time
—
—
—
tLLPD
Latch Propagation Delay (Transparent Mode)
0.09
0.10
0.12
28
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 125B/C & ispXPGA 125EB/EC PFU Timing Parameters (Cont.)
Over Recommended Operating Conditions
-51
-4
-3
Parameter
Reset/Set
tLASSRO
Description
Min. Max. Min. Max. Min. Max. Units
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Pulse Width
Asynchronous Set/Reset Recovery
Synchronous Set/Reset Setup Time
Synchronous Set/Reset Hold Time
—
4.19
—
1.09
—
—
4.5
1.1
—
—
5.1
—
1.35
—
ns
ns
tLASSRPW
tLASSRR
0.51
—
.55
—
0.63
—
ns
tLSSR_S
-0.03
0.03
-0.03
0.03
-0.03
0.03
ns
tLSSR_H
—
—
ns
1. Only available for ispXPGA 125B and ispXPGA 125EB (2.5V/3.3V) devices.
2. tLCTHRUL quoted bit by bit.
iming v.0.3
ispXPGA 125B/C & ispXPGA 125EB/EC PIC Timing Parameters
51
-4
-3
Parameter
Description
Min. Max. Min. Max. MinMax. Units
Register/Latch Delays
tIO_CO
tIO_S
Register Clock to Output Delay
—
0.05
0.06
-0.
0.13
—
0.89
—
—
0.05
-0.03
0.13
—
0.9
—
—
0.06
0.07
-0.03
0.15
—
1.10
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Register Setup Time (Data before Clo
Register Hold Time (Data after Clock)
Register Clock Enable Setup Tme
Register Clock Enable Holme
Latch Gate to Output Delay
tIO_H
—
—
tIOCE_S
tIOCE_H
tIO_GO
tIOL_S
—
—
—
—
—
0.8
—
0.73
—
0.84
—
Latch Setup Time
0.
0.06
—
0.05
0.06
—
0.06
0.07
—
tIOL_H
Latch Hold Time
—
—
—
tIOLPD
tIOASRO
tIOASRPW
tIOASRR
Latch Propaation elay (Tnsparent Mode)
Asynchroous Set/Reset to Output
AsynchrouSet/Reset Pulse Widt
AsynchronoSeReset Recovery T
0.09
1.00
—
0.10
1.08
—
0.12
1.24
—
—
—
—
4.19
—
4.50
—
5.18
—
0.23
0.25
0.29
Input/Output elays
tIOBUF Outt Buer Delay
tIOIN
—
—
—
—
—
0.97
0.57
0.53
-0.14
0.19
—
—
—
—
—
1.04
0.61
0.57
-0.13
0.20
—
—
—
—
—
1.20
0.70
0.66
-0.11
0.23
ns
ns
ns
ns
ns
nput Bffer Delay
Outut Enable Del
utput Disable De
Feed-thru Dela
tIOEN
tIODIS
tFT
1. Only ailable for ispX125B d ispXPGA 125EB (2.5V/3.3V) devices.
Timing v.0.3
29
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 125B/C & ispXPGA 125EB/EC EBR Timing Parameters
-51
-4
-3
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
Synchronous Write
tEBSWAD_S Address Setup Delay
tEBSWAD_H Address Hold Delay
0.59
-0.40
3.16
-0.12
0.16
0.27
-0.27
—
—
—
—
—
0.61
-0.39
3.4
-2
0.16
0.28
-0.2
—
—
—
—
—
—
—
0.70
-0.33
3.9
-0.10
0.18
0.32
-0.22
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tEBSWCPW
Clock Pulse Width
tEBSWWE_S Write Enable Setup Time
tEBSWWE_H Write Enable Hold Time
tEBSWD_S
tEBSWD_H
Data Setup Time
Data Hold Time
Synchronous Read
tEBSR_CO
tEBSRAD_S
tEBSRAD_H
tEBSRCPW
tEBSRCE_S
tEBSRCE_H
Clock to Data Delay
0.1
-
3.16
1.76
1.64
-0.18
0.12
—
4
—
—
0.10
-0.07
3.40
.71
1.6
.17
—
2.19
—
02
-0.06
.1
-1.45
1.94
-0.14
0.14
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Delay
Address Hold Delay
Clock Pulse Width
—
—
—
—
—
—
Clock Enable Setup Time
Clock Enable Hold Time
—
—
—
—
—
—
tEBSRWE_S Write Enable Setup Time
—
—
—
tEBSRWE_H Write Enable Hold Time
—
—
tEBSRWEEN Write Enable to Data Enable me
tEBSRWEDIS Write Enable to Data Disale ime
1.0
99
1.02
0.83
1.05
1.02
1.05
0.86
1.21
1.17
1.21
0.99
—
—
—
tEBSREN
tEBSRDIS
Output Enable to Data Enable Te
Output Enable to Dta Disable Time
—
—
—
—
—
—
Asynchronous Read
tEBARADO Address to ew VaData elay
tEBARAD_H Address o Preous Valid Data Delay
—
—
—
—
—
—
2.39
2.10
1.01
0.98
1.02
0.83
—
—
—
—
—
—
2.46
2.17
1.04
1.01
1.05
0.86
—
—
—
—
—
—
2.83
2.50
1.20
1.16
1.21
0.99
ns
ns
ns
ns
ns
tEBARWEEN Write Enato DatEnable Time
tEBARWEDIS Write Enable ata Disable Time
tEBAREN
tEBARDI
Oput Enable to Data EnabTime
OutpEble to Data Disae Time
ns
1. Onavaile for ispXPGA 125B and ispXPG125EB 2.5V/3.3V) devices.
Timing v.0.3
30
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 125B/C & ispXPGA 125EB/EC Timing Adders
-51
-4
-3
Base
Parameter
Optional Adders
tIOINDLY
Description
Input Delay
Parameter Min. Max. Min. Max. Min. Max. Units
—
—
4.28
—
46
5.29
ns
tIOI Input Adjusters
LVTTL_in
Using 3.3V TTL
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tN
tIOIN
—
—
—
—
—
—
—
—
—
0.5
0.0
0.
0.5
0
1.0
0
0.5
0.5
0.5
0.8
—
—
—
—
—
—
—
—
—
0.5
0.0
0
0.5
1.0
1.0
1.0
5
0.5
.5
0
—
—
—
—
—
—
—
—
—
—
0.5
0.0
0.3
0.5
0.5
0.5
0.5
0.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS_18_in
LVCMOS_25_in
LVCMOS_33_in
AGP_1X_in
CTT25_in
Using 1.8V CMOS
Using 2.5V CMOS
Using 3.3V CMOS
Using AGP 1x
Using CTT 2.5V
CTT33_in
Using CTT 3.3V
GTL+_in
Using GTL+
HSTL_I_in
Using HSTL 2.5V, Class I
Using HSTL 2.5V, Class III
HSTL_III_in
LVDS_in
Using Low Voltage
Differential Signaling (LVD
BLVDS_in
Using Bus Low Voltage
Differential Signaling (BL
—
0.8
—
0.8
—
0.8
ns
LVPECL_in
PCI_in
Using Low Voltage PECL
Using PCI
OIN
tIOIN
tIOIN
tIOIN
tIOIN
tI
—
—
—
—
8
1.0
8
0.5
0.8
0.8
—
—
—
—
—
—
0.8
1.0
0.8
0.5
0.8
0.8
—
—
—
—
—
—
0.8
1.0
0.8
0.5
0.8
0.8
ns
ns
ns
ns
ns
ns
SSTL2_I_in
SSTL2_II_in
SSTL3_I_in
SSTL3_II_in
Using SSTL 2.5VClass I
Using L 2.5V, Cs II
UsiSSTL 3.3V, Class I
UsinSSTL 3V, Class II
tIOO Output Adjusters
Slow Slew
Using Slow Slew (LVTTUF, tIOEN
LVCOS Outputs only
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL_out
ing 3.3V TTL Dive
BUF, IOEN,
t
tIODIS
LVCMO_18_4mAut
Using 1.8V COS Stanard, tIOBUF, IOEN,
t
4mA Drive tIODIS
LVCMO8_5.3mA_out Usin1.8V CMOS Standard, tIOBUF, IOEN,
t
5.33A ve tIODIS
LVO_18_8mA_out
ing 1.8V COS Standard, tIOBUF, IOEN,
t
8mDrivtIODIS
LVOS_18_12mAsing 8V CMOS Standard, tIOBUF, IOEN,
t
mA Drive tIODIS
LVCMOS_25_4mA_o
ng 2.5V CMOS Standard, tIOBUF, IOEN,
t
mA Drive tIODIS
LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
5.33 mA Drive tIODIS
LVCMOS_25_8mA_out
Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
8mA Drive tIODIS
LVCMOS_25_12mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
12mA Drive tIODIS
LVCMOS_25_16mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
16mA Drive tIODIS
31
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 125B/C & ispXPGA 125EB/EC Timing Adders (Cont.)
-51
Parameter Min. Max. Min. Max. Min. Max. Units
Using 3.3V CMOS Standard, tIOBUF, IOEN,
4mA Drive tIODIS
IOBUF, tIOEN,
tIODIS
-4
-3
Base
Parameter
Description
LVCMOS_33_4mA_out
t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
0.7
0.5
.5
0.5
0.5
0.5
0.5
0.5
0.
5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
10
0.7
0.
0.5
0.5
5
0.5
0.
0.5
0.5
0.5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
0.7
0.5
5
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard,
5.33mA Drive
t
LVCMOS_33_8mA_out
Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
8mA Drive tIODIS
LVCMOS_33_12mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
12mA Drive tIODIS
LVCMOS_33_16mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
16mA Drive tIODIS
LVCMOS_33_24mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
24mA Drive
tIODIS
tIOBUF, IO
tIODIS
tIUF, IN,
tIOS
tIOBUOE
IS
F, IOEN,
IS
IOBUF, IOEN,
tIODIS
tIOBUF, IEN,
tIODIS
tIOBUF, IN,
AGP_1X_out
CTT25_out
CTT33_out
GTL+_out
Using AGP 1x Standard
t
Using CTT 2.5V
t
Using CTT 3.3V
t
Using GTL+
t
HSTL_I_out
HSTL_III_out
LVDS_out
Using HSTL 2.5, Class I
Using HSTL 2.5VClass III
t
t
UsiLow Voltage Differen-
tial gnaling VDS)
t
BLVDS_out
LVPECL_out
PCI_out
Using us LVoltage Differ- tIOF, tIOEN,
enial Signaling (BLVDS)
tODIS
UF, IOEN,
IS
OBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
Using ow Voltage PE
t
Using PCI Stan
t
SSTL2_out
SSTL2_Iut
SL3_out
SSTL3_II_out
Using SSTL 2V, Clas
UsinSSTL .5V, Class II
Ung SSTL 33V, Class I
ing STL 3.3V, Class II
t
t
t
t
1. Only available for ispXB and ispXPGA 125EB (2.5V/3.3V) devices.
Timing v.0.3
32
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 200B/C & ispXPGA 200EB/EC External Switching Characteristics
Over Recommended Operating Conditions
-51
Min. Max. Min. Max. Min. Max. Units
-4
-3
Parameter
Description
Conditions
Global Clock Input to Out- PIO Output Register
put
tCO
—
-2.0
3.7
5.5
—
—
-.0
3
9
—
-17
4.4
6.8
—
ns
ns
PIO Input Register without input
delay
tS
Global Clock Input Setup
Global Clock Input Hold
PIO Input Register without input
delay
tH
tSINDLY
tHINDLY
tCOPLL
—
—
—
ns
ns
Global Clock Input Setup PIO Input Register with input delay 3.8
—
—
3.8
0
—
—
4.4
0.
—
Global Clock Input Hold
PIO Input Register with input delay 0.0
Global Clock Input to
Output
PIO Output Register using PLL
without delay
—
3.3
—
—
—
—
—
3.6
—
—
—
—
0.1
18
7.3
-2.2
—
—
—
—
ns
ns
ns
ns
PIO Input Register without input
.2
tSPLL
Global Clock Input Setup
Global Clock Input Hold
-0.2
1.5
3
2.6
delay using PLL without delay
PIO Input Register witout input
1.5
tHPLL
delay using PLL withut dey
PIO Input Register with ut dey
6.3
tSINDLYPLL Global Clock Input Setup
tHINDLYPLL Global Clock Input Hold
using PLL witlay
PIO Input nput delay
-2.
ns
using PLL wi
1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V) devices.
Timing v.0.2
33
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 200B/C & ispXPGA 200EB/EC PFU Timing Parameters
Over Recommended Operating Conditions
-51
-4
-3
Parameter
Functional Delays
LUTs
Description
Min. Max. Min. Max. Min. Max. Units
tLUT4
tLUT5
tLUT6
4-Input LUT Delay
—
—
—
0.41
0.73
0.8
—
—
0.44
0.79
0.9
—
—
0.51
0.91
1.07
ns
ns
ns
5-Input LUT Delay
6-Input LUT Delay
Shift Register (LUT)
tLSR_S
tLSR_H
tLSR_CO
Shift Register Setup Time
Shift Register Hold Time
Shift Register Clock to Output Delay
-0.64
061
—
-0.6
.63
—
—
—
-0.5
0.7
—
ns
ns
ns
00
0.75
Arithmetic Functions
tLCTHRUR MC (Macro Cell) Carry In to MC Carry Out Delay (ipple)
—
—
—
—
—
0.08
0.05
0.42
0.29
0.36
6
—
—
—
—
0.09
05
0.4
0.
0.39
0.28
—
—
—
—
—
0.10
0.06
0.52
0.36
0.45
0.32
ns
ns
ns
ns
ns
ns
2
tLCTHRUL
tLSTHRU
MC Carry In to MC Carry Out Delay (Look Ahed)
MC Sum In to MC Sum Out Delay
tLSINCOUT
MC Sum In to MC Carry Out Delay
tLCINSOUTR MC Carry In to MC Sum Out Delay (R
tLCINSOUTL MC Carry In to MC Sum Out Delay (Look
Feed-thru
tLFT
PFU Feed-Thru Delay
—
15
—
0.16
—
0.18
ns
Distributed RAM
tLRAM_CO
tLRAMAD_S
tLRAMD_S
Clock to RAM Outut
—
1.24
—
—
1.33
—
—
1.53
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Tie
Data Setup Time
-0.41
0.21
0.45
0.58
0.11
0.12
2.91
—
-0.40
0.22
0.46
0.60
0.11
0.12
3.00
—
-0.34
0.25
0.53
0.69
0.13
0.14
3.45
—
—
—
—
tLRAMWE_S Write Eble Stup Time
—
—
—
tLRAMAD_H
tLRAMD_H
Address HTime
Data Hold Tim
—
—
—
—
—
—
tLRAMWE_We EnablHold Time
tLRAMCW Clock ue Width (High or ow)
tLRAMAO Address to Output D
—
—
—
—
—
—
0.86
0.93
1.07
gisteratch Delays
Regers
tL_CO
tL_S
Register Clock tutpuelay
—
0.58
—
—
0.62
—
—
0.71
—
ns
ns
ns
ns
ns
RegistTime Data before Clock)
Regie (Data after Clock)
Register nable Setup Time
Register Clock Enable Hold Time
0.14
-0.12
-0.11
0.11
0.14
-0.12
-0.11
0.11
0.16
-0.10
-0.09
0.13
tL_H
—
—
—
tLCE_S
tLCE_H
Latches
tL_GO
tLL_S
—
—
—
—
—
—
Latch Gate to Output Delay
Latch Setup Time
—
0.14
-0.12
—
0.09
—
—
0.14
-0.12
—
0.10
—
—
0.16
-0.10
—
0.12
—
ns
ns
ns
ns
tLL_H
Latch Hold Time
—
—
—
tLLPD
Latch Propagation Delay (Transparent Mode)
0.09
0.10
0.12
34
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 200B/C & ispXPGA 200EB/EC PFU Timing Parameters (Cont.)
Over Recommended Operating Conditions
-51
-4
-3
Parameter
Reset/Set
tLASSRO
Description
Min. Max. Min. Max. Min. Max. Units
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Pulse Width
Asynchronous Set/Reset Recovery
Synchronous Set/Reset Setup Time
Synchronous Set/Reset Hold Time
—
4.19
—
1.09
—
—
4.5
1.1
—
—
5.1
—
1.35
—
ns
ns
tLASSRPW
tLASSRR
0.51
—
.55
—
0.63
—
ns
tLSSR_S
-0.03
0.03
-0.03
0.03
-0.03
0.03
ns
tLSSR_H
—
—
ns
1. Only available for ispXPGA 200B and ispXPGA 200EB (2.5V/3.3V) devices.
2. tLCTHRUL quoted bit by bit.
iming v.0.3
ispXPGA 200B/C & ispXPGA 200EB/EC PIC Timing Parameters
51
-4
-3
Parameter
Description
Min. Max. Min. Max. MinMax. Units
Register/Latch Delays
tIO_CO
tIO_S
Register Clock to Output Delay
—
0.05
0.06
-0.
0.13
—
0.93
—
—
0.05
-0.03
0.13
—
1.0
—
—
0.06
0.07
-0.03
0.15
—
1.15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Register Setup Time (Data before Clo
Register Hold Time (Data after Clock)
Register Clock Enable Setup Tme
Register Clock Enable Holme
Latch Gate to Output Delay
tIO_H
—
—
tIOCE_S
tIOCE_H
tIO_GO
tIOL_S
—
—
—
—
—
0.2
—
0.77
—
0.89
—
Latch Setup Time
0.
0.06
—
0.05
0.06
—
0.06
0.07
—
tIOL_H
Latch Hold Time
—
—
—
tIOLPD
tIOASRO
tIOASRPW
tIOASRR
Latch Propaation elay (Tnsparent Mode)
Asynchroous Set/Reset to Output
AsynchrouSet/Reset Pulse Widt
AsynchronoSeReset Recovery T
0.09
1.04
—
0.10
1.12
—
0.12
1.29
—
—
—
—
4.19
—
4.50
—
5.18
—
0.23
0.25
0.29
Input/Output elays
tIOBUF Outt Buer Delay
tIOIN
—
—
—
—
—
0.97
0.60
0.53
-0.13
0.19
—
—
—
—
—
1.04
0.64
0.57
-0.12
0.20
—
—
—
—
—
1.20
0.74
0.66
-0.10
0.23
ns
ns
ns
ns
ns
nput Bffer Delay
Outut Enable Del
utput Disable De
Feed-thru Dela
tIOEN
tIODIS
tFT
1. Only ailable for ispX200B d ispXPGA 200EB (2.5V/3.3V) devices.
Timing v.0.3
35
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 200B/C & ispXPGA 200EB/EC EBR Timing Parameters
-51
-4
-3
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
Synchronous Write
tEBSWAD_S Address Setup Delay
tEBSWAD_H Address Hold Delay
0.59
-0.40
3.16
-0.12
0.16
0.27
-0.27
—
—
—
—
—
0.61
-0.39
3.4
-2
0.16
0.28
-0.2
—
—
—
—
—
—
—
0.70
-0.33
3.9
-0.10
0.18
0.32
-0.22
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tEBSWCPW
Clock Pulse Width
tEBSWWE_S Write Enable Setup Time
tEBSWWE_H Write Enable Hold Time
tEBSWD_S
tEBSWD_H
Data Setup Time
Data Hold Time
Synchronous Read
tEBSR_CO
tEBSRAD_S
tEBSRAD_H
tEBSRCPW
tEBSRCE_S
tEBSRCE_H
Clock to Data Delay
0.1
-
3.16
1.76
1.64
-0.18
0.12
—
4
—
—
0.10
-0.07
3.40
.71
1.6
.17
—
2.19
—
02
-0.06
.1
-1.45
1.94
-0.14
0.14
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Delay
Address Hold Delay
Clock Pulse Width
—
—
—
—
—
—
Clock Enable Setup Time
Clock Enable Hold Time
—
—
—
—
—
—
tEBSRWE_S Write Enable Setup Time
—
—
—
tEBSRWE_H Write Enable Hold Time
—
—
tEBSRWEEN Write Enable to Data Enable me
tEBSRWEDIS Write Enable to Data Disale ime
1.0
99
1.02
0.83
1.05
1.02
1.05
0.86
1.21
1.17
1.21
0.99
—
—
—
tEBSREN
tEBSRDIS
Output Enable to Data Enable Te
Output Enable to Dta Disable Time
—
—
—
—
—
—
Asynchronous Read
tEBARADO Address to ew VaData elay
tEBARAD_H Address o Preous Valid Data Delay
—
—
—
—
—
—
2.39
2.10
1.01
0.98
1.02
0.83
—
—
—
—
—
—
2.46
2.17
1.04
1.01
1.05
0.86
—
—
—
—
—
—
2.83
2.50
1.20
1.16
1.21
0.99
ns
ns
ns
ns
ns
tEBARWEEN Write Enato DatEnable Time
tEBARWEDIS Write Enable ata Disable Time
tEBAREN
tEBARDI
Oput Enable to Data EnabTime
OutpEble to Data Disae Time
ns
1. Onavaile for ispXPGA 200B and ispXPG200EB 2.5V/3.3V) devices.
Timing v.0.3
36
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 200B/C & ispXPGA 200EB/EC Timing Adders
-51
-4
-3
Base
Parameter
Optional Adders
tIOINDLY
Description
Input Delay
Parameter Min. Max. Min. Max. Min. Max. Units
—
—
4.84
—
52
5.98
ns
tIOI Input Adjusters
LVTTL_in
Using 3.3V TTL
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tN
tIOIN
—
—
—
—
—
—
—
—
—
0.5
0.0
0.
0.5
0
1.0
0
0.5
0.5
0.5
0.8
—
—
—
—
—
—
—
—
—
0.5
0.0
0
0.5
1.0
1.0
1.0
5
0.5
.5
0
—
—
—
—
—
—
—
—
—
—
0.5
0.0
0.3
0.5
0.5
0.5
0.5
0.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS_18_in
LVCMOS_25_in
LVCMOS_33_in
AGP_1X_in
CTT25_in
Using 1.8V CMOS
Using 2.5V CMOS
Using 3.3V CMOS
Using AGP 1x
Using CTT 2.5V
CTT33_in
Using CTT 3.3V
GTL+_in
Using GTL+
HSTL_I_in
Using HSTL 2.5V, Class I
Using HSTL 2.5V, Class III
HSTL_III_in
LVDS_in
Using Low Voltage
Differential Signaling (LVD
BLVDS_in
Using Bus Low Voltage
Differential Signaling (BL
—
0.8
—
0.8
—
0.8
ns
LVPECL_in
PCI_in
Using Low Voltage PECL
Using PCI
OIN
tIOIN
tIOIN
tIOIN
tIOIN
tI
—
—
—
—
8
1.0
8
0.5
0.8
0.8
—
—
—
—
—
—
0.8
1.0
0.8
0.5
0.8
0.8
—
—
—
—
—
—
0.8
1.0
0.8
0.5
0.8
0.8
ns
ns
ns
ns
ns
ns
SSTL2_I_in
SSTL2_II_in
SSTL3_I_in
SSTL3_II_in
Using SSTL 2.5VClass I
Using L 2.5V, Cs II
UsiSSTL 3.3V, Class I
UsinSSTL 3V, Class II
tIOO Output Adjusters
Slow Slew
Using Slow Slew (LVTTUF, tIOEN
LVCOS Outputs only
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL_out
ing 3.3V TTL Dive
BUF, IOEN,
t
tIODIS
LVCMO_18_4mAut
Using 1.8V COS Stanard, tIOBUF, IOEN,
t
4mA Drive tIODIS
LVCMO8_5.3mA_out Usin1.8V CMOS Standard, tIOBUF, IOEN,
t
5.33A ve tIODIS
LVO_18_8mA_out
ing 1.8V COS Standard, tIOBUF, IOEN,
t
8mDrivtIODIS
LVOS_18_12mAsing 8V CMOS Standard, tIOBUF, IOEN,
t
mA Drive tIODIS
LVCMOS_25_4mA_o
ng 2.5V CMOS Standard, tIOBUF, IOEN,
t
mA Drive tIODIS
LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
5.33 mA Drive tIODIS
LVCMOS_25_8mA_out
Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
8mA Drive tIODIS
LVCMOS_25_12mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
12mA Drive tIODIS
LVCMOS_25_16mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
16mA Drive tIODIS
37
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 200B/C & ispXPGA 200EB/EC Timing Adders (Cont.)
-51
Parameter Min. Max. Min. Max. Min. Max. Units
Using 3.3V CMOS Standard, tIOBUF, IOEN,
4mA Drive tIODIS
IOBUF, tIOEN,
tIODIS
-4
-3
Base
Parameter
Description
LVCMOS_33_4mA_out
t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
0.7
0.5
.5
0.5
0.5
0.5
0.5
0.5
0.
5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
10
0.7
0.
0.5
0.5
5
0.5
0.
0.5
0.5
0.5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
0.7
0.5
5
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard,
5.33mA Drive
t
LVCMOS_33_8mA_out
Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
8mA Drive tIODIS
LVCMOS_33_12mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
12mA Drive tIODIS
LVCMOS_33_16mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
16mA Drive tIODIS
LVCMOS_33_24mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
24mA Drive
tIODIS
tIOBUF, IO
tIODIS
tIUF, IN,
tIOS
tIOBUOE
IS
F, IOEN,
IS
IOBUF, IOEN,
tIODIS
tIOBUF, IEN,
tIODIS
tIOBUF, IN,
AGP_1X_out
CTT25_out
CTT33_out
GTL+_out
Using AGP 1x Standard
t
Using CTT 2.5V
t
Using CTT 3.3V
t
Using GTL+
t
HSTL_I_out
HSTL_III_out
LVDS_out
Using HSTL 2.5, Class I
Using HSTL 2.5VClass III
t
t
UsiLow Voltage Differen-
tial gnaling VDS)
t
BLVDS_out
LVPECL_out
PCI_out
Using us LVoltage Differ- tIOF, tIOEN,
enial Signaling (BLVDS)
tODIS
UF, IOEN,
IS
OBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
Using ow Voltage PE
t
Using PCI Stan
t
SSTL2_out
SSTL2_Iut
SL3_out
SSTL3_II_out
Using SSTL 2V, Clas
UsinSSTL .5V, Class II
Ung SSTL 33V, Class I
ing STL 3.3V, Class II
t
t
t
t
1. Only available for ispXB and ispXPGA 200EB (2.5V/3.3V) devices.
Timing v.0.3
38
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 500B/C & ispXPGA 500EB/EC External Switching Characteristics
Over Recommended Operating Conditions
-51
Min. Max. Min. Max. Min. Max. Units
-4
-3
Parameter
Description
Conditions
Global Clock Input to Out- PIO Output Register
put
tCO
—
-2.9
3.6
6.4
—
—
-.7
3
9
—
-23
4.5
7.9
—
ns
ns
PIO Input Register without input
delay
tS
Global Clock Input Setup
Global Clock Input Hold
PIO Input Register without input
delay
tH
tSINDLY
tHINDLY
tCOPLL
—
—
—
ns
ns
Global Clock Input Setup PIO Input Register with input delay 3.3
—
—
3.6
0
—
—
4.1
0.
—
Global Clock Input Hold
PIO Input Register with input delay 0.0
Global Clock Input to
Output
PIO Output Register using PLL
without delay
—
3.2
—
—
—
—
—
0.2
0.9
2
4.0
3.4
—
—
—
—
0.3
10
8.3
-3.4
—
—
—
—
ns
ns
ns
ns
PIO Input Register without input
.1
tSPLL
Global Clock Input Setup
Global Clock Input Hold
delay using PLL without delay
PIO Input Register witout input
0.8
tHPLL
delay using PLL withut dey
PIO Input Register with ut dey
6.7
tSINDLYPLL Global Clock Input Setup
tHINDLYPLL Global Clock Input Hold
using PLL witlay
PIO Input nput delay
-4.
ns
using PLL wi
1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V) devices.
Timing v.0.3
39
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 500B/C & ispXPGA 500EB/EC PFU Timing Parameters
Over Recommended Operating Conditions
-51
-4
-3
Parameter
Functional Delays
LUTs
Description
Min. Max. Min. Max. Min. Max. Units
tLUT4
tLUT5
tLUT6
4-Input LUT Delay
—
—
—
0.41
0.73
0.8
—
—
0.44
0.79
0.9
—
—
0.51
0.91
1.07
ns
ns
ns
5-Input LUT Delay
6-Input LUT Delay
Shift Register (LUT)
tLSR_S
tLSR_H
tLSR_CO
Shift Register Setup Time
Shift Register Hold Time
Shift Register Clock to Output Delay
-0.64
061
—
-0.6
.63
—
—
—
-0.5
0.7
—
ns
ns
ns
00
0.75
Arithmetic Functions
tLCTHRUR MC (Macro Cell) Carry In to MC Carry Out Delay (ipple)
—
—
—
—
—
0.08
0.05
0.42
0.29
0.36
6
—
—
—
—
0.09
05
0.4
0.
0.39
0.28
—
—
—
—
—
0.10
0.06
0.52
0.36
0.45
0.32
ns
ns
ns
ns
ns
ns
2
tLCTHRUL
tLSTHRU
MC Carry In to MC Carry Out Delay (Look Ahed)
MC Sum In to MC Sum Out Delay
tLSINCOUT
MC Sum In to MC Carry Out Delay
tLCINSOUTR MC Carry In to MC Sum Out Delay (R
tLCINSOUTL MC Carry In to MC Sum Out Delay (Look
Feed-thru
tLFT
PFU Feed-Thru Delay
—
15
—
0.16
—
0.18
ns
Distributed RAM
tLRAM_CO
tLRAMAD_S
tLRAMD_S
Clock to RAM Outut
—
1.24
—
—
1.33
—
—
1.53
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Tie
Data Setup Time
-0.41
0.21
0.45
0.58
0.11
0.12
2.91
—
-0.40
0.22
0.46
0.60
0.11
0.12
3.00
—
-0.34
0.25
0.53
0.69
0.13
0.14
3.45
—
—
—
—
tLRAMWE_S Write Eble Stup Time
—
—
—
tLRAMAD_H
tLRAMD_H
Address HTime
Data Hold Tim
—
—
—
—
—
—
tLRAMWE_We EnablHold Time
tLRAMCW Clock ue Width (High or ow)
tLRAMAO Address to Output D
—
—
—
—
—
—
0.86
0.93
1.07
gisteratch Delays
Regers
tL_CO
tL_S
Register Clock tutpuelay
—
0.58
—
—
0.62
—
—
0.71
—
ns
ns
ns
ns
ns
RegistTime Data before Clock)
Regie (Data after Clock)
Register nable Setup Time
Register Clock Enable Hold Time
0.14
-0.12
-0.11
0.11
0.14
-0.12
-0.11
0.11
0.16
-0.10
-0.09
0.13
tL_H
—
—
—
tLCE_S
tLCE_H
Latches
tL_GO
tLL_S
—
—
—
—
—
—
Latch Gate to Output Delay
Latch Setup Time
—
0.14
-0.12
—
0.09
—
—
0.14
-0.12
—
0.10
—
—
0.16
-0.10
—
0.12
—
ns
ns
ns
ns
tLL_H
Latch Hold Time
—
—
—
tLLPD
Latch Propagation Delay (Transparent Mode)
0.09
0.10
0.12
40
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 500B/C & ispXPGA 500EB/EC PFU Timing Parameters (Cont.)
Over Recommended Operating Conditions
-51
-4
-3
Parameter
Reset/Set
tLASSRO
Description
Min. Max. Min. Max. Min. Max. Units
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Pulse Width
Asynchronous Set/Reset Recovery
Synchronous Set/Reset Setup Time
Synchronous Set/Reset Hold Time
—
4.19
—
1.09
—
—
4.5
1.1
—
—
5.1
—
1.35
—
ns
ns
ns
ns
tLASSRPW
tLASSRR
0.51
—
.55
—
0.63
—
tLSSR_S
-0.03
0.03
-0.03
0.03
-0.03
0.03
tLSSR_H
—
—
ns
1. Only available for ispXPGA 500B and ispXPGA 500EB (2.5V/3.3V) devices.
2. tLCTHRUL quoted bit by bit.
Timing v.0.3
ispXPGA 500B/C & ispXPGA 500EB/EC PIC Timing Parameters
51
-4
-3
Parameter
Description
Min. Max. Min. Max. MinMax. Units
Register/Latch Delays
tIO_CO
tIO_S
Register Clock to Output Delay
—
0.05
0.06
-0.
0.13
—
1.00
—
0.05
6
-0.03
0.13
—
1.0
—
—
0.06
0.07
-0.03
0.15
—
1.23
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Register Setup Time (Data before Clo
Register Hold Time (Data after Clock)
Register Clock Enable Setup Tme
Register Clock Enable Hold me
Latch Gate to Output Delay
tIO_H
—
—
tIOCE_S
tIOCE_H
tIO_GO
tIOL_S
—
—
—
—
0.8
—
0.84
—
0.97
—
Latch Setup Time
0.
0.06
—
0.05
0.06
—
0.06
0.07
—
tIOL_H
Latch Hold Time
—
—
—
tIOLPD
tIOASRO
tIOASRPW
tIOASRR
Latch Propagation elay (Tnsparent Mode)
Asynchroous Set/Resto Output
AsynchrouSet/Reset Pulse Widt
AsynchronoSeReset Recovery T
0.09
1.11
—
0.10
1.19
—
0.12
1.37
—
—
—
—
4.19
—
4.50
—
5.18
—
0.23
0.25
0.29
Input/Output elays
tIOBUF Outt Bufr Delay
tIOIN
—
—
—
—
—
0.98
0.65
0.52
-0.12
0.19
—
—
—
—
—
1.05
0.70
0.56
-0.11
0.20
—
—
—
—
—
1.21
0.81
0.64
-0.09
0.23
ns
ns
ns
ns
ns
nput Bffer Delay
Outut Enable Del
utput Disable Dey
Feed-thru Dela
tIOEN
tIODIS
tT
1. Only ailable for ispXPA 500B nd ispXPGA 500EB (2.5V/3.3V) devices.
Timing v.0.3
41
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 500B/C & ispXPGA 500EB/EC EBR Timing Parameters
-51
-4
-3
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
Synchronous Write
tEBSWAD_S Address Setup Delay
tEBSWAD_H Address Hold Delay
0.59
-0.40
3.16
-0.12
0.16
0.27
-0.27
—
—
—
—
—
0.61
-0.39
3.4
-2
0.16
0.28
-0.2
—
—
—
—
—
—
—
0.70
-0.33
3.9
-0.10
0.18
0.32
-0.22
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tEBSWCPW
Clock Pulse Width
tEBSWWE_S Write Enable Setup Time
tEBSWWE_H Write Enable Hold Time
tEBSWD_S
tEBSWD_H
Data Setup Time
Data Hold Time
Synchronous Read
tEBSR_CO
tEBSRAD_S
tEBSRAD_H
tEBSRCPW
tEBSRCE_S
tEBSRCE_H
Clock to Data Delay
0.1
-
3.16
1.76
1.64
-0.18
0.12
—
4
—
—
0.10
-0.07
3.40
.71
1.6
.17
—
2.19
—
02
-0.06
.1
-1.45
1.94
-0.14
0.14
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Delay
Address Hold Delay
Clock Pulse Width
—
—
—
—
—
—
Clock Enable Setup Time
Clock Enable Hold Time
—
—
—
—
—
—
tEBSRWE_S Write Enable Setup Time
—
—
—
tEBSRWE_H Write Enable Hold Time
—
—
tEBSRWEEN Write Enable to Data Enable me
tEBSRWEDIS Write Enable to Data Disale ime
1.0
99
1.02
0.83
1.05
1.02
1.05
0.86
1.21
1.17
1.21
0.99
—
—
—
tEBSREN
tEBSRDIS
Output Enable to Data Enable Te
Output Enable to Dta Disable Time
—
—
—
—
—
—
Asynchronous Read
tEBARADO Address to ew VaData elay
tEBARAD_H Address o Preous Valid Data Delay
—
—
—
—
—
—
2.39
2.10
1.01
0.98
1.02
0.83
—
—
—
—
—
—
2.46
2.17
1.04
1.01
1.05
0.86
—
—
—
—
—
—
2.83
2.50
1.20
1.16
1.21
0.99
ns
ns
ns
ns
ns
tEBARWEEN Write Enato DatEnable Time
tEBARWEDIS Write Enable ata Disable Time
tEBAREN
tEBARDI
Oput Enable to Data EnabTime
OutpEble to Data Disae Time
ns
1. Onavaile for ispXPGA 500B and ispXPG500EB 2.5V/3.3V) devices.
Timing v.0.3
42
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 500B/C & ispXPGA 500EB/EC Timing Adders
-51
-4
-3
Base
Parameter
Optional Adders
tIOINDLY
Description
Input Delay
Parameter Min. Max. Min. Max. Min. Max. Units
—
—
5.21
—
50
6.44
ns
tIOI Input Adjusters
LVTTL_in
Using 3.3V TTL
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tN
tIOIN
—
—
—
—
—
—
—
—
—
0.5
0.0
0.
0.5
0
1.0
0
0.5
0.5
0.5
0.8
—
—
—
—
—
—
—
—
—
0.5
0.0
0
0.5
1.0
1.0
1.0
5
0.5
.5
0
—
—
—
—
—
—
—
—
—
—
0.5
0.0
0.3
0.5
0.5
0.5
0.5
0.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS_18_in
LVCMOS_25_in
LVCMOS_33_in
AGP_1X_in
CTT25_in
Using 1.8V CMOS
Using 2.5V CMOS
Using 3.3V CMOS
Using AGP 1x
Using CTT 2.5V
CTT33_in
Using CTT 3.3V
GTL+_in
Using GTL+
HSTL_I_in
Using HSTL 2.5V, Class I
Using HSTL 2.5V, Class III
HSTL_III_in
LVDS_in
Using Low Voltage
Differential Signaling (LVD
BLVDS_in
Using Bus Low Voltage
Differential Signaling (BL
—
0.8
—
0.8
—
0.8
ns
LVPECL_in
PCI_in
Using Low Voltage PECL
Using PCI
OIN
tIOIN
tIOIN
tIOIN
tIOIN
tI
—
—
—
—
8
1.0
8
0.5
0.8
0.8
—
—
—
—
—
—
0.8
1.0
0.8
0.5
0.8
0.8
—
—
—
—
—
—
0.8
1.0
0.8
0.5
0.8
0.8
ns
ns
ns
ns
ns
ns
SSTL2_I_in
SSTL2_II_in
SSTL3_I_in
SSTL3_II_in
Using SSTL 2.5VClass I
Using L 2.5V, Cs II
UsiSSTL 3.3V, Class I
UsinSSTL 3V, Class II
tIOO Output Adjusters
Slow Slew
Using Slow Slew (LVTTUF, tIOEN
LVCOS Outputs only
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL_out
ing 3.3V TTL Dive
BUF, IOEN,
t
tIODIS
LVCMO_18_4mAut
Using 1.8V COS Stanard, tIOBUF, IOEN,
t
4mA Drive tIODIS
LVCMO8_5.3mA_out Usin1.8V CMOS Standard, tIOBUF, IOEN,
t
5.33A ve tIODIS
LVO_18_8mA_out
ing 1.8V COS Standard, tIOBUF, IOEN,
t
8mDrivtIODIS
LVOS_18_12mAsing 8V CMOS Standard, tIOBUF, IOEN,
t
mA Drive tIODIS
LVCMOS_25_4mA_o
ng 2.5V CMOS Standard, tIOBUF, IOEN,
t
mA Drive tIODIS
LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
5.33 mA Drive tIODIS
LVCMOS_25_8mA_out
Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
8mA Drive tIODIS
LVCMOS_25_12mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
12mA Drive tIODIS
LVCMOS_25_16mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
16mA Drive tIODIS
43
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 500B/C & ispXPGA 500EB/EC Timing Adders (Cont.)
-51
Parameter Min. Max. Min. Max. Min. Max. Units
Using 3.3V CMOS Standard, tIOBUF, IOEN,
4mA Drive tIODIS
IOBUF, tIOEN,
tIODIS
-4
-3
Base
Parameter
Description
LVCMOS_33_4mA_out
t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
0.7
0.5
.5
0.5
0.5
0.5
0.5
0.5
0.
5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
10
0.7
0.
0.5
0.5
5
0.5
0.
0.5
0.5
0.5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
0.7
0.5
5
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard,
5.33mA Drive
t
LVCMOS_33_8mA_out
Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
8mA Drive tIODIS
LVCMOS_33_12mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
12mA Drive tIODIS
LVCMOS_33_16mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
16mA Drive tIODIS
LVCMOS_33_24mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
24mA Drive
tIODIS
tIOBUF, IO
tIODIS
tIUF, IN,
tIOS
tIOBUOE
IS
F, IOEN,
IS
IOBUF, IOEN,
tIODIS
tIOBUF, IEN,
tIODIS
tIOBUF, IN,
AGP_1X_out
CTT25_out
CTT33_out
GTL+_out
Using AGP 1x Standard
t
Using CTT 2.5V
t
Using CTT 3.3V
t
Using GTL+
t
HSTL_I_out
HSTL_III_out
LVDS_out
Using HSTL 2.5, Class I
Using HSTL 2.5VClass III
t
t
UsiLow Voltage Differen-
tial gnaling VDS)
t
BLVDS_out
LVPECL_out
PCI_out
Using us LVoltage Differ- tIOF, tIOEN,
enial Signaling (BLVDS)
tODIS
UF, IOEN,
IS
OBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
Using ow Voltage PE
t
Using PCI Stan
t
SSTL2_out
SSTL2_Iut
SL3_out
SSTL3_II_out
Using SSTL 2V, Clas
UsinSSTL .5V, Class II
Ung SSTL 33V, Class I
ing STL 3.3V, Class II
t
t
t
t
1. Only available for ispXB and ispXPGA 500EB (2.5V/3.3V) devices.
Timing v.0.3
44
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 1200B/C & ispXPGA 1200EB/EC External Switching
Characteristics
Over Recommended Operating Conditions
-51
Min. Max. Min. Mx. Min. Max. Units
-4
-3
Parameter
Description
Conditions
Global Clock Input to Out- PIO Output Register
put
tCO
—
-2.7
4.5
6.6
—
—
2.7
4.6
7.1
—
—
-2.3
5.3
8.2
—
ns
ns
PIO Input Register without input
delay
tS
Global Clock Input Setup
Global Clock Input Hold
PIO Input Register without input
delay
tH
tSINDLY
tHINDLY
tCOPLL
—
—
—
ns
ns
Global Clock Input Setup PIO Input Register with input delay 3.8
—
—
8
0.0
—
—
4.
0
Global Clock Input Hold
PIO Input Register with input dela0.
Global Clock Input to
Output
PIO Output Register using PLL
without delay
—
.1
—
—
—
—
—
0.5
0.8
7.6
-4.0
33
—
—
—
—
0.6
1.0
8.8
-3.4
—
—
—
—
ns
ns
ns
ns
PIO Input Register withot input
tSPLL
Global Clock Input Setup
Global Clock Input Hold
delay using PLL withot delay
PIO Input Register wouinput
0.8
tHPLL
delay using PLL withouelay
PIO Input Reh inpdelay
7.6
tSINDLYPLL Global Clock Input Setup
tHINDLYPLL Global Clock Input Hold
using PLL
PIO Input Regiinput delay
4.1
ns
usinPLL withoulay
1. Only available for ispXPGA 1200B and ispA 1200EB (2.5V/3.3V) device
Timing v.0.2
45
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters
Over Recommended Operating Conditions
-51
-4
-3
Parameter
Functional Delays
LUTs
Description
Min. Max. Min. Max. Min. Max. Units
tLUT4
tLUT5
tLUT6
4-Input LUT Delay
—
—
—
0.41
0.73
0.8
—
—
0.44
0.79
0.9
—
—
0.51
0.91
1.07
ns
ns
ns
5-Input LUT Delay
6-Input LUT Delay
Shift Register (LUT)
tLSR_S
tLSR_H
tLSR_CO
Shift Register Setup Time
Shift Register Hold Time
Shift Register Clock to Output Delay
-0.64
061
—
-0.6
.63
—
—
—
-0.5
0.7
—
ns
ns
ns
00
0.75
Arithmetic Functions
tLCTHRUR MC (Macro Cell) Carry In to MC Carry Out Delay (ipple)
—
—
—
—
—
0.08
0.05
0.42
0.29
0.36
6
—
—
—
—
0.09
05
0.4
0.
0.39
0.28
—
—
—
—
—
0.10
0.06
0.52
0.36
0.45
0.32
ns
ns
ns
ns
ns
ns
2
tLCTHRUL
tLSTHRU
MC Carry In to MC Carry Out Delay (Look Ahed)
MC Sum In to MC Sum Out Delay
tLSINCOUT
MC Sum In to MC Carry Out Delay
tLCINSOUTR MC Carry In to MC Sum Out Delay (R
tLCINSOUTL MC Carry In to MC Sum Out Delay (Look
Feed-thru
tLFT
PFU Feed-Thru Delay
—
15
—
0.16
—
0.18
ns
Distributed RAM
tLRAM_CO
tLRAMAD_S
tLRAMD_S
Clock to RAM Outut
—
1.24
—
—
1.33
—
—
1.53
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Tie
Data Setup Time
-0.41
0.21
0.45
0.58
0.11
0.12
2.91
—
-0.40
0.22
0.46
0.60
0.11
0.12
3.00
—
-0.34
0.25
0.53
0.69
0.13
0.14
3.45
—
—
—
—
tLRAMWE_S Write Eble Stup Time
—
—
—
tLRAMAD_H
tLRAMD_H
Address HTime
Data Hold Tim
—
—
—
—
—
—
tLRAMWE_We EnablHold Time
tLRAMCW Clock ue Width (High or ow)
tLRAMAO Address to Output D
—
—
—
—
—
—
0.86
0.93
1.07
gisteratch Delays
Regrs
tL_CO
tL_S
Register Clock tutpuelay
—
0.58
—
—
0.62
—
—
0.71
—
ns
ns
ns
ns
ns
RegistTime Data before Clock)
Regie (Data after Clock)
Register nable Setup Time
Register Clock Enable Hold Time
0.14
-0.12
-0.11
0.11
0.14
-0.12
-0.11
0.11
0.16
-0.10
-0.09
0.13
tL_H
—
—
—
tLCE_S
tLCE_H
Latches
tL_GO
tLL_S
—
—
—
—
—
—
Latch Gate to Output Delay
Latch Setup Time
—
0.14
-0.12
—
0.09
—
—
0.14
-0.12
—
0.10
—
—
0.16
-0.10
—
0.12
—
ns
ns
ns
ns
tLL_H
Latch Hold Time
—
—
—
tLLPD
Latch Propagation Delay (Transparent Mode)
0.09
0.10
0.12
46
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 1200B/C & ispXPGA 1200EB/EC PFU Timing Parameters (Cont.)
Over Recommended Operating Conditions
-51
-4
-3
Parameter
Reset/Set
tLASSRO
Description
Min. Max. Min. Max. Min. Max. Units
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Pulse Width
Asynchronous Set/Reset Recovery
Synchronous Set/Reset Setup Time
Synchronous Set/Reset Hold Time
—
4.19
—
1.09
—
—
4.5
1.1
—
—
5.1
—
1.35
—
ns
ns
ns
ns
tLASSRPW
tLASSRR
0.51
—
.55
—
0.63
—
tLSSR_S
-0.03
0.03
-0.03
0.03
-0.03
0.03
tLSSR_H
—
—
ns
1. Only available for ispXPGA 1200B and ispXPGA 1200EB (2.5V/3.3V) devices.
2. tLCTHRUL quoted bit by bit.
Timing v.2.1
ispXPGA 1200B/C & ispXPGA 1200EB/EC PIC ming Paramters
-51
-4
-3
Parameter
Description
Min. Max. n. MaMin. Max. Units
Register/Latch Delays
tIO_CO
tIO_S
Register Clock to Output Delay
—
0.05
0.06
-0.03
13
—
1.01
—
0
0.06
-0.03
0.13
—
1.09
—
—
0.06
0.07
-0.03
0.15
—
1.25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Register Setup Time (Data before Clock)
Register Hold Time (Data aftClock)
Register Clock Enable Seup me
Register Clock Enable Hold Tim
Latch Gate to Outt Delay
tIO_H
—
—
—
tIOCE_S
tIOCE_H
tIO_GO
tIOL_S
—
—
—
—
—
0.85
—
0.91
—
1.05
—
Latch Setup Time
0.05
0.06
—
0.05
0.06
—
0.06
0.07
—
tIOL_H
Latch Hold ime
—
—
—
tIOLPD
tIOASRO
tIOASRPW
tIOASRR
Latch Ppagan Delay (Transparent
Asynchrons Set/eset to Output
Asynchronout/Reset Pulse Width
Anchronos Set/Reset Reovery Time
0.09
1.17
—
0.10
1.26
—
0.12
1.45
—
—
—
—
4.19
—
4.50
—
5.18
—
0.23
0.25
0.29
Input/Otput Dela
tIOBUF Output Buffer Delay
tN
—
—
—
—
—
0.99
0.71
0.52
-0.11
0.19
—
—
—
—
—
1.06
0.76
0.56
-0.10
0.20
—
—
—
—
—
1.22
0.87
0.64
-0.09
0.23
ns
ns
ns
ns
ns
Inut Buffer Delay
Output EnablDelay
Output Disable lay
Feed-ty
tIOE
tIODIS
tIOF
1. Only available for B and ispXPGA 1200EB (2.5V/3.3V) devices.
Timing v.2.1
47
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 1200B/C & ispXPGA 1200EB/EC EBR Timing Parameters
-51
-4
-3
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
Synchronous Write
tEBSWAD_S Address Setup Delay
tEBSWAD_H Address Hold Delay
0.59
-0.40
3.16
-0.12
0.16
0.27
-0.27
—
—
—
—
—
0.61
-0.39
3.4
-2
0.16
0.28
-0.2
—
—
—
—
—
—
—
0.70
-0.33
3.9
-0.10
0.18
0.32
-0.22
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
tEBSWCPW
Clock Pulse Width
tEBSWWE_S Write Enable Setup Time
tEBSWWE_H Write Enable Hold Time
tEBSWD_S
tEBSWD_H
Data Setup Time
Data Hold Time
Synchronous Read
tEBSR_CO
tEBSRAD_S
tEBSRAD_H
tEBSRCPW
tEBSRCE_S
tEBSRCE_H
Clock to Data Delay
0.1
-
3.16
1.76
1.64
-0.18
0.12
—
4
—
—
0.10
-0.07
3.40
.71
1.6
.17
—
2.19
—
02
-0.06
.1
-1.45
1.94
-0.14
0.14
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Delay
Address Hold Delay
Clock Pulse Width
—
—
—
—
—
—
Clock Enable Setup Time
Clock Enable Hold Time
—
—
—
—
—
—
tEBSRWE_S Write Enable Setup Time
—
—
—
tEBSRWE_H Write Enable Hold Time
—
—
tEBSRWEEN Write Enable to Data Enable me
tEBSRWEDIS Write Enable to Data Disale ime
1.0
99
1.02
0.83
1.05
1.02
1.05
0.86
1.21
1.17
1.21
0.99
—
—
—
tEBSREN
tEBSRDIS
Output Enable to Data Enable Te
Output Enable to Dta Disable Time
—
—
—
—
—
—
Asynchronous Read
tEBARADO Address to ew VaData elay
tEBARAD_H Address o Preous Valid Data Delay
—
—
—
—
—
—
2.39
2.10
1.01
0.98
1.02
0.83
—
—
—
—
—
—
2.46
2.17
1.04
1.01
1.05
0.86
—
—
—
—
—
—
2.83
2.50
1.20
1.16
1.21
0.99
ns
ns
ns
ns
ns
tEBARWEEN Write Enato DatEnable Time
tEBARWEDIS Write Enable ata Disable Time
tEBAREN
tEBARDI
Oput Enable to Data EnabTime
OutpEble to Data Disae Time
ns
1. Onavaile for ispXPGA 1200B and ispXP1200B (2.5V/3.3V) devices.
Timing v.2.1
48
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 1200B/C & ispXPGA 1200EB/EC Timing Adders
-51
-4
-3
Base
Parameter
Optional Adders
tIOINDLY
Description
Input Delay
Parameter Min. Max. Min. Max. Min. Max. Units
—
—
5.58
—
60
6.90
ns
tIOI Input Adjusters
LVTTL_in
Using 3.3V TTL
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tIOIN
tN
tIOIN
—
—
—
—
—
—
—
—
—
0.5
0.0
0.
0.5
0
1.0
0
0.5
0.5
0.5
0.8
—
—
—
—
—
—
—
—
—
0.5
0.0
0
0.5
1.0
1.0
1.0
5
0.5
.5
0
—
—
—
—
—
—
—
—
—
—
0.5
0.0
0.3
0.5
0.5
0.5
0.5
0.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS_18_in
LVCMOS_25_in
LVCMOS_33_in
AGP_1X_in
CTT25_in
Using 1.8V CMOS
Using 2.5V CMOS
Using 3.3V CMOS
Using AGP 1x
Using CTT 2.5V
CTT33_in
Using CTT 3.3V
GTL+_in
Using GTL+
HSTL_I_in
Using HSTL 2.5V, Class I
Using HSTL 2.5V, Class III
HSTL_III_in
LVDS_in
Using Low Voltage
Differential Signaling (LVD
BLVDS_in
Using Bus Low Voltage
Differential Signaling (BL
—
0.8
—
0.8
—
0.8
ns
LVPECL_in
PCI_in
Using Low Voltage PECL
Using PCI
OIN
tIOIN
tIOIN
tIOIN
tIOIN
tI
—
—
—
—
8
1.0
8
0.5
0.8
0.8
—
—
—
—
—
—
0.8
1.0
0.8
0.5
0.8
0.8
—
—
—
—
—
—
0.8
1.0
0.8
0.5
0.8
0.8
ns
ns
ns
ns
ns
ns
SSTL2_I_in
SSTL2_II_in
SSTL3_I_in
SSTL3_II_in
Using SSTL 2.5VClass I
Using L 2.5V, Cs II
UsiSSTL 3.3V, Class I
UsinSSTL 3V, Class II
tIOO Output Adjusters
Slow Slew
Using Slow Slew (LVTTUF, tIOEN
LVCOS Outputs only
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
0.7
1.0
0.8
0.6
0.0
0.2
0.7
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL_out
ing 3.3V TTL Dive
BUF, IOEN,
t
tIODIS
LVCMO_18_4mAut
Using 1.8V COS Stanard, tIOBUF, IOEN,
t
4mA Drive tIODIS
LVCMO8_5.3mA_out Usin1.8V CMOS Standard, tIOBUF, IOEN,
t
5.33A ve tIODIS
LVO_18_8mA_out
ing 1.8V COS Standard, tIOBUF, IOEN,
t
8mDrivtIODIS
LVOS_18_12mAsing 8V CMOS Standard, tIOBUF, IOEN,
t
mA Drive tIODIS
LVCMOS_25_4mA_o
ng 2.5V CMOS Standard, tIOBUF, IOEN,
t
mA Drive tIODIS
LVCMOS_25_5.33mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
5.33 mA Drive tIODIS
LVCMOS_25_8mA_out
Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
8mA Drive tIODIS
LVCMOS_25_12mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
12mA Drive tIODIS
LVCMOS_25_16mA_out Using 2.5V CMOS Standard, tIOBUF, IOEN,
t
16mA Drive tIODIS
49
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA 1200B/C & ispXPGA 1200EB/EC Timing Adders (Cont.)
-51
Parameter Min. Max. Min. Max. Min. Max. Units
Using 3.3V CMOS Standard, tIOBUF, IOEN,
4mA Drive tIODIS
IOBUF, tIOEN,
tIODIS
-4
-3
Base
Parameter
Description
LVCMOS_33_4mA_out
t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
0.7
0.5
.5
0.5
0.5
0.5
0.5
0.5
0.
5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
10
0.7
0.
0.5
0.5
5
0.5
0.
0.5
0.5
0.5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.0
1.0
0.7
0.5
5
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard,
5.33mA Drive
t
LVCMOS_33_8mA_out
Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
8mA Drive tIODIS
LVCMOS_33_12mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
12mA Drive tIODIS
LVCMOS_33_16mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
16mA Drive tIODIS
LVCMOS_33_24mA_out Using 3.3V CMOS Standard, tIOBUF, IOEN,
t
24mA Drive
tIODIS
tIOBUF, IO
tIODIS
tIUF, IN,
tIOS
tIOBUOE
IS
F, IOEN,
IS
IOBUF, IOEN,
tIODIS
tIOBUF, IEN,
tIODIS
tIOBUF, IN,
AGP_1X_out
CTT25_out
CTT33_out
GTL+_out
Using AGP 1x Standard
t
Using CTT 2.5V
t
Using CTT 3.3V
t
Using GTL+
t
HSTL_I_out
HSTL_III_out
LVDS_out
Using HSTL 2.5, Class I
Using HSTL 2.5VClass III
t
t
UsiLow Voltage Differen-
tial gnaling VDS)
t
BLVDS_out
LVPECL_out
PCI_out
Using us LVoltage Differ- tIOF, tIOEN,
enial Signaling (BLVDS)
tODIS
UF, IOEN,
IS
OBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
tIOBUF, IOEN,
tIODIS
Using ow Voltage PE
t
Using PCI Stan
t
SSTL2_out
SSTL2_Iut
SL3_out
SSTL3_II_out
Using SSTL 2V, Clas
UsinSSTL .5V, Class II
Ung SSTL 33V, Class I
ing STL 3.3V, Class II
t
t
t
t
1. Only available for ispX0B and ispXPGA 1200EB (2.5V/3.3V) devices.
Timing v.2.1
50
Lattice Semiconductor
ispXPGA Family Data Sheet
sysHSI Block Timing
Figure 24 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on
a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance.
Figure 24. Receive Data Eye Diagram Template (Differential)
Bit Time
VTHD
200 mV Differential
+/- 100 mV Single Ended
TH
SIN
jtTH : Optimum Threshold Csing itter
The data pattern eye opening at the receive enink ionsidered the timatmesure of received signal
quality. Almost all detrimental characteristics ot signal and the interconection link design result in eye
closure. This combined with the eye-opening limitthe line receivean e a good indication of a link’s
ability to transfer error-free data.
Signal jitter is of special interest to sysm designers. It is oftthe primy limiting characteristic of long digital
links and of systems with high noise level evironments. An interestg characteristic of the clock and data recovery
(CDR) portion of the ispXPGSERDES receiver is its abily to filter coming signal jitter that is below the clock
recovery PLL bandwidth. For ignals wth high levels of low fruency jitter, the receiver can detect incoming data
error free, with eye openngs snificay less than thaoigure 24.
51
Lattice Semiconductor
ispXPGA Family Data Sheet
sysHSI Block AC Specifications
Operating Frequency Ranges
Test
-51
-4
-3
Symbol
Description
Mode
Condition
Device
LFX125B/C
LFX200B/C
LFX500B/C
LFX1200B/C
LFX125B/C
LFX200B/C
LFX500B/C
LFX1200B/C
LFX125B/C
LFX200B/C
LFX500B/C
LFX200BC
LFX5/C
X200C
00B/C
00B/C
X125B/C
LFX200B/C
LFX500B/
LFX12B/C
LFX125B/
LF0B/
FX50B/C
200B/C
25B/C
FX200B/C
LFX500B/C
LFX1200B/C
Min. Max. Min. Max. Min. Max. Units
50
50
200
188
188
175
67
50
50
20
18
188
175
67
50
50
200
188
188
175
67
SS:CAL
MHz
MHz
50
5
50
50
50
50
33
3
33
33
63
33
63
33
63
Reference Clock
Frequency
fCLK
10B12B
8B10B
SS:CAL
10B12B
8B10
LVDS
33
63
63
33
33
58
40
80
40
80
40
40
75
40
5
0
MHz
75
40
7
40
75
40
70
40
70
4
70
400
400
400
400
0
400
400
00
400
400
400
400
400
400
400
400
800
70
750
70
0
750
750
700
800
750
750
700
800
750
750
700
400
0
400
0
400
400
400
400
400
400
400
400
400
400
400
400
80
7
750
700
800
750
750
700
800
750
750
700
800
750
750
700
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
400
800
750
750
700
800
750
750
700
800
750
750
700
800
750
750
700
with eoSIN
wieoSIN
with eoSIN
Mbps
Mbps
Mbps
Mbps
2
fSIN
Serial Input
CL = 5 pF,
L = 100¾
2
fOUT
Serial ut
CLK with no jit-
r
1. Only lable fispXPGA 125B200B, 500B and 1200B (2.5V/3.3V) devices.
2. fSIN and speeds are suppoed VCC nd VCCP at 1.7V to 1.9V for ispXPGA 1.8V devices.
LOCKITime
Symbol
tSCLOCK
cription
CSPLme
Mode
All
Condition
Min
Max
Unit
After input is stabilized
25
S
1
SS
With SS mode sync pattern
1024
1024
960
tRCP
tCDRLOCK
CDRPLL Lock-in Time
10B12B With 10B12B sync pattern
tRCP
tRCP
tRCP
tRCP
tRCP
tRCP
8B10B
SS
With 8B10B idle pattern
tSYNC
SyncPat Length
1200
1100
50
tCAL
CAL Duration
SS
tSUSYNC
tHDSYNC
SyncPat Set-up Time to CAL
SyncPat Hold Time from CAL
SS
SS
50
1. REFCLK clock period.
52
Lattice Semiconductor
ispXPGA Family Data Sheet
REFCLK and SS_CLKIN Timing
Symbol
tDREFCLK
tJPPREFCLK
Description
Mode
Condition
Min
Max
100
Unit
Frequency Deviation Between TX REFCLK and
CDRX REFCLK on One Link
8B10B/
10B12B
-100
ppm
REFCLK, SS_CLKIN Peak-to-Peak Period Jitter
All
Random Jitter
40-100MHz
0.01
UIPP
ns
REFCLK, SS_CLKIN Pulse Width, (80% to 80% or
20% to 20%).
2
1
tPWREFCLK
All
100-200Mz
REFCLK, SS_CLKIN Rise/Fall Time (20% to 80% or
80% to 20%)
tRFREFCLK
All
2
ns
Serializer Timing2
Symbol
Description
Mode
All
Coitio
Min
Unit
UIPP
ps
tJPPSOUT
tJPP8B10B
tRFSOUT
tCOSOUT
SOUT Peak-to-Peak Output Data Jitter
SOUT Peak-to-Peak Random Jitter
SOUT Peak-to-Peak Deterministic Jitter
fCLK th no ter
0
130
160
8B10B
800 Ms w/K2.7-
8B10B 80bw/K28.5+
ps
SOUT Output Data Rise/Fall Time (20%,
80%)
LDS
700
ps
SS/8BB
12B
2Bt1 +
11 2
2Bt1 +10
1Bt1 +10
ns
ns
REFCLK to SOUT Delay
Skew of SOUT with Respect to
SS_CLKOUT
tSKTX
300
ps
tCKOSOUT
SS_CLKOUT to bit0 of SOU
SS
2Bt1 - tSKTX 2Bt1 + tSKTX
ns
ns
ns
tHSITXDDATAS TXD Data Setup Time
tHSITXDDATAH TXD Data Hold Time
All
All
Ne 3
Note
1.5
1.0
1. Bt: Bit Time Period. High Speed rial Bit Time.
2. The SIN and SOUT jitter specificions listed bove are under the conditiohat the clock tree that drives the REFCLK to sysHSI Block is in
sysCLOCK PLL BYPASS mode.
3. Internal timing for referene only.
Deserializer Timing
Symbol
fDSIN
Descript
Mode
Conditions
Min
-100
0.45
Max
Units
8B10B/
10B12B
N equency Deviatn from RFCLK
100
ppm
eoSIN
SIN Eye Openioleran
Bit Error Rate
All
All
Notes 1, 2
UIPP
Bits
10-12
RXD, SYT Valid Time efore RECCLK Fall-
ing Edge
tOUTLIDPRE
tHSIOUTVALIDPOST
tDSIN
All
All
All
Note 3
Note 3
tRCP/2 - 0.7
tRCP/2 - 0.7
ns
ns
ns
RXT VaTime
LK Falling Edge
BiDelay to RXD Valid at RECCLK
Falline
1.5 tRCP
+
1.5 tRCP +
4.5Bt + 15
4.5Bt + 3
1. Eye opening based on jitter frequency of 100KHz.
2. Lower frequency operation assumes maximum eye closure of 800ps.
3. Internal timing for reference only.
53
Lattice Semiconductor
Lock-in Timing
ispXPGA Family Data Sheet
CDRX_SS LOCK-IN (DE-SKEW) TIMING
SIN
MIN. 1200 SYNCPAT
MIN. 1100 LS CYCLE
DATA (SERIAL)
CAL
tHDSYNC
tSUSYNC
SYDT
RXD(0:7)
SYNCPAT
TRAINING SEQUENCE
DATA (PARALLE
SS MODE DATNSFER
CDR_10B12B LOCK-IN TIMING
SIN
1024 SYNCPAT
DATA (RIAL)
SYDT
RXD(0:9)
NCPAT
DATA (PARALLEL)
CDR_8B10B LOCK-IN
SIN
240 Idle Pattern(960 TRCP)
TA (SEAL)
SYDT
R(0:9)
Idle Patt
DATA (PARALLEL)
SYDT Timing
SYDT TIMING R CDRX_1B
RECCLK
SYDT
RXD(0:9)
Data0 Data1 Data2 Data3 Data4
Parallel Data
SYNC PATTERN
YDT TIMING FOR CDRX_8B10B
RECCLK
SYDT
RXD(0:9)
K28.5 D21.4 D21.5 D21.5 K28.5 D21.4 D21.5 D21.5
D0
D2
D1
IDLE PATTERN
IDLE PATTERN
Data
54
Lattice Semiconductor
Serializer Timing
ispXPGA Family Data Sheet
8B/10B SERIALIZER DELAY TIMING
SYMBOL N
tCOSOUT
SYMBOL N+1
TXD
REFCLK
SOUT
b4
b4 b5 b6 b7 b8 b9 b0 b1 b2 b3
b5 b6 b7 b8 bbb1 b2
SYMBOL N
SYMBOL N-1
SMOL N+1
10B/12B SERIALIZER DELAY TIMING
SYOL
tCOST
SYML +1
TXD
REFCLK
SOUT
b4
b5 bb7 b9
"0" "1"
b4 b5 b6 b7 b8 b9
SYMBOL N-1
0 b1 b2 b3
B
SS Mode SERIALIZER DEAY TIMING
SYM
SYMBOL N+1
TXD
tCOSOUT
REFC
SS_CLKOU
SO
CKOSOUT
tSKTX
b4
b4
b5
b6
b7
b0
b2
SYMBOL N
b5
b1
b3
b6
b7
b0
SYMBOL
N+1
SYMOL N-1
NAL ING FOR sysHSI BLOCK
REC
tHSIOUTVALIDPRE
tHSIOUTVALIDPOST
SYDT, RXD
55
Lattice Semiconductor
Deserializer Timing
ispXPGA Family Data Sheet
8B/10B DESERIALIZER DELAY TIMING
SYMBOL N+1
b4
SYMBOL N
SYMBOL N+2
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3
TDSIN
b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5
SIN
RECCLK
RXD
SYMBOL N
SYMBOL N-1
10B/12B DESERIALIZER DELAY TIMING
SMBOL N
SYMBOL N
b0 b1 b2 b3 b4 b5
SYMBOL +1
SIN
b8 b9
b6 b7
"0" "1" b0 b1 b3 bb5 b6 b7 b8 b9
b4
"1"
"0" b0 b2 b3
TTDSIN
RECCLK
RXD
SYMB
SYMBOL N-2
SYML N
CDRX_SS DESERIALIZER DEAY TIMING
SYBOL N
SYMBOL N+2
YMBOL N+
b7
b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 bb3 b4 b5 b6
TDSIN
b0 b1 b2 b3 b4
SIN
RECCLK
RXD
SYON-2
SYMBOL N
N-1
INTERNAL TIMING FOR sySI BLCK
TPWREFCLK
EFCLK
TXD
SITXDDATAS
tHSITXDDATAH
56
Lattice Semiconductor
ispXPGA Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
tPWH
Parameter
Conditions
Min
1.2
1.2
Max
—
Units
ns
Input clock, high time
80% to 80%
20% to 20%
20% to 80%
tPWL
Input clock, low time
—
ns
tR, tF
Input Clock, rise and fall time
Input clock stability, cycle to cycle (peak)
M Divider input, frequency range
M Divider output, frequency range
N Divider input, frequency range
N Divider output, frequency range
V Divider input, frequency range
V Divider output, frequency range
output clock, duty cycle
3.0
ns
tINSTB
—
+/- 250
320
320
320
60
ps
fMDIVIN
fMDIVOUT
fNDIVIN
fNDIVOUT
fVDIVIN
fVDIVOUT
tOUTDUTY
10
MHz
MHz
MHz
MHz
MHz
MHz
%
10
10
10
100
0
40
Cean refere
10MHz ð fMDIVOUT ð 40MHz or
10MHz ð f VDIVIN ð 160MHz
Can rerence1
40Mð fMDIVOUT ð 32MHz d
160MHz ð fVDIVIN ð 400Mz
Clean reference1
10MHz ð fMDIUT ð 0MHz or
100MHz fVDIVIð 16Hz
Clean rence1
40MHz ð fMVOUT ð 320MHz and
1MHz ð fVDN ð 400MHz
—
—
—
—
+/- 600
+/- 150
+/- 600
+/- 150
ps
ps
ps
ps
tJIT(CC)
Output clock, cycle to cycle jitter (peak)
Output clock, period jittpeak)
2
tJIT(PER)
tCLK_OUT_DELAY Input clock to LK_OUT elay
Interl feedback
Exteedback
—
—
—
3.0
1.5
25
ns
ns
us
ps
ns
ns
ns
ns
tPHASE
Input cloto ernal fedback delta
Time o acqre phase lock after inpble
Delay cement Lead/Lag)
tLOCK
tPLL_DELAY
tRANGE
Typical = +/- 250ps
+/- 120 +/- 550
+/- 0.84 +/- 3.85
Total outpday range (lead/lag
Minimum reset pulse wid
tPLL_RSTW
1.8
—
—
3
tCLK_IN
Gbal lock input delay
1.0
1.5
tPLL_C_DAY Secondary PLL output dey
—
1. This cition aures that the ouput phase jitter will remain within specifications. Jitter spec is based on optimized M, N and V settings
determinbthe ispLEVER sofare
2. Aulated jitter measurever 10,000 waform samples
Interntiming for reference on
57
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXP sysCONFIG Port Timing Specifications
Symbol
Timing Parameter
Min.
Typ.
Max.
Units
sysCONFIG Write Cycle Timing
tSUCS
tHCS
tSUWD
tHWD
Input setup time of CS to CCLK rise
Hold time of CS to CCLK Rise
Input setup time of write data to CCLK rise
Hold time of write data to CCLK rise
Low time to reset device SRAM
INIT pulse width
10
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
5
ns
ns
12
0
ns
ns
tPRGM
tWINIT
tIODISS
tIOENSS
tWH
5
ns
—
—
—
2
12
—
ms
ns
User I/O disable
30
3
—
33
User I/O enable
ns
Write clock High pulse width
Write clock Low pulse width
Write fMAX
ns
tWL
ns
fMAXW
MHz
sysCONFIG Read Cycle Timing
tHREAD
tSUREAD
tRH
Hold time of READ to CCLK rise
0
—
—
—
—
—
—
—
—
—
—
33
25
ns
ns
Input setup time of READ High to K rise
READ clock high pulse wi
READ clock low pulse
Read fMAX
30
12
15
—
ns
tRL
ns
fMAXR
tCORD
MHz
ns
Clock to out for ead data
Boundary Scan Timing
Parameter
Descriptio
TCK [BSAN] CloPulse Width
TK [BSCAClk Pulse Width High
Min.
40
20
20
8
Max.
Units
ns
tBTCP
—
—
—
—
—
—
18
18
18
—
—
45
20
20
tBTCPH
tBTCPL
tBTS
ns
CK SCAN] Clock Pulse W
T[BSCN] Setup Time
ns
ns
tBTH
TCK CAN] Hold Time
10
50
—
—
—
8
ns
tBTRF
TC[BSCAN] RisFall Time
mV/ns
ns
tBTCO
AP Controller Falg Edge Clock to Valid Output
TAP ControFalling dgof Clock to Valid Disable
TAP Conoller g Edge of Clock to Valid Enable
BSCN Test CaptuRegister Setup Time
BSCAN est Capture Register Hold Time
tBTCOD
BTCOEN
tBTS
tBTCRH
tBUTCO
tBTUODIS
tBTUPOEN
ns
ns
ns
25
—
—
—
ns
N TesUpdate Register, Falling Edge of Clock to Valid Output
Test Update Register, Falling Edge of Clock to Valid Disable
Test Update Register, Falling Edge of Clock to Valid Enable
ns
ns
ns
58
Lattice Semiconductor
ispXPGA Family Data Sheet
Switching Test Conditions
Figure 25 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 7.
Figure 25. Output Test Load, LVTTL and LVCMOS Standards
VCCO
R
1
Test
Point
Device
Output
R
C *
L
2
*C includes test fixture and pre capacitan
L
Table 7. Text Fixture Required Components
Test Condition
R1
R2
Timing Referen
LVCMOS 3VCO
LVCMO2.5 VCCO/2
LVCOS 1= VCO/2
0.9V
VCCO
LVCMOS 3.3 = 3.0V
LVCMOS 2.5 = 2.3V
LVCMOS 1.8 = 1.65V
1.65V
LVCMOS I/O, (L -> H, H -> L)
106
106
Default LVCMOS 1.8 I/O (Z -> H)
Default LVCMOS 1.8 I/O (Z -> L)
Default LVCMOS 1.8 I/O (H -> Z
Default LVCMOS 1.8 I/O (L -> Z
×
106
×
35pF
35pF
5pF
106
×
0.9V
1.65V
106
×
VOH - 0.3
1.65V
1
5
VOL + 0.3
1.65V
Note: Output test conditionor all otheeces are determined by respective standards.
59
Lattice Semiconductor
ispXPGA Family Data Sheet
Signal Descriptions1
Signal Name
Signal Type
Description
General Purpose
BKy_IOx1,2
GCLKn/In 7
GSR
Input/Output General purpose I/O number x in I/O Bank y
Input
Input
—
Global clock/input8
Global Set/Reset
NC
No Connect
GND
GND
VCC
VCC
VCC
Input
Output
Ground
VCC
Core logic power supply
IEEE 1149.1 TAP powesupply
I/O Bank y power supp
I/O Bank y referenvolte
VCCJ
2
VCCOy
2
VREFy
DXN, DXP
Temperature Ssing odes, provide a diffential which
corresponds to ttempature of the dece.
Test and Program/Configuration
TMS
TCK
TDI
Input
Input
Input
Outp
Inpu
Input
TesMode Select
Tt Clck
Test ta In
TDO
TOE
CFG0
t DatOut
Output Enable tes aO pins when driven low
lects the SRAmemy configuration type (Peripheral or
E2CMOS Refrsh)
PROGRAMb
Input
Initiates dload from 2CMOS or the peripheral port to SRAM
memory activlow)
DONE
Bi-directional Indicas when cfiguration is complete
INITb
Bi-directional Indicates e device is ready for programming (active low)
READ
Input
Input
In
Scts thEAD operation when in sysCONFIG mode
sysCNFIG Configuration Clock
CCLK
CSb
CONFIG Chip Select (active low)
DATA[0:7]
Bi-direCONFIG Peripheral Port Data I/O
sysCLOCK PL
PLL_FBz
Inp
Inpt
Optional external feedback
PLL_STz
Optional external M divider reset
CLK_OU
Internal Signal Clock output (routable to any I/O)
nternal Signal Lock output (routable to any I/O)
PLL_LOCKz
NDP0
GND
GND
VCC
VCC
Left side PLL Ground
GND1
Right side PLL Ground
Left side PLL power supply
Right side PLL power supply
VCCP0
VCCP1
sysHSI Block4, 5
HSImA_SINP, HSImB_SINP
HSImA_SINN, HSImB_SINN
HSImA_SOUTP, HSImB_SOUTP
HSImA_SOUTN, HSImB_SOUTN
HSImA_SYDT, HSImB_SYDT
HSImA_RECCLK, HSImB_RECCLK
Input
Input
P-side of differential serial data input
N-side of differential serial data input
P-side of differential serial data output
N-side of differential serial data output
Output
Output
Internal Signal Symbol alignment detect
Internal Signal Recovered clock
60
Lattice Semiconductor
ispXPGA Family Data Sheet
Signal Descriptions1 (Cont.)
Signal Name
Signal Type
Input
Internal Signal Indicates when the CSPLL circuit is locked
Description
HSImA_CDRRST, HSImB_CDRRST
CDR Reset
HSIm_CSLOCK, HSIm_CSLOCK
sysHSI Block (Source Synchronous Mode)6
SS_CLKIN0P, SS_CLKIN1P
SS_CLKIN0N, SS_CLKIN1N
SS_CLKOUT0P, SS_CLKOUT1P
SS_CLKOUT0N, SS_CLKOUT1N
CAL0, CAL1
Input
Input
P-side of differential clock input
N-side of differential clock input
Output
Output
Input
P-side of differential clock outp
N-side of differential clock output
Initiates source synchroous calibratisequence
1. x is a variable for the I/O number.
2. y is a variable for the I/O Bank.
3. z is a variable for the PLL number.
4. m is a variable for the sysHSI block number.
5. A and B refer to the sysHSI block channels.
6. 0 and 1 refer to Source Synchronous group 0 and 1
7. n is a variable for the GCLK and Input number
8. See Logic Signal Connections Table for differential pairing.
61
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Power Supply and NC Connections1
Signal
256-Ball fpBGA3
516-Ball fpBGA3
VCC
C3, C14, D4, D13, E5, E12, F6, F11, A9, A22, D4, D27, J1, J30, L11, L12, L15, L16, L19, L20, M11, M20, R11,
L6, L11, M5, M12, N4, N13, P3, P14 R20, T11, T20, W11, W20, Y11, Y12, Y15, Y16, Y19, Y20, AB1, AB30, AG4,
AG27, AK9, AK22
VCCO0 F5, G5
VCCO1 K5, L5
F4, J4, M4, N11, P4, P11
U4, U11, V11, W4, AB4, AE4
Y13, Y14, AG6, AG9, AG12, AG14
Y17, Y18, AG17, AG19, AG22, AG25
U20, U27, V20, W27, AB27, AE27
F27, J27, M27, N20, P20, P27
D17, D19, D22, D25, L17, L
D6, D9, D12, D14, L13, L4
R4, T30
VCCO2 M6, M7
VCCO3 M10, M11
VCCO4 K12, L12
VCCO5 G12, F12
VCCO6 E10, E11
VCCO7 E6, E7
VCCP
VCCJ
GND
H3, J15
A2
C4
A1, A16, B2, B15, F7, F8, F9, F10,
A1, A30, B2, 29, C3, C28, M12, M13, M14, M5, M1M1M18, M19,
G6, G7, G8, G9, G10, G11, H6, H7, N12, N13, 4, N, N16, N17, N18, N19, P12, 13, P1P15, P16, P17,
H8, H9, H10, H11, J6, J7, J8, J9, J10, P18, P19, R113, R1, R15, R16, R1R18, R1T12, T13, T14, T15,
J11, K6, K7, K8, K9, K10, K11, L7,
L8, L9, L10, R2, R15, T1, T16
T16, T1T18, 9, U2, U13, U14, U15, 6, U17U18, U19, V12, V13,
V146, V1V18, V19, W12, 13, W, 15, W16, W17, W18,
W28, AJ2, AJ29, AK1, AK3
GNDP
NC2
H15, J4
—
R29,
LFX125: 10, A13, A16, A1724, 5, A26, A4, A5, A6, A7, AA1, AA2,
AA28, AA29, AA3, AB, AC1, C28, AD1, AD27, AD4, AE28, AE29, AE3,
AE30, AF27, AF28, F, AF3, A, AG1, AG10, AG11, AG15, AG2, AG20,
AG23, AG24, AG29, AG3G8, AH1, AH15, AH19, AH2, AH20, AH23, AH24,
AH30, AH7, AHAH9, AJ1J12, AJ14, AJ15, AJ19, AJ20, AJ21, AJ23,
AJ24, AJ25, AJ27, J30, AJ6, AJ7, AJ8, AK11, AK14, AK15, AK20, AK21,
AK23, AK25, 27, AK5, AK6, AK7, B10, B13, B16, B17, B18, B23,
B24, B25, B5B6, B7, 11, C13, C14, C16, C17, C22, C23, C24, C25, C6,
C7, C11, D6, D23, D24, D28, D29, D3, D7, D8, E30, E4, F1, F29, F30,
GG28G29, G30, H1, H2, H27, H28, H29, H30, J2, J28, J29, J3,
K28, K3, K4, L1, L2, L27, L3, L4, M1, M2, M29, M3, M30, V27,
V2W1, W30, Y1, Y27, Y28, Y3, Y30
LFX200: A26, A25, A24, A17, A10, A7, A6, A5, A4, B25, B24, B23, B17, B10,
B7B6, B5, C25, C24, C23, C22, C16, C11, C8, C7, C6, D24, D23, D16,
D1, D8, D7, E30, F30, F29, F1, G30, G29, G28, G27, G2, G1, H30, H29,
28, H27, H2, H1, J29, J28, J3, J2, K28, K27, K4, K3, K2, K1, L27, L4, L3,
L2, L1, M3, V28, V27, V4, V3, W30, W1, Y30, Y28, Y27, Y3, Y1, AA29,
AA28, AA3, AA2, AA1, AD27, AD4, AE28, AE3, AF29, AF28, AF27, AF3,
AG29, AG24, AG23, AG20, AG11, AG10, AG8, AG2, AG1, AH30, AH24,
AH23, AH20, AH9, AH8, AH7, AH2, AH1, AJ30, AJ27, AJ25, AJ24, AJ23,
AJ21, AJ15, AJ12, AJ8, AJ7, AJ6, AJ1, AK27, AK25, AK24, AK23, AK21,
AK15, AK11, AK7, AK6, AK5
1. All grounds must be connected at the board level.
2. NC pins should not be cted to any active signals, VCC or GND.
3. Balls for GND, VCC and VCCOx are connected within the substrate to their respective common signals. Pin orientation A1 starts from the
upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.
62
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Power Supply and NC Connections1 (Continued)
Signal
680-Ball fpBGA3
900-Ball fpBGA3
V
AE35, AE5, AL5, AR15, AR25, AR31, AR35, AR5, L11, L20, M12, M13, M14, M17, M18, M19, N12, N19, P12, P19,
AT36, AT4, AU3, AU37, C3, C37, D36, D4, E15, E25, U12, U19, V12, V19, W12, W13, W14, W17, W18, W19, Y11, Y20
E35, E5, E9, J35, R35, R5
CC
V
V
V
V
V
V
V
V
V
V
E11, E12, E13, E17, E18, E7
E22, E23, E27, E29, E31, E33
G35, L35, M35, N35, U35, V35
AB35, AC35, AG35, AJ35, AL35, AN35
AR22, AR23, AR27, AR28, AR29, AR33
AR11, AR13, AR17, AR18, AR7, AR9
AB5, AC5, AG5, AH5, AJ5, AN5
G5, J5, L5, N5, U5, V5
K3, L10, M11, N11, N5, P11, R11, R12
AA3, T11, T12, U11, V11, V5, W11, Y10
AA11, AF13, AH10, W15, Y12, Y3, Y14, Y1
AA20, AF18, AH21, W16, Y16, 17, 18, Y19
AA28, T19, T20, U20, V226, W0, Y2
K28, L21, M20, N20, N6, P20, R19, R20
C21, E18, K20, L16, L, L18, L, M16
C10, E13, K11, L1L13, 4, 15, M15
R5, T26
CCO0
CCO1
CCO2
CCO3
CCO4
CCO5
CCO6
CCO7
CCP
E20, AW22
D3
B3
CCJ
GND
A1, A2, A20, A38, A39, AE3, AE37, AK3, AK37,
AR36, AR4, AT20, AT35, AT5, AU10, AU14, AU20,
AU26, AU30, AV1, AV2, AV20, AV38, AV39, AW1,
A1, 2, A29, 0B28, AB3, AG27, AGH22, A28, AH3, AH9,
A1, AJ2, AJ29, AJ30, AK1, AK2, A9, AK, BB2, B29, B30,
22, 8, C3, C9, D27, D4, J28, J3, N, N14, 15, N16, N17, N18,
AW2, AW20, AW38, AW39, B1, B2, B20, B38, B39, P14, P5, P16, P17, P1R13, R1415, R16, R17, R18, T13,
C10, C14, C20, C26, C30, D20, D35, D5, E36, E, T1T15, 16, T17, T18, U13, 4, U15, 16, U17, U18, V13, V14,
K3, K37, P37, R3, Y1, Y2, Y3, Y36, Y37, Y3V15, , V17, V18
Y4
GND
AR20, A21
8, T3
P
63
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Power Supply and NC Connections1 (Continued)
Signal
NC2
680-Ball fpBGA3
900-Ball fpBGA3
A3, B29, AW3, AV3, AW11, AV11, AV29, AW29,
AW37, B3, AV37, C39, C38, AU39, AU38, AJ39,
LFX500: A8, A9, A10, A11, A19, A20, A21, A22, B8, B9, B10, B11,
B19, B20, B21, B22, C1, C2, C11, C12, C19, C20, C23, D3, D10,
AJ38, N38, N39, C2, C1, AU1, AU2, AJ2, AJ1, N2, D11, D12, D19, D20, D21, D22, D23, E3, E5, E6, E10, E11, E12,
N1, B11, A11, A37, B37, A29
E21, E22, E25, E26, E28, E29, E30, F1, 2, F6, F9, F10, F11, F12,
F21, F22, F25, F26, F29, F30, G1, G2, , GG8, G9, G10,
G11, G12, G14, G15, G16, G17, G19, G20G21, G2, G23, G24,
G25, G26, G27, G28, G29, G30, 1, H2, H3, H4, 5, H6, H7, H8,
H9, H10, H11, H12, H13, H14, 15, H1, H17, H18, H19, H20, H21,
H22, H23, H24, H27, H28, H293J1, J2, J4, J5, J6, J7, J8, J9,
J10, J11, J12, J13, J14, J15, J16, 7, J18J19, J20, J21, J22, J23,
J24, J25, J26, J27, K6, 7, K8, K9, K0K12, K13, K14, K15, K16,
K17, K18, K19, K21, K2, K23, K24, K25, L7, L8, L9, L22, L23, L24,
M7, M8, M9, M10, M2M22, M2M24, N8, N9, N, N22,
N23, P7, P8, P9, 10, P, P22P23, P24, R8, , R22,
R23, R24, R2, T6, 7, T8, 9, T10, T21, T22, T2U7,
U8, U9, U10, U1, U2U23, U24, V8, V9, 10, V213, W7,
W8, W9, W10, 21, W2, W23, W24, W5, W26, Y3, Y5, Y6,
Y7, Y8, Y22, 23, Y24, Y25, Y26, 7, Y2, AA4, AA5, AA6,
AAAA8, AA10, AA12, AA13, AA1A15, A16, AA17,
A18, AA19, AA21, AA22, AA23, A4, AA, A26, AA27, AB1,
B2, B4, AB5, AB6, AB7, AB8, AB9, B10, A11, AB12, AB13,
A, AB15AB16, AB17, AB8, AB19, 20, AB21, AB22, AB23,
ABAB5, AB26, AB27AC1, C2, ACAC4, AC5, AC6, AC7,
C8, 9, AC10, AC11, A2, AC, 14, AC15, AC16, AC17’
18’ AC19, AC20, AC21, A2, AC23, AC24, AC27, AC28, AC29,
30, AD1, AD2, AA, AD10, AD11, AD12, AD14,
D15, AD16, A7, AD9, AD20, AD21, AD22, AD23, AD24, AD29,
AD30, AE6, AE9, E10, 11, AE12, AE19, AE20, AE21, AE22,
AE25, AE, AE30, F5, AF6, AF10, AF11, AF12, AF19, AF20,
AF21, A2AF25, AF, AG10, AG11, AG12, AG19, AG20, AG21,
AG22, AH11, H12, AH19, AH20, AJ8, AJ9, AJ10, AJ11, AJ20,
AJ2AJ22, AKAK9, AK10, AK11, AK20, AK21, AK22
FX120AA22, AA23, AA24, AA25, AB23, AC24, T21, T22, T23,
4, T1, U22, U23, U24, V21, V22, V23, W21, W22, W23,
W, Y22, Y23, Y24, AA16, AA17, AA18, AA19, AA21, AB16, AB17,
AB1AB19, AB20, AB21, AB22, AC16, AC17, AC18, AC19, AC20,
C21, AC22, AC23, AD16, AD17, AD19, AD20, AD22, AD23, AD24,
E22, AE25, AF25, AF26, AA10, AA12, AA13, AA14, AA15, AB10,
AB11, AB12, AB13, AB14, AB15, AB9, AC10, AC11, AC12, AC13,
AC14, AC15, AC8, AC9, AD11, AD12, AD14, AD15, AD7, AD8,
AD9, AE6, AE9, AF5, AF6, H24, J23, K22, K23, K24, K25, L22, L23,
L24, M21, M22, M23, M24, N21, N22, N23, P21, P22, P23, P24,
R21, R22, R23, R24, R25, AA6, AA7, AA8, AA9, AB8, AC7, T10, T6,
T7, T8, T9, U10, U7, U8, U9, V10, V8, V9, W10, W7, W8, W9, Y7,
Y8, Y9, H5, H6, H7, J8, K6, K7, K8, K9, L7, L8, L9, M10, M7, M8,
M9, N10, N8, N9, P10, P7, P8, P9, R10, R8, R9, E25, E26, F22,
F25, G16, G17, G19, G20, G22, G23, G24, H16, H17, H18, H19,
H20, H21, H22, H23, J16, J17, J18, J19, J20, J21, J22, K16, K17,
K18, K19, K21, E5, E6, F6, F9, G11, G12, G14, G15, G7, G8, G9,
H10, H11, H12, H13, H14, H15, H8, H9, J10, J11, J12, J13, J14,
J15, J9, K10, K12, K13, K14, K15
1. All grounds must be eley connected at the board level.
2. NC pins should not be conected to any active signals, VCC or GND.
3. Balls for GND, VCC and VCCOx are connected within the substrate to their respective common signals. Pin orientation A1 starts from the
upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.
64
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 256-Ball fpBGA
LFX200
LFX125
256-fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK0_IO2
GND (Bank 0)
BK0_IO3
BK0_IO6
-
Function
sysHSI Reserved2 Signal Name
Function
sysHSI Reserved2
C2
-
HSI0A_SOUTP
1P/HSI0
BK0_IO0
-
HSI0A_SOUP
0P
-
-
-
-
D2
B1
-
HSI0A_SOUTN
1N/HSI0
BK0_IO1
BK0_IO4
GND (Bank 0)
BK0_IO5
BK0_IO
BK0O7
B0_IO
-
HSI0_SOUTN
0N
HSI0A_SINP
3P/HSI0
I0A_INP
2P/HSI0
-
-
-
-
C1
D3
E3
D1
-
BK0_IO7
BK0_IO8
BK0_IO9
BK0_IO10
GND (Bank 0)
BK0_IO11
BK0_IO12
BK0_IO13
BK0_IO14
-
HSI0A_SINN
3N/HSI0
HSI0ANN
2N/HSI0
-
4P/HSI0
-
SI0
VREF0
4N/HSI0
VREF0
0
HSI0B_SOUTP
5P/HSI0
HSI0B_SOUT
-
-
-
E1
E2
F2
F1
-
HSI0B_SOUTN
5N/HSI0
K0O9
BK0_IO10
BK0_IO11
BK0_IO12
GND (Bank 0)
BK0_IO
BKIO14
-
HSI0B_SOTN
4N/HSI0
-
6P/HSI
5P/HSI0
-
6N/HS
-
5N/HSI0
HSI0B_SINP
7HSI0
H0B_SI
6P/HSI0
-
-
G1
F3
-
BK0_IO15
BK0_IO18
GND (Bank 0)
BK0_IO19
BK0_IO20
BK0_IO21
BK0_IO2
-
HSI0B_SINN
0B_SINN
6N/HSI0
PLL_FBK0
PLL_FBK0
7P/HSI0
-
-
-
-
G2
E4
F4
H1
-
PLL_RST1
9N
K0_IO15
BKIO16
BK0_IO17
BK0_IO18
GND (Bank 0)
BK0_IO19
BK0_IO20
BK0_IO21
-
PLL_RST1
7N/HSI0
-
10P
-
8P/HSI0
PLL_FBK1
10N
PLL_FBK1
8N/HSI0
LL_RS0
11P
PLL_RST0
9P
-
-
-
-
J1
H2
G3
-
BK0_2
BK0_IO2
BK0_IO25
G(Bak 0)
GCLK0
-
-
9N
CLK_OUT0
CLK_OUT0
10P
CLK_OUT
CLK_OUT1
10N
-
-
-
-
4
H
H3
J
J
J3
-
-
VDS Pair0P
GCLK0
-
LVDS Pair0P
GCLK1
-
LVDS Pair0N
GCLK1
-
LVDS Pair0N
VCCP0
-
-
VCCP0
-
-
GNDP0
-
-
GNDP0
-
-
GC
-
-
LVDS Pair1P
GCLK2
-
-
LVDS Pair1P
LVDS Pair1N
GCLK3
LVDS Pair1N
GND
BK1_I
BK1_IO1
BK1_IO2
-
-
-
-
-
-
H5
J5
K1
-
CLK_OUT2
CLK_OUT3
SS_CLKOUT0P
-
13P
13N
14P
-
BK1_IO0
BK1_IO1
BK1_IO2
GND (Bank 1)
BK1_IO3
BK1_IO4
BK1_IO5
BK1_IO6
CLK_OUT2
CLK_OUT3
SS_CLKOUT0P
-
11P
11N
12P
-
L1
K4
L4
K3
BK1_IO3
BK1_IO4
BK1_IO5
BK1_IO6
SS_CLKOUT0N
PLL_FBK2
PLL_FBK3
SS_CLKIN0P
14N
15P
15N
16P
SS_CLKOUT0N
PLL_FBK2
PLL_FBK3
SS_CLKIN0P
12N
13P
13N
14P
65
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)
LFX200
LFX125
256-fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
GND (Bank 1)
BK1_IO7
BK1_IO8
-
Function
sysHSI Reserved2 Signal Name
Function
sysHSI Reserved2
-
-
-
-
-
-
L3
K2
-
SS_CLKIN0N
16N
BK1_IO7
BK1_IO8
GND (Bank 1)
BK1_IO9
BK1_IO10
BK1_IO1
BK1O12
B1_IO3
-
K1O141
BK1_O16
GND (Bank 1)
BK1_IO17
BK1_IO181
BK1_I
SS_CLKIN
14N
15P
-
-
17P
-
-
-
-
L2
M1
N1
M3
M4
-
BK1_IO9
BK1_IO10
BK1_IO11
BK1_IO12
BK1_IO13
GND (Bank 1)
BK1_IO161
BK1_IO18
-
-
17N
-
15N
16P
6N
HSI1A_SOUTP
18P/HSI1
HSI1A_SOUTN
18N/HSI1
-
PLL_RST2
19P/HSI1
PL_RST2
PLL_RST3
19N/HSI1
PLL_RST3
-
-
-
M2
P1
-
VREF1
-
VREF
-
HSI1B_SOUTP
22P/HSI
19P
-
-
-
-
R1
N3
N2
-
BK1_IO19
BK1_IO201
BK1_IO22
GND (Bank 1)
BK1_IO23
TCK
HSI1B_SOUTN
22N/HSI1
-
19N
-
-
HSI1B_SINP
-
21P
-
-
-
P2
P4
T2
T3
R3
R4
N5
-
HSI1B_SN
24N/HSI1
-
BK1_I1
TCK
-
21N
-
-
-
TMS
-
-
MS
-
-
TOE
-
-
TOE
-
-
BK2_IO0
BK2_1
BK2O2
GND (Ban2)
BK2_IO3
-
-
26
26N
BK2_IO0
BK2_IO1
BK2_IO2
-
-
22P
22N
23P
-
-
-
-
-
-
P5
-
-
-
BK2_IO3
GND (Bank 2)
BK2_IO6
BK2_IO7
BK2_IO8
BK2_IO9
BK2_IO10
-
-
23N
-
-
-
4
T
N6
P
R
-
BKIO6
K2_IO7
BK2_IO8
BK2_IO9
BK2_IO10
GN
BK
BK2_I
-
-
29P
29N
30P
30N
31P
-
-
25P
25N
26P
26N
27P
-
-
-
-
-
VREF
VREF2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R6
N7
-
31N
32P
-
BK2_IO11
BK2_IO12
GND (Bank 2)
BK2_IO13
BK2_IO14
BK2_IO15
BK2_IO16
BK2_IO17
BK2_IO18
27N
28P
-
P7
T6
T7
M8
M9
R7
BK2_IO13
BK2_IO14
BK2_IO15
BK2_IO16
BK2_IO17
BK2_IO18
32N
33P
33N
34P
34N
35P
28N
29P
29N
30P
30N
31P
66
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)
LFX200
LFX125
256-fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
GND (Bank 2)
BK2_IO19
BK2_IO20
BK2_IO21
GND (Bank 2)
GND (Bank 3)
BK3_IO0
BK3_IO1
BK3_IO2
-
Function
sysHSI Reserved2 Signal Name
Function
sysHSI Reserved2
-
-
-
GND (Bank 2)
BK2_IO19
BK2_IO20
BK2_IO21
-
-
-
R8
N8
P8
-
-
35N
-
31N
32P
32N
-
-
36P
-
-
36N
-
-
-
-
-
-
-
-
-
T8
-
39P
BK3_IO
BKIO1
3_I
GND Bank 3
BK3IO3
BK3IO4
BK3_IO5
BK3_IO6
-
-
3P
T9
-
39N
-
R9
-
-
40P
-
-
-
-
R10
P9
N9
T10
-
BK3_IO3
BK3_IO4
BK3_IO5
BK3_IO6
GND (Bank 3)
BK3_IO7
BK3_IO8
-
-
40N
-
34N
35P
35N
36P
-
-
41P
-
41N
-
-
42P
-
-
T11
P10
-
-
BK3_I
BK_IO8
GND (Bk 3)
BK3_IO9
B_IO10
-
-
36N
37P
-
-
-
-
-
-
N10
R11
-
BK3_IO9
BK3_IO14
GND (Bank 3)
BK3_IO15
BK3_I16
BK3_17
BK3_IO
BK3_IO19
K3_IO0
-
43N
-
37N
38P
-
-
46P
-
-
-
-
R12
P11
N11
T12
T13
R13
-
46
BK3_IO11
BK3_IO12
BK3_IO13
BK3_IO14
BK3_IO15
BK3_IO16
GND (Bank 3)
BK3_IO17
BK3_IO18
-
-
38N
39P
39N
40P
40N
41P
-
VF3
47P
VREF3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
49P
-
-
R
P12
-
K3_IO21
BK3_IO22
GND (Bank 3
BK3_IO23
-
49N
41N
42P
-
-
50P
-
-
N1
T14
T15
P13
P15
N14
R16
-
-
50N
BK3_IO19
GSR
42N
-
-
-
-
-
DXP
-
DX
-
-
DXN
-
BK4_IO0
BK4_IO1
BK4_IO2
GND (Bank 4)
BK4_IO3
BK4_IO4
-
-
52P/HSI2
52N/HSI2
53P/HSI2
-
BK4_IO0
BK4_IO1
BK4_IO2
-
44P
44N
45P
-
-
HSI2A_SINP
-
P16
N15
-
HSI2A_SINN
53N/HSI2
54P/HSI2
-
BK4_IO3
BK4_IO4
GND (Bank 4)
45N
46P
-
-
-
67
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)
LFX200
LFX125
256-fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK4_IO5
BK4_IO8
BK4_IO9
GND (Bank 4)
BK4_IO12
BK4_IO13
BK4_IO14
BK4_IO15
-
Function
sysHSI Reserved2 Signal Name
Function
sysHSI Reserved2
M15
M14
M13
-
-
54N/HSI2
BK4_IO5
BK4_IO6
BK4_IO7
-
-
46N
-
56P/HSI2
-
47P
VREF4
56N/HSI2
VEF4
47N
-
-
-
-
L13
L14
N16
M16
-
PLL_RST4
58P/HSI2
BK4_IO8
BK4_IO9
BK4_IO1
BK4O11
GN(Ba4)
BK_IO14
PRST4
48P
PLL_RST5
58N/HSI2
PLL_S5
48N
HSI2B_SOUTP
59P/HSI2
-
9P
HSI2B_SOUTN
59N/HSI2
-
-
-
-
L15
-
BK4_IO18
GND (Bank 4)
BK4_IO19
BK4_IO20
BK4_IO21
BK4_IO22
-
SS_CLKIN1P
61P
SS_CLKINP
-
-
-
-
K15
K14
K13
L16
-
SS_CLKIN1N
61N
BK4_O15
BK4_IO16
BK4_IO17
BK4_IO18
GND (Ba
BKIO19
BK4_I0
K4_IO21
-
SS_CKIN1N
51N
PLL_FBK4
62P
PLL_FB4
52P
PLL_FBK5
62N
L_FBK
52N
SS_CLKOUT1P
S_CLT1P
53P
-
-
-
K16
J13
J12
-
BK4_IO23
BK4_IO24
BK4_IO25
GND (Bank 4)
GCLK4
SS_CLKOUT1N
SS_CLKOUT1N
53N
CLK_O4
64P
CLK_OUT4
54P
CLK_OUT
64N
CLK_OUT5
54N
-
-
-
-
J14
H14
J15
H15
J16
H16
-
-
LVDS Pair2P
GCLK4
-
LVDS Pair2P
GCLK5
-
LVDS P
GCLK5
-
LVDS Pair2N
VCC1
-
VCCP1
-
-
GN1
-
GNDP1
-
-
GCLK6
-
3P
GCLK6
-
LVDS Pair3P
GCLK7
-
Lir3N
GCLK7
-
LVDS Pair3N
GD (Ba5)
BKIO0
K5_IO1
BK5_IO2
-
-
-
-
-
-
55P
H2
H
G14
-
CLK_OU6
65P
BK5_IO0
BK5_IO1
BK5_IO2
GND (Bank 5)
BK5_IO3
BK5_IO6
-
CLK_OUT6
LK_OUT7
65N
CLK_OUT7
55N
-
66P
-
56P
-
-
-
-
G
G13
-
BK5_I3
B
GND
BK5_I
BK5_IO10
-
PLL_RST7
66N
PLL_RST7
56N
PL_RST6
68P
PLL_RST6
58P/HSI1
-
-
-
-
F13
G16
-
PLL_FBK7
68N
BK5_IO7
BK5_IO8
GND (Bank 5)
BK5_IO9
BK5_IO10
BK5_IO11
BK5_IO12
-
PLL_FBK7
58N/HSI1
59P/HSI1
-
HSI3A_SINP
70P
HSI1A_SINP
-
-
-
F16
F14
F15
E16
-
BK5_IO11
BK5_IO12
BK5_IO13
BK5_IO14
GND (Bank 5)
HSI3A_SINN
70N/HSI3
71P/HSI3
71N/HSI3
72P/HSI3
-
HSI1A-SINN
59N/HSI1
60P/HSI1
60N/HSI1
61P/HSI1
-
-
-
-
-
HSI3A_SOUTP
-
HSI1A_SOUTP
-
68
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)
LFX200
LFX125
256-fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK5_IO15
BK5_IO16
BK5_IO17
BK5_IO18
-
Function
sysHSI Reserved2 Signal Name
Function
sysHSI Reserved2
D16
E13
E14
E15
-
HSI3A_SOUTN
72N/HSI3
BK5_IO13
BK5_IO14
BK5_IO15
BK5_IO16
GND (Bank 5)
BK5_IO17
BK5_IO2
HSI1A_SOUN
61N/HSI1
VREF5
73P/HSI3
VREF
62P/HSI1
-
73N/HSI3
-
62N/HSI1
HSI3B_SINP
74P/HSI3
HI1B_NP
63P/HSI1
-
-
-
-
D15
C16
-
BK5_IO19
BK5_IO22
GND (Bank 5)
BK5_IO23
BK5_IO24
BK5_IO25
CFG0
HSI3B_SINN
74N/HSI3
HSI1BSN
63N/HSI1
HSI3B_SOUTP
76P/HSI3
HSIB_SOUTP
6/HSI1
-
-
-
B16
D14
C15
C13
A15
A14
D12
C12
B14
-
HSI3B_SOUTN
76N/HSI3
B5_IO1
BK_IO18
K5O19
CFG0
HSI1B_SOUTN
1
-
77P/HSI3
77N/HSI3
-
-
6SI1
64N/HSI1
-
-
-
-
DONE
-
-
DONE
-
-
PROGRAMb
BK6_IO0
BK6_IO1
BK6_IO2
GND (Bank 6)
BK6_IO3
BK6_IO4
-
-
-
PROGRAMb
BK6_IO0
BK6_I
BK_IO2
-
-
-
INITb
-
I
66P
66N
67P
-
CCLK
CCLK
-
-
-
-
B13
A13
-
-
79N
80P
-
BK6_IO3
B_IO4
GND (Bank 6)
BK6_IO5
BK6_IO6
BK6_IO7
BK6_IO8
BK6_IO9
BK6_IO10
-
-
67N
68P
-
Sb
CSb
-
-
A12
D11
C11
B12
B11
D10
BK6_IO5
BK6_6
BK6O7
BK6_IO
BK6_IO9
K6_IO0
GND ank 6)
K6_IO11
-
Read
80
81P
83P
-
READ
68N
69P
69N
70P
70N
71P
-
A7
DATA7
DATA6
DATA6
-
-
VREF6
VREF6
DATA
DATA5
-
-
C
-
DATA4
83N
-
BK6_IO11
GND (Bank 6)
BK6_IO14
BK6_IO15
BK6_IO16
BK6_IO17
BK6_IO18
GND (Bank 6)
BK6_IO19
BK6_IO20
BK6_IO21
-
DATA4
71N
-
-
-
A
A1
D9
BK6_IO14
BK6_IO15
B
BK
BK6_I
GND (Bank 6)
BK6_IO19
BK6_IO20
BK6_IO21
GND (Bank 6)
GND (Bank 7)
BK7_IO0
DATA
85P
85N
86P
86N
87P
-
DATA3
73P
73N
74P
74N
75P
-
DATA2
DATA2
-
-
C9
-
-
B10
-
DATA1
DATA1
-
-
B9
DATA0
87N
88P
88N
-
DATA0
75N
76P
76N
-
E9
-
-
-
-
-
-
-
-
-
-
E8
-
-
-
-
-
D8
91P
BK7_IO0
77P
69
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 256-Ball fpBGA (Cont.)
LFX200
LFX125
256-fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK7_IO1
BK7_IO2
BK7_IO3
BK7_IO6
GND (Bank 7)
BK7_IO7
BK7_IO10
BK7_IO11
BK7_IO12
-
Function
sysHSI Reserved2 Signal Name
Function
sysHSI Reserved2
C8
B8
B7
A9
-
-
91N
92P
92N
94P
-
BK7_IO1
BK7_IO2
BK7_IO3
BK7_IO4
-
-
77N
78P
78N
79P
-
-
-
-
-
-
-
-
-
A8
C7
D7
D6
-
-
94N
96P
96N
97P
-
BK7_IO5
BK7_IO
BKIO7
7_I
GND Bank 7
BK7IO9
BK7_O10
-
79N
0P
-
-
-
-
-
-
-
-
C6
B6
-
BK7_IO13
BK7_IO14
GND (Bank 7)
BK7_IO15
BK7_IO16
BK7_IO17
BK7_IO18
BK7_IO19
BK7_IO20
-
-
97N
98P
-
-
81N
82P
-
-
-
-
B5
A7
A6
D5
C5
A5
-
-
98N
100N
101P
-
BK7_IO11
BK7_IO12
BK7_I
BKIO14
BK7_I5
K7_IO16
GNBank 7)
BK7_IO17
BK7_IO18
-
-
82N
83P
83N
84P
84N
85P
-
VREF7
V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A4
B4
-
BK7_IO21
BK7_IO22
GND (Bk 7)
BK7_23
TDO
101N
102
-
85N
86P
-
B3
A3
A2
C4
BK7_IO19
TDO
86N
-
VCCJ
VCCJ
-
TDI
-
TDI
-
1. Not vailablfor diffntial pairs.
2. If a sHBlock is used, the indicasysHSserd pins are unavailable for general purpose I/O use.
70
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 516-Ball fpBGA
LFX500
LFX200
LFX125
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
LVDS Pair/
516-Ball
Second
Second
Second
sysHSI
BGA Ball
Signal Name
BK0_IO0
Function
Reserved1
Signal Name
BK0_IO0
BK0_IO1
BK0_IO2
GND (Bank 0)
BK0_IO3
BK0_IO4
BK0_IO5
BK0_IO6
-
Function
Reserved1
Signal Name
NC
Function
Reserved1
E4
D3
E3
-
-
0P
0N
-
0P/HSI0
-
-
BK0_IO1
-
-
0N/HSI0
NC
-
BK0_IO2
HSI0A_SOUTP
1P/HSI0
-
HSI0A_SOUTP
1P/HSI0
BK0O0
-
HSI0A_SOP
0P
GND (Bank 0)
BK0_IO3
-
-
-
-
F3
C2
B1
G4
-
HSI0A_SOUTN
1N/HSI0
2P/HSI0
2N/HSI0
3P/HSI0
-
HSI0A_SOUTN
1N/HSI0
K0_I
BO2
BK0_I
B0_IO4
GNBank 0)
K0_IO5
BK0_IO6
BK0_IO7
BK0_IO8
HSI0A_SOUTN
0N
BK0_IO4
-
-
2P/HSI0
-
1P/HSI0
BK0_IO5
-
-
2N/H
-
1N/HSI0
BK0_IO6
HSI0A_SINP
HSI0A_SINP
3P/H0
HSI0A_SINP
2P/HSI0
-
-
-
-
-
-
G3
C1
D2
H4
-
BK0_IO7
HSI0A_SINN
3N/HSI0
4P/HSI0
4N/HSI0
5P/HSI0
-
BK0_IO7
BK0_IO8
BK0_IO9
BK0_IO10
GND (Bank 0)
BK0_IO11
BK0_IO12
B
HSI0A_SINN
HSI0
HSI0A
HSI0
BK0_IO8
-
-
4P/0
-
HSI0
BK0_IO9
VREF0
VREF0
4N/HSI
VRF0
3N/HSI0
BK0_IO10
GND (Bank 0)
BK0_IO11
BK0_IO12
BK0_IO13
BK0_IO14
-
HSI0B_SOUTP
HSI0B_SP
-
P/HSI0
HSB_SOUTP
4P/HSI0
-
-
-
-
H3
D1
E1
E2
-
HSI0B_SOUTN
5N/HSI0
6P/HSI0
6N/HSI0
7P/HSI0
-
HSI0SOUTN
5N/HSI0
BK0_IO
K0_IO10
BIO11
BK0_
(Bank 0)
B_IO13
NC
HSIOUTN
4N/HSI0
-
6P/HSI0
-
5P/HSI0
-
-
6N/HSI0
-
5N/HSI0
HSI0B_SINP
HSI0B_SINP
7P/HSI0
HSI0B_SINP
6P/HSI0
-
-
-
-
F2
G2
F1
J3
-
BK0_IO15
BK0_IO16
BK0_IO17
BK0_IO18
GND (Bank 0)
BK0_IO19
BK0_IO20
BK0_IO21
BK0_IO22
BK0_IO23
BK0_IO24
K0_IO25
B_IO26
GND (Bk 0
BK0_IO2
BK0O28
0_IO29
BK0_IO30
BK0_IO31
BK0_IO3
BK0_
BK0_IO
GND (Bank 0
BK0_IO35
BK0_IO36
BK0_IO37
BK0_IO38
-
HSI0B_SINN
7N/HSI0
8PSI0
SI0
9P
BK
NC
HSI0B_SINN
7N/H0
HSI0B_SINN
6N/HSI0
-
-
-
-
-
-
NC
-
NC
-
-
HSI1A_SOUTP
NC
-
NC
-
-
-
-
-
-
-
-
-
-
K3
K4
L4
H2
J2
G1
H1
L3
-
HSI1A_UTN
9N
NC
-
-
NC
-
-
-
0P
NC
-
NC
-
-
-
10N
NC
-
-
NC
-
-
HSI_SINP
11P
-
-
NC
-
-
I1A_SIN
11N
-
-
NC
-
-
-
12P
-
-
NC
-
-
-
12N
-
-
NC
-
-
HI1B_SOUTP
3P
NC
-
-
-
NC
-
-
-
-
-
-
-
-
-
K2
L2
L1
M
M1
N3
-
HSI1B_SOUTN
NC
-
-
NC
-
-
-
14P
NC
-
-
NC
-
-
-
N
NC
-
-
NC
-
-
HB_SINP
P
NC
-
-
NC
-
-
HSI1INN
15N
NC
-
-
NC
-
-
-
16P
BK0_IO16
BK0_IO17
BK0_IO18
GND (Bank 0)
BK0_IO19
BK0_IO20
BK0_IO21
BK0_IO22
-
-
8P
8N
9P
-
NC
-
-
16N
-
NC
-
-
BK0
17P
PLL_FBK0
BK0_IO14
-
PLL_FBK0
7P/HSI0
-
-
-
-
-
7N/HSI0
8P/HSI0
8N/HSI0
9P
N4
N2
N1
P1
-
PLL_RST1
17N
PLL_RST1
9N
10P
10N
11P
-
BK0_IO15
BK0_IO16
BK0_IO17
BK0_IO18
GND (Bank 0)
BK0_IO19
BK0_IO20
-
PLL_RST1
-
18P
-
-
PLL_FBK1
18N
PLL_FBK1
PLL_FBK1
PLL_RST0
19P
PLL_RST0
PLL_RST0
-
-
-
-
-
R1
P3
-
BK0_IO39
BK0_IO40
GND (Bank 0)
BK0_IO41
-
19N
BK0_IO23
BK0_IO24
-
-
11N
12P
-
-
9N
CLK_OUT0
-
20P
CLK_OUT0
-
CLK_OUT0
-
10P
-
-
P2
CLK_OUT1
20N
BK0_IO25
CLK_OUT1
12N
BK0_IO21
CLK_OUT1
10N
71
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)
LFX500
LFX200
LFX125
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
516-Ball
Second
Second
Second
BGA Ball
Signal Name
-
Function
Reserved1
Signal Name
GND (Bank 0)
GCLK0
Function
Reserved1
Signal Name
-
Function
Reserved1
-
-
-
-
-
-
-
R2
R3
R4
T4
T3
T2
-
GCLK0
GCLK1
VCCP0
GNDP0
GCLK2
GCLK3
-
-
LVDS Pair0P
-
LVDS Pair0P
GCLK0
GCLK1
VCP0
GNDP
2
GCL
-
LVDS Pair0P
-
LVDS Pair0N
GCLK1
-
LVDS Pair0N
-
LVDS Pair0N
-
-
VCCP0
-
-
-
-
-
-
GNDP0
GCLK2
-
-
-
-
-
LVDS Pair1P
-
LVDS Pair1P
-
LVDS Pair1P
-
LVDS Pair1N
GCLK3
-
LVDS Pa
-
LVDS Pair1N
-
-
GND (Bank 1)
BK1_IO0
-
-
-
-
-
T1
-
BK1_IO0
GND (Bank 1)
BK1_IO1
BK1_IO2
-
CLK_OUT2
-
21P
-
CLK_OUT2
13
-
B_IO0
-
CLK_O
11P
-
-
CLK_OUT3
SS_CLKOUT0P
LK_OU
SS_CLKOUT0
-
U1
U2
-
CLK_OUT3
SS_CLKOUT0P
-
21N
22P
-
BK1_IO1
BK1_IO2
-
14P
-
BK1_IO1
BK1_IO2
GND (Bank
BK1O3
1N
12P
-
U3
BK1_IO3
SS_CLKOUT0N
22N
BK1_IO3
S_CLKOUT0
N
14N
_CLKO0
N
12N
V1
V2
BK1_IO4
BK1_IO5
BK1_IO6
GND (Bank 1)
BK1_IO7
BK1_IO8
BK1_IO9
BK1_IO10
-
PLL_FBK2
23P
23N
BK1_IO4
BK1_IO5
P_FBK2
15P
BK1_IO4
K1_IO5
PLFBK2
13P
PLL_FBK3
LL_FB
15N
PLL_FBK3
13N
V3
-
24P
-
-
-
-
-
-
-
-
-
-
-
V4
-
24N
-
NC
-
-
W1
Y1
-
25
-
-
NC
-
-
-
-
N
NC
-
-
NC
-
W2
-
SS_CLKINOP
2
BK1_IO6
GND (Bank 1)
BK1_IO7
BK1_IO8
-
SS_CLP
1
BK1_IO6
-
SS_CLKIN0P
14P
-
-
-
-
-
-
W3
Y2
BK1_IO11
BK1_IO12
-
SS_CLKIN
26N
_CLKIN0N
16N
BK1_IO7
BK1_IO8
GND (Bank 1)
BK1_IO9
NC
SS_CLKIN0N
14N
15P
-
-
27P
17P
-
-
-
-
-
-
Y4
BK1_IO13
BK1_IO1
GND (Bank 1)
BK1_IO15
K1_IO16
BKO17
BK1_I
BK1_IO19
BKIO20
K1_IO21
BK1_IO22
GND (Bank 1)
BK1_IO
BK1_
BK1_IO2
BK1_IO26
-
-
27N
BK1_IO9
-
17N
-
15N
-
Y3
-
28P
-
-
-
-
-
-
-
-
-
-
-
AA1
AA2
AA3
AB2
A
AB3
AA4
C1
-
28N
-
-
NC
-
-
-
2
-
-
NC
-
-
-
9N
NC
-
-
NC
-
-
HSI2A_SOUTP
0P
BK1_IO10
BK1_IO11
BK1_IO12
BK1_IO13
BK1_IO14
GND (Bank 1)
BK1_IO15
BK1_IO16
BK1_IO17
BK1_IO18
-
HSI1A_SOUTP
18P/HSI1
18N/HSI1
19P/HSI1
19N/HSI1
20P/HSI1
-
BK1_IO10
BK1_IO11
BK1_IO12
BK1_IO13
NC
-
16P
16N
17P
17N
-
HSI2A_SOU
3
HSI1A_SOUTN
-
PLL_R2
31P
PLL_RST2
PLL_RST2
PLL_R
N
PLL_RST3
PLL_RST3
HA_SINP
2P
HSI1A_SINP
-
-
-
-
-
-
AE1
AF1
AC3
-
A_SI
32N
HSI1A_SINN
20N/HSI1
21P/HSI1
21N/HSI1
22P/HSI1
-
NC
-
-
F1
33P/HSI2
33N/HSI2
34P/HSI2
-
VREF1
BK1_IO14
BK1_IO15
BK1_IO16
GND (Bank 1)
BK1_IO17
BK1_IO18
BK1_IO19
BK1_IO20
-
VREF1
18P
18N
19P
-
-
-
-
-
-
-
-
-
-
-
-
B_SOUTP
HSI1B_SOUTP
-
-
AC4
AD2
AD3
AE2
-
BK1_IO27
BK1_IO28
BK1_IO29
BK1_IO30
GND (Bank 1)
BK1_IO31
BK1_IO32
HSI2B_SOUTN
34N/HSI2
35P/HSI2
35N/HSI2
36P/HSI2
-
BK1_IO19
BK1_IO20
BK1_IO21
BK1_IO22
GND (Bank 1)
BK1_IO23
NC
HSI1B_SOUTN
22N/HSI1
23P/HSI1
23N/HSI1
24P/HSI1
-
19N
20P
20N
21P
-
-
-
-
-
HSI2B_SINP
HSI1B_SINP
-
-
AF2
AD4
HSI2B_SINN
-
36N/HSI2
37P/HSI2
HSI1B_SINN
-
24N/HSI1
-
BK1_IO21
NC
21N
-
72
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)
LFX500
LFX200
LFX125
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
516-Ball
Second
Second
Second
BGA Ball
Signal Name
BK1_IO33
BK1_IO34
BK1_IO35
BK1_IO36
BK1_IO37
BK1_IO38
GND (Bank 1)
BK1_IO39
BK1_IO40
BK1_IO41
TCK
Function
Reserved1
Signal Name
NC
Function
Reserved1
Signal Name
Function
Reserved1
AE3
AG1
AH1
AG2
AF3
AJ1
-
-
37N/HSI2
38P/HSI2
38N/HSI2
39P/HSI2
39N/HSI2
40P/HSI2
-
-
-
NC
NC
-
-
-
NC
-
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
C
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
-
-
-
-
-
-
-
-
-
AH2
AG3
AF4
AK2
AJ3
AG5
AH4
AK3
AJ4
-
-
40N/HSI2
41P
41N
-
NC
-
-
NC
-
-
-
BK1_IO24
BK1_IO25
TCK
-
25P/H1
C
-
-
-
-
N/HSI
NC
-
-
-
TCK
-
-
TMS
-
-
TMS
-
-
TMS
-
-
TOE
-
-
TOE
-
TOE
-
-
BK2_IO0
BK2_IO1
BK2_IO2
GND (Bank 2)
BK2_IO3
BK2_IO4
-
-
42P
42N
43P
-
BK2_IO0
BK2_IO1
BK2_IO2
GND (nk 2)
-
26P
BK2O0
BK2_IO
BK2_IO2
-
-
22P
-
26N
22N
-
-
27P
-
23P
-
-
-
-
-
AH5
AK4
-
-
43N
44P
-
27N
BK2
K2_IO4
Bank 2)
BK2_IO5
BK2_IO6
BK2_IO7
NC
-
23N
-
-
P
-
24P
-
-
-
-
AJ5
AG7
AH6
AK5
AJ6
AG8
-
BK2_IO5
BK2_IO6
BK2_IO7
BK2_IO8
BK2_IO9
BK2_IO10
GND (Bank 2)
BK2_IO11
BK2_IO1
BK2_IO13
BK2_IO14
_IO15
BK216
BK2_IO1
BK2O18
GN(Bank 2)
BK2_IO19
BK2_IO20
BK2_IO21
BK2_I
-
-
4
P
45
46P
46N
7P
-
BK2_
BK2_IO6
BK2_IO7
NC
-
28N
-
24N
-
-
P
-
25P
-
29
-
25N
-
-
-
-
-
-
NC
-
-
NC
-
-
-
NC
-
NC
-
-
-
-
-
-
-
-
AH7
AK6
AJ7
AH8
AG10
AK7
A
AH
-
-
47N
48P
48N
49P
N
0P
N
51
-
-
-
NC
-
-
-
-
-
NC
-
-
-
-
-
NC
-
-
-
-
NC
-
-
-
-
-
-
NC
-
-
-
-
NC
-
NC
-
-
NC
-
-
NC
-
-
-
NC
-
-
NC
-
-
-
-
-
-
-
-
-
AG1
AK8
AJ9
AH10
-
-
N
52P
52N
53P
-
NC
-
-
NC
-
-
BK2_IO8
BK2_IO9
BK2_IO10
GND (Bank 2)
BK2_IO11
BK2_IO12
BK2_IO13
BK2_IO14
-
-
30P
30N
31P
-
BK2_IO8
BK2_IO9
BK2_IO10
-
-
26P
26N
27P
-
VRE
VREF2
VREF2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AH11
AJ10
AK10
AH12
-
BK2_IO23
BK2_IO24
BK2_IO25
BK2_IO26
GND (Bank 2)
BK2_IO27
BK2_IO28
BK2_IO29
BK2_IO30
BK2_IO31
53N
54P
54N
55P
-
31N
32P
32N
33P
-
BK2_IO11
BK2_IO12
BK2_IO13
BK2_IO14
-
27N
28P
28N
29P
-
-
-
-
-
-
-
-
-
AJ11
AK11
AJ12
AG13
AH13
55N
56P
56N
57P
57N
BK2_IO15
NC
33N
-
BK2_IO15
NC
29N
-
NC
-
NC
-
BK2_IO16
BK2_IO17
34P
34N
BK2_IO16
BK2_IO17
30P
30N
73
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)
LFX500
LFX200
LFX125
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
516-Ball
Second
Second
Second
BGA Ball
Signal Name
BK2_IO32
-
Function
Reserved1
Signal Name
BK2_IO18
GND (Bank 2)
BK2_IO19
BK2_IO20
-
Function
Reserved1
Signal Name
Function
Reserved1
AJ13
-
-
58P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
35P
-
BK2_IO18
-
31P
-
GND (Bank 2
-
AK12
AK13
-
BK2_IO33
BK2_IO34
GND (Bank 2)
BK2_IO35
BK2_IO36
BK2_IO37
BK2_IO38
BK2_IO39
BK2_IO40
BK2_IO41
GND (Bank 2)
GND (Bank 3)
BK3_IO0
-
58N
59P
-
35N
36P
-
BK2_IO19
-
31N
-
BKIO20
-
32P
-
-
-
-
AH14
AJ14
AK14
AG15
AH15
AJ15
AK15
-
-
59N
60P
60N
61P
61N
62P
62N
-
BK2_IO21
BK2_IO22
BK2_IO23
BK2_IO24
BK2_IO25
NC
36N
37P
37
38
38N
B21
-
32N
-
N
-
-
-
NC
-
-
-
C
-
-
-
NC
-
-
NC
-
-
-
NC
-
NC
-
-
-
-
GND (Bank 2)
GND (Bank 3)
BK3_IO0
BK3_IO1
BK3O2
B
BK3_
GND (Bank 3)
BK3_IO7
BK3_IO8
-
-
-
-
-
-
-
-
-
-
AK16
AJ16
AH16
AG16
AK17
AJ17
AH17
-
-
63P
63N
64P
64N
65P
65N
6
39P
39N
40P
40N
P
4
42P
BK3_IO
BK3_IO1
3_IO2
BK3
K3_IO4
_IO5
BK3_IO6
-
33P
BK3_IO1
-
-
33N
BK3_IO2
-
-
34P
BK3_IO3
-
-
34N
BK3_IO4
-
-
35P
BK3_IO5
-
-
35N
BK3_IO6
-
-
36P
GND (Bank 3)
BK3_IO7
-
-
-
AJ18
AH18
-
-
66
67P
-
42
43P
-
BK3_IO7
BK3_IO8
GND (Bank 3)
BK3_IO9
BK3_IO10
BK3_IO11
NC
-
36N
BK3_IO8
-
-
37P
-
-
-
-
AG18
AK18
AK19
AJ19
AH19
AK20
-
BK3_IO9
-
7N
8P
68N
69P
69N
70P
BK3_IO9
BK3_IO10
BK11
GND k 3)
BK3_IO15
NC
43N
44P
44N
45P
45N
46P
-
-
37N
BK3_IO10
BK3_IO11
BK3_IO1
BK3_IO13
BK3_IO14
G(Bank 3)
BK315
BK3_IO1
BK3O17
B3_IO18
BK3_IO19
BK3_IO20
BK3_IO21
BK3_I
GND (B
BK3_IO23
BK3_IO24
BK3_IO25
BK3_IO26
BK3_IO27
BK3_IO28
BK3_IO29
BK3_IO30
GND (Bank 3)
BK3_IO31
-
-
38P
-
-
38N
-
-
-
-
NC
-
-
-
NC
-
-
-
-
-
-
-
AJ20
AH
AG
AK21
A
AH21
AG2
AJ22
-
-
0N
P
71
2P
N
73P
73N
74P
-
-
46N
-
NC
-
-
-
-
NC
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
NC
-
-
VF3
BK3_IO16
BK3_IO17
BK3_IO18
-
VREF3
47P
47N
48P
-
BK3_IO12
BK3_IO13
BK3_IO14
-
VREF3
39P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
39N
40P
-
AH22
AK23
AJ23
AH23
AK24
AJ24
AG23
AH24
-
74N
75P
75N
76P
76N
77P
77N
78P
-
BK3_IO19
NC
48N
-
BK3_IO15
NC
40N
-
-
-
-
-
-
-
-
-
NC
-
NC
NC
-
NC
NC
-
NC
NC
-
NC
NC
-
NC
NC
-
NC
-
-
AK25
78N
NC
-
NC
74
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)
LFX500
LFX200
LFX125
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
516-Ball
Second
Second
Second
BGA Ball
Signal Name
BK3_IO32
BK3_IO33
BK3_IO34
-
Function
Reserved1
Signal Name
NC
Function
Reserved1
Signal Name
NC
Function
Reserved1
AJ25
AG24
AK26
-
-
79P
-
-
-
-
-
79N
NC
-
-
NC
-
-
80P
BK3_IO20
-
-
49P
BK3_IO16
GND Bank 3)
K3_IO
B18
-
-
41P
-
-
-
-
-
-
AH25
AJ26
-
BK3_IO35
BK3_IO36
-
-
80N
BK3_IO21
BK3_IO22
GND (Bank 3)
BK3_IO23
NC
-
49N
-
41N
-
81P
-
50P
-
42P
-
-
81N
-
-
-
-
AH26
AK27
-
BK3_IO37
BK3_IO38
GND (Bank 3)
BK3_IO39
BK3_IO40
BK3_IO41
GSR
-
-
50
BK3_IO19
C
-
42N
-
82P
-
-
-
-
-
-
-
-
-
-
-
AJ27
AG26
AH27
AK28
AJ28
AK29
AH29
AG28
AF27
-
-
82N
NC
-
NC
-
-
-
83P
BK3_IO24
BK3_IO25
GSR
-
51P
BK3_IO20
BK3_IO21
GR
-
43P
-
83N
51N
-
43N
-
-
-
-
-
-
DXP
-
-
DXP
-
DXP
-
DXN
-
-
DXN
-
-
DXN
-
-
BK4_IO0
BK4_IO1
BK4_IO2
GND (Bank 4)
BK4_IO3
BK4_IO4
BK4_IO5
BK4_IO6
BK4_IO7
BK4_IO8
BK4_IO9
BK4_IO10
GND (Bank
BK4_IO11
BK4_IO12
-
-
84P
BK40
-
52P/HSI2
4_IO0
BK4
NC
-
44P
-
84N
52N/HSI2
-
44N
-
85P/HSI3
-
-
-
-
-
-
-
-
-
AF28
AJ30
AH30
AG29
AF29
AE28
AD27
AG30
-
-
85NSI3
HSI3
86N/3
87P/HSI3
87N/HSI3
8HSI3
8/HSI3
89P/HSI3
-
N
-
-
NC
-
-
-
NC
-
NC
-
-
-
NC
-
NC
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
NC
-
-
-
NC
-
NC
-
-
-
NC
-
NC
-
-
HSI3_SINP
BO2
SI2A_SINP
53P/HSI2
BK4_IO2
-
-
45P
-
-
-
-
-
AF30
AD28
-
SI3A_SN
89N/HSI3
90P/HSI3
HSI2A_SINN
53N/HSI2
BK4_IO3
BK4_IO4
GND (Bank 4)
BK4_IO5
NC
-
45N
-
54P/HSI2
-
46P
-
-
-
-
-
AC27
AE
AE
AD29
A0
AC28
-
BK413
BK4_IO1
BK4O15
B4_IO16
BK4_IO17
BK4_IO18
GND (Bank
BK4_I
BK4_I
BK4_IO21
BK4_IO22
BK4_IO23
BK4_IO24
BK4_IO25
BK4_IO26
GND (Bank 4)
BK4_IO27
BK4_IO28
-
-
9/HSI3
91HSI3
91N/H
HSI3
92HSI3
93P
BK4_IO5
BK4_IO6
BK4_IO7
BK4_IO8
BK4_IO9
BK4_IO10
GND (Bank 4)
BK4_IO11
BK4_IO12
BK4_IO13
BK4_IO14
BK4_IO15
NC
-
54N/HSI2
-
46N
HSI3A_SOUTP
HSI2A_SOUTP
55P/HSI2
-
-
HSI3A_SON
HSI2A_SOUTN
55N/HSI2
NC
-
-
-
-
56P/HSI2
BK4_IO6
BK4_IO7
NC
-
47P
VREF4
VREF4
56N/HSI2
VREF4
47N
HSISINP
HSI2B_SINP
57P/HSI2
-
-
-
-
-
-
-
-
-
AB28
AA27
AB29
AC29
AC30
AA28
Y27
_SIN
93N
HSI2B_SINN
57N/HSI2
NC
-
-
ST4
94P
PLL_RST4
58P/HSI2
BK4_IO8
BK4_IO9
BK4_IO10
BK4_IO11
NC
PLL_RST4
48P
RST5
94N
PLL_RST5
58N/HSI2
PLL_RST5
48N
I3B_SOUTP
95P
HSI2B_SOUTP
59P/HSI2
-
-
-
-
-
-
-
-
-
49P
HSI3B_SOUTN
95N
HSI2B_SOUTN
59N/HSI2
49N
-
-
-
-
-
-
-
96P
-
-
-
-
-
-
-
-
-
96N
NC
-
NC
-
Y28
97P
NC
-
NC
-
-
-
-
-
-
-
AA29
Y29
97N
NC
-
60P
-
NC
-
50P
-
98P
BK4_IO16
-
BK4_IO12
GND (Bank 4)
-
-
75
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)
LFX500
LFX200
LFX125
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
516-Ball
Second
Second
Second
BGA Ball
Signal Name
BK4_IO29
BK4_IO30
-
Function
Reserved1
Signal Name
BK4_IO17
BK4_IO18
GND (Bank 4)
BK4_IO19
NC
Function
Reserved1
Signal Name
BK4_IO13
BK4_IO14
-
Function
Reserved1
AA30
W28
-
-
98N
99P
-
60N
-
50N
SS_CLKIN1P
SS_CLKIN1P
61P
SS_C1P
51P
-
-
-
-
-
-
W29
Y30
W30
V27
-
BK4_IO31
BK4_IO32
BK4_IO33
BK4_IO34
GND (Bank 4)
BK4_IO35
BK4_IO36
BK4_IO37
BK4_IO38
BK4_IO39
BK4_IO40
GND (Bank 4)
BK4_IO41
-
SS_CLKIN1N
99N
SS_CLKIN1N
61N
BKIO15
NC
SS_CLK1N
51N
-
100P
-
-
-
-
-
100N
NC
-
-
-
-
-
101P
NC
-
-
N
-
-
-
-
-
-
-
-
-
-
V28
V29
V30
U30
U29
U28
-
-
101N
NC
-
-
C
-
-
PLL_FBK4
102P
BK4_IO20
BK4_IO21
BK4_IO22
BK4_IO23
BK4_IO24
-
PLL_FBK4
62P
4_IO16
BK4_IO17
BK4_IO18
BK4_IO19
BK4_O20
-
PLL
2P
PLL_FBK5
102N
PLL_FBK5
LL_FB
2N
SS_CLKOUT1P
103P
SS_CLKOUT1P
63P
SS_CLKOUT1
53P
SS_CLKOUT1N
103N
SS_CL1N
63N
SS_KOUT1N
53N
CLK_OUT4
104P
CLK_OUT4
64P
LK_OU
54P
-
-
-
-
T27
-
CLK_OUT5
104N
BK4_IO25
GND (nk 4)
GND
GCLK6
GCLK7
GND (Bank 5)
BK5_IO0
-
K_OUT5
64N
BK4_IO21
-
CLK_OUT5
54N
-
-
-
-
-
-
T28
T29
T30
R29
R28
R27
-
GCLK4
-
LVDS Pair2P
LVDS Pair2N
-
LVDS Pair2P
GC
GCLK5
CP1
GNDP1
GCLK6
GCLK7
-
-
LVDS Pair2P
GCLK5
-
-
LVDair2N
-
LVDS Pair2N
VCCP1
-
-
-
-
GNDP1
-
-
-
-
-
GCLK6
-
LVPair3P
LVDS P3N
-
-
LVDair3P
-
LVDS Pair3P
GCLK7
-
LVDS PN
-
LVDS Pair3N
-
-
-
-
-
-
R30
-
BK5_IO0
GND (Bank 5)
BK5_IO1
BK5_IO2
-
CLK_OT6
105P
C_OUT6
65P
BK5_IO0
-
CLK_OUT6
55P
-
-
-
-
-
P30
P29
-
LK_O
05N
BK5_IO1
BO2
C
65N
BK5_IO1
BK5_IO2
GND (Bank 5)
BK5_IO3
BK5_IO4
BK5_IO5
BK5_IO6
-
CLK_OUT7
55N
-
106P
-
66P
-
56P
-
-
-
-
-
-
P28
N30
N29
N28
BK5_IO3
BK5_IO4
5_IO5
BK56
ND (Ban)
BK5O7
5_IO8
BK5_IO9
BK5_IO10
-
PLL_RS7
106N
BK5
BK5_IO6
ND (Bank 5)
BK5_IO7
BK5_IO8
BK5_IO9
BK5_IO10
-
PLL_RST7
66N
PLL_RST7
56N
BK6
107P
PLL_FBK6
67P
PLL_FBK6
57P/HSI1
-
7N
-
67N
-
57N/HSI1
PLL-RST6
08P
PLL_RST6
68P
PLL_RST6
58P//HSI1
-
-
-
-
-
N2
M30
M
L30
-
PLL_FB
108
PLL_FBK7
68N
BK5_IO7
NC
PLL_FBK7
58N/HSI1
-
/HSI4
109HSI4
P/HSI4
-
-
69P
-
-
-
-
69N
NC
-
-
HSISINP
HSI3A_SINP
70P/HSI3
BK5_IO8
GND (Bank 5)
BK5_IO9
BK5_IO10
BK5_IO11
BK5_IO12
-
HSI1A_SINP
59P/HSI1
-
-
-
-
-
L29
M28
L28
K30
-
BK5_I
BK5_I
BK5_IO13
BK5_IO14
GND (Bank 5)
BK5_IO15
BK5_IO16
BK5_IO17
BK5_IO18
BK5_IO19
BK5_IO20
BK5_IO21
_SIN
110N/HSI4
111P/HSI4
111N/HSI4
112P/HSI4
-
BK5_IO11
BK5_IO12
BK5_IO13
BK5_IO14
GND (Bank 5)
BK5_IO15
NC
HSI3A_SINN
-
70N/HSI3
HSI1A_SINN
59N/HSI1
71P/HSI3
-
60P/HSI1
-
71N/HSI3
-
60N/HSI1
I4A_SOUTP
HSI3A_SOUTP
72P/HSI3
HSI1A_SOUTP
61P/HSI1
-
-
-
-
-
K29
L27
K28
H30
G30
J28
K27
HSI4A_SOUTN
112N/HSI4
113P/HSI4
113N/HSI4
114P/HSI4
114N/HSI4
115P/HSI4
115N/HSI4
HSI3A_SOUTN
72N/HSI3
BK5_IO13
NC
HSI1A_SOUTN
61N/HSI1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NC
NC
HSI4B_SINP
NC
NC
HSI4B_SINN
NC
NC
-
-
NC
NC
NC
NC
76
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)
LFX500
LFX200
LFX125
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
516-Ball
Second
Second
Second
BGA Ball
Signal Name
BK5_IO22
GND (Bank 5)
BK5_IO23
BK5_IO24
BK5_IO25
BK5_IO26
BK5_IO27
BK5_IO28
BK5_IO29
BK5_IO30
GND (Bank 5)
BK5_IO31
BK5_IO32
BK5_IO33
BK5_IO34
-
Function
Reserved1
Signal Name
Function
Reserved1
Signal Name
Function
Reserved1
J29
-
HSI4B_SOUTP
116P/HSI4
-
NC
-
-
-
NC
-
-
-
-
-
-
NC
-
H29
F30
G29
H28
H27
E30
F29
G28
-
HSI4B_SOUTN
116N/HSI4
117P/HSI5
117N/HSI5
118P/HSI5
118N/HSI5
119P/HSI5
119N/HSI5
120P/HSI5
-
NC
-
-
-
-
-
NC
-
-
C
-
-
-
NC
-
-
NC
-
-
HSI5A_SINP
NC
-
-
-
-
HSI5A_SINN
NC
-
-
N
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
C
-
-
HSI5A_SOUTP
NC
-
-
NC
-
-
-
-
-
-
-
G27
E29
F28
D30
-
HSI5A_SOUTN
120N/HSI5
121P/HSI5
121N/HSI5
122P/HSI5
-
NC
-
-
NC
-
-
VREF5
BK5_IO16
BK5_IO17
BK5_IO18
-
VR
3P/HSI3
BK5_IO14
BK5_O15
BK5_IO
ND (Bank 5
_IO17
N
EF5
62P/HSI1
-
-
N/HSI3
-
62N/HSI1
HSI5B_SINP
HSI3SINP
-
74P/HSI3
HSINP
63P/HSI1
-
-
-
-
C30
D29
D28
E28
-
BK5_IO35
BK5_IO36
BK5_IO37
BK5_IO38
GND (Bank 5)
BK5_IO39
BK5_IO40
BK5_IO41
CFG0
HSI5B_SINN
122N/HSI5
123P/HSI5
123N/HSI5
124P/HSI5
BK519
B
GND (B5)
BK5_IO23
BK5_IO24
BK5_IO25
CFG0
DONE
PROGRAM
BO0
BK3
BK6_IO4
-
I3B_NN
74N/HSI3
HSI1B_SINN
63N/HSI1
-
75P/HSI3
-
-
-
75SI3
NC
-
-
HSI5B_SOUTP
HSI3B_SOUTP
76PI3
_IO20
-
HSI1B_SOUTP
65P/HSI1
-
-
-
-
-
E27
C29
B30
A29
B28
A28
D26
C27
B27
-
HSI5B_SOUTN
1/HSI5
12
HSI3B_SOTN
76SI3
BK5_IO21
BK5_IO18
BK5_IO19
CFG0
DONE
PROGRAMb
BK6_IO0
BK6_IO1
BK6_IO2
-
HSI1B_SOUTN
65N/HSI1
-
77P/H
-
64P/HSI1
-
125N
-
77N/HSI3
-
64N/HSI1
-
-
-
-
-
-
DONE
-
-
-
-
-
PROGRAMb
BK6_IO0
-
-
-
-
-
INITb
126P
INITb
78P
INITb
66P
BK6_IO1
CCLK
126N
CLK
78N
CCLK
66N
BK6_IO2
-
127P
-
79P
-
67P
GND (Bank 6)
6_IO3
-
-
-
-
-
A27
C26
-
7N
-
79N
BK6_IO3
BK6_IO4
GND (Bank 6)
BK6_IO5
NC
-
67N
BK64
CSb
28P
CSb
80P
CSb
68P
-
-
-
-
-
-
B2
A26
C
D24
B25
A25
-
BK6O5
Read
128
BK6_IO5
NC
Read
80N
Read
68N
6_IO6
-
9P
-
-
-
-
BK6_IO7
-
1N
NC
-
-
NC
-
-
BK6_IO8
130P
NC
-
-
NC
-
-
BK6_IO9
-
130N
NC
-
-
NC
-
-
BK6_I
GND (B
BK6_IO11
BK6_IO12
BK6_IO13
BK6_IO14
BK6_IO15
BK6_IO16
BK6_IO17
BK6_IO18
GND (Bank 6)
BK6_IO19
-
131P
NC
-
-
NC
-
-
-
-
-
-
-
-
-
C24
D23
B24
C23
A24
C22
B23
B22
-
-
131N
NC
-
-
NC
-
-
-
132P
NC
-
-
NC
-
-
-
132N
NC
-
-
NC
-
-
-
133P
NC
-
-
NC
-
-
-
133N
NC
-
-
NC
-
-
-
134P
NC
-
-
-
NC
-
-
-
-
134N
NC
-
NC
-
DATA7
-
135P
BK6_IO6
-
DATA7
-
81P
-
BK6_IO6
-
DATA7
-
69P
-
-
A23
DATA6
135N
BK6_IO7
DATA6
81N
BK6_IO7
DATA6
69N
77
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)
LFX500
LFX200
LFX125
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
516-Ball
Second
Second
Second
BGA Ball
Signal Name
BK6_IO20
BK6_IO21
BK6_IO22
-
Function
Reserved1
Signal Name
BK6_IO8
BK6_IO9
BK6_IO10
GND (Bank 6)
BK6_IO11
BK6_IO12
-
Function
Reserved1
Signal Name
BK6_IO8
BK6_IO9
BK6_IO10
-
Function
Reserved1
D21
C21
B21
-
-
136P
136N
137P
-
-
82P
82N
83P
-
-
70P
VREF6
VREF6
V
70N
DATA5
DATA5
DATA5
71P
-
-
-
-
A21
D20
-
BK6_IO23
BK6_IO24
-
DATA4
137N
138P
-
DATA4
83N
84P
-
K6_IO
B12
GND (B6
BK6_IO13
B_IO14
-
DATA4
71N
-
-
-
72P
-
-
-
-
C20
B20
-
BK6_IO25
BK6_IO26
GND (Bank 6)
BK6_IO27
BK6_IO28
BK6_IO29
BK6_IO30
-
-
138N
139P
-
BK6_IO13
BK6_IO14
-
-
84
85
-
-
72N
DATA3
DATA3
-
DATA
73P
-
-
A20
C19
B19
A19
-
DATA2
139N
140P
140N
141P
-
BK6_IO15
BK6_IO16
BK6_IO17
BK6_IO18
GND (Bank 6
BK6_IO19
BK620
DATA2
86P
86N
87P
-
BK6_IO15
BK6_IO16
BK6_IO17
BK6_O18
GND (Ba6)
BK6_IO19
_IO20
BK6
NC
DATA2
3N
-
-
74P
-
-
74N
DATA1
DATA1
DATA1
75P
-
-
A18
D18
C18
B18
-
BK6_IO31
BK6_IO32
BK6_IO33
BK6_IO34
GND (Bank 6)
BK6_IO35
BK6_IO36
BK6_IO37
BK6_IO38
BK6_IO39
BK6_IO40
BK6_IO41
GND (Bank 6
GND (Bank
BK7_IO0
BK7_IO1
7_IO2
DATA0
141N
142P
142N
143P
-
DATA0
87N
88P
88N
P
DATA0
75N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
76P
76N
-
-
-
-
C17
B17
A17
D16
C16
B16
A16
-
14
4P
144
145P
145N
6P
46N
-
BK6_I
NC
89N
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
BK6_IO2
BK6_IO25
GND nk 6)
BK2
-
90P
90N
-
NC
-
NC
-
-
-
-
-
-
-
-
77P
77N
78P
-
A15
B15
C15
-
147P
147N
8P
-
91P
91N
92P
-
BK7_IO0
BK7_IO1
BK7_IO2
GND (Bank 7)
BK7_IO3
BK7_IO4
BK7_IO5
NC
D
A1
B14
C
-
BK7_IO
BK7O4
7_IO5
BK7_IO6
GND (Bank 7)
BK7_IO7
BK7_
BK7_I
BK7_IO10
BK7_IO11
BK7_IO12
-
N
149
9N
1P
-
BK7_IO3
BK7_IO4
BK7_IO5
BK7_IO6
GND (Bank 7)
BK7_IO7
BK7_IO8
BK7_IO9
BK7_IO10
BK7_IO11
BK7_IO12
-
92N
93P
93N
94P
-
78N
79P
79N
-
-
-
A13
B13
C13
D13
B12
C12
-
150N
151P
151N
152P
152N
153P
-
94N
95P
95N
96P
96N
97P
-
NC
-
NC
-
NC
-
BK7_IO6
BK7_IO7
BK7_IO8
GND (Bank 7)
BK7_IO9
BK7_IO10
-
80P
80N
81P
-
A12
A11
-
BK7_IO13
BK7_IO14
GND (Bank 7)
BK7_IO15
BK7_IO16
BK7_IO17
153N
154P
-
BK7_IO13
BK7_IO14
GND (Bank 7)
BK7_IO15
NC
97N
98P
-
81N
82P
-
-
-
-
-
-
B11
C11
D11
154N
155P
155N
98N
-
BK7_IO11
NC
82N
-
NC
-
NC
-
78
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 516-Ball fpBGA (Cont.)
LFX500
LFX200
LFX125
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
LVDS Pair/
sysHSI
516-Ball
Second
Second
Second
BGA Ball
Signal Name
BK7_IO18
BK7_IO19
BK7_IO20
BK7_IO21
BK7_IO22
GND (Bank 7)
BK7_IO23
BK7_IO24
-
Function
Reserved1
Signal Name
Function
Reserved1
Signal Name
Function
Reserved1
A10
B10
C10
D10
B9
-
-
156P
156N
157P
157N
158P
-
NC
NC
-
-
NC
NC
-
-
-
-
-
-
VREF7
BK7_IO16
BK7_IO17
BK7_IO18
-
VREF7
99P
BK7_IO12
BKIO13
K7_IO
VREF7
83P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
99N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83N
100P
84P
-
-
C9
A8
-
158N
159P
-
BK7_IO19
BK7_IO20
-
100N
BK7_5
BK7_IO16
GNBank 7)
7_IO17
NC
84N
10
85P
-
-
B8
C8
D8
A7
B7
C7
-
BK7_IO25
BK7_IO26
BK7_IO27
BK7_IO28
BK7_IO29
BK7_IO30
GND (Bank 7)
BK7_IO31
BK7_IO32
BK7_IO33
BK7_IO34
BK7_IO35
BK7_IO36
BK7_IO37
BK7_IO38
GND (Bank 7)
BK7_IO39
BK7_IO40
BK7_IO41
TDO
159N
160P
160N
161P
161N
162P
-
BK7_IO21
NC
01N
5N
-
NC
-
NC
-
NC
-
NC
-
NC
-
N
-
NC
-
NC
-
-
-
-
-
D7
A6
B6
B5
C6
A5
A4
B4
-
162N
163P
163N
164P
16
5P
16
166P
-
-
NC
-
-
N
-
NC
-
C
-
N
-
NC
-
NC
NC
-
NC
-
NC
-
86P
-
BK7_IO22
GND (Bank 7)
BK7_IO2
BK7_IO24
BK25
102P
BK7_IO18
-
-
C5
A3
A2
D5
C4
B3
6N
67P
167N
-
102N
BK7_IO19
BK7_IO20
BK7_IO21
TDO
86N
87P
87N
-
103P
103N
-
-
-
VCCJ
-
VCCJ
TDI
-
TDI
-
-
1. If a sysHSI Blois used, the indicated sysHreserved pinre unavailable for general purpose I/O use.
79
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA
LFX1200
680-Ball fpBGA
Signal Name
BK0_IO0
Second Function
LVDS Pair/sysHSI Reserved1
C4
B4
E6
-
-
0P
0N
BK0_IO1
-
BK0_IO2
-
GND (Bank 0)
BK0_IO3
-
D6
A4
E8
C5
C6
A6
A5
B6
-
-
1N
BK0_IO4
-
2P
BK0_IO5
-
2N
BK0_IO6
HSI0A_SOUTP
3P
BK0_IO7
HSI0A_SOUTN
3N
BK0_IO8
-
P
BK0_IO9
-
4N
BK0_IO10
GND (Bank 0)
BK0_IO11
BK0_IO12
BK0_IO13
BK0_IO14
BK0_IO15
BK0_IO16
BK0_IO17
BK0O18
GND ank 0)
BK0_19
B0_IO20
BK0_I21
_IO22
BK0_IO23
BK0_IO24
BK0_IO
BK0O26
GND (Bank 0)
BK_IO2
K0_28
_IO29
0_IO30
BK0_IO31
BK0_IO32
BK0_IO33
BK0_IO34
GND (Bank 0)
BK0_IO35
BK0_IO36
HSI0ASINP
5SI0
-
-
B5
B7
A7
D8
D7
D9
E10
C8
-
HSISINN
5/HSI0
/HSI0
6N/HSI0
7P/HSI0
7N/HSI0
8P/HSI0
8N/HSI0
9P/HSI0
-
VRE
-
_SOUTP
HI0B_SOUTN
-
-
HSI0BINP
-
C7
A8
A9
C9
B8
B
10
D1
-
HSB_SIN
9N/HSI0
10P/HSI0
10N/HSI0
11P/HSI0
11N/HSI0
12P/HSI0
12N/HSI0
13P/HSI1
-
-
-
A_SOUTP
HSI1A_SOUTN
-
-
HSI1A_SINP
-
D
10
C12
D12
C11
A12
A13
B13
-
HSI1A_SINN
13N/HSI1
14P/HSI1
14N/HSI1
15P/HSI1
15N/HSI1
16P/HSI1
16N/HSI1
17P/HSI1
-
-
-
HSI1B_SOUTP
HSI1B_SOUTN
-
-
HSI1B_SINP
-
B12
E14
HSI1B_SINN
-
17N/HSI1
18P/HSI1
80
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
D14
C13
D13
B14
A14
C15
-
Signal Name
BK0_IO37
BK0_IO38
BK0_IO39
BK0_IO40
BK0_IO41
BK0_IO42
GND (Bank 0)
BK0_IO43
BK0_IO44
BK0_IO45
BK0_IO46
BK0_IO47
BK0_IO48
BK0_IO49
BK0_IO50
GND (Bank 0)
BK0_IO51
BK0_IO52
BK0_IO53
BK0_IO54
BK0_55
BK0IO56
BK0_57
B0_IO58
ND (Bank 0)
K_IO59
BK0_IO60
BK0_IO61
GND (Bank 0)
GCK0
Second Function
LVDS Pair/sysHSI Reserved1
-
18N/HSI1
1P/HSI1
1NI1
20P/HSI1
20N/HSI1
21HSI2
-
HSI2A_SOUTP
HSI2A_SOUTN
-
-
HSI2A_SINP
-
D15
A15
C16
B15
B16
A16
B17
D16
-
HSI2A_SINN
21N/HSI2
22P/HS
22NSI2
P/HS2
2/SI2
24P/I
2N/HSI2
2/HSI2
-
-
-
HSI2B_SOUTP
HSI2B_OUTN
-
-
SI2BIN
-
E16
D17
C17
A18
D18
A17
E19
A19
-
B_SINN
25N/HSI2
26P/HSI2
26N/HSI2
27P/HSI2
27N/HSI2
28P/HSI2
28N/HSI2
29P
-
-
PLL_RS0
PLL_ST1
-
-
PLL_BK0
-
-
B19
C18
B1
-
_FBK1
29N
CLK_OUT0
30P
CLK_OUT1
30N
-
-
D
C19
E
21
B21
C21
B23
C23
B22
-
-
LVDS Pair0P
LVDS Pair0N
-
GC
-
CCP0
-
GN0
-
-
-
CLK2
LVDS Pair1P
LVDS Pair1N
31P
CLK3
-
BK1_IO0
CLK_OUT2
CLK_OUT3
SS_CLKOUT0P
-
BK1_IO1
31N
BK1_IO2
32P
GND (Bank 1)
BK1_IO3
-
C22
D21
E21
B24
SS_CLKOUT0N
PLL_FBK2
PLL_FBK3
SS_CLKIN0P
32N
BK1_IO4
33P
BK1_IO5
33N
BK1_IO6
34P
81
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
C24
A22
D22
A23
-
Signal Name
BK1_IO7
Second Function
LVDS Pair/sysHSI Reserved1
34N
SS_CLKIN0N
BK1_IO8
-
35P
BK1_IO9
-
3
BK1_IO10
GND (Bank 1)
BK1_IO11
BK1_IO12
BK1_IO13
BK1_IO14
BK1_IO15
BK1_IO16
BK1_IO17
BK1_IO18
GND (Bank 1)
BK1_IO19
BK1_IO20
BK1_IO21
BK1_IO22
BK1_IO23
BK1_IO24
BK1_25
BK1IO26
ND (nk 1)
B1_IO27
BK1_I28
K_IO29
BK1_IO30
BK1_IO31
BK1_IO32
BK1O33
BK1_4
GN(Bank 1)
BK1_35
1_IO36
1_IO37
BK1_IO38
BK1_IO39
BK1_IO40
BK1_IO41
BK1_IO42
GND (Bank 1)
BK1_IO43
BK1_IO44
-
36P
-
-
B25
D23
A24
A25
E24
D24
A26
D25
-
-
6N
PLL_RST2
37P
PLL_RST3
37N
-
38P
-
3N
-
39P
-
N
-
40
-
-
C25
B26
B27
D26
A27
A28
E26
C27
-
-
0N
-
41P/HSI3
41N/HSI3
42P/HSI3
42N/HSI3
43P/HSI3
43N/HSI3
44P/HSI3
-
-
-
-
-
HSI3A_SOTP
-
D27
B28
A30
C28
D2
31
B
E28
SI3AOUTN
44N/HSI3
45P/HSI3
45N/HSI3
46P/HSI3
46N/HSI3
47P/HSI3
47N/HSI3
48P/HSI3
-
-
-
SI3A_SINP
HSI3A_SINN
-
-
HSI3B_SOUTP
-
29
C29
B31
D30
E30
A32
C31
D31
-
HSI3B_SOUTN
48N/HSI3
49P/HSI4
49N/HSI4
50P/HSI4
50N/HSI4
51P/HSI4
51N/HSI4
52P/HSI4
-
-
-
HSI3B_SINP
HSI3B_SINN
-
-
HSI4A_SOUTP
-
C32
B32
HSI4A_SOUTN
-
52N/HSI4
53P/HSI4
82
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
A33
C33
B33
A34
A35
D32
-
Signal Name
BK1_IO45
BK1_IO46
BK1_IO47
BK1_IO48
BK1_IO49
BK1_IO50
GND (Bank 1)
BK1_IO51
BK1_IO52
BK1_IO53
BK1_IO54
BK1_IO55
BK1_IO56
BK1_IO57
BK1_IO58
GND (Bank 1)
BK1_IO59
BK1_IO60
BK1_IO61
TCK
Second Function
LVDS Pair/sysHSI Reserved1
-
53N/HSI4
5P/HSI4
5NI4
55P/HSI4
55N/HSI4
56HSI4
-
HSI4A_SINP
HSI4A_SINN
-
VREF1
HSI4B_SOUTP
-
D33
E32
C34
B34
B35
A36
D34
C35
-
HSI4B_SOUTN
56N/HSI4
57P
-
-
5N
58P
HSI4B_SINP
HSI4BSINN
N
59
-
-
59N
60P
-
-
-
E34
B36
C36
D39
D37
D38
E37
F35
E39
-
-
60N
61P
-
-
61N
-
-
TM
-
TE
-
-
BK2O0
-
62P
B2_IO1
62N
63P
BK2_IO2
-
GD Bank 2)
BK2_IO3
-
-
F39
F3
38
G
F37
G6
39
H35
-
-
63N
64P
BK2_IO4
-
BK2_IO5
-
64N
65P
BK2IO6
-
BK2
-
65N
66P
B2_IO8
-
BK2O9
-
66N
67P
2_IO10
(Bank 2)
BK2_IO11
BK2_IO12
BK2_IO13
BK2_IO14
BK2_IO15
BK2_IO16
BK2_IO17
BK2_IO18
-
-
-
F38
J37
-
67N
68P
VREF2
H36
G37
H37
H39
K35
J36
-
-
-
-
-
-
68N
69P
69N
70P
70N
71P
83
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
-
Signal Name
GND (Bank 2)
BK2_IO19
BK2_IO20
BK2_IO21
BK2_IO22
BK2_IO23
BK2_IO24
BK2_IO25
BK2_IO26
GND (Bank 2)
BK2_IO27
BK2_IO28
BK2_IO29
BK2_IO30
BK2_IO31
BK2_IO32
BK2_IO33
BK2_IO34
GND (Bank 2)
BK2_IO35
BK2_36
BK2IO37
BK2_38
B2_IO39
BK2_I40
K_IO41
BK2_IO42
GND (Bank 2)
BK2_IO43
BK2O44
BK2_5
B_IO4
BK2_47
2_IO48
2_IO49
BK2_IO50
GND (Bank 2)
BK2_IO51
BK2_IO52
BK2_IO53
BK2_IO54
BK2_IO55
BK2_IO56
Second Function
LVDS Pair/sysHSI Reserved1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K36
H38
J38
J39
L36
K38
M36
L37
-
71N
7
72N
73P
3N
74P
74N
75P
K39
L38
P35
N36
M37
L39
M38
M39
-
75N
P
76
77P
7N
78P
78N
79P
-
P36
R36
N37
P38
T35
R37
R38
P39
-
79N
80P
80N
81P
81N
82P
82N
83P
-
39
T
T36
T
36
U37
T39
V36
-
83N
84P
84N
85P
85N
86P
86N
87P
-
U38
U39
V38
V37
W36
W35
87N
88P
88N
89P
89N
90P
84
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
V39
Signal Name
BK2_IO57
BK2_IO58
GND (Bank 2)
BK2_IO59
BK2_IO60
BK2_IO61
GND (Bank 2)
GND (Bank 3)
BK3_IO0
Second Function
LVDS Pair/sysHSI Reserved1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
90N
91P
W37
-
W38
W39
AA39
-
91N
92P
2N
-
-
-
AA38
Y35
93P
9N
94P
BK3_IO1
AA37
-
BK3_IO2
GND (Bank 3)
BK3_IO3
AA35
AB39
AB38
AA36
AB37
AC39
AC38
AB36
-
94
95P
5N
96P
96N
97P
97N
98P
-
BK3_IO4
BK3_IO5
BK3_IO6
BK3_IO7
BK3_IO8
BK3_IO9
BK3_IO10
GND (nk 3)
BK3IO11
BK3_12
B3_IO13
BK3_I14
K_IO15
BK3_IO16
BK3_IO17
BK3_IO18
GND (ank 3)
BK3_9
B_IO2
BK3_21
3_IO22
3_IO23
BK3_IO24
BK3_IO25
BK3_IO26
GND (Bank 3)
BK3_IO27
BK3_IO28
BK3_IO29
BK3_IO30
AC37
AC36
AD39
AD37
AD36
AD35
AE8
D38
98N
99P
99N
100P
100N
101P
101N
102P
-
AE39
AF8
A37
AF39
AE36
AF36
AG38
AG39
-
102N
103P
103N
104P
104N
105P
105N
106P
-
AG37
AH37
AH38
AG36
106N
107P
107N
108P
85
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
AH39
AK39
AK38
AF35
-
Signal Name
BK3_IO31
BK3_IO32
BK3_IO33
BK3_IO34
GND (Bank 3)
BK3_IO35
BK3_IO36
BK3_IO37
BK3_IO38
BK3_IO39
BK3_IO40
BK3_IO41
BK3_IO42
GND (Bank 3)
BK3_IO43
BK3_IO44
BK3_IO45
BK3_IO46
BK3_IO47
BK3_IO48
BK3_49
BK3IO50
ND (nk 3)
B3_IO51
BK3_I52
K_IO53
BK3_IO54
BK3_IO55
BK3_IO56
BK3O57
BK3_8
GN(Bank 3)
BK3_59
3_IO60
3_IO61
GSR
Second Function
LVDS Pair/sysHSI Reserved1
-
108N
09P
0
110P
-
-
-
-
-
AJ37
AH36
AM39
AL38
AL39
AJ36
AH35
AL37
-
-
10N
111P
111N
112P
11N
113P
N
11
-
-
-
-
-
-
-
-
-
AN38
AM38
AK36
AM37
AN37
AN39
AL36
AK35
-
-
14N
115P
115N
116P
116N
117P
117N
118P
-
-
-
-
-
-
VR3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AP39
AM36
AP38
AR39
AN6
M35
AR
AP37
118N
119P
119N
120P
120N
121P
121N
122P
-
A39
AR37
AP36
AT38
AP35
AT37
AU36
AV36
AR34
-
122N
123P
123N
-
DXP
-
DXN
-
BK4_IO0
124P
124N
125P
-
BK4_IO1
BK4_IO2
GND (Bank 4)
BK4_IO3
AW36
125N
86
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
AW35
AV35
AV34
AU34
AT34
AU35
AT33
-
Signal Name
BK4_IO4
Second Function
LVDS Pair/sysHSI Reserved1
126P
-
BK4_IO5
-
26N
BK4_IO6
HSI5A_SINP
2
BK4_IO7
HSI5A_SINN
127N
BK4_IO8
-
128P
BK4_IO9
-
18N
BK4_IO10
GND (Bank 4)
BK4_IO11
BK4_IO12
BK4_IO13
BK4_IO14
BK4_IO15
BK4_IO16
BK4_IO17
BK4_IO18
GND (Bank 4)
BK4_IO19
BK4_IO20
BK4_IO21
BK4_22
BK4IO23
BK4_24
B4_IO25
BK4_I26
GD Bank 4)
BK4_IO27
BK4_IO28
BK4_IO29
BK4O30
BK4_1
B_IO3
BK4_33
4_IO34
(Bank 4)
BK4_IO35
BK4_IO36
BK4_IO37
BK4_IO38
BK4_IO39
BK4_IO40
BK4_IO41
BK4_IO42
HSI5A_SOUTP
29P/HSI5
-
-
AU33
AW34
AV33
AR32
AT32
AU32
AW33
AV32
-
HSI5A_SOUTN
129N/HS
130PHSI5
10N/HS5
13HSI5
131NSI
1P/HSI5
13N/HSI5
133P/HSI5
-
VREF4
-
HSI5BSINP
HSB_SINN
-
-
_SOUTP
-
AV31
AU31
AW32
AR30
AT31
AW31
AV30
AT30
-
5B_SOUTN
133N/HSI5
134P/HSI5
134N/HSI5
135P/HSI5
135N/HSI5
136P/HSI5
136N/HSI5
137P/HSI6
-
-
-
HSI6ASINP
HSI6A_SIN
-
A_SOUTP
-
AT29
AW0
U29
AT
AU28
AV8
A27
AU27
-
I6A_SOUTN
137N/HSI6
138P/HSI6
138N/HSI6
139P/HSI6
139N/HSI6
140P/HSI6
140N/HSI6
141P/HSI6
-
-
-
HSI6B_SINP
HSI6B_SINN
-
-
HSI6B_SOUTP
-
AV27
AW28
AR26
AW27
AT26
AV26
AR24
AT25
HSI6B_SOUTN
141N/HSI6
142P/HSI6
142N/HSI6
143P/HSI6
143N/HSI6
144P/HSI6
144N/HSI6
145P/HSI6
-
-
-
-
-
-
-
87
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
-
Signal Name
GND (Bank 4)
BK4_IO43
BK4_IO44
BK4_IO45
BK4_IO46
BK4_IO47
BK4_IO48
BK4_IO49
BK4_IO50
GND (Bank 4)
BK4_IO51
BK4_IO52
BK4_IO53
BK4_IO54
BK4_IO55
BK4_IO56
BK4_IO57
BK4_IO58
GND (Bank 4)
BK4_IO59
BK4_60
BK4IO61
ND (nk 4)
CLK4
Second Function
LVDS Pair/sysHSI Reserved1
-
-
45N
AW26
AV25
AT24
AU24
AU25
AW25
AW24
AU23
-
-
-
4
-
146N
-
147P
-
17N
PLL_RST4
148P
PLL_RST5
148N
-
149P
-
AT23
AV24
AW23
AV23
AU22
AR21
AT22
AV22
-
-
149N
-
5P
-
15
SS_LIN1P
51P
S_CLN1
51N
_FBK4
152P
_FBK5
152N
CLKOUT1P
153P
-
-
AV21
AT21
AU21
-
SS_CLKO1N
153N
CLK_UT4
154P
CLK_OU
154N
-
-
AT19
AU19
AW22
AR20
AU8
T18
LVDS Pair2P
LVDS Pair2N
-
GCL5
-
VCP1
-
GNDP1
-
-
GCLK6
-
LVDS Pair3P
LVDS Pair3N
-
GCLK7
-
GND (ank 5)
BK5
-
AV17
AV8
A21
-
CLK_OUT6
155P
B5_IO1
CLK_OUT7
155N
BK5O2
PLL_FBK6
156P
(Bank 5)
5_IO3
-
-
AV19
AR19
AW19
AW18
AW17
AT17
AV16
AU17
-
PLL_FBK7
156N
BK5_IO4
-
157P/HSI7
157N/HSI7
158P/HSI7
158N/HSI7
159P/HSI7
159N/HSI7
160P/HSI7
-
BK5_IO5
-
BK5_IO6
PLL_RST6
BK5_IO7
PLL_RST7
BK5_IO8
-
BK5_IO9
-
BK5_IO10
GND (Bank 5)
HSI7A_SINP
-
88
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
AT16
AW16
AU16
AV14
AV15
AU15
AW15
AT15
-
Signal Name
BK5_IO11
BK5_IO12
BK5_IO13
BK5_IO14
BK5_IO15
BK5_IO16
BK5_IO17
BK5_IO18
GND (Bank 5)
BK5_IO19
BK5_IO20
BK5_IO21
BK5_IO22
BK5_IO23
BK5_IO24
BK5_IO25
BK5_IO26
GND (Bank 5)
BK5_IO27
BK5_IO28
BK5_29
BK5IO30
BK5_31
B5_IO32
BK5_I33
K_IO34
GND (Bank 5)
BK5_IO35
BK5_IO36
BK5O37
BK5_8
B_IO3
BK5_40
5_IO41
5_IO42
ND (Bank 5)
BK5_IO43
BK5_IO44
BK5_IO45
BK5_IO46
BK5_IO47
BK5_IO48
BK5_IO49
Second Function
LVDS Pair/sysHSI Reserved1
160N/HSI7
16P/HSI7
1NSI7
162P/HSI7
162N/HSI7
163/HSI7
63N/HSI7
164P/HSI7
-
HSI7A_SINN
-
-
HSI7A_SOUTP
HSI7A_SOUTN
-
-
HSI7B_SINP
-
AR16
AW14
AW13
AR14
AT14
AT13
AV13
AU12
-
HSI7B_SINN
164NHSI7
15P/HS8
16HSI8
166PSI
1N/HSI8
16P/HSI8
167N/HSI8
168P/HSI8
-
-
-
HSI7_SOUTP
HSI7_OUTN
-
-
A_SINP
-
AU13
AV12
AT12
AR12
AT11
AW12
AU11
AV9
HSI8A_SINN
168N/HSI8
169P/HSI8
169N/HSI8
170P/HSI8
170N/HSI8
171P/HSI8
171N/HSI8
172P/HSI8
-
-
HSI8A_SOTP
HSI_SO
-
B_SINP
-
-
AV0
W10
A
AT10
A9
HSI8B_SINN
172N/HSI8
173P/HSI9
173N/HSI9
174P/HSI9
174N/HSI9
175P/HSI9
175N/HSI9
176P/HSI9
-
-
-
HSI8B_SOUTP
HSI8B_SOUTN
T9
-
AR10
AU8
-
HSI9A_SINP
-
-
AV8
HSI9A_SINN
176N/HSI9
177P/HSI9
177N/HSI9
178P/HSI9
178N/HSI9
179P/HSI9
179N/HSI9
AW8
AW7
AU7
-
-
HSI9A_SOUTP
HSI9A_SOUTN
-
AT8
AV7
AW6
VREF5
89
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
AU6
-
Signal Name
BK5_IO50
GND (Bank 5)
BK5_IO51
BK5_IO52
BK5_IO53
BK5_IO54
BK5_IO55
BK5_IO56
BK5_IO57
BK5_IO58
GND (Bank 5)
BK5_IO59
BK5_IO60
BK5_IO61
CFG0
Second Function
LVDS Pair/sysHSI Reserved1
HSI9B_SINP
180P/HSI9
-
-
AV6
AR8
AT7
AU5
AV5
AW5
AW4
AT6
-
HSI9B_SINN
1NSI9
181P
181N
12P
182N
183P
183N
18P
-
-
-
HSI9B_SOUTP
HSI9B_SOUTN
-
-
-
-
AV4
AR6
AU4
AT1
AT3
AT2
AP4
AP5
AR3
-
-
8N
18
85N
-
-
-
-
DONE
-
-
PROGRAMb
BK6_IO0
-
-
INITb
186P
186N
187P
-
BK6_IO1
CCLK
BK6_IO2
-
GND (nk 6)
BK_IO3
AR2
AP3
AR1
AP2
AP1
AN4
AM
N3
-
187N
188P
188N
189P
189N
190P
190N
191P
-
BK6O4
Sb
B6_IO5
Rd
BK6_IO6
-
BK_IO7
-
BK6_IO8
-
BK6_IO9
-
BK6_IO10
GND (ank 6)
BK6_1
B_IO1
BK6_13
6_IO14
6_IO15
BK6_IO16
BK6_IO17
BK6_IO18
GND (Bank 6)
BK6_IO19
BK6_IO20
BK6_IO21
BK6_IO22
-
-
AN2
A4
M3
AN1
AM2
AL4
AK5
AM1
-
-
191N
192P
192N
193P
193N
194P
194N
195P
-
VREF6
-
-
-
-
-
-
-
-
-
-
-
AK4
AL3
AL2
AL1
195N
196P
196N
197P
90
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
AK2
AK1
AJ4
AJ3
-
Signal Name
BK6_IO23
BK6_IO24
BK6_IO25
BK6_IO26
GND (Bank 6)
BK6_IO27
BK6_IO28
BK6_IO29
BK6_IO30
BK6_IO31
BK6_IO32
BK6_IO33
BK6_IO34
GND (Bank 6)
BK6_IO35
BK6_IO36
BK6_IO37
BK6_IO38
BK6_IO39
BK6_IO40
BK6_41
BK6IO42
ND (nk 6)
B6_IO43
BK6_I44
K_IO45
BK6_IO46
BK6_IO47
BK6_IO48
BK6O49
BK6_0
GN(Bank 6)
BK6_51
6_IO52
6_IO53
BK6_IO54
BK6_IO55
BK6_IO56
BK6_IO57
BK6_IO58
GND (Bank 6)
BK6_IO59
BK6_IO60
Second Function
LVDS Pair/sysHSI Reserved1
-
197N
98P
9
199P
-
-
-
-
-
AH4
AH3
AH2
AH1
AG4
AF5
AG3
AG2
-
-
19N
200P
200N
201P
20N
202P
0N
20
-
-
-
-
-
DATA7
DAT6
-
-
AF4
AF3
AG1
AE2
AF1
AF2
AE1
AE4
-
-
03N
204P
204N
205P
205N
206P
206N
207P
-
ATA5
ATA4
-
-
-
-
-
AD4
AD5
AD3
AD2
AD
C4
A
AC2
207N
208P
208N
209P
209N
210P
210N
211P
-
-
-
-
-
-
-
DATA3
-
C1
AB3
AB4
AB2
AB1
AA3
AA4
AA5
-
DATA2
211N
212P
212N
213P
213N
214P
214N
215P
-
-
-
DATA1
DATA0
-
-
-
-
-
-
AA2
AA1
215N
216P
91
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
Signal Name
BK6_IO61
GND (Bank 6)
GND (Bank 7)
BK7_IO0
Second Function
LVDS Pair/sysHSI Reserved1
Y5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
216N
-
-
W3
W1
W2
-
217P
217N
28P
-
BK7_IO1
BK7_IO2
GND (Bank 7)
BK7_IO3
W4
V1
V2
V3
V4
W5
U1
U2
-
218N
219P
21N
220P
2N
22
21N
22P
-
BK7_IO4
BK7_IO5
BK7_IO6
BK7_IO7
BK7_IO8
BK7_IO9
BK7_IO10
GND (Bank 7)
BK7_IO11
BK7_IO12
BK7_IO13
BK7_IO14
BK7_15
BK7IO16
BK7_17
B7_IO18
ND (Bank 7)
K_IO19
BK7_IO20
BK7_IO21
BK7_IO22
BK7O23
BK7_4
B_IO2
BK7_26
(Bank 7)
7_IO27
BK7_IO28
BK7_IO29
BK7_IO30
BK7_IO31
BK7_IO32
BK7_IO33
BK7_IO34
GND (Bank 7)
U3
U4
T1
T2
T3
R1
R2
T4
-
222N
223P
223N
224P
224N
225P
225N
226P
-
P1
P2
P
R4
T
M1
M
3
-
226N
227P
227N
228P
228N
229P
229N
230P
-
P4
L1
M3
L2
N4
K1
K2
P5
-
230N
231P
231N
232P
232N
233P
233N
234P
-
92
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 680-Ball fpBGA (Cont.)
LFX1200
680-Ball fpBGA
Signal Name
BK7_IO35
BK7_IO36
BK7_IO37
BK7_IO38
BK7_IO39
BK7_IO40
BK7_IO41
BK7_IO42
GND (Bank 7)
BK7_IO43
BK7_IO44
BK7_IO45
BK7_IO46
BK7_IO47
BK7_IO48
BK7_IO49
BK7_IO50
GND (Bank 7)
BK7_IO51
BK7_IO52
BK7_53
BK7IO54
BK7_55
B7_IO56
BK7_I57
K_IO58
GND (Bank 7)
BK7_IO59
BK7_IO60
BK7O61
TD
Second Function
LVDS Pair/sysHSI Reserved1
L3
J1
J2
M4
H1
J3
L4
M5
-
-
234N
35P
3
236P
236N
27P
237N
238P
-
-
-
-
-
-
-
-
-
H2
K4
G1
H3
J4
K5
G3
H4
-
-
23N
239P
3N
24
40N
41P
241N
242P
-
-
-
-
E7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F2
G2
H5
F3
F1
G4
E1
F4
-
242N
243P
243N
244P
244N
245P
245N
246P
-
E
F5
E
D2
D
1
246N
247P
247N
-
CCJ
-
T
-
1. If a sysHSI Block dicated sysHSI reserved pins are unavailable for general purpose I/O use.
93
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK0_IO0
Function
sysHSI Reserved1
Signal Name
Function
sysHSI Reserved1
D3
E3
C2
-
-
0P
0N
NC
-
-
BK0_IO1
-
NC
-
BK0_IO2
-
1P
NC
-
-
-
GND (Bank 0)
BK0_IO3
-
-
-
C1
E4
F5
D2
-
-
1N
NC
-
-
BK0_IO4
-
2P
BK0_IO
BK0_1
K0_I
ND ank 0)
K0_I
B0_IO4
B0_IO5
BK0_IO6
-
-
0P
BK0_IO5
-
2N
-
0N
BK0_IO6
HSI0A_SOUTP
3P
I0A_SOUTP
SI0
-
-
-
-
D1
F4
F3
E2
-
BK0_IO7
HSI0A_SOUTN
3N
HSI0A_SUTN
SI0
BK0_IO8
-
4P
2P/HSI0
BK0_IO9
-
4
-
2N/HSI0
BK0_IO10
GND (Bank 0)
BK0_IO11
BK0_IO12
BK0_IO13
BK0_IO14
BK0_IO15
BK0_IO16
BK0_IO17
BK0_IO18
GND Bank 0)
0_I19
BK0O20
BK0_IO1
BK0IO22
K0_IO23
BK0_IO24
BK0_IO25
BK0_I6
GND (Bank
7
B29
BK0_IO30
-
HSI0A_SINP
5HSI0
-
HSI0SINP
3P/HSI0
-
-
-
E1
G6
G5
F1
F2
G4
G3
G2
-
HSI0A_SINN
HSI0
SI0
HSI0
7P/HSI0
7N/HSI0
8P/HSI0
8N/HSI0
I0
BK0_IO7
BK9
K0_I8
C
H0SINN
3N/HSI0
VREF0
VREF0
4N/HSI0
-
-
4P/HSI0
HSI0_SOUTP
-
-
HI0BOUTN
NC
-
-
-
NC
-
-
-
NC
-
-
HSB_SINP
NC
-
-
-
-
-
-
G1
H3
H4
H1
2
7
J6
HSI0B_SINN
/HSI
HSI0
/HSI0
11P/HSI0
11N/HSI0
12P/HSI0
12N/HSI0
13P/HSI1
-
NC
-
-
-
NC
-
-
-
NC
-
-
HSI_SOUTP
NC
-
-
HSI1_SOUT
NC
-
-
-
NC
-
-
-
NC
-
-
HSIA_SINP
NC
-
-
-
-
-
-
J2
J4
J5
K1
-
HSI1A_SINN
13N/HSI1
14P/HSI1
14N/HSI1
15P/HSI1
-
NC
-
-
-
NC
-
-
-
NC
-
-
HSI1B_SOUTP
BK0_IO10
GND (Bank 0)
BK0_IO11
BK0_IO12
BK0_IO13
BK0_IO14
-
HSI0B_SOUTP
5P/HSI0
-
-
-
K2
K5
K4
L1
-
BK0_IO31
BK0_IO32
BK0_IO33
BK0_IO34
GND (Bank 0)
HSI1B_SOUTN
15N/HSI1
16P/HSI1
16N/HSI1
17P/HSI1
-
HSI0B_SOUTN
5N/HSI0
6P/HSI0
6N/HSI0
7P/HSI0
-
-
-
-
-
HSI1B_SINP
-
HSI0B_SINP
-
94
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK0_IO35
BK0_IO36
BK0_IO37
BK0_IO38
-
Function
sysHSI Reserved1
Signal Name
BK0_IO15
BK0_IO16
BK0_IO17
BK0_IO18
GND (Bank 0)
BK0_IO1
BK0_I20
BK0_IO1
BKO22
-
Function
sysHSI Reserved1
L2
L6
L5
M1
-
HSI1B_SINN
17N/HSI1
18P/HSI1
18N/HSI1
19P/HSI1
-
HSI0B_SI
7N/HSI0
8P/HSI0
8N/HSI0
9P/HSI1
-
-
-
-
-
HSI2A_SOUTP
SI1A_SOU
-
-
M2
L3
L4
M6
-
BK0_IO39
BK0_IO40
BK0_IO41
BK0_IO42
GND (Bank 0)
BK0_IO43
BK0_IO44
BK0_IO45
BK0_IO46
-
HSI2A_SOUTN
19N/HSI1
20P/HSI1
20N/HSI1
21P/HSI2
-
HSA_SUTN
9N/HSI1
10P/HSI1
SI1
I1
-
-
-
-
HSI2A_SINP
HSI1A_SINP
-
-
M5
M4
M3
N1
-
HSI2A_SINN
21N/HSI2
22P/HSI2
22HSI
23P/2
-
B0_IO23
_IO24
BK0_IO25
BK0_IO26
GND (Bank
BK0O27
BK0_I28
BK_IO29
BK0_I30
-
HSI1SINN
11N/HSI1
12P/HSI1
12N/HSI1
13P/HSI1
-
-
-
-
HSI2B_SOUTP
SI1B_SUTP
-
-
N2
N7
N6
P1
-
BK0_IO47
BK0_IO48
BK0_IO49
BK0_IO50
GND (Bank 0)
BK0_IO51
BK0_IO52
BK_IO53
0_I4
BKO55
BK0_I6
BK0O57
0_IO58
GND (Bank 0)
BK0_IO59
BK0_I60
-
HSI2B_SOUT
SI2
HSI2
4N/HSI2
25P/HSI2
-
HSI1B_SOUTN
13N/HSI1
14P/HSI1
14N/HSI1
15P/HSI1
-
-
-
-
-
SI2SINP
HSI1B_SINP
-
-
P2
N3
N4
P6
P5
P3
P4
7
-
HSI2B_SINN
25N/HS
2HSI2
26NSI2
P/HS
HSI2
/HSI2
28N/HSI2
29P
B0_IO31
BK0_IO32
BK0_IO33
BK0_IO38
BK0_IO35
BK0_IO36
BK0_IO39
BK0_IO34
GND (Bank 0)
BK0_IO37
BK0_IO40
GND (Bank 0)
BK0_IO41
-
HSI1B_SINN
15N/HSI1
16P/HSI1
16N/HSI1
19P
-
-
-
-
PLL_RST0
PLL_RST0
PLL_RST1
PLL_RST1
17N
-
-
18P
-
-
19N
P_FBK0
PLL_FBK0
17P
-
-
-
R6
1
_FBK1
29N
PLL_FBK1
18N
CLOUT0
30P
CLK_OUT0
20P
-
-
-
-
R2
-
61
0)
CLK_OUT1
30N
CLK_OUT1
20N
-
-
-
-
R3
R4
R5
T3
T4
T5
-
-
LVDS Pair0P
LVDS Pair0N
-
GCLK0
-
LVDS Pair0P
LVDS Pair0N
-
GCLK1
-
GCLK1
-
VCCP0
-
VCCP0
-
GNDP0
-
-
GNDP0
-
-
GCLK2
-
LVDS Pair1P
LVDS Pair1N
-
GCLK2
-
LVDS Pair1P
LVDS Pair1N
-
GCLK3
-
GCLK3
-
GND (Bank 1)
BK1_IO0
-
-
-
T2
CLK_OUT2
31P
BK1_IO0
CLK_OUT2
21P
95
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
-
Function
sysHSI Reserved1
Signal Name
GND (Bank 1)
BK1_IO1
BK1_IO2
-
Function
sysHSI Reserved1
-
-
-
31N
-
-
21N
22P
-
T1
U2
-
BK1_IO1
BK1_IO2
GND (Bank 1)
BK1_IO3
BK1_IO4
BK1_IO5
BK1_IO6
BK1_IO7
BK1_IO8
BK1_IO9
BK1_IO10
GND (Bank 1)
BK1_IO11
BK1_IO12
BK1_IO13
BK1_IO14
BK1_IO15
BK1_IO16
-
CLK_OUT3
CLK_UT3
SS_CLKOUT0P
32P
SS_CLKOUT0P
-
-
-
U1
U3
U4
V1
V2
U5
U6
V4
-
SS_CLKOUT0N
32N
BK1_IO3
BK1_IO
BK1_5
BK1_IO0
BKO11
K1_IO2
B1_IO13
_IO6
GND (Bank 1)
BK1_IO7
BK1_IO20
BK1O21
BK1_8
B_IO9
BK1_I14
ND (Bank 1)
B1_IO15
BK1_IO16
-
S_LKOUT0N
22N
23P
23N
P
P
27N
24P
-
PLL_FBK2
33P
PL_FK2
PLL_FBK3
33N
PLL_FBK3
SS_CLKIN0P
34P
S_CLKIN0P
SS_CLKIN0N
34N
SS_CLKIN0N
-
35P
-
-
35N
-
36
-
-
-
V3
V6
V7
W1
W2
W3
-
-
36
-
24N
31P
31N
25P
25N
28P
-
PLL_RST2
7P
L_ST2
PLL_RST3
N
PLL_RST3
-
8P
-
-
38N
-
39P
-
-
-
-
W4
W5
-
BK1_IO17
BK1_IO18
GND Bank 1)
1_I9
BKO20
BK1_I1
BK1O22
1_IO23
BK1_IO24
BK1_IO25
BK1_I26
GND (Bank )
27
B9
BK1_IO30
-
-
39N
-
28N
29P
-
-
P
-
-
-
W6
Y6
Y5
Y4
3
A5
AA
2
-
40N
BK1_IO17
NC
-
29N
-
-
HSI3
/HSI3
42P/HSI3
42N/HSI3
43P/HSI3
43N/HSI3
44P/HSI3
-
-
-
NC
-
-
-
NC
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
HSI3_SOUTP
BK1_IO18
-
HSI2A_SOUTP
30P
-
-
-
Y1
AB7
AB6
AA2
-
HSI3A_SOUTN
44N/HSI3
45P/HSI3
45N/HSI3
46P/HSI3
-
BK1_IO19
NC
HSI2A_SOUTN
30N
-
-
-
-
NC
-
-
HSI3A_SINP
BK1_IO22
GND (Bank 1)
BK1_IO23
NC
HSI2A_SINP
32P
-
-
-
AA1
AB5
AB4
AB2
-
BK1_IO31
BK1_IO32
BK1_IO33
BK1_IO34
GND (Bank 1)
HSI3A_SINN
46N/HSI3
47P/HSI3
47N/HSI3
48P/HSI3
-
HSI2A_SINN
32N
-
-
-
-
-
-
-
NC
-
HSI3B_SOUTP
-
NC
-
-
-
96
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK1_IO35
BK1_IO36
BK1_IO37
BK1_IO38
BK1_IO39
BK1_IO40
BK1_IO41
BK1_IO42
GND (Bank 1)
BK1_IO43
BK1_IO44
BK1_IO45
BK1_IO46
BK1_IO47
BK1_IO48
BK1_IO49
BK1_IO50
GND (Bank 1)
BK1_IO51
BK1_IO52
BK1_IO53
BK1_IO54
-
Function
sysHSI Reserved1
Signal Name
NC
Function
sysHSI Reserved1
AB1
AC6
AC5
AC2
AC1
AC4
AC3
AD2
-
HSI3B_SOUTN
48N/HSI3
49P/HSI4
49N/HSI4
50P/HSI4
50N/HSI4
51P/HSI4
51N/HSI4
52P/HSI4
-
-
-
-
NC
-
-
-
-
NC
-
HSI3B_SINP
NC
-
-
HSI3B_SINN
NC
-
-
-
NC
-
-
-
NC
-
-
HSI4A_SOUTP
NC
-
-
-
AD1
AD3
AD4
AE2
AE1
AD5
AD6
AF2
-
HSI4A_SOUTN
52N/HSI4
53P/HSI4
53N/SI4
54HSI
54N/4
/HSI
SI4
HSI4
-
NC
-
-
B1_IO32
_IO33
BK1_IO34
BK1_IO35
BK1_IO25
BK1O24
BK1_I26
-
37P/HSI3
37N
38P
38N
33N
33P
34P
-
-
-
HSI4A_SINP
HSI4A_SINN
-
-
-
VREF1
VREF1
HSI4B_SOUTP
HSI2B_SOUTP
-
-
AF1
AE3
AE4
AG1
-
HI4BOUTN
56N/HSI4
57P
BK1_I27
BK1_IO28
B1_IO29
BK1_IO30
GND (Bank 1)
BK1_IO31
BK1_IO36
BK1_IO37
BK1_IO38
GND (Bank 1)
BK1_IO39
BK1_IO40
BK1_IO41
TCK
HSI2B_SOUTN
34N
35P
35N
36P
-
-
-
-
57N
-
HSB_SINP
P
HSI2B_SINP
-
-
AG2
AE5
AF4
AH1
1_I5
BKO56
BK1_I7
BK1O58
(Bank 1)
BK1_IO59
BK1_IO60
BK1_I61
TCK
HSI4B_SINN
58N
HSI2B_SINN
36N
39P
39N
40P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9N
60P
-
H2
AF
G3
A4
AJ3
AK3
AG5
AH5
AJ4
-
60N
40N
41P
41N
-
61P
61N
-
-
TMS
-
-
TOE
-
B0
BK2_IO1
BK2_IO2
GND (Bank 2)
BK2_IO3
BK2_IO4
BK2_IO5
BK2_IO6
62P
BK2_IO0
BK2_IO1
BK2_IO2
GND (Bank 2)
BK2_IO3
BK2_IO4
BK2_IO5
BK2_IO6
42P
42N
43P
-
62N
63P
-
AK4
AG6
AH6
AJ5
63N
43N
44P
44N
45P
64P
64N
65P
97
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK2_IO7
Function
sysHSI Reserved1
Signal Name
BK2_IO7
BK2_IO8
BK2_IO9
BK2_IO10
GND (Bank 2)
BK2_IO1
BK2_I21
BK2_IO0
BKO12
K2_IO3
B2_IO14
_IO15
BK2_IO16
-
Function
sysHSI Reserved1
AK5
AE7
AF7
AG7
-
-
65N
66P
66N
67P
-
-
45N
BK2_IO8
-
-
46P
BK2_IO9
-
-
46N
BK2_IO10
GND (Bank 2)
BK2_IO11
BK2_IO12
BK2_IO13
BK2_IO14
BK2_IO15
BK2_IO16
BK2_IO17
BK2_IO18
GND (Bank 2)
BK2_IO19
BK2_IO20
-
-
-
47P
-
-
-
AH7
AE8
AF8
AJ6
AK6
AG8
AH8
AJ7
-
-
67N
68P
68N
69P
69N
70P
70
1P
-
-
47N
VREF2
VREF2
52N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P
N
49P
49N
50P
-
AK7
AF9
-
1N
P
-
BK2_IO17
BK2O18
GND (Bk 2)
BK_IO19
NC
50N
51P
-
AG9
AJ8
AK8
AD10
AE10
AJ9
-
BK2_IO21
BK2_IO22
BK2_IO23
BK2_IO24
BK2_IO25
BK_IO26
G(Bak 2)
BKO27
BK2_I8
BK2O29
2_IO30
BK2_IO31
BK2_IO32
BK2_I33
BK2_IO3
k 2)
B6
BK2_IO37
BK2_IO38
BK2_IO39
BK2_IO40
BK2_IO41
BK2_IO42
GND (Bank 2)
72N
73P
73N
74P
N
7P
-
51N
-
NC
-
NC
-
NC
-
NC
-
-
-
AK9
AF10
AG10
A10
10
AE1
11
A1
-
N
6P
76N
77P
77N
78P
78N
79P
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
-
-
AH11
AE12
AF12
AJ11
AK11
AG12
AH12
AK12
-
79N
80P
80N
81P
81N
82P
82N
83P
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
53P
-
BK2_IO22
-
98
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK2_IO43
BK2_IO44
BK2_IO45
BK2_IO46
-
Function
sysHSI Reserved1
Signal Name
BK2_IO23
BK2_IO24
BK2_IO25
BK2_IO26
GND (Bank 2)
BK2_IO2
BK2_I28
BK2_IO9
BKO30
-
Function
sysHSI Reserved1
AJ12
AD13
AE13
AK13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
83N
84P
84N
85P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
53N
54P
54N
55P
-
AJ13
AG13
AH13
AE14
-
BK2_IO47
BK2_IO48
BK2_IO49
BK2_IO50
GND (Bank 2)
BK2_IO51
BK2_IO52
BK2_IO53
BK2_IO54
-
85N
86P
86N
87P
-
55N
56P
N
AF14
AG14
AH14
AJ14
-
87N
88
8N
89
-
B2_IO31
_IO32
BK2_IO33
BK2_IO34
GND (Bank
BK2O35
BK2_I36
BK_IO37
BK2_I38
-
57N
58P
58N
59P
-
AK14
AE15
AF15
AG15
-
BK2_IO55
BK2_IO56
BK2_IO57
BK2_IO58
GND (Bank 2)
BK2_IO59
BK2_IO60
BK_IO61
G(Bak 2)
GND ank 3
BK3_I
BK3IO1
K3_IO2
GND (Bank 3)
BK3_IO3
BK3_4
BK3_IO5
6
N
0P
90N
91P
-
59N
60P
60N
61P
-
AH15
AJ15
AK15
-
91N
P
9N
-
B2_IO39
BK2_IO40
BK2_IO41
GND (Bank 2)
GND (Bank 3)
BK3_IO0
BK3_IO1
BK3_IO2
-
61N
62P
62N
-
-
-
AK16
AJ16
A16
-
3P
93N
94P
-
63P
63N
64P
-
AG1
16
A6
AK17
-
94N
95P
95N
96P
-
BK3_IO3
BK3_IO4
BK3_IO5
BK3_IO6
GND (Bank 3)
BK3_IO7
BK3_IO8
BK3_IO9
BK3_IO10
-
64N
65P
65N
66P
-
AJ17
AH17
AG17
AF17
-
B7
BK3_IO8
BK3_IO9
BK3_IO10
GND (Bank 3)
BK3_IO11
BK3_IO12
BK3_IO13
96N
97P
97N
98P
-
66N
67P
67N
68P
-
AE17
AH18
AG18
98N
99P
99N
BK3_IO11
BK3_IO12
BK3_IO13
68N
69P
69N
99
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK3_IO14
-
Function
sysHSI Reserved1
Signal Name
BK3_IO14
GND (Bank 3)
BK3_IO15
BK3_IO16
BK3_IO17
BK3_IO1
-
Function
sysHSI Reserved1
AJ18
-
-
100P
-
-
70P
-
-
-
AK18
AE18
AD18
AJ19
-
BK3_IO15
BK3_IO16
BK3_IO17
BK3_IO18
GND (Bank 3)
BK3_IO19
BK3_IO20
BK3_IO21
BK3_IO22
BK3_IO23
BK3_IO24
BK3_IO25
BK3_IO26
GND (Bank 3)
BK3_IO27
BK3_IO28
BK3_IO29
BK3_IO30
BK3_IO31
BK3_IO32
BK_IO33
3_I4
GND ank 3
BK3_I5
BK3O36
3_IO37
BK3_IO38
BK3_IO39
BK3_I40
-
-
100N
101P
101N
102P
-
-
70N
-
-
71P
-
-
71N
-
-
72P
-
-
-
AK19
AH19
AG19
AK20
AJ20
AF19
AE19
AH20
-
-
102N
103P
103N
104P
104
5P
10
06P
BK3_IO9
C
-
N
-
-
-
NC
-
-
NC
-
-
NC
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
-
-
-
AG20
AF20
AE20
AJ21
AK21
AG21
AF21
AK22
-
-
6N
107P
107N
108P
108N
9P
1N
10P
NC
-
-
-
C
-
-
NC
-
-
-
NC
-
-
-
NC
-
-
-
NC
-
-
-
NC
-
-
-
-
NC
-
-
-
-
-
AJ22
AE21
A21
2
AF2
23
-
10N
111P
111N
112P
112N
113P
-
NC
-
-
-
NC
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
-
BK3_IO22
GND (Bank 3)
BK3_IO23
BK3_IO24
-
-
74P
-
-
-
AH23
AJ23
-
41
GNk 3)
BK3_IO43
BK3_IO44
BK3_IO45
BK3_IO46
BK3_IO47
BK3_IO48
BK3_IO49
-
113N
114P
-
-
74N
75P
-
-
-
-
-
AK23
AF23
AE23
AJ24
AK24
AH24
AG24
-
114N
115P
115N
116P
116N
117P
117N
BK3_IO25
BK3_IO26
BK3_IO27
BK3_IO28
BK3_IO29
BK3_IO21
BK3_IO20
-
75N
76P
76N
77P
77N
73N
73P
-
-
-
-
-
-
-
-
-
-
VREF3
VREF3
100
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK3_IO50
GND (Bank 3)
BK3_IO51
BK3_IO52
BK3_IO53
BK3_IO54
BK3_IO55
BK3_IO56
BK3_IO57
BK3_IO58
GND (Bank 3)
BK3_IO59
BK3_IO60
BK3_IO61
GSR
Function
sysHSI Reserved1
Signal Name
BK3_IO30
GND (Bank 3)
BK3_IO31
BK3_IO32
BK3_IO33
BK3_IO3
BK3_I35
BK3_IO6
BKO37
K3_IO8
GN(Bank 3)
_IO39
BK3_IO40
BK3_IO41
GSR
Function
sysHSI Reserved1
AJ25
-
-
118P
-
-
78P
-
-
-
AK25
AF24
AE24
AK26
AJ26
AH25
AG25
AK27
-
-
118N
119P
-
78N
-
-
79P
-
119N
120P
-
79N
-
-
80P
-
120N
121P
-
80N
-
-
P
-
121N
122P
-
-
-
P
-
-
-
AJ27
AG26
AH26
AK28
AJ28
AH27
AG28
AF27
AF28
-
-
122
3P
-
82N
-
83P
-
12
-
-
83N
-
-
-
DXP
-
DP
-
-
DXN
-
-
DX
-
-
BK4_IO0
BK4_IO1
BK4_IO2
GND (Bank
BK4_IO3
BK_IO4
K4_I5
BKIO6
-
-
124P
B_IO0
BK4_1
BK4_IO2
GN(Bank 4)
BK4_IO3
BK4_IO4
BK4_IO5
BK4_IO10
GND (Bank 4)
BK4_IO11
BK4_IO12
BK4_IO13
BK4_IO14
-
-
84P
124N
125P
-
84N
-
-
85P/HSI3
-
-
-
-
AE26
AE27
AE28
AH30
-
-
5N
1P
-
85N/HSI3
86P/HSI3
86N/HSI3
89P/HSI3
-
-
-
-
26N
7P
-
HSI5A_SIN
HSI3A_SINP
-
-
-
AH29
A25
2
AG2
BK4IO7
K4_IO8
BK4_IO9
BK4_IO10
GND (Bk 4)
BK4_IO1
12
B4
BK4_IO15
BK4_IO16
BK4_IO17
BK4_IO18
GND (Bank 4)
BK4_IO19
BK4_IO20
HSA_SINN
127N
128P
HSI3A_SINN
89N/HSI3
90P/HSI3
90N/HSI3
91P/HSI3
-
-
-
128N
129P/HSI5
-
-
H_SOUTP
HSI3A_SOUTP
-
-
A0
AD27
AD28
AF29
AF30
AC25
AC26
AE29
-
HSI5A_SOUTN
129N/HSI5
130P/HSI5
130N/HSI5
131P/HSI5
131N/HSI5
132P/HSI5
132N/HSI5
133P/HSI5
-
BK4_IO15
BK4_IO17
BK4_IO16
BK4_IO6
BK4_IO7
BK4_IO8
BK4_IO9
NC
HSI3A_SOUTN
91N/HSI3
92N/HSI3
92P/HSI3
87P/HSI3
87N/HSI3
88P/HSI3
88N/HSI3
-
VREF4
VREF4
-
-
-
-
-
-
-
-
-
-
HSI5B_SINP
HSI5B_SINN
-
-
HSI5B_SOUTP
-
-
-
AE30
AC28
HSI5B_SOUTN
-
133N/HSI5
134P/HSI5
NC
-
NC
-
101
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK4_IO21
BK4_IO22
BK4_IO23
BK4_IO24
BK4_IO25
BK4_IO26
GND (Bank 4)
BK4_IO27
BK4_IO28
BK4_IO29
BK4_IO30
-
Function
sysHSI Reserved1
Signal Name
NC
Function
sysHSI Reserved1
AC27
AD29
AD30
AB24
AB25
AC29
-
-
134N/HSI5
135P/HSI5
135N/HSI5
136P/HSI5
136N/HSI5
137P/HSI6
-
-
-
HSI6A_SINP
NC
-
-
HSI6A_SINN
NC
-
-
-
NC
-
-
-
NC
-
-
HSI6A_SOUTP
NC
-
-
-
-
-
-
AC30
AB27
AB26
AB30
-
HSI6A_SOUTN
137N/HSI6
138P/HSI6
138N/HSI6
139P/HSI6
-
NC
-
-
C
-
-
NC
-
HSI6B_SINP
B4_IO18
GBank 4)
BK4_IO19
NC
HSI3SINP
93P
-
-
-
AB29
AA26
AA27
AA30
-
BK4_IO31
BK4_IO32
BK4_IO33
BK4_IO34
GND (Bank 4)
BK4_IO35
BK4_IO36
BK4_IO37
BK4_IO38
BK4_IO39
BK_IO40
4_I1
BKO42
GND (Ba4)
BK4O43
4_IO44
-
HSI6B_SINN
13/HSI
140PI6
N/HS
HSI6
-
HSI3_SINN
93N
-
-
-
-
NC
-
-
HSI6B_SOUT
BK4O22
-
HSI3B_SOUTP
95P
-
-
-
AA29
Y25
Y26
Y28
Y27
W25
W26
W27
-
HSI6_SOUTN
141N/HSI6
142P/HSI6
142N/HSI6
143P/HS
1HSI6
144PHSI6
N/H6
5P
BK_IO23
NC
HSI3B_SOUTN
95N
-
-
-
NC
-
-
-
NC
-
-
-
NC
-
-
-
NC
-
-
-
NC
-
-
-
BK4_IO24
-
-
96P
-
-
-
-
W28
4
-
-
145N
BK4_IO25
BK4_IO26
GND (Bank 4)
BK4_IO27
BK4_IO32
BK4_IO33
BK4_IO20
BK4_IO21
BK4_IO34
GND (Bank 4)
BK4_IO35
BK4_IO28
BK4_IO29
BK4_IO30
BK4_IO31
BK4_IO36
-
96N
97P
-
-
146P
-
-
-
V2
29
Y0
V27
V28
W29
-
BK4_IO45
BK4_I46
BK4_IO4
48
B0
GND (Bank 4)
BK4_IO51
BK4_IO52
BK4_IO53
BK4_IO54
BK4_IO55
BK4_IO56
-
146N
-
97N
100P
100N
94P
94N
101P
-
-
147P
-
-
147N
-
PLL_RST4
148P
PLL_RST4
PLL_RST5
148N
PLL_RST5
-
149P
-
-
-
-
W30
U25
U26
V29
V30
U28
-
149N
-
101N
98P
98N
99P
99N
102P
-
150P
-
-
150N
-
SS_CLKIN1P
SS_CLKIN1N
PLL_FBK4
151P
SS_CLKIN1P
SS_CLKIN1N
PLL_FBK4
151N
152P
102
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK4_IO57
BK4_IO58
GND (Bank 4)
BK4_IO59
BK4_IO60
-
Function
sysHSI Reserved1
Signal Name
BK4_IO37
BK4_IO38
-
Function
sysHSI Reserved1
U27
U29
-
PLL_FBK5
152N
153P
PLL_FBK
102N
SS_CLKOUT1P
SS_CLKUT1P
103P
--
-
-
-
103N
U30
T30
-
SS_CLKOUT1N
153N
BK4_IO39
BK4_IO40
GND (Ban
BK4_I41
-
S_CLKOUT
CLK_OUT4
154P
C_OUT4
104P
-
-
-
-
T29
-
BK4_IO61
GND (Bank 4)
GCLK4
CLK_OUT5
154N
CLK_OUT5
104N
-
-
-
T28
T27
T26
R28
R27
R26
-
-
LVDS Pair2P
LVDS Pair2N
-
GK4
-
r2P
Lair2N
-
GCLK5
-
GCLK
-
VCCP1
-
CCP1
GNDP1
-
-
DP1
-
-
GCLK6
-
LVDPair
LVDS 3N
-
GCLK6
LVDS Pair3P
LVDS Pair3N
-
GCLK7
-
GCLK7
-
GND (Bank 5)
BK5_IO0
-
-
-
-
R29
-
CLK_OUT6
P
BK5IO0
GND (Bk 5)
B_IO1
BK5_4
ND (Bank 5)
B5_IO7
BK5_IO2
BK5_IO5
BK5_IO6
BK5_IO3
BK5_IO8
BK5_IO9
BK5_IO10
-
CLK_OUT6
105P
-
-
-
-
R30
P30
-
BK5_IO1
BK5_IO2
GND (Bank 5)
BK5_IO3
BK5_IO4
BK_IO5
K5_I6
BKIO7
BK5_I
BK5IO9
5_IO10
GND (Bank 5)
BK5_IO11
BK5_I12
BK5_IO1
14
CLOUT7
155N
CLK_OUT7
105N
LLBK6
156P
PLL_FBK6
107P
-
-
-
-
P29
P27
P28
P26
P25
N27
N28
29
-
PLL_FBK7
156N
PLL_FBK7
108N
-
1HSI7
157NHSI7
P/H7
HSI7
P/HSI7
159N/HSI7
160P/HSI7
-
-
106P
-
-
107N
PLL_RST6
PLL_RST6
108P
PLL_RST7
PLL_RST7
106N
-
-
109P/HSI4
109N/HSI4
110P/HSI4
-
-
-
HSA_SINP
HSI4A_SINP
-
N3
25
N4
M29
-
A_SINN
160N/HSI7
161P/HSI7
161N/HSI7
162P/HSI7
-
BK5_IO11
BK5_IO12
BK5_IO13
BK5_IO14
GND (Bank 5)
BK5_IO15
BK5_IO16
BK5_IO17
BK5_IO18
-
HSI4A_SINN
110N/HSI4
111P/HSI4
111N/HSI4
112P/HSI4
-
-
-
-
-
HSI7A_SOUTP
HSI4A_SOUTP
-
-
M30
M28
M27
L30
-
B5
BK5_IO16
BK5_IO17
BK5_IO18
GND (Bank 5)
BK5_IO19
BK5_IO20
BK5_IO21
HSI7A_SOUTN
162N/HSI7
163P/HSI7
163N/HSI7
164P/HSI7
-
HSI4A_SOUTN
112N/HSI4
113P/HSI4
113N/HSI4
114P/HSI4
-
-
-
-
-
HSI7B_SINP
HSI4B_SINP
-
-
L29
M26
M25
HSI7B_SINN
164N/HSI7
165P/HSI8
165N/HSI8
BK5_IO19
BK5_IO20
BK5_IO21
HSI4B_SINN
114N/HSI4
115P/HSI4
115N/HSI4
-
-
-
-
103
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK5_IO22
-
Function
sysHSI Reserved1
Signal Name
BK5_IO22
GND (Bank 5)
BK5_IO23
BK5_IO24
BK5_IO25
BK5_IO2
-
Function
sysHSI Reserved1
K30
-
HSI7B_SOUTP
166P/HSI8
-
HSI4B_SOP
116P/HSI4
-
-
-
K29
L28
L27
L26
-
BK5_IO23
BK5_IO24
BK5_IO25
BK5_IO26
GND (Bank 5)
BK5_IO27
BK5_IO28
BK5_IO29
BK5_IO30
-
HSI7B_SOUTN
166N/HSI8
167P/HSI8
167N/HSI8
168P/HSI8
-
HSIB_SOUTN
116N/HSI4
-
-
117P/HSI5
-
-
117N/HSI5
HSI8A_SINP
H5A_INP
118P/HSI5
-
-
-
L25
K27
K26
J30
-
HSI8A_SINN
168N/HSI8
169P/HSI8
169N/HSI8
170P/HSI8
-
BK5_IO7
BKO28
K5_IO9
B5_IO30
GBank 5)
BK5_IO31
NC
SI5A_SINN
HSI5
-
-
SI5
-
-
HSI5
HSI8A_SOUTP
HSI5AOUT
120P/HSI5
-
-
-
J29
J26
J27
H30
-
BK5_IO31
BK5_IO32
BK5_IO33
BK5_IO34
GND (Bank 5)
BK5_IO35
BK5_IO36
BK5_IO37
BK5_IO38
BK5_IO39
BK_IO40
5_I1
BKO42
GND (Ba5)
BK5O43
5_IO44
BK5_IO45
BK5_IO46
BK5_I47
BK5_IO4
49
GNk 5)
BK5_IO51
BK5_IO52
BK5_IO53
BK5_IO54
-
HSI8A_SOUTN
17/HSI
171PI8
N/HS
HSI8
-
HSI5ASOUT
120N/HSI5
-
-
-
-
NC
-
-
HSI8B_SINP
NC
-
-
-
-
-
-
H29
J25
J24
G30
G29
H27
H28
F30
-
HSI_SINN
172N/HSI8
173P/HSI9
173N/HSI9
174P/HS
1HSI9
175PHSI9
N/H9
HSI9
-
C
-
-
NC
-
-
-
NC
-
-
HSI8B_SOUTP
NC
-
-
HSI8_SOUTN
NC
-
-
-
NC
-
-
-
NC
-
-
HSI9A_SIN
NC
-
-
-
-
-
-
F29
27
28
E3
29
H6
H25
D30
-
HSA_SINN
176N/HSI9
177P/HSI9
177N/HSI9
178P/HSI9
178N/HSI9
179P/HSI9
179N/HSI9
180P/HSI9
-
NC
-
-
-
NC
-
-
NC
-
-
H_SOUTP
NC
-
-
HSI9_SOUTN
NC
-
-
-
BK5_IO33
BK5_IO32
BK5_IO34
-
-
121N/HSI5
121P/HSI5
122P/HSI5
-
VREF5
VREF5
HSI9B_SINP
HSI5B_SINP
-
-
D29
F28
F27
C30
-
HSI9B_SINN
180N/HSI9
181P
BK5_IO35
BK5_IO36
BK5_IO37
BK5_IO38
GND (Bank 5)
BK5_IO39
NC
HSI5B_SINN
122N/HSI5
123P/HSI5
123N/HSI5
124P/HSI5
-
-
-
-
181N
-
HSI9B_SOUTP
182P
HSI5B_SOUTP
-
-
-
C29
G26
BK5_IO55
BK5_IO56
HSI9B_SOUTN
-
182N
HSI5B_SOUTN
-
124N/HSI5
-
183P
104
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK5_IO57
BK5_IO58
GND (Bank 5)
BK5_IO59
BK5_IO60
BK5_IO61
CFG0
Function
sysHSI Reserved1
Signal Name
NC
Function
sysHSI Reserved1
G25
F26
-
-
183N
184P
-
-
-
-
NC
-
-
-
-
-
-
E28
E27
D28
C27
B28
A28
D26
C26
B27
-
-
184N
185P
185N
-
NC
-
-
-
BK5_IO40
BK5_IO4
CFG
-
125P
-
-
125N
-
-
-
DONE
-
-
DON
-
PROGRAMb
BK6_IO0
-
-
RORAMb
BK6_I
6_IO1
_IO2
GND (Bank 6)
BK6_IO3
BK6_IO4
BK6IO5
BK6_6
B_IO7
BK6_8
BK6_IO9
B6_IO10
GND (Bank 6)
BK6_IO11
BK6_IO21
BK6_IO20
BK6_IO12
BK6_IO13
BK6_IO14
BK6_IO15
BK6_IO16
-
-
INITb
186P
186N
187
-
INIT
P
126N
127P
-
BK6_IO1
CCLK
CK
BK6_IO2
-
-
GND (Bank 6)
BK6_IO3
-
A27
D25
C25
B26
A26
F24
E24
A25
-
-
18
88P
N
9P
189N
190P
190N
191P
-
127N
128P
128N
129P
129N
130P
130N
131P
-
BK6_IO4
CSb
C
BK6_IO5
Read
READ
BK6_IO6
-
-
BK6_IO7
-
-
BK6_IO8
-
BK6_IO9
-
-
BK6_IO10
GND (Bank
BK_IO11
6_I2
BKO13
BK6_I4
BK6O15
6_IO16
BK6_IO17
BK6_IO18
GND (Bk 6)
BK6_IO1
20
B2
BK6_IO23
BK6_IO24
BK6_IO25
BK6_IO26
GND (Bank 6)
BK6_IO27
BK6_IO28
-
-
-
-
B25
D24
C24
A24
B24
3
23
A2
-
1N
92P
2N
93P
193N
194P
194N
195P
-
-
131N
136N
136P
132P
132N
133P
133N
134P
-
VREF6
VREF6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B3
C23
D23
E22
D22
G21
F21
B22
-
195N
196P
196N
197P
197N
198P
198N
199P
-
BK6_IO17
NC
134N
-
NC
-
NC
-
NC
-
NC
-
NC
-
NC
-
-
-
A22
E21
199N
200P
NC
-
NC
-
105
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK6_IO29
BK6_IO30
BK6_IO31
BK6_IO32
-
Function
sysHSI Reserved1
Signal Name
NC
Function
sysHSI Reserved1
D21
A21
B21
F20
-
-
200N
201P
201N
202P
-
-
-
-
NC
-
-
-
NC
-
-
DATA7
BK6_IO18
GND (Bank 6)
BK6_IO1
NC
DATA7
135P
-
-
-
E20
D20
-
BK6_IO33
BK6_IO34
GND (Bank 6)
BK6_IO35
BK6_IO36
BK6_IO37
BK6_IO38
BK6_IO39
BK6_IO40
BK6_IO41
BK6_IO42
GND (Bank 6)
BK6_IO43
BK6_IO44
BK6_IO45
BK6_IO46
BK6_IO47
BK_IO48
-
DATA6
202N
203P
-
AT6
135N
-
-
-
-
-
-
C20
F19
E19
B20
A20
D19
C19
A19
-
203N
204P
204N
205
5N
20
06N
P
-
C
-
DATA5
K6_IO2
B6_IO23
NC
DATA
P
137N
-
DATA4
DA4
-
-
-
NC
-
-
NC
-
-
-
NC
-
-
-
NC
-
-
-
-
-
-
B19
G18
F18
A18
B18
D18
-
-
207N
208P
208N
209P
9N
2P
-
C
-
-
BK6_I24
BK6_IO25
B6_IO32
BK6_IO33
BK6_IO34
GND (Bank 6)
BK6_IO35
BK6_IO26
GND (Bank 6)
BK6_IO27
BK6_IO28
BK6_IO29
BK6_IO30
BK6_IO31
BK6_IO36
BK6_IO37
BK6_IO38
-
-
138P
138N
142P
142N
143P
-
-
-
-
-
-
-
-
-
-
-
C18
F17
-
BKO49
BK6_I0
GND (ank 6)
6_IO51
BK6_IO52
BK6_IO53
BK6_I54
BK6_IO5
56
B8
GND (Bank 6)
BK6_IO59
BK6_IO60
BK6_IO61
GND (Bank 6)
GND (Bank 7)
BK7_IO0
-
0N
11P
-
-
143N
139P
-
DATA3
DATA3
-
-
17
17
C1
17
A7
F16
E16
D16
-
ATA2
211N
212P
212N
213P
213N
214P
214N
215P
-
DATA2
139N
140P
140N
141P
141N
144P
144N
145P
-
-
-
-
DTA1
DATA1
DATA0
DATA0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C16
B16
A16
-
215N
216P
216N
-
BK6_IO39
BK6_IO40
BK6_IO41
GND (Bank 6)
GND (Bank 7)
BK7_IO0
145N
146P
146N
-
-
-
-
A15
217P
147P
106
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK7_IO1
Function
sysHSI Reserved1
Signal Name
BK7_IO1
Function
sysHSI Reserved1
B15
C15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
217N
218P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
147N
BK7_IO2
BK7_IO2
148P
GND (Bank 7)
BK7_IO3
-
D15
E15
F15
A14
-
218N
219P
219N
220P
-
BK7_IO3
BK7_IO4
BK7_IO
BK7_6
GND (Ba7)
BKIO7
BK7_I
7_IO9
_IO10
-
148N
BK7_IO4
149P
BK7_IO5
149N
BK7_IO6
150P
-
B14
C14
D14
E14
-
BK7_IO7
220N
221P
221N
222
-
BK7_IO8
P
BK7_IO9
151N
BK7_IO10
GND (Bank 7)
BK7_IO11
BK7_IO12
BK7_IO13
BK7_IO14
-
152P
-
F14
C13
D13
B13
-
22
23P
N
4P
-
BK7_IO11
BK7_IO12
BK7O13
BK7_I14
GND Bank )
BK7_I15
BK7_IO16
B7_IO17
BK7_IO18
-
152N
153P
153N
154P
-
A13
F13
G13
A12
-
BK7_IO15
BK7_IO16
BK7_IO17
BK7_IO18
GND Bank 7)
7_I9
BKO20
BK7_I1
BK7O22
7_IO23
BK7_IO24
BK7_IO25
BK7_I26
GND (Bank )
27
B9
BK7_IO30
BK7_IO31
BK7_IO32
BK7_IO33
BK7_IO34
GND (Bank 7)
BK7_IO35
224N
225P
225N
6P
154N
155P
155N
156P
-
B12
C12
D12
A11
1
12
F1
11
26N
7P
27N
228P
228N
229P
229N
230P
-
BK7_IO19
NC
156N
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NC
NC
NC
NC
NC
NC
-
D11
E11
F11
B10
A10
D10
E10
A9
230N
231P
231N
232P
232N
233P
233N
234P
-
NC
NC
NC
NC
NC
NC
NC
NC
-
-
B9
234N
NC
107
Lattice Semiconductor
ispXPGA Family Data Sheet
ispXPGA Logic Signal Connections: 900-Ball fpBGA (Cont.)
LFX1200
LFX500
900 fpBGA
Ball
Second
LVDS Pair/
Second
LVDS Pair/
Signal Name
BK7_IO36
BK7_IO37
BK7_IO38
BK7_IO39
BK7_IO40
-
Function
sysHSI Reserved1
Signal Name
NC
Function
sysHSI Reserved1
F10
G10
A8
B8
D9
-
-
235P
235N
236P
236N
237P
-
-
-
-
NC
-
-
-
NC
-
-
-
NC
-
-
-
BK7_IO22
GND (Ban
BK7_I23
BK7_IO4
-
158P
-
-
-
E9
A7
-
BK7_IO41
BK7_IO42
GND (Bank 7)
BK7_IO43
BK7_IO44
BK7_IO45
BK7_IO46
BK7_IO47
BK7_IO48
BK7_IO49
BK7_IO50
GND (Bank 7)
BK7_IO51
BK7_IO52
BK7_IO53
BK7_IO54
BK_IO55
7_I6
BKO57
BK7_I8
GND (ank 7)
7_IO59
BK7_IO60
BK7_IO61
TD
-
237N
238P
-
-
158N
P
-
-
-
-
B7
C8
D8
A6
B6
E8
F8
C7
-
-
238N
239P
239
0P
24
41P
N
2P
-
K7_IO5
B7_IO26
_IO27
BK7_IO21
BK7_IO20
BK7_IO28
BK7O29
BK7_I30
GND Bank )
BK7_I31
BK7_IO32
B7_IO33
BK7_IO34
BK7_IO35
BK7_IO36
BK7_IO37
BK7_IO38
GND (Bank 7)
BK7_IO39
BK7_IO40
BK7_IO41
TDO
-
N
160P
160N
157N
157P
161P
161N
162P
-
-
-
-
-
VREF7
VRE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D7
E7
F7
A5
B5
C6
D6
D5
-
242N
243P
243N
4P
2N
45P
5N
46P
-
162N
163P
163N
164P
164N
165P
165N
166P
-
5
4
A4
3
B
C4
246N
247P
247N
-
166N
167P
167N
-
VCCJ
-
VCCJ
-
-
TDI
-
1. If a sysHSI Block iicated sysHSI reserved pins are unavailable for general purpose I/O use.
108
Lattice Semiconductor
ispXPGA Family Data Sheet
Part Number Description
LFX XXXX X X – XX XXXXX X
Device Family
LFX
Grade
C = Commercial
I = Industrial
Gates
Package
125 = 139K Gates
200 = 210K Gates
500 = 476K Gates
1200 = 1.25M Gates1
F256 = 256-Ball BGA
FH516 = 516-Ball fGA (wth Heat Spreader)
F516 = 51-Ball fpBG(ithout Heat Spreader)
FE680 = 80-Ball fSBGA
F900 = 90Ball fpGA
FN256 Lead-Free 256-Ball fpB
FN0 = Lad-Free 900-Bll fpBGA
sysHSI Support
Blank = Supports sysHSI
E = No sysHSI Support
Power Supply Voltage
B = 2.5/3.3V
C = 1.8V
Sed
5 = Ftest
4
= Slowest
1. Discontinued via PCN #03A-10.
2. Select products only. See Ordering Information tables cific support.
Ordering Information
Conventional Packaging
Commercal
Part Number
LFX125B-05F256C
LFX125B-04F256C
LFX125B-03F256C
LFX125C-04F56C
LFX125C3F256
LFX12B-0516C
LFX124F516
LFX125B-F6C
LF25-04F516C
LFX125-03F516C
LFX125B-05FH516
LFX125B-04FH516C
LFX125B-03FH516C1
LFX125C-04FH516C1
LFX125C-03FH516C1
LFX200B-05F256C
LFX200B-04F256C
LFX200B-03F256C
LFX200C-04F256C
LFX200C-03F256C
Gates
13
139K
139K
139K
139K
139K
39K
13
139K
139K
19K
139K
139K
139K
139K
210K
210K
210K
210K
210K
Voltag
2.5/3.3
eed Grade
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Balls
256
256
256
256
256
516
516
516
516
516
516
516
516
516
516
256
256
256
256
256
-5
-4
-3
-4
-3
-5
-4
-3
-4
-3
-5
-4
-3
-4
-3
-5
-4
-3
-4
-3
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
109
Lattice Semiconductor
ispXPGA Family Data Sheet
Commercial (Cont.)
Part Number
LFX200B-05F516C
LFX200B-04F516C
LFX200B-03F516C
LFX200C-04F516C
LFX200C-03F516C
LFX200B-05FH516C1
LFX200B-04FH516C1
LFX200B-03FH516C1
LFX200C-04FH516C1
LFX200C-03FH516C1
LFX500B-05F516C
LFX500B-04F516C
LFX500B-03F516C
LFX500C-04F516C
LFX500C-03F516C
LFX500B-05FH516C1
LFX500B-04FH516C1
LFX500B-03FH516C1
LFX500C-04FH516C1
LFX500C-03FH516C1
LFX500B-05F900C
LFX500B-04F900C
LFX500B-03F900C
LFX500C-04F900C
LFX500C-03F900C
LFX1200B-05F900C2
LFX1200B-04F900C2
LFX1200B-0300C2
LFX1200-04F90C2
LFX120C-0F900C
LFX1205FE60C2
LFX1200B4E680C2
LF20B-03FE680C2
LFX120C-04FE680C2
LFX1200C-03FE68
Gates
210K
210K
210K
210K
210K
210K
210K
210K
210K
210K
476K
476K
476K
476K
476K
476K
476K
476K
476K
476K
476K
K
476K
476K
47
1.25M
1.25M
1.25M
1.25M
1.25M
.25M
1.2
1.25M
1.25M
1.25M
Voltage
2.5/3.3
2.5/3.3
2.5/3.3
1.8
Speed Grade
Package
fpBGA
fpBGA
fpBGA
fpBGA
fBGA
fpBG
GA
fpB
pBGA
pBGA
fpBGA
fpBGA
fpBGA
fpGA
fpBG
fpBGA
fp
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpSBGA
fpSBGA
fpSBGA
fpSBGA
fpSBGA
Balls
516
516
516
516
516
516
516
516
516
6
516
516
516
516
516
516
516
516
900
900
900
900
900
900
900
900
900
900
680
680
680
680
680
-5
-4
-3
-4
-3
-5
-4
-3
-4
-3
5
-3
-4
-3
-5
-4
-3
-
-3
-5
-3
-4
-3
-5
-4
-3
-4
-3
-5
-4
-3
-4
-3
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
2.5/3.3
1
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
1. FH516 package wao F516 via PCN #09A-08.
2. Discontinued via PCN .
110
Lattice Semiconductor
ispXPGA Family Data Sheet
“E-Series” Commercial
Part Number
LFX125EB-05F256C
LFX125EB-04F256C
LFX125EB-03F256C
LFX125EC-04F256C
LFX125EC-03F256C
LFX125EB-05F516C
LFX125EB-04F516C
LFX125EB-03F516C
LFX125EC-04F516C
LFX125EC-03F516C
LFX125EB-05FH516C1
LFX125EB-04FH516C1
LFX125EB-03FH516C1
LFX125EC-04FH516C1
LFX125EC-03FH516C1
LFX200EB-05F256C
LFX200EB-04F256C
LFX200EB-03F256C
LFX200EC-04F256C
LFX200EC-03F256C
LFX200EB-05F516C
LFX200EB-04F516C
LFX200EB-03F516C
LFX200EC-04F516C
LFX200EC-03F516C
LFX200EB-05FH516C
LFX200EB-04FH516C1
LFX200EB-03516C1
LFX200E-04FH56C1
LFX2EC-0FH516
LFX50005F5C
LFX500EB516C
L500B-03F516C
LFX50EC-04F516C
LFX500EC-03F51
LFX500EB-05FH516
LFX500EB-04FH516C1
LFX500EB-03FH516C1
LFX500EC-04FH516C1
LFX500EC-03FH516C1
LFX500EB-05F900C
LFX500EB-04F900C
LFX500EB-03F900C
LFX500EC-04F900C
Gates
139K
139K
139K
139K
139K
139K
139K
139K
139K
139K
139K
139K
139K
139K
139K
210K
210K
210K
210K
210K
210K
K
210K
10K
210K
210K
210K
210K
210K
210K
476K
K
476K
476K
476K
476K
476K
476K
476K
476K
476K
476K
476K
476K
Voltage
2.5/3.3
2.5/3.3
2.5/3.3
1.8
Speed Grade
Package
fpBGA
fpBGA
fpBGA
fpBGA
fBGA
fpBA
GA
fpB
pBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpA
fpBGA
pBGA
fpA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Balls
256
256
256
256
256
516
516
516
16
6
516
516
516
256
256
256
256
256
516
516
516
516
516
516
516
516
516
516
516
516
516
516
516
516
516
516
516
516
900
900
900
900
-5
-4
-3
-4
-3
-5
-4
-3
-4
-3
5
-
-3
-4
-3
-5
-4
-3
-
-3
-5
-3
-4
-3
-5
-4
-3
-4
-3
-5
-4
-3
-4
-3
-5
-4
-3
-4
-3
-5
-4
-3
-4
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
2.53
1
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
111
Lattice Semiconductor
ispXPGA Family Data Sheet
“E-Series” Commercial (Cont.)
Part Number
Gates
476K
Voltage
1.8
Speed Grade
Package
fpBGA
Balls
900
900
900
900
900
900
680
680
680
LFX500EC-03F900C
-3
-5
-4
-3
-4
-3
-5
-4
-3
-4
3
LFX1200EB-05F900C2
LFX1200EB-04F900C2
LFX1200EB-03F900C2
LFX1200EC-04F900C2
LFX1200EC-03F900C2
LFX1200EB-05FE680C2
LFX1200EB-04FE680C2
LFX1200EB-03FE680C2
LFX1200EC-04FE680C2
LFX1200EC-03FE680C2
1.25M
1.25M
1.25M
1.25M
1.25M
1.25M
1.25M
1.25M
1.25M
1.25M
2.5/3.3
2.5/3.3
2.5/3.3
1.8
fpBGA
fpBGA
fpBGA
fBGA
1.8
fpBG
2.5/3.3
2.5/3.3
2.5/3.3
1.8
BGA
fpSG
SBGA
pSBGA
fpSBGA
1.8
1. FH516 package was converted to F516 via PCN #09A-08.
2. Discontinued via PCN #03A-10.
“E-Series” dustrl
Part Number
LFX125EB-04F256I
LFX125EB-03F256I
LFX125EC-03F256I
LFX125EB-04F516I
LFX125EB-03F516I
LFX125EC-03F516I
LFX125EB-04FH516I1
LFX125EB-03FH516I1
LFX125EC-03FH516I
LFX200EB-04F256I
LFX200EB-03256I
LFX200E-03F2I
LFX20EB-04F516I
LFX2003F51I
FX200E316I
LFB-04FH516I1
LFX200B-03FH516I1
LFX200EC-03FH51
LFX500EB-04F516I
LFX500EB-03F516I
LFX500EC-03F516I
LFX500EB-04FH516I1
LFX500EB-03FH516I1
LFX500EC-03FH516I1
LFX500EB-04F900I
LFX500EB-03F900I
LFX500EC-03F900I
Gates
139K
139K
139K
139K
1K
139K
139K
1
139K
210K
210K
210K
210K
10K
210
210K
210K
20K
476K
476K
476K
476K
476K
476K
476K
476K
476K
2.
1.8
Speed Grade
Paae
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Balls
256
256
256
516
516
516
516
516
516
256
256
256
516
516
516
516
516
516
516
516
516
516
516
516
900
900
900
-4
-
-3
-4
-3
-4
-3
-3
-4
-3
-3
-4
-3
-3
-4
-3
-3
-4
-3
-3
-4
-3
-3
-4
-3
-3
2.5/3.3
2.5/3.3
1.8
2.5/3.
2.5/3.3
1.8
2.5/3.3
2.5/3.3
1.8
2.5/3.3
2.5/3.3
1.8
2.5/3.3
2.5/3.3
1.8
2.5/3.3
2.5/3.3
1.8
2.5/3.3
2.5/3.3
1.8
112
Lattice Semiconductor
ispXPGA Family Data Sheet
“E-Series” Industrial (Cont.)
Part Number
Gates
1.25M
1.25M
1.25M
1.25M
1.25M
1.25M
Voltage
2.5/3.3
2.5/3.3
1.8
Speed Grade
Package
fpBGA
Balls
900
900
900
680
680
680
LFX1200EB-04F900I2
LFX1200EB-03F900I2
LFX1200EC-03F900I2
LFX1200EB-04FE680I2
LFX1200EB-03FE680I2
LFX1200EC-03FE680I2
-4
-3
-3
-4
-3
-3
fpBGA
fpBGA
2.5/3.3
2.5/3.3
1.8
fpSBG
fpBGA
fpSBA
1. FH516 package was converted to F516 via PCN #09A-08.
2. Discontinued via PCN #03A-10.
Lead-Free Packaging
Commercial
Part Number
LFX125B-05FN256C
LFX125B-04FN256C
LFX125B-03FN256C
LFX125C-04FN256C
LFX125C-03FN256C
LFX200B-05FN256C
LFX200B-04FN256C
LFX200B-03FN256C
LFX200C-04FN256C
LFX200C-03FN256C
LFX500B-05FN900C
LFX500B-04FN900C
LFX500B-03FN900C
LFX500C-04FN900C
LFX500C-03FN900C
Gates
139K
139K
139K
139K
139K
210K
210K
210K
210
210K
476K
476K
76K
476K
476K
Voltage
2.5/3.3
2.5/3.3
2.5/3.3
1.8
Speed Gade
Package
256
256
256
256
256
256
256
256
256
256
900
900
900
900
900
-5
-4
-3
4
-3
-5
-4
-
-4
-
-5
-4
-3
-4
-3
Lead-Free fpGA
Lead-FrefpBG
Lead-Free fBGA
LeaFree fpBA
ad-FrfpBA
LeaFree fpBGA
Leadee fpBGA
ead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
2.5
2.5/3.
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
“ESeries” Commercial
aNumber
FX125E5N256C
LFB-04FN256C
LFX125B-03FN256C
LFX125EC-04FN25
LFX125EC-03FN25
LFX200EB-05FN256C
LFX200EB-04FN256C
LFX200EB-03FN256C
LFX200EC-04FN256C
LFX200EC-03FN256C
LFX500EB-05FN900C
LFX500EB-04FN900C
LFX500EB-03FN900C
Gates
13
139K
139K
39K
139K
210K
210K
210K
210K
210K
476K
476K
476K
Voltage
2.5/3.3
2.5/3.3
2.5/3.3
1.8
Speed Grade
Package
Balls
256
256
256
256
256
256
256
256
256
256
900
900
900
-5
-4
-3
-4
-3
-5
-4
-3
-4
-3
-5
-4
-3
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
Lead-Free fpBGA
1.8
2.5/3.3
2.5/3.3
2.5/3.3
1.8
1.8
2.5/3.3
2.5/3.3
2.5/3.3
113
Lattice Semiconductor
ispXPGA Family Data Sheet
“E-Series” Commercial (Cont.)
Part Number
LFX500EC-04FN900C
LFX500EC-03FN900C
Gates
476K
476K
Voltage
1.8
Speed Grade
Package
Balls
900
-4
-3
Lead-Free fpBGA
Lead-Free fpBGA
1.8
900
“E-Series” Industrial
Part Number
LFX125EB-04FN256I
LFX125EB-03FN256I
LFX125EC-03FN256I
LFX200EB-04FN256I
LFX200EB-03FN256I
LFX200EC-03FN256I
LFX500EB-04FN900I
LFX500EB-03FN900I
LFX500EC-03FN900I
Gates
139K
139K
139K
210K
210K
210K
476K
476K
476K
Voltage
2.5/3.3
2.5/3.3
1.8
Speed Grade
Paage
Balls
256
256
256
256
00
900
900
-4
-3
-3
-4
-3
-
-4
3
-3
LeaFree BGA
Lead-e fpBG
Lead-FrefpGA
Lead-ree fpBGA
Leadree fpBGA
Lead-Free fpBGA
Lead-Free fpGA
Lead-Free fpGA
Lead-FrfpBG
2.5/3.3
2.5/3.3
1.8
2.5/3.3
2.5/3.3
1.8
For Further Information
In addition to this data sheet, the following Lattial notes may be helpfuwhen signing with the ispXPGA
Family:
• TN1028, ispXPGA Memory Usae Guideline
• TN1003, sysCLOCK PLL Usaand Design Guidelines
• TN1000, sysIO Usage Guidelines r Lattice Devices
• TN1026, ispXP Configuon Usage uidelines
• TN1020, sysHSI UsaGuidelines
• TN1043, Power Estimion in iXPGA Device
Revision Histry
Date
Versi
Change Summary
—
—
revious Lattice eleas
Septembe2003
07
Improved tycal Icc data for LFX125B/C and LFX500B/C.
Improved exrnal swihing characteristics timing numbers for LFX125B/C.
Imprved PIC tnnumbers for LFX125B/C.
ImoveIODLY timing numbers for LFX125B/C.
Improved extrnal switching characteristics timing numbers for LFX500B/C.
Iroved PIC timing numbers for LFX500B/C.
mpred tIOINDLY timing numbers for LFX500B/C.
nhanced CDR functionality description.
Logic Signal Connections and Signal Descriptions - removed CDRLOCK, LOSS and EXLOSS
descriptions.
January 2004
June 2004
07.1
08.0
Added lead-free package designators.
Updated CDR specifications and reference notes. Removed Source Synchronous (SS:No CAL)
mode references for the sysHSI blocks.
Revised Figures 16 and 24 for clarification.
Clarification of VCC sysHSI Block for 1.8V devices.
Updated IIL and IIH max specification.
Updated LVTTL and PCI 3.3 to support 5V tolerance.
114
Lattice Semiconductor
ispXPGA Family Data Sheet
Revision History (Cont.)
Date
Version
Change Summary
Updated Global Clock Input Setup time specifications.
Clarification of Serial Out LVDS test condition.
June 2004
(cont.)
08.0
(cont.)
Clarification of REFCLK, SS_CLKIN peak-to-peak period jitter conditio
Added sysHSI Reserved pins and footnote.
Removed industrial ordering part numbers.
Added “E” Series product family.
July 2004
August 2004
December 2004
April 2005
09.0
10.0
10.1
10.2
11.0
12.0
13.0
Final release.
Updated NC Connections table.
Clarification of IDK specification.
April 2005
Select lead-free packages release.
July 2005
Added lead-free 516 fpBGA ordering part nubers.
April 2007
Removed lead-free 680 fpSBGA information frPart Number Descrition ad Ordng Part
Number tables. Removed lead-free 516 fpGA fLFX125 from Ordeg Prt Number tables.
November 2007
July 2008
14.0
14.1
15.0
Removed lead-free 516 fpBGA inrmation from art Number Desiption nd dering Part
Number tables.
Added 516 fpBGA package withoeat speader to Part Nuer Descption and Ordering Part
Number tables.
February 2010
Ordering part numbeGA Family Selection Guidtable have been updated per PCN
#03A-10 (discontinuatioXPGA 1200 dev
References to system gathanged to "funcnal ges."
115
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