LFXP10C-4FN388C_技术文档

LatticeXP Family Data Sheet

DS1001 Version 05.1, November 2007

LatticeXP Family Data Sheet

Introduction

July 2007

Data Sheet DS1001

■ Flexible I/O Buffer

• Programmable sysIO™ buffer supports wide

range of interfaces:

Features

■ Non-volatile, Inﬁnitely Reconﬁgurable

• Instant-on – powers up in microseconds

• No external conﬁguration memory

− LVCMOS 3.3/2.5/1.8/1.5/1.2

− LVTTL

– SSTL 18 Class I

− SSTL 3/2 Class I, II

– HSTL15 Class I, III

− HSTL 18 Class I, II, III

− PCI

• Excellent design security, no bit stream to

intercept

• Reconﬁgure SRAM based logic in milliseconds

• SRAM and non-volatile memory programmable

through system conﬁguration and JTAG ports

■ Sleep Mode

− LVDS, Bus-LVDS, LVPECL, RSDS

• Allows up to 1000x static current reduction

■ Dedicated DDR Memory Support

■ TransFR™ Reconﬁguration (TFR)

• Implements interface up to DDR333 (166MHz)

• In-ﬁeld logic update while system operates

■ sysCLOCK™ PLLs

■ Extensive Density and Package Options

• 3.1K to 19.7K LUT4s

• Up to 4 analog PLLs per device

• Clock multiply, divide and phase shifting

• 62 to 340 I/Os

• Density migration supported

■ System Level Support

• IEEE Standard 1149.1 Boundary Scan, plus

ispTRACY™ internal logic analyzer capability

• Onboard oscillator for conﬁguration

• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V

power supply

■ Embedded and Distributed Memory

• 54 Kbits to 396 Kbits sysMEM™ Embedded

Block RAM

• Up to 79 Kbits distributed RAM

• Flexible memory resources:

− Distributed and block memory

Table 1-1. LatticeXP Family Selection Guide

Device

PFU/PFF Rows

LFXP3

16

LFXP6

24

LFXP10

32

LFXP15

40

LFXP20

44

PFU/PFF Columns

PFU/PFF (Total)

LUTs (K)

24

30

38

48

56

384

3

720

6

1216

10

1932

15

2464

20

Distributed RAM (KBits)

EBR SRAM (KBits)

EBR SRAM Blocks

12

23

39

61

79

54

72

216

24

324

36

396

44

6

8

V

Voltage

1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V 1.2/1.8/2.5/3.3V

CC

PLLs

2

4

Max. I/O

136

188

244

300

340

Packages and I/O Combinations:

100-pin TQFP (14 x 14 mm)

144-pin TQFP (20 x 20 mm)

208-pin PQFP (28 x 28 mm)

256-ball fpBGA (17 x 17 mm)

388-ball fpBGA (23 x 23 mm)

484-ball fpBGA (23 x 23 mm)

62

100

136

100

142

188

244

188

268

300

188

268

340

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

1-1

DS1001 Introduction_01.5a July 6, 2007 3:01 p.m.

Introduction

LatticeXP Family Data Sheet

Lattice Semiconductor

Introduction

The LatticeXP family of FPGA devices combine logic gates, embedded memory and high performance I/Os in a

single architecture that is both non-volatile and inﬁnitely reconﬁgurable to support cost-effective system designs.

The re-programmable non-volatile technology used in the LatticeXP family is the next generation ispXP™ technol-

ogy. With this technology, expensive external conﬁguration memories are not required and designs are secured

from unauthorized read-back. In addition, instant-on capability allows for easy interfacing in many applications.

The ispLEVER^®design tool from Lattice allows large complex designs to be efﬁciently implemented using the Lat-

ticeXP family of FPGA devices. Synthesis library support for LatticeXP is available for popular logic synthesis tools.

The ispLEVER tool uses the synthesis tool output along with the constraints from its ﬂoor planning tools to place

and route the design in the LatticeXP device. The ispLEVER tool extracts the timing from the routing and back-

annotates it into the design for timing veriﬁcation.

Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeXP family.

By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,

increasing their productivity.

1-2

LatticeXP Family Data Sheet

Architecture

July 2007

Data Sheet DS1001

Architecture Overview

The LatticeXP architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-

spersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) as shown in Figure 2-

1.

On the left and right sides of the PFU array, there are Non-volatile Memory Blocks. In conﬁguration mode this non-

volatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™ peripheral port. On power up,

the conﬁguration data is transferred from the Non-volatile Memory Blocks to the conﬁguration SRAM. With this

technology, expensive external conﬁguration memories are not required and designs are secured from unautho-

rized read-back. This transfer of data from non-volatile memory to conﬁguration SRAM via wide busses happens in

microseconds, providing an “instant-on” capability that allows easy interfacing in many applications.

There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit

without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register func-

tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks

are optimized for ﬂexibility, allowing complex designs to be implemented quickly and efﬁciently. Logic Blocks are

arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the out-

side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every

three rows of PFF blocks there is a row of PFU blocks.

Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and

right edges of the device can be conﬁgured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast

memory blocks. They can be conﬁgured as RAM or ROM.

The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in

Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and

route software tool automatically allocates these routing resources.

At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These

PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the

clocks. The LatticeXP architecture provides up to four PLLs per device.

Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG

port which allows for serial or parallel device conﬁguration. The LatticeXP devices are available for operation from

3.3V, 2.5V, 1.8V and 1.2V power supplies, providing easy integration into the overall system.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

2-1

DS1001 Architecture_02.0 July 6, 2007 3:03 p.m.

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-1. LatticeXP Top Level Block Diagram

Programmable I/O Cell

(PIC) includes sysIO

Interface

sysMEM Embedded

Block RAM (EBR)

Non-volatile Memory

JTAG Port

sysCONFIG Programming

Port (includes dedicated

and dual use pins)

PFF (PFU without

RAM)

sysCLOCK PLL

Programmable

Functional Unit (PFU)

PFU and PFF Blocks

The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform

Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform

Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term

PFU to refer to both PFU and PFF blocks.

Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-

tions to and from PFU blocks are from routing.There are 53 inputs and 25 outputs associated with each PFU block.

Figure 2-2. PFU Diagram

From

Routing

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

LUT4 &

CARRY

Slice 3

Slice 0

Slice 1

Slice 2

D

FF/

D

FF/

D

FF/

Latch

To

Routing

2-2

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Slice

Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and

some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and

LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock

select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic of the slice.

The registers in the slice can be conﬁgured for positive/negative and edge/level clocks.

There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).

There are 7 outputs: 6 to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associated

with each slice.

Figure 2-3. Slice Diagram

To / From

Different slice / PFU Fast Carry In (FCI)

Slice

OFX1

F1

A1

B1

C1

D1

CO

F

LUT4 &

CARRY

D

SUM

FF/

Latch

Q1

CI

To

From

Routing

M1

M0

OFX0

F0

LUT

Expansion

Mux

CO

A0

B0

C0

LUT4 &

CARRY

F

D0

OFX0

SUM

D

FF/

Latch

Q0

CI

Control Signals

selected and

inverted per

CE

CLK

LSR

slice in routing

Note: Some interslice signals

are not shown.

To / From

Different slice / PFU Fast Carry Out (FCO)

2-3

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Table 2-1. Slice Signal Descriptions

Function

Input

Type

Signal Names

Description

Data signal

A0, B0, C0, D0 Inputs to LUT4

A1, B1, C1, D1 Inputs to LUT4

Input

Data signal

Input

Multi-purpose

Control signal

Inter-PFU signal

Data signals

Inter-PFU signal

M0

M1

Multipurpose Input

Clock Enable

Input

CE

Input

LSR

Local Set/Reset

System Clock

Fast Carry In¹

Input

CLK

Input

FCIN

F0, F1

Q0, Q1

OFX0

OFX1

FCO

Output

LUT4 output register bypass signals

Register Outputs

Output of a LUT5 MUX

Output of a LUT6, LUT7, LUT8²MUX depending on the slice

For the right most PFU the fast carry chain output¹

1. See Figure 2-2 for connection details.

2. Requires two PFUs.

Modes of Operation

Each Slice is capable of four modes of operation: Logic, Ripple, RAM and ROM. The Slice in the PFF is capable of

all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.

Table 2-2. Slice Modes

Logic

Ripple

RAM

SP 16x2

N/A

ROM

PFU Slice

PFF Slice

LUT 4x2 or LUT 5x1

2-bit Arithmetic Unit

ROM 16x1 x 2

Logic Mode: In this mode, the LUTs in each Slice are conﬁgured as 4-input combinatorial lookup tables. A LUT4

can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this

lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger lookup

tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other Slices.

Ripple Mode: Ripple mode allows the efﬁcient implementation of small arithmetic functions. In ripple mode, the fol-

lowing functions can be implemented by each Slice:

• Addition 2-bit

• Subtraction 2-bit

• Add/Subtract 2-bit using dynamic control

• Up counter 2-bit

• Down counter 2-bit

• Ripple mode multiplier building block

• Comparator functions of A and B inputs

- A greater-than-or-equal-to B

- A not-equal-to B

- A less-than-or-equal-to B

Two additional signals: Carry Generate and Carry Propagate are generated per Slice in this mode, allowing fast

arithmetic functions to be constructed by concatenating Slices.

RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x1-bit memory.

Through the combination of LUTs and Slices, a variety of different memories can be constructed.

2-4

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-

ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3

shows the number of Slices required to implement different distributed RAM primitives. Figure 2-4 shows the dis-

tributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices, one Slice functions

as the read-write port. The other companion Slice supports the read-only port. For more information on RAM mode

in LatticeXP devices, please see details of additional technical documentation at the end of this data sheet.

Table 2-3. Number of Slices Required for Implementing Distributed RAM

SPR16x2

DPR16x2

Number of Slices

1

2

Note: SPR = Single Port RAM, DPR = Dual Port RAM

Figure 2-4. Distributed Memory Primitives

SPR16x2

DPR16x2

AD0

AD1

AD2

AD3

RAD0

RAD1

RAD2

RAD3

WAD0

WAD1

WAD2

WAD3

DO0

DO1

DI0

DI1

WRE

DI0

DI1

WCK

WRE

RDO0

RDO1

WDO0

WDO1

CK

ROM16x1

AD0

AD1

AD2

AD3

DO0

ROM Mode:The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is

accomplished through the programming interface during conﬁguration.

PFU Modes of Operation

Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the

functionality possible at the PFU level.

2-5

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Table 2-4. PFU Modes of Operation

Logic

Ripple

RAM¹

ROM

LUT 4x8 or

MUX 2x1 x 8

SPR16x2 x 4

DPR16x2 x 2

2-bit Add x 4

ROM16x1 x 8

LUT 5x4 or

MUX 4x1 x 4

SPR16x4 x 2

DPR16x4 x 1

2-bit Sub x 4

2-bit Counter x 4

2-bit Comp x 4

ROM16x2 x 4

ROM16x4 x 2

ROM16x8 x 1

LUT 6x 2 or

MUX 8x1 x 2

SPR16x8 x 1

LUT 7x1 or

MUX 16x1 x 1

1. These modes are not available in PFF blocks

Routing

There are many resources provided in the LatticeXP devices to route signals individually or as buses with related

control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-

ments.

The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).

The x1 and x2 connections provide fast and efﬁcient connections in horizontal, vertical and diagonal directions.The

x2 and x6 resources are buffered allowing both short and long connections routing between PFUs.

The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the

place and route tool is completely automatic, although an interactive routing editor is available to optimize the

design.

Clock Distribution Network

The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed

through the chip via a clock distribution system.

Primary Clock Sources

LatticeXP devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing. Lat-

ticeXP devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There are four

dedicated clock inputs, one on each side of the device. Figure 2-5 shows the 20 primary clock sources.

2-6

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-5. Primary Clock Sources

From Routing

Clock Input

From Routing

PLL Input

PLL

20 Primary Clock Sources

To Quadrant Clock Selection

Clock Input

PLL

PLL Input

From Routing

Clock Input

From Routing

Note: Smaller devices have two PLLs.

Secondary Clock Sources

LatticeXP devices have four secondary clock resources per quadrant. The secondary clock branches are tapped at

every PFU. These secondary clock networks can also be used for controls and high fanout data. These secondary

clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-6.

2-7

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-6. Secondary Clock Sources

Clock

Input

From

Routing

From

Routing

From

Routing

From

Routing

From Routing

20 Secondary Clock Sources

To Quadrant Clock Selection

Clock Input

From Routing

From

Routing

From

Routing

From

Routing

From

Routing

Clock

Input

Clock Routing

The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-

work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this

clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-

8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-

9.

Figure 2-7. Per Quadrant Primary Clock Selection

1

20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing

DCS²

4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant

1. Smaller devices have fewer PLL related lines.

2. Dynamic clock select.

2-8

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-8. Per Quadrant Secondary Clock Selection

20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals

4 Secondary Clocks per Quadrant

Figure 2-9. Slice Clock Selection

Primary Clock

Secondary Clock

Routing

Clock to Each Slice

GND

sysCLOCK Phase Locked Loops (PLLs)

The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-

nals to the feedback divider: from CLKOP (PLL internal), from clock net (CLKOP or CLKOS) or from a user clock

(PIN or logic).There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-10

shows the sysCLOCK PLL diagram.

The setup and hold times of the device can be improved by programming a delay in the feedback or input path of

the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-

grammed during conﬁguration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after

adjustment and not relock until the t

parameter has been satisﬁed. Additionally, the phase and duty cycle block

LOCK

allows the user to adjust the phase and duty cycle of the CLKOS output.

The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated

with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider

is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal.The post

scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-

quency range. The secondary divider is used to derive lower frequency outputs.

2-9

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-10. PLL Diagram

Dynamic Delay Adjustment

LOCK

RST

Input Clock

Divider

(CLKI)

Post Scalar

Divider

(CLKOP)

Phase/Duty

Select

Voltage

ConVtCroOlled

Oscillator

CLKOS

Delay

Adjust

CLKI

(from routing or

external pin)

CLKOP

Secondary

Clock

CLKOK

Divider

Feedback

Divider

(CLKFB)

CLKFB

from CLKOP

(PLL internal),

from clock net

(CLKOP) or

from a user

(CLKOK)

clock (PIN or logic)

Figure 2-11 shows the available macros for the PLL. Table 2-11 provides signal description of the PLL Block.

Figure 2-11. PLL Primitive

CLKOP

RST

CLKI

CLKOP

LOCK

CLKOS

CLKOK

LOCK

EPLLB

CLKFB

DDA MODE

DDAIZR

EHXPLLB

DDAOZR

DDAILAG

DDAOLAG

DDAODEL[2:0]

DDAIDEL[2:0]

Table 2-5. PLL Signal Descriptions

Signal

I/O

Description

CLKI

I

Clock input from external pin or routing

PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock

(PIN or logic)

CLKFB

RST

I

“1” to reset input clock divider

CLKOS

O

I

PLL output clock to clock tree (phase shifted/duty cycle changed)

PLL output clock to clock tree (No phase shift)

PLL output to clock tree through secondary clock divider

“1” indicates PLL LOCK to CLKI

CLKOP

CLKOK

LOCK

DDAMODE

DDAIZR

Dynamic Delay Enable. “1” Pin control (dynamic), “0”: Fuse Control (static)

Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on

Dynamic Delay Lag/Lead. “1”: Lag, “0”: Lead

Dynamic Delay Input

I

DDAILAG

DDAIDEL[2:0]

DDAOZR

DDAOLAG

DDAODEL[2:0]

I

O

Dynamic Delay Zero Output

Dynamic Delay Lag/Lead Output

Dynamic Delay Output

2-10

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

For more information on the PLL, please see details of additional technical documentation at the end of this data

sheet.

Dynamic Clock Select (DCS)

The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and

outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is

toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-12 illustrates

the DCS Block Macro.

Figure 2-12. DCS Block Primitive

CLK0

DCS

CLK1

SEL

DCSOUT

Figure 2-13 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to

other modes. For more information on the DCS, please see details of additional technical documentation at the end

of this data sheet.

Figure 2-13. DCS Waveforms

CLK0

CLK1

SEL

DCSOUT

sysMEM Memory

The LatticeXP family of devices contain a number of sysMEM Embedded Block RAM (EBR).The EBR consists of a

9-Kbit RAM, with dedicated input and output registers.

sysMEM Memory Block

The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in

a variety of depths and widths as shown in Table 2-6.

2-11

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Table 2-6. sysMEM Block Conﬁgurations

Memory Mode

Conﬁgurations

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

Single Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

True Dual Port

Pseudo Dual Port

8,192 x 1

4,096 x 2

2,048 x 4

1,024 x 9

512 x 18

256 x 36

Bus Size Matching

All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB

word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for

each port varies, this mapping scheme applies to each port.

RAM Initialization and ROM Operation

If desired, the contents of the RAM can be pre-loaded during device conﬁguration. By preloading the RAM block

during the chip conﬁguration cycle and disabling the write controls, the sysMEM block can also be utilized as a

ROM.

Memory Cascading

Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools

cascade memory transparently, based on speciﬁc design inputs.

Single, Dual and Pseudo-Dual Port Modes

Figure 2-14 shows the four basic memory conﬁgurations and their input/output names. In all the sysMEM RAM

modes the input data and address for the ports are registered at the input of the memory array. The output data of

the memory is optionally registered at the output.

2-12

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-14. sysMEM Memory Primitives

ADA[12:0]

DIA[17:0]

CLKA

CEA

RSTA

WEA

CSA[2:0]

DOA[17:0]

ADB[12:0]

DIB[17:0]

CEB

CLKB

RSTB

WEB

CSB[2:0]

DOB[17:0]

AD[12:0]

DI[35:0]

CLK

DO[35:0]

CE

EBR

RST

WE

CS[2:0]

True Dual Port RAM

Single Port RAM

ADW[12:0]

DI[35:0]

CLKW

CEW

ADR[12:0]

DO[35:0]

AD[12:0]

CLK

DO[35:0]

CE

EBR

WE

RST

CS[2:0]

CER

RST

CS[2:0]

CLKR

ROM

Pseudo-Dual Port RAM

The EBR memory supports three forms of write behavior for single port or dual port operation:

1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current

address) does not appear on the output. This mode is supported for all data widths.

2. Write Through - a copy of the input data appears at the output of the same port during a write cycle. This

mode is supported for all data widths.

3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.

This mode is supported for x9, x18 and x36 data widths.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respec-

tively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both

ports are as shown in Figure 2-15.

2-13

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-15. Memory Core Reset

SET

D

Q

Memory Core

Port A[17:0]

Port B[17:0]

L_CLR

Output Data

Latches

SET

D

Q

L_CLR

RSTA

RSTB

GSRN

Programmable Disable

For further information on sysMEM EBR block, see the details of additional technical documentation at the end of

this data sheet.

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the

reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-16. The GSR input to the

EBR is always asynchronous.

Figure 2-16. EBR Asynchronous Reset (Including GSR) Timing Diagram

Reset

Clock

Enable

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f

(EBR clock). The reset

MAX

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

If an EBR is pre-loaded during conﬁguration, the GSR input must be disabled or the release of the GSR during

device Wake Up must occur before the release of the device I/Os becoming active.

These instructions apply to all EBR RAM and ROM implementations.

Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled.

Programmable I/O Cells (PICs)

Each PIC contains two PIOs connected to their respective sysIO Buffers which are then connected to the PADs as

shown in Figure 2-17. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysIO

buffer, and receives input from the buffer.

2-14

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-17. PIC Diagram

PIO A

TD

D0

TD

OPOS1

ONEG1

D1

DDRCLK

IOLT0

DO

Tristate

Register Block

(2 Flip Flops)

PADA

"T"

D0

D1

OPOS0

ONEG0

DDRCLK

IOLD0

Output

Register Block

(2 Flip Flops)

sysIO

Buffer

INCK

INDD

INCK

INDD

INFF

IPOS0

IPOS1

IPOS0

IPOS1

DI

Control

Muxes

Input

Register Block

(5 Flip Flops)

CLKO

CEO

LSR

CLK

CE

LSR

GSR

CLKI

CEI

GSRN

DQS

DDRCLKPOL

PADB “C”

PIO B

In the LatticeXP family, seven PIOs or four (3.5) PICs are grouped together to provide two LVDS differential pairs,

one PIC pair and one single I/O, as shown in Figure 2-18.

Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”). The PAD Labels “T” and

“C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device can be conﬁgured as

LVDS transmit/receive pairs.

One of every 14 PIOs (a group of 8 PICs) contains a delay element to facilitate the generation of DQS signals as

shown in Figure 2-19. The DQS signal feeds the DQS bus which spans the set of 13 PIOs (8 PICs). The DQS sig-

nal from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is

designed for memories that support one DQS strobe per eight bits of data.

The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-

tional detail is provided in the Signal Descriptions table in this data sheet.

2-15

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-18. Group of Seven PIOs

PADA “T”

LVDS Pair

PADB “C”

PIO A

PIO B

PIO A

PIO B

PIO A

PADA “T”

One PIO Pair

PADB “C”

Four PICs

PADA “T”

LVDS Pair

PIO B

PIO A

PADB “C”

PADA “T”

Figure 2-19. DQS Routing

PADA “T”

LVDS Pair

PADB “C”

PIO A

PIO B

PADA “T”

PADB “C”

PIO A

PIO B

PADA “T”

LVDS Pair

PADB “C”

PIO A

PIO B

PADA “T”

PIO A

PADB “C”

PIO B

PIO A

PIO B

sysIO

Buffer

Assigned DQS Pin

PADA “T”

LVDS Pair

DQS

Delay

PADB “C”

PADA “T”

PADB “C”

PIO A

PIO B

PADA “T”

LVDS Pair

PADB “C”

PIO A

PIO B

PIO

The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic

block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along

with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-

nals are also included in these blocks.

Input Register Block

The input register block contains delay elements and registers that can be used to condition signals before they are

passed to the device core. Figure 2-20 shows the diagram of the input register block.

Input signals are fed from the sysIO buffer to the input register block (as signal DI). If desired the input signal can

bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and

2-16

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal ﬁrst

passes through an optional delay block. This delay, if selected, ensures no positive input-register hold-time require-

ment when using a global clock.

The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the

registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used

to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.

These two data streams are synchronized with the system clock before entering the core. Further discussion on

this topic is in the DDR Memory section of this data sheet.

Figure 2-21 shows the input register waveforms for DDR operation and Figure 2-22 shows the design tool primi-

tives. The SDR/SYNC registers have reset and clock enable available.

The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-

quate timing when data is transferred from the DQS to the system clock domain. For further discussion of this topic,

see the DDR memory section of this data sheet.

Figure 2-20. Input Register Diagram

DI

(From sysIO

Buffer)

INCK

INDD

Delay Block

Fixed Delay

SDR & Sync

Registers

DDR Registers

D0

D2

To Routing

Q

D

Q

D

IPOS0

IPOS1

D-Type

/LATCH

D-Type

D1

Q

D

Q

D

D-Type

/LATCH

D-Type

DQS Delayed

(From DQS

Bus)

CLK0

(From Routing)

DDRCLKPOL

(From DDR Polarity

Control Bus)

2-17

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-21. Input Register DDR Waveforms

DI

F

A

B

C

D

E

(In DDR Mode)

DQS

Delayed

B

A

D

C

D0

D2

Figure 2-22. INDDRXB Primitive

D

ECLK

QA

QB

LSR

SCLK

IDDRXB

CE

DDRCLKPOL

Output Register Block

The output register block provides the ability to register signals from the core of the device before they are passed

to the sysIO buffers. The block contains a register for SDR operation that is combined with an additional latch for

DDR operation. Figure 2-23 shows the diagram of the Output Register Block.

In SDR mode, ONEG0 feeds one of the ﬂip-ﬂops that then feeds the output. The ﬂip-ﬂop can be conﬁgured as a D-

type or as a latch. In DDR mode, ONEG0 is fed into one register on the positive edge of the clock and OPOS0 is

latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).

Figure 2-24 shows the design tool DDR primitives. The SDR output register has reset and clock enable available.

The additional register for DDR operation does not have reset or clock enable available.

2-18

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-23. Output Register Block

OUTDDN

Q

D

D-Type

/LATCH

ONEG0

0

DO

0

1

From

Routing

To sysIO

Buffer

OPOS0

Q

D

LATCH

LE*

CLK1

Programmed

Control

*Latch is transparent when input is low.

Figure 2-24. ODDRXB Primitive

DA

DB

ODDRXB

Q

CLK

LSR

Tristate Register Block

The tristate register block provides the ability to register tri-state control signals from the core of the device before

they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for

DDR operation. Figure 2-25 shows the diagram of the Tristate Register Block.

In SDR mode, ONEG1 feeds one of the ﬂip-ﬂops that then feeds the output. The ﬂip-ﬂop can be conﬁgured a D-

type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is

latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).

2-19

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-25. Tristate Register Block

TD

OUTDDN

Q

D

D-Type

/LATCH

ONEG1

0

TO

0

1

From

1

Routing

To sysIO

Buffer

OPOS1

Q

D

LATCH

LE*

CLK1

Programmed

Control

*Latch is transparent when input is low.

Control Logic Block

The control logic block allows the selection and modiﬁcation of control signals for use in the PIO block. A clock is

selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from

the programmable DQS pin. The clock can optionally be inverted.

The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate

signal is passed through this block.

DDR Memory Support

Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input

(for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the LatticeXP

devices provide this capability. In addition to these registers, the LatticeXP devices contain two elements to simplify

the design of input structures for read operations: the DQS delay block and polarity control logic.

DLL Calibrated DQS Delay Block

Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at

the input register. For most interfaces a PLL is used for this adjustment, however in DDR memories the clock

(referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the

required clock alignment for DDR memory interfaces.

The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS rout-

ing resource.The DQS signal also feeds the polarity control logic which controls the polarity of the clock to the sync

registers in the input register blocks. Figures 2-26 and 2-27 show how the polarity control logic are routed to the

PIOs.

The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration

(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of

the device as shown in Figure 2-27. The DLL loop is compensated for temperature, voltage and process variations

by the system clock and feedback loop.

2-20

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-26. DQS Local Bus

Delay

Control

Bus

PIO

DDR

Datain

PAD

sysIO

Buffer

Input

Register Block

( 5 Flip Flops)

Polarity

Control

Bus

To Sync.

Reg.

DI

GSR

CLKI

CEI

DQS

Bus

To DDR

Reg.

DQS

PIO

DQS

Strobe

PAD

sysIO

Buffer

Polarity Control

Logic

DI

DQS

DQSDEL

Calibration Bus

from DLL

Figure 2-27. DLL Calibration Bus and DQS/DQS Transition Distribution

Delay Control Bus

Polarity Control Signal Bus

DQS Signal Bus

DLL

2-21

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Polarity Control Logic

In a typical DDR Memory interface design, the phase relation between the incoming delayed DQS strobe and the

internal system Clock (during the READ cycle) is unknown.

The LatticeXP family contains dedicated circuits to transfer data between these domains. To prevent setup and

hold violations at the domain transfer between DQS (delayed) and the system Clock a clock polarity selector is

used. This changes the edge on which the data is registered in the synchronizing registers in the input register

block. This requires evaluation at the start of the each READ cycle for the correct clock polarity.

Prior to the READ operation in DDR memories DQS is in tristate (pulled by termination). The DDR memory device

drives DQS low at the start of the preamble state. A dedicated circuit detects this transition. This signal is used to

control the polarity of the clock to the synchronizing registers.

sysIO Buffer

Each I/O is associated with a ﬂexible buffer referred to as a sysIO buffer. These buffers are arranged around the

periphery of the device in eight groups referred to as Banks. The sysIO buffers allow users to implement the wide

variety of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.

sysIO Buffer Banks

LatticeXP devices have eight sysIO buffer banks; each is capable of supporting multiple I/O standards. Each sysIO

bank has its own I/O supply voltage (V

), and two voltage references V

and V

resources allowing each

CCIO

REF1

REF2

bank to be completely independent from each other. Figure 2-28 shows the eight banks and their associated sup-

plies.

In the LatticeXP devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI and PCI-X) are

powered using V

independent of V

. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as a ﬁxed threshold input

CCIO

In addition to the bank V

supplies, the LatticeXP devices have a V core logic power sup-

CCIO.

CCIO

CC

ply, and a V

supply that power all differential and referenced buffers.

CCAUX

Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-

enced input buffers. In the LatticeXP devices, a dedicated pin in a bank can be conﬁgured to be a reference voltage

supply pin. Each I/O is individually conﬁgurable based on the bank’s supply and reference voltages.

2-22

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-28. LatticeXP Banks

1

N

1

N

1

Bank 0

Bank 1

V_CCIO7

V_CCIO2

V_REF1(2)

V_REF2(2)

GND

V_REF1(7)

V_REF2(7)

GND

M

1

M

1

V_CCIO6

V_CCIO3

V_REF1(6)

V_REF2(6)

V_REF1(3)

V_REF2(3)

GND

M

N

M

Bank 5

Bank 4

1

N

1

Note: N and M are the maximum number of I/Os per bank.

LatticeXP devices contain two types of sysIO buffer pairs.

1. Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)

The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and

two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be

conﬁgured as a differential input.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

Only the I/Os on the top and bottom banks have PCI clamps. Note that the PCI clamp is enabled after V

CC,

V

and V

are at valid operating levels and the device has been conﬁgured.

CCAUX

CCIO

2. Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)

The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two

sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-

enced input buffer can also be conﬁgured as a differential input. In these banks the two pads in the pair are

described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,

and the comp (complementary) pad is associated with the negative side of the differential I/O.

Select I/Os in the left and right banks have LVDS differential output drivers. Refer to the Logic Signal Connec-

tions tables for more information.

2-23

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Typical I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when V and V

have reached satisfactory levels.

CC

CCAUX

After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure

that all other V banks are active with valid input logic levels to properly control the output logic states of all the

CCIO

I/O banks that are critical to the application. The default conﬁguration of the I/O pins in a blank device is tri-state

with a weak pull-up to VCCIO. The I/O pins will not take on the user conﬁguration until VCC, VCCAUX and VCCIO

have reached satisfactory levels at which time the I/Os will take on the user-conﬁgured settings.

The V and V

supply the power to the FPGA core fabric, whereas the V

supplies power to the I/O buff-

CC

CCAUX

CCIO

ers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended

that the I/O buffers be powered-up prior to the FPGA core fabric. V supplies should be powered up before or

CCIO

together with the V and V

supplies.

CC

CCAUX

Supported Standards

The LatticeXP sysIO buffer supports both single-ended and differential standards. Single-ended standards can be

further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS 1.2, 1.5,

1.8, 2.5 and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually conﬁgurable options for

drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. Other sin-

gle-ended standards supported include SSTL and HSTL. Differential standards supported include LVDS, BLVDS,

LVPECL, differential SSTL and differential HSTL. Tables 2-7 and 2-8 show the I/O standards (together with their

supply and reference voltages) supported by the LatticeXP devices. For further information on utilizing the sysIO

buffer to support a variety of standards please see the details of additional technical documentation at the end of

this data sheet.

Table 2-7. Supported Input Standards

Input Standard

Single Ended Interfaces

LVTTL

LVCMOS33²

LVCMOS25²

V

(Nom.)

V

¹(Nom.)

CCIO

REF

—

LVCMOS18

1.8

1.5

—

LVCMOS15

LVCMOS12²

PCI

3.3

—

HSTL18 Class I, II

HSTL18 Class III

HSTL15 Class I

0.9

1.08

0.75

0.9

—

HSTL15 Class III

SSTL3 Class I, II

SSTL2 Class I, II

SSTL18 Class I

—

1.5

—

1.25

0.9

—

Differential Interfaces

Differential SSTL18 Class I

Differential SSTL2 Class I, II

Differential SSTL3 Class I, II

Differential HSTL15 Class I, III

Differential HSTL18 Class I, II, III

LVDS, LVPECL

—

BLVDS

1. When not speciﬁed V

can be set anywhere in the valid operating range.

CCIO

2. JTAG inputs do not have a ﬁxed threshold option and always follow V

CCJ.

2-24

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Table 2-8. Supported Output Standards

Output Standard

Single-ended Interfaces

LVTTL

Drive

V

(Nom.)

CCIO

4mA, 8mA, 12mA, 16mA, 20mA

3.3

LVCMOS33

4mA, 8mA, 12mA 16mA, 20mA

3.3

2.5

1.8

1.5

1.2

—

LVCMOS25

4mA, 8mA, 12mA 16mA, 20mA

LVCMOS18

4mA, 8mA, 12mA 16mA

LVCMOS15

4mA, 8mA

LVCMOS12

2mA, 6mA

LVCMOS33, Open Drain

LVCMOS25, Open Drain

LVCMOS18, Open Drain

LVCMOS15, Open Drain

LVCMOS12, Open Drain

PCI33

4mA, 8mA, 12mA 16mA, 20mA

—

4mA, 8mA, 12mA 16mA

—

4mA, 8mA

2mA. 6mA

N/A

—

3.3

1.8

1.5

3.3

2.5

1.8

HSTL18 Class I, II, III

HSTL15 Class I, III

SSTL3 Class I, II

N/A

SSTL2 Class I, II

N/A

SSTL18 Class I

N/A

Differential Interfaces

Differential SSTL3, Class I, II

Differential SSTL2, Class I, II

Differential SSTL18, Class I

Differential HSTL18, Class I, II, III

Differential HSTL15, Class I, III

LVDS

N/A

3.3

2.5

1.8

1.5

2.5

3.3

BLVDS¹

LVPECL¹

1. Emulated with external resistors.

Hot Socketing

The LatticeXP devices have been carefully designed to ensure predictable behavior during power-up and power-

down. Power supplies can be sequenced in any order. During power up and power-down sequences, the I/Os

remain in tristate until the power supply voltage is high enough to ensure reliable operation. In addition, leakage

into I/O pins is controlled to within speciﬁed limits, which allows easy integration with the rest of the system.

These capabilities make the LatticeXP ideal for many multiple power supply and hot-swap applications.

Sleep Mode

The LatticeXP “C” devices (V = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced by up

CC

to three orders of magnitude during periods of system inactivity. Entry and exit to Sleep Mode is controlled by the

SLEEPN pin.

During Sleep Mode, the FPGA logic is non-operational, registers and EBR contents are not maintained and I/Os

are tri-stated. Do not enter Sleep Mode during device programming or conﬁguration operation. In Sleep Mode,

power supplies can be maintained in their normal operating range, eliminating the need for external switching of

power supplies. Table 2-9 compares the characteristics of Normal, Off and Sleep Modes.

2-25

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Table 2-9. Characteristics of Normal, Off and Sleep Modes

Characteristic

SLEEPN Pin

Normal

High

Off

—

Sleep

Low

Static Icc

Typical <100mA

<10µA

0

Typical <100uA

<10µA

I/O Leakage

<1mA

Off

Power Supplies VCC/VCCIO/VCCAUX

Logic Operation

Normal Range

User Deﬁned

Operational

Maintained

Normal Range

Non Operational

Tri-state

Non operational

Tri-state

I/O Operation

JTAG and Programming circuitry

EBR Contents and Registers

Non-operational

Non-maintained

Non-operational

Non-maintained

SLEEPN Pin Characteristics

The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the

device.This pin also has a weak pull-up typically in the order of 10µA along with a Schmidt trigger and glitch ﬁlter to

prevent false triggering. An external pull-up to V is recommended when Sleep Mode is not used to ensure the

CC

device stays in normal operation mode. Typically the device enters Sleep Mode several hundred ns after SLEEPN

is held at a valid low and restarts normal operation as speciﬁed in the Sleep Mode Timing table. The AC and DC

speciﬁcations portion of this data sheet show a detailed timing diagram.

Conﬁguration and Testing

The following section describes the conﬁguration and testing features of the LatticeXP family of devices.

IEEE 1149.1-Compliant Boundary Scan Testability

All LatticeXP devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access

port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan

path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in

and loaded directly onto test nodes, or test data to be captured and shifted out for veriﬁcation. The test access port

consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage V

operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.

and can

CCJ

For more details on boundary scan test, please see information regarding additional technical documentation at

the end of this data sheet.

Device Conﬁguration

All LatticeXP devices contain two possible ports that can be used for device conﬁguration and programming. The

test access port (TAP), which supports serial conﬁguration, and the sysCONFIG port that supports both byte-wide

and serial conﬁguration.

The non-volatile memory in the LatticeXP can be conﬁgured in three different modes:

• In sysCONFIG mode via the sysCONFIG port. Note this can also be done in background mode.

• In 1532 mode via the 1149.1 port.

• In background mode via the 1149.1 port. This allows the device to be operated while reprogramming takes

place.

The SRAM conﬁguration memory can be conﬁgured in three different ways:

• At power-up via the on-chip non-volatile memory.

• In 1532 mode via the 1149.1 port SRAM direct conﬁguration.

• In sysCONFIG mode via the sysCONFIG port SRAM direct conﬁguration.

2-26

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 2-29 provides a pictorial representation of the different programming ports and modes available in the Lat-

ticeXP devices.

On power-up, the FPGA SRAM is ready to be conﬁgured with the sysCONFIG port active. The IEEE 1149.1 serial

mode can be activated any time after power-up by sending the appropriate command through the TAP port.

Leave Alone I/O

When using 1532 mode for non-volatile memory programming, users may specify I/Os as high, low, tristated or

held at current value. This provides excellent ﬂexibility for implementing systems where reprogramming occurs on-

the-ﬂy.

TransFR (Transparent Field Reconﬁguration)

TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the ﬁeld without interrupting

system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Inter-

ruption During Conﬁguration Using TransFR Technology, for details.

Security

The LatticeXP devices contain security bits that, when set, prevent the readback of the SRAM conﬁguration and

non-volatile memory spaces. Once set, the only way to clear security bits is to erase the memory space.

For more information on device conﬁguration, please see details of additional technical documentation at the end

of this data sheet.

Figure 2-29. ispXP Block Diagram

ISP 1149.1 TAP Port

sysCONFIG Peripherial Port

Port

sysCONFIG

BACKGND

1532

Mode

Configure in milliseconds

Program in seconds

Power-up

Refresh

SRAM

Memory Space

Download in microseconds

Memory Space

Internal Logic Analyzer Capability (ispTRACY)

All LatticeXP devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabil-

ities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace mem-

ory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile

time.

For more information on ispTRACY, please see information regarding additional technical documentation at the

end of this data sheet.

Oscillator

Every LatticeXP device has an internal CMOS oscillator which is used to derive a master serial clock for conﬁgura-

tion. The oscillator and the master serial clock run continuously in the conﬁguration mode. The default value of the

2-27

Architecture

LatticeXP Family Data Sheet

Lattice Semiconductor

master serial clock is 2.5MHz. Table 2-10 lists all the available Master Serial Clock frequencies. When a different

Master Serial Clock is selected during the design process, the following sequence takes place:

1. User selects a different Master Serial Clock frequency for conﬁguration.

2. During conﬁguration the device starts with the default (2.5MHz) Master Serial Clock frequency.

3. The clock conﬁguration settings are contained in the early conﬁguration bit stream.

4. The Master Serial Clock frequency changes to the selected frequency once the clock conﬁguration bits are

received.

For further information on the use of this oscillator for conﬁguration, please see details of additional technical docu-

mentation at the end of this data sheet.

Table 2-10. Selectable Master Serial Clock (CCLK) Frequencies During Conﬁguration

CCLK (MHz)

2.5¹

13

15

20

26

30

34

41

45

51

55

60

130

—

4.3

5.4

6.9

8.1

9.2

10.0

—

1. Default

Density Shifting

The LatticeXP family has been designed to ensure that different density devices in the same package have the

same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from

lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design tar-

geted for a high-density device to a lower density device. However, the exact details of the ﬁnal resource utilization

will impact the likely success in each case.

2-28

LatticeXP Family Data Sheet

DC and Switching Characteristics

Data Sheet DS1001

November 2007

Absolute Maximum Ratings^{1, 2, 3, 4}

XPE (1.2V)

XPC (1.8V/2.5V/3.3V)

Supply Voltage V . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V

CC

Supply Voltage V

. . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V

CCP

. . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

CCAUX

. . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

CCJ

Output Supply Voltage V

. . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

CCIO

I/O Tristate Voltage Applied⁵. . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V

Dedicated Input Voltage Applied ⁵. . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 4.25V

Storage Temperature (Ambient) . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C

Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C . . . . . . . . . . . . . . . . . . . +125°C

1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the

device at these or any other conditions outside of those indicated in the operational sections of this speciﬁcation is not implied.

2. Compliance with the Lattice Thermal Management document is required.

3. All voltages referenced to GND.

4. All chip grounds are connected together to a common package GND plane.

5. Overshoot and undershoot of -2V to (V

+ 2) volts is permitted for a duration of <20ns.

IHMAX

Recommended Operating Conditions³

Symbol

Parameter

Min.

1.14

1.71

1.14

1.71

3.135

1.14

0

Max.

1.26

3.465

1.26

3.465

85

Units

V

Core Supply Voltage for 1.2V Devices

V

CC

Core Supply Voltage for 1.8V/2.5V/3.3V Devices

Supply Voltage for PLL for 1.2V Devices

Supply Voltage for PLL for 1.8V/2.5V/3.3V Devices

Auxiliary Supply Voltage

V

CCP

V

4

V

CCAUX

1, 2

I/O Driver Supply Voltage

V

CCIO

1

Supply Voltage for IEEE 1149.1 Test Access Port

Junction Temperature, Commercial Operation

Junction Temperature, Industrial Operation

Junction Temperature, Flash Programming, Commercial

Junction Temperature, Flash Programming, Industrial

V

CCJ

t

C

JCOM

JIND

-40

100

C

0

85

C

JFLASHCOM

JFLASHIND

0

85

C

1. If V

or V

is set to 3.3V, they must be connected to the same power supply as V

For the XPE devices (1.2V V ), if V

or

CCIO

CCJ

CCAUX.

CC

V

is set to 1.2V, they must be connected to the same power supply as V

.

CCJ

CC

2. See recommended voltages by I/O standard in subsequent table.

3. The system designer must ensure that the FPGA design stays within the speciﬁed junction temperature and package thermal capabilities

of the device based on the expected operating frequency, activity factor and environment conditions of the system.

4. V

ramp rate must not exceed 30mV/µs during power up when transitioning between 0V and 3.3V.

CCAUX

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

3-1

DS1001 DC and Switching_02.7

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Hot Socketing Speciﬁcations^{1, 2, 3, 4, 5, 6}

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

I

Input or I/O Leakage Current

0 ≤ V ≤ V (MAX.)

—

+/-1000

µA

DK

IN

IH

1. Insensitive to sequence of V

V

and V

. However, assumes monotonic rise/fall rates for V

V

and V

CC, CCAUX

CCIO

CC, CCAUX CCIO.

2. 0 ≤ V ≤ V (MAX) or 0 ≤ V

≤ V

(MAX).

CC

CCAUX

3. 0 ≤ V

≤ V

(MAX) for top and bottom I/O banks.

CCIO

4. 0.2 ≤ V

≤ V

(MAX) for left and right I/O banks.

CCIO

5. I is additive to I

I

or I

.

DK

PU, PW

BH

6. LVCMOS and LVTTL only.

3-2

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

DC Electrical Characteristics

Over Recommended Operating Conditions

Symbol

Parameter

Condition

- 0.2V)

CCIO

Min.

—

Typ.

—

Max.

10

Units

µA

V

0 ≤ V ≤ (V

IN

1, 2, 4

I

Input or I/O Leakage

IL, IH

(V

- 0.2V) < V ≤ 3.6V

—

40

CCIO

IN

CCIO

I

I/O Active Pull-up Current

0 ≤ V ≤ 0.7 V

-30

30

-150

150

—

PU

IN

I/O Active Pull-down Current

Bus Hold Low sustaining current

Bus Hold High sustaining current

V

(MAX) ≤ V ≤ V (MAX)

IN IH

PD

IL

= V (MAX)

30

BHLS

BHHS

BHLO

BHHO

IN

IL

= 0.7V

-30

—

CCIO

Bus Hold Low Overdrive current 0 ≤ V ≤ V (MAX)

150

-150

IN

IH

Bus Hold High Overdrive current 0 ≤ V ≤ V (MAX)

—

IN

IH

V

Bus Hold trip Points

I/O Capacitance³

0 ≤ V ≤ V (MAX)

V

(MAX)

V

(MIN)

BHT

IN

IH

IL

IH

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

CCIO

CC

C1

C2

—

8

—

pf

= 1.2V, V = 0 to V (MAX)

IO

IH

V

= 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

Dedicated Input Capacitance³

—

CCIO

CC

= 1.2V, V = 0 to V (MAX)

IO

IH

1. Input or I/O leakage current is measured with the pin conﬁgured as an input or as an I/O with the output driver tri-stated. It is not measured

with the output driver active. Bus maintenance circuits are disabled.

2. Not applicable to SLEEPN/TOE pin.

3. T 25°C, f = 1.0MHz

A

4. When V is higher than V

, a transient current typically of 30ns in duration or less with a peak current of 6mA can be expected on the

CCIO

IH

high-to-low transition.

Supply Current (Sleep Mode)^{1, 2, 3}

Symbol

Parameter

Device

LFXP3C

Typ.⁴

12

14

16

18

20

1

Max

65

Units

µA

LFXP6C

75

I

Core Power Supply

LFXP10C

LFXP15C

LFXP20C

All LFXP ‘C’ Devices

LFXP3C

85

CC

95

105

5

PLL Power Supply (per PLL)

Auxiliary Power Supply

CCP

2

90

LFXP6C

2

100

110

120

130

20

LFXP10C

LFXP15C

LFXP20C

LFXP3C

2

CCAUX

3

4

2

LFXP6C

2

22

I

Bank Power Supply⁵

VCCJ Power Supply

LFXP10C

LFXP15C

LFXP20C

All LFXP ‘C’ Devices

2

24

CCIO

3

27

4

30

1

5

CCJ

1. Assumes all inputs are conﬁgured as LVCMOS and held at the VCCIO or GND.

2. Frequency 0MHz.

3. User pattern: blank.

4. T =25°C, power supplies at nominal voltage.

A

5. Per bank.

3-3

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Supply Current (Standby)^{1, 2, 3, 4}

Over Recommended Operating Conditions

Symbol

Parameter

Device

LFXP3E

LFXP6E

LFXP10E

LFXP15E

LFXP20E

LFXP3C

LFXP6C

LFXP10C

LFXP15C

LFXP20C

Typ.⁵

15

20

35

45

55

35

40

70

80

90

Units

mA

I

Core Power Supply

CC

PLL Power Supply

(per PLL)

I

All

8

mA

CCP

LFXP3E/C

LFXP6E/C

LFXP10E/C

LFXP15E/C

LFXP20E/C

All

22

30

2

mA

Auxiliary Power Supply

CCAUX

V

= 3.3V

CCAUX

I

Bank Power Supply⁶

Power Supply

CCIO

V

All

1

CCJ

1. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.

2. Assumes all outputs are tristated, all inputs are conﬁgured as LVCMOS and held at the VCCIO or GND.

3. Frequency 0MHz.

4. User pattern: blank.

5. T =25°C, power supplies at nominal voltage.

A

6. Per bank.

3-4

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Initialization Supply Current^{1, 2, 3, 4, 5, 6}

Over Recommended Operating Conditions

Symbol

Parameter

Device

LFXP3E

Typ.⁷

40

Units

mA

LFXP6E

50

LFXP10E

LFXP15E

LFXP20E

LFXP3C

110

140

250

60

I

Core Power Supply

CC

LFXP6C

70

LFXP10C

LFXP15C

LFXP20C

LFXP3E /C

LFXP6E /C

LFXP10E /C

LFXP15E /C

LFXP20E /C

All

150

180

290

50

60

Auxiliary Power Supply

I

90

CCAUX

V

= 3.3V

CCAUX

110

130

2

V

Power Supply

CCJ

1. Until DONE signal is active.

2. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.

3. Assumes all outputs are tristated, all inputs are conﬁgured as LVCMOS and held at the V

4. Frequency 0MHz.

or GND.

CCIO

5. Typical user pattern.

6. Assume normal bypass capacitor/decoupling capacitor across the supply.

7. T =25°C, power supplies at nominal voltage.

A

3-5

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Programming and Erase Flash Supply Current^{1, 2, 3, 4, 5}

Symbol

Parameter

Device

LFXP3E

Typ^.6

Units

mA

30

LFXP6E

40

LFXP10E

LFXP15E

LFXP20E

LFXP3C

50

60

70

I

Core Power Supply

CC

50

LFXP6C

60

LFXP10C

LFXP15C

LFXP20C

LFXP3E /C

LFXP6E /C

LFXP10E /C

LFXP15E /C

LFXP20E /C

All

90

100

110

50

60

Auxiliary Power Supply

I

90

CCAUX

V

= 3.3V

CCAUX

110

130

2

V

Power Supply⁷

CCJ

1. For further information on supply current, please see details of additional technical documentation at the end of this data sheet.

2. Assumes all outputs are tristated, all inputs are conﬁgured as LVCMOS and held at the V

3. Blank user pattern; typical Flash pattern.

or GND.

CCIO

4. Bypass or decoupling capacitor across the supply.

5. JTAG programming is at 1MHz.

6. T =25°C, power supplies at nominal voltage.

A

7. When programming via JTAG.

3-6

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

sysIO Recommended Operating Conditions

V

(V)

REF

CCIO

Standard

LVCMOS 3.3

Min.

3.135

2.375

1.71

Typ.

3.3

2.5

1.8

1.5

1.2

3.3

1.8

2.5

3.3

1.5

1.8

2.5

3.3

2.5

Max.

3.465

2.625

1.89

Min.

—

Typ.

—

Max.

—

LVCMOS 2.5

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

LVTTL

—

1.425

1.14

1.575

1.26

—

3.135

1.71

3.465

1.89

—

PCI33

—

SSTL18 Class I

SSTL2 Class I, II

SSTL3 Class I, II

HSTL15 Class I

HSTL15 Class III

HSTL 18 Class I, II

HSTL 18 Class III

LVDS

0.833

1.15

1.3

0.68

—

0.9

1.25

1.5

0.75

0.9

1.08

—

0.969

1.35

1.7

0.9

—

2.375

3.135

1.425

1.71

2.625

3.465

1.575

1.89

—

1.71

1.89

—

2.375

3.135

2.375

2.625

3.465

2.625

—

LVPECL¹

BLVDS¹

—

1. Inputs on chip. Outputs are implemented with the addition of external resistors.

3-7

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

sysIO Single-Ended DC Electrical Characteristics

V

IH

IL

Input/Output

Standard

V

Max.

V

Min.

I

OH

(mA)

OL

OH

OL

Min. (V) Max. (V)

Min. (V)

Max. (V)

(V)

(mA)

20, 16, 12,

8, 4

-20, -16, -12,

-8, -4

0.4

0.2

0.4

0.2

0.4

V

- 0.4

- 0.2

- 0.4

- 0.2

- 0.4

- 0.2

CCIO

LVCMOS 3.3

LVTTL

-0.3

0.8

0.7

2.0

1.7

3.6

0.1

-0.1

20, 16, 12,

8, 4

-20, -16, -12,

-8, -4

3.6

0.1

-0.1

20, 16, 12,

8, 4

-20, -16, -12,

-8, -4

LVCMOS 2.5

0.2

0.4

0.2

0.4

0.2

0.4

0.2

0.4

0.2

V

0.1

-0.1

-16, -12, -8, -4

-0.1

CCIO

- 0.4 16, 12, 8, 4

LVCMOS 1.8

LVCMOS 1.5

-0.3

0.35V

0.65V

3.6

CCIO

- 0.2

- 0.4

- 0.2

- 0.4

- 0.2

- 0.4

- 0.2

0.1

8, 4

0.1

6, 2

0.1

6, 2

0.1

1.5

8

-8, -4

-0.1

0.35V

0.65V

CCIO

-6, -2

-0.1

LVCMOS 1.2

(“C” Version)

0.42

0.78

-6, -2

-0.1

LVCMOS 1.2

(“E” Version)

0.35V

0.65V

CC

PCI

-0.3

0.3V

0.5V

3.6

0.1V

0.9V

-0.5

CCIO

SSTL3 class I

SSTL3 class II

SSTL2 class I

SSTL2 class II

SSTL18 class I

HSTL15 class I

HSTL15 class III

HSTL18 class I

HSTL18 class II

HSTL18 class III

V

- 0.2

V

+ 0.2

0.7

V

- 1.1

- 0.9

- 0.62

- 0.43

- 0.4

-8

REF

CCIO

V

- 0.2

- 0.18

V

+ 0.2

+ 0.18

+ 0.125

0.5

0.54

0.35

0.4

V

16

-16

V

7.6

15.2

6.7

8

-7.6

REF

CCIO

-15.2

-6.7

V

- 0.125 V

V

REF

CCIO

V

- 0.1

V

+ 0.1

0.4

V

-8

REF

0.4

V

24

-8

0.4

9.6

16

-9.6

0.4

-16

0.4

24

-8

1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as

shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or

between the last GND in a bank and the end of a bank.

3-8

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

sysIO Differential Electrical Characteristics

LVDS

Over Recommended Operating Conditions

Parameter

Symbol

Parameter Description

Input Voltage

Test Conditions

Min.

0

Typ.

—

Max.

2.4

Units

V

INP, INM

Differential Input Threshold

Input Common Mode Voltage

Input current

+/-100

—

mV

V

THD

100mV ≤ V

V

/2

1.2

—

1.8

THD

V

200mV ≤ V

350mV ≤ V

1.9

V

CM

2.0

V

THD

I

Power on or power off

R = 100 ohms

—

+/-10

1.60

—

µA

V

IN

V

Output high voltage for V or V

—

1.38

1.03

350

OH

OL

OD

OP

OM

T

Output low voltage for V or V

R = 100 ohms

0.9V

250

V

OP

OM

T

Output voltage differential

(V - V ), R = 100 ohms

450

mV

OP

OM

T

Change in V between high and

low

OD

ΔV

—

50

mV

OD

V

Output voltage offset

(V - V )/2, R = 100 ohms

1.125

—

1.25

—

1.375

50

V

OS

OP

OM

T

ΔV

Change in V between H and L

mV

OS

V

= 0V Driver outputs

OD

I

Output short circuit current

—

6

mA

OSD

shorted

3-9

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Differential HSTL and SSTL

Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-

able single-ended output classes (class I and class II) are supported in this mode.

LVDS25E

The top and bottom side of LatticeXP devices support LVDS outputs via emulated complementary LVCMOS out-

puts in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-1 is one possi-

ble solution for point-to-point signals.

Figure 3-1. LVDS25E Output Termination Example

Bourns

CAT16-LV4F12

VCCIO = 2.5V ( 5ꢀ)

RS=165 ohms

( 1ꢀ)

+

-

RD = 140 ohms

( 1ꢀ)

RD = 100 ohms

( 1ꢀ)

VCCIO = 2.5V ( 5ꢀ)

RS=165 ohms

( 1ꢀ)

Transmission line, Zo = 100 ohm differential

ON-chip

OFF-chip

OFF-chip ON-chip

Table 3-1. LVDS25E DC Conditions

Over Recommended Operating Conditions

Parameter

Description

Output high voltage

Output low voltage

Typical

1.43

1.07

0.35

1.25

100

Units

V

OH

OL

Output differential voltage

Output common mode voltage

Back impedance

V

OD

V

CM

Z

Ω

BACK

I

DC output current

3.66

mA

DC

BLVDS

The LatticeXP devices support BLVDS standard. This standard is emulated using complementary LVCMOS out-

puts in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-

drop and bi-directional multi-point differential signaling is required.The scheme shown in Figure 3-2 is one possible

solution for bi-directional multi-point differential signals.

3-10

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 3-2. BLVDS Multi-point Output Example

Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential

2.5V

80

45-90 ohms

80

2.5V

80

. . .

+

-

+

-

2.5V

Table 3-2. BLVDS DC Conditions¹

Over Recommended Operating Conditions

Typical

Symbol

Description

Output impedance

Zo = 45 Zo = 90

Units

ohms

V

Z

100

45

100

90

OUT

R

Left end termination

Right end termination

Output high voltage

TLEFT

TRIGHT

OH

45

90

V

1.375

1.125

0.25

1.25

11.2

1.48

1.02

0.46

1.25

10.2

Output low voltage

V

OL

Output differential voltage

Output common mode voltage

DC output current

V

OD

V

CM

I

mA

DC

1. For input buffer, see LVDS table.

3-11

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

LVPECL

The LatticeXP devices support differential LVPECL standard. This standard is emulated using complementary

LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is

supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-

to-point signals.

Figure 3-3. Differential LVPECL

3.3V

R_S= 100 ohms

+

= 187 ohms

= 100 ohms

R_T

R_P

3.3V

-

= 100 ohms

R_S

Transmission line, Zo = 100 ohm differential

Off-chip

Table 3-3. LVPECL DC Conditions¹

Over Recommended Operating Conditions

Symbol

Description

Output impedance

Typical

100

Units

ohms

V

Z

OUT

R

Driver parallel resistor

Driver series resistor

Receiver termination

Output high voltage

Output low voltage

187

P

S

T

100

V

2.03

1.27

0.76

1.65

85.7

12.7

OH

V

OL

Output differential voltage

Output common mode voltage

Back impedance

V

OD

V

CM

Z

ohms

mA

BACK

I

DC output current

DC

1. For input buffer, see LVDS table.

For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni-

cal documentation at the end of the data sheet.

RSDS

The LatticeXP devices support differential RSDS standard. This standard is emulated using complementary LVC-

MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-

ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS

standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in

Figure 3-4 are industry standard values for 1% resistors.

3-12

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 3-4. RSDS (Reduced Swing Differential Standard)

VCCIO = 2.5V

R_S

Zo = 100

+

VCCIO = 2.5V

R_P

R_T

-

R_S

On-chip

Off-chip

Emulated

RSDS Buffer

Table 3-4. RSDS DC Conditions

Parameter

Description

Output impedance

Typical

20

Units

ohms

V

Z

OUT

R

Driver series resistor

Driver parallel resistor

Receiver termination

Output high voltage

Output low voltage

300

S

121

P

100

T

V

1.35

1.15

0.20

1.25

101.5

3.66

OH

OL

OD

CM

BACK

V

Output differential voltage

V

Output common mode voltage

Back impedance

V

Z

ohms

mA

I

DC output current

DC

3-13

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Typical Building Block Function Performance¹

Pin-to-Pin Performance (LVCMOS25 12 mA Drive)

Function

-5 Timing

Units

Basic Functions

16-bit decoder

32-bit decoder

64-bit decoder

4:1 MUX

6.1

7.3

8.2

4.9

5.3

5.7

6.3

ns

8:1 MUX

16:1 MUX

32:1 MUX

Register to Register Performance

Function

Basic Functions

16-bit decoder

-5 Timing

Units

351

248

237

590

523

434

355

343

292

130

388

295

200

164

MHz

32-bit decoder

64-bit decoder

4:1 MUX

8:1 MUX

16:1 MUX

32:1 MUX

8-bit adder

16-bit adder

64-bit adder

16-bit counter

32-bit counter

64-bit counter

64-bit accumulator

Embedded Memory Functions

Single Port RAM 256x36 bits

True-Dual Port RAM 512x18 bits

Distributed Memory Functions

16x2 SP RAM

254

MHz

434

332

235

322

291

MHz

64x2 SP RAM

128x4 SP RAM

32x2 PDP RAM

64x4 PDP RAM

1. These timing numbers were generated using the ispLEVER design tool. Exact performance may vary with design and tool version.The tool

uses internal parameters that have been characterized but are not tested on every device.

Timing v.F0.11

3-14

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Derating Logic Timing

Logic timing provided in the following sections of this data sheet and in the ispLEVER design tools are worst case

numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process can be

much better than the values given in the tables. The ispLEVER design tool from Lattice can provide logic timing

numbers at a particular temperature and voltage.

3-15

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

LatticeXP External Switching Characteristics

Over Recommended Operating Conditions

-5

-4

-3

Parameter

Description

Device

Min. Max. Min. Max. Min. Max. Units

General I/O Pin Parameters (Using Primary Clock without PLL)¹

LFXP3

LFXP6

—

5.12

5.30

5.52

5.72

5.97

—

6.12

6.34

6.60

6.84

7.14

—

7.43

7.69

8.00

8.29

8.65

—

ns

—

t

Clock to Output - PIO Output Register

Clock to Data Setup - PIO Input Register

Clock to Data Hold - PIO Input Register

LFXP10

LFXP15

LFXP20

LFXP3

LFXP6

LFXP10

LFXP15

LFXP20

LFXP3

LFXP6

LFXP10

LFXP15

LFXP20

LFXP3

LFXP6

LFXP10

LFXP15

LFXP20

LFXP3

LFXP6

LFXP10

LFXP15

LFXP20

All

—

CO

—

-0.40

-0.33

-0.61

-0.71

-0.95

2.10

2.28

3.02

2.70

2.95

2.38

2.92

2.72

2.99

4.47

-0.70

-0.47

-0.60

-1.05

-0.80

—

-0.28

-0.32

-0.71

-0.77

-1.14

2.50

2.72

3.51

3.22

3.52

2.49

3.18

2.75

3.13

4.56

-0.80

-0.38

-0.47

-0.98

-0.58

—

-0.16

-0.30

-0.81

-0.87

-1.35

2.98

3.24

3.71

3.85

4.21

2.66

3.42

2.84

3.18

4.80

-0.92

-0.31

-0.32

-1.01

-0.31

—

SU

—

H

—

Clock to Data Setup - PIO Input Register

with Input Data Delay

—

SU_DEL

—

Clock to Data Hold - PIO Input Register with

Input Data Delay

t

f

—

H_DEL

—

Clock Frequency of I/O and PFU Register

400

360

320 MHz

MAX_IO

DDR I/O Pin Parameters²

t

f

Data Valid After DQS (DDR Read)

Data Hold After DQS (DDR Read)

Data Valid Before DQS

All

—

0.19

—

0.19

—

0.19

—

UI

DVADQ

DVEDQ

DQVBS

DQVAS

MAX_DDR

0.67

0.20

95

0.67

0.20

95

0.67

0.20

95

—

Data Valid After DQS

—

DDR Clock Frequency

166

133

100 MHz

Primary and Secondary Clocks

f

t

Frequency for Primary Clock Tree

Clock Pulse Width for Primary Clock

All

—

1.19

—

450

—

1.19

—

412

—

1.19

—

375 MHz

MAX_PRI

W_PRI

All

—

ns

ps

LFXP3/6/10/15

LFXP20

250

300

350

400

t

Primary Clock Skew within an I/O Bank

SKEW_PRI

—

1. General timing numbers based on LVCMOS 2.5, 12mA.

2. DDR timing numbers based on SSTL I/O.

Timing v.F0.11

3-16

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 3-5. DDR Timings

DQ and DQS Read Timings

DQS

DQ

t_DVADQ

t_DVEDQ

DQ and DQS Write Timings

DQS

DQ

t_DQVBS

t_DQVAS

3-17

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

LatticeXP Internal Timing Parameters¹

Over Recommended Operating Conditions

-5

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

PFU/PFF Logic Mode Timing

t

LUT4 Delay (A to D Inputs to F Output)

LUT6 Delay (A to D Inputs to OFX Output)

Set/Reset to Output of PFU

—

0.28

0.44

0.90

—

0.34

0.53

1.08

—

0.40

0.63

1.29

—

ns

LUT4_PFU

LUT6_PFU

LSR_PFU

SUM_PFU

HM_PFU

—

Clock to Mux (M0,M1) Input Setup Time

Clock to Mux (M0,M1) Input Hold Time

Clock to D Input Setup Time

0.13

-0.04

0.13

-0.03

—

0.15

-0.03

0.16

-0.02

—

0.19

-0.03

0.19

-0.02

—

SUD_PFU

HD_PFU

Clock to D Input Hold Time

—

Clock to Q Delay, D-type Register Conﬁguration

Clock to Q Delay Latch Conﬁguration

D to Q Throughput Delay when Latch is Enabled

0.40

0.53

0.55

0.48

0.64

0.66

0.58

0.76

0.79

CK2Q_PFU

LE2Q_PFU

LD2Q_PFU

—

PFU Dual Port Memory Mode Timing

t

Clock to Output

—

0.40

—

0.48

—

0.58

—

ns

CORAM_PFU

SUDATA_PFU

HDATA_PFU

Data Setup Time

-0.18

0.28

-0.46

0.71

-0.22

0.33

-0.14

0.34

-0.37

0.85

-0.17

0.40

-0.11

0.40

-0.30

1.02

-0.14

0.48

Data Hold Time

—

Address Setup Time

Address Hold Time

—

SUADDR_PFU

HADDR_PFU

SUWREN_PFU

HWREN_PFU

—

Write/Read Enable Setup Time

Write/Read Enable Hold Time

—

PIC Timing

PIO Input/Output Buffer Timing

t

Input Buffer Delay

Output Buffer Delay

—

0.62

2.12

—

0.72

2.54

—

0.85

3.05

ns

IN_PIO

OUT_PIO

IOLOGIC Input/Output Timing

t

Input Register Setup Time (Data Before Clock)

Input Register Hold Time (Data After Clock)

Output Register Clock to Output Delay

Input Register Clock Enable Setup Time

Input Register Clock Enable Hold Time

Set/Reset Setup Time

1.35

0.05

—

1.83

0.05

—

2.37

0.05

—

ns

SUI_PIO

HI_PIO

0.36

—

0.44

—

0.52

—

COO_PIO

SUCE_PIO

HCE_PIO

SULSR_PIO

HLSR_PIO

-0.09

0.13

0.19

-0.14

-0.07

0.16

0.23

-0.11

-0.06

0.19

0.28

-0.09

—

Set/Reset Hold Time

—

EBR Timing

t

Clock to Output from Address or Data

Clock to Output from EBR Output Register

Setup Data to EBR Memory

—

4.01

0.81

—

4.81

0.97

—

5.78

1.17

—

ns

CO_EBR

—

COO_EBR

-0.26

0.41

-0.26

0.41

-0.17

0.26

-0.21

0.49

-0.21

0.49

-0.13

0.31

0.23

-0.10

-0.17

0.59

-0.17

0.59

-0.11

0.37

0.28

-0.08

SUDATA_EBR

HDATA_EBR

SUADDR_EBR

HADDR_EBR

SUWREN_EBR

HWREN_EBR

SUCE_EBR

HCE_EBR

Hold Data to EBR Memory

—

Setup Address to EBR Memory

—

Hold Address to EBR Memory

—

Setup Write/Read Enable to EBR Memory

Hold Write/Read Enable to EBR Memory

—

Clock Enable Setup Time to EBR Output Register 0.19

—

Clock Enable Hold Time to EBR Output Register

-0.13

—

3-18

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

LatticeXP Internal Timing Parameters¹(Continued)

Over Recommended Operating Conditions

-5

-4

-3

Parameter

Description

Min. Max. Min. Max. Min. Max. Units

Reset To Output Delay Time from EBR Output

Register

t

—

1.61

—

1.94

—

2.32

ns

RSTO_EBR

PLL Parameters

t

Reset Recovery to Rising Clock

Reset Signal Setup Time

1.00

—

1.00

—

1.00

—

ns

RSTREC

RSTSU

1. Internal parameters are characterized but not tested on every device.

Timing v.F0.11

3-19

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Timing Diagrams

PFU Timing Diagrams

Figure 3-6. Slice Single/Dual Port Write Cycle Timing

CK

WRE

AD

AD[3:0]

D

DI[1:0]

DO[1:0]

Old Data

D

Figure 3-7. Slice Single /Dual Port Read Cycle Timing

WRE

AD

AD[3:0]

DO[1:0]

Old Data

D

3-20

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

EBR Memory Timing Diagrams

Figure 3-8. Read Mode (Normal)

CLKA

CSA

WEA

ADA

DIA

A0

A1

D1

A0

A1

A0

t_SUt_H

D0

t_ACCESS

D0

D1

DOA

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.

Figure 3-9. Read Mode with Input and Output Registers

CLKA

CSA

WEA

ADA

A1

A0

A1

D1

A0

t

H

SU

DIA

D0

D1

DOA

D0

Mem(n) data from previous read

D0

DOA

t

ACCESS

DOA

(Registered)

D1

D0

Mem(n) data from previous read

output is only updated during a read cycle

3-21

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Figure 3-10. Read Before Write (SP Read/Write on Port A, Input Registers Only)

CLKA

CSA

WEA

ADA

A0

A1

D1

A0

A1

A0

t

H

SU

D2

D3

D1

D0

DIA

t

ACCESS

old A0 Data

old A1 Data

D0

D1

DOA

D2

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.

Figure 3-11. Write Through (SP Read/Write On Port A, Input Registers Only)

CLKA

CSA

WEA

Three consecutive writes to A0

ADA

A0

A1

D1

A0

t

H

SU

D2

D3

D2

D4

D0

DIA

t

ACCESS

Data from Prev Read

or Write

D0

D1

D3

DOA

D4

Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock.

3-22

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

LatticeXP Family Timing Adders¹

Over Recommended Operating Conditions

Buffer Type

Input Adjusters

LVDS25E

Description

-5

-4

-3

Units

LVDS 2.5 Emulated

LVDS

0.5

0.4

0.5

0.6

0.4

0.5

0.6

0.5

0.2

0.0

0.1

0.2

0.5

0.4

0.5

0.6

0.4

0.5

0.6

0.5

0.2

0.0

0.1

0.2

0.5

0.4

0.5

0.6

0.4

0.5

0.6

0.5

0.2

0.0

0.1

0.2

ns

LVDS25

BLVDS25

BLVDS

LVPECL33

HSTL18_I

LVPECL

HSTL_18 class I

HSTL_18 class II

HSTL_18 class III

Differential HSTL 18 class I

Differential HSTL 18 class II

Differential HSTL 18 class III

HSTL_15 class I

HSTL_15 class III

Differential HSTL 15 class I

Differential HSTL 15 class III

SSTL_3 class I

HSTL18_II

HSTL18_III

HSTL18D_I

HSTL18D_II

HSTL18D_III

HSTL15_I

HSTL15_III

HSTL15D_I

HSTL15D_III

SSTL33_I

SSTL33_II

SSTL33D_I

SSTL33D_II

SSTL25_I

SSTL_3 class II

Differential SSTL_3 class I

Differential SSTL_3 class II

SSTL_2 class I

SSTL25_II

SSTL25D_I

SSTL25D_II

SSTL18_I

SSTL_2 class II

Differential SSTL_2 class I

Differential SSTL_2 class II

SSTL_18 class I

Differential SSTL_18 class I

LVTTL

SSTL18D_I

LVTTL33

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

PCI33

LVCMOS 3.3

LVCMOS 2.5

LVCMOS 1.8

LVCMOS 1.5

LVCMOS 1.2

PCI

Output Adjusters

LVDS25E

LVDS 2.5 Emulated

LVDS 2.5

0.3

0.1

0.2

0.1

-0.1

0.2

0.3

0.1

0.2

0.1

-0.1

0.2

0.3

0.1

0.2

0.1

-0.1

0.2

ns

LVDS25

BLVDS25

BLVDS 2.5

LVPECL33

HSTL18_I

LVPECL 3.3

HSTL_18 class I

HSTL18_II

HSTL18_III

HSTL18D_I

HSTL18D_II

HSTL18D_III

HSTL_18 class II

HSTL_18 class III

Differential HSTL 18 class I

Differential HSTL 18 class II

Differential HSTL 18 class III

3-23

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

LatticeXP Family Timing Adders¹(Continued)

Over Recommended Operating Conditions

Buffer Type

HSTL15_I

Description

HSTL_15 class I

-5

0.2

-4

0.2

-3

0.2

0.1

0.3

0.1

0.3

-0.1

0.3

-0.1

0.3

0.1

0.8

0.5

0.3

0.4

0.3

0.8

0.5

0.3

0.4

0.3

0.7

0.4

0.0

0.2

0.4

0.6

0.4

0.2

0.6

0.2

0.4

0.3

Units

ns

HSTL15_III

HSTL15D_I

HSTL15D_III

SSTL33_I

HSTL_15 class III

0.2

0.1

0.3

0.1

0.3

-0.1

0.3

-0.1

0.3

0.1

0.8

0.5

0.3

0.4

0.3

0.8

0.5

0.3

0.4

0.3

0.7

0.4

0.0

0.2

0.4

0.6

0.4

0.2

0.6

0.2

0.4

0.3

0.2

0.1

0.3

0.1

0.3

-0.1

0.3

-0.1

0.3

0.1

0.8

0.5

0.3

0.4

0.3

0.8

0.5

0.3

0.4

0.3

0.7

0.4

0.0

0.2

0.4

0.6

0.4

0.2

0.6

0.2

0.4

0.3

Differential HSTL 15 class I

Differential HSTL 15 class III

SSTL_3 class I

SSTL33_II

SSTL_3 class II

SSTL33D_I

SSTL33D_II

SSTL25_I

Differential SSTL_3 class I

Differential SSTL_3 class II

SSTL_2 class I

SSTL25_II

SSTL_2 class II

SSTL25D_I

SSTL25D_II

SSTL18_I

Differential SSTL_2 class I

Differential SSTL_2 class II

SSTL_1.8 class I

SSTL18D_I

LVTTL33_4mA

LVTTL33_8mA

LVTTL33_12mA

LVTTL33_16mA

LVTTL33_20mA

Differential SSTL_1.8 class I

LVTTL 4mA drive

LVTTL 8mA drive

LVTTL 12mA drive

LVTTL 16mA drive

LVTTL 20mA drive

LVCMOS33_2mA LVCMOS 3.3 2mA drive

LVCMOS33_4mA LVCMOS 3.3 4mA drive

LVCMOS33_8mA LVCMOS 3.3 8mA drive

LVCMOS33_12mA LVCMOS 3.3 12mA drive

LVCMOS33_16mA LVCMOS 3.3 16mA drive

LVCMOS33_20mA LVCMOS 3.3 20mA drive

LVCMOS25_2mA LVCMOS 2.5 2mA drive

LVCMOS25_4mA LVCMOS 2.5 4mA drive

LVCMOS25_8mA LVCMOS 2.5 8mA drive

LVCMOS25_12mA LVCMOS 2.5 12mA drive

LVCMOS25_16mA LVCMOS 2.5 16mA drive

LVCMOS25_20mA LVCMOS 2.5 20mA drive

LVCMOS18_2mA LVCMOS 1.8 2mA drive

LVCMOS18_4mA LVCMOS 1.8 4mA drive

LVCMOS18_8mA LVCMOS 1.8 8mA drive

LVCMOS18_12mA LVCMOS 1.8 12mA drive

LVCMOS18_16mA LVCMOS 1.8 16mA drive

LVCMOS15_2mA LVCMOS 1.5 2mA drive

LVCMOS15_4mA LVCMOS 1.5 4mA drive

LVCMOS15_8mA LVCMOS 1.5 8mA drive

LVCMOS12_2mA LVCMOS 1.2 2mA drive

LVCMOS12_6mA LVCMOS 1.2 6mA drive

PCI33

1. General timing numbers based on LVCMOS 2.5, 12mA.

Timing v.F0.11

3-24

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

sysCLOCK PLL Timing

Over Recommended Operating Conditions

Parameter

Descriptions

Conditions

Min.

25

Typ.

—

Max.

375

187.5

750

—

Units

MHz

f

Input Clock Frequency (CLKI, CLKFB)

Output Clock Frequency (CLKOP, CLKOS)

K-Divider Output Frequency (CLKOK)

PLL VCO Frequency

IN

25

—

OUT

OUT2

VCO

PFD

0.195

375

25

—

Phase Detector Input Frequency

—

AC Characteristics

t

Output Clock Duty Cycle

Default duty cycle elected³

45

—

50

—

250

—

55

0.05

+/- 125

0.02

+/- 200

—

%

UI

DT

PH

4

Output Phase Accuracy

f

≥ 100MHz

—

ps

OUT

1

t

Output Clock Period Jitter

OPJIT

< 100MHz

—

UIPP

ps

OUT

t

Input Clock to Output Clock Skew

Output Clock Pulse Width

PLL Lock-in Time

Divider ratio = integer

At 90% or 10%³

—

SK

1

ns

W

2

—

150

us

LOCK

PA

Programmable Delay Unit

Input Clock Period Jitter

External Feedback Delay

Input Clock High Time

Input Clock Low Time

RST Pulse Width

100

—

400

ps

+/- 200

10

ps

IPJIT

—

ns

FBKDLY

HI

90% to 90%

10% to 10%

0.5

10

—

ns

—

ns

LO

—

ns

RST

1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock.

2. Output clock is valid after t for PLL reset and dynamic delay adjustment.

LOCK

3. Using LVDS output buffers.

4. As compared to CLKOP output.

Timing v.F0.11

LatticeXP “C” Sleep Mode Timing

Parameter

Descriptions

SLEEPN Low to I/O Tristate

Min.

—

Typ.

Max.

Units

t

20

1.4

1.7

1.1

1.4

1.7

—

32

2.1

2.4

1.8

2.1

2.4

—

ns

ms

ns

PWRDN

LFXP3

—

LFXP6

—

t

SLEEPN High to Power Up

LFXP10

LFXP15

LFXP20

—

PWRUP

—

t

SLEEPN Pulse Width to Initiate Sleep Mode

SLEEPN Pulse Rejection

400

—

WSLEEPN

—

120

ns

WAWAKE

Sleep Mode

I/O

t_PWRUP

t_PWRDN

SLEEPN

3-25

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

LatticeXP sysCONFIG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Parameter

Description

Min.

Max.

Units

sysCONFIG Byte Data Flow

t

Byte D[0:7] Setup Time to CCLK

7

3

—

12

—

12

ns

SUCBDI

HCBDI

CODO

SUCS

HCS

Byte D[0:7] Hold Time to CCLK

Clock to Dout in Flowthrough Mode

CS[0:1] Setup Time to CCLK

CS[0:1] Hold Time to CCLK

—

7

2

Write Signal Setup Time to CCLK

Write Signal Hold Time to CCLK

CCLK to BUSY Delay Time

7

SUWD

HWD

2

—

DCB

Clock to Out for Read Data

CORD

sysCONFIG Byte Slave Clocking

t

Byte Slave Clock Minimum High Pulse

Byte Slave Clock Minimum Low Pulse

Byte Slave Clock Cycle Time

6

8

—

ns

BSCH

BSCL

15

BSCYC

sysCONFIG Serial (Bit) Data Flow

t

DI (Data In) Setup Time to CCLK

DI (Data In) Hold Time to CCLK

Clock to Dout in Flowthrough Mode

7

2

—

12

ns

SUSCDI

HSCDI

CODO

—

sysCONFIG Serial Slave Clocking

t

Serial Slave Clock Minimum High Pulse

Serial Slave Clock Minimum Low Pulse

6

—

ns

SSCH

SSCL

sysCONFIG POR, Initialization and Wake Up

t

Minimum Vcc to INIT High

Time from t to Valid Master Clock

—

50

2

ms

us

ICFG

VMC

ICFG

Program Pin Pulse Rejection

—

7

ns

PRGMRJ

2

PROGRAMN Low Time to Start Conﬁguration

INIT Low Time

25

—

1

ns

PRGM

ms

ns

DINIT

Delay Time from PROGRAMN Low to INIT Low

Delay Time from PROGRAMN Low to DONE Low

User I/O Disable from PROGRAMN Low

User I/O Enabled Time from CCLK Edge During Wake-up Sequence

Additional Wake Master Clock Signals after Done Pin High

—

37

25

—

DPPINIT

DINITD

IODISS

IOENSS

MWC

—

ns

—

ns

—

ns

120

cycles

Conﬁguration Master Clock (CCLK)

Selected Selected

Frequency¹

Value -

Value +

MHz

30%

Duty Cycle

40

60

%

1. See Table 2-10 for available CCLK frequencies.

2. The threshold level for PROGRAMN, as well as for CFG[1] and CFG[0], is determined by V , such that the threshold = V /2.

CC

Timing v.F0.11

3-26

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Flash Download Time

Symbol

Parameter

LFXP3

LFXP6

Min.

—

Typ.

1.1

1.4

0.9

1.1

1.3

Max.

1.7

2.0

1.5

1.7

1.9

Units

ms

—

ms

PROGRAMN Low-to-

t

High. Transition to Done LFXP10

—

ms

REFRESH

High.

LFXP15

—

ms

LFXP20

—

ms

JTAG Port Timing Speciﬁcations

Over Recommended Operating Conditions

Symbol

Parameter

Min.

—

40

20

10

8

Max.

Units

MHz

ns

f

t

25

—

10

—

25

MAX

TCK [BSCAN] clock pulse width

BTCP

TCK [BSCAN] clock pulse width high

ns

BTCPH

BTCPL

BTS

TCK [BSCAN] clock pulse width low

ns

TCK [BSCAN] setup time

ns

TCK [BSCAN] hold time

ns

BTH

TCK [BSCAN] rise/fall time

50

—

8

ns

BTRF

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to valid disable

TAP controller falling edge of clock to valid enable

BSCAN test capture register setup time

ns

BTCO

ns

BTCODIS

BTCOEN

BTCRS

BTCRH

BUTCO

BTUODIS

BTUPOEN

ns

BSCAN test capture register hold time

25

—

ns

BSCAN test update register, falling edge of clock to valid output

BSCAN test update register, falling edge of clock to valid disable

BSCAN test update register, falling edge of clock to valid enable

ns

Timing v.F0.11

Figure 3-12. JTAG Port Timing Waveforms

TMS

TDI

t

BTH

BTS

t

BTCP

t

BTCPL

BTCPH

TCK

t

BTCODIS

t

BTCO

BTCOEN

TDO

Valid Data

t

BTCRH

t

BTCRS

Data to be

captured

from I/O

Data Captured

t

BTUPOEN

BUTCO

BTUODIS

Data to be

driven out

to I/O

Valid Data

3-27

DC and Switching Characteristics

LatticeXP Family Data Sheet

Lattice Semiconductor

Switching Test Conditions

Figure 3-13 shows the output test load that is used for AC testing. The speciﬁc values for resistance, capacitance,

voltage, and other test conditions are shown in Figure 3-5.

Figure 3-13. Output Test Load, LVTTL and LVCMOS Standards

V_T

R1

DUT

Test Point

CL

Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

R

C

Timing Ref.

V

T

1

L

LVCMOS 3.3 = 1.5V

—

LVCMOS 2.5 = V

LVCMOS 1.8 = V

LVCMOS 1.5 = V

LVCMOS 1.2 = V

/2

CCIO

LVTTL and other LVCMOS settings (L -> H, H -> L)

0pF

∞

LVCMOS 2.5 I/O (Z -> H)

LVCMOS 2.5 I/O (Z -> L)

LVCMOS 2.5 I/O (H -> Z)

LVCMOS 2.5 I/O (L -> Z)

V

/2

V

OL

CCIO

V

OH

188

0pF

V

- 0.15

+ 0.15

V

OL

OH

V

OH

OL

Note: Output test conditions for all other interfaces are determined by the respective standards.

3-28

LatticeXP Family Data Sheet

Pinout Information

Data Sheet DS1001

November 2007

Signal Descriptions

Signal Name

I/O

Descriptions

General Purpose

[Edge] indicates the edge of the device on which the pad is located. Valid

edge designations are L (Left), B (Bottom), R (Right), T (Top).

[Row/Column Number] indicates the PFU row or the column of the device on

which the PIC exists. When Edge is T (Top) or (Bottom), only need to specify

Row Number. When Edge is L (Left) or R (Right), only need to specify Col-

umn Number.

[A/B] indicates the PIO within the PIC to which the pad is connected.

P[Edge] [Row/Column Number*]_[A/B]

I/O

Some of these user programmable pins are shared with special function

pins. These pin when not used as special purpose pins can be programmed

as I/Os for user logic.

During conﬁguration, the user-programmable I/Os are tri-stated with an inter-

nal pull-up resistor enabled. If any pin is not used (or not bonded to a pack-

age pin), it is also tri-stated with an internal pull-up resistor enabled after

conﬁguration.

Global RESET signal. (Active low). Any I/O pin can be conﬁgured to be

GSRN.

GSRN

I

NC

—

No connect.

GND

GND - Ground. Dedicated Pins.

VCC - The power supply pins for core logic. Dedicated Pins.

V

CC

V

- The Auxiliary power supply pin. It powers all the differential and ref-

CCAUX

V

—

CCAUX

erenced input buffers. Dedicated Pins.

V

—

Voltage supply pins for ULM0PLL (and LLM1PLL¹).

Voltage supply pins for URM0PLL (and LRM1PLL¹).

Ground pins for ULM0PLL (and LLM1PLL¹).

Ground pins for URM0PLL (and LRM1PLL¹).

CCP0

CCP1

GNDP0

GNDP1

V

- The power supply pins for I/O bank x. Dedicated Pins.

CCIOx

CCIO

Reference supply pins for I/O bank x. Pre-determined pins in each bank are

assigned as V inputs. When not used, they may be used as I/O pins.

V

—

REF1(x), REF2(x)

REF

PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)

Reference clock (PLL) input Pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A, B, C...at each side.

[LOC][num]_PLL[T, C]_IN_A

[LOC][num]_PLL[T, C]_FB_A

PCLK[T, C]_[n:0]_[3:0]

[LOC]DQS[num]

—

Optional feedback (PLL) input Pads: ULM, LLM, URM, LRM, num = row from

center, T = true and C = complement, index A, B, C...at each side.

Primary Clock Pads, T = true and C = complement, n per side, indexed by

bank and 0,1, 2, 3 within bank.

DQS input Pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = Ball

function number. Any pad can be conﬁgured to be DQS output.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

4-1

DS1001 Pinouts_02.5

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Signal Descriptions (Cont.)

Signal Name

I/O

Descriptions

Test and Programming (Dedicated pins. Pull-up is enabled on input pins during conﬁguration.)

TMS

TCK

I

Test Mode Select input, used to control the 1149.1 state machine.

Test Clock input pin, used to clock the 1149.1 state machine.

Test Data in pin, used to load data into device using 1149.1 state machine.

After power-up, this TAP port can be activated for conﬁguration by sending

appropriate command. (Note: once a conﬁguration port is selected it is

locked. Another conﬁguration port cannot be selected until the power-up

sequence).

TDI

I

TDO

O

Output pin -Test Data out pin used to shift data out of device using 1149.1.

V

—

V

- The power supply pin for JTAG Test Access Port.

CCJ

Conﬁguration Pads (used during sysCONFIG)

Mode pins used to specify conﬁguration modes values latched on rising edge

of INITN. During conﬁguration, a pull-up is enabled.

CFG[1:0]

I

Open Drain pin - Indicates the FPGA is ready to be conﬁgured. During con-

I/O ﬁguration, a pull-up is enabled. If CFG1 and CFG0 are high (SDM) then this

pin is pulled low.

INITN

Initiates conﬁguration sequence when asserted low. This pin always has an

active pull-up.

PROGRAMN

DONE

I

Open Drain pin - Indicates that the conﬁguration sequence is complete, and

the startup sequence is in progress.

I/O

CCLK

BUSY

I/O Conﬁguration Clock for conﬁguring an FPGA in sysCONFIG mode.

I/O Generally not used. After conﬁguration it is a user-programmable I/O pin.

sysCONFIG chip select (Active low). During conﬁguration, a pull-up is

enabled. After conﬁguration it is user a programmable I/O pin.

CSN

I

sysCONFIG chip select (Active Low). During conﬁguration, a pull-up is

enabled. After conﬁguration it is user programmable I/O pin

CS1N

I

Write Data on Parallel port (Active low). After conﬁguration it is a user pro-

grammable I/O pin

WRITEN

D[7:0]

I

sysCONFIG Port Data I/O. After conﬁguration these are user programmable

I/O pins.

I/O

Output for serial conﬁguration data (rising edge of CCLK) when using

sysCONFIG port. After conﬁguration, it is a user-programmable I/O pin.

DOUT, CSON

O

Input for serial conﬁguration data (clocked with CCLK) when using sysCON-

FIG port. During conﬁguration, a pull-up is enabled. After conﬁguration it is a

user-programmable I/O pin.

DI

I

Sleep Mode pin - Active low sleep pin. When this pin is held high, the device

operates normally. When driven low, the device moves into Sleep Mode after

a speciﬁed time.This pin has a weak internal pull-up, but when not used an

SLEEPN²

TOE³

external pull-up to V is recommended.

CC

Test Output Enable tri-states all I/O pins when driven low. This pin has a

weak internal pull-up, but when not used an external pull-up to V is recom-

CC

mended.

1. Applies to LFXP10, LFXP15 and LFXP20 only.

2. Applies to LFXP “C” devices only.

3. Applies to LFXP “E” devices only.

4-2

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin

PICs Associated

with DQS Strobe

DDR Strobe (DQS)

and Data (DQ) Pins

PIO within PIC

Polarity

True

A

B

A

B

A

B

A

DQ

P[Edge] [n-4]

Complement

True

P[Edge] [n-3]

P[Edge] [n-2]

P[Edge] [n-1]

P[Edge] [n]

Complement

True

Complement

True

B

A

B

A

B

A

B

Complement

True

DQ

[Edge]DQSn

DQ

P[Edge] [n+1]

P[Edge] [n+2]

P[Edge] [n+3]

Complement

True

DQ

Complement

True

DQ

Complement

DQ

Notes:

1. “n” is a row/column PIC number.

2. The DDR interface is designed for memories that support one DQS strobe per eight bits of data. In some packages, all the potential DDR

data (DQ) pins may not be available.

3. The deﬁnition of the PIC numbering is provided in the Signal Names column of the Signal Descriptions table in this data sheet.

4-3

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Pin Information Summary¹

XP3

XP6

Pin Type

Single Ended User I/O

Differential Pair User I/O²

100 TQFP 144 TQFP 208 PQFP 144 TQFP 208 PQFP 256 fpBGA

62

19

11

14

5

100

35

11

14

5

136

56

11

14

5

100

35

11

14

5

142

58

11

14

5

188

80

Dedicated

11

Conﬁguration

Muxed

14

TAP

5

Dedicated (total without supplies)

6

V

2

4

8

4

8

CC

2

4

2

CCAUX

CCPLL

2

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

V

CCIO

1

2

1

2

1

2

1

2

1

2

1

2

1

2

GND

NC

10

2

13

2

24

2

13

2

24

2

24

2

PLL

0

6

0

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

8/2

9/0

8/3

6/2

5/2

12/4

4/2

10/4

1

12/3

12/2

12/5

13/5

14/6

12/4

13/5

12/5

1

20/8

18/6

14/6

21/9

14/6

1

12/3

12/2

12/5

13/5

14/6

12/4

13/5

12/5

1

20/8

18/6

17/7

14/6

21/9

17/7

14/6

1

26/11

21/9

26/11

21/9

1

SingleEnded/Differential

I/O per Bank²

V

CCJ

1. During conﬁguration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not

bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after conﬁguration.

2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table

for more information.

4-4

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Pin Information Summary¹(Cont.)

XP10

XP15

XP20

Pin Type

256 fpBGA 388 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA

Single Ended User I/O

Differential Pair User I/O²

188

76

11

14

5

244

104

11

188

76

11

14

5

268

112

11

300

128

11

188

76

11

14

5

268

112

11

340

144

11

Dedicated

Conﬁguration

Muxed

14

TAP

5

Dedicated

(total without supplies)

6

V

8

14

8

14

28

12

8

14

28

CC

4

2

4

2

4

2

4

12

CCAUX

CCPLL

2

5

2

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

2

5

4

2

5

4

2

5

2

5

4

2

5

4

2

4

2

4

2

4

2

4

2

4

V

CCIO

2

5

2

5

4

2

5

4

2

5

2

5

4

2

5

4

2

4

2

4

2

4

2

4

2

4

2

4

GND

NC

24

50

24

50

56

24

50

56

2

PLL

0

24

0

40

0

Bank0

Bank1

Bank2

Bank3

Bank4

Bank5

Bank6

Bank7

26/11

21/8

26/11

21/8

1

33/14

28/12

33/14

28/12

1

26/11

21/8

26/11

21/8

1

39/16

28/12

39/16

28/12

1

40/17

35/15

40/17

35/15

1

26/11

21/8

26/11

21/8

1

39/16

28/12

39/16

28/12

1

47/20

38/16

47/20

38/16

1

Single Ended/

Differential I/O

per Bank²

V

CCJ

1. During conﬁguration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded

to a package pin), it is also tri-stated with an internal pull-up resistor enabled after conﬁguration.

2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table for

more information.

4-5

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Power Supply and NC Connections

Signals

100 TQFP

28, 77

144 TQFP

208 PQFP

256 fpBGA

388 fpBGA

484 fpBGA

V

14, 39, 73, 112

19, 35, 53, 80, 107, D4, D13, E5, E12, H9, J8, J15, K8,

F10, F13, G9, G10,

CC

151, 158, 182

M5, M12, N4, N13 K15, L8, L15, M8, G13, G14, H8,

M15, N8, N15, P8, H15, J7, J16, K6,

P15, R9

K7, K16, K17, N6,

N7, N16, N17, P7,

P16, R8, R15, T9,

T10, T13, T14,

U10, U13

V

94

82

133

119

189, 199

167, 177

F7, F8

G8, G9, G10, G11, F11, G11, H10,

CCIO0

CCIO1

H8

H11

F9, F10

G12, G13, G14,

G15, H15

F12, G12, H12,

H13

V

65

58

98

88

140, 149

115, 125

G11, H11

J11, K11

H16, J16, K16, L16 K15, L15, L16, L17

CCIO2

CCIO3

M16, N16, P16,

R16

M15, M16, M17,

N15

V

47

38

61, 68

49

87, 97

64, 74

L9, L10

L7, L8

R15, T12, T13,

T14, T15

R12, R13, T12,

U12

CCIO4

CCIO5

R8, T8, T9, T10,

T11

R10, R11, T11,

U11

V

22

21

28, 41

13, 23

154

J6, K6

G6, H6

D16

M7, N7, P7, R7

M6, M7, M8, N8

CCIO6

CCIO7

CCJ

7

8

H7, J7, K7, L7

K8, L6, L7, L8

73

108

19

E20

M2

E20

L5

17

25

H4

CCP0

CCP1

CCAUX

60

91

128

J12

M21

L18

25, 71

36, 106

50, 152

E4, E13, M4, M13 G7, G16, T7, T16 G7, G8, G15, G16,

H7, H16, R7, R16,

T7, T8, T15, T16

GND¹

10, 18, 21, 33, 43, 3, 11, 20, 28, 44,

44, 52, 59, 68, 84, 54, 56, 64, 75, 85, 49, 59, 69, 79, 82, G7, G8, G9, G10, H12, H13, H14, J9, B1, B22, H9, H14,

5, 7, 16, 26, 38, 47, A1, A16, F6, F11, A1, A22, H10, H11, A1, A2, A21, A22,

90, 99

90, 101, 121, 127, 92, 106, 109, 118, H5, H7, H8, H9,

J10, J11, J12, J13, J8, J9, J10, J11,

J14, K9, K10, K11, J12, J13, J14, J15,

K12, K13, K14, L9, K9, K10, K11, K12,

136

121, 127, 130, 135, H10, J7, J8, J9,

143, 163, 172, 181, J10, J13, K7, K8,

184, 194, 207

K9, K10, L6, L11, L10, L11, L12, L13, K13, K14, L9, L10,

T1, T16

L14, M9, M10,

M11, M12, M13,

L11, L12, L13, L14,

M9, M10, M11,

M14, N1, N9, N10, M12, M13, M14,

N11, N12, N13, M20, N2, N9, N10,

N14, N22, P9, P10, N11, N12, N13,

P11, P12, P13,

P14, R10, R11,

R12, R13, R14,

AB1, AB22

N14, P8, P9, P10,

P11, P12, P13,

P14, P15, R9, R14,

AA1, AA22, AB1,

AB2, AB21, AB22

NC²

—

XP3: 27, 33, 34,

129, 133, 134

—

XP10: C2, C15,

XP15:B21, C4, C5,

C16, C17, D4, D5, C6, C18, C19, C20,

D6, D7, D16, D17, C21, D6, D18, E4,

E4, E19, W3, W4, E6, E18, F6, L1,

W7, W17, W18,

W19, W20, Y3,

Y15, Y16, AA1,

AA2

L19, L20, M1, M2,

M19, M21, N1,

N21, N22, P1, P2,

U5, U6, U17, U18,

V5, V6, V17, V18,

W17, W18, W19,

Y3, Y4, Y5

1. All grounds must be electrically connected at the board level.

2. NC pins should not be connected to any active signals, V or GND.

CC

4-6

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 Logic Signal Connections: 100 TQFP

Pin Number

Pin Function

Bank

0

7

-

Differential

Dual Function

1

CFG1

-

2

DONE

PROGRAMN

CCLK

-

3

-

4

-

5

PL3A

T

C

-

LUM0_PLLT_FB_A

6

PL3B

LUM0_PLLC_FB_A

7

VCCIO7

PL5A

-

8

-

VREF1_7

9

PL6B

-

VREF2_7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

GNDIO7

PL7A

-

T³

C³

T

C

T³

C³

-

DQS

PL7B

-

PL8A

LUM0_PLLT_IN_A

PL8B

LUM0_PLLC_IN_A

PL9A

-

PL9B

-

VCCP0

GNDP0

PL12A

PL12B

GNDIO6

VCCIO6

PL18A

PL18B

VCCAUX

SLEEPN¹/TOE²

INITN

-

6

-

T

C

-

PCLKT6_0

PCLKC6_0

-

T³

C³

-

5

-

VCC

-

PB2B

5

-

VREF1_5

PB5B

-

VREF2_5

PB8A

T

C

-

PB8B

-

GNDIO5

PB9A

-

PB10B

PB11A

PB11B

VCCIO5

PB12A

PB12B

PB13A

PB13B

GND

-

T

C

-

DQS

-

T

C

T

C

-

4-7

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 Logic Signal Connections: 100 TQFP (Cont.)

Pin Number

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

Pin Function

GNDIO4

PB15A

PB15B

VCCIO4

PB19A

PB19B

PB24A

PR18B

GNDIO3

PR18A

PR15B

PR14A

PR13B

PR13A

VCCIO3

GNDP1

VCCP1

PR9B

Bank

4

3

-

Differential

Dual Function

-

T

C

-

PCLKT4_0

PCLKC4_0

-

T

C

-

DQS

VREF1_4

VREF2_4

C³

-

T³

-

VREF1_3

-

VREF2_3

C

T

-

2

-

C

T

C

T

-

PCLKC2_0

PR9A

PCLKT2_0

PR8B

RUM0_PLLC_IN_A

PR8A

RUM0_PLLT_IN_A

VCCIO2

PR6B

-

VREF1_2

PR5A

-

VREF2_2

GNDIO2

PR3B

-

C

T

-

RUM0_PLLC_FB_A

PR3A

RUM0_PLLT_FB_A

VCCAUX

TDO

-

VCCJ

-

TDI

-

TMS

-

TCK

-

VCC

-

PT24A

PT23A

PT22B

PT21A

VCCIO1

PT20B

GNDIO1

PT17A

PT16A

PT15B

1

-

D0

D1

D2

-

D3

-

D4

D5

D6

-

4-8

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 Logic Signal Connections: 100 TQFP (Cont.)

Pin Number

Pin Function

PT14B

PT13B

GNDIO0

PT13A

PT12B

PT12A

VCCIO0

PT9A

Bank

Differential

Dual Function

88

89

90

91

92

93

94

95

96

97

98

99

100

1

0

-

C

-

D7

BUSY

-

T

C

T

-

CS1N

PCLKC0_0

PCLKT0_0

-

DOUT

PT8A

-

WRITEN

PT6A

-

DI

PT5A

-

CSN

GND

-

CFG0

0

-

1. Applies to LFXP “C” only.

2. Applies to LFXP “E” only.

3. Supports dedicated LVDS outputs.

4-9

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP

LFXP3

LFXP6

Number Pin Function

Bank Differential

Dual Function

Pin Function

PROGRAMN

CCLK

Bank Differential

Dual Function

1

PROGRAMN

CCLK

7

-

7

-

2

-

3

GND

-

GND

-

4

PL2A

7

-

T³

C³

T

C

-

PL2A

7

-

T³

C³

T

C

-

5

PL2B

-

PL2B

-

6

PL3A

LUM0_PLLT_FB_A

PL3A

LUM0_PLLT_FB_A

7

PL3B

LUM0_PLLC_FB_A

PL3B

LUM0_PLLC_FB_A

8

VCCIO7

PL5A

-

VCCIO7

PL5A

-

9

-

VREF1_7

-

VREF1_7

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

PL6B

-

VREF2_7

PL6B

-

VREF2_7

GNDIO7

PL7A

-

GNDIO7

PL7A

-

T³

C³

-

DQS

T³

C³

-

DQS

PL7B

-

PL7B

-

VCC

-

VCC

-

PL8A

7

-

T

C

T³

C³

-

LUM0_PLLT_IN_A

PL8A

7

-

T

C

T³

C³

-

LUM0_PLLT_IN_A

PL8B

LUM0_PLLC_IN_A

PL8B

LUM0_PLLC_IN_A

PL9A

-

PL9A

-

PL9B

-

PL9B

-

VCCP0

GNDP0

VCCIO6

PL11A

PL11B

PL12A

PL12B

PL13A

PL13B

GNDIO6

PL14A

PL15B

PL16A

PL16B

PL17A

PL18A

PL18B

VCCAUX

SLEEPN¹/TOE²

INITN

-

VCCP0

GNDP0

VCCIO6

PL16A

PL16B

PL17A

PL17B

PL18A

PL18B

GNDIO6

PL22A

PL23B

PL24A

PL24B

PL25A

PL26A

PL26B

VCCAUX

SLEEPN¹/TOE²

INITN

-

6

-

6

-

T³

C³

T

C

T³

C³

-

T³

C³

T

C

T³

C³

-

PCLKT6_0

PCLKC6_0

-

VREF1_6

-

VREF1_6

-

VREF2_6

-

VREF2_6

T³

C³

-

T³

C³

-

DQS

T³

C³

-

T³

C³

-

DQS

-

5

-

5

-

VCC

-

VCC

-

PB2B

5

-

VREF1_5

PB5B

5

-

VREF1_5

PB5B

VREF2_5

PB8B

-

VREF2_5

-

PB7A

T

C

-

PB10A

PB10B

GNDIO5

PB12A

PB13B

T

C

-

PB7B

GNDIO5

PB9A

-

PB10B

-

4-10

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.)

LFXP3

LFXP6

Number Pin Function

Bank Differential

Dual Function

Pin Function

PB14A

PB14B

VCCIO5

PB15A

PB15B

PB16A

PB16B

GND

Bank Differential

Dual Function

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

PB11A

PB11B

VCCIO5

PB12A

PB12B

PB13A

PB13B

GND

5

-

T

C

-

DQS

5

-

T

C

-

DQS

-

T

C

T

C

-

T

C

T

C

-

PB14A

GNDIO4

PB14B

PB15A

PB15B

PB16A

VCCIO4

PB16B

PB19A

GNDIO4

PB19B

PB20A

PB20B

VCCIO4

PB22A

PB24A

PB24B

PB25A

VCC

4

-

T

-

PB17A

GNDIO4

PB17B

PB18A

PB18B

PB19A

VCCIO4

PB19B

PB22A

GNDIO4

PB22B

PB23A

PB23B

VCCIO4

PB25A

PB27A

PB27B

PB28A

VCC

4

-

T

-

C

T

C

T

-

C

T

C

T

-

PCLKT4_0

PCLKC4_0

-

C

T

-

C

T

-

DQS

-

C

T

C

-

VREF1_4

C

T

C

-

VREF1_4

-

T

C

-

VREF2_4

T

C

-

VREF2_4

-

C³

-

C³

-

PR18B

GNDIO3

PR18A

PR17B

PR17A

PR16B

PR16A

PR15B

PR14A

PR13B

PR13A

GND

3

-

PR26B

GNDIO3

PR26A

PR25B

PR25A

PR24B

PR24A

PR23B

PR22A

PR21B

PR21A

GND

3

-

T³

C

T

C³

T³

-

T³

C

T

C³

T³

-

DQS

VREF1_3

-

VREF2_3

-

VREF2_3

C

T

-

C³

T³

-

PR12A

PR11B

VCCIO3

PR11A

GNDP1

VCCP1

PR9B

3

-

PR20A

PR19B

VCCIO3

PR19A

GNDP1

VCCP1

PR12B

3

-

C³

-

C

-

T

-

T³

-

2

C

PCLKC2_0

2

C

PCLKC2_0

4-11

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.)

LFXP3

LFXP6

Number Pin Function

Bank Differential

Dual Function

Pin Function

PR12A

PR8B

Bank Differential

Dual Function

93

PR9A

PR8B

2

-

T

C

T

C³

T³

-

PCLKT2_0

2

-

T

C

T

C³

T³

-

PCLKT2_0

94

RUM0_PLLC_IN_A

95

PR8A

RUM0_PLLT_IN_A

PR8A

RUM0_PLLT_IN_A

96

PR7B

-

PR7B

-

97

PR7A

DQS

PR7A

DQS

98

VCCIO2

PR6B

-

VCCIO2

PR6B

-

99

-

VREF1_2

-

VREF1_2

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

PR5A

-

VREF2_2

PR5A

-

VREF2_2

GNDIO2

PR3B

-

GNDIO2

PR3B

-

C

T

C³

T³

-

RUM0_PLLC_FB_A

C

T

C³

T³

-

RUM0_PLLC_FB_A

PR3A

RUM0_PLLT_FB_A

PR3A

RUM0_PLLT_FB_A

PR2B

-

PR2B

-

PR2A

-

PR2A

-

VCCAUX

TDO

-

VCCAUX

TDO

-

VCCJ

-

VCCJ

-

TDI

-

TDI

-

TMS

-

TMS

-

TCK

-

TCK

-

VCC

-

VCC

-

PT25A

PT24A

PT23A

PT22B

PT22A

PT21A

VCCIO1

PT20B

GNDIO1

PT17A

PT16A

PT15B

PT15A

PT14B

GND

1

-

VREF1_1

PT28A

PT27A

PT26A

PT25B

PT25A

PT24A

VCCIO1

PT23B

GNDIO1

PT20A

PT19A

PT18B

PT18A

PT17B

GND

1

-

VREF1_1

-

D0

-

D0

C

T

-

D1

C

T

-

D1

VREF2_1

D2

-

D3

-

D3

-

D4

-

D4

-

D5

-

D5

-

C

T

-

D6

C

T

-

D6

-

D7

-

BUSY

CS1N

PCLKC0_0

PCLKT0_0

-

BUSY

CS1N

PCLKC0_0

PCLKT0_0

-

PT13B

PT13A

PT12B

PT12A

PT11B

VCCIO0

PT11A

PT9A

0

C

T

C

T

C

-

PT16B

PT16A

PT15B

PT15A

PT14B

VCCIO0

PT14A

PT12A

GNDIO0

PT11A

PT10A

0

C

T

C

T

C

-

T

-

DQS

T

-

DQS

DOUT

-

DOUT

-

GNDIO0

PT8A

-

WRITEN

VREF1_0

-

WRITEN

VREF1_0

PT7A

-

4-12

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.)

LFXP3

LFXP6

Number Pin Function

Bank Differential

Dual Function

Pin Function

PT9A

Bank Differential

Dual Function

139

140

141

142

143

144

PT6A

PT5A

PT3B

CFG0

CFG1

DONE

0

-

DI

0

-

DI

-

CSN

PT8A

CSN

-

VREF2_0

PT6B

VREF2_0

-

CFG0

-

CFG1

DONE

1. Applies to LFXP “C” only.

2. Applies to LFXP “E” only.

3. Supports dedicated LVDS outputs.

4-13

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP

LFXP3

LFXP6

Number Pin Function

Bank Differential

Dual Function

Pin Function

CFG1

Bank Differential

Dual Function

1

CFG1

DONE

PROGRAMN

CCLK

GND

0

7

-

0

7

-

2

-

DONE

PROGRAMN

CCLK

-

3

-

4

-

5

-

GND

-

6

PL2A

7

-

T³

-

PL2A

7

-

T³

-

7

GNDIO7

PL2B

-

GNDIO7

PL2B

-

8

C³

T

C

T³

C³

-

C³

T

C

T³

C³

-

9

PL3A

LUM0_PLLT_FB_A

PL3A

LUM0_PLLT_FB_A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

PL3B

LUM0_PLLC_FB_A

PL3B

LUM0_PLLC_FB_A

PL4A

-

PL4A

-

PL4B

-

PL4B

-

VCCIO7

PL5A

-

VCCIO7

PL5A

-

VREF1_7

-

VREF1_7

PL6B

-

VREF2_7

PL6B

-

VREF2_7

GNDIO7

PL7A

-

GNDIO7

PL7A

-

T³

C³

-

DQS

T³

C³

-

DQS

PL7B

-

PL7B

-

VCC

-

VCC

-

PL8A

7

-

T

C

T³

-

LUM0_PLLT_IN_A

PL8A

7

-

T

C

T³

-

LUM0_PLLT_IN_A

PL8B

LUM0_PLLC_IN_A

PL8B

LUM0_PLLC_IN_A

PL9A

-

PL9A

-

VCCIO7

PL9B

-

VCCIO7

PL9B

-

C³

-

C³

-

VCCP0

GNDP0

NC

-

VCCP0

GNDP0

PL15B

VCCIO6

PL16A

PL16B

PL17A

PL17B

PL18A

PL18B

VCC

-

6

-

VCCIO6

PL11A

PL11B

PL12A

PL12B

NC

6

-

T³

C³

T

C

-

T³

C³

T

C

T³

C³

-

T³

C³

-

PCLKT6_0

PCLKC6_0

-

NC

-

VCC

-

PL13A

PL13B

GNDIO6

PL14A

PL15B

VCCIO6

PL16A

PL16B

PL17A

PL17B

PL18A

6

T³

C³

-

PL21A

PL21B

GNDIO6

PL22A

PL23B

VCCIO6

PL24A

PL24B

PL25A

PL25B

PL26A

6

-

VREF1_6

-

VREF1_6

-

VREF2_6

-

VREF2_6

-

T³

C³

T

C

T³

DQS

T³

C³

T

C

T³

DQS

-

4-14

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.)

LFXP3

LFXP6

Number Pin Function

Bank Differential

Dual Function

Pin Function

GNDIO6

PL26B

GND

Bank Differential

Dual Function

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

GNDIO6

PL18B

GND

6

-

C³

-

6

-

C³

-

VCCAUX

SLEEPN¹/TOE²

INITN

-

VCCAUX

SLEEPN¹/TOE²

INITN

-

5

-

5

-

VCC

-

VCC

-

PB2B

5

-

VREF1_5

PB5B

5

-

VREF1_5

PB3A

T

C

T

C

-

PB6A

T

C

T

C

-

DQS

PB3B

-

PB6B

-

PB4A

-

PB7A

-

PB4B

-

PB7B

-

GNDIO5

PB5A

-

GNDIO5

PB8A

-

T

C

T

C

-

T

C

T

C

-

PB5B

VREF2_5

PB8B

VREF2_5

PB6A

-

PB9A

-

PB6B

-

PB9B

-

VCCIO5

PB7A

-

VCCIO5

PB10A

PB10B

PB11A

PB11B

GNDIO5

PB12A

PB13B

PB14A

PB14B

VCCIO5

PB15A

PB15B

PB16A

PB16B

GND

-

T

C

T

C

-

T

C

T

C

-

PB7B

-

PB8A

-

PB8B

-

GNDIO5

PB9A

-

PB10B

PB11A

PB11B

VCCIO5

PB12A

PB12B

PB13A

PB13B

GND

-

T

C

-

DQS

T

C

-

DQS

-

T

C

T

C

-

T

C

T

C

-

VCC

-

VCC

-

PB14A

GNDIO4

PB14B

PB15A

PB15B

PB16A

VCCIO4

PB16B

PB17A

PB18B

PB19A

GNDIO4

4

T

-

PB17A

GNDIO4

PB17B

PB18A

PB18B

PB19A

VCCIO4

PB19B

PB20A

PB21B

PB22A

GNDIO4

4

T

-

C

T

C

T

-

C

T

C

T

-

PCLKT4_0

PCLKC4_0

-

C

-

C

-

DQS

-

DQS

-

T

-

T

-

4-15

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.)

LFXP3

LFXP6

Number Pin Function

Bank Differential

Dual Function

Pin Function

PB22B

PB23A

PB23B

PB24A

VCCIO4

PB24B

PB25A

PB25B

PB26A

PB26B

PB27A

PB30A

PB30B

GND

Bank Differential

Dual Function

93

PB19B

PB20A

PB20B

PB21A

VCCIO4

PB21B

PB22A

PB22B

PB23A

PB23B

PB24A

PB24B

PB25A

GND

4

-

C

T

C

T

-

VREF1_4

4

-

C

T

C

T

-

VREF1_4

94

-

95

-

96

-

97

-

98

C

T

C

T

C

T

C

-

C

T

C

T

C

-

99

-

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

-

VREF2_4

-

T

C

-

DQS

-

VCC

-

C³

-

VCC

-

C³

-

PR18B

GNDIO3

PR18A

PR17B

PR17A

PR16B

PR16A

VCCIO3

PR15B

PR14A

GNDIO3

PR13B

PR13A

GND

3

-

PR26B

GNDIO3

PR26A

PR25B

PR25A

PR24B

PR24A

VCCIO3

PR23B

PR22A

GNDIO3

PR21B

PR21A

GND

3

-

T³

C

T

C³

T³

-

T³

C

T

C³

T³

-

DQS

-

VREF1_3

-

VREF1_3

-

VREF2_3

-

VREF2_3

-

C

T

-

C³

T³

-

PR12B

PR12A

PR11B

VCCIO3

PR11A

GNDP1

VCCP1

NC

3

-

C

T

C

-

PR20B

PR20A

PR19B

VCCIO3

PR19A

GNDP1

VCCP1

PR13A

GND

3

-

C

T

C³

-

T

-

T³

-

2

-

GND

-

PR9B

2

-

C

T

-

PCLKC2_0

PR12B

PR12A

PR11B

PR11A

GNDIO2

PR8B

2

C

T

C³

T³

-

PCLKC2_0

PR9A

PCLKT2_0

NC

-

NC

-

GNDIO2

PR8B

2

-

C

T

C³

RUM0_PLLC_IN_A

RUM0_PLLT_IN_A

-

C

T

C³

RUM0_PLLC_IN_A

RUM0_PLLT_IN_A

-

PR8A

PR7B

4-16

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.)

LFXP3

LFXP6

Number Pin Function

Bank Differential

Dual Function

Pin Function

PR7A

Bank Differential

Dual Function

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

PR7A

VCCIO2

PR6B

2

-

T³

DQS

2

-

T³

DQS

-

VCCIO2

PR6B

-

VREF1_2

-

VREF1_2

PR5A

-

VREF2_2

PR5A

-

VREF2_2

GNDIO2

PR4B

-

GNDIO2

PR4B

-

C³

T³

C

T

C³

-

C³

T³

C

T

C³

-

PR4A

-

PR4A

-

PR3B

RUM0_PLLC_FB_A

PR3B

RUM0_PLLC_FB_A

PR3A

RUM0_PLLT_FB_A

PR3A

RUM0_PLLT_FB_A

PR2B

-

PR2B

-

VCCIO2

PR2A

-

VCCIO2

PR2A

-

T³

-

T³

-

VCC

-

VCC

-

VCCAUX

TDO

-

VCCAUX

TDO

-

VCCJ

-

VCCJ

-

TDI

-

TDI

-

TMS

-

TMS

-

TCK

-

TCK

-

VCC

-

VCC

-

PT25A

PT24B

PT24A

PT23A

GNDIO1

PT22B

PT22A

PT21A

VCCIO1

PT20B

PT20A

PT19B

PT19A

GNDIO1

PT18B

PT17A

PT16B

PT16A

VCCIO1

PT15B

PT15A

PT14B

GND

1

-

VREF1_1

PT28A

PT27B

PT27A

PT26A

GNDIO1

PT25B

PT25A

PT24A

VCCIO1

PT23B

PT23A

PT22B

PT22A

GNDIO1

PT21B

PT20A

PT19B

PT19A

VCCIO1

PT18B

PT18A

PT17B

GND

1

-

VREF1_1

C

T

-

C

T

-

D0

-

C

T

-

D1

C

T

-

D1

VREF2_1

D2

-

C

T

C

T

-

D3

C

T

C

T

-

D3

-

DQS

-

D4

-

D4

C

T

-

C

T

-

D5

-

C

T

-

D6

C

T

-

D6

-

D7

-

VCC

-

BUSY

-

VCC

-

BUSY

-

PT13B

GNDIO0

0

C

-

PT16B

GNDIO0

0

C

-

4-17

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP (Cont.)

LFXP3

LFXP6

Number Pin Function

Bank Differential

Dual Function

Pin Function

PT16A

PT15B

PT15A

PT14B

VCCIO0

PT14A

PT13B

PT12A

PT11B

GNDIO0

PT11A

PT10B

PT10A

PT9B

Bank Differential

Dual Function

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

PT13A

PT12B

PT12A

PT11B

VCCIO0

PT11A

PT10B

PT9A

0

-

T

C

T

C

-

CS1N

0

-

T

C

T

C

-

CS1N

PCLKC0_0

PCLKT0_0

-

T

-

DQS

T

-

DQS

-

DOUT

-

DOUT

PT8B

C

-

C

-

GNDIO0

PT8A

-

T

C

T

C

-

WRITEN

T

C

T

C

-

WRITEN

PT7B

-

PT7A

VREF1_0

PT6B

-

VCCIO0

PT6A

-

VCCIO0

PT9A

-

T

C

T

C

T

-

DI

T

C

T

C

T

-

DI

PT5B

-

PT8B

-

PT5A

CSN

PT8A

CSN

PT4B

-

PT7B

-

PT4A

-

PT7A

-

PT3B

VREF2_0

PT6B

VREF2_0

PT2B

-

PT5B

-

GND

-

GND

-

CFG0

0

-

CFG0

0

-

1. Applies to LFXP “C” only.

2. Applies to LFXP “E” only.

3. Supports dedicated LVDS outputs.

4-18

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA

LFXP6

LFXP10

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

C2

C1

-

PROGRAMN

CCLK

7

-

PROGRAMN

CCLK

7

-

GNDIO7

PL3A

-

GNDIO7

PL3A

-

D2

D3

D1

E2

-

T

LUM0_PLLT_FB_A

T

C

-

LUM0_PLLT_FB_A

PL3B

C

T³

-

LUM0_PLLC_FB_A

PL3B

LUM0_PLLC_FB_A

PL2A

-

PL5A

-

PL5A

VREF1_7

PL6B

-

VREF1_7

GNDIO7

PL7A

-

GNDIO7

PL7A

-

E1

F1

E3

F4

F3

F2

-

T³

C³

T

DQS

T³

C³

T

C

T³

C³

-

DQS

PL7B

-

PL7B

-

PL12A

PL12B

PL4A

-

PL8A

-

C

T³

C³

-

PL8B

-

PL9A

-

PL4B

-

PL9B

-

GNDIO7

PL2B

-

GNDIO7

PL11B

PL12A

PL12B

PL13A

PL13B

PL14A

PL15B

GNDIO7

PL16A

PL16B

PL18A

PL18B

VCCP0

GNDP0

PL20A

PL20B

GNDIO6

PL22A

PL23B

PL24A

PL24B

PL25A

PL25B

PL26A

GNDIO6

PL26B

PL28A

-

G1

G3

G2

H1

H2

G4

G5

-

C³

-

PL8A

T

LUM0_PLLT_IN_A

T

C

T³

C³

-

LUM0_PLLT_IN_A

PL8B

C

T³

C³

-

LUM0_PLLC_IN_A

PL9A

-

PL9B

-

PL6B

VREF2_7

PL14A

GNDIO7

PL11A

PL11B

PL13A

PL13B

VCCP0

GNDP0

PL17A

PL17B

GNDIO6

PL15B

PL22A

PL16A

PL16B

PL18A

PL18B

PL19A

GNDIO6

PL19B

PL21A

-

J1

J2

H3

J3

H4

H5

K1

K2

-

T³

C³

T³

C³

-

T³

C³

T³

C³

-

DQS

-

6

T

PCLKT6_0

6

T

C

-

PCLKT6_0

C

-

PCLKC6_0

-

J4

J5

L1

L2

M1

M2

K3

-

VREF1_6

-

VREF1_6

T³

C³

T³

C³

T³

-

T³

C³

T

C

T³

-

DQS

-

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

-

L3

L4

C³

T³

C³

-

4-19

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP6

LFXP10

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

K4

K5

-

PL20A

PL20B

GNDIO6

PL23B

PL21B

PL24A

PL24B

PL25A

PL25B

PL26A

GNDIO6

PL26B

SLEEPN¹/TOE²

INITN

6

-

T

C

-

PL29A

PL29B

GNDIO6

PL31A

PL32B

PL33A

PL33B

PL34A

PL34B

PL35A

GNDIO6

PL35B

SLEEPN¹/TOE²

INITN

6

-

T

C

-

N1

N2

P1

P2

L5

M6

M3

-

VREF2_6

-

VREF2_6

C³

T³

C³

T

C

T³

-

DQS

T³

C³

T

C

T³

-

DQS

-

LLM0_PLLT_FB_A

-

LLM0_PLLC_FB_A

-

N3

P4

P3

-

C³

-

C³

-

5

-

5

-

GNDIO5

PB2A

-

GNDIO5

PB6A

-

R4

N5

-

T

C

-

T

C

-

PB2B

-

PB6B

-

GNDIO5

PB5B

-

GNDIO5

PB7A

-

P5

R1

N6

M7

R2

T2

R3

T3

-

VREF1_5

T

C

-

VREF1_5

PB3B

C

-

PB7B

-

PB4A

-

PB8A

-

PB3A

T

C

T

C

-

PB9B

-

PB6A

DQS

PB10A

PB10B

PB11A

PB11B

GNDIO5

PB12A

PB12B

PB13A

PB13B

PB14A

PB14B

PB15A

PB15B

GNDIO5

PB16A

PB17B

PB18A

PB18B

PB19A

PB19B

T

C

T

C

-

DQS

PB6B

-

PB7A

-

PB7B

-

GNDIO5

PB8A

-

T4

R5

N7

M8

T5

P6

T6

R6

-

T

C

T

C

T

C

T

C

-

T

C

T

C

T

C

T

C

-

PB8B

VREF2_5

PB9A

-

PB9B

-

PB10A

PB10B

PB11A

PB11B

GNDIO5

PB12A

PB13B

PB14A

PB14B

PB15A

PB15B

-

P7

N8

R7

T7

P8

T8

-

T

C

T

C

DQS

T

C

T

C

DQS

-

4-20

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP6

LFXP10

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

R8

T9

PB16A

PB16B

PB17A

GNDIO4

PB17B

PB18A

PB18B

PB19A

PB19B

PB20A

PB21B

PB22A

GNDIO4

PB22B

PB23A

PB23B

PB24A

PB24B

PB25A

PB25B

PB26A

GNDIO4

PB26B

PB27A

PB27B

PB28A

PB29B

PB30A

PB30B

PB31A

GNDIO4

PB31B

GNDIO3

PR26B

PR26A

PR24B

PR24A

PR15B

PR23B

GNDIO3

PR25B

PR25A

5

4

3

T

C

T

-

PB20A

PB20B

PB21A

GNDIO4

PB21B

PB22A

PB22B

PB23A

PB23B

PB24A

PB25B

PB26A

GNDIO4

PB26B

PB27A

PB27B

PB28A

PB28B

PB29A

PB29B

PB30A

GNDIO4

PB30B

PB31A

PB31B

PB32A

PB33B

PB34A

PB34B

PB35A

GNDIO4

PB35B

GNDIO3

PR34B

PR34A

PR33B

PR33A

PR32B

PR31A

GNDIO3

PR29B

PR29A

5

4

3

T

C

T

-

R9

-

P9

C

T

C

T

C

-

C

T

C

T

C

-

T10

T11

R10

P10

N9

PCLKT4_0

PCLKC4_0

-

M9

-

R12

-

T

-

DQS

T

-

DQS

-

T12

P13

R13

M11

N11

N10

M10

T13

-

C

T

C

T

C

T

C

T

-

VREF1_4

C

T

C

T

C

T

C

T

-

VREF1_4

-

P14

R11

P12

T14

R14

P11

N12

T15

-

C

T

C

-

C

T

C

-

VREF2_4

-

T

C

T

-

DQS

T

C

T

-

DQS

-

R15

-

C

-

C

-

P15

N15

P16

R16

M15

N14

-

C³

T³

C³

T³

-

C

T

C³

T³

-

RLM0_PLLC_FB_A

-

RLM0_PLLT_FB_A

-

DQS

-

VREF1_3

-

VREF1_3

-

M14

L13

C

T

C

T

4-21

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP6

LFXP10

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

L15

L14

-

PR21B

PR21A

GNDIO3

PR17B

PR20B

PR20A

PR19B

PR19A

PR17A

PR22A

GNDIO3

PR18B

PR18A

PR16B

PR16A

GNDP1

VCCP1

GNDIO2

PR12B

PR12A

PR13B

PR13A

PR2B

3

-

C³

T³

-

PR28B

PR28A

GNDIO3

PR26A

PR25B

PR25A

PR24B

PR24A

PR23B

PR22A

GNDIO3

PR21B

PR21A

PR19B

PR19A

GNDP1

VCCP1

GNDIO2

PR17B

PR17A

PR16B

PR16A

PR15B

PR14A

GNDIO2

PR13B

PR13A

PR12B

PR12A

PR11B

GNDIO2

PR8B

3

-

C³

T³

-

L12

M16

N16

K14

K15

K12

K13

-

C

T

C³

T³

T

-

C

T

C³

T³

-

RLM0_PLLC_IN_A

-

RLM0_PLLT_IN_A

-

DQS

-

VREF2_3

-

VREF2_3

-

L16

K16

J15

J14

J13

J12

-

C³

T³

C³

T³

-

C³

T³

C³

T³

-

2

-

2

-

J16

H16

H13

H12

H15

H14

-

C

T

C³

T³

C³

-

PCLKC2_0

C

T

C³

T³

-

PCLKC2_0

PCLKT2_0

-

DQS

-

PR6B

VREF1_2

-

VREF1_2

GNDIO2

PR11B

PR11A

PR8B

-

G15

G14

G16

F16

G13

-

C³

T³

C

T

-

C³

T³

C

T

-

RUM0_PLLC_IN_A

PR8A

RUM0_PLLT_IN_A

PR2A

T³

-

GNDIO2

PR9B

-

G12

F13

B16

C16

F15

E15

-

C³

T³

C³

T³

-

C

T

C³

T³

-

PR9A

-

PR8A

-

PR7B

-

PR7B

-

PR7A

DQS

PR7A

DQS

PR14A

PR5A

-

PR6B

-

VREF2_2

PR5A

-

VREF2_2

GNDIO2

PR4B

-

GNDIO2

PR4B

-

F14

E14

D15

C15

C³

T³

C

T

-

C³

T³

C

T

-

PR4A

-

PR4A

-

PR3B

RUM0_PLLC_FB_A

RUM0_PLLT_FB_A

PR3B

RUM0_PLLC_FB_A

RUM0_PLLT_FB_A

PR3A

4-22

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP6

LFXP10

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

E16

D16

D14

C14

B14

-

TDO

VCCJ

-

TDO

VCCJ

-

TDI

-

TDI

-

TMS

-

TMS

-

TCK

-

TCK

-

GNDIO1

PT31B

PT31A

GNDIO1

PT28A

PT30A

PT29B

PT30B

PT27B

PT27A

PT26B

PT26A

GNDIO1

PT25B

PT25A

PT24B

PT24A

PT23B

PT23A

PT22B

PT22A

GNDIO1

PT21B

PT20A

PT19B

PT19A

PT18B

PT18A

PT17B

PT17A

PT16B

GNDIO0

PT16A

PT15B

PT15A

PT14B

PT14A

1

0

-

GNDIO1

PT35B

PT35A

GNDIO1

PT34B

PT34A

PT33B

PT32A

PT31B

PT31A

PT30B

PT30A

GNDIO1

PT29B

PT29A

PT28B

PT28A

PT27B

PT27A

PT26B

PT26A

GNDIO1

PT25B

PT24A

PT23B

PT23A

PT22B

PT22A

PT21B

PT21A

PT20B

GNDIO0

PT20A

PT19B

PT19A

PT18B

PT18A

1

0

-

A15

B15

-

C

T

-

C

T

-

D12

C11

A14

B13

F12

E11

A13

C13

-

VREF1_1

C

T

-

VREF1_1

T

-

DQS

-

C

T

C

T

-

C

T

C

T

-

D0

-

C10

E10

A12

B12

C12

A11

B11

D11

-

C

T

C

T

C

T

C

T

-

D1

C

T

C

T

C

T

C

T

-

D1

VREF2_1

-

D2

D3

-

DQS

-

B9

-

D9

-

D4

-

D4

A10

B10

D10

A9

C

T

C

T

C

T

C

-

C

T

C

T

C

T

C

-

D5

D6

-

C9

D7

C8

-

BUSY

-

BUSY

-

E9

-

B8

T

C

T

C

T

CS1N

PCLKC0_0

PCLKT0_0

-

T

C

T

C

T

CS1N

PCLKC0_0

PCLKT0_0

-

A8

A7

B7

C7

DQS

4-23

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP6

LFXP10

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

E8

D8

A6

-

PT13B

PT12A

PT11B

GNDIO0

PT11A

PT10B

PT10A

PT9B

PT9A

PT8B

PT8A

PT7B

GNDIO0

PT7A

PT6B

PT6A

PT5B

PT4A

PT3B

PT3A

PT2B

GNDIO0

PT2A

CFG0

CFG1

DONE

GND

0

-

PT17B

PT16A

PT15B

GNDIO0

PT15A

PT14B

PT14A

PT13B

PT13A

PT12B

PT12A

PT11B

GNDIO0

PT11A

PT10B

PT10A

PT9B

PT8A

PT7B

PT7A

PT6B

GNDIO0

PT6A

CFG0

CFG1

DONE

GND

0

-

DOUT

C

-

C

-

C6

E7

D7

A5

B5

A4

B6

E6

-

T

C

T

C

T

C

T

C

-

WRITEN

T

C

T

C

T

C

T

C

-

WRITEN

-

VREF1_0

-

DI

-

CSN

-

D6

D5

A3

B3

B2

A2

B1

F5

-

T

C

T

-

T

C

T

-

VREF2_0

DQS

-

C

T

C

-

C

T

C

-

C5

C4

B4

C3

A1

A16

F11

F6

G10

G7

G8

G9

H10

H7

H8

H9

J10

J7

T

-

T

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

J8

GND

-

GND

-

J9

GND

-

GND

-

4-24

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP6

LFXP10

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

K10

K7

GND

-

GND

-

K8

GND

-

GND

-

K9

GND

-

GND

-

L11

L6

GND

-

GND

-

GND

-

GND

-

T1

GND

-

GND

-

T16

D13

D4

GND

-

GND

-

VCC

-

VCC

-

VCC

-

VCC

-

E12

E5

VCC

-

VCC

-

VCC

-

VCC

-

M12

M5

N13

N4

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

E13

E4

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

-

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

-

M13

M4

F7

-

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

F8

F10

F9

G11

H11

J11

K11

L10

L9

L7

L8

J6

K6

G6

H6

1. Applies to LFXP “C” only.

2. Applies to LFXP “E” only.

3. Supports dedicated LVDS outputs.

4-25

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

C2

C1

-

PROGRAMN

CCLK

7

-

PROGRAMN

CCLK

7

-

GNDIO7

PL7A

-

GNDIO7

PL7A

-

D2

D3

D1

E2

E1

F1

-

T

C

-

LUM0_PLLT_FB_A

T

C

-

LUM0_PLLT_FB_A

PL7B

LUM0_PLLC_FB_A

PL7B

LUM0_PLLC_FB_A

PL9A

-

PL9A

-

PL10B

PL11A

PL11B

GNDIO7

PL12A

PL12B

PL13A

PL13B

PL15B

GNDIO7

PL16A

PL16B

PL17A

PL17B

PL18A

PL19B

PL20A

GNDIO7

PL20B

PL22A

PL22B

VCCP0

GNDP0

PL24A

GNDIO6

PL24B

PL26A

PL27B

PL28A

PL28B

GNDIO6

PL29A

PL29B

PL30A

PL30B

-

VREF1_7

PL10B

PL11A

PL11B

GNDIO7

PL12A

PL12B

PL13A

PL13B

PL15B

GNDIO7

PL16A

PL16B

PL17A

PL17B

PL18A

PL19B

PL20A

GNDIO7

PL20B

PL22A

PL22B

VCCP0

GNDP0

PL28A

GNDIO6

PL28B

PL30A

PL31B

PL32A

PL32B

GNDIO6

PL33A

PL33B

PL34A

PL34B

-

VREF1_7

T³

C³

-

DQS

T³

C³

-

DQS

-

E3

F4

F3

F2

G1

-

T

C

T³

C³

-

T

C

T³

C³

-

G3

G2

H1

H2

G4

G5

J1

-

T

C

T³

C³

-

LUM0_PLLT_IN_A

T

C

T³

C³

-

LUM0_PLLT_IN_A

LUM0_PLLC_IN_A

-

VREF2_7

-

T³

-

T³

-

DQS

-

J2

H3

J3

H4

H5

K1

-

C³

T³

C³

-

C³

T³

C³

-

6

T

-

PCLKT6_0

6

T

-

PCLKT6_0

-

K2

J4

J5

L1

L2

-

C

-

PCLKC6_0

C

-

PCLKC6_0

-

VREF1_6

-

VREF1_6

T³

C³

-

DQS

T³

C³

-

DQS

-

M1

M2

K3

L3

T

C

T³

C³

LLM0_PLLT_IN_A

T

C

T³

C³

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

-

4-26

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

L4

-

PL32A

GNDIO6

PL33A

6

-

PL36A

GNDIO6

PL37A

6

-

K4

K5

N1

N2

P1

P2

-

T

C

-

T

C

-

PL33B

-

PL37B

-

PL35A

VREF2_6

PL39A

VREF2_6

PL36B

-

PL40B

-

PL37A

T³

C³

-

DQS

PL41A

T³

C³

-

DQS

PL37B

-

PL41B

-

GNDIO6

PL38A

-

GNDIO6

PL42A

-

L5

M6

M3

N3

-

T

C

T³

C³

-

LLM0_PLLT_FB_A

T

C

T³

C³

-

LLM0_PLLT_FB_A

PL38B

LLM0_PLLC_FB_A

PL42B

LLM0_PLLC_FB_A

PL39A

-

PL43A

-

PL39B

-

PL43B

-

GNDIO6

SLEEPN¹/TOE²

INITN

-

GNDIO6

SLEEPN¹/TOE²

INITN

-

P4

P3

-

5

-

5

-

GNDIO5

PB11A

PB11B

PB12A

GNDIO5

PB12B

PB13A

PB14B

PB15A

PB15B

PB16A

PB16B

PB17A

PB17B

PB18A

GNDIO5

PB18B

PB19A

PB19B

PB20A

PB20B

PB21A

PB22B

PB23A

-

GNDIO5

PB15A

PB15B

PB16A

GNDIO5

PB16B

PB17A

PB18B

PB19A

PB19B

PB20A

PB20B

PB21A

PB21B

PB22A

GNDIO5

PB22B

PB23A

PB23B

PB24A

PB24B

PB25A

PB26B

PB27A

-

R4

N5

P5

-

T

C

T

-

T

C

T

-

VREF1_5

-

R1

N6

M7

R2

T2

R3

T3

T4

R5

N7

-

C

-

C

-

T

C

T

C

T

C

T

-

DQS

T

C

T

C

T

C

T

-

DQS

-

VREF2_5

-

M8

T5

P6

T6

R6

P7

N8

R7

C

T

C

T

C

-

C

T

C

T

C

-

T

DQS

T

DQS

4-27

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

T7

-

PB23B

GNDIO5

PB24A

PB24B

PB25A

PB25B

PB26A

PB26B

PB27A

PB27B

GNDIO4

PB28A

PB28B

PB29A

PB30B

PB31A

PB31B

PB32A

PB32B

PB33A

GNDIO4

PB33B

PB34A

PB34B

PB35A

PB35B

PB36A

PB36B

PB37A

PB38B

GNDIO4

PB39A

PB39B

PB40A

PB40B

GNDIO4

GNDIO3

PR38B

PR38A

5

4

3

C

-

PB27B

GNDIO5

PB28A

PB28B

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

GNDIO4

PB32A

PB32B

PB33A

PB34B

PB35A

PB35B

PB36A

PB36B

PB37A

GNDIO4

PB37B

PB38A

PB38B

PB39A

PB39B

PB40A

PB40B

PB41A

PB42B

GNDIO4

PB43A

PB43B

PB44A

PB44B

GNDIO4

GNDIO3

PR42B

PR42A

5

4

3

C

-

P8

T

C

T

C

T

C

T

C

-

T

C

T

C

T

C

T

C

-

T8

-

R8

T9

-

R9

P9

-

T10

T11

-

PCLKT4_0

PCLKC4_0

-

R10

P10

N9

M9

R12

T12

P13

R13

M11

-

T

C

-

T

C

-

T

C

T

C

T

-

DQS

T

C

T

C

T

-

DQS

VREF1_4

-

N11

N10

M10

T13

P14

R11

P12

T14

R14

-

C

T

C

T

C

T

C

-

C

T

C

T

C

T

C

-

VREF2_4

-

P11

N12

T15

R15

-

T

C

T

C

-

DQS

T

C

T

C

-

DQS

-

P15

N15

C

T

RLM0_PLLC_FB_A

RLM0_PLLT_FB_A

C

T

RLM0_PLLC_FB_A

RLM0_PLLT_FB_A

4-28

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

P16

R16

M15

N14

-

PR37B

PR37A

PR36B

PR35A

GNDIO3

PR33B

PR33A

PR32B

PR32A

PR30A

PR29B

PR29A

GNDIO3

PR28B

PR28A

PR27B

PR26A

PR25B

PR25A

GNDIO3

PR23B

PR23A

GNDP1

VCCP1

GNDIO2

PR21B

PR21A

PR20B

PR20A

PR19B

PR18A

GNDIO2

PR17B

PR17A

PR16B

PR16A

PR15B

GNDIO2

PR12B

PR12A

PR11B

PR11A

3

-

C³

T³

-

PR41B

PR41A

PR40B

PR39A

GNDIO3

PR37B

PR37A

PR36B

PR36A

PR34A

PR33B

PR33A

GNDIO3

PR32B

PR32A

PR31B

PR30A

PR29B

PR29A

GNDIO3

PR27B

PR27A

GNDP1

VCCP1

GNDIO2

PR21B

PR21A

PR20B

PR20A

PR19B

PR18A

GNDIO2

PR17B

PR17A

PR16B

PR16A

PR15B

GNDIO2

PR12B

PR12A

PR11B

PR11A

3

-

C³

T³

-

DQS

-

VREF1_3

-

VREF1_3

-

M14

L13

L15

L14

L12

M16

N16

-

C

T

C³

T³

-

C

T

C³

T³

-

C

T

-

C³

T³

-

RLM0_PLLC_IN_A

C

T

-

C³

T³

-

RLM0_PLLC_IN_A

RLM0_PLLT_IN_A

-

K14

K15

K12

K13

L16

K16

-

DQS

-

VREF2_3

-

VREF2_3

C³

T³

-

C³

T³

-

C³

T³

-

C³

T³

-

J15

J14

J13

J12

-

2

-

2

-

J16

H16

H13

H12

H15

H14

-

C

T

C³

T³

-

PCLKC2_0

C

T

C³

T³

-

PCLKC2_0

PCLKT2_0

-

DQS

-

VREF1_2

-

VREF1_2

-

G15

G14

G16

F16

G13

-

C³

T³

C

T

-

C³

T³

C

T

-

RUM0_PLLC_IN_A

RUM0_PLLT_IN_A

-

G12

F13

B16

C16

C

T

C³

T³

-

C

T

C³

T³

-

DQS

4-29

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

-

GNDIO2

PR10B

PR9A

2

-

GNDIO2

PR10B

PR9A

2

-

F15

E15

F14

E14

D15

C15

-

VREF2_2

-

VREF2_2

PR8B

C³

T³

C

T

-

PR8B

C³

T³

C

T

-

PR8A

-

PR8A

-

PR7B

RUM0_PLLC_FB_A

PR7B

RUM0_PLLC_FB_A

PR7A

RUM0_PLLT_FB_A

PR7A

RUM0_PLLT_FB_A

GNDIO2

TDO

-

GNDIO2

TDO

-

E16

D16

D14

C14

B14

-

VCCJ

-

VCCJ

-

TDI

-

TDI

-

TMS

-

TMS

-

TCK

-

TCK

-

GNDIO1

PT40B

PT40A

PT39B

GNDIO1

PT39A

PT38B

PT37A

PT36B

PT36A

PT35B

PT35A

PT34B

PT34A

PT33B

PT33A

GNDIO1

PT32B

PT32A

PT31B

PT31A

PT30B

PT29A

PT28B

PT28A

GNDIO1

PT27B

1

-

GNDIO1

PT44B

PT44A

PT43B

GNDIO1

PT43A

PT42B

PT41A

PT40B

PT40A

PT39B

PT39A

PT38B

PT38A

PT37B

PT37A

GNDIO1

PT36B

PT36A

PT35B

PT35A

PT34B

PT33A

PT32B

PT32A

GNDIO1

PT31B

1

-

A15

B15

D12

-

C

T

C

-

C

T

C

-

VREF1_1

-

C11

A14

B13

F12

E11

A13

C13

C10

E10

A12

B12

-

T

-

DQS

T

-

DQS

-

C

T

C

T

C

T

C

T

-

C

T

C

T

C

T

C

T

-

D0

D1

VREF2_1

-

D2

-

D2

-

C12

A11

B11

D11

B9

C

T

C

T

-

D3

-

C

T

C

T

-

D3

-

DQS

-

DQS

-

D9

-

D4

-

D4

-

A10

B10

-

C

T

-

C

T

-

D5

-

D5

-

D10

C

D6

C

D6

4-30

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

A9

C9

C8

E9

-

PT27A

PT26B

PT26A

PT25B

GNDIO0

PT25A

PT24B

PT24A

PT23B

PT23A

PT22B

PT21A

PT20B

GNDIO0

PT20A

PT19B

PT19A

PT18B

PT18A

PT17B

PT17A

PT16B

PT16A

PT15B

PT15A

PT14B

PT13A

GNDIO0

PT12B

PT12A

PT11B

PT11A

GNDIO0

CFG0

1

0

-

T

C

T

C

-

PT31A

PT30B

PT30A

PT29B

GNDIO0

PT29A

PT28B

PT28A

PT27B

PT27A

PT26B

PT25A

PT24B

GNDIO0

PT24A

PT23B

PT23A

PT22B

PT22A

PT21B

PT21A

PT20B

PT20A

PT19B

PT19A

PT18B

PT17A

GNDIO0

PT16B

PT16A

PT15B

PT15A

GNDIO0

CFG0

1

0

-

T

C

T

C

-

D7

-

BUSY

-

B8

A8

A7

B7

C7

E8

D8

A6

-

T

C

T

C

T

-

CS1N

T

C

T

C

T

-

CS1N

PCLKC0_0

PCLKT0_0

-

DQS

-

DOUT

-

DOUT

C

-

C

-

C6

E7

D7

A5

B5

A4

B6

E6

D6

D5

A3

B3

B2

-

T

C

T

C

T

C

T

C

T

C

T

-

WRITEN

T

C

T

C

T

C

T

C

T

C

T

-

WRITEN

-

VREF1_0

-

DI

-

CSN

-

VREF2_0

DQS

-

A2

B1

F5

C5

-

C

T

C

T

-

C

T

C

T

-

C4

B4

C3

A1

A16

F11

F6

-

CFG1

-

CFG1

-

DONE

GND

-

DONE

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

4-31

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

G10

G7

G8

G9

H10

H7

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

H8

GND

-

GND

-

H9

GND

-

GND

-

J10

J7

GND

-

GND

-

GND

-

GND

-

J8

GND

-

GND

-

J9

GND

-

GND

-

K10

K7

GND

-

GND

-

GND

-

GND

-

K8

GND

-

GND

-

K9

GND

-

GND

-

L11

L6

GND

-

GND

-

GND

-

GND

-

T1

GND

-

GND

-

T16

D13

D4

GND

-

GND

-

VCC

-

VCC

-

VCC

-

VCC

-

E12

E5

VCC

-

VCC

-

VCC

-

VCC

-

M12

M5

N13

N4

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

E13

E4

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

-

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

-

M13

M4

F7

-

0

1

2

3

4

0

1

2

3

4

F8

F10

F9

G11

H11

J11

K11

L10

L9

4-32

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

L7

L8

J6

VCCIO5

VCCIO6

VCCIO7

5

6

7

-

VCCIO5

VCCIO6

VCCIO7

5

6

7

-

K6

G6

H6

1. Applies to LFXP “C” only.

2. Applies to LFXP “E” only.

3. Supports dedicated LVDS outputs.

4-33

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA

LFXP10

LFXP15

LFXP20

Ball

Number

Ball

Function

Ball

Function

Ball

Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

F4

G4

-

PROGRAMN

CCLK

7

-

PROGRAMN

CCLK

7

-

PROGRAMN

CCLK

7

-

GNDIO7

PL2A

-

GNDIO7

PL6A

-

GNDIO7

PL6A

-

D2

D1

-

T³

C³

-

T³

C³

-

T³

C³

-

PL2B

-

PL6B

-

PL6B

-

GNDIO7

PL3A

-

GNDIO7

PL7A

-

GNDIO7

PL7A

-

E2

E3

F3

F2

H4

H3

G3

G2

-

T

LUM0_PLLT_FB_A

T

LUM0_PLLT_FB_A

T

LUM0_PLLT_FB_A

PL3B

C

T³

C³

-

LUM0_PLLC_FB_A

PL7B

C

T³

C³

-

LUM0_PLLC_FB_A

PL7B

C

T³

C³

-

LUM0_PLLC_FB_A

PL4A

-

PL8A

-

PL8A

-

PL4B

-

PL8B

-

PL8B

-

PL5A

-

PL9A

-

PL9A

-

PL6B

-

VREF1_7

PL10B

PL11A

PL11B

GNDIO7

PL12A

PL12B

PL13A

PL13B

PL15A

PL15B

GNDIO7

PL16A

PL16B

PL17A

PL17B

PL18A

PL19B

PL20A

GNDIO7

PL20B

PL21A

PL21B

PL22A

PL22B

VCCP0

GNDP0

PL23A

PL23B

PL24A

GNDIO6

PL24B

PL25A

PL25B

PL26A

PL27B

PL28A

PL28B

GNDIO6

-

VREF1_7

PL10B

PL11A

PL11B

GNDIO7

PL12A

PL12B

PL13A

PL13B

PL15A

PL15B

GNDIO7

PL16A

PL16B

PL17A

PL17B

PL18A

PL19B

PL20A

GNDIO7

PL20B

PL21A

PL21B

PL22A

PL22B

VCCP0

GNDP0

PL27A

PL27B

PL28A

GNDIO6

PL28B

PL29A

PL29B

PL30A

PL31B

PL32A

PL32B

GNDIO6

-

VREF1_7

PL7A

T³

C³

-

DQS

T³

C³

-

DQS

T³

C³

-

DQS

PL7B

-

GNDIO7

PL8A

-

F1

E1

J4

K4

G1

H2

-

T

-

T

-

T

-

PL8B

C

T³

C³

T³

C³

-

C

T³

C³

T³

C³

-

C

T³

C³

T³

C³

-

PL9A

-

PL9B

-

PL11A

PL11B

GNDIO7

PL12A

PL12B

PL13A

PL13B

PL14A

PL15B

PL16A

GNDIO7

PL16B

PL17A

PL17B

PL18A

PL18B

VCCP0

GNDP0

PL19A

PL19B

PL20A

GNDIO6

PL20B

PL21A

PL21B

PL22A

PL23B

PL24A

PL24B

GNDIO6

-

J2

H1

J1

K2

K3

J3

K1

-

T

LUM0_PLLT_IN_A

T

LUM0_PLLT_IN_A

T

LUM0_PLLT_IN_A

C

T³

C³

-

LUM0_PLLC_IN_A

C

T³

C³

-

LUM0_PLLC_IN_A

C

T³

C³

-

LUM0_PLLC_IN_A

-

VREF2_7

-

T³

-

T³

-

T³

-

DQS

-

L2

L3

L4

L1

M1

M2

N1

M3

M4

P1

-

C³

T

-

C³

T

-

C³

T

-

C

T³

C³

-

C

T³

C³

-

C

T³

C³

-

6

T³

C³

T

-

6

T³

C³

T

-

6

T³

C³

T

-

PCLKT6_0

-

N2

R1

P2

N3

N4

T1

R2

-

C

T³

C³

-

PCLKC6_0

C

T³

C³

-

PCLKC6_0

C

T³

C³

-

PCLKC6_0

-

VREF1_6

-

VREF1_6

-

VREF1_6

T³

C³

-

DQS

T³

C³

-

DQS

T³

C³

-

DQS

-

4-34

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)

LFXP10

LFXP15

LFXP20

Ball

Number

Ball

Function

Ball

Function

Ball

Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

U1

T2

V1

U2

W1

V2

-

PL25A

PL25B

PL26A

PL26B

PL28A

PL28B

GNDIO6

PL29A

PL29B

PL30A

PL30B

PL31A

PL32B

PL33A

PL33B

GNDIO6

PL34A

PL34B

PL35A

PL35B

GNDIO6

6

T

C

T³

C³

T³

C³

-

LLM0_PLLT_IN_A

PL29A

PL29B

PL30A

PL30B

PL32A

PL32B

GNDIO6

PL33A

PL33B

PL34A

PL34B

PL35A

PL36B

PL37A

PL37B

GNDIO6

PL38A

PL38B

PL39A

PL39B

GNDIO6

6

-

T

C

T³

C³

T³

C³

-

LLM0_PLLT_IN_A

PL33A

PL33B

PL34A

PL34B

PL36A

PL36B

GNDIO6

PL37A

PL37B

PL38A

PL38B

PL39A

PL40B

PL41A

PL41B

GNDIO6

PL42A

PL42B

PL43A

PL43B

GNDIO6

6

T

C

T³

C³

T³

C³

-

LLM0_PLLT_IN_A

LLM0_PLLC_IN_A

-

P3

P4

Y1

W2

R3

R4

T3

T4

-

T

-

6

T

-

T

-

C

T³

C³

-

C

T³

C³

-

C

T³

C³

-

VREF2_6

-

T³

C³

-

DQS

T³

C³

-

DQS

T³

C³

-

DQS

-

V4

V3

U4

U3

-

T

LLM0_PLLT_FB_A

T

LLM0_PLLT_FB_A

T

LLM0_PLLT_FB_A

C

T³

C³

-

LLM0_PLLC_FB_A

C

T³

C³

-

LLM0_PLLC_FB_A

C

T³

C³

-

LLM0_PLLC_FB_A

-

SLEEPN¹/

TOE²

W5

-

Y2

-

INITN

GNDIO5

-

5

-

INITN

GNDIO5

PB3B

5

-

INITN

GNDIO5

PB7B

5

-

Y3

-

W3

W4

AA2

AA1

W6

W7

Y4

-

PB4A

T

C

-

PB8A

T

C

-

PB4B

-

PB8B

-

PB5A

-

PB9A

-

PB6B

-

PB10B

PB11A

PB11B

PB12A

GNDIO5

PB12B

PB13A

PB13B

PB14A

PB14B

PB15A

PB15B

PB16A

GNDIO5

PB16B

PB17A

PB18B

PB19A

PB19B

PB20A

-

PB2A

-

5

-

PB7A

T

C

T

-

DQS

T

C

T

-

DQS

-

PB7B

-

PB3A

GNDIO5

PB3B

PB4A

PB4B

PB5A

PB5B

PB6A

PB6B

PB7A

GNDIO5

PB7B

PB8A

PB9B

PB10A

PB10B

PB11A

5

T

-

PB8A

-

GNDIO5

PB8B

-

Y5

C

T

C

T

C

T

C

T

-

C

T

C

T

C

T

C

T

-

C

T

C

T

C

T

C

T

-

AB2

AA3

AB3

AA4

W8

W9

AB4

-

PB9A

-

PB9B

-

PB10A

PB10B

PB11A

PB11B

PB12A

GNDIO5

PB12B

PB13A

PB14B

PB15A

PB15B

PB16A

-

VREF1_5

-

AA5

AB5

Y6

C

-

C

-

C

-

AA6

AB6

Y9

T

C

T

DQS

T

C

T

DQS

T

C

T

DQS

-

4-35

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)

LFXP10

LFXP15

LFXP20

Ball

Number

Ball

Function

Ball

Function

Ball

Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Y10

AA7

AB7

Y7

PB11B

PB12A

PB12B

PB13A

GNDIO5

PB13B

PB14A

PB14B

PB15A

PB15B

PB16A

PB17B

PB18A

PB18B

GNDIO5

PB19A

PB19B

PB20A

PB20B

PB21A

PB21B

PB22A

PB22B

GNDIO4

PB23A

PB23B

PB24A

PB25B

PB26A

PB26B

PB27A

PB27B

PB28A

GNDIO4

PB28B

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

PB32A

PB33B

GNDIO4

PB34A

PB34B

PB35A

PB35B

PB36A

5

4

C

T

C

T

-

PB16B

PB17A

PB17B

PB18A

GNDIO5

PB18B

PB19A

PB19B

PB20A

PB20B

PB21A

PB22B

PB23A

PB23B

GNDIO5

PB24A

PB24B

PB25A

PB25B

PB26A

PB26B

PB27A

PB27B

GNDIO4

PB28A

PB28B

PB29A

PB30B

PB31A

PB31B

PB32A

PB32B

PB33A

GNDIO4

PB33B

PB34A

PB34B

PB35A

PB35B

PB36A

PB36B

PB37A

PB38B

GNDIO4

PB39A

PB39B

PB40A

PB40B

PB41A

5

4

C

T

C

T

-

PB20B

PB21A

PB21B

PB22A

GNDIO5

PB22B

PB23A

PB23B

PB24A

PB24B

PB25A

PB26B

PB27A

PB27B

GNDIO5

PB28A

PB28B

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

GNDIO4

PB32A

PB32B

PB33A

PB34B

PB35A

PB35B

PB36A

PB36B

PB37A

GNDIO4

PB37B

PB38A

PB38B

PB39A

PB39B

PB40A

PB40B

PB41A

PB42B

GNDIO4

PB43A

PB43B

PB44A

PB44B

PB45A

5

4

C

T

C

T

-

VREF2_5

-

AA8

AB8

Y8

C

T

C

T

C

-

C

T

C

T

C

-

C

T

C

T

C

-

AB9

AA9

W10

W11

AB10

AA10

-

T

C

-

DQS

T

C

-

DQS

T

C

-

DQS

-

AA11

AB11

Y11

Y12

AB12

AA12

AB13

AA13

-

T

C

T

C

T

C

T

C

-

T

C

T

C

T

C

T

C

-

T

C

T

C

T

C

T

C

-

PCLKT4_0

PCLKC4_0

-

AA14

AB14

W12

W13

AA15

AB15

AA16

AB16

Y17

-

T

C

-

T

C

-

T

C

-

T

C

T

C

T

-

DQS

T

C

T

C

T

-

DQS

T

C

T

C

T

-

DQS

VREF1_4

-

AA17

Y13

Y14

AB17

Y18

AA18

AB18

Y19

AB19

-

C

T

C

T

C

T

C

-

C

T

C

T

C

T

C

-

C

T

C

T

C

T

C

-

VREF2_4

-

AA19

Y20

W14

W15

AB20

T

C

T

C

T

DQS

T

C

T

C

T

DQS

T

C

T

C

T

DQS

-

4-36

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)

LFXP10

LFXP15

LFXP20

Ball

Number

Ball

Function

Ball

Function

Ball

Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

AA20

AB21

AA21

AA22

Y21

-

PB36B

PB37A

PB37B

PB38A

PB38B

GNDIO4

PB39A

-

4

-

C

T

C

T

C

-

PB41B

PB42A

PB42B

PB43A

PB43B

GNDIO4

PB44A

PB44B

PB45A

PB46B

PB47A

PB47B

PB48A

GNDIO4

GNDIO3

PR39B

PR39A

GNDIO3

PR38B

PR38A

PR37B

PR37A

PR36B

PR35A

PR34B

PR34A

GNDIO3

PR33B

PR33A

PR32B

PR32A

PR30B

PR30A

PR29B

PR29A

GNDIO3

PR28B

PR28A

PR27B

PR26A

PR25B

PR25A

PR24B

PR24A

GNDIO3

PR23B

PR23A

GNDP1

4

3

-

C

T

C

T

C

-

PB45B

PB46A

PB46B

PB47A

PB47B

GNDIO4

PB48A

PB48B

PB49A

PB50B

PB51A

PB51B

PB52A

GNDIO4

GNDIO3

PR43B

PR43A

GNDIO3

PR42B

PR42A

PR41B

PR41A

PR40B

PR39A

PR38B

PR38A

GNDIO3

PR37B

PR37A

PR36B

PR36A

PR34B

PR34A

PR33B

PR33A

GNDIO3

PR32B

PR32A

PR31B

PR30A

PR29B

PR29A

PR28B

PR28A

GNDIO3

PR27B

PR27A

GNDP1

4

3

-

C

T

C

T

C

-

W16

W17

Y15

Y16

W19

W18

W20

-

T

C

-

T

C

-

T

C

-

DQS

T

C

-

DQS

-

GNDIO4

GNDIO3

PR35B

PR35A

GNDIO3

PR34B

PR34A

PR33B

PR33A

PR32B

PR31A

PR30B

PR30A

GNDIO3

PR29B

PR29A

PR28B

PR28A

PR26B

PR26A

PR25B

PR25A

GNDIO3

PR24B

PR24A

PR23B

PR22A

PR21B

PR21A

PR20B

PR20A

GNDIO3

PR19B

PR19A

GNDP1

4

3

-

T20

T19

-

C³

T³

-

C³

T³

-

C³

T³

-

U19

U20

V19

V20

R19

R20

W21

Y22

-

C

T

C³

T³

-

RLM0_PLLC_FB_A

C

T

C³

T³

-

RLM0_PLLC_FB_A

C

T

C³

T³

-

RLM0_PLLC_FB_A

RLM0_PLLT_FB_A

-

DQS

-

VREF1_3

-

VREF1_3

-

VREF1_3

C³

T³

-

C³

T³

-

C³

T³

-

P19

P20

V21

W22

U21

V22

T21

U22

-

C

T

C³

T³

C³

T³

C

T

-

C

T

C³

T³

C³

T³

C

T

-

C

T

C³

T³

C³

T³

C

T

-

RLM0_PLLC_IN_A

RLM0_PLLT_IN_A

-

R21

T22

N19

N20

R22

P22

P21

N21

-

C³

T³

-

C³

T³

-

C³

T³

-

DQS

-

VREF2_3

-

VREF2_3

-

VREF2_3

C³

T³

C

T

-

C³

T³

-

C³

T³

C

T

-

C³

T³

-

C³

T³

C

T

-

C³

T³

-

M20

M19

N22

4-37

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)

LFXP10

LFXP15

LFXP20

Ball

Number

Ball

Function

Ball

Function

Ball

Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

M21

-

VCCP1

GNDIO2

PR18B

PR18A

PR17B

PR17A

PR16B

PR16A

PR15B

PR14A

GNDIO2

PR13B

PR13A

PR12B

PR12A

PR11B

PR11A

GNDIO2

PR9B

PR9A

PR8B

PR8A

PR7B

PR7A

GNDIO2

PR6B

PR5A

PR4B

PR4A

PR3B

PR3A

PR2B

PR2A

GNDIO2

TDO

-

VCCP1

GNDIO2

PR22B

PR22A

PR21B

PR21A

PR20B

PR20A

PR19B

PR18A

GNDIO2

PR17B

PR17A

PR16B

PR16A

PR15B

PR15A

GNDIO2

PR13B

PR13A

PR12B

PR12A

PR11B

PR11A

GNDIO2

PR10B

PR9A

-

VCCP1

GNDIO2

PR22B

PR22A

PR21B

PR21A

PR20B

PR20A

PR19B

PR18A

GNDIO2

PR17B

PR17A

PR16B

PR16A

PR15B

PR15A

GNDIO2

PR13B

PR13A

PR12B

PR12A

PR11B

PR11A

GNDIO2

PR10B

PR9A

-

2

-

2

-

2

-

M22

L22

K22

K21

L19

K20

L20

L21

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

PCLKC2_0

PCLKT2_0

-

DQS

-

VREF1_2

-

VREF1_2

-

VREF1_2

-

J22

J21

H22

H21

K19

J19

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

RUM0_PLLC_IN_A

RUM0_PLLT_IN_A

-

J20

H20

H19

G19

G22

G21

-

DQS

-

F20

G20

F22

F21

E22

E21

D22

D21

-

VREF2_2

-

VREF2_2

-

VREF2_2

C³

T³

C

T

C³

T³

-

PR8B

C³

T³

C

T

C³

T³

-

PR8B

C³

T³

C

T

C³

T³

-

PR8A

-

PR8A

-

RUM0_PLLC_FB_A

PR7B

RUM0_PLLC_FB_A

PR7B

RUM0_PLLC_FB_A

RUM0_PLLT_FB_A

PR7A

RUM0_PLLT_FB_A

PR7A

RUM0_PLLT_FB_A

-

PR6B

-

PR6B

-

PR6A

-

PR6A

-

GNDIO2

TDO

-

GNDIO2

TDO

-

F19

E20

D20

D19

D18

-

VCCJ

TDI

-

VCCJ

-

VCCJ

-

TDI

-

TDI

-

TMS

-

TMS

-

TMS

-

TCK

-

TCK

-

TCK

-

GNDIO1

-

1

-

GNDIO1

PT48A

PT47B

PT47A

PT46B

PT45A

PT44B

PT44A

PT43B

GNDIO1

1

-

GNDIO1

PT52A

PT51B

PT51A

PT50B

PT49A

PT48B

PT48A

PT47B

GNDIO1

1

-

E19

D17

D16

C16

C15

C17

C18

C19

-

C

T

-

C

T

-

DQS

-

C

T

C

-

C

T

C

-

PT39A

PT38B

GNDIO1

1

-

C

-

4-38

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)

LFXP10

LFXP15

LFXP20

Ball

Number

Ball

Function

Ball

Function

Ball

Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

C20

C21

C22

B22

A21

D15

D14

B21

-

PT38A

PT37B

PT37A

PT36B

PT36A

PT35B

PT35A

PT34B

GNDIO1

PT34A

PT33B

PT32A

PT31B

PT31A

PT30B

PT30A

PT29B

PT29A

PT28B

PT28A

GNDIO1

PT27B

PT27A

PT26B

PT26A

PT25B

PT24A

PT23B

PT23A

GNDIO1

PT22B

PT22A

PT21B

PT21A

PT20B

GNDIO0

PT20A

PT19B

PT19A

PT18B

PT18A

PT17B

PT16A

PT15B

GNDIO0

PT15A

PT14B

PT14A

PT13B

1

0

T

C

T

C

T

C

T

C

-

PT43A

PT42B

PT42A

PT41B

PT41A

PT40B

PT40A

PT39B

GNDIO1

PT39A

PT38B

PT37A

PT36B

PT36A

PT35B

PT35A

PT34B

PT34A

PT33B

PT33A

GNDIO1

PT32B

PT32A

PT31B

PT31A

PT30B

PT29A

PT28B

PT28A

GNDIO1

PT27B

PT27A

PT26B

PT26A

PT25B

GNDIO0

PT25A

PT24B

PT24A

PT23B

PT23A

PT22B

PT21A

PT20B

GNDIO0

PT20A

PT19B

PT19A

PT18B

1

0

T

C

T

C

T

C

T

C

-

PT47A

PT46B

PT46A

PT45B

PT45A

PT44B

PT44A

PT43B

GNDIO1

PT43A

PT42B

PT41A

PT40B

PT40A

PT39B

PT39A

PT38B

PT38A

PT37B

PT37A

GNDIO1

PT36B

PT36A

PT35B

PT35A

PT34B

PT33A

PT32B

PT32A

GNDIO1

PT31B

PT31A

PT30B

PT30A

PT29B

GNDIO0

PT29A

PT28B

PT28A

PT27B

PT27A

PT26B

PT25A

PT24B

GNDIO0

PT24A

PT23B

PT23A

PT22B

1

0

T

C

T

C

T

C

T

C

-

VREF1_1

-

A20

B20

A19

B19

A18

C14

C13

B18

A17

B17

A16

-

T

-

DQS

T

-

DQS

T

-

DQS

-

C

T

C

T

C

T

C

T

-

C

T

C

T

C

T

C

T

-

C

T

C

T

C

T

C

T

-

D0

D1

VREF2_1

-

D2

-

B16

A15

B15

A14

D13

D12

B14

A13

-

C

T

C

T

-

D3

C

T

C

T

-

D3

C

T

C

T

-

D3

-

DQS

-

D4

-

D4

-

D4

C

T

-

C

T

-

C

T

-

D5

-

B13

A12

B12

C12

C11

-

C

T

C

T

C

-

D6

C

T

C

T

C

-

D6

C

T

C

T

C

-

D6

-

D7

-

BUSY

-

B11

A11

A10

B10

B9

T

C

T

C

T

-

CS1N

T

C

T

C

T

-

CS1N

T

C

T

C

T

-

CS1N

PCLKC0_0

PCLKT0_0

-

DQS

D11

D10

A9

-

DOUT

-

DOUT

-

DOUT

C

-

C

-

C

-

C8

T

C

T

C

WRITEN

T

C

T

C

WRITEN

T

C

T

C

WRITEN

B8

-

A8

VREF1_0

-

VREF1_0

-

VREF1_0

-

C7

4-39

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)

LFXP10

LFXP15

LFXP20

Ball

Number

Ball

Function

Ball

Function

Ball

Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

A7

B7

PT13A

PT12B

PT12A

PT11B

PT11A

PT10B

PT10A

PT9B

PT8A

GNDIO0

PT7B

PT7A

PT6B

PT6A

PT5B

PT5A

PT4B

PT4A

PT3B

PT3A

GNDIO0

-

0

-

T

C

T

C

T

C

T

-

DI

PT18A

PT17B

PT17A

PT16B

PT16A

PT15B

PT15A

PT14B

PT13A

GNDIO0

PT12B

PT12A

PT11B

PT11A

PT10B

PT10A

PT9B

PT9A

PT8B

PT8A

GNDIO0

PT7B

PT7A

PT6B

PT5A

PT4B

PT4A

PT3B

GNDIO0

CFG0

CFG1

DONE

GND

0

-

T

C

T

C

T

C

T

-

DI

PT22A

PT21B

PT21A

PT20B

PT20A

PT19B

PT19A

PT18B

PT17A

GNDIO0

PT16B

PT16A

PT15B

PT15A

PT14B

PT14A

PT13B

PT13A

PT12B

PT12A

GNDIO0

PT11B

PT11A

PT10B

PT9A

0

-

T

C

T

C

T

C

T

-

DI

-

C6

C10

C9

A6

CSN

-

VREF2_0

B6

DQS

A5

-

B5

-

C5

A4

C

T

C

T

C

T

C

T

C

T

-

C

T

C

T

C

T

C

T

C

T

-

C

T

C

T

C

T

C

T

C

T

-

D9

D8

B4

-

A2

-

A3

-

B3

-

C4

C3

-

C2

D3

D7

D6

E4

-

C

T

-

C

T

-

PT2A

-

0

-

DQS

-

C

T

-

PT8B

C

T

-

D4

D5

-

PT8A

-

PT7B

GNDIO0

CFG0

CFG1

DONE

GND

0

-

GNDIO0

CFG0

CFG1

DONE

GND

-

C1

B2

-

B1

-

A1

-

A22

AB1

AB22

H10

H11

H12

H13

H14

J10

J11

J12

J13

J14

J9

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

K10

-

GND

-

GND

-

4-40

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)

LFXP10

LFXP15

LFXP20

Ball

Number

Ball

Function

Ball

Function

Ball

Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

K11

K12

K13

K14

K9

GND

VCC

VCCAUX

-

GND

VCC

VCCAUX

-

GND

VCC

VCCAUX

-

L10

L11

L12

L13

L14

L9

M10

M11

M12

M13

M14

M9

N10

N11

N12

N13

N14

N9

P10

P11

P12

P13

P14

P9

R10

R11

R12

R13

R14

H9

J15

J8

K15

K8

L15

L8

M15

M8

N15

N8

P15

P8

R9

G16

4-41

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA (Cont.)

LFXP10

LFXP15

LFXP20

Ball

Number

Ball

Function

Ball

Function

Ball

Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

Bank Diff.

Dual Function

G7

T16

T7

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

-

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

-

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

-

G10

G11

G8

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

G9

H8

G12

G13

G14

G15

H15

H16

J16

K16

L16

M16

N16

P16

R16

R15

T12

T13

T14

T15

R8

T10

T11

T8

T9

M7

N7

P7

R7

H7

J7

K7

L7

1. Applies to LFXP “C” only.

2. Applies to LFXP “E” only.

3. Supports dedicated LVDS outputs.

4-42

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

F5

E3

C1

-

PROGRAMN

CCLK

7

-

PROGRAMN

CCLK

7

-

PL2B

-

PL2B

-

GNDIO7

PL3A

-

GNDIO7

PL3A

-

G5

G6

F4

F3

G4

G3

D1

D2

-

T³

C³

T

-

T³

C³

T

-

PL3B

-

PL3B

-

PL4A

-

PL4A

-

PL4B

C

T³

C³

T³

C³

-

PL4B

C

T³

C³

T³

C³

-

PL5A

-

PL5A

-

PL5B

-

PL5B

-

PL6A

-

PL6A

-

PL6B

-

PL6B

-

GNDIO7

PL7A

-

GNDIO7

PL7A

-

E1

E2

H5

H6

H4

H3

F1

F2

-

T

LUM0_PLLT_FB_A

T

LUM0_PLLT_FB_A

PL7B

C

T³

C³

-

LUM0_PLLC_FB_A

PL7B

C

T³

C³

-

LUM0_PLLC_FB_A

PL8A

-

PL8A

-

PL8B

-

PL8B

-

PL9A

-

PL9A

-

PL10B

PL11A

PL11B

GNDIO7

PL12A

PL12B

PL13A

PL13B

PL15A

PL15B

GNDIO7

PL16A

PL16B

PL17A

PL17B

PL18A

PL19B

PL20A

GNDIO7

PL20B

PL21A

PL21B

PL22A

PL22B

-

VREF1_7

PL10B

PL11A

PL11B

GNDIO7

PL12A

PL12B

PL13A

PL13B

PL15A

PL15B

GNDIO7

PL16A

PL16B

PL17A

PL17B

PL18A

PL19B

PL20A

GNDIO7

PL20B

PL21A

PL21B

PL22A

PL22B

-

VREF1_7

T³

C³

-

DQS

T³

C³

-

DQS

-

J5

J6

G1

G2

J4

J3

-

T

-

T

-

C

T³

C³

T³

C³

-

C

T³

C³

T³

C³

-

H1

H2

J1

J2

K3

K2

K4

-

T

LUM0_PLLT_IN_A

T

LUM0_PLLT_IN_A

C

T³

C³

-

LUM0_PLLC_IN_A

C

T³

C³

-

LUM0_PLLC_IN_A

-

VREF2_7

-

T³

-

T³

-

DQS

-

K5

K1

L2

L4

L3

C³

T

C³

T

C

T³

C³

C

T³

C³

4-43

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

L1

M1

M2

L5

N2

N1

P2

P1

M4

M3

R2

-

PL23A

PL23B

PL24A

VCCP0

GNDP0

PL25B

PL26A

PL26B

PL27A

PL27B

PL28A

GNDIO6

PL28B

PL29A

PL29B

PL30A

PL31B

PL32A

PL32B

GNDIO6

PL33A

PL33B

PL34A

PL34B

PL36A

PL36B

GNDIO6

PL37A

PL37B

PL38A

PL38B

PL39A

PL40B

PL41A

PL41B

GNDIO6

PL42A

PL42B

PL43A

PL43B

PL44A

PL44B

7

-

T³

C³

-

VCCP0

GNDP0

-

6

-

T³

C³

T³

C³

T

-

PL23A

PL23B

PL24A

GNDIO6

PL24B

PL25A

PL25B

PL26A

PL27B

PL28A

PL28B

GNDIO6

PL29A

PL29B

PL30A

PL30B

PL32A

PL32B

GNDIO6

PL33A

PL33B

PL34A

PL34B

PL35A

PL36B

PL37A

PL37B

GNDIO6

PL38A

PL38B

PL39A

PL39B

PL40A

PL40B

6

T³

C³

T

-

PCLKT6_0

-

R1

N3

N4

M5

N5

T2

T1

-

C

T³

C³

-

PCLKC6_0

C

T³

C³

-

PCLKC6_0

-

VREF1_6

-

VREF1_6

T³

C³

-

DQS

T³

C³

-

DQS

-

U2

U1

P3

P4

P6

P5

-

T

LLM0_PLLT_IN_A

T

LLM0_PLLT_IN_A

C

T³

C³

T³

C³

-

LLM0_PLLC_IN_A

C

T³

C³

T³

C³

-

LLM0_PLLC_IN_A

-

V2

V1

W2

W1

R3

R4

R6

R5

-

T

-

T

-

C

T³

C³

-

C

T³

C³

-

VREF2_6

-

T³

C³

-

DQS

T³

C³

-

DQS

-

Y2

Y1

T3

T4

W3

V3

T

LLM0_PLLT_FB_A

T

LLM0_PLLT_FB_A

C

T³

C³

T³

C³

LLM0_PLLC_FB_A

C

T³

C³

T³

C³

LLM0_PLLC_FB_A

-

4-44

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

T6

T5

-

PL41A

PL41B

GNDIO6

PL42A

PL42B

PL43A

6

T

C

-

T³

C³

-

PL45A

PL45B

GNDIO6

PL46A

PL46B

PL47A

6

T

C

-

T³

C³

-

U3

U4

V4

SLEEPN¹/

W4

-

TOE²

W5

Y3

-

INITN

-

5

-

INITN

PB3B

5

-

GNDIO5

-

5

-

GNDIO5

PB4A

-

U5

V5

Y4

Y5

V6

-

T

C

T

C

T

-

PB4B

-

PB5A

-

PB5B

-

PB6A

-

GNDIO5

-

5

-

GNDIO5

PB6B

-

U6

W6

Y6

AA2

AA3

V7

U7

Y7

W7

AA4

-

C

T

C

T

C

-

PB3A

PB3B

PB4A

PB4B

PB5A

PB6B

PB7A

PB7B

PB8A

GNDIO5

PB8B

PB9A

PB9B

PB10A

PB10B

PB11A

PB11B

PB12A

GNDIO5

PB12B

PB13A

PB14B

PB15A

PB15B

5

T

C

T

C

-

PB7A

-

PB7B

-

PB8A

-

PB8B

-

PB9A

-

PB10B

PB11A

PB11B

PB12A

GNDIO5

PB12B

PB13A

PB13B

PB14A

PB14B

PB15A

PB15B

PB16A

GNDIO5

PB16B

PB17A

PB18B

PB19A

PB19B

-

T

C

T

-

DQS

T

C

T

-

DQS

-

AA5

AB3

AB4

AA6

AA7

U8

V8

Y8

-

C

T

C

T

C

T

C

T

-

C

T

C

T

C

T

C

T

-

VREF1_5

-

W8

V9

U9

Y9

W9

C

-

C

-

DQS

-

DQS

-

T

C

T

C

4-45

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

AB5

AB6

AA8

AA9

W10

-

PB16A

PB16B

PB17A

PB17B

PB18A

GNDIO5

PB18B

PB19A

PB19B

PB20A

PB20B

PB21A

PB22B

PB23A

PB23B

GNDIO5

PB24A

PB24B

PB25A

PB25B

PB26A

PB26B

PB27A

PB27B

GNDIO4

PB28A

PB28B

PB29A

PB30B

PB31A

PB31B

PB32A

PB32B

PB33A

GNDIO4

PB33B

PB34A

PB34B

PB35A

PB35B

PB36A

PB36B

5

4

T

C

T

C

T

-

PB20A

PB20B

PB21A

PB21B

PB22A

GNDIO5

PB22B

PB23A

PB23B

PB24A

PB24B

PB25A

PB26B

PB27A

PB27B

GNDIO5

PB28A

PB28B

PB29A

PB29B

PB30A

PB30B

PB31A

PB31B

GNDIO4

PB32A

PB32B

PB33A

PB34B

PB35A

PB35B

PB36A

PB36B

PB37A

GNDIO4

PB37B

PB38A

PB38B

PB39A

PB39B

PB40A

PB40B

5

4

T

C

T

C

T

-

VREF2_5

-

V10

AB7

AB8

AB9

AB10

Y10

AA10

W11

V11

-

C

T

C

T

C

-

C

T

C

T

C

-

T

C

-

DQS

T

C

-

DQS

-

Y11

AA11

AB11

AB12

Y12

AA12

W12

V12

-

T

C

T

C

T

C

T

C

-

T

C

T

C

T

C

T

C

-

PCLKT4_0

PCLKC4_0

-

AB13

AB14

AA13

Y13

AB15

AB16

V13

W13

AA14

-

T

C

-

T

C

-

T

C

T

C

T

-

DQS

T

C

T

C

T

-

DQS

VREF1_4

-

AA15

AB17

AB18

W14

Y14

U14

V14

C

T

C

T

C

T

C

-

C

T

C

T

C

T

C

-

VREF2_4

-

VREF2_4

-

4-46

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

AB19

AB20

-

PB37A

PB38B

GNDIO4

PB39A

PB39B

PB40A

PB40B

PB41A

PB41B

PB42A

PB42B

PB43A

PB43B

GNDIO4

PB44A

PB44B

PB45A

PB46B

PB47A

PB47B

PB48A

PB48B

GNDIO4

-

4

-

PB41A

PB42B

GNDIO4

PB43A

PB43B

PB44A

PB44B

PB45A

PB45B

PB46A

PB46B

PB47A

PB47B

GNDIO4

PB48A

PB48B

PB49A

PB50B

PB51A

PB51B

PB52A

PB52B

GNDIO4

PB53A

PB53B

PB54A

PB54B

PB55A

PB55B

GNDIO4

PB56A

GNDIO3

PR47A

PR46B

PR46A

PR45B

PR45A

PR44B

PR44A

PR43B

PR43A

GNDIO3

4

3

-

V15

U15

Y15

W15

AA16

AA17

AA18

AA19

Y16

W16

-

T

C

T

C

T

C

T

C

T

C

-

DQS

T

C

T

C

T

C

T

C

T

C

-

DQS

-

AA20

AA21

Y17

Y18

Y19

Y20

V16

U16

-

T

C

-

T

C

-

T

C

T

C

-

DQS

T

C

T

C

-

DQS

-

U18

V18

W19

W18

U17

V17

-

T

C

T

C

T

C

-

GNDIO4

-

4

-

W17

-

GNDIO3

PR43A

PR42B

PR42A

PR41B

PR41A

PR40B

PR40A

PR39B

PR39A

GNDIO3

3

-

V19

U20

U19

V20

W20

T17

T18

T19

T20

-

C³

T³

C

T

C³

T³

C³

T³

-

C³

T³

C

T

C³

T³

C³

T³

-

4-47

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

R18

R17

Y22

Y21

W22

W21

P17

P18

-

PR38B

PR38A

PR37B

PR37A

PR36B

PR35A

PR34B

PR34A

GNDIO3

PR33B

PR33A

PR32B

PR32A

PR30B

PR30A

PR29B

PR29A

GNDIO3

PR28B

PR28A

PR27B

PR26A

PR25B

PR25A

PR24B

PR24A

GNDIO3

PR23B

PR23A

-

3

-

C

T

C³

T³

-

RLM0_PLLC_FB_A

PR42B

PR42A

PR41B

PR41A

PR40B

PR39A

PR38B

PR38A

GNDIO3

PR37B

PR37A

PR36B

PR36A

PR34B

PR34A

PR33B

PR33A

GNDIO3

PR32B

PR32A

PR31B

PR30A

PR29B

PR29A

PR28B

PR28A

GNDIO3

PR27B

PR27A

PR26B

PR26A

PR25B

GNDP1

VCCP1

PR24A

PR23B

PR23A

GNDIO2

PR22B

PR22A

PR21B

PR21A

3

-

C

RLM0_PLLC_FB_A

RLM0_PLLT_FB_A

T

RLM0_PLLT_FB_A

-

C³

T³

-

DQS

-

VREF1_3

-

VREF1_3

C³

T³

-

C³

T³

-

R19

R20

V22

V21

U22

U21

P19

P20

-

C

T

C³

T³

C³

T³

C

T

-

C

T

-

C³

T³

C³

T³

C

T

-

RLM0_PLLC_IN_A

RLM0_PLLT_IN_A

-

T22

T21

R22

R21

N19

N20

N18

M18

-

C³

T³

-

C³

T³

-

DQS

-

VREF2_3

-

VREF2_3

C³

T³

C

T

-

C³

T³

-

C³

T³

C

T

-

P22

P21

N22

N21

M19

M20

L18

M21

M22

L22

-

C³

T³

C³

T³

-

GNDP1

VCCP1

-

2

-

PR22B

PR22A

GNDIO2

-

2

-

C³

T³

-

C³

T³

-

C³

T³

C

T

-

L19

L20

L21

K22

-

PR21B

PR21A

2

C

T

PCLKC2_0

PCLKT2_0

PCLKC2_0

PCLKT2_0

4-48

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

J21

J22

K18

K19

-

PR20B

PR20A

PR19B

PR18A

GNDIO2

PR17B

PR17A

PR16B

PR16A

PR15B

PR15A

GNDIO2

PR13B

PR13A

PR12B

PR12A

PR11B

PR11A

GNDIO2

PR10B

PR9A

2

-

C³

T³

-

PR20B

PR20A

PR19B

PR18A

GNDIO2

PR17B

PR17A

PR16B

PR16A

PR15B

PR15A

GNDIO2

PR13B

PR13A

PR12B

PR12A

PR11B

PR11A

GNDIO2

PR10B

PR9A

2

-

C³

T³

-

DQS

-

VREF1_2

-

VREF1_2

-

K21

K20

H21

H22

J20

J19

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

C³

T³

C

T

C³

T³

-

RUM0_PLLC_IN_A

RUM0_PLLT_IN_A

-

J17

J18

G21

G22

F21

F22

-

DQS

-

H20

H19

H17

H18

E21

E22

D21

D22

G20

G19

G17

G18

-

VREF2_2

-

VREF2_2

PR8B

C³

T³

C

T

C³

T³

C³

T³

C

T

-

PR8B

C³

T³

C

T

C³

T³

C³

T³

C

T

-

PR8A

-

PR8A

-

PR7B

RUM0_PLLC_FB_A

PR7B

RUM0_PLLC_FB_A

PR7A

RUM0_PLLT_FB_A

PR7A

RUM0_PLLT_FB_A

PR6B

-

PR6B

-

PR6A

PR5B

PR5A

PR4B

PR4A

GNDIO2

PR3B

-

GNDIO2

PR3B

-

F18

F19

C22

F20

E20

D19

E19

D20

C20

-

C³

T³

-

C³

T³

-

PR3A

PR2B

TDO

-

TDO

-

VCCJ

-

VCCJ

-

TDI

-

TDI

-

TMS

-

TMS

-

TCK

-

TCK

-

PT56A

GNDIO1

1

-

GNDIO1

1

-

4-49

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

D18

E18

C19

C18

C21

-

PT55B

PT55A

PT54B

PT54A

PT53B

GNDIO1

PT53A

PT52B

PT52A

PT51B

PT51A

PT50B

PT49A

PT48B

PT48A

PT47B

GNDIO1

PT47A

PT46B

PT46A

PT45B

PT45A

PT44B

PT44A

PT43B

GNDIO1

PT43A

PT42B

PT41A

PT40B

PT40A

PT39B

PT39A

PT38B

PT38A

PT37B

PT37A

GNDIO1

PT36B

PT36A

PT35B

PT35A

1

C

T

C

T

C

-

GNDIO1

-

1

-

B21

E17

E16

C17

D17

F17

F16

C16

D16

A20

-

T

C

T

C

T

-

PT48B

PT48A

PT47B

PT47A

PT46B

PT45A

PT44B

PT44A

PT43B

GNDIO1

PT43A

PT42B

PT42A

PT41B

PT41A

PT40B

PT40A

PT39B

GNDIO1

PT39A

PT38B

PT37A

PT36B

PT36A

PT35B

PT35A

PT34B

PT34A

PT33B

PT33A

GNDIO1

PT32B

PT32A

PT31B

PT31A

1

C

T

C

T

-

DQS

-

C

T

C

-

C

T

C

-

B20

A19

B19

C15

D15

A18

B18

F15

-

T

C

T

C

T

C

T

C

-

T

C

T

C

T

C

T

C

-

VREF1_1

-

E15

A17

B17

E14

F14

D14

C14

A16

B16

A15

B15

-

T

-

DQS

T

-

DQS

-

C

T

C

T

C

T

C

T

-

C

T

C

T

C

T

C

T

-

D0

D1

VREF2_1

-

D2

-

D2

-

E13

D13

C13

B13

C

T

C

T

D3

-

C

T

C

T

D3

-

DQS

4-50

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

A14

B14

C12

B12

-

PT30B

PT29A

PT28B

PT28A

GNDIO1

PT27B

PT27A

PT26B

PT26A

PT25B

GNDIO0

PT25A

PT24B

PT24A

PT23B

PT23A

PT22B

PT21A

PT20B

GNDIO0

PT20A

PT19B

PT19A

PT18B

PT18A

PT17B

PT17A

PT16B

PT16A

PT15B

PT15A

PT14B

PT13A

GNDIO0

PT12B

PT12A

PT11B

PT11A

PT10B

PT10A

PT9B

1

0

-

PT34B

PT33A

PT32B

PT32A

GNDIO1

PT31B

PT31A

PT30B

PT30A

PT29B

GNDIO0

PT29A

PT28B

PT28A

PT27B

PT27A

PT26B

PT25A

PT24B

GNDIO0

PT24A

PT23B

PT23A

PT22B

PT22A

PT21B

PT21A

PT20B

PT20A

PT19B

PT19A

PT18B

PT17A

GNDIO0

PT16B

PT16A

PT15B

PT15A

PT14B

PT14A

PT13B

PT13A

1

0

-

D4

-

D4

C

T

-

C

T

-

D5

-

D12

E12

A13

A12

A11

-

C

T

C

T

C

-

D6

C

T

C

T

C

-

D6

-

D7

-

BUSY

-

A10

D11

E11

B11

C11

B9

T

C

T

C

T

-

CS1N

T

C

T

C

T

-

CS1N

PCLKC0_0

PCLKT0_0

-

DQS

-

A9

-

DOUT

-

DOUT

B8

C

-

C

-

A8

T

C

T

C

T

C

T

C

T

C

T

-

WRITEN

T

C

T

C

T

C

T

C

T

C

T

-

WRITEN

E10

D10

C10

B10

B7

-

VREF1_0

-

DI

-

A7

CSN

C9

D9

B6

-

VREF2_0

A6

DQS

F9

-

E9

-

B5

C

T

C

T

C

T

C

T

C

T

C

T

C

T

C

T

A5

C8

D8

B4

A4

F8

E8

PT9A

4-51

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

B3

A3

PT8B

PT8A

GNDIO0

PT7B

PT7A

PT6B

PT5A

PT4B

PT4A

PT3B

PT3A

GNDIO0

-

0

-

C

T

-

PT12B

PT12A

GNDIO0

PT11B

PT11A

PT10B

PT9A

PT8B

PT8A

PT7B

PT7A

GNDIO0

PT6B

PT6A

PT5B

PT5A

PT4B

PT4A

GNDIO0

PT3B

CFG0

CFG1

DONE

GND

0

-

C

T

-

D7

C

T

-

C

T

-

C7

DQS

B2

-

C2

-

C3

C

T

C

T

-

C

T

C

T

-

D3

F7

E7

-

C6

-

C

T

C

T

C

T

-

D6

-

C5

-

C4

-

F6

-

E6

-

GNDIO0

-

0

-

E4

-

E5

CFG0

CFG1

DONE

GND

0

-

D4

-

D5

-

A1

-

A2

-

GND

-

A21

A22

AA1

AA22

AB1

AB2

AB21

AB22

B1

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

GND

-

B22

H14

H9

-

GND

-

GND

-

GND

-

J10

J11

J12

J13

J14

-

GND

-

GND

-

GND

-

GND

-

GND

-

4-52

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

J15

J8

GND

VCC

-

GND

VCC

-

J9

K10

K11

K12

K13

K14

K9

L10

L11

L12

L13

L14

L9

M10

M11

M12

M13

M14

M9

N10

N11

N12

N13

N14

N9

P10

P11

P12

P13

P14

P15

P8

P9

R14

R9

F10

F13

G10

G13

G14

4-53

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

G9

H15

H8

VCC

-

VCC

-

VCC

-

VCC

-

J16

J7

VCC

-

VCC

-

VCC

-

VCC

-

K16

K17

K6

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

K7

VCC

-

VCC

-

N16

N17

N6

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

N7

VCC

-

VCC

-

P16

P7

VCC

-

VCC

-

VCC

-

VCC

-

R15

R8

VCC

-

VCC

-

VCC

-

VCC

-

T10

T13

T14

T9

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

VCC

-

U10

U13

G15

G16

G7

VCC

-

VCC

-

VCC

-

VCC

-

VCCAUX

VCCIO0

VCCIO1

-

VCCAUX

VCCIO0

VCCIO1

-

G8

-

H16

H7

-

R16

R7

-

T15

T16

T7

-

T8

-

F11

G11

H10

H11

F12

G12

H12

0

1

0

1

4-54

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA (Cont.)

LFXP15

LFXP20

Ball

Number

Ball

Function

Dual

Function

Ball

Function

Dual

Function

Bank Differential

H13

K15

L15

L16

L17

M15

M16

M17

N15

R12

R13

T12

U12

R10

R11

T11

U11

M6

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

1

2

3

4

5

6

7

-

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

1

2

3

4

5

6

7

-

M7

M8

N8

K8

L6

L7

L8

1. Applies to LFXP “C” only.

2. Applies to LFXP “E” only.

3. Supports dedicated LVDS outputs.

4-55

Pinout Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Thermal Management

Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal

characteristics of a system, Lattice speciﬁes a maximum allowable junction temperature in all device data sheets.

Designers must complete a thermal analysis of their speciﬁc design to ensure that the device and package do not

exceed the junction temperature limits. Refer to the Thermal Management document to ﬁnd the device/package

speciﬁc thermal values.

For Further Information

For further information regarding Thermal Management, refer to the following located on the Lattice website at

www.latticesemi.com.

• Thermal Management document

• Technical Note TN1052 - Power Estimation and Management for LatticeECP/EC and LatticeXP Devices

• Power Calculator tool included with Lattice’s ispLEVER design tool, or as a standalone download from

www.latticesemi.com/software

4-56

LatticeXP Family Data Sheet

Ordering Information

Data Sheet DS1001

December 2005

Part Number Description

LFXP XX X – X XXXXXX X

Device Family

Grade

LatticeXP FPGA

C = Commercial

I = Industrial

Logic Capacity

3K LUTs = 3

Package

T100 = 100-pin TQFP

T144 = 144-pin TQFP

Q208 = 208-pin PQFP

F256 = 256-ball fpBGA

F388 = 388-ball fpBGA

F484 = 484-ball fpBGA

6K LUTs = 6

10K LUTs = 10

15K LUTs = 15

20K LUTs = 20

Supply Voltage

C = 1.8V/2.5V/3.3V

E = 1.2V

TN100 = 100-pin Lead-free TQFP

TN144 = 144-pin Lead-free TQFP

QN208 = 208-pin Lead-free PQFP

FN256 = 256-ball Lead-free fpBGA

FN388 = 388-ball Lead-free fpBGA

FN484 = 484-ball Lead-free fpBGA

Note: Parts dual marked per table below.

Speed

3 = Slowest

4

5 = Fastest

Ordering Information (Contact Factory for Speciﬁc Device Availability)

Note: LatticeXP devices are dual marked. For example, the commercial speed grade LFXP10E-4F256C is also

marked with industrial grade -3I (LFXP10E-3F256I). The commercial grade is one speed grade faster than the

associated dual mark industrial grade. The slowest commercial speed grade does not have industrial markings.

The markings appear as follows:

LFXP10E-

4F256C-3I

Datecode

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

5-1

DS1001 Ordering Information_03.0

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Conventional Packaging

Commercial

Part Number

LFXP3C-3Q208C

LFXP3C-4Q208C

LFXP3C-5Q208C

LFXP3C-3T144C

LFXP3C-4T144C

LFXP3C-5T144C

LFXP3C-3T100C

LFXP3C-4T100C

LFXP3C-5T100C

I/Os

Voltage

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

COM

LUTs

3.1K

136

100

62

1.8/2.5/3.3V

-4

-5

-3

-4

-5

-3

62

-4

62

-5

Part Number

LFXP6C-3F256C

LFXP6C-4F256C

LFXP6C-5F256C

LFXP6C-3Q208C

LFXP6C-4Q208C

LFXP6C-5Q208C

LFXP6C-3T144C

LFXP6C-4T144C

LFXP6C-5T144C

I/Os

188

142

100

Voltage

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

256

208

144

Temp.

COM

LUTs

5.8K

1.8/2.5/3.3V

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

LFXP10C-3F388C

LFXP10C-4F388C

LFXP10C-5F388C

LFXP10C-3F256C

LFXP10C-4F256C

LFXP10C-5F256C

I/Os

244

188

Voltage

Grade

-3

Package

fpBGA

Pins

388

256

Temp.

COM

LUTs

9.7K

1.8/2.5/3.3V

-4

-5

-3

-4

-5

5-2

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Commercial (Cont.)

Part Number

LFXP15C-3F484C

LFXP15C-4F484C

LFXP15C-5F484C

LFXP15C-3F388C

LFXP15C-4F388C

LFXP15C-5F388C

LFXP15C-3F256C

LFXP15C-4F256C

LFXP15C-5F256C

I/Os

300

268

188

Voltage

Grade

-3

Package

Pins

484

388

256

Temp.

COM

LUTs

15.5K

1.8/2.5/3.3V

fpBGA

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

LFXP20C-3F484C

LFXP20C-4F484C

LFXP20C-5F484C

LFXP20C-3F388C

LFXP20C-4F388C

LFXP20C-5F388C

LFXP20C-3F256C

LFXP20C-4F256C

LFXP20C-5F256C

I/Os

340

268

188

Voltage

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

COM

LUTs

19.7K

1.8/2.5/3.3V

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

LFXP3E-3Q208C

LFXP3E-4Q208C

LFXP3E-5Q208C

LFXP3E-3T144C

LFXP3E-4T144C

LFXP3E-5T144C

LFXP3E-3T100C

LFXP3E-4T100C

LFXP3E-5T100C

I/Os

136

100

62

Voltage

1.2V

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

COM

LUTs

3.1K

-4

-5

-3

-4

-5

-3

62

-4

62

-5

5-3

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Commercial (Cont.)

Part Number

LFXP6E-3F256C

LFXP6E-4F256C

LFXP6E-5F256C

LFXP6E-3Q208C

LFXP6E-4Q208C

LFXP6E-5Q208C

LFXP6E-3T144C

LFXP6E-4T144C

LFXP6E-5T144C

I/Os

188

142

100

Voltage

Grade

-3

Package

Pins

256

208

144

Temp.

COM

LUTs

5.8K

1.2V

fpBGA

PQFP

TQFP

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

LFXP10E-3F388C

LFXP10E-4F388C

LFXP10E-5F388C

LFXP10E-3F256C

LFXP10E-4F256C

LFXP10E-5F256C

I/Os

244

188

Voltage

1.2V

Grade

-3

Package

fpBGA

Pins

388

256

Temp.

COM

LUTs

9.7K

1.2V

-4

1.2V

-5

1.2V

-3

1.2V

-4

1.2V

-5

Part Number

LFXP15E-3F484C

LFXP15E-4F484C

LFXP15E-5F484C

LFXP15E-3F388C

LFXP15E-4F388C

LFXP15E-5F388C

LFXP15E-3F256C

LFXP15E-4F256C

LFXP15E-5F256C

I/Os

300

268

188

Voltage

1.2V

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

COM

LUTs

15.5K

-4

-5

-3

-4

-5

-3

-4

-5

5-4

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Commercial (Cont.)

Part Number

LFXP20E-3F484C

LFXP20E-4F484C

LFXP20E-5F484C

LFXP20E-3F388C

LFXP20E-4F388C

LFXP20E-5F388C

LFXP20E-3F256C

LFXP20E-4F256C

LFXP20E-5F256C

I/Os

340

268

188

Voltage

Grade

-3

Package

Pins

484

388

256

Temp.

COM

LUTs

19.7K

1.2V

fpBGA

-4

-5

-3

-4

-5

-3

-4

-5

Industrial

Part Number

LFXP3C-3Q208I

LFXP3C-4Q208I

LFXP3C-3T144I

LFXP3C-4T144I

LFXP3C-3T100I

LFXP3C-4T100I

I/Os

136

100

62

Voltage

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

IND

LUTs

3.1K

1.8/2.5/3.3V

-4

-3

-4

-3

62

-4

Part Number

LFXP6C-3F256I

LFXP6C-4F256I

LFXP6C-3Q208I

LFXP6C-4Q208I

LFXP6C-3T144I

LFXP6C-4T144I

I/Os

188

142

100

Voltage

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

256

208

144

Temp.

IND

LUTs

5.8K

1.8/2.5/3.3V

-4

-3

-4

-3

-4

TQFP

Part Number

LFXP10C-3F388I

LFXP10C-4F388I

LFXP10C-3F256I

LFXP10C-4F256I

I/Os

244

188

Voltage

Grade

-3

Package

fpBGA

Pins

388

256

Temp.

IND

LUTs

9.7K

1.8/2.5/3.3V

-4

IND

-3

IND

-4

IND

5-5

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Industrial (Cont.)

Part Number

LFXP15C-3F484I

LFXP15C-4F484I

LFXP15C-3F388I

LFXP15C-4F388I

LFXP15C-3F256I

LFXP15C-4F256I

I/Os

300

268

188

Voltage

Grade

-3

Package

Pins

484

388

256

Temp.

IND

LUTs

15.5K

1.8/2.5/3.3V

fpBGA

-4

-3

-4

-3

-4

Part Number

LFXP20C-3F484I

LFXP20C-4F484I

LFXP20C-3F388I

LFXP20C-4F388I

LFXP20C-3F256I

LFXP20C-4F256I

I/Os

340

268

188

Voltage

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

IND

LUTs

19.7K

1.8/2.5/3.3V

-4

-3

-4

-3

-4

Part Number

LFXP3E-3Q208I

LFXP3E-4Q208I

LFXP3E-3T144I

LFXP3E-4T144I

LFXP3E-3T100I

LFXP3E-4T100I

I/Os

136

100

62

Voltage

1.2V

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

IND

LUTs

3.1K

1.2V

-4

1.2V

-3

1.2V

-4

1.2V

-3

62

1.2V

-4

Part Number

LFXP6E-3F256I

LFXP6E-4F256I

LFXP6E-3Q208I

LFXP6E-4Q208I

LFXP6E-3T144I

LFXP6E-4T144I

I/Os

188

142

100

Voltage

1.2V

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

256

208

144

Temp.

IND

LUTs

5.8K

1.2V

-4

1.2V

-3

1.2V

-4

1.2V

-3

1.2V

-4

TQFP

Part Number

LFXP10E-3F388I

LFXP10E-4F388I

LFXP10E-3F256I

LFXP10E-4F256I

I/Os

244

188

Voltage

1.2V

Grade

-3

Package

fpBGA

Pins

388

256

Temp.

IND

LUTs

9.7K

1.2V

-4

IND

1.2V

-3

IND

1.2V

-4

IND

5-6

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Industrial (Cont.)

Part Number

LFXP15E-3F484I

LFXP15E-4F484I

LFXP15E-3F388I

LFXP15E-4F388I

LFXP15E-3F256I

LFXP15E-4F256I

I/Os

300

268

188

Voltage

1.2V

Grade

-3

Package

Pins

484

388

256

Temp.

IND

LUTs

15.5K

fpBGA

1.2V

-4

1.2V

-3

1.2V

-4

1.2V

-3

1.2V

-4

Part Number

LFXP20E-3F484I

LFXP20E-4F484I

LFXP20E-3F388I

LFXP20E-4F388I

LFXP20E-3F256I

LFXP20E-4F256I

I/Os

340

268

188

Voltage

1.2V

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

IND

LUTs

19.7K

1.2V

-4

1.2V

-3

1.2V

-4

1.2V

-3

1.2V

-4

5-7

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Lead-free Packaging

Commercial

Part Number

LFXP3C-3QN208C

LFXP3C-4QN208C

LFXP3C-5QN208C

LFXP3C-3TN144C

LFXP3C-4TN144C

LFXP3C-5TN144C

LFXP3C-3TN100C

LFXP3C-4TN100C

LFXP3C-5TN100C

I/Os

136

100

62

Voltage

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

COM

LUTs

3.1K

1.8/2.5/3.3V

-4

-5

-3

-4

-5

-3

62

-4

62

-5

Part Number

LFXP6C-3FN256C

LFXP6C-4FN256C

LFXP6C-5FN256C

LFXP6C-3QN208C

LFXP6C-4QN208C

LFXP6C-5QN208C

LFXP6C-3TN144C

LFXP6C-4TN144C

LFXP6C-5TN144C

I/Os

188

142

100

Voltage

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

256

208

144

Temp.

COM

LUTs

5.8K

1.8/2.5/3.3V

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

LFXP10C-3FN388C

LFXP10C-4FN388C

LFXP10C-5FN388C

LFXP10C-3FN256C

LFXP10C-4FN256C

LFXP10C-5FN256C

I/Os

244

188

Voltage

Grade

-3

Package

fpBGA

Pins

388

256

Temp.

COM

LUTs

9.7K

1.8/2.5/3.3V

-4

-5

-3

-4

-5

Part Number

LFXP15C-3FN484C

LFXP15C-4FN484C

LFXP15C-5FN484C

LFXP15C-3FN388C

LFXP15C-4FN388C

LFXP15C-5FN388C

LFXP15C-3FN256C

LFXP15C-4FN256C

LFXP15C-5FN256C

I/Os

300

268

188

Voltage

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

COM

LUTs

15.5K

1.8/2.5/3.3V

-4

-5

-3

-4

-5

-3

-4

-5

5-8

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Commercial (Cont.)

Part Number

LFXP20C-3FN484C

LFXP20C-4FN484C

LFXP20C-5FN484C

LFXP20C-3FN388C

LFXP20C-4FN388C

LFXP20C-5FN388C

LFXP20C-3FN256C

LFXP20C-4FN256C

LFXP20C-5FN256C

I/Os

340

268

188

Voltage

Grade

-3

Package

Pins

484

388

256

Temp.

COM

LUTs

19.7K

1.8/2.5/3.3V

fpBGA

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

LFXP3E-3QN208C

LFXP3E-4QN208C

LFXP3E-5QN208C

LFXP3E-3TN144C

LFXP3E-4TN144C

LFXP3E-5TN144C

LFXP3E-3TN100C

LFXP3E-4TN100C

LFXP3E-5TN100C

I/Os

136

100

62

Voltage

1.2V

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

COM

LUTs

3.1K

-4

-5

-3

-4

-5

-3

62

-4

62

-5

Part Number

LFXP6E-3FN256C

LFXP6E-4FN256C

LFXP6E-5FN256C

LFXP6E-3QN208C

LFXP6E-4QN208C

LFXP6E-5QN208C

LFXP6E-3TN144C

LFXP6E-4TN144C

LFXP6E-5TN144C

I/Os

188

142

100

Voltage

1.2V

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

256

208

144

Temp.

COM

LUTs

5.8K

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

LFXP10E-3FN388C

LFXP10E-4FN388C

LFXP10E-5FN388C

LFXP10E-3FN256C

LFXP10E-4FN256C

LFXP10E-5FN256C

I/Os

244

188

Voltage

1.2V

Grade

-3

Package

fpBGA

Pins

388

256

Temp.

COM

LUTs

9.7K

1.2V

-4

1.2V

-5

1.2V

-3

1.2V

-4

1.2V

-5

5-9

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Commercial (Cont.)

Part Number

LFXP15E-3FN484C

LFXP15E-4FN484C

LFXP15E-5FN484C

LFXP15E-3FN388C

LFXP15E-4FN388C

LFXP15E-5FN388C

LFXP15E-3FN256C

LFXP15E-4FN256C

LFXP15E-5FN256C

I/Os

300

268

188

Voltage

Grade

-3

Package

Pins

484

388

256

Temp.

COM

LUTs

15.5K

1.2V

fpBGA

-4

-5

-3

-4

-5

-3

-4

-5

Part Number

LFXP20E-3FN484C

LFXP20E-4FN484C

LFXP20E-5FN484C

LFXP20E-3FN388C

LFXP20E-4FN388C

LFXP20E-5FN388C

LFXP20E-3FN256C

LFXP20E-4FN256C

LFXP20E-5FN256C

I/Os

340

268

188

Voltage

1.2V

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

COM

LUTs

19.7K

-4

-5

-3

-4

-5

-3

-4

-5

Industrial

Part Number

LFXP3C-3QN208I

LFXP3C-4QN208I

LFXP3C-3TN144I

LFXP3C-4TN144I

LFXP3C-3TN100I

LFXP3C-4TN100I

I/Os

136

100

62

Voltage

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

IND

LUTs

3.1K

1.8/2.5/3.3V

-4

-3

-4

-3

62

-4

Part Number

LFXP6C-3FN256I

LFXP6C-4FN256I

LFXP6C-3QN208I

LFXP6C-4QN208I

LFXP6C-3TN144I

LFXP6C-4TN144I

I/Os

188

142

100

Voltage

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

256

208

144

Temp.

IND

LUTs

5.8K

1.8/2.5/3.3V

-4

-3

-4

-3

-4

TQFP

5-10

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Industrial (Cont.)

Part Number

LFXP10C-3FN388I

LFXP10C-4FN388I

LFXP10C-3FN256I

LFXP10C-4FN256I

I/Os

244

188

Voltage

Grade

-3

Package

Pins

388

256

Temp.

IND

LUTs

9.7K

1.8/2.5/3.3V

fpBGA

-4

IND

-3

IND

-4

IND

Part Number

LFXP15C-3FN484I

LFXP15C-4FN484I

LFXP15C-3FN388I

LFXP15C-4FN388I

LFXP15C-3FN256I

LFXP15C-4FN256I

I/Os

300

268

188

Voltage

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

IND

LUTs

15.5K

1.8/2.5/3.3V

-4

-3

-4

-3

-4

Part Number

LFXP20C-3FN484I

LFXP20C-4FN484I

LFXP20C-3FN388I

LFXP20C-4FN388I

LFXP20C-3FN256I

LFXP20C-4FN256I

I/Os

340

268

188

Voltage

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

IND

LUTs

19.7K

1.8/2.5/3.3V

-4

-3

-4

-3

-4

Part Number

LFXP3E-3QN208I

LFXP3E-4QN208I

LFXP3E-3TN144I

LFXP3E-4TN144I

LFXP3E-3TN100I

LFXP3E-4TN100I

I/Os

136

100

62

Voltage

1.2V

Grade

-3

Package

PQFP

TQFP

Pins

208

144

100

Temp.

IND

LUTs

3.1K

1.2V

-4

1.2V

-3

1.2V

-4

1.2V

-3

62

1.2V

-4

Part Number

LFXP6E-3FN256I

LFXP6E-4FN256I

LFXP6E-3QN208I

LFXP6E-4QN208I

LFXP6E-3TN144I

LFXP6E-4TN144I

I/Os

188

142

100

Voltage

1.2V

Grade

-3

Package

fpBGA

PQFP

TQFP

Pins

256

208

144

Temp.

IND

LUTs

5.8K

1.2V

-4

1.2V

-3

1.2V

-4

1.2V

-3

1.2V

-4

TQFP

5-11

Ordering Information

LatticeXP Family Data Sheet

Lattice Semiconductor

Industrial (Cont.)

Part Number

LFXP10E-3FN388I

LFXP10E-4FN388I

LFXP10E-3FN256I

LFXP10E-4FN256I

I/Os

244

188

Voltage

1.2V

Grade

-3

Package

Pins

388

256

Temp.

IND

LUTs

9.7K

fpBGA

1.2V

-4

IND

1.2V

-3

IND

1.2V

-4

IND

Part Number

LFXP15E-3FN484I

LFXP15E-4FN484I

LFXP15E-3FN388I

LFXP15E-4FN388I

LFXP15E-3FN256I

LFXP15E-4FN256I

I/Os

300

268

188

Voltage

1.2V

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

IND

LUTs

15.5K

1.2V

-4

1.2V

-3

1.2V

-4

1.2V

-3

1.2V

-4

Part Number

LFXP20E-3FN484I

LFXP20E-4FN484I

LFXP20E-3FN388I

LFXP20E-4FN388I

LFXP20E-3FN256I

LFXP20E-4FN256I

I/Os

340

268

188

Voltage

1.2V

Grade

-3

Package

fpBGA

Pins

484

388

256

Temp.

IND

LUTs

19.7K

1.2V

-4

1.2V

-3

1.2V

-4

1.2V

-3

1.2V

-4

5-12

LatticeXP Family Data Sheet

Supplemental Information

Data Sheet DS1001

November 2007

For Further Information

A variety of technical notes for the LatticeXP family are available on the Lattice website at www.latticesemi.com.

• LatticeECP/EC and LatticeXP sysIO Usage Guide (TN1056)

• Lattice ispTRACY Usage Guide (TN1054)

• LatticeECP/EC and LatticeXP sysCLOCK PLL Design and Usage Guide (TN1049)

• Memory Usage Guide for LatticeECP/EC and LatticeXP Devices (TN1051)

• LatticeECP/EC and XP DDR Usage Guide (TN1050)

• Power Estimation and Management for LatticeECP/EC and LatticeXP Devices (TN1052)

• LatticeXP sysCONFIG Usage Guide (TN1082)

For further information on interface standards refer to the following web sites:

• JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org

• PCI: www.pcisig.com

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

6-1

DS1001 Further Information_01.3

LatticeXP Family Data Sheet

Revision History

Data Sheet DS1001

November 2007

Revision History

Date

Version

Section

—

Change Summary

February 2005

April 2005

May 2005

01.0

Initial release.

01.1

Architecture

Introduction

Architecture

Pinout Information

Introduction

Architecture

EBR memory support section updated with clariﬁcation.

Added TransFR Reconﬁguration to Features section.

Added TransFR section.

01.2

June 2005

July 2005

01.3

02.0

Added pinout information for LFXP3, LFXP6, LFXP15 and LFXP20.

Updated XP6, XP15 and XP20 EBR SRAM Bits and Block numbers.

Updated Per Quadrant Primary Clock Selection ﬁgure.

Added Typical I/O Behavior During Power-up section.

Updated Device Conﬁguration section under Conﬁguration and Testing.

Clariﬁed Hot Socketing Speciﬁcation

DC and Switching

Characteristics

Updated Supply Current (Standby) Table

Updated Initialization Supply Current Table

Added Programming and Erase Flash Supply Current table

Added LVDS Emulation section. Updated LVDS25E Output Termination

Example ﬁgure and LVDS25E DC Conditions table.

Updated Differential LVPECL diagram and LVPECL DC Conditions

table.

Deleted 5V Tolerant Input Buffer section. Updated RSDS ﬁgure and

RSDS DC Conditions table.

Updated sysCONFIG Port Timing Speciﬁcations

Updated JTAG Port Timing Speciﬁcations. Added Flash Download

Time table.

Pinout Information

Updated Signal Descriptions table.

Updated Logic Signal Connections Dual Function column.

Ordering Information Added lead-free ordering part numbers.

July 2005

02.1

02.2

DC and Switching

Characteristics

Clariﬁcation of Flash Programming Junction Temperature

August 2005

Introduction

Architecture

Added Sleep Mode feature.

Added Sleep Mode section.

DC and Switching

Characteristics

Added Sleep Mode Supply Current Table

Added Sleep Mode Timing section

Pinout Information

Added SLEEPN and TOE signal names, descriptions and footnotes.

Added SLEEPN and TOE to pinout information and footnotes.

Added footnote 3 to Logic Signal Connections tables for clariﬁcation on

emulated LVDS output.

September 2005

03.0

Architecture

Added clariﬁcation of PCI clamp.

Added clariﬁcation to SLEEPN Pin Characteristics section.

DC and Switching

Characteristics

DC Characteristics, added footnote 4 for clariﬁcation. Updated Supply

Current (Sleep Mode), Supply Current (Standby), Initialization Supply

Current, and Programming and Erase Flash Supply Current typical

numbers.

or product names are trademarks or registered trademarks of their respective holders. The speciﬁcations and information herein are subject to change without notice.

www.latticesemi.com

7-1

Revision History

LatticeXP Family Data Sheet

Lattice Semiconductor

Date

Version

Section

Change Summary

September 2005

(cont.)

03.0

(cont.)

DC and Switching

Characteristics (cont.)

Updated Typical Building Block Function Performance timing numbers.

Updated External Switching Characteristics timing numbers.

Updated Internal Timing Parameters.

Updated LatticeXP Family timing adders.

Updated LatticeXP "C" Sleep Mode timing numbers.

Updated JTAG Port Timing numbers.

Pinout Information

Added clariﬁcation to SLEEPN and TOE description.

Clariﬁcation of dedicated LVDS outputs.

Updated list of technical notes.

Supplemental

Information

September 2005

December 2005

03.1

04.0

Pinout Information

Power Supply and NC Connections table corrected VCCP1 pin number

for 208 PQFP.

Introduction

Architecture

Moved data sheet from Advance to Final.

Added clariﬁcation to Typical I/O Behavior During Power-up section.

Added clariﬁcation to Recommended Operating Conditions.

DC and Switching

Characteristics

Updated timing numbers.

Pinout Information

Updated Signal Descriptions table.

Added clariﬁcation to Differential I/O Per Bank.

Updated Differential dedicated LVDS output support.

Ordering Information Added 208 PQFP lead-free package and ordering part numbers.

February 2006

March 2006

04.1

04.2

Pinout Information

Corrected description of Signal Names VREF1(x) and VREF2(x).

Corrected condition for IIL and IIH.

DC and Switching

Characteristics

March 2006

04.3

DC and Switching

Characteristics

Added clariﬁcation to Recommended Operating Conditions for

VCCAUX.

April 2006

May 2006

04.4

04.5

Pinout Information

Removed Bank designator "5" from SLEEPN/TOE ball function.

DC and Switching

Characteristics

Added footnote 2 regarding threshold level for PROGRAMN to sysCON-

FIG Port Timing Speciﬁcations table.

June 2006

04.6

04.7

DC and Switching

Characteristics

Corrected LVDS25E Output Termination Example.

August 2006

Architecture

Added clariﬁcation to Typical I/O Behavior During Power-Up section.

Added clariﬁcation to Left and Right sysIO Buffer Pair section.

Changes to LVDS25E Output Termination Example diagram.

DC and Switching

Characteristics

December 2006

February 2007

July 2007

04.8

04.9

05.0

Architecture

Introduction

Architecture

EBR Asynchronous Reset section added.

Updated EBR Asynchronous Reset section.

Updated LatticeXP Family Selection Guide table.

Updated Typical I/O Behavior During Power-up text section.

DC and Switching

Characteristics

Updated sysIO Single-Ended DC Electrical Characteristics table. Split

out LVCMOS 1.2 by supply voltage.

November 2007

05.1

DC and Switching

Characteristics

Added JTAG Port Timing Waveforms diagram.

Pinout Information

Added Thermal Management text section.

Updated title list.

Supplemental

Information

7-2


型号：	LFXP10C-4FN388C
厂家：	LATTICE SEMICONDUCTOR
描述：	LatticeXP Family Data Sheet 的LatticeXP系列数据手册
文件：	总130页 (文件大小：788K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LFXP10C-4FN388C [LATTICE]

相关型号：

LFXP10C-4FN388I

LFXP10C-5F256C

LFXP10C-5F388C

LFXP10C-5FN256C

LFXP10C-5FN388C

LFXP10E-3F256C

LFXP10E-3F256I

LFXP10E-3F256NI

LFXP10E-3F388C

LFXP10E-3F388I

LFXP10E-3FN256C

LFXP10E-3FN256I