LX128EB-5FN208C [LATTICE]
Crossbar Switch, CMOS, PBGA208, LEAD FREE, FPBGA-208;
| 型号： | LX128EB-5FN208C |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | Crossbar Switch, CMOS, PBGA208, LEAD FREE, FPBGA-208 外围集成电路 |
| 文件： | 总75页 (文件大小：876K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ispGDX2™ Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notifications (PCNs) #09-10 has been issued to discontinue select
devices in this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
LX64V
Ordering Part Number
LX64V-3F100C
LX64V-3FN100C
LX64V-5F100C
Product Status
Reference PCN
Active / Orderable
LX64V-5FN100C
LX64B-3F100C
LX64B-3FN100C
LX64B-5F100C
LX64B-5FN100C
LX64C-3F100C
LX64C-3FN100C
LX64C-5F100C
LC64B
LX64C
Discontinued
Discontinued
Active / Orderable
Discontinued
Discontinued
Active / Orderable
Discontinued
PCN#09-10
PCN#09-10
LX64C-5FN100C
LX128V-32F208C
LX128V-32FN208C
LX128V-5F208C
LX128V-5FN208C
LX128B-32F208C
LX128B-32FN208C
LX128B-5F208C
LX128B-5FN208C
LX128C-32F208C
LX128C-32FN208C
LX128C-5F208C
LX128C-5FN208C
LX256V-35F484C
LX256V-35FN484C
LX256V-5F484C
LX256V-5FN484C
LX256B-35F484C
LX256B-35FN484C
LX256B-5F484C
LX256B-5FN484C
LX128V
LX128B
LX128C
LX256V
LX256B
PCN#09-10
PCN#09-10
PCN#09-10
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
LX256C
Ordering Part Number
LX256C-35F484C
LX256C-35FN484C
LX256C-5F484C
Product Status
Discontinued
Reference PCN
PCN#09-10
LX256C-5FN484C
LX64EV-3F100C
LX64EV-3FN100C
LX64EV-5F100C
LX64EV-5F100I
LX64EV-5FN100C
LX64EV-5FN100I
LX64EB-3F100C
LX64EB-3FN100C
LX64EB-5F100C
LX64EB-5F100I
LX64EB-5FN100C
LX64EB-5FN100I
LX64EC-3F100C
LX64EC-3FN100C
LX64EC-5F100C
LX64EC-5F100I
LX64EC-5FN100C
LX64EC-5FN100I
LX128EV-32F208C
LX128EV-32FN208C
LX128EV-5F208C
LX128EV-5F208I
LX128EV-5FN208C
LX128EV-5FN208I
LX128EB-32F208C
LX128EB-32FN208C
LX128EB-5F208C
LX128EB-5F208I
LX128EB-5FN208C
LX128EB-5FN208I
LX128EC-32F208C
LX128EC-32FN208C
LX128EC-5F208C
LX128EC-5F208I
LX128EC-5FN208C
LX128EC-5FN208I
LX256EV-35F484C
LX256EV-35FN484C
LX256EV-5F484C
LX256EV-5F484I
LX256EV-5FN484C
LX256EV-5FN484I
LX64EV
LX64EB
LX64EC
LX128EV
LX128EB
LX128EC
LX256EV
Active / Orderable
Discontinued
PCN#09-10
PCN#09-10
Discontinued
Active / Orderable
Discontinued
PCN#09-10
PCN#09-10
Discontinued
Active / Orderable
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
LX256EB
Ordering Part Number
LX256EB-35F484C
LX256EB-35FN484C
LX256EB-5F484C
LX256EB-5F484I
Product Status
Discontinued
Reference PCN
PCN#09-10
LX256EB-5FN484C
LX256EB-5FN484I
LX256EC-35F484C
LX256EC-35FN484C
LX256EC-5F484C
LX256EC-5F484I
LX256EC
Discontinued
PCN#09-10
LX256EC-5FN484C
LX256EC-5FN484I
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
™
ispGDX2 Family
High Performance Interfacing and Switching
September 2005
Data Sheet
■ Two Options Available
Features
• High-performance sysHS(standard part number)
• Low-cost, no sysHSI (“E-ies”)
■ High Performance Bus Switching
• High bandwidth
■ sysHSI Blocks Prvide up t16 High-speed
Channels
– Up to 12.8 Gbps (SERDES)
– Up to 38 Gbps (without SERDES)
• Up to 16 (15x10) FIFOs for data buffering
• High speed performance
• Serializer/de-serialir (SRDES) included
• Clock DaRecovery DR) built in
• 800 Mbpper chanel
• LVDdiffeential upport
• 1B/12support
– f
= 360MHz
MAX
– t = 3.0ns
PD
– t = 2.9ns
CO
– Encong / decoding
– it alignment
mbol alignment
– t = 2.0ns
S
• Built-in programmable control logic capability
• I/O intensive: 64 to 256 I/Os
• Expanded MUX capability up to 188:1 MUX
• 8B/10B support
– Bit alignment
– Symbol aligent
• Source Syncronousuport
■ sysCLOCK™ PLL
• Frequency synthesis and skew managem
• Clock multiply and divide capability
• Clock shifting up to +/-2.35ns in 335ps st
• Up to four PLLs
■ Flexible Pramng and Testing
• IEE153compliant In-System Programmabil-
iy (IS™)
■ sysIO™ Interfacing
Boundascan test through IEEE 1149.1
ierface
• 3.32.5V or 1.8V power supplies
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
• LVCMOS 1.8, 2.5, 3.3 and LVTTL upport for
standard board interface
• SSTL 2/3 Class I and support
• HSTL Class I, III and suppo
• GTL+, PCI-X for bus intface
• LVPECL, LVDand us LVDS differential t
• Hot socketing
• Programmable de srength
Table 1. ispGX2 Family Selection Gide
ispDX2-64/E
ispGDX2-128/E
ispGDX2-256/E
I/Os
64
128
256
16
X Blos
4
3.0ns
8
3.2ns
t
t
t
f
3.5ns
PD
S
2.0ns
2.0ns
2.0ns
2.9ns
3.1ns
3.2ns
CO
MAX
(Toggle)
360MHz
3.2Gbps
11Gbps
4
330MHz
6.4Gbps
21Gbps
8
300MHz
12.8Gbps
38Gbps
16
S1, 2
Withut SERDES3
Max Bandwidth
sysHSI Channels2
LVDS/Bus LVDS (Pairs)
PLLs
32
64
128
2
2
4
Package
100-ball fpBGA
208-ball fpBGA
484-ball fpBGA
1. Max number of SERDES channels per device * 800Mbps
2. “E-Series” does not support sysHSI.
3. f
(Toggle) * maximum I/Os divided by 2.
MAX
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
gdx2fam_13
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 1. ispGDX2 Block Diagram (256-I/O Device)
sysIO Bank
sysIO Bank
sysHSI
Block
sysHSI
Block
SERDES
FIFO
SERDES
FIFO
SERDES
SERDES
FIFO
sysCLOCK
PLL
sysCLCK
P
FIFO
GDX Block
GDX Block
GDX Block
GDX Block
Global Rong Pool
(RP)
GDX Bl
FO
GDX Block
GDX Block
FI
GDX Block
FIFO
FIFO
sysCLOCK
PL
sysCLOCK
PLL
sys
Block
sysHSI
Block
SERDES
SS
ERDES
SERDES
ISP & Boundary Scan
Test Port
sysIO
sysIO Bank
Introduction
The ispX2™ amily is Lattic’s second eneration in-system programmable generic digital crosspoint switch for
igh speebuswitching and ntecapplications.
e ispDX2 family is avaible in twoptions. The standard device supports sysHSI capability for ultra fast serial
commnications whie lor-cost “E-series” supports the same high-performance FPGA fabric without the
sysHSI Block.
This family of switchbines a flexible switching architecture with advanced sysIO interfaces including high
performance sysHSI Blcks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through
a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions.
The availability of on-chip control logic further enhances the power of these devices. A high-performance solution,
the family supports bandwidth up to 38Gbps.
Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple
clocks and manage clock skews in their systems.
2
Lattice Semiconductor
ispGDX2 Family Data Sheet
The sysIO interfaces provide system-level performance and integration. These I/Os support various modes of
LVCMOS/LVTTL and support popular high-speed standard interfaces such as GTL+, PCI-X, HSTL, SSTL, LVDS
and Bus-LVDS. The sysHSI Blocks further extend this capability by providing high speed serial data transfer capa-
bility.
Devices in the family can operate at 3.3V, 2.5V or 1.8V core voltages and can be programd in-system via an
IEEE 1149.1 interface that is compliant with the IEEE 1532 standard. Voltages required for he I/O uffers are inde-
pendent of the core voltage supply. This further enhances the flexibility of this famiin syem designs.
Typical applications for the ispGDX2 include multi-port multi-processor interfaces, ide dta and address bus mul-
tiplexing, programmable control signal routing and programmable bus interfaces. e 1 shws the members of
the ispGDX2 family and their key features.
Architecture
The ispGDX2 devices consist of GDX Blocks interconnected by a Glol Roung Pool (GRP). erface
with the external system via sysIO banks. In addition, each GDX Bck is ssociated with FIFO sysHSI
Block to facilitate the transfer of data on- and off-chip. Figur1 shos the ispGDX2 blk digram. ach GDX
Block can be individually configured in one of four modes:
• Basic (No FIFO or SERDES)
• FIFO Only
• SERDES Only
• SERDES and FIFO
Each sysIO bank has its own I/O power supply rence voltage. scan use any output standard
within a bank that is compatible with the power supAny input stanard ay be used, providing it is compatible
with the reference voltage. The banks e independent.
Global Routing Pool (GRP)
The ispGDX2 architecture is ganized into GDX Blocks, whh are conected via a Global Routing Pool. The inno-
vative GRP is optimized for rtability, exibility and speed. All e signals enter via the GDX Block. The block sup-
plies these either directy or iregistred form to the RP. TGRP routes the signals to different blocks, and
provides separate daand control routing.The dpath ioptimized to achieve faster speed and routing flexibility
for nibble oriented sigalThe control routing d to provide high-speed bit oriented routing of control sig-
nals.
There are somrestrictions on the allcation of pins for optimal bus routing. These restrictions are considered by
the software in thallcation of pins.
GDX lck
The blockarorganized in a “blck” ibble) manner, with each GDX Block providing data flow and control logic
for 6 O buffers. The da flow is oganized as four nibbles, each nibble containing four Multiplexer Register
Blocks MRBs). Data for the RBs is provided from 64 lines from the GRP. Figure 2 illustrates the groups of signals
goiinto and out X Blk.
Control signals for are provided from the Control Array. The Control Array receives the 32 signals from
the GRP and generatecontrol signals: eight MUX Select, four Clock/Clock Enable, two Set/Reset and two Out-
put Enable. Each nibble is controlled via two MUX select signals. The remaining control signals go to all the MRBs.
Besides the control signals from the Control Array, the following global signals are available to the MRBs in each
GDX Block: four Clock/Clock Enable, one reset/preset, one power-on reset, two of four MUX select (two of two in
64 I/O), four Output Enable (two in 64 I/O) and Test Out Enable (TOE).
3
Lattice Semiconductor
ispGDX2 Family Data Sheet
MUX and Register Block (MRB)
Every MRB Block has a 4:1 MUX (I/O MUX) and a set of three registers which are connected to the I/O buffers,
FIFO and sysHSI Blocks. Multiple MRBs can be combined to form large multiplexers as described below. Figure 3
shows the structure of the MRB.
Each of the three registers in the MRB can be configured as edge-triggered D-type flip-floor as a level sensitive
latch. One register operates on the input data, the other output data and the last register yncrones the output
enable function. The input and output data signals can bypass each of their registersThe polarity f the data out
and output enable signals can be selected.
The Output and OE register share the same clock and clock enable signals.The Inpugistehas a separate clock
and clock enable.The initialization signals of each register can be independntly configuas Set or Reset.These
registers have programmable polarity control for Clock, Clock Enable anSet/Rest. The output enle register
input can be set either by one of the two output enables generated locly frthe Control Array oof the
four (two in 64 I/O) Global OE enable pins. In addition to the local ock nd clock enable signalsB has
access to Global Clock, Clock Enable, Reset and TOE nets.
4
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 2. GDX Block
GRP
GDX Block
sysIO Bank
MUX
Select
32 bits
4 bits
4 bits
Control Array
Control
8
Nibble 0
8
OE
IN
MUX and Register
Block (MRB)
0
8
2
T
8
OE
IN
MUX and Rester
Block (MR
2
OUT
8
E
IN
MUand Register
Block (MRB)
2
4 bits
OUT
8
OE
IN
Mand Regisr
Bk (MRB)
2
its
OUT
8
OE
IN
2
Nibble 1
MRBs 4-7
16 bits
OUT
4
OE
IN
2
Nibble 2
MRBs 8-11
16 bits
OUT
8
OE
IN
2
Nibble 3
MRBs 12-15
16 bits
OUT
4
The output register of the MRB has a built-in bi-directional shift register capability. Each output register correspond-
ing to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift regis-
ter capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input
register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability.
The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be
combined as one shift register via the GRP.
5
Lattice Semiconductor
ispGDX2 Family Data Sheet
The four data inputs to the 4:1 MUX come from the GRP. The output of this MUX connects to the output register. A
fast feedback path from the MUX to the GRP allows wider MUXes to be built. Table 2 summarizes the various MUX
sizes and delay levels.
Table 2. MUX Size Versus Internal Delay
MUX Sizes
Levels of Internal GRP Delays
One Level
4:1
Up to 16:1
Up to 64:1
Two Levels
Three Levels
Up to 188:1 (with ispGDX2-256)
Four Levels
Figure 3. ispGDX2 Family MRB
Global
Signals
GDX
Control Array
MUX Select
Control Array Signals
2-4
4
2
2
4
/L
ClK
Q
OE
MUX
Select
Global
Signals
OE
CK
Reg/Latch
TE
CE
CE
t
Re
Flags*
(FIFO, SERDES
or PLL)
V
CC
from
Out_Reg(n-1)
From GRP
Q
to Out_Reg(n-1)
to Out_Reg(n+1)
from
Out_Reg(n+1)
ClK
Out
Reg/Latch
CE
Set
Reset
V
CC
Global Resetb
To G
Delay
FIFO Out*
to IN_Reg(n-1)
to IN_Reg(n+1)
from IN_Reg(n-1)
from IN_Reg(n+1)
D/L
Q
ClK
CK
Input
Reg/Latch
CE
CE
Set
Reset
S/R
Global Resetb
*Selected MRBs see Logic Signal Connection Table for details
Control Array
The control array generates control signals for the 16 MRBs within a GDX Block. The true and complement forms
of 32 inputs from the GRP are available in the control array. The 20 NAND terms can use any or all of these inputs
to form the control array outputs. Two AND terms are combined with a NOR term to form Set/Reset and OE sig-
nals. Figure 4 illustrates the control array.
6
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 4. ispGDX2 Family Control Array
32 Inputs from Control GRP
Each connection
is programmable.
MUX Select
to Nibb
MUX elect
to Nbble 1
MUX Select
to Nibble 2
MUX Selec
to Nible 3
To RB Clock/
CloEnable
On selected blocks,
this signal can reset
the M Divider of the
PLL.
To MRB
Set/Reset
To MRB
Output Enable
sysIO Banks
The iuts nd outputs of ispGDX2 deves ardivided into eight sysIO banks, where each bank is capable of sup-
porting erent /O standardsThe number of I/Os per bank is 32, 16 and 8 for the 256-, 128- and 64-I/O devices
espectivelach sysIO bank haits wn I/O supply voltage (V
) and reference voltage (V
), allowing each
CCO
REF
bacmplete independece from thother banks. Each I/O within a bank can be individually configured to any
standarconsistent with the and V settings. Figure 5 shows the I/O banks for the ispGDX2-256 device.
CO
REF
The I/O of the ispces contain a programmable strength and slew rate tri-state output buffer, a program-
mable input buffer, mmable pull-up resistor, a programmable pull-down resistor and a programmable bus-
keeper latch. These prmmable capabilities allow the support of a wide range of I/O standards.
7
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 5. ispGDX2-256 sysIO Banks
sysIO Bank 4
sysIO Bank 5
sysIO Bank 3
sysIO Bk 2
VCCO5
VCCO
VR
GND
VREF5
GND
VCCO6
VREF6
GND
VCCO1
VREF1
GND
sysIO Bank
sysIBank 7
sysIO Ban
sysIBank 0
There e hree classes of I/O terface snrds implemented in the ispGDX2 devices. The first is the non-termi-
ned, sile-eded interfaceit inces the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V LVCMOS
interface stadards. The slew rate and trength of these output buffers can be controlled individually. Additionally,
I 3.3PCI-X and AGP-1are ll ubsets of this interface type. The second interface class implemented is the
terminted, single-eninterce standard. This group of interfaces includes different versions of SSTL and HSTL
interfaces along wnd GTL+. Use of these I/O interfaces requires an additional V
signal. At the system
REF
level, a termination V , is also required. Typically, an output will be terminated to V at the receiving end
TT
TT
of the transmission lis driving. The final types of interfaces implemented are the differential standards
LVPECL, LVDS and Bus LVDS. Table 3 shows the I/O standards supported by the ispGDX2 devices along with
nominal V
, V
and V .
CCO REF TT
The ispGDX2 family also features 5V tolerant I/O. I/O banks with V
= 3.3V may have inputs driven to a maxi-
CCO
mum of 5.5V for easy interfacing with legacy systems. Up to 64 I/O pins per device may be driven by 5V inputs.
8
Lattice Semiconductor
ispGDX2 Family Data Sheet
Table 3. ispGDX2 Supported I/O Standards
sysIO Standard
LVCMOS 3.3
Nominal V
3.3V
2.5V
1.8V
3.3V
3.3V
3.3V
3.3V
3.3V
2.5V
3.3V
2.5V
1.5V
1.5V
1.5V
Nominal V
—
Nominal V
—
CCO
REF
TT
LVCMOS 2.5
LVCMOS 1.8
LVTTL
—
—
—
—
—
PCI 3.3
—
—
PCI -X
—
—
AGP-1X
—
—
SSTL3 class I & II
SSTL2 class I & II
CTT 3.3
1.5V
1.25V
1V
1.25V
75V
0V
0.9V
1.0V
—
1.5V
1.2
1.
0.75V
0.75V
.5V
1.5V
—
CTT 2.5
HSTL class I
HSTL class III
HSTL class IV
GTL+
1.8/2.5/3.3V
3.3V
LVPECL1, 2, 3
LVDS
2.5/3.3V
2.5/3.3V
—
—
Bus-LVDS
—
—
1. LVPECL drivers require three resistor pack (seFigure 17).
2. Depending on the driving LVPECL output spification, GDX2 LVPECL input der maequirerminating resistors.
3. For additional information on LVPECL refto attice technical note number 1000, sysDesign and Usage Guidelines.
The dedicated inputs support subset of the sysIO standrds indiced in Table 4. These inputs are associated
with a bank consistent with thir location.
Table 4. I/O Standards Suppord y Dedicated Input
LVCMO
Yes
LVDS
No
All other ASIC I/Os
Global OE Pins
Global MUX Sect Pins
Resetb
Yes2
Yes2
Yes2
Yes2
No
Ys
No
Yes
No
GlobaClocklock Eables
ispJTAGPort
TOE
Yes
Yes
Yes
No
Yes
No
No
1. CMS as defined by the V
2. No Pclamp.
pin voltag
For more informasysIO capability, please refer to Lattice technical note number TN1000, sysIO Design
and Usage Guidelin
sysCLOCK PLL
The sysCLOCK PLL circuitry consists of Phase-Lock Loops (PLLs) along the various dividers and reset and feed-
back signals associated with the PLLs. This feature gives the user the ability to synthesize clock frequencies and
generate multiple clock signals for routing within the device. Furthermore, it can generate clock signals that are
deskewed either at the board level or the device level. Figure 6 shows the ispGDX2 PLL block diagram.
Each PLL has a set of PLL_RST, PLL_FBK and PLL_LOCK signals. In order to facilitate the multiply and divide
capabilities of the PLL, each PLL has associated dividers.The M divider is used to divide the clock signal, while the
9
Lattice Semiconductor
ispGDX2 Family Data Sheet
N divider is used to multiply the clock signal. The K divider is used to provide a divided clock frequency of the adja-
cent PLL. This output can be routed to the global clock net. The V divider is used to provide lower frequency output
clocks, while maintaining a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay fea-
ture that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better per-
formance. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL
Design and Usage Guidelines.
Figure 6. sysCLOCK PLL
PLL_LOCK
CLK_OUT
CLK_IN
Input Clock
Programmable
(M) Divider
+Delay
P-scalar
(V) Dr
1 to 32
--------------------
PLL (n)
Clock Nt
1, 2, 4, 8,
6, 32
Programmable
-Delay
PLL_RST
Clock (K)
Divider
2, 4, ,
132
To Adjacent_PLL
From
Adjacent_PLL
Feedback
Divider (N)
X 1 32
PLL_FBK
There are four lobal clock networks roted to each MRB block. These global clocks, CLK0-3, can either be gener-
ated by e PLL ccuitor supplied eernally. xternal clock pins can be configured as single-ended or differential
(LVDinpuFigure 7 illustrates how tsysCOCK PLL inputs and outputs can be routed to the I/O pins or gen-
eral rog. Figue 10 shows he clock nework for the ispGDX2-256 and Figure 8 shows the clock networks for
pGDX2-28 and ispGDX2-4. Te eset (0) pin from the Control Array of selected GDX Blocks can be pro-
gramd to reset the M Divider of thPLLs. This provides a means for generating the reset signal internally.
Table 5 etails which GDX Bck pvides reset to the PLLs.
Table 5. Internal ut of the PLL (M Divider)
PLL0
PLL1
PLL2
PLL3
ispGDX2-256
ispGDX2-128
ispGDX2-64
GDX Block 5A
GDX Block 2A
GDX Block 0A
GDX Block 7B
GDX Block 1A
GDX Block 0A
GDX Block 1B
GDX Block 3B
—
—
—
—
10
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 7. I/O Pin Connection to the sysCLOCK PLL1
PLL_LOCK
CLK_OUT
Output
Reg/
Latch
Input Clock
(M) Divider
÷ 1 to 32
Programmable
+ Delay
GCLK_IN
Post-scalar
(V) Divider
÷
--------------------
PLL (n)
Clock Net
1, 2, 4, 8,
16, 32
Programmable
- Delay
Clock
(K) Divider
÷
2, 4, 8,
16, 32
To Adjacent_PLL
Delay
In
g/
Latch
From Adjacent_PLL
Feedback
Divider (N)
x 1 to 32
GRP
GDX Block
PLL_FBK
PLL_RST
Resetb (0)
Control Array
(from selected blocks)
GCK_IN
1. Se pins shared. See Logic Signal nnections ble for details.
11
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 8. ispGDX2-64 CLOCK Network
Clock Net
MRB
sysIO Interface
sysCLOCK
CLK0
K(0)
PLL
(0)
Reg/
GCLK/CE0
+
Clock Net
ch
VREF0
-
CLK_OUT0
Reg/
Clock Net
Latch
GCLK/CE1
+
-
VREF1
CLK_OUT2
CLK2
K(2)
PLL
(2)
Reg
GCLK/CE2
+
Clock Net
h
VREF2
-
Reg/
CNet
Latch
GCLK/CE3
+
-
VREF3
Figure 9. ispGDX2-128 CLOCK etwork
Clock Net
MRB
sIO Interface
sysCCK
CLK0
K(0)
Reg/
GCLK/CE0
+
Clock Net
Latch
VREF0
-
CLKUT0
Reg/
Clock Net
Latch
GCK/CE1
+
VREF1
CLK_OUT
CLK2
K(2)
PLL
(2)
Reg/
GCLK/CE2
+
Clock Net
Latch
-
VREF2
Reg/
Clock Net
Latch
GCLK/CE3
+
-
VREF3
12
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 10. ispGDX2-256 CLOCK Network
MRB
sysIO Interface
sysCLOCK
Clock Net
CLK0
K(0)
PLL
(0)
Reg/
GCLK/CE0
+
Clock Net
Latch
VREF0
-
CLK_OUT0
CLK1
CLK2
CLK3
K(1)
PLL
(1)
Reg/
GCLK/CE1
+
Clock t
Latch
-
VREF1
CLK_OUT1
PLL
(2)
Reg/
Latch
GCLK/CE2
+
Clock Net
VREF2
-
CLK_OUT2
(3)
Reg/
Latch
GCLK/CE3
+
Clock Net
-
REF3
CLK_T3
13
Lattice Semiconductor
ispGDX2 Family Data Sheet
Operating Modes
All the GDX Blocks in the ispGDX2 family can be programmed in four modes: Basic, FIFO only, SERDES only, and
FIFO with SERDES mode. In basic mode, the SERDES and FIFO are disabled and the MUX output of the MRB
connects to the output register. Inputs are connected to the GRP via the MRB.
Figure 11 shows the four different operating modes. Precise detail of the FIFO and SERES connections is pro-
vided in their respective sections.
Figure 11. Four Operating Modes of ispGDX2 Devices
Basic
Mode
FIFO
sysIO
Bnk
GDX
Block
GRP
GRP
GR
ERDS
SERDES
SERDES
FIFO
Mode
FIFO
sysIO
ank
GDX
Block
SERDES
Mode
(FIFO
Flohrough
ode)
FI
sysIO
Bank
GDX
Block
SEDES
and
IFO Mode
FIFO
sysIO
Bank
k
GRP
SERDES
*FIO held in RESfor SERDES-only mode.
FIFO Operations
Each GDX Block is aociatewith a 10-bit wide and 15-word deep (10x15) RAM. This RAM, combined with two
address counters omprators, is used to implement a FIFO as a “circular queue”. The FIFO has separate
clocks, the Read LK) and Write Clock (WCLK), for asynchronous operation. The FIFO has three addi-
tional control signals Enable, Read Enable and FIFO Reset. Three flags show the status of the FIFO: Empty,
Full and Start Read. Eah FIFO receives the global Power-on Reset and Reset signals. Figure 12 shows the con-
nections to the FIFO.
14
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 12. ispGDX2 FIFO Signals
10
10
Data Out (DOUT)
Data In (DIN)
Write Clock (WCLK)
Write Enable (WE)
Read Clock (RCLK)
Read Enable (RE)
FIFO
10x15
Fu(FULL)
Emty (EMY)
Srt Read (STRDb)
Global Reset (RESETb)
Power-on Reset (PORb)
FIFO Reset (FIFORSTb)
Read Clock and Read Enable are the same as tlock nd Clock Enable signaof thinput registers of the
associated MRB.These registers are used to reFIFO outputs, and in mdes tht utilize the FIFO are con-
figured to use the same clock and clock enable e Write Clock lectfrom one of the GCLK/CE sig-
nals or the RECCLK (Recovered Clock) signal froassociated ERDS. The Write Enable is selected from
one of the local MRB product term CK/CE signals. All FIFO operatins ocur on the rising edge of the clock
although clock polarity of these signls an be programmed.
The flags from the FIFO, FULLMPTY anSTRDb (Stat Read) ae each fed via a MUX in the MRB to an I/O
buffer. The STRDb (half full) gnal is used in conjunction witSERDES. STRDb is an active low signal, the signal
is inactive (high) on FIFO REET. Aftthe FIFO reshen tFIFO contains data in five memory locations, at
the following write cloctransitithSTRDb becomes ctive (low). Note, if the Read Clocks arrive before writing
the sixth location, it ay tae longer than five wcks fore the STRDb becomes active. When the FIFO has
data in the first six loons, athe next writnsition the STRDb becomes inactive (high). Again, if the
Read Clocks arrive befowting the seventh e STRDb may stay active for longer than one write clock
period, even ithe FIFO contains data in s thaocations. After this event, the STRDb stays inactive until the
FIFO is RESET gain. TRDb does nt become active again even if less than six memory locations are occupied
in the FO. Iis thser’s responsibilto moor the FULL and EMPTY signals to avoid data underflow/overflow
and to akappropriate actions.
Figure 13 ws how the FIFiconncted between the I/O banks and the GDX Blocks in FIFO mode. For more
infmaon on the FIFO, pase refer tLattice technical note number TN1020, sysHSI Usage Guidelines.
15
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 13. Operation in FIFO Mode2
GDX Block 1
SERDES
Pre-Assigned Pins
GRP
FIFO
10
Delay
Input
Reg/
10
DIN
RXD
Parallel
Data
DOUT
ri
Dan
(SIN)
Latch
RCLK
RE
TXD Serial
allel Data Out
Data (SOUT)
10
Output
Reg/
Latch
PT-CL(0:3
WE
GCLK/CE(0:3)
C
Input
Reg/
Latch
CAL
WCLK
Input
Reg/
Latch
SYDT
put
Latc
FULL
EMPTY
Output
Reg/
Latch
CDRRSTb
FIFORSTb
Notes:
POR
RESETb
1. For clarity, only GDX Block is shown.
2. Some signals sharLogic Signal Connections tables for details.
16
Lattice Semiconductor
ispGDX2 Family Data Sheet
High Speed Serial Interface Block (sysHSI Block)1
The High Speed Serial Interface (sysHSI) allows high speed serial data transfer over a pair of LVDS I/O. The
ispGDX2 devices have multiple sysHSI Blocks.
Each sysHSI Block has two SERDES blocks which contain two main sub-blocks, Transmitter (with a serializer) and
Receiver (with a deserializer) including Clock/Data Recovery Circuit (CDR). Each SERDEcan be used as a full
duplex channel. The two SERDES in a given sysHSI Block share a common clock and mperaat the same
nominal frequency. Figure 14 shows the sysHSI Block.
Device features support two data coding modes: 10B/12B and 8B/10B (for use witoter encoding schemes, see
Lattice’s sysHSI application notes). The encoding and decoding of the 10B/12standrd ae performed within the
device in dedicated logic. For the 8B/10B standard, the symbol boundaries are aligned iternally but the encoding
and decoding are performed outside the device.
Each SERDES block receives a single high speed serial data inpustrem (with embedded clockinput,
and provide a low speed 10-bit wide data stream and a recovered ock to he device. For ansmittie SER-
DES converts a 10-bit wide low-speed data stream to a singhigh-peed data stream ith ebedded clock for
output.
Additionally, multiple sysHSI Blocks can be grouped togther o form a source synchronointerace of between 1-
8 channels.
Figure 15 shows the connections of the SERDith the FIFO, sysIO blk and the MRB. Table 6 provides
the descriptions of the SERDES.
For more information on the SERDES/DR, refer to attice technical ne nuber TN1020, sysHSI Usage Guide-
lines.
Table 6. SERDES Signal Descrtions
Signal
CDRRSTb
SYDT
I/O
Description
Resets the CcircusysHSI block
I
O
Symbnmendetect for sysHSI block
Initisynchronous calibration sequence
Parfor sysHSI block
CAL
I
RXD
Internal
Internal
Interna
I
TXD
Parallel out for sysHSI block
REFCL
S
Refeence clock received from the clock tree
Seridata input for sysHSI block (LVDS input)
Serial data output for sysHSI block (LVDS output)
Clock input for source synchronous group
Clock output for source synchronous group
Recovered clock from encoded data by CDR of sysHSI block
Lock output of the PLL associated with sysHSI block
SOUT
O
SCLKIN
SS_CLKOUT
RECCLK
CSLOC
I
ternal
Internal
1. “E-Series” does not support sysHSI.
17
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 14. sysHSI Block with SERDES and FIFO
sysHSI Block
Core Logic
SERDES
10
10
SOUT
TXD
Serializer
RXD
SIN
De-serializer
including CDR
FIFO
RECCLK
DX
Block
CSLOCK
CSLOCK
SS_CLKOUT
CSPLL
SS_CLKIN
CAL
GRP
Shared Source Synchronous
pins drive multiple sysHSI
blocks
SERDES
Selizer
10
SOUT
N
TXD
RXD
De-serializer
including CDR
FIFO
RCL
GDX
Block
REFCLK (0:3)
Reference clocks
from CLK (0:3)
Note: Sme pins are shared. Seogic SConnections table for details
18
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 15. Operation in SERDES Only Mode1, 2
GRP
GDX Block
SERDES
Pre-Assigned Pins
FIFO
10
Delay
Input
Reg/
DIN
RXD
Parallel
ata
DOUT
eria
Dan
(SIN)
Latch
RCLK
RE
TXSerial
allel Data Out
ta (SOUT)
10
Output
Reg/
Latch
PT-CE(0:3
WE
GLK/CE(0:3)
Input
Reg/
Latch
CAL
WCLK
Input
Reg/
Latch
SYDT
put
/
Lat
FULL
EMPTY
Output
Reg/
Latch
CDRRSTb
FIFORSTb
:
POR
RESETb
1. Some pins sharSignal
Connections table f
2. For SERDES only mrammable bit
holds FIFO in reset. Inpugisters used for
DOUT, and RECCLK configured as
latches and held in pass through.
19
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 16. Operation in SERDES with FIFO Mode
GRP
GDX Block
SERDES
FIFO
Pre-Assigned Pins
10
Delay
Input
Reg/
DIN
RXD
Parallel
DOUT
erial
Dn
(SIN)
Latch
RCLK
RE
TXerial
allel Data Out
ta (SOUT)
10
Output
Reg/
Latch
PT-CCE(0:3
WE
LK/CE(0:3)
LK
Input
Reg/
Latch
CAL
WCLK
Input
Reg/
Latch
SYDT
put
/
Lat
FULL
EMPTY
Output
Reg/
Latch
CDRRSTb
FIFORSTb
POR
RESETb
20
Lattice Semiconductor
ispGDX2 Family Data Sheet
IEEE 1149.1-Compliant Boundary Scan Testability
All ispGDX2 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows func-
tional testing of the circuit board on which the device is mounted through a serial scan path that can access all crit-
ical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
test nodes, or test node data to be captured and shifted out for verification. In addition, these vices can be linked
into a board-level serial scan path for more board-level testing. The test access port has its wn sply voltage that
can operate with LVCMOS3.3, 2.5 and 1.8 standards.
sysIO Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be sbeforrunning any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required foonfiguration of the I/Os'
physical nature should be minimal so that board test time is minimized. ThispGDX2 family of devicallows this
by offering the user the ability to quickly configure the physical nature of thsysIO cells. This quuration
takes milliseconds to complete, whereas it takes seconds for the ere device to be prograttice's
ispVM™ System programming software can either perform the quicconfigration through te PC pport, or
can generate the ATE or test vectors necessary for a third-partest sstem.
IEEE 1532-Compliant In-System Programming
In-system programming of devices provides a number f signifiant benefits icluding pid prototyping, lower
inventory levels, higher quality and the ability to main-fielmoifications. AlispGX2 deces provide In-System
Programming (ISP) capability through their Bcan Test Access PorThis pability has been imple-
mented in a manner that ensures that the port rmpliant to the E 15standard. By using IEEE 1532
as the communication interface through which ISP eved, designers gthe benefit of a standard, well defined
interface.
The ispGDX2 devices can be programmacross the commciatemperaure and voltage range. The PC-based
Lattice software facilitates in-sym programing of ispGDX2 devics. The software takes the JEDEC file output
produced by the design implementation software, along with formation about the scan chain, and creates a set of
vectors used to drive the scachain. Te software cae thevectors to drive a scan chain via the parallel port
of a PC. Alternatively, te softwre cn output files in fomats understood by common automated test equipment.
This equipment can en bused to program ispdeves during the testing of a circuit board.
Security Schem
A programmae security scheme is povided on tispGDX2 devices as a deterrent to unauthorized copying of
the array configution patterns. Once programmed, this scheme prevents readback of the programmed pattern by
a devie prorammr, securing propriery desns from competitors. The security scheme also prevents program-
ming aerificaion. The entirdevice mbe erased in order to reset the security scheme.
Hot Socketing
The ispDX2 devices are wl suited for those applications that require hot socketing capability. Hot socketing a
devie requires thvicewhen powered down, can tolerate active signals on the I/Os and inputs without
being damaged. Ait requires that the effects of the powered-down device be minimal on active signals.
21
Lattice Semiconductor
ispGDX2 Family Data Sheet
Absolute Maximum Ratings1, 2, 3
ispGDX2C (1.8V)
ispGDX2B/V (2.5/3.3V)
Supply Voltage V
. . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V. . . . . . . . . . . . . . . . -0.5 to 5.5V
CC
PLL Supply Voltage V
. . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V. . . . . . . . . . . . . . . . -0.5 to 5
CCP
Output Supply Voltage V
. . . . . . . . . . . . . . . . . -0.5 to 4.5V. . . . . . . . . . . . . . . . -0.5 to 4.5
CCO
JTAG Supply Voltage (V
) . . . . . . . . . . . . . . . . . -0.5 to 4.5V. . . . . . . . . . . . . . . . 0.5 to 4.5V
CCJ
Input or I/O Tristate Voltage Applied 4, 5 . . . . . . . . . -0.5 to 5.5V. . . . . . . . . . . . . . . . 0.to 5.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . -65 o 50°C
Junction Temp. (T ) with Power Applied . . . . . . . . -55 to 150°C . . . . . . . . . . . . . . 5 to 150°C
J
1. Stress above those listed under the Absolute Maximum Ratings may cause permnenamage device. Functionf the
device at these or any other conditions above those indicated in the operational stions this specification is nompliegram-
ming, following the programming specifications).
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (V (MAX)+2) volts is permittefor a duration of <20ns.
IH
5. A maximum of 64 I/Os per device with V > 3.6V is allowed.
IN
Recommended Operating Conditins
Symbol
Pa
Supply Voltage for 1.8V Devices1
Min.
1.65
2.3
3
Max.
1.95
2.7
Units
V
V
V
V
Supply Voltage for 2.5V evices
V
CC
Supply Voltage for 3V Dvices
3.6
V
Supply Voltage for PLL and ssHSI Blocks, 1.8V Device
Supply Voltagfor PLL and sysHSI Blocks, 2.5V Devices
Supply Voltagfor PLL nd sysHSI Bloc3V Dces
Power Supply Vgor JTAG Programmin1.8V Operation
Por Suply Voltage for JTAG Png 2V Operation
Power pply oltage for JTAG g 3.3V Operation
Junction Cmmercial Operation
1.65
2.3
3
1.95
2.7
V
V
CCP
CCJ
3.6
V
1.65
2.3
3
1.95
2.7
V
V
3.6
V
T (COM)
0
90
°C
°C
J
T (IND)
JunctioIndustrial Opeation
-40
105
J
1. sysHI specficatioalid for V and V
= 1.7V t1.9V.
C
CC
Erase eprogram Secifications
Parameter
Min
Max
Units
Erase/Rprogram Cycle
1,000
—
Cycles
Note: Valid over commraturrange.
Hot Socketing ecifications1, 2, 3
Symbol
Parameter
Condition
Min
Typ
Max
Units
4
I
Input or Tristated I/O Leakage Current 0 ≤ V ≤ 3.0V
—
+/-50
+/-800
μA
DK
IN
1. Insensitive to sequence of V and V
. However, assumes monotonic rise/fall rates for V and V
provided (V - V
) ≤ 3.6V.
CCO
CC
CCO
CC
CCO,
IN
2. LVTTL, LVCMOS only.
3. 0 < V ≤ V (MAX), 0 < V
≤ V
(MAX).
CCO
CC
CC
CCO
4. I is additive to I , I or I . Device defaults to pull-up until fuse circuitry is active.
DK
PU PD
BH
22
Lattice Semiconductor
ispGDX2 Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
0 ≤ V ≤ (V - 0.2V)
Min.
—
Typ.
—
Max.
10
Units
μA
IN
CCO
1
I , I
Input or I/O Low Leakage
IL IH
(V
- 0.2V) < V ≤ 3.6V
—
—
30
μA
CCO
IN
3.6V < V ≤ 5.5V and
3
IN
I
Input High Leakage Current
—
—
mA
IH
3.0V ≤ V
≤ 3.6V
CCO
I
I
I
I
I
I
I/O Active Pull-up Current
0 ≤ V ≤ 0.7 V
CCO
-30
30
30
—
—
—
—
—
—
—
-150
150
—
μA
μA
μA
μA
μA
μA
V
PU
IN
I/O Active Pull-down Current
V (MAX) ≤ V ≤ V (MAX)
IL IN IH
PD
Bus Hold Low Sustaining Current V = V (MAX)
BHLS
BHHS
BHLO
BHLH
IN
IL
Bus Hold High Sustaining Current V = 0.7 V
—
IN
CCO
Bus Hold Low Overdrive Current 0 ≤ V ≤ V (MAX)
-
IN
IH
Bus Hold High Overdrive Current 0 ≤ V ≤ V (MAX)
—
IN
IH
V
Bus Hold Trip Points
I/O Capacitance2
V
* 0.35
V
*
BHT
CCO
CCO
V
V
V
V
V
V
= 3.3V, 2.5V, 1.8V
—
—
—
—
—
—
—
—
—
—
—
CCO
C
C
C
8
6
6
pf
pf
pf
1
2
3
= 1.8V, V = 0 to V (MAX)
CC
IO
IH
= 3.3V, 2.1.8
CCO
Clock Capacitance2
= 1.8V, V = 0 V (AX)
CC
IO
IH
= , 1.8
CCO
Global Input Capacitance2
= 1to V (MAX)
CC
IH
1. Input or I/O leakage current is measured with the pin configan input or as aI/O wthe output driver tri-stated. It is not
measured with the output driver active. Bus mntenance circuare disabled.
2. T = 25°C, f = 1.0MHz.
A
3. 5V tolerant inputs and I/Os should be plaed in nks where 3.0V ≤ V
3. The JTAorts are not included for the 5V tolerant inter-
CCO
face.
Supply Current
Over ecomended Operatg Contions (ispGDX2-256)4
Symbol
Descption
Po
cc (V)
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
3.3
2.5
1.8
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Typ.
59.6
58.7
60.0
118.7
118.7
117.5
14.7
14.7
17.4
35
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
Core Logic PowSupply Current
1,2
I
V
CC
CC
PLL/sysHSI Logic Power Supy
Curret
GPLL/sysHSI CSL Poer
Supply Curt
2
I
I
I
V
CCP
CCP
3
Bank Powely Current
JTAG Programming Current
V
35
CCO
CCO
25
1.5
V
1.0
CCJ
CCJ
800
1. 64-input switching frequency at 20 MHz, with one GRP fanout.
2. One GPLL with f = 400 MHz and one sysHSI Block (two receivers and two transmitters) at 622 MHz data rate.
VCO
3. All 8-bank reference circuit currents, all I/Os in tristate, inputs held at valid logic levels, and bus maintenance circuits disabled.
4. T = 25°C
A
23
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysIO Recommended Operating Conditions
V
(V)1
V
(V)
REF
CCO
Standard
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.82
LVTTL
Min.
3.0
2.3
1.65
3.0
3.0
3.0
3.15
2.3
3.0
3.0
2.3
1.4
1.4
1.4
1.4
3.0
2.3
2.3
Typ.
Max.
3.6
2.7
1.95
3.6
3.6
3.6
3.45
2.7
3.6
3.6
2.7
1.6
.6
3.6
6
6
3.6
Min.
Typ.
Max.
3.3
2.5
-
-
-
-
-
-
-
1.8
-
-
3.3
-
-
-
PCI 3.3
3.3
-
-
-
PCI-X
3.3
-
-
-
AGP-1X
3.3
-
-
SSTL 2
2.5
1.1
1.25
1.5
1.5
1
0.7
.9
0.
1.0
-
35
SSTL 3
3.3
.3
CTT 3.3
3.3
1.3
CTT 2.5
2.5
1.35
.65
HSTL Class I
HSTL Class III
HSTL Class IV
GTL+
1.5
.68
0.9
1.5
-
-
1.5
-
-
-
0.882
1.122
LVPECL
3.3
-
-
-
-
-
LVDS
2.5/3.3
2.3.3
-
BLVDS
-
1. Inputs are independent of V
2. Software default setting.
setting. Her, V
must be set within thvalid opeing range for one of the supported standards.
CCO
CCO
24
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysIO Single Ended DC Electrical Characteristics
Over Recommended Operating Conditions
V
V
IH
2
2
IL
Input/Output
Standard
V
V
I
I
OH
OL
OH
OL
Min (V)
Max (V)
Min (V)
Max (V)
Max (V)
Min (V)
(mA)
(mA)
0, 16, 12, -20, -16, -12,
8, 5.-8, -5.33, -4
0.4
2.4
LVCMOS 3.3
LVTTL
-0.3
0.8
2.0
5.5
0.2
0.4
0.2
V
- 02
0.1
-0.1
-4
CCO
24
-0.3
-0.3
0.8
0.7
2.0
1.7
5.5
3.6
V
V
02
0.1
-0.1
CCO
16, 12, 8, -16, -12, -8,
0.4
- 0.
CCO
5.33, 4
-5.33, -4
LVCMOS 2.5
0.2
0.
0.4
2
V
0.2
- 0.4
0.1
-0.1
CCO
LVCMOS 1.81, 3
LVCMOS 1.83
-0.3
-0.3
0.68
0.68
1.07
1.07
3.6
3.6
8
8
CO
V
-0.4 15.33, 4 5.33, -4
CCO
CCO
V
- 0.2
0.
1.5
1.5
8
-0.1
-0.5
-0.5
-0.5
-8
PCI 3.34
PCI -X5
AGP-1X4
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-3
1.08
1.26
1.08
1.5
1.5
1.5
3
3.6
3.6
.6
3.6
3.6
3.6
3.6
3.6
3.6
.6
3.
0.
0.9 V
0.9 V
0.V
CO
C
CCO
0.1 V
CCO
0.1 V
CCO
CCO
SSTL3 class I
SSTL3 class II
SSTL2 class I
SSTL2 class II
CTT 3.3
V
V
- 0.2
- 0.2
V
V
+ 0
0.7
0.5
.1
REF
REF
REF
REF
REF
REF
REF
CCO
C
V
- 0.9
0.62
- 0.43
+ 0.4
+ 0.4
- 0.4
16
7.6
15.2
8
-16
-7.6
-15.2
-8
V
- 0.18 V
- 0.18 V
+ 0.
+ 0.18
+ 0.2
+ 0.2
+ 0.1
+ 0.1
+ 0.1
+
0.54
0.
V
REF
REF
CCO
CCO
V
V
- 02
- 0.3
- 0.1
- 0.2
- 0.
- 0.2
V
V
- 0
- 0.4
V
REF
REF
REF
REF
R
REF
REF
F
REF
CTT 2.5
V
V
V
8
-8
F
REF
REF
REF
REF
REF
HSTL class I
HSTL class III
HSTL class IV
GTL+
V
V
V
V
V
V
0
V
V
V
8
-8
CCO
CCO
CCO
0.4
0.4
0.6
- 0.4
24
48
36
-8
- 0.4
-8
n/a
n/a
1. Software default setting.
2. The average DC current drn I/Os between adjacconnections, or between the last GND in an I/O bank and the end of
the I/O bank, s shown in the gic signals conon tanot exceed n*8mA. Where n is the number of I/Os between bank GND
connections or tween thlast GND in a bk and the end of a bank.
3. For 1.8devices (iGD2C) these specificons are V = 0.35 V and V = 0.65V
CC
IH
CC
4. For V por suppldevices these specificons are = 0.3 * V * 3.3/1.8, V = 0.5 * V * 3.3/1.8
L
CC
IH
CC
5. For 1V wer suply devices thesspecificatiV = 0.35 * V * 3.3/1.8 and V = 0.5 * V * 3.3/1.8
IL
CC
IH
CC
25
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysIO Differential DC Electrical Characteristics
Over Recommended Operating Conditions
Parameter
Symbol
Parameter Description
Test Conditions
Min.
Typ.
Max.
Units
LVDS
V
V
V
Input Voltage
—
0
+/-100
—
—
—
.4
—
V
mV
µA
V
INP INM
Differential Input Threshold
Input Current
0.2V ≤ V
≤ 1.8V
THD
CM
I
Power On
R = 100Ω
—
+/-10
1.60
—
IN
V
V
V
Output High Voltage for V or V
—
1.38
103
350
—
OH
OL
OD
OP
OM
T
Output Low Voltage for V or V
R = 100Ω
0.9
V
OP
OM
T
Output Voltage Differential
(V - V ), R = 100Ω
250
—
450
mV
mV
V
OP
OM
T
ΔV
Change in V Between High and Low —
OD
OD
V
Output Voltage Offset
(V - V )/2, R = 00Ω
1.125
—
1.25
50
OS
OP
OM
T
ΔV
Change in VOS Between H and L
Output Short Circuit Current
—
mV
OS
I
V
= 0V. Driveutpu
OSD
OD
—
24
mA
Shorted.
Bus LVDS1
V
V
V
Output High Voltage for V or V
R = 27
0.95
40
1
300
—
1.80
—
V
V
OH
OL
OD
OP
OM
T
Output Low Voltage for V or V
7Ω
OP
OM
Output Voltage Differential
|, RT = 27Ω
460
27
mV
mV
V
M
ΔV
Change in V Between H and L
OD
OD
V
Output Voltage Offset
|V - VOM| /2, RT = 2
1.1
—
1.3
—
1.5
27
OS
OP
ΔV
Change in V Between anL
mV
OS
OS
I
Output Short Circuit Current
V
= 0. Driver Ouuts
OSD
OD
—
36
65
mA
Shorted.
1. V and V
are the two outputof the LVDoutput buffer.
OP
OM
1
LVPECL
DC Parameter
meter escription
Output ply Voltage
Input Voltage High
Max.
Min.
Max.
Min.
Max.
Units
V
V
V
V
V
V
0
3.3
3.6
V
V
V
V
V
V
CCO
IH
1
0.86
1.7
2.72
2.125
2.11
1.49
0.86
1.92
1.06
0.3
2.72
2.125
2.28
1.49
0.86
2.03
1.25
0.3
2.72
2.125
2.41
npuVoltage Low
IL
Output Voltage High
Output VoltaLow
Differential Inpvoltag
OH
0.96
0.3
1.27
1.43
1.57
2
DIF
Thesalues are valid at the put of he ource termination pack as shown above with 100-ohm differential load only (see Figure 17).
The levels are 200below e standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.
OH
2. Vid for 0.2V ≤ V
C
Figure 17. LVPECL with Three Resistor Pack
1/4 of Bourns P/N
ispGDX2
CAT 16-PC4F12
LVPECL Buffer
A
Zo
Zo
Rs
to LVPECL
differential
receiver
Rs
26
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics
Over Recommended Operating Conditions
-3
-32
-35
-5
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Output Paths
t
t
t
t
t
Data From Input Pin to Output Pin
Data From Global Select Pin to Output Pin
Global Clock to Output
—
—
3.0
2.8
2.9
—
—
—
3.2
3.0
3.1
—
—
—
3.
3.3
.2
—
—
—
5.0
4.7
5.4
—
ns
ns
ns
ns
ns
PD
PD_SEL
CO
—
—
—
Set-up Time Before Global Clock
Hold Time After Global Clock
2.0
0.0
2.0
0.0
2.0
0.0
3.0
0.0
OPS
OPH
—
—
PT Clock Enable Setup Time Before
Global Clock
t
3.0
—
3.0
4.1
—
6.9
ns
OPCES
PT Clock Enable Hold Time After
Global Clock
t
t
0.0
—
—
0
—
0.0
—
—
0.0
—
ns
ns
OPCEH
External Reset Pin to Output Delay
5.
6.0
10.0
OPRSTO
Input Paths
t
t
t
t
Set-up Time Before Global Clock
0.
2.0
—
—
—
—
0.5
2.0
1.0
0.0
—
—
—
0.5
2
1.0
0.
—
—
—
—
9
3.0
1.7
0.0
—
—
—
—
ns
ns
ns
ns
IPS
Set-up Time Before Global Clock
(Zero Hold Time)
IPSZ
IPH
Hold Time After Global Clock
Hold Time After Global Clock
(Zero Hold Time)
IPHZ
PT Clock Enable Setup Time efore
Global Clock
t
3.1
—
3.1
—
3.1
—
5.1
—
ns
IPCES
PT Clock Enable Hold Time After bal
Clock
t
t
0.0
—
—
0.
—
—
0.0
—
—
0.0
—
—
ns
ns
IPCEH
External Reset Pin o Output elay
5.6
6.5
7.5
12.5
IPRSTO
Output Enable Paths
t
t
t
t
Global Clk to utput Enabled Pin
.2
—
—
—
—
4.5
—
—
—
—
5.5
—
—
—
—
9.1
—
—
—
ns
ns
ns
ns
OECO
Output EnaRegistr Set-up Time
Before Global loc
0
3.5
1.6
0.0
3.5
2.0
0.0
4.1
3.4
0.0
6.9
OES
Hd Time After Global Clock
OEH
PT Clck Eable Setup Time Before
lobal ck
OECES
PT Clck Enable HolTime After bal
Clok
t
0.0
—
0.0
—
0.0
—
0.0
—
ns
OCEH
t
t
t
Global OE Inputo Output Enle/Disable
Test OE Input to Otput Eable/Disable
Input to nablDisable
—
—
—
3.5
5.2
5.2
—
—
—
3.8
5.5
5.5
—
—
—
4.5
6.2
6.2
—
—
—
7.5
ns
ns
ns
GO
TOE/DIS
EN/DIS
10.3
10.3
Clock and Reset P
t
t
t
Width of Rulse
Clock Width
2.5
1.3
1.5
—
—
—
2.5
1.5
1.6
—
—
—
2.5
1.6
1.6
—
—
—
4.1
2.7
2.7
—
—
—
ns
ns
ns
RW
CW
GW
Clock Width
Clock Frequency with External
f
(Ext)
—
—
204
360
—
—
196
330
—
—
192
300
—
—
119 MHz
180 MHz
MAX
Feedback 1/(t
+ t
)
OPS
CO
f
(Tog, Clock Frequency Maximum Toggle
(No PLL)
MAX
No PLL)
27
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC External Switching Characteristics
Over Recommended Operating Conditions
-3
-32
-35
-5
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
f
Clock Frequency Maximum Toggle
MAX
—
360
—
330
—
30
—
180 MHz
(Tog, PLL) (With PLL)
Timing v.2.2
28
Lattice Semiconductor
ispGDX2 Family Data Sheet
Timing Model
The task of determining the timing through the ispGDX2 family is relatively simple. The timing model provided in
Figure 18 shows the specific delay paths. Once the implementation of a given function is determined either con-
ceptually or from the software report file, the delay path of the function can easily be determined from the timing
model. The Lattice design tools report the timing delays based on the same timing model fa particular design.
Note that the internal timing parameters are given for reference only, and are not tested.Thexterl timing param-
eters are tested and guaranteed for every device.
Figure 18. ispGDX2 Timing Model Diagram (I/O Cell)
TOE path
tTOE_IN
TOE/
GOE
tGOE_IN
t IOI
GOE path
tPTOE
from GRP
to FIFO
(WE)
to sysHSI
(REFCLK)
tGCLK
tPTCLKEN
tCLK_IN
tCLKEN_IN
tIOI
t OEBY
GCLK/
GCLKEN
from GRP
tPLL_DELAY
tPLL_SEC_DELAY
tPTCLK
OE Reg
to sysHSI/FIFO
(Global Reset)
to FIFO
(WCLK)
CE
t SR_IN
GSR
from sysHSI
(SOUT)
tIOI
t HSISOUT
S
from GRP
from GRP
tPTSR
from sysHSO
(Flags)
t HLAG
Output
Delays
tSEL_IN
tIOI
rom sysHSI
)
SISSCLKOUT
GSEL
tBUF
tEN
tDIS
t IOO
from Adjacent
Ce(Output)
tOPBYPA
OUT
tPTSEL
Out Reg
Q
t OPAC
tD
XSEL
from GRP
CE
to sysHSI
(TXD)
S/R
from Adjacent Cells
(Input)
IPAC
from FIFO
(DOUT)
TAOUT
to Adjacent Cells
(Output)
from SI
(RECSYDT)
Input Reg.
t HSIOUT
S/R
CE
from
(PLL Outp
OUT
t
t IOI
D
Q
IN
t ROUTEGRP
to GRP
tINDIO
tIPBYPASS
to sIFO
(SIN, Contrset, SSCLKIN)
to Adjacent Cells
(Input)
to FIFO
(REN)
Italicrameters are optional.
el Vern 1.6.7
to FIFO
(RCLK)
29
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 19. ispGDX2 Timing Model Diagram (with sysHSI and FIFO Receive Mode)
to I/O Cell
(RECCLK)
sysHSI
(RXD)
FIFO
Serial Data
In
Data Out
(RXD)
from I/O Cell
(SIN)
tFIFODATAIN
Data In
tHSISIN
Recovered
Clock
Write CLK
tFIFOWCLK
to I/O Cell
(DOUT)
HSI Controls
CAL
HSI Flags
CSLOCK
to I/O Cell
(Output Path Flag)
from I/O Cell
(Control)
tHSICTRLCAL
FIFO Flags
to I/O Cell
(SYDT and Output
Path Flags)
SYDT
to I
(Output PaFlags)
FULL, EMP
Source
Synchronous Clock
from I/O Cell
(SSCLKIN)
tHSISSCLKIN
d
Clock
from I/O Cel
(RCLK
tIFORCLK
from I/O Cell
(REFCLK)
Reference Clock
tHSIREFCLK
Read
Enable
from I/O C
(RE)
tFIFO
RESET
RES
from I/O Cell
(Global RESET)
tHSIFIFORST
from I/O Cell
(I/O RESET)
Figure 20. ispGDX2 mng Model Diagram HSI Transmit Mode)
sysHSI
(TXD)
Serial
Data Out
to I/O Cell
(SOUT)
from I/O Cell
(TXD)
Data In
tHSIT
frI/O Cell
(RLK)
Reference Clock
SIREFCLK
Source
to I/O Cell
Synchronous Clock
(SSCLKOUT)
30
Lattice Semiconductor
ispGDX2 Family Data Sheet
Figure 21. ispGDX2 Timing Model Diagram (in FIFO Only Mode)
from I/O Cell
(DIN)
tFIFODATAIN
tFIFOWCLK
tFIFOWEN
Data In
FIFO
to I/O Cell
(DOUT)
Data Out
from I/O Cell
(WCLK)
Write
Clock
from I/O Cell
(WE)
Write
Enable
FIFO Flags
Cell
(Outputh Fla)
FULL, EMPTY
Read
Clock
from I/O Cell
(RCLK)
tFIFORCLK
Read
Enable
from I/O Cell
(RE)
tFIFOREN
RESET
from I/O Cell
(Global RESET)
tHSIFIFORST
from I/O Cell
(I/O RESET)
31
Lattice Semiconductor
ispGDX2 Family Data Sheet
Sample External Timing Calculations
The following equations illustrate the task of determining the timing through the ispGDX2 family. These are only a
sample of equations to calculate the timing through the ispGDX2.
Figure 18 shows the specific delay paths and the Internal Timing Parameters table provides the parameter values.
Note that the internal timing parameters are given for reference only and are not tested. Thexternal timing param-
eters are tested and guaranteed for every device.
Data from global select pin to output pin:
t
= t
+ t
+ t
+ t
PD_SEL
SEL_IN
MUXSEL
OPBYPASS BUF
Global clock to output:
= t + t + t
t
+ t
BUF
CO
CLK_IN
GCLK
OPCOi
Input register or latch set-up time before global clock:
= t + t - (t + t
t
)
GCLK
IPS
IN
IPS
CLK
Input register or latch hold time after global clock:
= (t + t ) + t - t
t
IPH
CLK_IN
GCLK
IPHi IN
Data from product term select to output pin:
t
= t + t
+ t
+ t
+
+ t
+ t
PD_PTSEL
IN
IPBYPASS
ROUTEGRP
PTSEL
XSE
PBYPASS BF
Product term clock to output:
= t + t + t
t
+ t
+ t
t
CO_PT
IN
IPBYPASS
ROUTEGRP
PTCLK
BUF
Input register or latch set-up time befoproduct term clock:
= t + t - (t + t + t )
PTCLK
t
IPS_PT
IN
IPSi_PT
IN
IPBYPASS
OUTEGRP
Input register or latch hold timafter product term clock:
t
= (t + t
+ t
+ t
) + t
- t
IPH_PT
IN
IPBYPASS
RUTEGRP
PTCLK
IPHi IN
Global OE input to outut enabldisble:
= t + + t
t
GOE/DIS
GOE_IN
OEBASS
EN
External reset pin to outut dlay:
= t + t + t
BUF
t
OPRSTO
SRN
OPASROi
32
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1
Over Recommended Operating Conditions
-3
-32
-35
-5
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Input/Output Delays
t
t
t
t
t
t
t
t
t
t
Output Buffer Delay
—
—
—
—
—
—
—
—
—
—
0.80
1.00
1.80
1.80
1.50
2.00
0.40
1.60
2.00
3.7
—
—
—
—
—
—
—
—
0.80
1.00
1.80
1.80
1.80
2.00
40
1.60
.70
3.70
—
—
—
—
—
—
—
—
80
1.00
1.80
2.5
.50
2.00
0.40
1.60
270
30
—
—
—
—
—
—
—
—
—
1.14
1.67
3.00
4.17
4.17
3
0
6.17
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUF
Global Clock Input Delay
Global Clock Enable Input Delay
Output Disable Delay
CLK_IN
CLKEN_IN
DIS
Output Enable Delay
EN
Global Output Enable Path Delay
Input Pin Delay
GOE_IN
IN
Global MUX Select Input Delay
Global Set/Reset Path Delay
Test Output Enable Path Delay
SEL_IN
SR_IN
TOE_IN
Shift Register and MUX Delays
Input Path Adjacent I/O Cell Delay
(Shift Register)
t
t
—
0.
1.30
—
—
0.80
1.3
—
—
00
1.30
—
—
1.33
2.17
ns
ns
IPAC
Output Path Adjacent I/O Cell Delay
(Shift Register)
OPAC
t
t
MUX Data Path Delay
MUX Select Path Delay
—
—
0.90
0.4
—
0.90
00
—
—
0.90
0.40
—
—
1.29
0.57
ns
ns
MUXPD
MUXSEL
AND Arrays and Routing Delays
t
t
t
t
FIFO Output to I/O Block Dela
Clock Tree Dela
—
—
—
—
0.00
0.40
.00
0.00
—
—
—
—
0.00
0.40
0.00
0.00
—
—
—
—
0.00
0.40
0.00
0.00
—
—
—
—
0.00
0.67
0.00
0.00
ns
ns
ns
ns
FIFODATAOUT
GCLK
HSI/FIFO Flag I/O BloDelay
HSI Outut to I/O ell Bck Delay
HSIFIFOFLAG
HSIOUT
HSI urce ynchronous Clock to I
Block Dl
t
—
0.00
—
0.00
—
0.00
—
0.00
ns
HSISSCLKOUT
t
t
t
t
t
t
PLL Delay cment
—
—
—
—
—
—
—
0.33
2.20
2.10
2.40
1.70
1.40
0.90
—
—
—
—
—
—
—
0.33
2.20
2.10
2.40
1.70
1.40
0.90
—
—
—
—
—
—
—
0.33
2.20
2.10
2.40
1.70
2.70
0.90
—
—
—
—
—
—
—
0.33
3.67
3.50
4.00
2.83
4.50
1.29
ns
ns
ns
ns
ns
ns
ns
PLL_DELAY
Clock AND Array Delay
Clk Eable AND Array elay
OE AND Array Delay
PTCLK
PTCLKE
PTOE
elect AND ArrDelay
Set/Reset AND Ay Del
Global RoutiPool ey
PEL
PTSR
OUTEGP
Registr/Latch Delayput ths
t
t
t
t
ASet/Reset to Output
AsynSet/Reset Recovery
Registertch Bypass Delay
—
—
2.50
2.50
0.00
—
—
—
2.50
2.50
0.20
—
—
—
2.50
2.50
0.50
—
—
—
4.17
4.17
0.71
—
ns
ns
ns
ns
OPASROi
OPASRRi
OPBYPASS
OPCEHi
—
—
—
—
Register Clock Enable Hold Time
1.30
1.30
1.30
2.17
Register Clock Enable Setup Time
(Global Clock Enable)
t
t
1.10
1.00
—
—
1.10
1.00
—
—
1.10
2.10
—
—
1.83
3.50
—
—
ns
ns
OPCESi
Register Clock Enable Setup Time
(Product Term Clock Enable)
OPCESi_PT
t
t
Register Clock to Output Delay
Register Hold Time
—
0.70
—
—
0.90
—
—
1.00
—
—
1.67
—
ns
ns
OPCOi
0.80
0.80
0.80
1.33
OPHi
33
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1 (Continued)
Over Recommended Operating Conditions
-3
-32
-35
-5
Parameter
Description
Latch Gate to Output Delay
Latch Hold Time
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
—
1.00
—
—
1.00
—
—
1.0
—
—
1.67
—
ns
ns
OPLGOi
0.80
0.80
0.80
.3
OPLHi
Latch Propagation Delay (Transparent
Mode)
t
—
0.30
—
0.30
0.30
0.50
ns
OPLPDi
t
t
t
t
t
Latch Setup Time (Global Gate)
1.20
1.00
1.20
1.00
—
—
—
1.20
1.00
1.20
.00
—
—
2
1.0
1.20
00
—
—
—
2.00
1.67
2.00
1.
—
—
—
ns
ns
ns
ns
ns
OPLSi
Latch Setup Time (Product Term Gate)
Register Setup Time (Global Clock)
Register Setup Time (Product Term Clock)
Asynchronous Set/Reset Pulse Width
OPLSi_PT
OPSi
—
—
—
—
—
—
—
OPSi_PT
OPSRPWi
2.50
2.50
2.50
Register/Latch Delays, Input Paths
t
t
t
t
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Recovery
Register/Latch Bypass Delay
—
—
00
2.50
0.00
—
1.00
2.50
0.00
—
—
—
70
2.5
.00
—
—
2.83
4.17
0.00
—
ns
ns
ns
ns
IPASROi
IPASRRi
IPBYPASS
IPCEHi
—
—
—
—
Register Clock Enable Hold Time
0
1.30
.30
2.17
Register Clock Enable Setup Time
(Global Clock Enable)
t
t
1.10
1.10
—
—
1.10
1.10
—
—
1.10
1.10
—
—
1.83
1.83
—
—
ns
ns
IPCESi
Register Clock Enable Setup Time
(Product Term Clock Enable)
IPCESi_PT
t
t
t
t
Register Clock to Outpuelay
Register Hold Time
—
0.00
—
00
—
—
0.00
—
1.00
—
—
0.00
—
1.00
—
—
0.00
—
1.67
—
ns
ns
ns
ns
IPCOi
IPHi
Latch Gate to Ouut Delay
Latch Hold Tim
1.00
—
1.00
—
1.00
—
1.67
—
IPLGOi
IPLHi
0.00
0.00
0.00
0.00
Latch ProagatiDelay Transparent
Mode)
t
—
0.0
—
0.30
—
0.30
—
0.50
ns
IPLPDi
t
t
t
t
t
Latch etuTime (Global Term)
1.5
1.50
1.50
1.50
—
—
—
1.50
1.50
1.50
1.50
—
—
—
1.50
1.50
1.50
1.50
—
—
—
2.50
2.50
2.50
2.50
—
—
—
ns
ns
ns
ns
ns
IPLSi
Latch Sep Tim(Product Term G
Register Setp Time (Globaock)
gister etup Time (Pruct Term Clock)
Asyhronous Set/Reset ulse Wih
IPLSi_PT
IPSi
—
—
—
—
—
—
—
—
IPSi_PT
IPSRP
2.50
2.50
2.50
4.17
OE Pat
t
t
t
Asynchronous t/Ret Output
Asynchronos Set/Reset ecovery
Register/Latch ypass Delay
—
—
2.50
2.50
0.00
—
—
—
2.50
2.50
0.00
—
—
—
2.50
2.50
0.00
—
—
—
4.17
4.17
0.00
—
ns
ns
ns
ns
OEASROi
OSRR
OEBYPAS
OECEHi
—
—
—
—
Rek Enble Hold Time
1.30
1.30
0.80
1.33
RegEnable Setup Time (Global
Clock
t
t
1.20
1.50
—
—
1.20
1.50
—
—
1.20
2.10
—
—
2.00
3.50
—
—
ns
ns
OECESi
Register Cock Enable Setup Time
(Product Term Clock Enable)
OECESi_PT
t
t
t
t
Register Clock to Output Delay
Register Hold Time
—
0.40
—
1.30
—
—
0.40
—
1.30
—
—
0.40
—
1.60
—
—
0.67
—
2.67
—
ns
ns
ns
ns
OECOi
OEHi
Latch Gate to Output Delay
Latch Hold Time
1.60
—
1.60
—
1.60
—
2.67
—
OELGOi
OELHi
0.40
0.40
0.40
0.67
Latch Propagation Delay (Transparent
Mode)
t
—
0.30
—
0.30
—
0.30
—
0.50
ns
OELPDi
34
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1 (Continued)
Over Recommended Operating Conditions
-3
-32
-35
-5
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
Latch Setup Time (Global Gate)
1.40
1.00
1.00
1.00
—
—
—
1.40
1.00
1.00
1.00
—
—
—
1.40
1.00
1.0
.00
—
2.33
.6
2.3
1.67
—
—
—
ns
ns
ns
ns
ns
OELSi
Latch Setup Time (Product Term Gate)
Register Setup Time (Global Clock)
Register Setup Time (Product Term Clock)
Asynchronous Set/Reset Pulse Width
OELSi_PT
OESi
—
—
—
—
—
—
—
—
OESi_PT
OESRPWi
2.50
2.50
2.5
4.17
Timing v.2.2
1. Internal parameters are not tested and are for reference only. Refer to the timing model in is data sheet for details.
2. t is the unit of increment by which the clock signal can be incremented. The PLL n adjust e clock signal by
(as
GE
PLL_DELAY
given in the sysCLOCK PLL Timing section) in either direction in steps of size t
PLL_DE.
35
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters
-3
-32
-35
-5
Parameter
Optional Adders
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
t
Input Delay
—
—
1.50
1.30
—
—
1.50
1.30
—
—
1.0
1.30
—
—
2.50
1.30
ns
ns
INDIO
Secondary PLL Output
Delay
t
PLL_SEC_DELAY
t
Output Adjusters
IOO
Using Slow Slew (LVTTL and
LVCMOS Outputs Only)
Slow Slew
—
—
—
0.90
1.20
0.30
—
—
0.90
1.20
00
—
—
0.9
1.20
0.30
—
—
0.90
1.20
ns
ns
ns
LVTTL_out
Using 3.3V TTL Drive
Using 1.8V CMOS Standard,
4mA Drive
LVCMOS_18_4mA_out
Using 1.8V CMOS Standard,
5.33mA Drive
LVCMOS_18_5.33mA_out
LVCMOS_18_8mA_out
LVCMOS_18_12mA_out
LVCMOS_25_4mA_out
LVCMOS_25_5.33mA_out
LVCMOS_25_8mA_out
LVCMOS_25_12mA_out
LVCMOS_25_16mA_out
LVCMOS_33_4mA_o
LVCMOS_33_5.33mA_out
LVCMOS33_8mout
LVCM_3_12mA_out
LVCMOS_3316mA_out
—
—
—
—
—
—
—
—
—
—
—
0.30
0.00
0.00
1.20
1.00
0.
0.40
0
1.20
1.20
0.80
0.60
0.60
—
—
—
—
—
—
—
—
—
—
—
—
0
0.00
0.00
1.20
.00
0.40
0.40
0.40
1.20
1.20
0.80
0.60
0.60
—
—
—
—
—
—
—
—
—
—
—
—
—
0.3
0.0
0.
.20
1.00
0.40
0.40
0.40
1.20
1.20
0.80
0.60
0.60
—
—
—
—
—
—
—
—
—
—
—
—
—
0.00
0.00
1.20
1.00
0.40
0.40
0.40
1.20
1.20
0.80
0.60
0.60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Using 1.8V CMOS Standard,
8mA Drive
Using 1.8V CMOS Standard,
12mA Drive
Using 2.5V CMOS Sta
4mA Drive
Using 2.5V CMOS Stan
5.33mA Drive
Using 2.5V MOS Standard,
8mA Drie
Using 2.5V CMOStandard,
1mA Drive
Uing 2.5V MOS Standard,
16A Driv
Using 3.3V CMOS Stan
4mA Drive
Uing 3.3V CMOS S
5.33mA Drive
Using 3.3V MOS Standard,
8mA Drive
Using 3.3V COS Sndard,
12A Drive
Un.3V MOS Standard,
16mA Drive
ing 3.3V CMOS Standard,
20Drive
LVCMOS_33_20mA_o
AGP_1X_out
—
—
—
0.30
0.60
1.00
—
—
—
0.30
0.60
1.00
—
—
—
0.30
0.60
1.00
—
—
—
0.30
0.60
1.00
ns
ns
ns
Using AGP 1x Standard
Using Bus Low Voltage Dif-
ferential Signaling (BLVDS)
BLVDS_out
CTT25_out
CTT33_out
GTL+_out
Using CTT 2.5v
—
—
—
—
—
—
0.30
0.20
0.50
0.50
0.60
0.60
—
—
—
—
—
—
0.30
0.20
0.50
0.50
0.60
0.60
—
—
—
—
—
—
0.30
0.20
0.50
0.50
0.60
0.60
—
—
—
—
—
—
0.30
0.20
0.50
0.50
0.60
0.60
ns
ns
ns
ns
ns
ns
Using CTT 3.3v
Using GTL+
HSTL_I_out
HSTL_III_out
HSTL_IV_out
Using HSTL 2.5V, Class I
Using HSTL 2.5V, Class III
Using HSTL 2.5V, Class IV
36
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters (Continued)
-3
-32
-35
-5
Parameter
LVPECL_out
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Using LVPECL Differential
Signaling
—
—
0.30
0.80
—
—
0.30
0.80
—
—
0.30
0.
—
—
0.30
0.80
ns
ns
Using Low Voltage Differen-
tial Signaling (LVDS)
LVDS_out
PCI_out
Using PCI Standard
—
—
—
—
—
—
0.60
0.60
0.30
0.50
0.20
0.40
—
—
—
—
—
—
0.60
0.60
0
0.50
20
0.40
—
—
—
0.60
0.60
0.0
0.50
0.20
0.40
—
—
—
—
—
0.60
0.60
0.30
0.50
ns
ns
ns
ns
ns
ns
PCI_X_out
Using PCI-X Standard
Using SSTL 2.5V, Class I
Using SSTL 2.5V, Class II
Using SSTL 3.3V, Class I
Using SSTL 3.3V, Class II
SSTL2_I_out
SSTL2_II_out
SSTL3_I_out
SSTL3_II_out
t
Input Adjusters
IOI
LVTTL_in
Using 3.3V TTL
Using 1.8V CMOS
Using 2.5V CMOS
Using 3.3V CMOS
Using AGP 1x
—
—
—
0
0.00
0.00
0.0
.00
—
—
—
0.00
0.00
0.00
0.00
1.0
—
—
—
—
—
0
0.0
00
0.
10
—
—
—
—
0.00
0.00
0.00
0.00
1.00
ns
ns
ns
ns
ns
LVCMOS_18_in
LVCMOS_25_in
LVCMOS_33_in
AGP_1X_in
Using Bus Low Voltag
ential Signaling (BLVDS
BLVDS_in
—
0.50
—
0
0.50
—
0.50
ns
CTT25_in
CTT33_in
GTL+_in
Using CTT 2V
—
—
—
—
—
—
1.00
1.
0.50
0.50
60
0
—
—
—
—
10
1.00
0.50
0.50
0.60
0.60
—
—
—
—
—
—
1.00
1.00
0.50
0.50
0.60
0.60
—
—
—
—
—
—
1.00
1.00
0.50
0.50
0.60
0.60
ns
ns
ns
ns
ns
ns
Using CT3V
Using GTL+
HSTL_I_in
HSTL_III_in
HSTL_IV_in
Ung HSTL 2.5V, Class I
Uing HST2.5V, Class III
Usg HST2.5V, Class IV
Using Differential Sign
(LVPECL)
LVPECL_in
LVDS_in
—
—
0.00
0.50
—
—
0.00
0.50
—
—
0.00
0.50
—
—
0.00
0.50
ns
ns
Uing Low Voltage D
tial Signaling (DS)
PCI_in
Using PCI
—
—
—
—
—
—
1.00
1.00
0.50
0.50
0.60
0.60
—
—
—
—
—
—
1.00
1.00
0.50
0.50
0.60
0.60
—
—
—
—
—
—
1.00
1.00
0.50
0.50
0.60
0.60
—
—
—
—
—
—
1.00
1.00
0.50
0.50
0.60
0.60
ns
ns
PCI_Xn
Using PCI-
SSTL2_i
STL2_II_
SS_in
SSTL3__in
Usig SSTL 2., lass I
Ung T2.5V, Class II
Using SSTL 3.3V, Class I
ing SSTL 3.3V, Class II
ns
ns
ns
ns
Timing v.2.2
37
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC FIFO Internal Timing
-3
-32
-35
-5
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Routing Delays
t
t
t
t
t
t
FIFO Input Delay
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
.00
—
—
—
—
—
—
0.0
0.
0.00
0.00
0.0
.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
0.00
ns
ns
ns
ns
ns
ns
FIFODATAIN
FIFODATAOUT
FIFORCLK
FIFOREN
FIFO Output to I/O Core Delay
Read Clock Input Delay
Read Clock Enable Input Delay
Write Clock Input Delay
FIFOWCLK
FIFOWEN
Write Clock Enable Input Delay
Core Delays
t
t
t
t
Global Read Clock to Write Clock Skew
Read Clock to Empty Flag Delay
Write Clock to Full Flag Delay
—
—
—
2.00
1.30
.30
—
—
—
2.
.80
1.80
—
—
—
2.00
1.80
10
—
—
3.0
ns
ns
ns
FIFOCLKSKEW
FIFOEMPTY
FIFOFULL
Read Clock Hold after Read Clock Enable
Time
FIFORCEH
0.00
1.50
—
0.00
1.50
—
—
0.00
1.
—
—
0.00
2.50
ns
ns
t
Read Clock Setup before Read Clock
Enable Time
FIFORCES
t
t
t
t
t
t
t
Read Clock to FIFO Out Delay
Reset to Output Delay
—
—
—
—
—
—
0.50
0.70
2.00
1.20
0.00
—
—
—
—
—
—
0.5
0.70
.00
1.5
.00
0.00
—
—
—
—
—
—
050
0.70
2.00
2.00
0.00
0.00
—
—
—
—
—
—
0.83
1.17
3.33
3.33
0.00
0.00
ns
ns
ns
ns
ns
ns
FIFORCLKO
FIFORSTO
FIFORSTPW
FIFORSTR
FIFOSTRD
FIFOTHRU
FIFOWCEH
Reset Pulse Width
Reset Recovery Time
Write Clock to Start Read FlaDelay
Flow Through Delay
Write Clock hold fter Write Clock Enable
Time
—
.00
0.00
—
—
2.00
0.00
—
—
2.00
0.00
—
—
3.33
0.00
ns
ns
t
Write ClocSetup fore rite Clock Enable
Time
FIFOWCES
t
t
Write Daold aftr Write Clock Ti
Write Data tubefore Write Clock
—
—
0.50
1.00
—
—
0.50
1.00
—
—
0.70
1.00
—
—
1.17
1.67
ns
ns
FIFOWCLKH
FIFOWCLKS
Timing v.2.2
38
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysHSI Block Timing
Figure 22 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on
a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance.
Figure 22. Receive Data Eye Diagram Template (Differential)
Bit Time
VTHD
200 mV Differential
+/- 100 mV Single Ended
TH
SIN
jtTH : Optimum Threshold Csing itter
The data pattern eye opening at the receive enink ionsidered the timatmesure of received signal
quality. Almost all detrimental characteristics ot signal and the interconection link design result in eye
closure. This combined with the eye-opening limitthe line receivean e a good indication of a link’s
ability to transfer error-free data.
Signal jitter is of special interest to sysm designers. It is oftthe primy limiting characteristic of long digital
links and of systems with high noise level evironments. An interestg characteristic of the clock and data recovery
(CDR) portion of the ispGDXSERDES receiver is its abily to filter coming signal jitter that is below the clock
recovery PLL bandwidth. For ignals wth high levels of low fruency jitter, the receiver can detect incoming data
error free, with eye openngs snificaly less than thaoigure 22.
sysHSI Block ASpcifications
Opeuency Ranges
Symbol
Description
Mode
SS:CAL
10B12
8B10B
Test Condition
Min.
50
Max.
200
67
Units
MHz
f
eferencClock Frequency
33
MHz
CLK
40
80
MHz
SS:CAL
10B12B
8B10B
with eo
400
400
400
8001
8001
8001
Mbps
Mbps
Mbps
SIN
f
f
Serial Input
Serial
with eo
N
SIN
with eo
SIN
C = 5 pF, R = 100 Ohms,
LVDS
400
8001
Mbps
2
L
L
SOUT
f
with no jitter
CLK
1. f
2. f
(8B/10B and 10B/10Mbps limit applicable only to the fastest speed grade. Limit is 700Mbps for the lower speed grade.
SIN
and f
speeds are supported at V and V at 1.7V to 1.9V for ispGDX2C devices.
SIN
SOUT
CC
CCP
39
Lattice Semiconductor
ispGDX2 Family Data Sheet
LOCKIN Time
Symbol
Description
Mode
All
Condition
Min.
Max.
25
Units
t
t
CSPLL Lock Time
After input is stabilized
With SS mode sync pattern
μS
SCLOCK
1
SS
1024
1024
60
t
RCP
CDRPLL Lock-in Time
10B12B With 10B12B sync pattern
t
CDRLOCK
RCP
RCP
RCP
RCP
RCP
RCP
8B10B
SS
With 8B10B idle pattern
t
t
t
t
t
SyncPat Length
1200
1100
50
t
t
t
t
SYNC
CAL Duration
SS
CAL
SyncPat Set-up Time to CAL
SyncPat Hold Time from CAL
SS
SUSYNC
SS
50
HDSYNC
1. REFCLK clock period.
REFCLK and SS_CLKIN Timing
Symbol
Description
Mod
Condition
Min
Max.
100
Units
ppm
UIPP
ns
Frequency Deviation Between TX REFCLK and
CDRX REFCLK on One Link
8B1
10B12B
t
t
t
-0
DREFCLK
REFCLK, SS_CLKIN Peak-to-Peak Period Jitt
All
Randm Jitter
0.01
JPPREFCLK
PWREFCLK
REFCLK, SS_CLKIN Pulse Width, (800% o
20% to 20%).
All
1
REFCLK, SS_CLKIN Rise/Fall Time (% or
80% to 20%)
t
All
2
ns
RFREFCLK
Serializer Timing2
Symbol
Desion
Mode
Cndition
with no jitter
CLK
Min.
Max.
Units
UIPP
ps
t
SOUT Peak-to-Pak Output Data Jitter
SOUT Peakto-Pek Randm Jitter
SOUT Pak-to-Peak Deterministic Jitter
All
f
0.25
130
JPPSOUT
8B Mbps w/K28.7-
t
JPP8B10B
8B1800 Mbps w/K28.5+
160
ps
DS
DS
700
ps
SOUT Opt Data ise/Fall Time (2
80%)
t
RFSOUT
900
ps
/8B10B
10B12B
2Bt1 + 2
1Bt1 + 2
2Bt1 +10
1Bt1 +10
ns
t
t
RFCLK to SOUT Delay
COSOUT
SKTX
ns
Skew f SOUT with Respecto
SS_CLKOUT
SS
250
ps
t
t
S_CLKOUT to 0 of O
TXD Data Sep Time
TXD Data Hold me
SS
2Bt1 - t
2Bt1 + t
SKTX
ns
ns
ns
CKOSOUT
SKTX
All
All
Note 3
Note 3
1.5
HXDTAS
1.0
HSITXDATAH
1. Bt: Bit Time Period. d SerBit Time.
2. The SIN and SOUations listed above are under the condition that the clock tree that drives the REFCLK to sysHSI Block is in
sysCLOCK PLL BYP
3. Internal timing for referenly.
40
Lattice Semiconductor
ispGDX2 Family Data Sheet
Deserializer Timing
Symbol
Description
Mode
Conditions
Min.
-100
0.45
Max.
Units
8B10B/
10B12B
f
SIN Frequency Deviation from REFCLK
100
ppm
DSIN
eo
SIN Eye Opening Tolerance
Bit Error Rate
All
All
Notes 1, 2
UIPP
Bits
SIN
ber
-12
RXD, SYDT Valid Time Before RECCLK Fall-
ing Edge
t
t
t
All
All
All
Note 3
Note 3
t
t
/2 - 0.7
/2 - 0.
ns
ns
ns
HSIOUTVALIDPRE
HSIOUTVALIDPOST
DSIN
CP
RXD, SYDT Valid Time
After RECCLK Falling Edge
Bit 0 of SIN Delay to RXD Valid at RECCLK
Falling edge
1.5 t
+
1.5 t
4.5B
+
RCP
RCP
.5Bt + 2
1. Eye opening based on jitter frequency of 100KHz.
2. Lower frequency operation assumes maximum eye closure of 800ps.
3. Internal timing for reference only.
Lock-in Timing
CDRX_SS LOCK-IN (DE-SKEW) IMG
SIN
MIN. 1CPAT
MI
DATA (RIAL)
CAL
tHDSYN
tSUSYNC
SYDT
RXD(0:7)
SYNCPAT
RAINING SEQUENC
DATA (RALLEL)
SS DE DATA TRANSFER
CDR_10B12B LOCKNG
SI
DATA (SERIAL)
SYDT
RXD(0:9)
SYNCPAT
DATA (PARALLEL)
41
Lattice Semiconductor
ispGDX2 Family Data Sheet
Lock-in Timing (Continued)
CDR_8B10B LOCK-IN TIMING
SIN
240 Idle Pattern(960 TRCP)
DATA (SERIAL)
SYDT
RXD(0:9)
Idle Pattern
DATA (PARALLEL)
SYDT Timing
SYDT TIMING FOR CDRX_10B12B
RECCLK
SYDT
RXD(0:9)
Data0 Data2 Data3 Dat
Parallel Data
SYNC PARN
SYDT TIMING FOR CDRX
RECCLK
SYDT
RXD(0:9)
K28.21.4 D21.5 D21.5 K28.5 D21.4 1.5 D21.5
D0
D2
D1
E PATTERN
IDLE PATTERN
Data
42
Lattice Semiconductor
Serializer Timing
ispGDX2 Family Data Sheet
8B/10B SERIALIZER DELAY TIMING
SYMBOL N
tCOSOUT
SYMBOL N+1
TXD
REFCLK
SOUT
b4
b4 b5 b6 b7 b8 b9 b0 b1 b2 b3
b5 b6 b7 b8 bbb1 b2
SYMBOL N
SYMBOL N-1
SMOL N+1
10B/12B SERIALIZER DELAY TIMING
SYOL
tCOST
SYML +1
TXD
REFCLK
SOUT
b4
b5 bb7 b9
"0" "1"
b4 b5 b6 b7 b8 b9
SYMBOL N-1
0 b1 b2 b3
B
SS Mode SERIALIZER DEAY TIMING
SYM
SYMBOL N+1
TXD
tCOSOUT
REFC
SS_CLKOU
SO
CKOSOUT
tSKTX
b4
b4
b5
b6
b7
b0
b2
SYMBOL N
b5
b1
b3
b6
b7
b0
SYMBOL
N+1
SYMOL N-1
AL TING FOR sysHSI BLOCK
tPWREFCLK
REFCLK
tHSITXDDATAS
tHSITXDDATAH
TXD
43
Lattice Semiconductor
Deserializer Timing
ispGDX2 Family Data Sheet
8B/10B DESERIALIZER DELAY TIMING
SYMBOL N+1
SYMBOL N
SYMBOL N+2
b4
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b0 b1 b2 b3
TDSIN
b5 b6 b7 b8 b9 b0 b1 b2 b3 b4 b5
SIN
RECCLK
RXD
SYMBOL N
SYMBOL N-1
10B/12B DESERIALIZER DELAY TIMING
YMBOL
SYMBOL N
b0 b1 b2 b3 b4 b5
SYMBON+1
SIN
b8 b9
b6 b7
"0" "1" b0 b2 b3 4 b5 b6 b7 b8 b9
b4
"1"
"01" b0 1 b2 b3
TTDSIN
RECCLK
RXD
SYM1
SYMBOL N-2
SYBOL N
CDRX_SS DESERIALIZER LAY TIMING
SMBOL N
SYMBOL N+2
SYMBOL 1
b7
b0 b1 bb3 bb5 b6 b7 b0 b1 b3 b4 b5 b6
TDSIN
b0 b1 b2 b3 b4
SIN
RECCLK
RXD
SMBL N-2
SYMBOL N
L N-1
INTERNAL TING FOsysHSI BLOCK
RECCLK
tHSIOUVALIDPRE
tHSIOUTVALIDPOST
SYDT, RXD
44
Lattice Semiconductor
ispGDX2 Family Data Sheet
sysCLOCK PLL Timing
Over Recommended Operating Conditions
Symbol
Parameter
Conditions
80% to 80%
Min
0.5
0.5
—
Max
—
Units
ns
t
t
Input clock, high time
Input clock, low time
PWH
PWL
20% to 20%
—
ns
t , t
Input Clock, rise and fall time
20% to 80%
3.0
ns
R
F
t
f
f
f
f
f
f
t
Input clock stability, cycle to cycle (peak)
M Divider input, frequency range
M Divider output, frequency range
N Divider input, frequency range
N Divider output, frequency range
V Divider input, frequency range
V Divider output, frequency range
Output clock, duty cycle
—
/- 300
320
320
320
6
ps
INSTB
10
MHz
MHz
MHz
MHz
MHz
MHz
%
MDIVIN
MDIVOUT
NDIVIN
0
10
10
NDIVOUT
VDIVIN
100
10
VDIVOUT
OUTDUTY
40
Clean refnc
1MHz ≤ f
100 Hz ≤ f
an refeence1:
≤ 40 MHz or
≤ 160 MHz
—
—
—
/- 600
+/- 150
+/- 600
+/- 150
ps
ps
ps
ps
MDIVOUT
VDIVIN
t
Output clock, cycle to cycle jitter (peak)
Output clock, period jitter eak)
JIT(CC)
40 Hz ≤ f
160 Hz ≤ f
≤ 30 MHand
≤ 400 Hz
MDIVOUT
VDIVIN
lean reference1:
10 MHz ≤ f
100 MHz ≤ f
40 MHz r
≤ 1MHz
MDOUT
VDI
2
T
JIT(PERIOD)
Clean rerence1:
40 M≤
160 MHz ≤ f
≤ 20 MHz and
≤ 400 MHz
DIVOUT
VVIN
t
t
t
t
t
t
Input clock to C_OUT delay
Interal feedback
terneedback
—
—
—
3.4
500
25
ns
ps
us
ps
ns
ns
CLK_OUT_DLY
Input clock to exrnal feeack delta
Time to quire phalk after input stable
Delay cremnt (Lead/Lag)
PHASE
LOCK
Typal = +/- 250ps
+/- 120 +/- 550
+/- 0.84 +/- 3.85
PLL_DELAY
RANGE
Total outpdelarange (lead/lag)
Minimum respulse width
1.8
—
PLL_RSTW
1. This conition aures thathe output phasitter will remain within specification. Jitter specification is based on optimized M, N and V set-
tings termined bhspLEVER software
2. Acmulatjitter measured over 10,000 waorm saples
45
Lattice Semiconductor
ispGDX2 Family Data Sheet
Boundary Scan Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min
40
2
20
8
Max
—
Units
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
TCK [BSCAN] clock pulse width
BTCP
TCK [BSCAN] clock pulse width high
—
ns
BTCPH
BTCPL
BTS
TCK [BSCAN] clock pulse width low
—
ns
TCK [BSCAN] setup time
—
ns
TCK [BSCAN] hold time
10
50
—
—
—
8
—
ns
BTH
TCK [BSCAN] rise/fall time
—
mV/ns
ns
BTRF
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to valid disable
TAP controller falling edge of clock to valid enable
BSCAN test capture register setup time
10
—
BTCO
ns
BTCODIS
BTCOEN
BTCRS
BTCRH
BUTCO
BTUODIS
BTUPOEN
ns
ns
BSCAN test capture register hold time
—
—
—
—
ns
BSCAN test update register, falling edge of clock o valid out
BSCAN test update register, falling edge of clk to vlid disable
BSCAN test update register, falling edge of clocvalid nable
2
25
25
ns
ns
ns
46
Lattice Semiconductor
ispGDX2 Family Data Sheet
Power Consumption
ICORE
IHSI
IPLL
200
90
80
100
IHSI_D
IPLL_D
70
60
50
40
30
20
10
0
80
150
100
50
60
40
2
0
IHSI_A
IPLL_A
0
0
200
400
600
800 1000 1200
0
50 100 150 200 250 300 350
0
200
400
600
MHz
Mbps
MHz
Power Estimation Coefficients – Core and PLL
Device
V
I
(mA)
K
K
K
LLA
CC
DC
REF
IN
CORE
LD
3.3
2.5
1.8
10.0
3.25
3.13
3.00
0139
0.292
.157
07
0.17
0.024
ispGDX2-256
10.0
4.0
0.0139
0213
0.292
0.239
0.024
0.024
I
:
Blank chip background curren
DC
K
K :
:
Reference voltage circuit cbank
I/O current per input per MH
REF
IN
K
K
K
:
Core current per MHz with GRout of 1
PLL logic current pr MHz per PLL
PLL analog poron urrent per MHz per PL
CORE
:
PLLD
:
PLLA
Power Estimation Coefficients – sysHSI
Device
V
K
K
K
K
K
TXA
CC
RXD
RXSTBY
XA
TXD
TXSTBY
3.3
25
1.
0.02
0.027
0.019
1.3
03
0.0023
0.0040
0.011
0.011
0.011
2.4
0.0018
0.0018
0.0023
ispGDX2-256
2.4
1.2
K
K
K
K
K
K
Receiver Logic urrent pps
Receiver Logstandby current
Receiver Anag porticurrent per Mbps
Transmtter Logicuent per Mbps
Tranmitter gic standby current
Transmitter Anlog portion current per Mbps
RXD
RXSTBY
:
:
RX
XD
:
STY
:
TXA
47
Lattice Semiconductor
ispGDX2 Family Data Sheet
Power Consumption (Continued)
Power consumption in the ispGDX2 family is the sum of three components:
I
= I
+ I
+ I
(I
combines current supplied via V pins and V pins)
CCP
CC-TOTAL
CORE
PLL
HSI CC-TOTAL
CC
I
= I + I
+ I
CORE
DC
REF IN
= Blank chip background current
+ K * Number of Banks with V
active
REF
REF
+ (K * Number of inputs + K
) * Average Input Switching Fquecy (MHz)
IN
CORE
I
I
= I
+ I
PLL
HSI
PLL_D PLL_A
= [K
* F
* Number of PLLs used] + [K
* F
Number of PLLs used]
PLLD
VCO
PLLA
VCO
= [(K
+ K
) * F
] * Number of PLLs used
PLLD
PLLA
VCO
= I + I
RX
TX
= [(K
+ K
) * F + I
] * Number of Receer Chnnels
RXD
RXA
RX
RXSTBY
+ [(K
+ K
) * F + I
] * Number of ansitter Channels
TXD
TXA
TX
TXSTBY
Where:
F
F
F
: sysClock PLL VCO Frequency in MHz
sysHSI Receiver Serial Data Rat
sysHSI Transmitter Serial Data
VCO
:
RX
:
TX
I
can also be determined by calculatig I
, turrent supplieby thV pin, and I the current sup-
HSI_A,
HSI
HSI_D
CC
plied by the V
and V
.
CCP0
CCP1
I
= I
+ I
HSI
HSI_D HSI_A
= [(K
* F + I
)* Number of Receer Chanls
RXD
R
RXSTBY
+ (K
* F + I
) * Number Transmter Channels]
TXD
XA
TX
TXSBY
+[(K
+
* F * Nmber of Receiver Cannels
RX
F ) * Number of Tr Chnnels]
TX
The I
is supplied throgh V
and V
LL and sysHSI analog portion. The equation for I
can
CCP
CCP0
CCP1
CCP
be derived frothe equations below.
I
= I
+ I
CCP
_A HSI_A
= [(K
* F
Numer of PLLs used]
PLLA
VC
+ [(K
* F ) * Number of Receiver Channels
RXA
X
+ (K
* F Numer of Transmitter Channels]
TXA
TX
Where:
I
I
: PPortion Current
: HSI ortion Current
PLL_A
HSI_A
Note: For further information about the use of these coefficients, refer to Technical Note TN1034, Power Estimation
in the ispGDX2 Family.
I
estimates are based on typical conditions. These values are for estimates only. Since the value of I
CC-
CC-TOTAL
is sensitive to operating conditions and the program in the device, the actual current should be verified.
TOTAL
48
Lattice Semiconductor
ispGDX2 Family Data Sheet
Switching Test Conditions
Figure 23 shows the output test load used for AC testing. Specific values for resistance, capacitance, voltage and
other test conditions are shown in Table 7.
Figure 23. Output Test Load, LVTTL and LVCMOS Standards (1.8V)
VCCO
R1
Device
Output
Test
Point
R2
CL*
*CL includes Test Fixture and Probe Capacitance.
Table 7. Test Fixture Required Components
Test Condition
C
TiminRef.
V
CCO
L
Default LVCMOS 1.8 I/O (L -> H, H -> L)
106
35pF
V
1.8V
LVCMOS3.3 = 3.0V
LVCMOS2.5 = 2.3V
LVCMOS1.8 = 1.65V
1.65V
CCO
VCMS3.3 = 1.5V
LVCMOS I/O (L -> H, H -> L)
—
—
35p
LVCOS2.5 = V
LVCMOS1.8 = V
/2
/2
CCO
CCO
Default LVCMOS 1.8 I/O (Z -> H)
Default LVCMOS 1.8 I/O (Z -> L
Default LVCMOS 1.8 I/O (-> Z)
Default LVCMOS 1.8 I/(L -> Z)
—
106
—
106
—
35pF
3pF
V
V
/2
/2
CCO
CCO
1.65V
1
—
V
- 0.15
+ 0.15
1.65V
OH
106
5pF
V
1.65V
OL
Note: Output test conditionall otheinterfaces are dehe respective standards.
49
Lattice Semiconductor
ispGDX2 Family Data Sheet
Signal Descriptions1
Signal Names
General Purpose
BKx_IOy
Description
Input/Output – General purpose I/O number y in I/O Bank X.
Input – Global clock/clock enable inputs.
GCLK/CE0, GCLK/CE1, GCLK/CE2,
GCLK/CE3
SEL0, SEL1, SEL22, SEL32
GOE0, GOE1, GOE22, GOE32
Input – Global MUX select inputs.
Input – Global output enable inputs.
Input – Global RESET signal (active low).
No connect.
RESETb
NC
GND
GND – Ground.
V
V
V
V
VCC – The power supply pins for ce log.
VCC – The power supply for the TAG gic.
VCC – The power supply pins for O BanX.
Input – Defines the reference oltafor I/O Bank X.
CC
CCJ
CCO
x
REF
x
Testing and Programming
TMS
Input – Test Mode elecinput, used to control the 1149state machine.
Input – Test Clock Inppin, sed to clock the 11.1 state machine.
Input – Tepin, ued to load data intdevicng 1149.1 state machine.
Output – Tut pin used to sha ouf device using 1149.1.
Input – Test OEnable pin. TOtristas all I/O pins when driven low.
TCK
TDI
TDO
TOE
PLL Functions
PLL_FBKz
PLL_RSTz
CLK_OUTz
Int – Optional feedback pallows exrnal feedback for PLL z.
Input Optional input resets the divider in PLL z.
Output – Optional clock tput from PLL z (clock signal occupies the input path of
is I/O pad).
PLL_LOCKz
Output – Optional lok output from PLL z (lock signal occupies the input path of this
I/O pad).
GND GND
GND – LLs.
P0,
P1
V
V
VCC – Tpply pins for PLLs.
CCP0, CCP1
FIFO Function
FIFOy_Nw
nput – DTA IN Bit w of FIFO y.
FIFODOUw
Iernal gnal – DATA OUT Bit w of FIFO y
Input – Reset input for FIFO y (active low).
utput – FULL flag for FIFO y.
FIFOy_FORST
FIFOy_FUL
FOy_MPTY
Output – EMPTY flag for FIFO y.
FIFOySTRDb
Output – Start read (STRDb) flag for FIFO y.
SERDES Functio
HSImA_SINP, HSImB
HSImA_SINN, HSImB_SIN
HSImA_SOUTP, HSImB_SOUTP
HSImA_SOUTN, HSImB_SOUTN
HSImA_SYDT, HSImB_ SYDT
HSImA_RECCLK, HSImB_RECCLK
Input – Positive sense serial input for sysHSI BLOCK m channel A, B.
Input – Negative (minus) sense serial input for sysHSI BLOCK m channel A, B.
Output – Positive sense serial output for sysHSI BLOCK m channel A, B.
Output – Negative (minus) sense serial output for sysHSI BLOCK m channel A, B.
Output – Symbol alignment detect for sysHSI BLOCK m channel A, B.
Internal Signal – Recovered clock for sysHSI BLOCK m channel A, B.
HSImA_CDRRSTb, HSImB_CDRRSTb Input – Resets the CDR circuit of sysHSI BLOCK m channel A, B.
HSIm_CSLOCK Output – LOCK output of the PLL associated with channel m.
50
Lattice Semiconductor
ispGDX2 Family Data Sheet
Signal Descriptions1 (Continued)
Signal Names
Description
HSImA_TXDw, HSImB_ TXDw
HSImA_RXDw, HSImB_ RXDw
Source Synchronous Functions
SS_SCLKIN0P, SS_SCLKIN1P
SS_SCLKIN0N, SS_SCLKIN1N
SS_CLKOUT0N, SS_CLKOUT1P
SS_CLKOUT0N, SS_CLKOUT1N
CAL
Internal Signal – Parallel data in bit w for sysHSI BLOCK m channel A, B.
Internal Signal – Parallel data out bit w for sysHSI BLOCK m channel A, B.
Input – Positive sense clock input for Source Synchronougrp A, .
Input – Negative (minus) sense clock input for Soure Synchronougroup A, B.
Output – Positive sense clock output for Source ynchnous group A, B.
Output – Negative (minus) sense clock output for Srce Schronous group A, B.
Input – Initiates source synchronous caliation seque.
1. m, w, x, y and z are variables.
2. Not on ispGDX2-64
ispGDX2-64 Power Supply and NC Connectios1
Signal
ispGDX2-64 (10BapBGA)2
V
V
V
V
V
V
V
V
V
V
A1, K10
CC
J7
CCO0
CCO1
CCO2
CCO3
CCO4
CCO
CCO6
CCO7
CCJ
F10
B
B4
E1
F1
K4
K1
G6
CCP0
GND
GND
G5
P0
C8, E6, E5, F6, F5, H3, J2
1. All grounds mully connected at the board level.
2. Pin orienttion Am the upper left corner of the top
side w with alphabetical order ascending vertically and
numical order scending horizontally.
51
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2 Power Supply and NC Connections1
Signal
ispGDX2-128 (208-Ball fpBGA)3
ispGDX2-256 (484-Ball fpBGA)3
V
B15, C14, R15, B2, C3, P3, R2,
AA3, AA20, B3, B20, C2, C11, C12, C21, H9, H10, H11,
H12, H13, H14, J8, J15, K8, K15, L8, L15, L20, M3, M8,
M15, M20, N8, N15, P8, P15, R9, 0, R11, R12, R13,
R14, Y2, Y11, Y12, Y21
CC
V
V
V
V
V
V
V
V
V
V
V
N11, T12
L13, M16
E16, F13
A12, D11
A5, D6
E1, F4
L4, M1
N6, T5
P14
AA14, AB20, Y17
P21, U20, Y22
C22, E20, J21
A20, B14, C17
A3, B9, C6
C1, F3, J2
P2, U3, Y1
AA9, A3, Y6
3
CCO0
CCO1
CCO2
CCO3
CCO4
CCO5
CCO6
CCO7
CCJ
J1
K1
CCP0
CCP1
J16
22
GND
GND
GND
H1
J1
P0
P1
H16
22
A16, D13, H15, J15, N13, T16, A1, B9, J2, A2, A11, A12, A21, , A22, AA1, AA2, AA11, AA12,
N4, R8, R9, T1, G7, G8, G9, G10, H7, H8J7, AA21, AA22AB11, AB12, AB21, AB22, B1,
J8, J9, J10, K7, K8, K9, K10
B2, B11B12, 21, B22, C3, C20, D4, D19, E5, E18, F6,
F17, G7, 6, HH15, J9, J10, J11, J12, J13, J14, K9,
K1K11, K, K13, K14, L1, L2, L7, L9, L10, L11, L12,
13L14,L16, 1, L22, M1, M2, M7, M9, M10, M11,
M12,3, M14, M16, M21, M22, N9, N10, N11, N12,
N13, N1P9, P10, P11, P12, P13, P14, R8, R15, T7,
16, U6, U17, V5, V18, W4, W19,Y3, Y20
NC2
A11, B16
D11, E6, E7, E8, E9, E12, E13, E14, E15, E16, F7,
F16, G5, G6, G18, G19, H19, K4, K19, L19, M4, M19,
N4, P4, P19, R4, R18, T4, T5, T17, T18, U5, U7, U16, V7,
V8, V9, V10, V11, V12, V15, V16, V17, W14, Y18
1. All grounds must be electrily onnected at the boar
2. NC pins shonot be connected to any activnals, V ND.
3. Pin orienation starts fm the upper left orner of the top side view with alphabetical order ascending vertically and numerical order
ascening horizonlly.
52
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-64 Logic Signal Connections
sysIO
LVDS
GDX
SERDES Mode
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
100
Signal Name
GOE0
Bank Pair/Polarity Block MRB
I/O Pin1
fpBGA
-
-
-
-
0
1
-
-
-
-
H6
J6
BK0_IO0/PLL_LOCK0
BK0_IO1
GND
0
0
0
0
0
0
0
0
0
0
0
-
0N
0P
-
0A
0A
-
-
-
F0_FULL
HSI0A_CDRRSTb
-
FFO0_FRSTb
K6
-
-
-
-
-
GND
G7
BK0_IO2
BK0_IO3
GND
1N
1P
-
0A
0A
-
2
3
-
HSI0A_SINN
HSI0A_RECCL
HSI0A_SINP
-
-
H7
-
GND
K7
BK0_IO4/PLL_RST0
BK0_IO5
BK0_IO6
BK0_IO7
GND
2N
2P
3N
3P
-
0A
0A
0A
0A
-
4
5
6
7
-
-
HSI0ARXD0/TXD0 FO0_DIN0/DOUT0
HSI0ARXD1/TXFIFO0_DIN1/
H0A_RD2/T2 FIFO0_DI
HSI0RXD3/TXD3 FIFO0DIN3/
-
K8
-
J8
Note 4
K9
-
-
-
-
-
-
GND
J10
J9
TCK
-
-
-
-
RESETb
-
-
-
-
-
BK1_IO0/PLL_FBK0
BK1_IO1
BK1_IO2
BK1_IO3/VREF(0,1)
GND
1
1
1
1
1
1
1
1
1
1
-
4P
4N
5P
5N
-
0A
0A
0A
0A
-
8
9
-
I0A_YDT5
HSI0A_RXD4/TXD4 O0_DN4/DOUT4
HSI0A_RXD5/TD5 FIF0_DIN5/DOUT5
HSI0A_RX/TXDFO0_DIN6/DOUT6
HSIA_RXD7/D7 FIFO0_DIN7/DOUT7
H10
H9
-
-
H8
0_STRDb6
G10
GND
G9
-
-
-
BK1_IO4
BK1_IO5
GND
6P
6N
0A
0A
12
13
HSI0A_SOUTP
H0A_R8/TXD8 FIFO0_DIN8/DOUT8
HSI0RXD9/TXD9 FIFO0_DIN9/DOUT9
HSI0A_SOU
G8
-
-
-
GND
F9
BK1_IO6
BK1_IO7
GCLK/CE2
GCLK/CE3
BK2_IO0
BK2_IO1
GND
7P
7N
0A
0A
-
14
15
-
SS_KIN1P
HSI0A_SYDT5
-
SS_CLK1N
-
FIFO0_ EMPTY
F8
K2P
CLK2N
8N
-
-
F7
-
-
-
-
-
-
E7
2
2
2
2
2
2
2
3
3
3
3
3
3
3
0B
0B
_CLKUT0N
-
FIFO1_FULL
E8
8P
CLKOUT0P
-
FIFO1_EMPTY
E9
-
-
-
-
GND
D8
BK2_IO2
BK2_IO
GND
9N
0B
0B
2
HSI0B_SOUTN
HSI0BA_SYDT5
HSI0B_RXD0/TXD0
-
-
9P
3
HSI0B_SOUTP
FIFO1_DIN0
-
D9
-
-
GND
D10
C9
_IO4/
BK2_I5
2_IO6
BK_I
BK3_IO0
BK3_IO1
BK3_IO2
BK3_IO3
GND
(2)
10N
10P
11N
1P
12P
12N
13P
13N
-
0B
0B
0B
0B
0B
0B
0B
0B
-
4
-
HSI0B_RXD1/TXD1 FIFO1_DIN1/DOUT1
HSI0B_RXD2/TXD2 FIFO1_DIN2/DOUT2
HSI0B_RXD3/TXD3 FIFO1_DIN3/DOUT3
HSI0B_RXD4/TXD4 FIFO1_DIN4/DOUT4
HSI0B_RXD5/TXD5 FIFO1_DIN5/DOUT5
HSI0B_RXD6/TXD6 FIFO1_DIN6/DOUT6
HSI0B_RXD7/TXD7 FIFO1_DIN7/DOUT7
HSI0B_RXD8/TXD8 FIFO1_DIN8/DOUT8
F
5
-
6
HSI0_CSLOCK
Note 4
C10
B10
A9
7
8
-
9
HSI0B_SYDT5
B8
10
11
-
A8
-
A7
-
-
-
GND
C7
BK3_IO4
BK3_IO5
GND
14P
14N
-
0B
0B
-
12
13
-
HSI0B_SINP
HSI0B_SINN
-
HSI0B_RXD9/TXD9 FIFO1_DIN9/DOUT9
HSI0B_RECCLK
-
D7
-
-
-
-
GND
B6
BK3_IO6
15P
15N
0B
0B
14
FIFO1_STRDb6
-
BK3_IO7/CLK_OUT0
15 HSI0B_CDRRSTb
FIFO1_FIFORSTb
C6
53
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-64 Logic Signal Connections (Continued)
sysIO
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
100
fpBGA
Signal Name
Bank Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
SEL0
SEL1
-
-
-
-
-
-
-
-
D6
D5
-
-
-
-
-
-
BK4_IO0/CLK_OUT2
BK4_IO1
GND
4
4
4
4
4
4
4
4
4
4
-
16N
16P
-
1A7
1A7
-
1A7
1A7
0
1
-
HSI1A_CDRRSTb
FIFO2_STRDb6
-
FFO2_FIFORSTb
C5
-
-
-
-
B5
-
-
GND
D4
BK4_IO2
BK4_IO3
GND
17N
17P
2
3
HSI1A_SINN
HSI1A_RECCK
HSI1A_SINP
HSI1A_RXD9/TXDFIFO_DIN9/DOUT9
C4
-
-
-
GND
A6
BK4_IO4
BK4_IO5
BK4_IO6
BK4_IO7
TMS
18N
18P
19N
19P
1A7
1A7
1A7
1A7
-
4
5
-
HSI1ARXD8/TXFIFO2_DIN8/D
1A_D7/TX7 FIFO2_DI
HSI1_RXD6/TXD6 FIFO2_DIN6
SI1A_D5/TXD5 FIF2_DIN5/DO
CAL
HSI1A_SYDT5
A5
6
A4
7
-
A3
-
-
-
-
-
-
-
-
-
-
-
B3
TDI
-
-
-
-
-
-
A2
GND
-
-
-
-
GND
B1
TDO
-
-
-
-
-
TOE
-
-
-
B2
BK5_IO0
BK5_IO1
BK5_IO2
BK5_IO3/Vref(4,5)
GND
5
5
5
5
5
5
5
5
5
5
20P
20N
21P
21N
-
1A7
1A7
1A7
1A7
1A
1A7
-
Note 4
HSI1A_RXD4XD4 FIFO2_DIN4/DOUT4
HSI1XDFIFO2_DIN3/DOUT3
1A_RD2/TXD2 FIFO2_DIN2/DOUT2
HSI1_RXD1/TXD1 FIFO2_DIN1/DOUT1
C1
_CSLOCK
C2
10
11
-
-
C3
-
D1
-
-
-
GND
D3
BK5_IO4
BK5_IO5
GND
P
22N
-
12
13
HSI1SOUTP
SI1A_RXD0/TXD0 FIFO2_DIN0/DOUT0
HSI1A_SUTN
HSI1A_SYDT5
-
D2
-
-
GND
E2
BK5_IO6
BK5_IO7
GCLK/CE0
GCLK/CE1
BK6_IO0
BK6_IO
GND
23
23N
LK0P
CLK0N
24N
24P
1A7
1A7
-
14
SSLKIN1P
-
FIFO2_EMPTY
S_CLIN1N
-
FIFO2_FULL
E3
-
-
-
E4
-
-
-
-
-
F4
6
6
6
6
6
6
7
7
7
7
7
7
7
1B
1B
-
0
SS_CLKOUT1N
-
FIFO3_EMPTY
F3
1
SS_CLKOUT1P
HSI1B_SYDT5
-
-
F2
-
-
-
GND
G3
G2
GND
G1
H1
BK6_IO2
BK6_IO3
D
25N
P
-
1B
1B
-
2
HSI1B_SOUTN
HSI1B_RXD9/TXD9 FIFO3_DIN9/DOUT9
HSI1B_RXD8/TXD8 FIFO3_DIN8/DOUT8
3
HSI1B_SOUTP
-
-
-
-
BK6_IO/Vref(Bank6,7)
BK6_IO5
BK6_IO6
BK6_IO7/PLL_FBK2
BK7_IO0
BK7_IO1
BK7_IO2
BK7_IO3/PLL_RST2
GND
6N
26P
27N
27P
28P
28N
29P
29N
-
1B
1B
1B
1B
1B
1B
1B
1B
-
4
FIFO3_STRDb6
HSI1B_RXD7/TXD7 FIFO3_DIN7/DOUT7
HSI1B_RXD6/TXD6 FIFO3_DIN6/DOUT6
HSI1B_RXD5/TXD5 FIFO3_DIN5/DOUT5
HSI1B_RXD4/TXD4 FIFO3_DIN4/DOUT4
HSI1B_RXD3/TXD3 FIFO3_DIN3/DOUT3
HSI1B_RXD2/TXD2 FIFO3_DIN2/DOUT2
HSI1B_RXD1/TXD1 FIFO3_DIN1/DOUT1
HSI1B_RXD0/TXD0 FIFO3_DIN0/DOUT0
5
-
6
-
H2
7
HSI1B_SYDT5
J1
8
Note 4
J3
9
-
K2
10
11
-
-
J4
-
K3
-
-
-
-
-
GND
G4
H4
BK7_IO4
BK7_IO5
30P
30N
1B
1B
12
13
HSI1B_SINP
HSI1B_SINN
-
HSI1B_RECCLK
54
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-64 Logic Signal Connections (Continued)
sysIO
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
100
fpBGA
Signal Name
Bank Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
GND
7
7
7
7
-
-
-
-
-
-
-
-
-
FIFOFIFORSTb
FIFO3_FULL
-
GND
K5
BK7_IO6
31P
31N
-
1B
1B
-
14 HSI1B_CDRRSTb
BK7_IO7/PLL_LOCK2
GOE1
15
-
-
-
J5
H5
1. The signals in this column route to/from the assigned pins of the associated I/O cell.
2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associatpin ivailable for output only. When
transmit data (TXD) is present in the cell, the associated pin is available for input only.
3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs routeirecrom the associated pins in
FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to tassociated pithrough the output MUX and
the pins.
4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable or aner use ad must be left un
5. The SYDT signal has two routing options. If direct output through the dedicated pin is ed, t/O ell (the whole HSavail-
able for transmitter. The SYDT in the I/O Cell column is routed to the GRP throughe int register of the cell anfrees for
transmitter.
6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only.
7. sysHSI Source Synchronous Receive Mode is not available for chann1A.
55
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-128 Logic Signal Connections
sysIO
LVDS
GDX
SERDES Mode
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
208
fpBGA
Signal Name
Bank Pair/Polarity Block MRB
I/O Pin1
TOE
-
-
-
-
-
-
-
-
-
-
P8
P9
BK0_IO0
BK0_IO1
0
0
0N
0P
0A
0A
0
1
O0A_FULL
T10
BK0_IO2 / PLL_LOCK2 /
PLL_RST2
0
1N
1P
0A
2
-
-
-
R10
BK0_IO3
GND
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
0A
-
3
-
-
HSI0A_SY5
-
FIFO0A_ EMPTY
-
T11
-
GND
BK0_IO4
BK0_IO5
BK0_IO6
BK0_IO7
BK0_IO8
BK0_IO9 / PLL_FB2
BK0_IO10
BK0_IO11
GND
2N
2P
3N
3P
4N
4P
5N
5P
0A
0A
4
HSI0A_SINN
HSI0ARXD0/TXD0 FO0A_DIN0/DOUT0 P10
HSI0_RXD1/T1 FIFO0A_DIN1/UT1 N10
SI0AXD2/TD2 FIFO0A_DR11
HSA_RXD3/TXD3 FIFO0A_DIT13
HSI0AXD4/TXD4 FIF0A_DIN4/4 P11
SI0A_RXD5/TXD5 FO0ADIN5/DOUT5 R12
I0A_RXD6/TXDFIFA_DINDOUT6 P12
HSI0A_RXD7/TXD7 FIFO0IN7/DOUT7 N12
5
HSI0A_SINP
6
-
0A
0A
0A
0A
0A
-
7
-
8
Note 4
9
-
10
11
-
HSI0_SOUTN
H0A_SUTP
-
-
GND
BK0_IO12
BK0_IO13
BK0_IO14
BK0_IO15 / VREF0
GOE3
6N
6P
7N
7P
0A
0A
0A
0A
-
1
HSI0A_D8/T8 FIO0A_DIN8/DOUT8 T14
HSI0A_RXDTXD9 FIFO0A_DIN9/DOUT9 R13
0A_SYDT5
_CDRRSTb
H
FIFO0A_FIFORSTb
T15
P13
T9
15
-
O0A_STRDb6
-
-
-
-
-
TDO
-
-
-
-
-
-
R16
GND
N14
GND
1
1
1
1
1
1
1
1
1
1
1
1
1
-
-
-
-
-
-
BK1_IO0 / VREF1
BK1_IO1
BK1_IO2
BK1_IO3
BK1_IO4
BK1_IO5
BK1_IO6
BK1_IO7
BK1_I
BK1_IO9
BK1_IO10
BIO1
GND
8P
8N
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
-
0
-
HSI0B_SYDT5
FIFO0B_FULL
1
-
HSI0B_RXD0/TXD0 FIFO0B_DIN0/DOUT0 P15
HSI0B_RXD1/TXD1 FIFO0B_DIN1/DOUT1 N15
HSI0B_RXD2/TXD2 FIFO0B_DIN2/DOUT2 L14
HSI0B_RXD3/TXD3 FIFO0B_DIN3/DOUT3 M14
HSI0B_RXD4/TXD4 FIFO0B_DIN4/DOUT4 M13
HSI0B_RXD5/TXD5 FIFO0B_DIN5/DOUT5 M15
HSI0B_RXD6/TXD6 FIFO0B_DIN6/DOUT6 L15
HSI0B_RXD7/TXD7 FIFO0B_DIN7/DOUT7 P16
HSI0B_RXD8/TXD8 FIFO0B_DIN8/DOUT8 N16
HSI0B_RXD9/TXD9 FIFO0B_DIN9/DOUT9 K14
2
ote 4
9N
10P
10N
11P
11N
12P
12N
13N
0B_SOUTP
0B_SOUTN
HSI0_CSLOCK
HSI0B_SYDT5
-
6
7
8
9
-
10
11
-
HSI0B_SINP
HSI0B_SINN
-
HSI0B_RECCLK
-
K13
GND
K15
L16
J14
J13
N8
-
-
-
BK1_IO12
BK1_IO13
BK1_IO14
BK1_IO15 / CLK_OUT2
GCLK/CE2
SEL2
4P
14N
15P
15N
0B
0B
0B
0B
-
12
FIFO0B_STRDb6
-
13 HSI0B_CDRRSTb
-
FIFO0B_FIFORSTb
14
15
-
SS_CLKIN1P
-
-
SS_CLKIN1N
-
FIFO0B_ EMPTY
-
-
-
-
-
-
-
-
-
K16
G16
N9
SEL3
-
-
-
-
-
-
GCLK/CE3
BK2_IO0
BK2_IO1
BK2_IO2
-
-
-
-
-
-
2
2
2
16N
16P
17N
1A7
1A7
1A7
0
1
2
SS_CLKOUT1N
SS_CLKOUT1P
-
-
FIFO1A_FULL
H13
H14
G15
-
-
-
HSI1A_SYDT5
56
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-128 Logic Signal Connections (Continued)
sysIO
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
208
Signal Name
BK2_IO3
Bank Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
fpBGA
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-
17P
1A7
-
3
-
-
HSI1A_RXD0/TXD0 FIFO1A_DIN0/DOUT0 F16
GND
GND
-
-
-
BK2_IO4
BK2_IO5
BK2_IO6
BK2_IO7
BK2_IO8
BK2_IO9
BK2_IO10
BK2_IO11
GND
18N
18P
19N
19P
20N
20P
21N
21P
1A7
1A7
1A7
1A7
1A7
1A7
1A7
1A7
-
1A7
1A7
1A7
1A7
-
4
HSI1A_SINN
HSI1A_SINP
HSI1_CSLOCK
Note 4
HSI1A_RXD1/TXD1 FO1A_DIN1/DOUT1 G13
HSI1A_RXD2/TXD2 FIA_DINDOUT2 G14
HSI1A_RXD3/TX3 FIFO1A_D3/DOUT3 F14
HSI1A_RXD4D4 FIFO1A_DIN4/DOUT4 F15
HSI1A_RXD5/TXFIF1A_DIN5/DOUT5 D16
HSI1RXD6/TXD6 IFO1A_DIN6/DOUT6 E15
HSI1_RXD7/T7 FIFO1A_DINT7 E13
SI1AXD8/TD8 FIFO1A_E14
5
6
7
8
CAL
9
-
10
11
-
HSI1A_SOUTN
HSI1A_SOUTP
-
-
-
GND
BK2_IO12
BK2_IO13
BK2_IO14
BK2_IO15 / VREF2
TCK
22N
22P
23N
23P
12
HSI1A_SYDT5
HSI1AXD9/TXD9 FIO1A_DIN9/9 C16
13 HSI1A_CDRRb
HSI1A_RECCLK
IFO_FIFORSTb
D15
C15
D14
R14
A9
14
15
-
FIFOA_STRDb6
-
-
-
-
-
FIFO_EMPTY
-
-
GOE2
-
-
BK3_IO0 / VREF3
BK3_IO1
BK3_IO2
BK3_IO3
GND
3
3
3
3
3
3
3
3
24P
24N
25P
25N
1B
1B
1B
1B
1
2
3
-
-
HSI1B_RXDXD0 FIFO1B_DIN0/DOUT0 C13
HSIRXD1 FIFO1B_DIN1/DOUT1 B14
SI1B_XD2/TXD2 FIFO1B_DIN2/DOUT2 A15
HS_RXD3/TXD3 FIFO1B_DIN3/DOUT3 B13
Note 4
-
-
-
-
-
GND
BK3_IO4
BK3_IO5
BK3_IO6
BK3_IO7
6
26N
27P
1B
1B
1B
4
5
6
HSI1BSOUTP
HSI1B_SUTN
HSI1B_RXD4/TXD4 FIFO1B_DIN4/DOUT4 D12
HSI1B_RXD5/TXD5 FIFO1B_DIN5/DOUT5 C12
HSI1B_RXD6/TXD6 FIFO1B_DIN6/DOUT6 A14
FIFO1B_DIN7/DOUT7
3
27N
1B
-
HSI1B_RXD7/TXD7
A13
/ FIFO1B_STRDb
BK3_IO8
BK3_IO9
BK3_IO10
BK3_IO11
GND
3
3
3
3
3
3
3
3
8P
28N
29P
29N
1B
1B
1B
1B
-
-
HSI1B_RXD8/TXD8 FIFO1B_DIN8/DOUT8 B12
HSI1B_RXD9/TXD9 FIFO1B_DIN9/DOUT9 C11
I1B_SYDT5
10
11
-
HSI1B_SINP
HSI1B_RECCLK
-
D10
C10
GND
B11
B10
A10
C9
HSI1B_SINN
-
-
-
-
-
-
BK3_IO1
BK3_IO13
BKO
BK3_IO1
RESET
30P
3
31P
31N
1B
1B
1B
1B
-
12
HSI1B_SYDT5
FIFO1B_FULL
FIFO1B_FIFORSTb
-
13 HSI1B_CDRRSTb
-
-
-
-
-
14
15
-
-
-
-
-
FIFO1B_ EMPTY
-
A7
BK4_IO0
32N
32P
2A
0
FIFO2A_EMPTY
C8
BK4_IO1 / PLL_LOCK0 /
PLL_RST0
2A
1
-
-
-
B7
BK4_IO2
BK4_IO3
GND
4
4
4
4
4
4
4
33N
33P
2A
2A
2
3
HSI2A_CDRRSTb
-
FIFO2A_FIFORSTb
A6
B6
-
HSI2A_SYDT5
FIFO2A_FULL
-
-
-
-
-
GND
C7
BK4_IO4
BK4_IO5
BK4_IO6
BK4_IO7
34N
34P
35N
35P
2A
2A
2A
2A
4
5
6
7
HSI2A_SINN
HSI2A_SINP
HSI2A_SYDT5
-
-
HSI2A_RECCLK
D7
HSI2A_RXD9/TXD9 FIFO2A_DIN9/DOUT9 C6
HSI2A_RXD8/TXD8 FIFO2A_DIN8/DOUT8 B5
57
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-128 Logic Signal Connections (Continued)
sysIO
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
208
Signal Name
BK4_IO8
Bank Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
fpBGA
4
4
4
4
4
4
4
4
4
-
36N
36P
37N
37P
2A
2A
2A
2A
8
9
FIFO2A_STRDb6
HSI2A_RXD7/TXD7 FIFO2A_DIN7/DOUT7 A4
HSI2A_RXD6/TXD6 FIFO_DIN6/DOUT6 A3
HSI2A_RXD5/TXD5 FO2A_DIN5/DOUT5 C5
HSI2A_RXD4/TXD4 FIA_DINDOUT4 D5
BK4_IO9 / PLL_FB0
BK4_IO10
BK4_IO11
GND
-
10
11
-
HSI2A_SOUTN
HSI2A_SOUTP
-
-
GND
BK4_IO12
BK4_IO13
BK4_IO14
BK4_IO15 / VREF4
GOE1
38N
38P
39N
39P
2A
2A
2A
2A
12
13
14
15
-
-
HSI2A_RXD3D3 FIFO2A_DIN3/DOUT3 B4
HSI2A_RXD2/TXFIF2A_DIN2/DOUT2 A2
HSI2RXD1/TXD1 IFO2A_DIN1/DOUT1 B3
HSI2_RXD0/T0 FIFO2A_DINT0 C4
-
Note 4
-
-
-
A8
R1
TMS
-
-
-
-
-
-
GND
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
-
-
-
-
-
GND
D3
BK5_IO0 / VREF5
BK5_IO1
BK5_IO2
BK5_IO3
BK5_IO4
BK5_IO5
BK5_IO6
BK5_IO7
BK5_IO8
BK5_IO9
BK5_IO10
BK5_IO11
GND
40P
40N
41P
41N
42P
42N
43P
43N
44P
44N
5
45N
2B
2B
2B
2B
2B
2B
2B
2B
2B
B
2B
2B
-
0
-
-
FIF2B_EMPTY
-
1
FIFOB_STRDb6
-
C2
2
HB_CRSTb
HSISYDT
HSI2B_RECCLK
FIFO2FIFORSTb
D2
3
HSI2B_RXD9XD9 FIO2B_DIN9/DOUT9 B1
HSI2B_RD8/TXFO2B_DIN8/DOUT8 E3
HSI2B_RXDXD7 FIFO2B_DIN7/DOUT7 E4
HSIRXD6 FIFO2B_DIN6/DOUT6 F3
SI2B_XD5/TXD5 FIFO2B_DIN5/DOUT5 E2
HS_RXD4/TXD4 FIFO2B_DIN4/DOUT4 F2
HSI2BRXD3/TXD3 FIFO2B_DIN3/DOUT3 C1
HSI2B_RXD2/TXD2 FIFO2B_DIN2/DOUT2 G3
HSI2B_RXD1/TXD1 FIFO2B_DIN1/DOUT1 G4
I2B_TP
B_SOUTN
6
-
7
-
8
Note 4
9
HSI2_CSOC
10
11
-
HSI2_SINP
HSI2B_NN
-
-
GND
BK5_IO12
BK5_IO13
BK5_IO14
BK5_IO15 / CLK_OUT0
GCLK/CE0
SEL0
4
46N
2B
2B
2B
2B
-
12
-
-
HSI2B_RXD0/TXD0 FIFO2B_DIN0/DOUT0 D1
HSI2B_SYDT5
-
G2
H4
H3
D9
F1
47P
_CLKIN0P
-
-
47N
S_CLKIN0N
-
FIFO2B_FULL
CLK0P
-
-
-
-
-
-
-
-
-
SEL1
-
-
-
-
-
-
G1
D8
J4
GCLK/CE
BK6_IO0
6_IO1
BK6_IO
BK6_IO3
GND
-
CLK0N
N
-
-
-
-
-
6
6
6
6
6
6
6
6
6
3A
3A
3A
3A
-
0
SS_CLKOUT0N
SS_CLKOUT0P
HSI3A_CDRRSTb
FIFO3A_STRDb6
-
-
FIFO3A_EMPTY
48
1
-
-
J3
49N
2
-
FIFO3A_FIFORSTb
K1
K2
GND
K4
49P
3
-
-
-
-
-
-
BK6_IO4
BK6_IO5
BK6_IO6
BK6_IO7
BK6_IO8
BK6_IO9
BK6_IO10
BK6_IO11
50N
50P
51N
51P
52N
52P
53N
53P
3A
3A
3A
3A
3A
3A
3A
3A
4
HSI3A_SINN
HSI3A_SINP
-
HSI3A_RECCLK
5
HSI3A_RXD9/TXD9 FIFO3A_DIN9/DOUT9 K3
HSI3A_RXD8/TXD8 FIFO3A_DIN8/DOUT8 L1
HSI3A_RXD7/TXD7 FIFO3A_DIN7/DOUT7 L2
HSI3A_RXD6/TXD6 FIFO3A_DIN6/DOUT6 N1
HSI3A_RXD5/TXD5 FIFO3A_DIN5/DOUT5 M2
HSI3A_RXD4/TXD4 FIFO3A_DIN4/DOUT4 M4
HSI3A_RXD3/TXD3 FIFO3A_DIN3/DOUT3 M3
6
7
-
8
HSI3A_SYDT5
HSI3_CSLOCK
HSI3A_SOUTN
HSI3A_SOUTP
9
10
11
58
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-128 Logic Signal Connections (Continued)
sysIO
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
208
fpBGA
Signal Name
Bank Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
GND
6
6
6
6
6
-
-
-
12
13
14
15
-
-
-
-
GND
BK6_IO12
BK6_IO13
BK6_IO14
BK6_IO15 / VREF6
TDI
54N
54P
55N
55P
3A
3A
3A
3A
-
-
HSI3A_RXD2/TXD2 FIFO_DIN2/DOUT2 L3
HSI3A_RXD1/TXD1 FO3A_DIN1/DOUT1 N2
HSI3A_RXD0/TXD0 FIA_DINDOUT0 P1
Note 4
-
-
HSI3A_SYDT
FIFO3FULL
P2
N3
-
-
-
GOE0
-
-
-
-
-
-
T8
GND
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
GND
T2
BK7_IO0 / VREF7
BK7_IO1
BK7_IO2
BK7_IO3
BK7_IO4
BK7_IO5
BK7_IO6
BK7_IO7
BK7_IO8
BK7_IO9
BK7_IO10
BK7_IO11
GND
56P
56N
57P
57N
58P
58N
59P
59N
60P
60N
61P
61N
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
-
0
FIFO3B_STRDb6
-
-
1
HSI3B_CDRRSTb
HSI3B_SYDT5
HSI3RECCK
FIFO3B
R3
2
HS_RXD9/TXD9 FIFO3B_DIP4
HSI3BXD8/TXD8 FIO3B_DIN8/8 T3
SI3B_RXD7/TXD7 O3_DIN7/DOUT7 N5
I3B_RXD6/TXDFIFB_DI/DOUT6 P5
HSI3B_RXD5/TXD5 IFO3BIN5/DOUT5 R4
HSI3B_RXD4XD4 FIO3B_DIN4/DOUT4 T4
HSI3B_RD3/TXFO3B_DIN3/DOUT3 R5
HSI3B_RXDXD2 FIFO3B_DIN2/DOUT2 P6
HSIRXD1 FIFO3B_DIN1/DOUT1 N7
SI3B_XD0/TXD0 FIFO3B_DIN0/DOUT0 P7
3
-
4
HSI3B_SOU
5
HSI_SOUTN
6
-
7
e 4
-
1
11
-
3B_SINP
HSI3B_SINN
-
-
-
-
-
GND
R6
BK7_IO12
BK7_IO13
BK7_IO14
BK7_IO15
62P
2
63P
63N
B
3B
3B
3B
12
13
14
15
HSIB_SYDT5
FIFO3B_ EMPTY
-
-
-
-
T6
-
R7
FIFO3B_FULL
T7
1. The signals in this columroute to/froassigned pins of the assiated I/O cell.
2. The signals in this con usthe I/O cell. If a receiver esenn the I/O cell, the associated pin is available for output only. When
transmit data (TXD) is pnt in thcell, the associatable for input only.
3. The DOUT outputs are roud to RP through the inphe cell and the DIN inputs are routed direct from the associated pins in
FIFO only me. In SERDES ith FIFO mode, tFULL TY flags are routed to the associated pins through the output MUX and
the pins.
4. If the Surce Synronos Receiver is usen the HSI lock, this pin is unavailable for another use and must be left unconnected.
5. The YDT snal hawo routing options. If ect outpthrough the dedicated pin is used, the I/O cell (the whole HSI Block) is not avail-
able r trsmitter. The SYDT in thCell cmn routed to the GRP through the input register of the cell and frees the I/O cell for
transmr.
6. FIFO_STflag output is used SDES ith FIFO Mode only.
7. sSource Synchronoueceive Mode not available for channel 1A.
59
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections
Signal
Name
sysIO
Bank
LVDS
GDX
SERDES Mode
SERDES Mode
I/O Cell2
FIFO Mode I/O
Cell/Pin3
484
fpBGA
Pair/Polarity Block MRB
I/O Pin1
BK0_IO0
BK0_IO1
0
0
0N
0P
0A
0A
0
1
-
-
-
-
FIFO0A_FULL
AB13
AA13
BK0_IO2/
PLL_LOCK2
0
1N
0A
2
-
-
V13
BK0_IO3
GND
0
0
0
0
0
0
0
1P
-
0A
-
3
-
-
-
FIFO0A_ EMTY
-
V14
GND
U12
U13
W12
Y13
-
SYDT_HSI0A5
BK0_IO4
BK0_IO5
BK0_IO6
BK0_IO7
BK0_IO8
2N
2P
3N
3P
4N
0A
0A
4
5
6
7
8
HSI0A_SINN
HSI0A_RXD0/TXD0
HSI0A_RXD1XD1
HSI0A_RXDTXD2
HSI0ARXD3XD3
HSA_R4/TXD4
IFO0ADIN0/DOUT0
0A_DIN1/DOUT1
FIFO0A_DIN2/DO2
FIFO0A_DIN3
FIFO0A_DIN4/
HSI0A_SINP
-
0A
0A
-
Note 4
W13
BK0_IO9/
PLL_FB2
0
4P
0A
9
-
HSI0RXD5/D5
FIFOA_DIN5/DOU
Y14
BK0_IO10
BK0_IO11
GND
0
0
0
0
0
0
0
0
5N
5P
-
0A
0A
-
10
11
-
HSI0A_SOUTN
HAXD6/TXD6
FIFO_IN6/DOUT6
O0A_N7OUT7
-
T12
T13
HSI0A_SOP
HSI0A_RXD7/TXD7
-
-
GND
AB14
AB15
Y15
BK0_IO12
BK0_IO13
BK0_IO14
BK0_IO15
BK0_IO16
6N
6P
7N
7P
8N
0A
0A
0A
0A
1A
12
13
14
15
0
-
SI0A_RXD8/TXD8
FIFO_DIN8/DOUT8
0A_DIN9/DOUT9
FIFO0A_FIFORSTb
-
T5
HTb
FIFODb6
-
HSI0A_RXD9/TX
HSI0A_LK
-
W15
AA15
FIFO1A_FULL
BK0_IO17/
PLL_RST2
0
8P
1A
-
-
-
AA16
BK0_IO18
BK0_IO19
GND
0
0
0
0
9N
9P
-
1A
1A
-
2
3
-
-
HA_SYDT5
HSI1A_RXD0/TXD0
-
-
Y16
W16
GND
U14
-
FIFO1A_DIN0/DOUT0
-
-
BK0_IO20
10N
4
HSI1A_SOU
HSI1A_RXD1/TXD1
FIFO1A_DIN1/DOUT1
BK0_IO21/
VREF0
0
P
1A
5
TP
HSI1A_RXD2/TXD2
FIFO1A_DIN2/DOUT2
U15
BK0_IO22
BK0_IO23
BK0_IO2
BK0_I5
BK0_IO
BK0_IO27
BKO
BK0_IO
BK0_IO30
BK0_IO31
GND
0
0
0
0
0
0
0
0
0
0
-
1
11P
12N
12P
13N
13P
14
14P
1A
1A
1A
1A
1A
A
1A
1A
1A
1A
-
6
7
HSI1A_RXD3/TXD3
FIFO1A_DIN3/DOUT3
AB16
AB17
AA17
W17
T14
4
HSI1A_RXD4/TXD4
FIFO1A_DIN4/DOUT4
8
-
HSI1A_RXD5/TXD5
FIFO1A_DIN5/DOUT5
9
-
HSI1A_RXD6/TXD6
FIFO1A_DIN6/DOUT6
10
11
12
13
14
15
-
HSI1A_SINN
HSI1A_RXD7/TXD7
FIFO1A_DIN7/DOUT7
HSI1A_SINP
HSI1A_SYDT5
HSI1A_CDRRSTb5
FIFO1A_STRDb6
HSI1A_RXD8/TXD8
FIFO1A_DIN8/DOUT8
T15
HSI1A_RXD9/TXD9
FIFO1A_DIN9/DOUT9
AA18
AB18
W18
Y19
HSI1A_RECCLK
FIFO1A_FIFORSTb
-
-
-
-
FIFO1A_EMPTY
-
-
-
GND
AA19
AB19
GND
W21
W20
V22
GOE3
-
-
-
-
-
-
TDO
-
-
-
-
-
-
-
GND
1
1
1
1
1
1
-
-
-
-
-
-
BK1_IO0
BK1_IO1
BK1_IO2
BK1_IO3
BK1_IO4
16P
16N
17P
17N
18P
0B
0B
0B
0B
0B
0
-
-
FIFO0B_ FULL
-
1
-
-
HSI0B_SYDT5
HSI0B_RXD0/TXD0
HSI0B_RXD1/TXD1
HSI0B_RXD2/TXD2
2
FIFO0B_DIN0/DOUT0
FIFO0B_DIN1/DOUT1
FIFO0B_DIN2/DOUT2
3
Note 4
HSI0B_SINP
W22
P16
4
60
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
484
fpBGA
Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
BK1_IO5
BK1_IO6
BK1_IO7
BK1_IO8
BK1_IO9
1
1
1
1
1
18N
19P
19N
20P
20N
0B
0B
0B
0B
0B
5
6
7
8
9
HSI0B_SINN
HSI0B_RXD3/TXD3
HSI0B_RXD4/TXD4
HSI0B_RXD5/TXD5
HSI0B_RXD6/TXD6
HSI0B_RXD7/TXD7
FIFO0B_DIN3/DOUT3
FIFO0BN4/DOUT4
FIFOB_DIN5DOUT5
FIFODIN6/DUT6
FIFO0B_DIN7OUT7
P17
U18
V19
V20
V21
HSI0_CSLOCK
-
-
HSI0B_SYDT5
BK1_IO10/
VREF1
1
21P
0B
10
HSI0B_SOUTP
HSI0B_RXD8/TXD8
FO0B_DIN8/DOUT8
R16
BK1_IO11
GND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
21N
-
0B
-
11
-
HSI0B_SOUTN
HSI0B_RXD9XD9
FOB_DIN9/DOUT9
R17
GND
U19
T19
U21
U22
R19
T20
T21
T22
GND
N16
N17
R20
R21
N19
P20
P18
N18
GND
R22
P22
M18
-
-
-
BK1_IO12
BK1_IO13
BK1_IO14
BK1_IO15
BK1_IO16
BK1_IO17
BK1_IO18
BK1_IO19
GND
22P
22N
23P
23N
24P
24N
25P
25N
-
0B
0B
0B
0B
1B
1B
1B
1B
-
12
13
14
15
0
HSI0B_CDRRSTb
FIFO0B_STRDb6
HSI0_RELK
FIFO0B_FIF
-
-
-
-
-
-
O0B_MPTY
FIB_FUL
FO1B_DOUT0
FIFOB_DIN1/DOUT1
FIFO_DIN2/DOUT2
-
-
SYDT5
HSI1B_RXD0/TXD0
HI1B_RXD1/TXD1
HSI1B_RXD2/TD2
-
1
-
2
Note 4
3
-
BK1_IO20
BK1_IO21
BK1_IO22
BK1_IO23
BK1_IO24
BK1_IO25
BK1_IO26
BK1_IO27
GND
26P
26N
27P
27N
28P
28N
29P
29N
1B
1B
1B
1
1B
1B
1B
1B
-
4
HP
HSI1UTN
HSI1_CSLOCK
HSI1B_SYDT5
-
HSI1B_R3
HSI1RXD4XD4
HI1B_RD5/TX5
I1B_RXDXD6
HSI_RXD7/TXD7
HSI1B_XD8/TXD8
HSI1B_RXD9/TXD9
HSI1B_RECCLK
-
FIFO1B_DIN3/DOUT3
FIFO1B_DIN4/DOUT4
FIFO1B_DIN5/DOUT5
FIFO1B_DIN6/DOUT6
FIFO1B_DIN7/DOUT7
FIFO1B_DIN8/DOUT8
FIFO1B_DIN9/DOUT9
-
5
6
8
9
-
10
11
-
HSI1B_P
HSI1B_SI
Db6
HSTb
SSIN1P
-
BK1_IO28
BK1_IO29
BK1_IO30
0P
3
31P
1B
1B
1B
12
13
14
-
-
-
FIFO1B_FIFORSTb
-
-
BK1_IO3
CLK_OT2
1
31N
1B
15
S_CLKIN1N
-
FIFO1B_EMPTY
M17
GCLK/2
2
-
-
-
CLK2P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
N20
N21
K21
K20
-
SEL3
CLK/C
CLK2
BKI0/
CLK_OUT3
2
3A7
0
SS_CLKOUT1N
-
FIFO3A_FULL
K17
BK2_IO1
BK2_IO2
BK2_IO3
GND
2
2
2
2
2
2
2
2
2
2
33P
3A7
3A7
3A7
-
3A7
3A7
3A7
3A7
3A7
3A7
1
2
3
-
SS_CLKOUT1P
-
-
K18
L17
L18
GND
J17
J18
J22
J20
H22
H21
-
HSI3A_SYDT5
-
-
HSI3A_RXD0/TXD0
-
FIFO3A_DIN0/DOUT0
-
-
HSI3A_SINN
HSI3A_SINP
HSI3_CSLOCK
Note 4
BK2_IO4
BK2_IO5
BK2_IO6
BK2_IO7
BK2_IO8
BK2_IO9
34N
34P
35N
35P
36N
36P
4
5
6
7
8
9
HSI3A_RXD1/TXD1
HSI3A_RXD2/TXD2
HSI3A_RXD3/TXD3
HSI3A_RXD4/TXD4
HSI3A_RXD5/TXD5
HSI3A_RXD6/TXD6
FIFO3A_DIN1/DOUT1
FIFO3A_DIN2/DOUT2
FIFO3A_DIN3/DOUT3
FIFO3A_DIN4/DOUT4
FIFO3A_DIN5/DOUT5
FIFO3A_DIN6/DOUT6
CAL
-
61
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
484
fpBGA
Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
BK2_IO10
BK2_IO11
GND
2
2
2
2
2
2
2
2
2
2
2
2
37N
37P
-
3A7
3A7
-
10
11
-
HSI3A_SOUTN
HSI3A_RXD7/TXD7
FIFO3A_DIN7/DOUT7
K16
J16
HSI3A_SOUTP
HSI3A_RXD8/TXD8
FIFO3AN8/DOUT8
-
-
-
GND
J19
BK2_IO12
BK2_IO13
BK2_IO14
BK2_IO15
BK2_IO16
BK2_IO17
BK2_IO18
BK2_IO19
GND
38N
38P
39N
39P
40N
40P
41N
41P
-
3A7
3A7
3A7
3A7
2A
2A
2A
2A
-
12
13
14
15
0
HSI3A_SYDT5
HSI3A_RXD9/TXD9
FIFODIN9/DUT9
HSI3A_CDRRSTb
FIFO3A_STRDb6
HSI3A_RECCLK
FIFO3A_FIFRSTb
H20
G21
G20
G22
F22
F20
F21
GND
-
-
-
-
FIF3A_EMPTY
-
-
IFO2A_FULL
1
-
HSI2A_SDT5
HSI2AXD0/D0
HSA_RX1/TXD1
-
-
2
-
FIFO2A_DIN
FIFO2A_DIN1/
-
3
Note 4
-
-
BK2_IO20/
PLL_FB3
2
2
42N
42P
2A
2A
4
5
HSI2A_SOUTN
HSI2A_STP
HAXD2/TXD2
HSI2A_RXD3/TXD3
FIFO_IN2/DOUT2
FI2A_D/DOUT3
H18
G17
BK2_IO21/
VREF2
BK2_IO22
BK2_IO23
BK2_IO24
BK2_IO25
BK2_IO26
BK2_IO27
BK2_IO28
BK2_IO29
BK2_IO30
BK2_IO31
GND
2
2
2
2
2
2
2
2
2
2
2
-
43N
43P
44N
44P
45N
45P
46N
46P
47N
7P
-
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
-
6
7
HSI2_CSLOC
SI2A_RXD4/TXD4
HSI2A_RXD5/TX
HSI2A_R6/TXD6
HSI2A_RXDTXD7
HS2A_D8/T8
SI2A_RX/TXD9
I2A_RECCLK
-
FIFO_DIN4/DOUT4
IF2A_DIN5/DOUT5
FIFO2A_DIN6/DOUT6
FIFO2A_DIN7/DOUT7
FIFO2A_DIN8/DOUT8
FIFO2A_DIN9/DOUT9
FIFO2A_FIFORSTb
-
E21
F19
E22
D22
H17
H16
E19
F18
D20
D21
GND
B19
C19
E17
D18
A19
A18
GND
G15
G14
D17
D16
C18
B18
8
9
HST5
10
1
12
13
14
15
-
HSI2ASINN
HSI2A_SINP
HSI2A_CDRRSTb
FIFO2A_STRDb
-
-
-
-
-
FIFO2A_EMPTY
-
-
TCK
-
-
-
-
GOE2
-
-
-
-
-
BK3_IO0
BK3_IO1
BK3_IO
BK3_I
D
3
3
3
3
3
3
3
3
3
3
48
8N
49P
49N
-
3B
3B
3B
B
HSI3B_SYDT5
HSI3B_RXD0/TXD0
HSI3B_RXD1/TXD1
HSI3B_RXD2/TXD2
-
FIFO3B_FULL
1
-
FIFO3B_DIN0/DOUT0
FIFO3B_DIN1/DOUT1
FIFO3B_DIN2/DOUT2
-
2
Note 4
-
-
-
BK3_
K3_IO5
BK_6
BK3_IO7
BK3_IO8
BK3_IO9
5P
50N
P
N
3B
3B
3B
3B
3B
4
HSI3B_SINP
HSI3B_RXD3/TXD3
HSI3B_RXD4/TXD4
HSI3B_RXD5/TXD5
HSI3B_RXD6/TXD6
HSI3B_RXD7/TXD7
HSI3B_RXD8/TXD8
FIFO3B_DIN3/DOUT3
FIFO3B_DIN4/DOUT4
FIFO3B_DIN5/DOUT5
FIFO3B_DIN6/DOUT6
FIFO3B_DIN7/DOUT7
FIFO3B_DIN8/DOUT8
5
HSI3B_SINN
6
-
7
HSI3B_SYDT5
8
-
-
9
BK3_IO10/
VREF3
3
53P
3B
10
HSI3B_SOUTP
HSI3B_RXD9/TXD9
FIFO3B_DIN9/DOUT9
F15
BK3_IO11
GND
3
3
3
3
53N
-
3B
-
11
-
HSI3B_SOUTN
-
FIFO3B_STRDb6
HSI3B_RECCLK
-
F14
GND
B17
A17
-
-
BK3_IO12
BK3_IO13
54P
54N
3B
3B
12
13
-
-
HSI3B_CDRRSTb
HSI3B_RECCLK
FIFO3B_FIFORSTb
BK3_IO14/
PLL_RST3
3
55P
3B
14
-
-
-
A16
62
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
484
fpBGA
Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
BK3_IO15
BK3_IO16
BK3_IO17
BK3_IO18
BK3_IO19
GND
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
55N
56P
56N
57P
57N
-
3B
2B
2B
2B
2B
-
15
0
-
-
FIFO3B_EMPTY
FIFO2BN0/DOUT0
FIFOB_DIN1DOUT1
FIFODIN2/DUT2
FIFO2B_DIN3OUT3
-
C16
D15
D14
B16
C15
GND
G13
G12
B15
A15
C14
A14
F13
F12
GND
D13
C13
-
HSI2B_RXD0/TXD0
HSI2B_RXD1/TXD1
HSI2B_RXD2/TXD2
HSI2B_RXD3/TXD3
-
1
Note 4
2
-
3
-
-
-
BK3_IO20
BK3_IO21
BK3_IO22
BK3_IO23
BK3_IO24
BK3_IO25
BK3_IO26
BK3_IO27
GND
58P
58N
59P
59N
60P
60N
61P
61N
-
2B
2B
2B
2B
2B
2B
2B
2B
-
4
HSI2B_SOUTP
HSI2B_RXD4/TXD4
HSI2B_RXDTXD5
HSI2B_RXDTXD6
HSI2BXD7/D7
HSB_RX8/TXD8
HSI2RXD9XD9
HSI2RECCLK
-
IFO2DIN4/DOUT4
F2B_DIN5/DOUT5
FIFO2B_DIN6/D
FIFO2B_DIN
FIFO2B_DIN8/
FIFO_DIN9/DOU
5
HSI2B_SOUTN
6
-
7
FIFO2B_STRDb6
8
-
HSI2B_SYDT5
HSI2B_SINP
HSI2B_SIN
-
9
10
11
-
-
-
BK3_IO28
BK3_IO29
62P
62N
2B
2B
12
13
-
HSI2B_SYDT5
FO2B_FULL
HSIRSTb
-
FIF2B_FIFORSTb
BK3_IO30/
3
63P
63N
2B
14
-
B13
PLL_LOCK3
BK3_IO31
RESETb
BK4_IO0
3
-
2B
-
15
-
-
-
-
-
FIFO2B_ EMPTY
A13
D12
A10
-
4
64N
64P
4
FIFO4A_EMPTY
BK4_IO1/
PLL_LOCK0
4
A
1
-
-
-
B10
BK4_IO2
BK4_IO3
GND
4
4
4
4
4
4
4
4
65N
5P
4A
4A
2
3
HSI4A_CDRRSTb
-
FIFO4A_FIFORSTb
E11
E10
GND
F11
F10
C10
C9
-
-
HSI4A_SYDT5
FIFO4A_FULL
-
-
BK4_IO4
BK4_IO5
BK4_IO6
BK4_IO7
BK4_IO
N
P
67
7P
68N
4A
4A
4A
4A
4A
4
5
7
8
N
P
HDT5
-
-
-
HSI4A_RECCLK
HSI4A_RXD9/TXD9
HSI4A_RXD8/TXD8
HSI4A_RXD7/TXD7
-
FIFO4A_DIN9/DOUT9
FIFO4A_DIN8/DOUT8
FIFO4A_DIN7 /DOUT7
FO4A_STRDb6
D10
BK4_I
PLL_FB0
4
68P
4A
9
-
HSI4A_RXD6/TXD6
FIFO4A_DIN6/DOUT6
D9
BK4_IO10
B_IO1
GND
4
4
4
4
4
4
4
4
69N
69
4A
4A
10
11
-
HSI4A_SOUTN
HSI4A_RXD5/TXD5
HSI4A_RXD4/TXD4
-
FIFO4A_DIN5/DOUT5
FIFO4A_DIN4/DOUT4
-
G11
G10
GND
A9
HSI4A_SOUTP
-
BK4_IO12
BK4_IO13
BK4_IO14
BK4_IO15
BK4_IO16
71P
72N
4A
4A
4A
4A
5A
12
13
14
15
0
-
HSI4A_RXD3/TXD3
HSI4A_RXD2/TXD2
HSI4A_RXD1/TXD1
HSI4A_RXD0/TXD0
-
FIFO4A_DIN3/DOUT3
FIFO4A_DIN2/DOUT2
FIFO4A_DIN1/DOUT1
FIFO4A_DIN0/DOUT0
FIFO5A_EMPTY
-
C8
Note 4
B8
-
-
A8
B7
BK4_IO17/
PLL_RST0
4
72P
5A
1
-
-
-
C7
BK4_IO18
BK4_IO19
GND
4
4
4
4
73N
73P
-
5A
5A
-
2
3
-
HSI5A_CDRRSTb
FIFO5A_STRDb6
-
-
FIFO5A_FIFORSTb
A7
B6
-
-
-
-
-
GND
F9
BK4_IO20
74N
5A
4
HSI5A_SOUTN
HSI5A_RECCLK
63
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
484
fpBGA
Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
BK4_IO21/
VREF4
4
74P
5A
5
HSI5A_SOUTP
HSI5A_RXD9/TXD9
FIFO5A_DIN9/DOUT9
F8
BK4_IO22
BK4_IO23
BK4_IO24
BK4_IO25
BK4_IO26
BK4_IO27
BK4_IO28
BK4_IO29
BK4_IO30
BK4_IO31
GND
4
4
4
4
4
4
4
4
4
4
4
-
75N
75P
76N
76P
77N
77P
78N
78P
79N
79P
5A
5A
5A
5A
5A
5A
5A
5A
5A
5A
-
6
7
-
HSI5A_RXD8/TXD8
HSI5A_RXD7/TXD7
HSI5A_RXD6/TXD6
HSI5A_RXD5/TXD5
HSI5A_RXD4/TXD4
HSI5A_RXD3XD3
HSI5A_RXDTXD2
HSI5ARXDXD1
HSA_RD0/TX
H5A_ST5
-
FIFO_DIN8/DOUT8
FIFOA_7/DUT7
FIFO5A_DIN6/OUT6
FI5A_DIN5/DOUT5
IFO5ADIN4/DOUT4
FOA_DIN3/DOUT3
FIFO5A_DIN2/DOUT2
FIFO5A_DIN1
FIFO5A_DIN0
FIF5A_FUL
D7
D6
A6
A5
G9
G8
C5
B5
D5
C4
GND
B4
A4
GND
D2
D3
F5
-
8
HSI5A_SYDT5
9
-
10
11
12
13
14
15
-
HSI5A_SINN
HSI5A_SINP
-
Note 4
-
-
-
-
GOE1
-
-
-
TMS
-
-
-
-
-
GND
5
5
5
5
5
5
5
5
5
5
5
-
-
-
-
-
BK5_IO0
BK5_IO1
BK5_IO2
BK5_IO3
BK5_IO4
BK5_IO5
BK5_IO6
BK5_IO7
BK5_IO8
BK5_IO9
80P
80N
81P
81N
82P
82N
83P
83N
84P
84N
4B
4B
4B
4B
4B
4
4B
4B
4B
4B
0
-
FIF4B_EMPTY
-
1
-
2
FIb6
HSI4BRSTb
HSI4B_SINP
HSI4B_SINN
HSI4B_SYDT5
-
-
3
HSI_RECLK
HI4B_RD9/TX9
I4B_RXDXD8
HSI_RXD7/TXD7
HSI4B_XD6/TXD6
HSI4B_RXD5/TXD5
HSI4_RXD4/TXD4
FIFO4B_FIFORSTb
FIFO4B_DIN9/DOUT9
FIFO4B_DIN8/DOUT8
FIFO4B_DIN7/DOUT7
FIFO4B_DIN6/DOUT6
FIFO4B_DIN5/DOUT5
FIFO4B_DIN4/DOUT4
E4
J7
4
J6
6
D1
E1
F4
7
8
-
9
HSI4_CSLOK
E3
BK5_IO10/
VREF5
5
8
4B
10
UTP
HSI4B_RXD3/TXD3
FIFO4B_DIN3/DOUT3
H7
BK5_IO11
GND
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
N
-
4B
-
11
TN
HSI4B_RXD2/TXD2
-
FIFO4B_DIN2/DOUT2
-
H6
GND
E2
BK5_IO12
BK5_IO3
BK5_I4
_IO15
BK5_6
K5_IO1
BK_18
BK5_IO19
GND
6P
86N
87P
87N
8P
88N
P
4B
4B
B
4
5B
5B
5B
-
12
13
15
0
Note 4
HSI4B_RXD1/TXD1
HSI4B_RXD0/TXD0
HSI4B_SYDT5
-
FIFO4B_DIN1/DOUT1
FIFO4B_DIN0/DOUT0
-
-
F2
-
G4
H5
F1
-
FIFO4B_FULL
-
-
FIFO5B_EMPTY
-
1
FIFO5B_STRDb6
HSI5B_CDRRSTb
HSI5B_SYDT5
-
-
G1
G3
G2
GND
K7
2
HSI5B_RECCLK
HSI5B_RXD9/TXD9
-
FIFO5B_FIFORSTb
FIFO5B_DIN9/DOUT9
-
3
-
BK5_IO20
BK5_IO21
BK5_IO22
BK5_IO23
BK5_IO24
BK5_IO25
BK5_IO26
BK5_IO27
P
90N
91P
91N
92P
92N
93P
93N
5B
5B
5B
5B
5B
5B
5B
5B
4
HSI5B_SOUTP
HSI5B_SOUTN
-
HSI5B_RXD8/TXD8
HSI5B_RXD7/TXD7
HSI5B_RXD6/TXD6
HSI5B_RXD5/TXD5
HSI5B_RXD4/TXD4
HSI5B_RXD3/TXD3
HSI5B_RXD2/TXD2
HSI5B_RXD1/TXD1
FIFO5B_DIN8/DOUT8
FIFO5B_DIN7/DOUT7
FIFO5B_DIN6/DOUT6
FIFO5B_DIN5/DOUT5
FIFO5B_DIN4/DOUT4
FIFO5B_DIN3/DOUT3
FIFO5B_DIN2/DOUT2
FIFO5B_DIN1/DOUT1
5
K6
6
H4
H3
H1
H2
J5
7
-
8
Note 4
9
HSI5_CSLOCK
HSI5B_SINP
HSI5B_SINN
10
11
K5
64
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
484
fpBGA
Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
GND
5
5
5
5
-
-
-
-
-
HSI5B_RXD0/TXD0
HSI5B_SYDT5
-
-
GND
J4
BK5_IO28
BK5_IO29
BK5_IO30
94P
94N
95P
5B
5B
5B
12
13
14
-
FIFO5BN0/DOUT0
-
-
-
J3
SS_CLKIN0P
L6
BK5_IO31/
CLK_OUT0
5
95N
5B
15
SS_CLKIN0N
-
FIFO5ULL
L5
GCLK/CE0
SEL0
-
-
-
-
CLK0P
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L4
K3
K2
N1
-
SEL1
-
GCLK/CE1
CLK0N
BK6_IO0/
CLK_OUT1
6
96N
7A
0
SS_CLKOUT0N
-
FIFO7A_EM
N6
BK6_IO1
BK6_IO2
BK6_IO3
GND
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
96P
97N
97P
-
7A
7A
7A
-
1
2
SS_CLKOUT0P
-
-
N5
M5
M6
GND
P6
HSI7A_CDRRST
FIFO7A_STRb6
-
FIFAIFORSTb
3
-
-
-
-
-
-
BK6_IO4
BK6_IO5
BK6_IO6
BK6_IO7
BK6_IO8
BK6_IO9
BK6_IO10
BK6_IO11
GND
98N
98P
99N
99P
100N
100P
101N
101P
-
7A
7A
7A
7A
7A
7A
7A
7A
-
4
HSI7A_SINN
HSI7A_RECCLK
HSI7A_RXD9/TX9
HSI7A_R8/TXD8
HSI7A_RXDTXD7
HSI7A_D6/TD6
SI7A_RX/TXD5
HA_RXD4/TXD4
HSI7ARXD3/TXD3
-
-
5
P
IF7A_DIN9/DOUT9
FIFO7A_DIN8/DOUT8
FIFO7A_DIN7/DOUT7
FIFO7A_DIN6/DOUT6
FIFO7A_DIN5/DOUT5
FIFO7A_DIN4/DOUT4
FIFO7A_DIN3/DOUT3
-
P5
6
N3
7
N2
8
HSI7AYDT5
P3
9
HSI7_CSLOCK
P1
10
11
-
HSI7A_SOUTN
N7
HSI7A_SOUTP
P7
-
GND
R3
BK6_IO12
BK6_IO13
BK6_IO14
BK6_IO15
BK6_IO16
BK6_IO17
BK6_IO8
BK6_I9
D
12N
102P
1N
3P
104
04P
105N
105P
-
7A
7A
7A
7A
6A
6A
6A
A
12
13
14
15
-
I7A_RXD2/TXD2
HSI7A_RXD1/TXD1
HSI7A_RXD0/TXD0
HSI7A_SYDT5
-
FIFO7A_DIN2/DOUT2
FIFO7A_DIN1/DOUT1
FIFO7A_DIN0/DOUT0
FIFO7A_ FULL
FIFO6A_EMPTY
-
e 4
R2
R1
T1
T2
1
-
-
T3
2
FO6A_STRDb6
SI6A_CDRRSTb
-
-
-
U1
HSI6_RECCLK
-
FIFO6A_FIFORSTb
-
U2
-
GND
BK6_0/
P_FB
6
6
10
P
6A
6A
4
5
HSI6A_SOUTN
HSI6A_RXD9/TXD9
HSI6A_RXD8/TXD8
FIFO6A_DIN9/DOUT9
FIFO6A_DIN8/DOUT8
R5
T6
BK6_IO/
VR
HSI6A_SOUTP
BK6_IO22
BK6_IO23
BK6_IO24
BK6_IO25
BK6_IO26
BK6_IO27
BK6_IO28
BK6_IO29
BK6_IO30
BK6_IO31
6
6
6
6
6
6
6
6
6
6
8N
108P
109N
109P
110N
110P
111N
111P
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6
HSI6A_SYDT5
HSI6A_RXD7/TXD7
HSI6A_RXD6/TXD6
HSI6A_RXD5/TXD5
HSI6A_RXD4/TXD4
HSI6A_RXD3/TXD3
HSI6A_RXD2/TXD2
HSI6A_RXD1/TXD1
HSI6A_RXD0/TXD0
HSI6A_SYDT5
FIFO6A_DIN7/DOUT7
FIFO6A_DIN6/DOUT6
FIFO6A_DIN5/DOUT5
FIFO6A_DIN4/DOUT4
FIFO6A_DIN3/DOUT3
FIFO6A_DIN2/DOUT2
FIFO6A_DIN1/DOUT1
FIFO6A_DIN0/DOUT0
-
U4
V4
V3
V2
R6
R7
W1
V1
W2
W3
7
-
8
-
9
HSI6_CSLOCK
10
11
12
13
14
15
HSI6A_SINN
HSI6A_SINP
Note 4
-
-
-
-
FIFO6A_ FULL
65
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
484
fpBGA
Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
GND
6
-
-
-
-
-
-
-
GND
AA4
Y4
TDI
-
-
-
-
-
GOE0
-
-
-
-
-
-
-
GND
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
-
GND
AB4
AB5
V6
BK7_IO0
BK7_IO1
BK7_IO2
BK7_IO3
BK7_IO4
BK7_IO5
BK7_IO6
BK7_IO7
BK7_IO8
BK7_IO9
112P
112N
113P
113N
114P
114N
115P
115N
116P
116N
7B
7B
7B
7B
7B
7B
7B
7B
7B
7B
0
1
2
3
4
5
6
7
8
9
-
-
FIFO7B_ EPTY
-
FIFO7B_STRDb6
-
HSI7B_CDRRSTb
HSI7B_SYDT5
HSI7B_RECCLK
HSI7B_RXDTXD9
HSI7B_RXDTXD8
HSI7BXD7/D7
HSB_RX6/TXD6
HSI7RXD5D5
SI7BXD4/TXD4
HSI7BXD3/TXD3
FIFO_FIFORSTb
F7B_DIN9/DOUT9
FIFO7B_DIN8/D
FIFO7B_DIN
FIFO7B_DIN6/
FIFO_DIN5/DOU
FIFB_DN4/DOUT4
IFO7BIN3/OUT3
W5
T8
HSI7B_SINP
HSI7B_SINN
T9
-
W6
Y5
-
Note 4
-
AA5
AA6
BK7_IO10/
VREF7
7
117P
7B
10
HSI7B_SOTP
HSI7B_RXD2/TXD2
FIFB_DIN2/DOUT2
U8
BK7_IO11
GND
7
7
7
7
117N
-
7B
-
11
-
HSIOUTN
HSI7B_RXD1/TD1
-
FIFO_DIN1/DOUT1
U9
GND
W7
-
BK7_IO12
BK7_IO13
118P
118N
7B
7B
12
13
HSI7B_R0
HSB_SYT5
FIFO7B_DIN0/DOUT0
-
W8
BK7_IO14/
PLL_RST1
7
119P
7B
14
-
-
AB6
BK7_IO15
BK7_IO16
BK7_IO17
BK7_IO18
BK7_IO19
GND
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
119N
120P
120N
1P
121N
7B
6B
6B
6B
6B
-
15
0
-
-
FIFO7B_FULL
-
AB7
Y7
FIFO6B_STRDb
-
1
HSI6B_CDRRSTb
HSI6B_S
HSI6B_RECCLK
I6B_RXD9/TXD9
HSI6B_RXD8/TXD8
-
FIFO6B_FIFORSTb
FIFO6B_DIN9/DOUT9
FIFO6B_DIN8/DOUT8
-
AA7
W9
2
3
Y8
-
GND
T10
T11
AA8
AB8
W10
Y9
BK7_IO20
BK7_IO21
BK7_IO22
BK7_IO3
BK7_I4
_IO25
BK7_6
K7_IO2
GN
2P
122
23P
123N
124P
124N
12P
125N
6B
6B
6B
6B
B
6
6B
-
4
TP
HSI6B_RXD7/TXD7
HSI6B_RXD6/TXD6
HSI6B_RXD5/TXD5
HSI6B_RXD4/TXD4
HSI6B_RXD3/TXD3
HSI6B_RXD2/TXD2
HSI6B_RXD1/TXD1
HSI6B_RXD0/TXD0
-
FIFO6B_DIN7/DOUT7
FIFO6B_DIN6/DOUT6
FIFO6B_DIN5/DOUT5
FIFO6B_DIN4/DOUT4
FIFO6B_DIN3/DOUT3
FIFO6B_DIN2/DOUT2
FIFO6B_DIN1/DOUT1
FIFO6B_DIN0/DOUT0
-
HUTN
6
-
7
-
Note 4
9
-
10
11
-
HSI6B_SINP
U10
U11
GND
W11
HSI6B_SINN
-
-
BK7_IO28
6B
12
HSI6B_SYDT5
FIFO6B_ EMPTY
BK7_IO29/
PLL_LOCK1
7
6B
13
-
-
-
Y10
BK7_IO30
BK7_IO31
7
7
127P
127N
6B
6B
14
15
-
-
-
-
-
AA10
AB9
FIFO6B_FULL
66
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2-256 Logic Signal Connections (Continued)
Signal
Name
sysIO
Bank
LVDS
GDX
SERDES Mode
SERDES Mode
FIFO Mode I/O
Cell/Pin3
484
fpBGA
Pair/Polarity Block MRB
I/O Pin1
I/O Cell2
TOE
-
-
-
-
-
-
-
AB10
1. The signals in this column route to/from the assigned pins of the associated I/O cell.
2. The signals in this column use the I/O cell. If a receiver signal is present in the I/O cell, the associated pin is ailable for output only. When
transmit data (TXD) is present in the cell, the associated pin is available for input only.
3. The DOUT outputs are routed to GRP through the input register of the cell and the DIN inputs are routed direct from the sociated pins in
FIFO only mode. In SERDES with FIFO mode, the FULL and EMPTY flags are routed to the associatd pins throuh toutput MUX and
the pins.
4. If the Source Synchronous Receiver is used in the HSI Block, this pin is unavailable for another use amust be eft unconnected.
5. The SYDT signal has two routing options. If direct output through the dedicated pin is used, tO cell e wle HSI Block) is not avail-
able for transmitter. The SYDT in the I/O Cell column is routed to the GRP through the inpregister of the ll and frees the I/O cell for
transmitter.
6. FIFO_STRDb flag output is used in SERDES with FIFO Mode only.
7. sysHSI Source Synchronous Receive Mode is not available for channel 3A.
67
Lattice Semiconductor
ispGDX2 Family Data Sheet
Part Number Description
LX XXX X X – XX FXXX X
Device Family
Grade
C = Commercil
I = Industrial
LX
Device Number
64 = 64 I/Os
Package
F100 100-all fpBGA
FN100 ead-Free 100-Ball fpBGA
208 = 20Bl fpBGA
FN208 = Lead-Free 208-Ball fpBGA
484 = 84-Ball fpBG
FN4 = Lead-Free 4GA
128 = 128 I/Os
256 = 256 I/Os
sysHSI Support
Blank = Supports sysHSI
E = No sysHSI support
Power Supply Voltage
V = 3.3V
B = 2.5V
Sed
3 = 3.0ns
32 = 3.2n
35 = 3.5ns
5 = 5ns
C = 1.8V
Ordering Information
Conventional Packaging
Commercial
Family
LX64V
Part Number
LX64V-3F100C
LX64V-5F100C
LX128V-32F20C
LX128V-5F08C
LX256V-358C
LX256V-5F484
LXB-3F100C
LX64BF10C
L128B-32F208C
LX12B-5F208C
56B-35F484C
LX256B-5F484C
LX64C-3F
LX64C
LX128C-
LX128C-5F2
LX256C-35F484C
LX256C-5F484C
I/Os
64
Voltage
t
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
100
100
208
208
484
484
100
100
208
208
484
484
100
100
208
208
484
484
Grade
C
P
3.3
3.3
3.3
3
2.5
2.5
2.5
2.5
2.5
1.8
1.8
1.8
1.8
1.8
1.8
3
64
5
C
1
128
256
256
64
2
5
C
LX128V
LX256V
LX64B
C
3.5
5
C
C
3
C
5
C
12
128
25
26
64
3.2
5
C
LX128
LX2
LXC
C
3.5
5
C
C
3
C
64
5
C
128
128
256
256
3.2
5
C
LX128C
LX256C
C
3.5
5
C
C
68
Lattice Semiconductor
ispGDX2 Family Data Sheet
“E-Series” Commercial
Family
Part Number
LX64EV-3F100C
LX64EV-5F100C
LX128EV-32F208C
LX128EV-5F208C
LX256EV-35F484C
LX256EV-5F484C
LX64EB-3F100C
LX64EB-5F100C
LX128EB-32F208C
LX128EB-5F208C
LX256EB-35F484C
LX256EB-5F484C
LX64EC-3F100C
LX64EC-5F100C
LX128EC-32F208C
LX128EC-5F208C
I/Os
64
Voltage
3.3
3.3
3.3
3.3
3.3
3.3
2.5
2.5
2.5
2.5
2.5
2.5
1.8
1.8
1.8
1.8
t
Package
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBG
fpBGA
fpBGA
fpBGA
pBGA
fpBGA
pBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
100
100
208
20
484
484
00
100
208
208
484
484
10
0
208
208
Grade
C
PD
3
LX64EV
64
5
C
128
128
256
256
64
3.2
5
C
LX128EV
LX256EV
LX64EB
C
3.5
5
C
C
3
C
64
5
C
128
128
256
256
64
3.2
5
C
LX128EB
LX256EB
LX64EC
LX128EC
3.5
5
C
C
64
5
C
128
128
3.2
5
C
C
“Industrial
Family
Part Number
I/Os
6
Vo
3.3
t
ackage
fGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
fpBGA
Pins
100
100
100
208
208
208
484
484
484
Grade
PD
LX64EV LX64EV-5F100I
LX64EB LX64EB-5F100I
LX64EC LX64EC-5F100I
LX128EV LX128EV-5F208I
LX128EB LX128EB-5F208I
LX128EC LX128EC-508I
LX256EV LX256EV-48
LX256EB LX256EB-5F44I
LX256EC LX56EC-5F484I
I
I
I
I
I
I
I
I
I
64
2.5
5
5
5
5
5
5
5
64
1.8
128
1
28
256
256
256
3.3
2.5
1.8
69
Lattice Semiconductor
ispGDX2 Family Data Sheet
Lead-Free Packaging
Commercial
Family
LX64V
Part Number
LX64V-3FN100C
LX64V-5FN100C
LX64B-3FN100C
LX64B-5FN100C
LX64C-3FN100C
LX64C-5FN100C
LX128V-32FN208C
LX128V-5FN208C
LX128B-32FN208C
LX128B-5FN208C
LX128C-32FN208C
LX128C-5FN208C
LX256V-35FN484C
LX256V-5FN484C
LX256B-35FN484C
LX256B-5FN484C
LX256C-35FN484C
LX256C-5FN484C
I/Os
64
Voltage
3.3
3.3
2.5
2.5
1.8
1.8
3.3
3.3
2.5
2.5
1.8
1.8
3.
3.
.5
.8
t
Package
Pins
100
100
10
10
100
100
208
20
20
208
208
84
484
484
484
484
484
Grade
C
PD
3.0
5.0
3.0
5.0
3.0
5.0
3.2
5.0
3.2
5.0
3.2
5
3.5
50
3.5
5.0
3.5
5.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free BGA
Lead-frfpBA
Lead-free fGA
ead-free fpB
ead-free pBGA
Le-frefpBGA
ead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBA
Lead-e fpBGA
Led-free BGA
Lead-ee fpBGA
eapBGA
Ld-free fpBGA
64
C
64
C
LX64B
64
C
64
C
LX64C
64
C
128
128
128
128
128
128
256
256
256
256
256
256
C
LX128V
LX128B
LX128C
LX256V
LX256B
LX256C
C
C
C
C
C
C
C
C
C
C
C
“E-Series” Commeral
Family
Part Numbe
LX64EV-3FN100
LX64EV-5F100C
LX64EBFN1C
LX64EB-5100C
LX64EC-3FNC
L4EC-5FN100C
LX12EV32FN208C
LX128EV-5FN208C
LX28EB-32FN20C
LX128EB-5FN208C
LX128EC-32FN8C
LX128208C
LX2584C
LX256E4C
LX256EB-3FN484C
LX256EB-5FN484C
LX256EC-35FN484C
LX256EC-5FN484C
I/Os
64
Voltage
3.3
3.
.5
1.8
3.3
3.3
2.5
2.5
1.8
1.8
3.3
3.3
2.5
2.5
1.8
1.8
t
Package
Pins
100
100
100
100
100
100
208
208
208
208
208
208
484
484
484
484
484
484
Grade
C
PD
3.0
.0
3.0
5.0
3.0
5.0
3.2
5.0
3.2
5.0
3.2
5.0
3.5
5.0
3.5
5.0
3.5
5.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
LX64EV
64
C
64
C
LX64EB
64
C
64
C
LX64EC
LX128V
LX128EB
LX128E
LX256EV
LX256EB
LX256EC
64
C
128
128
128
128
128
128
256
256
256
256
256
256
C
C
C
C
C
C
C
C
C
C
C
C
70
Lattice Semiconductor
ispGDX2 Family Data Sheet
“E-Series” Industrial
Family
LX64EV
Part Number
LX64EV-5FN100I
LX64EB-5FN100I
LX64EC-5FN100I
LX128EV-5FN208I
LX128EB-5FN208I
LX128EC-5FN208I
LX256EV-5FN484I
LX256EB-5FN484I
LX256EC-5FN484I
I/Os
64
Voltage
3.3
t
Package
Pins
100
100
100
2
2
208
484
484
484
Grade
PD
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fpBGA
Lead-free fBGA
Lead-frfpBA
Lead-free GA
ead-free fpB
ead-free pBGA
I
I
I
I
I
I
I
I
I
LX64EB
64
2.5
LX64EC
LX128EV
LX128EB
LX128EC
LX256EV
LX256EB
LX256EC
64
1.8
128
128
128
256
256
256
3.3
2.5
1.8
3.3
2.5
1.8
71
Lattice Semiconductor
ispGDX2 Family Data Sheet
For Further Information
In addition to this data sheet, the following Lattice technical notes may be helpful when designing with the ispGDX2
Family:
• sysIO Design and Usage Guidelines (TN1000)
• sysCLOCK PLL Design and Usage Guidelines (TN1003)
• sysHSI Usage Guide (TN1020)
• Power Estimation in ispGDX2 Devices (TN1021)
72
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