M4A3-128/128-7VC [LATTICE]
EE PLD, 7.5ns, 128-Cell, CMOS, PQFP176, TQFP-176;型号: | M4A3-128/128-7VC |
厂家: | LATTICE SEMICONDUCTOR |
描述: | EE PLD, 7.5ns, 128-Cell, CMOS, PQFP176, TQFP-176 |
文件: | 总62页 (文件大小:2620K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MACH 4 CPLD Family
High Performance EE CMOS
Programmable Logic
FEATURES
High-performance, EE CMOS 3.3-V & 5-V CPLD families
Flexible architecture for rapid logic designs
TM
— Excellent First-Time-Fit
— SpeedLocking
and refit feature
TM
performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns t Commercial and 7.5ns t Industrial
PD
PD
— 182MHz f
CNT
32 to 512 macrocells; 32 to 768 registers
44 to 352 pins in PLCC, PQFP, TQFP, BGA, or fpBGA packages
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
TM
— Programmable pull-up or Bus-Friendly inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Flexible architecture for a w ide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced EE CMOS process provides high-performance, cost-effective solutions
TM
Supported by Vantis DesignDirect
softw are for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice/Vantis and third-party hardw are programming support
TM
®
— Lattice/VantisPRO (formerly known as MACHPRO ) software for in-system programmability
support on PCs and automated test equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication# 1 7466
Amendment/0
Rev: J
Issue Date: May 1 999
1,2
Table 1. MACH 4 Device Features
M4-32/32
M4-64/32
M4-96/48
M4-128/64
M4-128N/64
M4-192/96
M4-256/128
Feature
M4LV-32/32 M4LV-64/32 M4LV-96/48 M4LV-128/64 M4LV-128N/64 M4LV-192/96 M4LV-256/128
Macrocells
32
32
64
32
96
48
128
64
128
64
192
96
256
128
7.5
111
5.5
5.5
100
Yes
Yes
Maximum User I/O Pins
t
(ns)
7.5
111
5.5
5.5
25
7.5
111
5.5
5.5
25
7.5
111
5.5
5.5
50
7.5
111
5.5
5.5
70
7.5
111
5.5
5.5
70
7.5
111
5.5
5.5
85
PD
f
(MHz)
CNT
t
t
(ns)
COS
(ns)
SS
Static Power (mA)
JTAG Compliant
PCI Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Notes:
1. For information on the M4-96/96 device, please refer to the M4-96/96 datasheet at www.vantis.com.
2. “M4-xxx” is for 5-V devices. “M4LV-xxx” is for 3.3-V devices.
2
MACH 4 Family
1
Table 2. MACH 4A Device Features
3.3 V Devices
Feature
M4A3-32
M4A3-64
M4A3-96
M4A3-128
M4A3-192
M4A3-256
M4A3-384
M4A3-512
Macrocells
32
64
96
128
192
256
384
512
132/160/192/
256
User I/O options
32
32/64
48
64/96/128
68/96/128
128/192
132/160/192
t
(ns)
5.0
182
4.0
5.0
182
4.0
5.0
182
4.0
5.0
182
4.0
5.0
182
4.0
5.0
182
4.0
6.5
154
4.5
6.5
154
4.5
PD
f
(MHz)
CNT
t
t
(ns)
COS
(ns)
3.0
3.0
3.0
3.0
3.0
3.0
4.0
4.0
SS
Static Power (mA)
JTAG Compliant
PCI Compliant
TBD
Yes
Yes
TBD
Yes
Yes
TBD
Yes
Yes
TBD
Yes
Yes
TBD
Yes
Yes
TBD
Yes
Yes
TBD
Yes
Yes
TBD
Yes
Yes
5 V Devices
Feature
M4A5-32
32
M4A5-64
64
M4A5-96
96
M4A5-128
128
M4A5-192
192
M4A5-256
256
Macrocells
User I/O options
32
32
48
64
96
128
t
(ns)
5.0
5.0
5.0
5.0
5.0
6.5
PD
f
(MHz)
182
4.0
182
4.0
182
4.0
182
182
154
CNT
t
t
(ns)
4.0
4.0
4.5
COS
(ns)
3.0
3.0
3.0
3.0
3.0
4.0
SS
Static Power (mA)
JTAG Compliant
PCI Compliant
TBD
Yes
TBD
Yes
TBD
Yes
TBD
Yes
TBD
Yes
TBD
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Notes:
1. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on
availability.
MACH 4 Family
3
GENERAL DESCRIPTION
®
The MACH 4 family from Lattice/Vantis offers an exceptionally flexible architecture and delivers
a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products
and software tools. The overall benefits for users are a guaranteed and predictable CPLD
solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer
densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention.
Both the MACH 4 and the MACH 4A families offer 5-V (M4-xxx and M4A5-xxx) and 3.3-V (M4LV-
xxx and M4A3-xxx) operation.
MACH 4 products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1)
interface. JTAG boundary scan testing capability also allows product testability on automated test
equipment for device connectivity.
All MACH 4 family members deliver First-Time Fit and easy system integration with pin-out
retention after any design change and refit. With multi-tiered central switch matrices, enhanced
logic arrays, intelligent logic allocators with an XOR gate and multi-clocking, the MACH 4 family
has D or T-type registers and latches as well as synchronous/asynchronous logic and flexible
set/reset capabilities. For both 3.3-V and 5-V operations, MACH 4 products can deliver
guaranteed fixed timing as fast as 5.0 ns t and 182 MHz f
through the SpeedLocking feature
PD
CNT
when using up to 20 product terms per output (Tables 3 and 4).
Table 3. MACH 4 Speed Grades
1
Speed Grade
Device
-7
-10
-12
-14
-15
-18
M4-32/32
C
C, I
C, I
I
C
I
M4LV-32/32
M4-64/32
C
C
C
C
C
C
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
I
I
I
I
I
I
C
C
C
C
C
C
I
I
I
I
I
I
M4LV-64/32
M4-96/48
M4LV-96/48
M4-128/64
M4LV-128/64
M4-128N/64
M4LV-128N/64
M4-192/96
M4LV-192/96
M4-256/128
M4LV-256/128
Note:
1. C = Commercial, I = Industrial
4
MACH 4 Family
Table 4. MACH 4A Speed Grades
1, 2
Speed Grade
Device
M4A3-32
-5
-55
-6
-65
-7
-10
-12
-14
C
C
C
C
C, I
C, I
C, I
I
M4A5-32
M4A3-64
M4A5-64
C
C
C
C
C
C
C
C
C
C
C
C
C
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
I
I
I
I
M4A3-96
M4A5-96
M4A3-128
M4A5-128
M4A3-192
M4A5-192
C
C
C
C
C
C
M4A3-256
M4A5-256
M4A3-384
M4A3-512
C
C
C
C
C, I
C
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
I
I
I
I
C
C
Notes:
1. C = Commercial, I = Industrial
2. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on
availability.
The MACH 4 family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic
Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), and fine-
pitch BGA (fpBGA) packages ranging from 44 to 352 pins (Tables 5 and 6). It also offers I/O
safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-
V devices do not overdrive 3.3-V inputs. Additional features include Bus-Friendly inputs and I/
Os, a programmable power-down mode for extra power savings and individual output slew rate
control for the highest speed transition or for the lowest noise transition.
Table 5. MACH 4 Package and I/O Options (Number of I/Os and dedicated inputs in Table)
M4-32/32
M4-64/32
M4-96/48
M4-128/64
M4-128N/64
M4-192/96
M4-256/128
Package
44-pin PLCC
M4LV-32/32 M4LV-64/32 M4LV-96/48 M4LV-128/64 M4LV-128N/64 M4LV-192/96 M4LV-256/128
32+2
32+2
32+2
32+2
32+2
32+2
44-pin TQFP
48-pin TQFP
84-pin PLCC
100-pin TQFP
100-pin PQFP
144-pin TQFP
208-pin PQFP
256-ball BGA
64+6
48+8
64+6
64+6
96+16
128+14
128+14
MACH 4 Family
5
1
Table 6. MACH 4A Package and I/O Options (Number of I/Os and dedicated inputs in Table)
3.3 V Devices
Package
44-pin PLCC
44-pin TQFP
48-pin TQFP
100-pin TQFP
100-pin PQFP
M4A3-32
32+2
M4A3-64
32+2
M4A3-96
M4A3-128
M4A3-192
M4A3-256
M4A3-384
M4A3-512
32+2
32+2
32+2
32+2
64+6
48+8
64+6
64+6
68+2
100-ball
fpBGA
64+6
64+6
96+16
96+16
128+4
128+4
68+2
96+16
96+16
128+4
128+4
144-pin TQFP
144-ball
fpBGA
176-pin TQFP
128+4
128+4
132
160
192
132
160
200-ball
fpBGA
208-pin PQFP
128+14, 160
192
320-ball
fpBGA
256-ball BGA
352-ball BGA
128+14
192
256
5 V Devices
M4A5-96
Package
44-pin PLCC
44-pin TQFP
48-pin TQFP
100-pin TQFP
100-pin PQFP
144-pin TQFP
208-pin PQFP
256-ball BGA
M4A5-32
32+2
M4A5-64
32+2
M4A5-128
M4A5-192
M4A5-256
32+2
32+2
32+2
32+2
48+8
64+6
64+6
96+16
128+14
128+14
Note:
1. All information on MACH 4A devices is Advance Information. Please contact a Lattice/Vantis sales representative for details on
availability.
6
MACH 4 Family
®
Lattice/Vantis offers software design support for MACH devices in both the MACHXL and
DesignDirect development systems. The DesignDirect development system is Vantis’
implementation software that includes support for all Vantis CPLD, FPGA and SPLD devices. This
system is supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX.
DesignDirect software is designed for use with design entry, simulation and verification software
from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model
Technology , Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists,
generates JEDEC files for Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL-
compliant VHDL and SDF simulation netlist for design verification.
DesignDirect software is also available in product configurations that include VHDL and Verilog
synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from
Model Technology. Schematic capture and ABEL entry, as well as functional simulation, are also
provided.
MACH 4 Family
7
FUNCTIONAL DESCRIPTION
®
The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple optimized PAL
blocks interconnected by a central switch matrix. The central switch matrix allows
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes.
In MACH 4 architecture, the macrocells have been decoupled from the product terms through
the logic allocator, and the I/O pins have been decoupled from the macrocells due to the output
switch matrix. In addition, more input routing options are provided by the input switch matrix.
These resources provide the flexibility needed to fit designs efficiently.
PAL Block
4
Note 2
Clock
Generator
Clock/Input
Pins
33/
34/
36
Note 3
I/O
Pins
16
16
8
Logic
Allocator
with XOR
Output/
Buried
Macrocells
Logic
Array
Note 1
Dedicated
Input Pins
16
Input
Switch
Matrix
16
I/O
Pins
PAL Block
PAL Block
I/O
Pins
17466G-001
Figure 1. MACH 4 Block Diagram and PAL Block Structure
Notes:
1. 16 for MACH 4 and MACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4(LV)-32/32 or M4A(3,5)-32/32.
3. M4(LV)-192/96, M4(LV)-256/128, M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which
cannot be used as inputs and do not connect to the central switch matrix.
8
MACH 4 Family
Table 7. Architectural Summary of MACH 4 devices
MACH 4A Devices
M4-64/32, M4LV-64/32
M4-96/48, M4LV-96/48
M4-128/64, M4LV-128/64
M4-128N/64, M4LV-128N/64
M4-192/96, M4LV-192/96
M4-256/128, M4LV-256/128
M4-32/32
M4LV-32/32
Macrocell-I/O Cell
Ratio
2:1
1:1
Input Switch Matrix
Input Registers
Yes
Yes
Yes
Yes
Yes
No
Central Switch Matrix
Output Switch Matrix
Yes
Yes
Table 8. Architectural Summary of MACH 4A devices
MACH 4A Devices
M4A3-64/32, M4A5-64/32
M4A3-96/48, M4A5-96/48
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96
M4A3-256/128, M4A5-256/128
M4A3-384
M4A3-32/32
M4A5-32/32
M4A3-64/64
M4A3-128/96, M4A3-128/128
M4A3-256/160
M4A3-256/192
M4A3-512
M4A3-192/68, M4A3-192/128
Macrocell-I/O Cell
Ratio
2:1
1:1
Input Switch Matrix
Input Registers
Yes
Yes
Yes
Yes
Yes
No
Central Switch Matrix
Output Switch Matrix
Yes
Yes
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O
cells internally in a PAL block (Tables 7 and 8).
The central switch matrix takes all dedicated inputs and signals from the input switch matrices
and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block
still must go through the central switch matrix. This mechanism ensures that PAL blocks in MACH
4 devices communicate with each other with consistent, predictable delays.
The central switch matrix makes a MACH 4 device more advanced than simply several PAL
devices on a single chip. It allows the designer to think of the device not as a collection of
blocks, but as a single programmable device; the software partitions the design into PAL blocks
through the central switch matrix so that the designer does not have to be concerned with the
internal architecture of the device.
MACH 4 Family
9
Each PAL block consists of:
Product-term array
Logic allocator
Macrocells
Output switch matrix
I/O cells
Input switch matrix
Clock generator
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic
being implemented. The inputs to the AND gates come from the central switch matrix (Table 9),
and are provided in both true and complement forms for efficient logic implementation.
Table 9. PAL Block Inputs
Device
M4-32/32 and M4LV-32/32
Number of Inputs to PAL Block
33
33
33
M4-64/32 and M4LV-64/32
M4-96/48 and M4LV-96/48
M4-128/64 and M4LV-128/64
M4-128N/64 and M4LV-128N/64
33
33
M4-192/96 and M4LV-192/96
M4-256/128 and M4LV-256/128
34
34
M4A3-32/32 and M4A5-32/32
M4A3-64/32 and M4A5-64/32
M4A3-96/48 and M4A5-96/48
M4A3-128/64 and M4A5-128/64
33
33
33
33
M4A3-192/96 and M4A5-192/96
M4A3-256/128 and M4A5-256/128
34
34
M4A3-64/64
36
36
36
36
36
36
M4A3-128/96 and M4A3-128/128
M4A3-192/68 and M4A3-192/128
M4A3-256/160 and M4A3-256/192
M4A3-384
M4A3-512
Because the number of product terms available for a given logic function is not fixed, the full
sum of products is not realized in the array. The product terms drive the logic allocator, which
allocates the appropriate number of product terms to generate the function.
Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in “product term clusters.”
The availability and distribution of product term clusters are automatically considered by the
software as it fits functions within a PAL block. The size of a product term cluster has been
optimized to provide high utilization of product terms, making complex functions using many
product terms possible. Yet when few product terms are used, there will be a minimal number
10
MACH 4 Family
of unused—or wasted—product terms left over. The product term clusters available to each
macrocell within a PAL block are shown in Tables 10 and 11.
Each product term cluster is associated with a macrocell. The size of a cluster depends on the
configuration of the associated macrocell. When the macrocell is used in synchronous mode
(Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in
asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term
cluster is routed to a different macrocell, the allocator configuration is not determined by the
mode of the macrocell actually being driven. The configuration is always set by the mode of the
macrocell that the cluster will drive if not routed away, regardless of the actual routing.
In addition, there is an extra product term that can either join the basic cluster to give an
extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included
with the basic cluster, this provides for up to 20 product terms on a synchronous function that
uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18
product terms.
When the extra product term is used to extend the cluster, the value of the second XOR input
can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic
allocator are shown in Figures 3 and 4.
MACH 4 Family
11
Table 10. Logic Allocator for All MACH 4 and MACH 4A Devices (except M4(LV)-32/32 and M4A(3,5)-32/32)
Output Macrocell
Available Clusters
C , C , C
Output Macrocell
Available Clusters
C , C , C , C
M
M
8
0
0
1
2
7
8
9
10
M
C , C , C , C
M
C , C , C , C
8 9 10 11
1
0
1
2
3
9
M
C , C , C , C
M
C , C , C , C
9 10 11 12
2
1
2
3
4
10
M
C , C , C , C
M
C , C , C , C
10 11 12 13
3
2
3
4
5
11
M
C , C , C , C
M
C , C , C , C
11 12 13 14
4
3
4
5
6
12
M
C , C , C , C
M
C , C , C , C
12 13 14 15
5
4
5
6
7
13
M
C , C , C , C
M
C , C , C
13 14 15
6
5
6
7
8
14
M
C , C , C , C
M
C , C
7
6
7
8
9
15
14 15
Table 11. Logic Allocator for M4(LV)-32/32 and M4A(3,5)-32/32
Output Macrocell
Available Clusters
C , C , C
Output Macrocell
Available Clusters
M
M
C , C , C
8 9 10
0
0
1
2
8
M
C , C , C , C
M
C , C , C , C
8 9 10 11
1
0
1
2
3
9
M
C , C , C , C
M
C , C , C , C
9 10 11 12
2
1
2
3
4
10
M
C , C , C , C
M
C , C , C , C
10 11 12 13
3
2
3
4
5
11
M
C , C , C , C
M
C , C , C , C
11 12 13 14
4
3
4
5
6
12
M
C , C , C , C
M
C , C , C , C
12 13 14 15
5
4
5
6
7
13
M
C , C , C
M
C , C , C
13 14 15
6
5
6
7
14
M
C , C
M
C , C
14 15
7
6
7
15
Logic Allocator
Basic Product
Term Cluster
n
n
0 Default
0 Default
Extra
Product
Term
Prog. Polarity
17466G-005
a. Synchronous Mode
Logic Allocator
Basic Product
Term Cluster
n
n
0 Default
0 Default
Extra
Product
Term
Prog. Polarity
b. Asynchronous Mode
17466G-006
Figure 2. Logic Allocator: Configuration of Cluster “n” Set by Mode of Macrocell “n”
12
MACH 4 Family
a. Basic cluster w ith XOR
b. Extended cluster, active high
c. Extended cluster, active low
0
d. Basic cluster routed aw ay;
single-product-term, active high
e. Extended cluster routed aw ay
17466G-007
Figure 3. Logic Allocator Configurations: Synchronous Mode
a. Basic cluster w ith XOR
b. Extended cluster, active high
c. Extended cluster, active low
0
d. Basic cluster routed aw ay;
single-product-term, active high
e. Extended cluster routed aw ay
17466G-008
Figure 4. Logic Allocator Configurations: Asynchronous Mode
Note that the configuration of the logic allocator has absolutely no impact on the speed of the
signal. All configurations have the same delay. This means that designers do not have to decide
between optimizing resources or speed; both can be optimized.
If not used in the cluster, the extra product term can act in conjunction with the basic cluster to
provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flip-
flop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to
another macrocell, the extra product term is still available for logic. In this case, the first XOR
input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without
giving up the use of the macrocell.
Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the
ends of the block have fewer product terms available.
MACH 4 Family
13
Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and
initialization control. The macrocell has two fundamental modes: synchronous and
asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the
macrocell.
Power-Up
Reset
PAL-Block
Initialization
Product Terms
SWAP
Common PAL-block resource
Individual macrocell resources
To Output and Input
Switch Matrices
AP
AR
From Logic Allocator
Q
D/T/L
Block CLK0
Block CLK1
Block CLK2
Block CLK3
From
PAL-Clock
Generator
17466G-009
a. Synchronous mode
Power-Up
Reset
Individual
Initialization
Product Term
To Output and Input
Switch Matrices
AP
AR
From Logic
Allocator
Q
D/T/L
Block CLK0
Block CLK1
From PAL-Block
Clock Generator
Individual Clock
Product Term
b. Asynchronous mode
Figure 5. Macrocell
17466G-010
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous
mode will generally be used, since it provides more product terms in the allocator.
14
MACH 4 Family
The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be
synthesized. The primary flip-flop configurations are shown in Figure 6, although others are
possible. Flip-flop functionality is defined in Table 12. Note that a J-K latch is inadvisable as it
will cause oscillation if both J and K inputs are HIGH.
AP AR
AP AR
D
Q
D
Q
b. D-type w ith programmable D polarity
a. D-type w ith XOR
AP AR
AP AR
L
Q
L
Q
G
G
c. Latch w ith XOR
d. Latch w ith programmable D polarity
AP AR
T
Q
f. Combinatorial w ith XOR
e. T-type w ith programmable T polarity
g. Combinatorial w ith programmable polarity
17466G-011
Figure 6. Primary Macrocell Configurations
MACH 4 Family
15
Table 12. Register/Latch Operation
1
Configuration
Input(s)
CLK/LE
Q+
D=X
D=0
D=1
0,1, ↓ (↑)
↑ (↓)
Q
0
D-type Register
T-type Register
↑ (↓)
1
T=X
T=0
T=1
0, 1, ↓ (↑)
↑ (↓)
Q
Q
Q
↑ (↓)
D=X
D=0
D=1
1(0)
0(1)
0(1)
Q
0
D-type Latch
1
Note:
1. Polarity of CLK/LE can be programmed
Although the macrocell shows only one input to the register, the XOR gate in the logic allocator
allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product
terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the
extra product term must be used on the XOR gate input for flip-flop emulation. In any register
type, the polarity of the inputs can be programmed.
The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode,
with the additional choice of either polarity of an individual product term clock in the
asynchronous mode.
The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous
reset and preset are provided, each driven by a product term common to the entire PAL block.
Power-Up
Reset
Power-Up
Preset
PAL-Block
PAL-Block
Initialization
Initialization
Product Terms
Product Terms
AR
Q
AP
D/T/L
AR
Q
AP
D/L
a. Pow er-up reset
b. Pow er-up preset
17466G-012
17466G-013
Figure 7. Synchronous Mode Initialization Configurations
16
MACH 4 Family
A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged,
providing flexibility. In asynchronous mode (Figure 8), a single individual product term is
provided for initialization. It can be selected to control reset or preset.
Power-Up
Preset
Power-Up
Reset
Individual
Preset
Product Term
Individual
Reset
Product Term
AR
Q
AP
D/L/T
AR
Q
AP
D/L/T
a. Reset
b. Preset
17466G-014
17466G-015
Figure 8. Asynchronous Mode Initialization Configurations
Note that the reset/preset swapping selection feature effects power-up reset as well. The
initialization functionality of the flip-flops is illustrated in Table 13. The macrocell sends its data
to the output switch matrix and the input switch matrix. The output switch matrix can route this
data to an output if so desired. The input switch matrix can send the signal back to the central
switch matrix as feedback.
Table 13. Asynchronous Reset/Preset Operation
1
AR
0
AP
0
CLK/LE
Q+
X
X
X
X
See Table 12
0
1
1
0
0
1
0
1
1
Note:
1. Transparent latch is unaffected by AR, AP
Output Sw itch Matrix
The output switch matrix allows macrocells to be connected to any of several I/O cells within a
PAL block. This provides high flexibility in determining pinout and allows design changes to
occur without effecting pinout.
In MACH 4 and MACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as
many macrocells as I/O cells. The MACH 4 output switch matrix allows for half of the macrocells
to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can
choose from eight macrocells; each macrocell has a choice of four I/O cells. The MACH 4 and
MACH 4A devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/
O cells (Figure 9).
MACH 4 Family
17
M0
M1
M2
M3
M4
M5
M6
M7
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
M0
M1
M0
M1
I/O0
I/O1
M2
M2
I/O2
M3
M3
I/O3
M4
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
M4
I/O4
M5
M5
I/O5
M6
M6
I/O6
M7
M7
I/O7
M8
M8
I/O8
M8
M9
I/O8
M9
M9
I/O9
I/O9
M10
M11
M12
M13
M14
M15
M10
M11
M12
M13
M14
M15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
M10
M11
M12
M13
M14
M15
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Each I/O cell can
choose one of 8
macrocells in
Each macrocell can drive
one of 4 I/O cells in MACH 4
and MACH 4A devices with
Each macrocell can drive
one of 8 I/O cells in MACH
4A devices with 1:1
Each macrocell can drive
one of 8 I/O cells in
M4(LV)-32/32 and
all MACH 4 and
MACH 4A devices.
2:1 macrocell-I/O cell ratio. macrocell-I/O cell ratio except
M4A(3, 5)-32/32 devices.
M4A(3, 5)-32/32 devices.
Figure 9. MACH 4 Output Sw itch Matrix
Table 14. Output Sw itch Matrix Combinations for MACH 4 and MACH 4A
Devices w ith 2:1 Macrocell-I/O Cell Ratio
Macrocell
M0, M1
Routable to I/O Cells
I/O0, I/O5, I/O6, I/O7
I/O0, I/O1, I/O6, I/O7
I/O0, I/O1, I/O2, I/O7
I/O0, I/O1, I/O2, I/O3
I/O1, I/O2, I/O3, I/O4
I/O2, I/O3, I/O4, I/O5
I/O3, I/O4, I/O5, I/O6
I/O4, I/O5, I/O6, I/O7
M2, M3
M4, M5
M6, M7
M8, M9
M10, M11
M12, M13
M14, M15
I/O Cell
I/O0
Available Macrocells
M0, M1, M2, M3, M4, M5, M6, M7
M2, M3, M4, M5, M6, M7, M8, M9
M4, M5, M6, M7, M8, M9, M10, M11
M6, M7, M8, M9, M10, M11, M12, M13
M8, M9, M10, M11, M12, M13, M14, M15
M0, M1, M10, M11, M12, M13, M14, M15
I/O1
I/O2
I/O3
I/O4
I/O5
18
MACH 4 Family
Table 14. Output Sw itch Matrix Combinations for MACH 4 and MACH 4A
Devices w ith 2:1 Macrocell-I/O Cell Ratio
Macrocell
I/O6
Routable to I/O Cells
M0, M1, M2, M3, M12, M13, M14, M15
M0, M1, M2, M3, M4, M5, M14, M15
I/O7
Table 15. Output Sw itch Matrix Combinations for MACH 4 and MACH 4A Devices w ith 1:1 Macrocell-I/O Cell
Ratio except M4(LV)-32/32 and M4A(3,5)-32/32
Macrocell
M0
Routable to I/O Cells
I/O0
I/O0
I/O0
I/O0
I/O0
I/O0
I/O0
I/O0
I/O8
I/O8
I/O8
I/O8
I/O8
I/O8
I/O8
I/O8
I/O1
I/O1
I/O1
I/O1
I/O1
I/O1
I/O1
I/O1
I/O9
I/O9
I/O9
I/O9
I/O9
I/O9
I/O9
I/O9
I/O2
I/O3
I/O4
I/O4
I/O5
I/O5
I/O6
I/O6
I/O7
M1
I/O2
I/O3
I/O7
M2
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
M3
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
M4
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
M5
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
M6
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
M7
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
M8
I/O10
I/O10
I/O10
I/O10
I/O10
I/O10
I/O10
I/O10
I/O11
I/O11
I/O11
I/O11
I/O11
I/O11
I/O11
I/O11
I/O12
I/O12
I/O12
I/O12
I/O12
I/O12
I/O12
I/O12
I/O13
I/O13
I/O13
I/O13
I/O13
I/O13
I/O13
I/O13
I/O14
I/O14
I/O14
I/O14
I/O14
I/O14
I/O14
I/O14
I/O15
I/O15
I/O15
I/O15
I/O15
I/O15
I/O15
I/O15
M9
M10
M11
M12
M13
M14
M15
I/O Cell
I/O0
Available Macrocells
M0
M0
M0
M0
M0
M0
M0
M0
M8
M8
M8
M8
M8
M8
M8
M8
M1
M1
M1
M1
M1
M1
M1
M1
M9
M9
M9
M9
M9
M9
M9
M9
M2
M3
M4
M5
M6
M7
I/O1
M2
M3
M4
M5
M6
M7
I/O2
M2
M3
M4
M5
M6
M7
I/O3
M2
M3
M4
M5
M6
M7
I/O4
M2
M3
M4
M5
M6
M7
I/O5
M2
M3
M4
M5
M6
M7
I/O6
M2
M3
M4
M5
M6
M7
I/O7
M2
M3
M4
M5
M6
M7
I/O8
M10
M10
M10
M10
M10
M10
M10
M10
M11
M11
M11
M11
M11
M11
M11
M11
M12
M12
M12
M12
M12
M12
M12
M12
M13
M13
M13
M13
M13
M13
M13
M13
M14
M14
M14
M14
M14
M14
M14
M14
M15
M15
M15
M15
M15
M15
M15
M15
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
MACH 4 Family
19
Table 16. Output Sw itch Matrix Combinations for M4(LV)-32/32 and M4A(3,5)-32/32
Macrocell
Routable to I/O Cells
M0, M1, M2, M3, M4, M5, M6, M7
M8, M9, M10, M11, M12, M13, M14, M15
I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7
I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
I/O Cell
Available Macrocells
I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7
I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15
M0, M1, M2, M3, M4, M5, M6, M7
M8, M9, M10, M11, M12, M13, M14, M15
20
MACH 4 Family
I/O Cell
The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback
path, and flip-flop (except MACH 4 and MACH 4A devices with 1:1 macrocell-I/O cell ratio.) An
individual output enable product term is provided for each I/O cell. The feedback signal drives
the input switch matrix.
Individual
Output Enable
Product Term
From Output
Switch Matrix
Individual
Output Enable
Product Term
To
Input
Switch
Matrix
From Output
Switch Matrix
D/L
Q
To
Input
Switch
Matrix
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Power-up reset
17466G-017
17466G-018
Figure 10. I/O Cell for MACH 4 and MACH 4A Devices Figure 11. I/O Cell for MACH 4 and MACH 4A Devices
w ith 2:1 Macrocell-I/O Cell Ratio w ith 1:1 Macrocell-I/O Cell Ratio
The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input
in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and
registered versions of the input are sent to the input switch matrix. This allows for such functions
as “time-domain-multiplexed” data comparison, where the first data value is stored, and then the
second data value is put on the I/O pin and compared with the previous stored value.
Note that the flip-flop used in the MACH 4 I/O cell is independent of the flip-flops in the
macrocells. It powers up to a logic low.
Zero-Hold-Time Input Register
The MACH 4 devices have a zero-hold-time (ZHT) fuse which controls the time delay associated
with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse
increases the data path setup delays to input storage elements, matching equivalent delays in
the clock path. When the fuse is erased, the setup time to the input storage element is minimized.
This feature facilitates doing worst-case designs for which data is loaded from sources which
have low (or zero) minimum output propagation delays from clock edges.
Input Sw itch Matrix
The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch
matrix. Without the input switch matrix, each input and feedback signal has only one way to
enter the central switch matrix. The input switch matrix provides additional ways for these
signals to enter the central switch matrix.
MACH 4 Family
21
From Input Cell
17466G-002
17466G-003
Figure 12. MACH 4 and MACH 4A w ith 2:1
Macrocell-I/O Cell Ratio - Input Sw itch Matrix
Figure 13. MACH 4 and MACH 4A w ith 1:1
Macrocell-I/O Cell Ratio - Input Sw itch Matrix
PAL Block Clock Generation
Each MACH 4 device has four clock pins that can also be used as inputs. These pins drive a
clock generator in each PAL block (Figure 14). The clock generator provides four clock signals
that can be used anywhere in the PAL block. These four PAL block clock signals can consist of
a large number of combinations of the true and complement edges of the global clock signals.
Table 17 lists the possible combinations.
GCLK0
Block CLK0
(GCLK0 or GCLK1)
GCLK1
Block CLK1
(GCLK1 or GCLK0)
GCLK2
Block CLK2
(GCLK2 or GCLK3)
GCLK3
Block CLK3
(GCLK3 or GCLK2)
17466G-004
1
Figure 14. PAL Block Clock Generator
Note:
1. M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied
to GCLK0, and GCLK3 is tied to GCLK1.
22
MACH 4 Family
1
Table 17. PAL Block Clock Combinations
Block CLK0
Block CLK1
Block CLK2
Block CLK3
GCLK0
GCLK1
GCLK0
GCLK1
X
GCLK1
GCLK1
GCLK0
GCLK0
X
X
X
X
X
X
X
X
X
GCLK2 (GCLK0)
GCLK3 (GCLK1)
GCLK2 (GCLK0)
GCLK3 (GCLK1)
GCLK3 (GCLK1)
GCLK3 (GCLK1)
GCLK2 (GCLK0)
GCLK2 (GCLK0)
X
X
X
X
X
X
Note:
1. Values in parentheses are for the M4(LV)-32/32, M4A(3,5)-32/32, M4(LV)-64/32 and M4A(3,5)-64/32.
This feature provides high flexibility for partitioning state machines and dual-phase clocks. It
also allows latches to be driven with either polarity of latch enable, and in a master-slave
configuration.
MACH 4 Family
23
MACH 4 TIMING MODEL
The primary focus of the MACH 4 timing model is to accurately represent the timing in a MACH
4 device, and at the same time, be easy to understand. This model accurately describes all
combinatorial and registered paths through the device, making a distinction between internal
feedback and external feedback. A signal uses internal feedback when it is fed back into the
switch matrix or block without having to go through the output buffer. The input register
specifications are also reported as internal feedback. When a signal is fed back into the switch
matrix after having gone through the output buffer, it is using external feedback.
The parameter, t , is defined as the time it takes to go from feedback through the output buffer
BUF
to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter
designator is followed by an “i”. By adding t
to this internal parameter, the external parameter
BUF
is derived. For example, t = t
+ t . A diagram representing the modularized MACH 4
PD
PDi
BUF
timing model is shown in Figure 15. Refer to the Technical Note entitled MACH 4 Timing and
High Speed Design for a more detailed discussion about the timing parameters.
(External Feedback)
(Internal Feedback)
COMB/DFF/TFF/
LATCH/SR*/JK*
tSLW
*emulated
Central
Switch
Matrix
IN
OUT
tSS(T)
tPDi
tBUF
Q
tSA(T)
tPDLi
tH(S/A)
tS(S/A)L
tH(S/A)L
tSRR
tCO(S/A)i
tGO(S/A)i
tSRi
tPL
INPUT REG/
INPUT LATCH
tEA
tER
S/R
tSIRS
tHIRS
tSIL
tPDILi
tICOSi
tIGOSi
tPDILZi
Q
tHIL
tSIRZ
tHIRZ
tSILZ
tHILZ
BLK CLK
17466G-025
Figure 15. MACH 4 Timing Model
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The MACH 4 architecture allows allocation of up to 20 product terms to an individual macrocell
with the assistance of an XOR gate without incurring additional timing delays.
The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is
independent of the logic required by the design. Other non-Vantis CPLDs incur serious timing
delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and
SpeedLocking combine to give designs easy access to the performance required in today’s
designs.
24
MACH 4 Family
IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY
All MACH 4 devices, except the M4(LV)-128N/64, have boundary scan cells and are compliant
to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the
device is mounted through a serial scan path that can access all critical logic nodes. Internal
registers are linked internally, allowing test data to be shifted in and loaded directly onto test
nodes, or test node data to be captured and shifted out for verification. In addition, these devices
can be linked into a board-level serial scan path for more complete board-level testing.
IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of significant benefits including: rapid
prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.
All MACH 4 devices provide In-System Programming (ISP) capability through their Boundary
ScanTest Access Ports. This capability has been implemented in a manner that ensures that the
port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication
interface through which ISP is achieved, customers get the benefit of a standard, well-defined
interface.
MACH 4 devices can be programmed across the commercial temperature and voltage range.
Vantis provides its free PC-based Lattice/VantisPRO software to facilitate in-system programming.
Lattice/VantisPRO takes the JEDEC file output produced by Vantis’ design implementation
software, along with information about the JTAG chain, and creates a set of vectors that are used
to drive the JTAG chain. Lattice/VantisPRO software can use these vectors to drive a JTAG chain
via the parallel port of a PC. Alternatively, Lattice/VantisPRO software can output files in formats
understood by common automated test equipment. This equpment can then be used to program
MACH 4 devices during the testing of a circuit board. For more information about in-system
programming, refer to the separate document entitled MACH ISP Manual.
PCI COMPLIANT
MACH 4(A) devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI
Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V
devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI
condition to clamp the inputs as they rise above V because of their 5-V input tolerant feature.
CC
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS
Both the 3.3-V and 5-V V MACH 4 devices are safe for mixed supply voltage system designs.
CC
The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they
accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the
5-V and 3.3-V versions have the same high-speed performance and provide easy-to-use mixed-
voltage design capability.
PULL UP OR BUS-FRIENDLY INPUTS AND I/OS
All MACH 4 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating
two inverters in series which loop back to the input. This double inversion weakly holds the
input at its last driven logic state. While it is good design practice to tie unused pins to a known
state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where
noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a
MACH 4 Family
25
logic level “1.” For the circuit diagram, please refer to the Input/Output Equivalent Schematics
(page 393) in the General Information Section of the Vantis 1999 Data Book.
All MACH 4A devices have a programmable bit that configures all inputs and I/Os with either
pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs
and I/O pins are weakly pulled up. For the circuit diagram, please refer to the Input/Output
Equivalent Schematics (page 393) in the General Information Section of the Vantis 1999 Data
Book.
POWER MANAGEMENT
Each individual PAL block in MACH 4 devices features a programmable low-power mode, which
results in power savings of up to 50%. The signal speed paths in the low-power PAL block will
be slower than those in the non-low-power PAL block. This feature allows speed critical paths
to run at maximum frequency while the rest of the signal paths operate in the low-power mode.
PROGRAMMABLE SLEW RATE
Each MACH 4 device I/O has an individually programmable output slew rate control bit. Each
output can be individually configured for the higher speed transition (3 V/ns) or for the lower
noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew
rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For
designs with short traces or well terminated lines, the fast slew rate can be used to achieve the
highest speed. The slew rate is adjusted independent of power.
POWER-UP RESET/SET
All flip-flops power up to a known state for predictable system initialization. If a macrocell is
configured to SET on a signal from the control generator, then that macrocell will be SET during
device power-up. If a macrocell is configured to RESET on a signal from the control generator
or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee
initialization values, the V rise must be monotonic, and the clock must be inactive until the
CC
reset delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the MACH 4 devices as a deterrent to unauthorized
copying of the array configuration patterns. Once programmed, this bit defeats readback of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
Programming and verification are also defeated by the security bit. The bit can only be reset by
erasing the entire device.
HOT SOCKETING
MACH 4A devices are well-suited for those applications that require hot socketing capability.
Hot socketing a device requires that the device, when powered down, can tolerate active signals
on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the
powered-down MACH devices be minimal on active signals.
26
MACH 4 Family
M4(LV)-64/32, M4A(3, 5)-64/32
M4(LV)-96/48, M4A(3, 5)-96/48
M4(LV)-128/64, M4A(3, 5)-128/64
M4A3-384
M4A3-512
M4(LV)-192/96, M4(3, 5)-192/96
M4(LV)-256/128, M4(3, 5)-256/128
CLOCK
A
A
B
16
17
17
17
18
18
GENERATOR
4
0
M0
C0
C1
MACROCELL
MACROCELL
I/O0
M0
I/O
O0
O1
M1
CELL
M1
M2
M3
C2
C3
MACROCELL
MACROCELL
M2
M3
I/O1
I/O2
I/O3
I/O
CELL
M4
M5
C4
C5
MACROCELL
MACROCELL
M4
M5
I/O
CELL
O2
O3
M6
M7
C6
C7
MACROCELL
MACROCELL
M6
M7
I/O
CELL
M8
M9
C8
C9
MACROCELL
MACROCELL
M8
M9
I/O4
I/O5
I/O6
I/O
CELL
O4
O5
O6
M10
M11
C10
C11
MACROCELL
MACROCELL
M10
M11
I/O
CELL
M12
M13
C12
C13
MACROCELL
MACROCELL
M12
M13
I/O
CELL
M14
M15
C14
C15
MACROCELL
MACROCELL
I/O7
M14
M15
I/O
CELL
O7
89
B
16
24
INPUT SWITCH
MATRIX
16
Figure 16. PAL Block for MACH 4 and MACH 4A w ith 2:1 Macrocell - I/O Cell Ratio
17466H-40
MACH 4 Family
27
Figure 17. PAL Block for MACH 4A Devices w ith 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32)
17466H-41
28
MACH 4 Family
CLK0/I0 CLK0/I1
CLOCK
16
GENERATOR
2
0
I/O0
I/O1
M0
M1
I/O
CELL
O0
O1
MACROCELL
MACROCELL
M0
M1
C0
C1
I/O
CELL
I/O2
I/O3
M2
M3
I/O
CELL
C2
C3
O2
O3
MACROCELL
MACROCELL
M2
M3
I/O
CELL
I/O4
I/O5
M4
M5
I/O
CELL
C4
C5
O4
O5
MACROCELL
MACROCELL
M4
M5
I/O
CELL
I/O6
I/O7
M6
M7
I/O
CELL
C6
C7
MACROCELL
MACROCELL
O6
O7
M6
M7
I/O
CELL
I/O8
I/O9
M8
M9
I/O
CELL
C8
C0
O8
O9
MACROCELL
MACROCELL
M8
M9
I/O
CELL
I/O10
I/O11
M10
M11
I/O
CELL
C0
C0
O10
O11
MACROCELL
MACROCELL
M10
M11
I/O
CELL
I/O12
I/O13
M12
M13
I/O
CELL
C0
C0
O12
O13
MACROCELL
MACROCELL
M12
M13
I/O
CELL
I/O14
I/O15
M14
M15
I/O
CELL
C0
C0
MACROCELL
MACROCELL
O14
O15
M14
M15
I/O
CELL
97
17
16
INPUT
SWITCH
MATRIX
32
16
Figure 18. PAL Block for M4(LV)-32/32 and M4A (3,5)-32/32
17466H-042
MACH 4 Family
29
BLOCK DIAGRAM – M4(LV)-32/32 AND M4A(3,5)-32/32
Block A
I/O8–I/O15
I/O0–I/O7
8
8
I/O Cells
I/O Cells
8
8
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
8
4
4
8
8
8
Macrocells
Macrocells
2
8
8
66 X 98
AND Logic Array
and Logic Allocator
16
16
16
33
Central Switch Matrix
2
2
33
16
66 X 98
AND Logic Array
and Logic Allocator
8
2
8
Macrocells
8
Macrocells
8
8
8
8
4
4
8
8
8
Output Switch
Matrix
Output Switch
Matrix
8
8
I/O Cells
8
I/O Cells
8
I/O16–I/O23
I/O24–I/O31
Block B
17466H-019
30
MACH 4 Family
BLOCK DIAGRAM – M4(LV)-64/32 AND M4A(3,5)-64/32
Block A
Block D
I/O0–I/O7
I/O24–I/O31
8
8
I/O Cells
I/O Cells
8
8
4
4
4
4
Output Switch
Matrix
Output Switch
Matrix
8
8
16
16
16
16
16
16
Macrocells
Macrocells
16
16
66 X 90
AND Logic Array
and Logic Allocator
66 X 90
AND Logic Array
and Logic Allocator
2
2
24
24
24
33
33
33
Central Switch Matrix
2
2
33
24
66 X 90
66 X 90
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
2
2
16
16
Macrocells
Macrocells
16
16
16
4
4
4
4
16
16
16
8
8
Output Switch
Matrix
Output Switch
Matrix
8
8
I/O Cells
8
I/O Cells
8
I/O8–I/O15
I/O16–I/O23
Block C
Block B
17466H-020
MACH 4 Family
31
BLOCK DIAGRAM – M4(LV)-96/48 AND M4A(3,5)-96/48
I2, I3, I6, I7
Input Switch
Matrix
Input Switch
Matrix
OE
OE
OE
OE
Clock Generator
Clock Generator
Input Switch
Matrix
Input Switch
Matrix
OE
Clock Generator
Clock Generator
Input Switch
Matrix
Input Switch
Matrix
OE
Clock Generator
Clock Generator
17466G-021
CLK0/I0, CLK1/I1,
CLK2/I4, CLK3/I5
MACH 4 Family
32
BLOCK DIAGRAM – M4(LV)-128N/64, M4(LV)-128/64 AND M4A(3,5)-128/64
I2, I5
Input Switch
Matrix
Input Switch
Matrix
OE
OE
OE
OE
OE
Clock Generator
Clock Generator
Input Switch
Matrix
Input Switch
Matrix
OE
Clock Generator
Clock Generator
Input Switch
Matrix
Input Switch
Matrix
OE
Clock Generator
Clock Generator
Input Switch
Matrix
Input Switch
Matrix
OE
Clock Generator
Clock Generator
CLK0/I0, CLK1/I1,
CLK2/I3, CLK3/I4
17466H-022
33
MACH 4 Family
BLOCK DIAGRAM – M4(LV)-192/96 AND M4A(3,5)-192/96
Block B
I/O8–I/O15
Block A
I/O0–I/O7
Block L
I/O88–I/O95
Block K
I/O80–I/O87
CLK0–CLK3
4
4
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
4
4
4
4
4
4
4
4
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
Macrocells
Macrocells
Macrocells
Macrocells
16
16
16
16
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
4
4
4
4
24
24
24
24
34
34
34
34
I/O72–I/O79 Block J
I/O64–I/O71 Block I
Block C I/O16–I/O23
Block D I/O24–I/O31
8
8
8
8
I/O Cells
8
I/O Cells
I/O Cells
I/O Cells
8
8
8
4
4
4
4
4
4
4
4
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
Macrocells
Macrocells
Macrocells
Macrocells
16
16
16
16
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
4
4
4
4
24
24
24
24
34
34
34
34
34
34
34
34
24
24
24
24
68 X 90
68 X 90
68 X 90
68 X 90
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
4
4
4
4
16
16
16
16
Macrocells
16
Macrocells
16
Macrocells
16
Macrocells
16
16
16
16
16
4
4
4
4
4
4
4
4
16
16
16
16
8
8
8
8
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
I/O Cells
8
8
I/O Cells
8
8
8
I/O Cells
I/O Cells
8
8
16
I0–I15
I/O32–I/O39
I/O40–I/O47
I/O48–I/O55
I/O56–I/O63
Block E
Block F
Block G
Block H
17466G-064
MACH 4 Family
34
BLOCK DIAGRAM – M4(LV)-256/128 AND M4A(3,5)-256/128
Block B
I/O8–I/O15
Block A
I/O0–I/O7
Block P
I/O120–I/O127
Block O
I/O112–I/O119
CLK0–CLK3
4
4
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
4
4
4
4
4
4
4
4
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
Macrocells
Macrocells
Macrocells
Macrocells
16
16
16
16
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
4
4
4
4
24
24
24
24
34
34
34
34
34
34
34
34
24
24
24
24
68 X 90
68 X 90
68 X 90
68 X 90
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
4
4
4
4
16
16
16
16
Macrocells
16
Macrocells
16
Macrocells
16
Macrocells
16
16
16
16
16
4
4
4
4
4
4
4
4
16
16
16
16
8
8
8
8
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
I/O Cells
8
8
8
8
I/O Cells
8
I/O Cells
I/O Cells
8
8
8
Block C I/O16–I/O23
Block D I/O24–I/O31
Block E I/O32–I/O39
Block F I/O40–I/O47
I/O104–I/O111 Block N
I/O96–I/O103 Block M
I/O88–I/O95 Block L
I/O80–I/O87 Block K
8
8
8
I/O Cells
8
I/O Cells
I/O Cells
I/O Cells
8
8
8
4
4
4
4
4
4
4
4
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
Macrocells
Macrocells
Macrocells
Macrocells
16
16
16
16
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
68 X 90
AND Logic Array
and Logic Allocator
4
4
4
4
24
24
24
24
34
34
34
34
34
34
34
34
24
24
24
24
68 X 90
68 X 90
68 X 90
68 X 90
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
4
4
4
4
16
16
16
16
Macrocells
16
Macrocells
16
Macrocells
16
Macrocells
16
16
16
16
16
4
4
4
4
4
4
4
4
16
16
16
16
8
8
8
8
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
I/O Cells
8
8
I/O Cells
8
8
8
I/O Cells
I/O Cells
8
8
14
I0–I13
I/O48–I/O55
I/O56–I/O63
I/O64–I/O71
I/O72–I/O79
Block G
Block H
Block I
Block J
17466G-024
35
MACH 4 Family
BLOCK DIAGRAM – M4A3-384/192
CLK0–CLK3
Block B
Block A
Block HX
Block GX
I/O8–I/O15
I/O0–I/O7
I/O184–I/O191
I/O176–I/O183
4
4
4
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
Detail A
4
4
4
4
4
4
4
4
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
Macrocells
Macrocells
Macrocells
Macrocells
16
16
16
16
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
4
4
4
4
24
24
24
24
36
36
36
36
36
36
36
36
24
24
24
24
72 X 90
72 X 90
72 X 90
72 X 90
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
4
4
4
4
16
16
16
16
Macrocells
16
Macrocells
16
Macrocells
16
Macrocells
16
16
16
16
16
4
4
4
4
4
4
4
4
16
16
16
16
8
8
8
8
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
Block D I/O24–I/O31
Block E I/O32–I/O39
Block C I/O16–I/O23
Block F I/O40–I/O47
I/O168–I/O175 Block FX
I/O144–I/O151 Block CX
I/O160–I/O167 Block EX
I/O152–I/O159 Block DX
Repeat Detail A
Block G I/O48–I/O55
Block J I/O72–I/O79
Block H I/O56–I/O63
Block I I/O64–I/O71
I/O128–I/O135 Block AX
I/O120–I/O127 Block P
I/O136–I/O143 Block BX
I/O112–I/O119 Block O
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
4
4
4
4
4
4
4
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
16
16
16
16
4
16
16
16
16
16
16
16
16
Macrocells
Macrocells
Macrocells
Macrocells
16
16
16
16
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
4
4
4
4
24
24
24
24
24
36
36
36
36
36
36
36
36
24
24
24
72 X 90
72 X 90
72 X 90
72 X 90
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
4
4
4
4
16
16
16
16
Macrocells
16
Macrocells
16
Macrocells
16
Macrocells
16
16
16
16
16
4
4
4
4
4
4
4
4
16
16
16
16
8
8
8
8
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
I/O Cells
I/O Cells
8
I/O Cells
8
I/O Cells
8
8
I/O80–I/O87
I/O88–I/O95
I/O196–I/O103
I/O104–I/O111
Block K
Block L
Block M
Block N
17466G-067
MACH 4 Family
36
BLOCK DIAGRAM - M4A3-512/256
CLK0–CLK3
Block B
Block A
Block PX
Block OX
I/O8–I/O15
I/O0–I/O7
I/O248–I/O255
I/O240–I/O247
4
4
4
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
Detail A
4
4
4
4
4
4
4
4
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
16
16
16
16
16
16
16
16
16
16
16
16
Macrocells
Macrocells
Macrocells
Macrocells
16
16
16
16
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
4
4
4
4
24
24
24
24
36
36
36
36
36
36
36
36
24
24
24
24
72 X 90
72 X 90
72 X 90
72 X 90
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
4
4
4
4
16
16
16
16
Macrocells
16
Macrocells
16
Macrocells
16
Macrocells
16
16
16
16
16
4
4
4
4
4
4
4
4
16
16
16
16
8
8
8
8
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
I/O Cells
8
Block D I/O24–I/O31
Block E I/O32–I/O39
Block C I/O16–I/O23
Block F I/O40–I/O47
I/O232–I/O239 Block NX
I/O208–I/O215 Block KX
I/O224–I/O231 Block MX
I/O216–I/O223 Block LX
Repeat Detail A
Repeat Detail A
Block G I/O48–I/O55
Block J I/O72–I/O79
Block H I/O56–I/O63
Block I I/O64–I/O71
I/O192–I/O199 Block IX
I/O184–I/O191 Block HX
I/O200–I/O207 Block JX
I/O176–I/O183 Block GX
Block K I/O80–I/O87
Block L I/O88–I/O95
Block M I/O96–I/O103
I/O160–I/O167 Block EX
I/O152–I/O159 Block DX
I/O168–I/O175 Block FX
I/O144–I/O151 Block CX
Block N I/O104–I/O111
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
8
I/O Cells
8
4
4
4
4
4
4
4
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
16
16
16
16
4
16
16
16
16
16
16
16
16
Macrocells
Macrocells
Macrocells
Macrocells
16
16
16
16
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
72 X 90
AND Logic Array
and Logic Allocator
4
4
4
4
24
24
24
24
24
36
36
36
36
36
36
36
36
24
24
24
72 X 90
72 X 90
72 X 90
72 X 90
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
AND Logic Array
and Logic Allocator
4
4
4
4
16
16
16
16
Macrocells
16
Macrocells
16
Macrocells
16
Macrocells
16
16
16
16
16
4
4
4
4
4
4
4
4
16
16
16
16
8
8
8
8
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
Output Switch
Matrix
8
8
8
8
I/O Cells
I/O Cells
8
I/O Cells
8
I/O Cells
8
8
I/O112–I/O119
I/O120–I/O127
I/O128–I/O135
I/O136–I/O143
Block O
Block P
Block AX
Block BX
17466G-068
37
MACH 4 Family
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
M4 and M4A5
Commercial (C) Devices
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature (T )
A
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . -55°C to +100°C
Supply Voltage (V )
CC
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Device Junction Temperature . . . . . . . . . . . . . +130°C
Supply Voltage
with Respect to Ground . . . . . . . . . . . -0.5 V to +7.0 V
Industrial (I) Devices
Ambient Temperature (T )
A
DC Input Voltage . . . . . . . . . . . . -0.5 V to V + 0.5 V
Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V
Supply Voltage (V )
CC
with Respect to Ground . . . . . . . . . . +4.50 V to +5.5 V
Latchup Current (T = -40°C to +85°C). . . . . . . 200 mA
A
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Str esses a bove those listed u n der Absolu te Ma ximu m
Ratings may cause permanent device failure. Functionality at
or a bove these limits is not implied. Exposure to Absolute
Ma ximum Ra tings for extended periods ma y a ffect device
reliability.
5-V DC CHARACTERISTICS OVER OPERATING RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Conditions
= –3.2 mA, V = Min, V = V or V
IL
Min
Typ
Max
Unit
V
I
2.4
OH
CC
IN
IH
V
OH
I
= 0 mA, V = Max, V = V or V
IL
3.3
0.5
V
OH
CC
IN
IH
V
Output LOW Voltage
Input HIGH Voltage
I
= 24 mA, V = Min, V = V or V (Note 1)
V
OL
OL
CC
IN
IH
IL
Guaranteed Input Logical HIGH Voltage for all Inputs
(Note 2)
V
2.0
V
V
IH
Guaranteed Input Logical LOW Voltage for all Inputs
(Note 2)
V
Input LOW Voltage
0.8
IL
I
Input HIGH Leakage Current
V = 5.25 V, V = Max (Note 3)
10
–10
10
µA
µA
µA
µA
mA
IH
IN
CC
I
Input LOW Leakage Current
V = 0 V, V = Max (Note 3)
IN CC
IL
I
Off-State Output Leakage Current HIGH
Off-State Output Leakage Current LOW
Output Short-Circuit Current
V
= 5.25 V, V = Max, V = V or V (Note 3)
OZH
OUT CC IN IH IL
I
V
= 0 V, V = Max , V = V or V (Note 3)
–10
–160
OZL
OUT
CC
IN
IH
IL
I
V
= 0.5 V, V = Max (Note 4)
–30
SC
OUT
CC
Notes:
1. Total I for one PAL block should not exceed 64 mA.
OL
2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
3. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
V
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
OUT
MACH 4 Family
38
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
M4LV and M4A3
Commercial (C) Devices
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature (T )
A
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . -55°C to +100°C
Supply Voltage (V )
CC
with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V
Device Junction Temperature . . . . . . . . . . . . . +130°C
Supply Voltage
with Respect to Ground . . . . . . . . . . . -0.5 V to +4.5 V
Industrial (I) Devices
Ambient Temperature (T )
A
DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 6.0 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V
Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (V )
CC
with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V
Latchup Current (T = -40°C to +85°C). . . . . . . 200 mA
A
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Str esses a bove those listed u n der Absolu te Ma ximu m
Ratings may cause permanent device failure. Functionality at
or a bove these limits is not implied. Exposure to Absolute
Ma ximum Ra tings for extended periods ma y a ffect device
reliability.
3.3-V DC CHARACTERISTICS OVER OPERATING RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Conditions
= –100 µA
Min
Typ
Max
Unit
V
I
V – 0.2
V = Min
OH
CC
CC
V
OH
V = V or V
I
= –3.2 mA
= 100 µA
= 24 mA
2.4
V
IN
IH
IL
OH
V = Min
CC
I
0.2
0.5
V
V
OL
V
Output LOW Voltage
V = V or V
OL
IN IH IL
I
(Note 1)
OL
Guaranteed Input Logical HIGH Voltage for all
Inputs
V
Input HIGH Voltage
Input LOW Voltage
2.0
5.5
0.8
V
V
IH
Guaranteed Input Logical LOW Voltage for all
Inputs
V
–0.3
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V = 3.6 V, V = Max (Note 2)
5
µA
µA
IH
IN
CC
I
V = 0 V, V = Max (Note 2)
–5
IL
IN
CC
V
= 3.6 V, V = Max
CC
OUT
I
Off-State Output Leakage Current HIGH
5
µA
OZH
V = V or V (Note 2)
IN
IH
IL
V
= 0 V, V = Max
CC
OUT
I
Off-State Output Leakage Current LOW
Output Short-Circuit Current
–5
µA
OZL
V = V or V (Note 2)
IN
IH
IL
I
V
= 0.5 V, V = Max (Note 3)
–15
–160
mA
SC
OUT
CC
Notes:
1. Total I for one PAL block should not exceed 64 mA.
OL
2. I/O pin leakage is the worst case of I and I
(or I and I
).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
39
MACH 4 Family
MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Unit
Combinatorial Delay:
t
Internal combinatorial propagation delay
Combinatorial propagation delay
5.5
7.5
8.0
10.0
12.0
12.0
14.0
13.0
15.0
16.0
18.0
ns
ns
PDi
t
10.0
PD
Registered Delays:
t
Synchronous clock setup time, D-type register
Synchronous clock setup time, T-type register
Asynchronous clock setup time, D-type register
Asynchronous clock setup time, T-type register
Synchronous clock hold time
5.5
6.5
3.5
4.5
0.0
3.5
6.0
7.0
4.0
5.0
0.0
4.0
7.0
8.0
5.0
6.0
0.0
5.0
10.0
11.0
8.0
10.0
11.0
8.0
12.0
13.0
10.0
11.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SS
t
SST
t
SA
t
9.0
9.0
SAT
t
0.0
0.0
HS
t
Asynchronous clock hold time
8.0
8.0
10.0
HA
t
Synchronous clock to internal output
Synchronous clock to output
3.5
5.5
7.5
9.5
4.5
6.5
6.0
8.0
8.0
8.0
10.0
12.0
18.0
20.0
COSi
t
10.0
16.0
18.0
10.0
16.0
18.0
COS
t
Asynchronous clock to internal output
Asynchronous clock to output
10.0
12.0
12.0
14.0
COAi
t
COA
Latched Delays:
t
Synchronous Latch setup time
6.0
4.0
0.0
4.0
7.0
4.0
0.0
4.0
8.0
5.0
0.0
5.0
10.0
8.0
0.0
8.0
10.0
8.0
0.0
8.0
12.0
10.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SSL
t
Asynchronous Latch setup time
Synchronous Latch hold time
SAL
t
HSL
t
Asynchronous Latch hold time
10.0
HAL
t
Transparent latch to internal output
Propagation delay through transparent latch to output
Synchronous Gate to internal output
Synchronous Gate to output
8.0
10.0
4.0
10.0
12.0
5.5
12.0
14.0
8.0
15.0
17.0
9.0
15.0
17.0
9.0
18.0
20.0
10.0
12.0
20.0
22.0
PDLi
t
PDL
t
GOSi
t
6.0
7.5
10.0
14.0
16.0
11.0
17.0
19.0
11.0
17.0
19.0
GOS
t
Asynchronous Gate to internal output
Asynchronous Gate to output
9.0
11.0
13.0
GOAi
t
11.0
GOA
Input Register Delays:
t
Input register setup time
2.0
3.0
2.0
3.0
2.0
3.0
2.0
4.0
2.0
4.0
2.0
4.0
ns
ns
ns
SIRS
t
Input register hold time
HIRS
t
Input register clock to internal feedback
3.5
4.5
6.0
6.0
6.0
6.0
ICOSi
Input Latch Delays:
t
Input latch setup time
2.0
3.0
2.0
3.0
2.0
3.0
2.0
4.0
2.0
4.0
2.0
4.0
ns
ns
ns
ns
SIL
t
Input latch hold time
HIL
t
Input latch gate to internal feedback
Transparent input latch to internal feedback
4.0
2.0
4.0
2.0
4.0
2.0
5.0
2.0
5.0
2.0
6.0
2.0
IGOSi
t
PDILi
Input Register Delays with ZHT Option:
t
Input register setup time - ZHT
Input register hold time - ZHT
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
ns
ns
SIRZ
t
HIRZ
MACH 4 Family
40
MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input Latch Delays with ZHT Option:
t
Input latch setup time - ZHT
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
ns
ns
ns
SILZ
t
Input latch hold time - ZHT
HILZ
t
Transparent input latch to internal feedback - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
PDILZi
Output Delays:
t
Output buffer delay
Slow slew rate delay adder
Output enable time
2.0
2.5
9.5
9.5
2.0
2.5
2.0
2.5
2.0
2.5
2.0
2.5
2.0
2.5
ns
ns
ns
ns
BUF
t
SLW
t
10.0
10.0
12.0
12.0
15.0
15.0
15.0
15.0
17.0
17.0
EA
t
Output disable time
ER
Power Delay:
Power-down mode delay adder
Reset and Preset Delays:
t
2.5
2.5
2.5
2.5
2.5
2.5
ns
PL
t
Asynchronous reset or preset to internal register output
Asynchronous reset or preset to register output
Asynchronous reset and preset register recovery time
Asynchronous reset or preset width
10.0
12.0
12.0
14.0
14.0
16.0
18.0
20.0
18.0
20.0
20.0
22.0
ns
ns
ns
ns
SRi
t
SR
t
8.0
8.0
10.0
12.0
15.0
15.0
15.0
15.0
17.0
17.0
SRR
t
10.0
10.0
SRW
Clock/LE Width:
t
Global clock width low
3.0
3.0
4.0
4.0
5.0
5.0
5.0
5.0
6.0
6.0
8.0
8.0
6.0
6.0
9.0
9.0
6.0
6.0
9.0
9.0
7.0
7.0
ns
ns
ns
ns
WLS
t
Global clock width high
WHS
t
Product term clock width low
Product term clock width high
10.0
10.0
WLA
t
WHA
Global gate width low (for low transparent) or high
(for high transparent)
t
5.0
4.0
5.0
5.0
6.0
6.0
6.0
9.0
6.0
9.0
7.0
ns
ns
GWS
Product term gate width low (for low transparent) or
high (for high transparent)
t
11.0
GWA
t
Input register clock width low
Input register clock width high
Input latch gate width
4.5
4.5
5.0
5.0
5.0
5.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
7.0
7.0
7.0
ns
ns
ns
WIRL
t
WIRH
t
6.0
WIL
41
MACH 4 Family
MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Unit
Frequency:
External feedback, D-type, Min of 1/(t + t ) or
WLS WHS
90.9
83.3
80.0
74.1
95.2
87.0
100.0
62.5
58.8
71.4
66.7
100.0
100.0
66.7
62.5
76.9
71.4
83.3
52.6
50.0
58.8
55.6
62.5
83.3
50.0
47.6
55.6
52.6
83.3
38.5
37.0
41.7
40.0
55.6
83.3
50.0
47.6
55.6
52.6
83.3
38.5
37.0
41.7
40.0
55.6
83.3
41.7
40.0
45.5
43.5
71.4
33.3
32.3
35.7
34.5
50.0
71.4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1/(t + t
)
SS COS
External feedback, T-type, Min of 1/(t + t ) or
WLS WHS
1/(t + t
)
SST COS
Internal feedback (f ), D-type,
CNT
f
111.1
100.0
153.8
76.9
MAXS
Min of 1/(t + t ) or 1/(t + t
)
WLS WHS
SS COSi
Internal feedback (f ), T-type,
CNT
Min of 1/(t + t ) or 1/(t + t
)
WLS WHS
2
SST COSi
No feedback , Min of 1/(t + t ), 1/(t + t ) or
WLS WHS
SS HS
1/(t + t )
SST HS
External feedback, D-type, Min of 1/(t + t ) or
WLA WHA
1/(t + t
)
SA COA
External feedback, T-type, Min of 1/(t + t ) or
WLA WHA
71.4
1/(t + t
)
SAT COA
Internal feedback (f ), D-type,
CNTA
f
90.9
MAXA
Min of 1/(t + t ) or 1/(t + t
)
WLA WHA
SA COAi
Internal feedback (f ), T-type,
CNTA
83.3
Min of 1/(t + t ) or 1/(t + t
)
WLA WHA
2
SAT COAi
No feedback , Min of 1/(t + t ),
WLA WHA
125.0
111.0
1/(t + t ) or 1/(t + t )
SA HA
SAT HA
Maximum input register frequency,
Min of 1/(t + t ) or 1/(t + t
f
MAXI
)
SIRS HIRS
WIRH WIRL
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Combinatorial Delay:
Internal combinatorial
t
3.5
5.0
4.0
5.5
4.0
6.0
4.5
6.5
5.0
7.5
7.0
9.0
11.0
14.0
ns
ns
PDi
propagation delay
Combinatorialpropagation
delay
t
10.0
12.0
PD
Registered Delays:
Synchronous clock setup
t
3.0
4.0
2.5
3.0
0.0
3.5
4.0
2.5
3.0
0.0
4.0
4.5
3.0
3.5
0.0
4.0
4.5
3.0
3.5
0.0
5.5
6.5
3.5
4.5
0.0
6.0
7.0
4.0
5.0
0.0
7.0
8.0
5.0
6.0
0.0
10.0
11.0
8.0
ns
ns
ns
ns
ns
SS
time, D-type register
Synchronous clock setup
time, T-type register
t
SST
Asynchronous clock setup
time, D-type register
t
SA
Asynchronous clock setup
time, T-type register
t
9.0
SAT
Synchronous clock hold
time
t
0.0
HS
MACH 4 Family
42
MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Asynchronous clock hold
time
t
2.5
2.5
3.0
3.0
3.5
4.0
5.0
8.0
ns
ns
ns
ns
ns
HA
Synchronous clock to
internal output
t
2.5
4.0
5.0
6.5
2.5
4.0
5.0
6.5
2.5
4.5
5.0
7.0
2.5
4.5
5.0
7.0
2.5
5.0
6.0
8.5
2.5
5.5
3.5
6.5
3.5
6.5
COSi
Synchronous clock to
output
t
COS
Asynchronous clock to
internal output
t
8.0
10.0
13.0
12.0
15.0
COAi
Asynchronous clock to
output
t
11.0
COA
Latched Delays:
Synchronous latch setup
t
4.0
3.0
0.0
3.0
4.0
3.0
0.0
3.0
4.5
3.5
0.0
3.5
4.5
3.5
0.0
3.5
6.0
4.0
0.0
4.0
7.0
4.0
0.0
4.0
8.0
5.0
0.0
5.0
10.0
8.0
0.0
8.0
ns
ns
ns
ns
ns
ns
SSL
time
Asynchronous latch setup
time
t
SAL
Synchronous latch hold
time
t
HSL
Asynchronous latch hold
time
t
HAL
Transparent latch to
internal output
t
5.5
7.0
5.5
7.0
6.0
8.0
6.0
8.0
7.5
9.0
11.0
14.0
12.0
15.0
PDLi
Propagation delay through
transparent latch to output
t
10.0
12.0
PDL
Synchronous gate to
internal output
t
3.0
4.5
6.0
3.0
4.5
6.0
3.0
5.0
6.0
3.0
5.0
6.0
3.5
6.0
8.5
4.5
7.5
7.0
8.0
ns
ns
ns
GOSi
t
Synchronous gate to output
10.0
13.0
11.0
15.0
GOS
Asynchronous gate to
internal output
t
10.0
GOAi
Asynchronous gate to
output
t
7.5
7.5
8.0
8.0
11.0
13.0
16.0
6.0
18.0
6.0
ns
GOA
Input Register Delays:
t
Input register setup time
Input register hold time
1.5
2.5
1.5
2.5
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
4.0
ns
ns
SIRS
t
HIRS
Input register clock to
internal feedback
t
3.0
3.0
3.0
3.0
3.5
4.5
ns
ICOSi
Input Latch Delays:
t
Input latch setup time
Input latch hold time
1.5
2.5
1.5
2.5
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
3.0
2.0
4.0
ns
ns
SIL
t
HIL
Input latch gate to internal
feedback
t
3.5
1.5
3.5
1.5
4.0
1.5
4.0
1.5
4.0
2.0
4.0
2.0
4.0
2.0
5.0
2.0
ns
ns
IGOSi
Transparent input latch to
internal feedback
t
PDILi
MACH 4 Family
43
MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input Register Delays with ZHT Option:
-55
-6
-65
-7
-10
-12
-14
Input register setup time -
ZHT
t
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
ns
ns
SIRZ
Input register hold time -
ZHT
t
HIRZ
Input Latch Delays with ZHT Option:
Input latch setup time -
ZHT
t
6.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
6.0
0.0
ns
ns
ns
SILZ
t
Input latch hold time - ZHT 0.0
HILZ
Transparent input latch to
internal feedback - ZHT
t
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
PDILZi
Output Delays:
t
Output buffer delay
Slow slew rate delay adder
Output enable time
1.5
2.5
7.5
7.5
1.5
2.5
7.5
7.5
2.0
2.5
8.5
8.5
2.0
2.5
8.5
8.5
2.5
2.5
9.5
9.5
3.0
2.5
3.0
2.5
3.0
2.5
ns
ns
ns
ns
BUF
t
SLW
t
10.0
10.0
12.0
12.0
15.0
15.0
EA
t
Output disable time
ER
Power Delay:
Power-down mode delay
adder
t
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
PL
Reset and Preset Delays:
Asynchronous reset or
t
preset to internal register
output
7.5
9.0
7.7
9.2
8.0
8.0
9.5
11.0
14.0
13.0
16.0
16.0
19.0
ns
ns
ns
ns
SRi
Asynchronous reset or
preset to register output
t
10.0
10.0
12.0
SR
Asynchronous reset and
preset register recovery
time
t
7.0
7.0
7.0
7.0
7.5
8.0
7.5
8.0
8.0
8.0
10.0
12.0
15.0
15.0
SRR
Asynchronous reset or
preset width
t
10.0
10.0
SRW
Clock/LE Width:
t
Global clock width low
Global clock width high
2.0
2.0
2.0
2.0
2.5
2.5
2.5
2.5
3.0
3.0
5.0
5.0
6.0
6.0
6.0
6.0
ns
ns
WLS
t
WHS
Product term clock width
low
t
3.0
3.0
3.0
3.0
3.5
3.5
3.5
3.5
4.0
4.0
5.0
5.0
8.0
8.0
9.0
9.0
ns
ns
WLA
Product term clock width
high
t
WHA
Global gate width low (for
low transparent) or high
(for high transparent)
t
4.0
4.0
4.5
4.5
5.0
5.0
6.0
6.0
ns
GWS
Product term gate width
low (for low transparent)
or high (for high
t
4.0
3.0
4.0
3.0
4.5
3.5
4.5
3.5
5.0
4.0
5.0
5.0
6.0
6.0
9.0
6.0
ns
ns
GWA
transparent)
Input register clock width
low
t
WIRL
44
MACH 4 Family
MACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-55
-6
-65
-7
-10
-12
-14
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input register clock width
high
t
3.0
4.0
3.0
4.0
3.5
4.5
3.5
4.5
4.0
5.0
5.0
5.0
6.0
6.0
6.0
6.0
ns
ns
WIRH
t
Input latch gate width
WIL
Frequency:
External feedback, D-type,
Min of 1/(t + t ) or 143
133
125
167
154
250
111
105
133
125
167
118
111
154
143
200
100
95.2
125
118
143
118
111
154
143
200
100
95.2
125
118
143
95.2
87.0
125
111
154
83.3
76.9
105
95.2
125
87.0
80.0
100
105
125
66.7
62.5
83.3
76.9
100
74.1
69.0
83.3
87.0
100
60.6
57.1
74.1
69.0
83.3
43.5
41.7
50.0
47.6
55.6
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
WLS WHS
1/(t + t
)
SS COS
External feedback, T-type,
Min of 1/(t + t ) or 125
WLS WHS
1/(t + t
)
SST COS
Internal feedback (f ),
CNT
f
D-type, Min of 1/(t
+
)
182
154
MAXS
WLS
t
) or 1/(t + t
WHS
SS COSi
Internal feedback (f ),
CNT
+
T-type, Min of 1/(t
WLS
t
) or 1/(t + t
)
WHS
SST COSi
2
No feedback , Min of 1/
(t + t ), 1/(t + t ) 250
WLS WHS
SS HS
or 1/(t + t )
SST HS
External feedback, D-type,
Min of 1/(t + t ) or 111
55.6
52.6
66.7
62.5
62.5
WLA WHA
1/(t + t
)
SA COA
External feedback, T-type,
Min of 1/(t + t ) or 105
WLA WHA
1/(t + t
)
SAT COA
Internal feedback (f ),
CNTA
f
D-type, Min of 1/(t
+
)
133
125
167
MAXA
WLA
t
) or 1/(t + t
WHA
SA COAi
Internal feedback (f ),
CNTA
+
T-type, Min of 1/(t
WLA
t
) or 1/(t + t
)
WHA
SAT COAi
2
No feedback , Min of 1/
(t + t ), 1/(t
+
SA
WLA WHA
t ) or 1/(t + t )
HA
SAT HA
Maximum input register
frequency, Min of 1/(t
WIRH
f
167
167
143
143
125
100
83.3
83.3
MHz
MAXI
+ t ) or 1/(t
+
WIRL
SIRS
t
)
HIRS
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
MACH 4 Family
45
CAPACITANCE 1
Parameter Symbol
Parameter Description
Input capacitance
Test Conditions
3.3 V or 5 V, 25°C, 1 MHz
3.3 V or 5 V, 25°C, 1 MHz
Typ
6
Unit
pF
C
V =2.0 V
IN
IN
C
Output capacitance
V
=2.0V
8
pF
I/O
OUT
Note:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where this parameter may be affected.
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system
frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the
device and exercises every macrocell. Maximum frequency shown uses internal feedback and
a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the
lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to
high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to
lowest power.
V
= 5 V or 3.3 V, T = 25 °C
CC
A
350
300
250
200
150
100
M4(LV)-256/128
M4(LV)-192/96
M4(LV)-128/64
M4(LV)-96/48
M4(LV)-64/32
M4(LV)-32/32
50
0
17466G-066
17466G-044
Frequency (MHz)
Figure 19. I Curves at High Pow er Mode
CC
46
MACH 4 Family
V
= 5 V or 3.3 V, T = 25 °C
A
350
300
250
200
150
100
CC
M4(LV)-256/128
M4(LV)-192/96
M4(LV)-128/64
M4(LV)-96/48
M4(LV)-64/32
M4(LV)-32/32
50
0
17466G-065
Frequency (MHz)
Figure 20. I Curves at Low Pow er Mode
CC
V
= 3.3V, T = 25°C
A
CC
M4A3-256/128 (HP)
HP: High Power
LP: Low Power
300
250
200
150
100
50
M4A3-256/128 (LP)
M4A3-128/64 (HP)
Icc (mA)
M4A3-128/64 (LP)
M4A3-32/32 (HP)
M4A3-32/32 (LP)
0
0
20
40
60
80 100 120 140 160 180 200 220 240 260
Frequency (MHz)
Figure 21. MACH 4A Device Dynamic Icc Curves at High and Low Pow er Modes
17466H-066
MACH 4 Family
47
44-PIN PLCC CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32,
M4(LV)-64/32 AND M4A(3,5)-64/32)
Top View
44-Pin PLCC
M4(LV)-64/32
M4(LV)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
40
1 44 43 42 41
6
5
4
3
2
39
I/O27 D3
I/O26 D2
I/O25 D1
I/O24 D0
TDO
B3
B2
B1
B0
7
A2
A1
A0
A2 I/O5
A1 I/O6
A0 I/O7
TDI
38
8
37
36
35
34
9
10
11
12
CLK0/I0
GND
M4(LV)-32/32
M4A(3,5)-32/32
M4(LV)-32/32
M4A(3,5)-32/32
GND
CLK1/I1
TMS
33
32
31
30
29
TCK
13
14
15
16
17
A8
A9
B0 I/O8
B1 I/O9
B2 I/O10
B3 I/O11
C0
C1
C2
B8
I/O23
I/O22
I/O21
B9
A10
A11
B10
28
18 19 20 21 22 23 24 25 26 27
M4(LV)-64/32
M4(LV)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
17466G-026
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
C
7
I/O
= Input/Output
= Supply Voltage
V
CC
I/O Cell (0-7)
TDI = Test Data In
TCK = Test Clock
PAL Block (A-D)
TMS = Test Mode Select
TDO = Test Data Out
48
MACH 4 Family
44-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32,
M4(LV)-64/32 AND M4A(3,5)-64/32)
Top View
44-Pin TQFP
M4(LV)-64/32
M4(LV)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
A2
A1
A0
A2
A1
A0
I/O5
I/O6
I/O7
TDI
I/O27 D3
I/O26 D2
I/O25 D1
I/O24 D0
TDO
GND
CLK1/I1
TMS
B3
B2
B1
B0
M4(LV)-32/32
M4A(3,5)-32/32
CLK0/I0
GND
M4(LV)-32/32
M4A(3,5)-32/32
TCK
I/O8
I/O9
A8
A9
A10
A11
B0
B1
B2 I/O10
B3 I/O11
9
10
11
I/O23
I/O22
I/O21
C0
C1
C2
B8
B9
B10
M4(LV)-64/32
M4(LV)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I/O
= Input/Output
= Supply Voltage
C
7
V
CC
I/O Cell (0-7)
TDI = Test Data In
TCK = Test Clock
PAL Block (A-D)
TMS = Test Mode Select
TDO = Test Data Out
MACH 4 Family
49
48-PIN TQFP CONNECTION DIAGRAM (M4(LV)-32/32, M4A(3,5)-32/32,
M4(LV)-64/32 AND M4A(3,5)-64/32)
Top View
48-Pin TQFP
M4(LV)-64/32
M4(LV)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
A2
A1
A0
A2 I/O5
A1 I/O6
A0 I/O7
TDI
CLK0/I0
NC
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
I/O27 D3
I/O26 D2
I/O25 D1
I/O24 D0
TDO
B3
B2
B1
B0
M4(LV)-32/32
M4A(3,5)-32/32
GND
NC
M4(LV)-32/32
M4A(3,5)-32/32
GND
TCK
CLK1/I1
TMS
I/O23 C0
I/O22 C1
I/O21 C2
A8
A9
A10
A11
B0
B1
B2
B3
9
I/O8
I/O9
I/O10
I/O11
10
11
12
B8
B9
B10
M4(LV)-64/32
M4(LV)-64/32
M4A(3,5)-64/32
M4A(3,5)-64/32
17466G-028
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I/O
= Input/Output
= Supply Voltage
= No Connect
C
7
V
CC
NC
I/O Cell (0-7)
TDI = Test Data In
TCK = Test Clock
PAL Block (A-D)
TMS = Test Mode Select
TDO = Test Data Out
50
MACH 4 Family
100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-96/48 AND M4A(3,5)-96/48)
Top View
100-Pin TQFP
NC
TDI
NC
NC
TDO
NC
NC
NC
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
A1
A0
B0
B1
I/O6
I/O7
I/O8
I/O9
I/O41
I/O40
I/O39
I/O38
I/O37
I/O36
I5/CLK3
GND
VCC
I4/CLK2
I/O35
I/O34
I/O33
I/O32
I/O31
I/O30
NC
F1
F0
E0
E1
E2
E3
B2 I/O10
B3 I/O11
I0/CLK0
VCC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
I1/CLK1
B4 I/O12
B5 I/O13
B6 I/O14
B7 I/O15
C0 I/O16
C1 I/O17
NC
E4
E5
E6
E7
D0
D1
NC
TMS
TCK
NC
NC
NC
NC
17466G-029
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
C
7
I
= Input
I/O
= Input/Output
= Supply Voltage
= No Connect
I/O Cell (0-7)
V
CC
NC
PAL Block (A-F)
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
MACH 4 Family
51
84-PIN PLCC CONNECTION DIAGRAM (M4(LV)-128N/64)
Top View
84-Pin PLCC
8
4 3
84 83
8180 78 7776 75
79
82
9
7 6 5
2 1
1110
12
B7
B6
B5
B4
B3
B2
B1
B0
74 GND
I/O8
I/O9
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
73 I/O55 G7
72
I/O54 G6
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
71
G5
I/O53
G4
70
I/O52
G3
G2
G1
G0
69 I/O51
68
67
66
I/O50
I/O49
I/O48
CLK /I
0 0
65 CLK /I
V
3 4
CC
64
63
62
61
60
GND
V
GND
CLK /I
CC
1 1
CLK /I
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
C0
C1
C2
C3
C4
C5
C6
C7
2 3
I/O47 F0
I/O46
59 I/O45
F1
F2
F3
F4
F5
58
I/O44
I/O43
I/O42
I/O41 F6
I/O40
57
56
55
54
F7
33
4142
4546 47
50 5152
48 49
53
3536
39 40
3738
43 44
34
17466G-030
Note:
Pin-compatible with the MACH131, MACH231, MACH435.
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
C
7
I/O Cell (0-7)
I
= Input
I/O
= Input/Output
= Supply Voltage
PAL Block (A-H)
V
CC
52
MACH 4 Family
100-PIN PQFP CONNECTION DIAGRAM (M4(LV)-128/64 AND M4A(3,5)-128/64)
Top View
100-Pin PQFP
1
2
3
4
5
6
7
8
9
80
79
78
77
GND
GND
TD0
TRST
I/O55
I/O54
I/O53
I/O52
I/O51
GND
GND
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
(83)
(12)
(13)
(14)
(15)
(16)
B7
B6
B5
B4
B3
B2
B1
B0
G7
G6
G5
G4
G3
G2
G1
G0
(73) 76
(72) 75
(71) 74
(70) 73
(69) 72
(68) 71
(67) 70
(66) 69
(65) 68
67
10(17)
11 (18)
12(19)
13(20)
14
15
16
17
I/O50
I/O49
I/O48
I4/CLK3
GND
I/O14
I/O15
IO/CLK0
V
CC
V
CC
GND
66
65
64
63
62
61
V
GND
CC
V
CC
GND
I1/CLK1
I/O16
(23)
(24)
(25)
18
19
20
I3/CLK2
I/O47
I/O46
(62)
(61)
(60)
C0
C1
F0
F1
I/O17
(26)
(27)
(28)
(29)
(30)
(31)
21
22
23
24
25
26
27
28
29
30
C2
C3
C4
C5
C6
C7
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
TMS
TCK
GND
GND
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
ENABLE
GND
GND
F2
F3
F4
F5
F6
F7
60
59
58
57
56
55
54
53
52
51
(59)
(58)
(57)
(56)
(55)
(54)
(41)
Note:
The numbers in parentheses reflect compatible pin numbers for 84-pin PLCC.
PIN DESIGNATIONS
I/CLK = Input or Clock
GND = Ground
C
7
I
= Input
I/O
= Input/Output
= Supply Voltage
I/O Cell (0-7)
V
CC
PAL Block (A-H)
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
TRST
= Test Reset
ENABLE = Program
MACH 4 Family
53
100-PIN TQFP CONNECTION DIAGRAM (M4(LV)-128/64 AND M4A(3,5)-128/64)
Top View
100-Pin TQFP
GND
TDI
I/O8
I/O9
GND
TDO
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
B7
B6
TRST
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
G7
G6
G5
G4
G3
G2
G1
G0
B5 I/O10
B4 I/O11
B3 I/O12
B2 I/O13
B1 I/O14
B0 I/O15
I0/CLK0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
GND
CC
I1/CLK1
I/O16
I/O17
C1
I/O18
I/O19
C3
I/O20
I/O21
C5
V
CC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
ENABLE
GND
C0
F0
F1
F2
F3
F4
F5
F6
F7
C2
C4
I/O22
I/O23
C7
C6
TMS
TCK
GND
17466G-032
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
= Input
C
7
I/O
= Input/Output
= Supply Voltage
V
CC
I/O Cell (0-7)
TDI = Test Data In
TCK = Test Clock
PAL Block (A-H)
TMS = Test Mode Select
TDO = Test Data Out
TRST
= Test Reset
ENABLE = Program
54
MACH 4 Family
144-PIN TQFP CONNECTION DIAGRAM (M4(LV)-192/96 AND M4A(3,5)-192/96)
Top View
144-Pin TQFP
GND
TDI
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
GND
TDO
NC
D7
D6
D5
D4
D3
D2
D1
D0
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I2
I3
VCC
GND
I4
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
GND
VCC
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
TMS
TCK
GND
I/O71 K0
I/O70 K1
I/O69 K2
I/O68 K3
I/O67 K4
I/O66 K5
I/O65 K6
I/O64 K7
I12
VCC
GND
I11
I10
I/O63 J0
I/O62 J1
I/O61 J2
I/O60 J3
I/O59 J4
I/O58 J5
I/O57 J6
I/O56 J7
GND
VCC
I/O55
I/O54
I/O53
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
C7
C6
C5
C4
C3
C2
C1
C0
E7
E6
E5
E4
E3
E2
E1
E0
I0
I1
I2
I3
I4
I5
I6
I7
I/O52
I/O51
I/O50
I/O49
I/O48
NC
GND
74
73
17466G-033
PIN DESIGNATIONS
CLK = Clock
GND = Ground
C
7
I
= Input
I/O
= Input/Output
= Supply Voltage
I/O Cell (0-7)
V
CC
TDI = Test Data In
TCK = Test Clock
PAL Block (A-L)
TMS = Test Mode Select
TDO = Test Data Out
MACH 4 Family
55
176-PIN TQFP CONNECTION DIAGRAM - M4A3-256/128, M4A3-192/128,
M4A3-128/128, AND M4A3-384/132
Top View
176-Pin TQFP
PIN DESIGNATIONS
CLK
GND
I
I/O
N/C
=
=
=
=
=
=
=
=
=
=
=
=
Clock
Ground
Input ( ) shows equivalent pin in M4A3-256/128 (208PQFP)
Input/Output
No Connect
Supply Voltage
Test Data In
Test Clock
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE
Test Mode Select
C
7
Test Data Out
Test Reset
Program
I/O Cell (0-7)
PAL Block (A-HX)
17466G-042
56
MACH 4 Family
208-PIN PQFP CONNECTION DIAGRAM - M4A3-256/128, M4A5-256/128,
M4-256/128, M4LV-256/128, AND M4A3-384/160
Top View
208-Pin PQFP
PIN DESIGNATIONS
CLK
GND
I
I/O
N/C
=
=
=
=
=
=
=
=
=
=
=
=
Clock
Ground
Input ( ) shows equivalent pin in M4A3-256/128 (208PQFP)
Input/Output
No Connect
Supply Voltage
Test Data In
Test Clock
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE
Test Mode Select
C
7
Test Data Out
Test Reset
Program
I/O Cell (0-7)
PAL Block (A-HX)
17466G-044
MACH 4 Family
57
256-BALL BGA CONNECTION DIAGRAM (M4(LV)-256/128 AND
M4A(3,5)-256/128)
Bottom View
256-Ball BGA
PIN DESIGNATIONS
CLK
GND
I
I/O
N/C
=
=
=
=
=
=
=
=
=
=
=
=
Clock
Ground
Input
Input/Output
No Connect
Supply Voltage
Test Data In
Test Clock
Test Mode Select
Test Data Out
Test Reset
Program
VCC
TDI
TCK
TMS
TDO
TRST
ENABLE
C
7
I/O Cell (0-7)
PAL Block (A-P)
17466G-045
58
MACH 4 Family
256-BALL BGA CONNECTION DIAGRAM - M4A3-384/192
Bottom View
256-Ball BGA
PIN DESIGNATIONS
CLK
GND
I
=
=
=
=
=
=
=
=
=
=
Clock
Ground
Input
Input/Output
No Connect
Supply Voltage
Test Data In
Test Clock
Test Mode Select
Test Data Out
I/O
N/C
VCC
TDI
TCK
TMS
TDO
C
7
I/O Cell (0-7)
PAL Block (A-HX)
17466G-046
MACH 4 Family
59
MACH 4 PRODUCT ORDERING INFORMATION
MACH 4 Devices Commercial & Industrial - 3.3V and 5V
Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is
formed by a combination of:
M4-
256 / 128 -7
Y
C
FAMILY TYPE
M4- = MACH 4 Family (5-V V
48
= 48-pin TQFP for M4(LV)-32/32
or M4(LV)-64/32
)
CC
M4LV- = MACH 4 Family Low Voltage (3.3-V V
)
CC
OPERATING CONDITIONS
C
I
= Commercial (0°C to +70°C)
= Industrial (-40 °C to +85 °C)
MACROCELL DENSITY
32 = 32 Macrocells 128N = 128 Macrocells, Non-ISP
64 = 64 Macrocells 192 = 192 Macrocells
96 = 96 Macrocells 256 = 256 Macrocells
128 = 128 Macrocells
PACKAGE TYPE
A
J
= Ball Grid Array (BGA)
= Plastic Leaded Chip Carrier
(PLCC)
V
Y
= Thin Quad Flat Pack (TQFP)
= Plastic Quad Flat Pack (PQFP)
I/Os
/32 = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP
/48 = 48 I/Os in 100-pin TQFP
/64 = 64 I/Os in 84-pin PLCC, 100-pin PQFP or 100-pin TQFP
/96 = 96 I/Os in 144-pin TQFP
SPEED
-7 = 7.5 ns t
-10 = 10 ns t
PD
PD
/128 = 128 I/Os in 208-pin PQFP or 256-ball BGA
-12 = 12 ns t
-14 = 14 ns t
-15 = 15 ns t
-18 = 18 ns t
PD
PD
PD
PD
Valid Combinations
Valid Combinations
M4-32/32
M4LV-32/32
M4-64/32
M4LV-64/32
M4-96/48
JC, VC, VC48
JC, VC, VC48
JC, VC, VC48
JC, VC, VC48
VC
M4-32/32
M4LV-32/32
M4-64/32
M4LV-64/32
M4-96/48
JI, VI, VI48
JI, VI, VI48
JI, VI, VI48
JI, VI, VI48
VI
M4LV-96/48
M4-128/64
M4LV-128/64
M4-128N/64
M4LV-128N/64
M4-192/96
M4LV-192/96
M4-256/128
M4LV-256/128
VC
M4LV-96/48
M4-128/64
M4LV-128/64
M4-128N/64
M4LV-128N/64
M4-192/96
M4LV-192/96
M4-256/128
M4LV-256/128
VI
YC, VC
YC, VC
JC
JC
VC
VC
YC, AC
YC, AC
YI, VI
YI, VI
JI
JI
VI
VI
YI, AI
YI, AI
-7, -10, -12, -15
-10, -12, -14, -18
All MACH devices are dual-marked with both Commercial and
Industrial grades. The Industrial speed grade is slower, i.e.,
M4-256/128-7YC-10YI
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
Lattice/ Vantis sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
60
MACH 4 Family
MACH 4A PRODUCT ORDERING INFORMATION
MACH 4A Devices Commercial and Industrial - 3.3V and 5V
Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is
formed by a combination of:
/
M4A3- 256 128 -7
Y
C
FAMILY TYPE
M4A3- = MACH4FamilyLowVoltageAdvancedFeature
(3.3-V V
48
= 48-pin TQFP for
M4A3-32/32 or M4A3-64/32
M4A5-32/32 or M4A5-64/32
)
CC
M4A5- = MACH 4 Family Advanced Feature (5-V V
)
CC
OPERATING CONDITIONS
C
I
= Commercial (0°C to +70°C)
= Industrial (-40 °C to +85 °C)
MACROCELL DENSITY
32 = 32 Macrocells 192 = 192 Macrocells
64 = 64 Macrocells 256 = 256 Macrocells
96 = 96 Macrocells 384 = 384 Macrocells
128 = 128 Macrocells 512 = 512 Macrocells
PACKAGE TYPE
A
J
= Ball Grid Array (BGA)
= Plastic Leaded Chip Carrier
(PLCC)
V
Y
FA
= Thin Quad Flat Pack (TQFP)
= Plastic Quad Flat Pack (PQFP)
= Fine-pitchBallGridArray0.8mm
(fpBGA)
I/Os
/32 = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP
/48 = 48 I/Os in 100-pin TQFP
/64 = 64 I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball fpBGA
/68 = 68 I/Os in 100-pin TQFP or 100-ball fpBGA
/96 = 96 I/Os in 144-pin TQFP or 144-ball fpBGA
/128 = 128 I/Os in 176-pin TQFP, 200-ball fpBGA, 208-pin PQFP, or
256-ball BGA
SPEED
-5
= 5.0 ns t
= 5.5 ns t
PD
PD
PD
-55
-6
= 6.0 ns t
/132 = 132 I/Os in 176-pin TQFP
/160 = 160 I/Os in 208-pin PQFP
-65
-7
= 6.5 ns t
= 7.5 ns t
PD
PD
/192 = 192 I/Os in 256-ball BGA or 320-ball fpBGA
/256 = 256 I/Os in 352-ball BGA
-10
-12
-14
= 10 ns t
= 12 ns t
= 14 ns t
PD
PD
PD
3.3V Commercial Combinations
3.3V Industrial Combinations
JI, VI, VI48
M4A3-32/32
M4A3-64/32
M4A3-64/64
M4A3-96/48
JC, VC, VC48
JC, VC, VC48
VC, FAC
VC
M4A3-32/32
M4A3-64/32
M4A3-64/64
M4A3-96/48
JI, VI, VI48
VI
VI
M4A3-128/64
M4A3-128/96
M4A3-128/128
M4A3-192/68
M4A3-192/96
M4A3-192/128
M4A3-256/128
M4A3-256/160
M4A3-256/192
M4A3-384/132
M4A3-384/160
M4A3-384/192
M4A3-512/132
M4A3-512/160
M4A3-512/192
M4A3-512/256
YC, VC, FAC
VC, FAC
VC, FAC
VC, FAC
VC, FAC
VC, FAC
YC, VC, AC, FAC
YC
AC
VC
YC
AC
M4A3-128/64
M4A3-128/96
M4A3-128/128
M4A3-192/68
M4A3-192/96
M4A3-192/128
M4A3-256/128
M4A3-256/160
M4A3-256/192
M4A3-384/132
M4A3-384/160
M4A3-384/192
M4A3-512/132
M4A3-512/160
M4A3-512/192
M4A3-512/256
YI, VI
VI
VI
VI
VI
-5, -55, -6, -65,
-7, -10, -12
-7, -10, -12, -14
VI
YI, VI, AI
YI
AI
VI
YI
AI
VI
YI
AI
-65, -7, -10, -12
VC
YC
AC
AC
-10, -12, -14
AI
MACH 4 Family
61
5V Commercial Combinations
JC, VC, VC48
5V Industrial Combinations
JI, VI, VI48
M4A5-32/32
M4A5-64/32
M4A5-96/48
M4A5-128/64
M4A5-192/96
M4A5-256/128
M4A5-32/32
M4A5-64/32
M4A5-96/48
M4A5-128/64
M4A5-192/96
M4A5-256/128
JC, VC, VC48
VC
YC, VC
VC
JI, VI, VI48
VI
-5, -55, -6, -65,
-7, -10, -12
-7, -10, -12, -14
-10, -12, -14
YI, VI
VI
-65, -7, -10, -12
YC, VC, AC
YI, VI, AI
Most MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial speed grade is slower, i.e., M4A3-
256/128-7YC-10YI
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice/Vantis sales office
to confirm availability of specific valid combinations and to check on newly released combinations.
Trademarks
Copyright © 1999 Lattice Semiconductor. All rights reserved.
Vantis, the Vantis logo, and combinations thereof, First-Time-Fit, SpeedLocking, Bus-Friendly, DesignDirect, and Lattice/VantisPRO are trademarks,
and MACHPRO, MACHXL, and PAL are registered trademarks of Lattice Semiconductor Corporation.
Other product names used in this publication are for indentification purposes only and may be trademarks of their respective companies.
62
MACH 4 Family
相关型号:
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