MACH231-10JC/1 [LATTICE]
High-Performance EE CMOS Programmable Logic; 高性能EE CMOS可编程逻辑
| 型号： | MACH231-10JC/1 |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | High-Performance EE CMOS Programmable Logic |
| 文件： | 总48页 (文件大小：1080K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
High-performance electrically-erasable CMOS PLD families
32 to 128 macrocells
44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages
SpeedLocking™ – guaranteed fixed timing up to 16 product terms
Commercial 5/5.5/6/7.5/10/12/15-ns t and Industrial 7.5/10/12/14/18-ns t
PD
PD
Configurable macrocells
— Programmable polarity
— Registered or combinatorial outputs
— Internal and I/O feedback paths
— D-type or T-type flip-flops
— Output Enables
— Choice of clocks for each flip-flop
— Input registers for MACH 2 family
JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available
Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns
Safe for mixed supply voltage system designs
Bus-Friendly™ inputs and I/Os reduce risk of unw anted oscillatory outputs
Programmable pow er-dow n mode results in pow er savings of up to 75%
Supported by Vantis DesignDirect™ softw are for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice/Vantis and third-party hardw are programming support
®
— Lattice/VantisPRO™ (formerly known as MACHPRO ) software for in-system programmability
support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication# 1 4051
Amendment/0
Rev: K
Issue Date: November 1 998
1
Table 1. MACH 1 and 2 Family Device Features
Feature
MACH111 (SP)
MACH131 (SP)
MACH211 (SP)
64
MACH221 (SP)
MACH231 (SP)
128
Macrocells
Maximum user I/O pins
(ns)
32
32
64
64
96
48
32
64
t
5.0
3.5
3.5
182
5.5
3.0
4
7.5 (6.0)
5.5 (5)
4.5 (4)
133 (166)
7.5
5.5
5
6.0 (10)
5 (6.5)
PD
t (ns)
S
t
(ns)
4 (6.5)
CO
f
(MHz)
182
133
166 (100)
CNT
Note:
1. Values in parentheses ( ) are for the SP version.
GENERAL DESCRIPTION
®
The MACH 1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex
Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking,
telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns
t
and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall benefits for
PD
users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.
1
Table 2. MACH 1 and 2 Family Speed Grades
Device
-5
-6
-7
C, I
C, I
C, I
C, I
C
-10
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C
-12
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-14
-15
C
C
C
C
C
C
C
C
C
C
-18
MACH111
C (Note 2)
C (Note 2)
C (Note 3)
C (Note 3)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
MACH111SP
MACH131
MACH131SP
MACH211
MACH211SP
MACH221
C
C
C
C
MACH221SP
MACH231
C
C
MACH231SP
C
Notes:
1. C = Commercial, I = Industrial
2. -5 speed grade for MACH111 (SP) = 5.0 ns t
PD
3. -5 speed grade for MACH131(SP) = 5.5 ns t
PD
The MACH 1 & 2 families consist of ten devices—five base options, each with a counterpart that
includes JTAG-compatible in-system programming (ISP). These devices offer five different density-
I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic
Leaded Chip Carrier (PLCC) packages from 44 to 100 pins (Table 3). Each MACH 1 & 2 device is
PCI compliant and includes other features such as SpeedLocking architecture for guaranteed fixed
timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power
savings.
2
MACH 1 & 2 Families
Table 3. MACH 1 and 2 Family Package and I/O Options
Device
MACH111
44-pin PLCC
44-pin TQFP
68-pin PLCC
84-pin PLCC
100-pin TQFP
100-pin PQFP
X
X
X
X
MACH111SP
MACH131
X
MACH131SP
MACH211
X
X
X
X
X
X
MACH211SP
MACH221
X
MACH221SP
MACH231
X
X
X
MACH231SP
X
Note:
1. The MACH110, MACH120, MACH130, MACH210, MACHLV210, MACH215, MACH220 and MACH230 are not listed above and
not recommended for new designs. However, they are still supported by Lattice/Vantis. For technical or sales support, please call
your local Lattice/Vantis sales office or visit our Web site at www.vantis.com for more information.
®
Lattice/Vantis offers software design support for MACH devices in both the MACHXL and
DesignDirect development systems. The DesignDirect development system is the Lattice/Vantis
implementation software that includes support for all Lattice/Vantis CPLD, FPGA, and SPLD
devices. This system is supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX.
DesignDirect software is designed for use with design entry, simulation and verification software
from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model
Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists,
generates JEDEC files for Lattice/Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL
compliant VHDL and SDF simulation netlists for design verification.
DesignDirect software is also available in product configurations that include VHDL and Verilog
synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model
Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.
MACH 1 & 2 Families
3
FUNCTIONAL DESCRIPTION
®
Each MACH 1 and 2 device consists of multiple, optimized PAL blocks interconnected by a switch
matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL
blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs
in a single device instead of using multiple devices.
Clock/Input Pins
Output
Macrocells
I/O Cells
I/O Pins
Array and
Allocator
Buried
Macrocells
PAL Block
I/O Pins
PAL Block
(note 1)
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
I/O Pins
PAL Block
PAL Block
I/O Pins
14051K-002
Dedicated Input
Note:
1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.
Device
MACH111(SP)
PAL Blocks
Macrocells per Block
I/Os per Block
Product Terms per Block
2
4
4
8
8
16
16
16
12
16
16
16
8
70
70
68
52
68
MACH131(SP)
MACH211(SP)
MACH221(SP)
MACH231(SP)
6
8
Figure 1. Overall Architecture of MACH 1 & 2 Devices
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must
go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices
communicate with each other with guaranteed fixed timing (SpeedLocking).
The switch matrix makes a MACH device more advanced than simply several PAL devices on a
single chip. It allows the designer to think of the device not as a collection of blocks, but as a
single programmable device; the software partitions the design into PAL blocks through the
central switch matrix so that the designer does not have to be concerned with the internal
architecture of the device.
4
MACH 1 & 2 Families
Each PAL block consists of the following elements:
Product-term array
Logic Allocator
Macrocells
I/O cells
Each PAL block additionally contains an asynchronous reset product term and an asynchronous
preset product term. This allows the flip-flops within a single PAL block to be initialized as a bank.
There are also output enable product terms that provide tri-state control for the I/O cells.
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic being
implemented. The inputs to the AND gates come from the switch matrix (Table 4), and are
provided in both true and complement forms for efficient logic implementation.
Because the number of product terms available for a given function is not fixed, the full sum of
products is not realized in the array. The product terms drive the logic allocator, which allocates
the appropriate number of product terms to generate the function.
Table 4. PAL Block Inputs
Device
Number of Inputs to PAL Block
Device
MACH211SP
Number of Inputs to PAL Block
MACH111
26
26
26
26
26
26
26
26
32
32
MACH111SP
MACH131
MACH221
MACH221SP
MACH231
MACH131SP
MACH211
MACH231SP
Logic Allocator
The logic allocator (Figure 2) is a block within which different product terms are allocated to the
appropriate macrocells in groups of four product terms called “product term clusters”. The
availability and distribution of product term clusters is automatically considered by the software as
it fits functions within the PAL block. The size of the product term clusters has been designed to
provide high utilization of product terms. Complex functions using many product terms are
possible, and when few product terms are used, there will be a minimal number of unused, or
wasted, product terms left over.
The product term clusters do not “wrap” around the logic block. This means that the macrocells
at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8).
MACH 1 & 2 Families
5
To
To From
n-2 n-1
n-1
*
To Macrocell
n
n
n
Product Term
Cluster
*
To
n+1
From From
n+1 n+2
14051K-003
Logic
Allocator
*MACH 2 only
Figure 2. Product Term Clusters and the Logic Allocator
Table 5. Logic Allocation for MACH111(SP)
Output Macrocell
Available Clusters
C , C
Output Macrocell
Available Clusters
C C
M
M
8
0
0
1
8, 9
M
C , C , C
M
C C C
8, 9, 10
1
0
1
2
9
M
C , C , C
M
C C C
9, 10, 11
2
1
2
3
10
M
C , C , C
M
C C C
10, 11, 12
3
2
3
4
11
M
C , C , C
M
C C C
11, 12, 13
4
3
4
5
12
M
C , C , C
M
C C C
12, 13, 14
5
4
5
6
13
M
C , C , C
M
C C C
13, 14, 15
6
5
6
7
14
M
C , C
M
C C
14, 15
7
6
7
15
Table 6. Logic Allocation for MACH131(SP)
Output Macrocell
Available Clusters
C , C
Output Macrocell
Available Clusters
M
M
C , C , C
7 8 9
0
0
1
8
M
C , C , C
M
C , C , C
8 9 10
1
0
1
2
9
M
C , C , C
M
C , C , C
9 10 11
2
1
2
3
10
M
C , C , C
M
C , C , C
10 11 12
3
2
3
4
11
M
C , C , C
M
C , C , C
11 12 13
4
3
4
5
12
M
C , C , C
M
C , C , C
12 13 14
5
4
5
6
13
M
C , C , C
M
C , C , C
13 14 15
6
5
6
7
14
M
C , C , C
M
C , C
14 15
7
6
7
8
15
6
MACH 1 & 2 Families
Table 7. Logic Allocation for MACH211(SP) and MACH231(SP)
Macrocell
Output Buried
Macrocell
Available Clusters
C , C , C
Output
Buried
Available Clusters
C , C , C , C
M
M
8
0
0
1
2
7
8
9
10
M
C , C , C , C
M
C , C , C , C
8 9 10 11
1
0
1
2
3
9
M
C , C , C , C
M
C , C , C , C
9 10 11 12
2
1
2
3
4
10
M
C , C , C , C
M
C , C , C , C
10 11 12 13
3
2
3
4
5
11
M
C , C , C , C
M
C , C , C , C
11 12 13 14
4
3
4
5
6
12
M
C , C , C , C
M
C , C , C , C
12 13 14 15
5
4
5
6
7
13
M
C , C , C , C
M
C , C , C
13 14 15
6
5
6
7
8
14
M
C , C , C , C
M
C , C
7
6
7
8
9
15
14 15
Table 8. Logic Allocation for MACH221(SP)
Macrocell
Output Buried
Macrocell
Available Clusters
C , C , C
Output
Buried
Available Clusters
M
M
C , C , C , C
5 6 7 8
0
0
1
2
6
M
C , C , C , C
M
C , C , C , C
6 7 8 9
1
0
1
2
3
7
M
C , C , C , C
M
C , C , C , C
7 8 9 10
2
1
2
3
4
8
M
C , C , C , C
M
C , C , C , C
8 9 10 11
3
2
3
4
5
9
M
C , C , C , C
M
C , C , C
9 10 11
4
3
4
5
6
10
M
C , C , C , C
M
C , C
10 11
5
4
5
6
7
11
Macrocell
There are two fundamental types of macrocell: the output macrocell and the buried macrocell. The
buried macrocell is only found in MACH 2 devices. The use of buried macrocells effectively
doubles the number of macrocells available without increasing the pin count.
Both macrocell types can generate registered or combinatorial outputs. For the MACH 2 series,
a transparent-low latch configuration is provided. If the register is used, it can be configured as
a T-type or a D-type flip-flop. Register and latch functionality is defined in Table 9.
Programmable polarity (for output macrocells) and the T-type flip-flop both give the software a
way to minimize the number of product terms needed. These choices can be made automatically
by the software when it fits the design into the device.
Table 9. Register/Latch Operation
Configuration
D/T
X
0
CLK/LE
Q+
Q
0
0,1,↓
D-Register
↑
1
↑
1
X
0
0,1,↓
Q
Q
Q
Q
0
T-Register
Latch
↑
↑
1
0
0
1
X
0
1
1
MACH 1 & 2 Families
7
The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback,
and to the I/O cell. The feedback is always available regardless of the configuration of the I/O cell.
This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as
inputs if not needed as outputs. The basic output macrocell configurations are shown in Figure 4.
The buried macrocell (Figure 5) does not send its output to an I/O cell. The output of a buried
macrocell is provided only as an internal feedback signal which feeds the switch matrix. This
allows the designer to generate additional logic without requiring additional pins. The buried
macrocell can also be used to register or latch inputs. The input register is a D-type flip-flop; the
input latch is a transparent-low D-type latch. Once configured as a registered or latched input, the
buried macrocell cannot generate logic from the product-term array. The basic buried macrocell
configurations are shown in Figure 6.
PAL-Block
Asynchronous
Preset
1
1
0
AP
Sum of Products
from Logic
To I/O
Cell
1
0
D/T/L Q
Allocator
CLK
0
AR
CLK
n
PAL-Block
Asynchronous
Reset
To
Switch
Matrix
14051K-004
Note:
1. Latch option available on MACH 2 devices only.
Figure 3. Output Macrocell
8
MACH 1 & 2 Families
To
I/O
Cell
From
Logic
Allocator
n
To
I/O
Cell
From
Logic
Allocator
n
To Switch
Matrix
To Switch
Matrix
b. Combinatorial, active low
a. Combinatorial, active high
From
Logic
Allocator
From
Logic
Allocator
To
I/O
Cell
To
I/O
Cell
n
n
AP
AR
AP
D
Q
D
Q
CLK
0
CLK
0
AR
CLK
n
CLK
n
To Switch
Matrix
To Switch
Matrix
c. D-type register, active high
d. D-type register, active low
From
Logic
Allocator
From
Logic
Allocator
To
I/O
Cell
To
I/O
Cell
n
n
AP
AR
AP
Q
T
Q
T
CLK
0
CLK
0
AR
CLK
n
CLK
n
To Switch
Matrix
To Switch
Matrix
f. T-type register, active low
e. T-type register, active high
From
Logic
Allocator
From
Logic
Allocator
To
I/O
Cell
n
AP
n
AP
To
I/O
Cell
L
Q
L
Q
CLK
0
CLK
0
G
G
AR
AR
CLK
n
CLK
n
To Switch
Matrix
To Switch
Matrix
h. Latch, active low (MACH 2 only)
g. Latch, active high (MACH 2 only)
14051K-005
Figure 4. Output Macrocell Configurations
MACH 1 & 2 Families
9
From I/O Pin
PAL-Block
Asynchronous
Preset
1
0
AP
D/T/L
1
0
Sum of Products
From Logic
IC Allocator
CLK
Q
0
CLK
AR
n
PAL-Block
Asynchronous
Reset
To
Switch
Matrix
14051K-030
Figure 5. Buried Macrocell (MACH 2 only)
From Logic
Allocator
From
Logic
Allocator
n
AP
AR
n
D
Q
CLKÂ
0
CLÂK
n
To Switch
Matrix
To Switch
Matrix
a. Combinatorial
b. D-type register
From I/O
Cell
n
From Logic
Allocator
AP
AR
T
Q
AP
AR
CLK
0
D
Q
CLK
n
CLK
0
CLK
n
To Switch
Matrix
To Switch
Matrix
c. T-type register
d. Input register
From I/O
Cell
From
Logic
Allocator
n
AP
AR
L
Q
AP
L
CLK
Q
0
G
CLK
n
CLK
0
G
CLK
n
AR
To Switch
Matrix
To Switch
Matrix
e. Latch
f. Input latch
14051K-006
Figure 6. Buried Macrocell Configurations (MACH 2 only)
MACH 1 & 2 Families
10
The flip-flops in either macrocell type can be clocked by one of several clock pins (Table 10).
Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate
input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal
acts as both clock and input to the same device.
Table 10. Macrocell Clocks
Device
Number of Clocks Available
Device
MACH211SP
Number of Clocks Available
MACH111
4
2
4
4
4
2
4
4
4
4
MACH111SP
MACH131
MACH221
MACH221SP
MACH231
MACH131SP
MACH211
MACH231SP
All flip-flops have asynchronous reset and preset. This is controlled by the common product terms
that control all flip-flops within a PAL block. For a single PAL block, all flip-flops, whether in an
output or a buried macrocell, are initialized together. The initialization functionality of the flip-flops
is illustrated in Table 11.
Table 11. Asynchronous Reset/Preset Operation
Configuration
AR
0
AP
0
CLK/LE
Q+
X
X
X
X
X
0
See Table 9
0
1
1
Register
1
0
0
1
1
0
See Table 9
Illegal
1
0
0
0
1
0
1
1
Latch
1
0
0
Illegal
0
1
0
1
1
1
0
Illegal
0
1
1
1
I/O Cells
The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left
permanently enabled for use only as an output, permanently disabled for use as an input, or it can
be controlled by one of two product terms for bi-directional signals and bus connections. The two
product terms provided are common to a bank of I/O cells.
MACH 1 & 2 Families
11
0 1
1 1
Output Enable
Product Terms
(Common to bank of
I/O Cells)
1 0
0 0
V
CC
From Output
Macrocell
To Switch
Matrix
To Buried
Macrocell
(MACH 2 only)
14051K-007
Figure 7. I/O Cell
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, and even more importantly, guaranteed fixed speed. The design of the switch
matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required
by the design. Other non-Lattice/Vantis CPLDs incur serious timing delays as product terms expand
beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to
give designers easy access to the performance required in today’s designs.
MACH 1 & 2 SpeedLocking
Non-MACH
• Variable
• Patented Architecture
• Path Dependent
• Path Independent
• Logic/Routing Dependent Delays
• Unpredictable
• 4-5 Product Terms before Delays
• Logic/Routing Independent
• Guaranteed Fixed Timing
• Up to 16 Product Terms per Output
SpeedLocking
Shared Expander Delay
10.4 ns
Non-MACH
11
10
9
8.8 ns
t
(ns)
PD
8
7
6
5
Parallel Expander Delay
7.4 ns
6.6 ns
5.8 ns
5 ns
MACH 1 & 2
5 PT
10 PT
15 PT
14051K-001
Product Terms
Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices
12
MACH 1 & 2 Families
JTAG IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of significant benefits including: rapid
prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.
All MACHxxxSP devices provide in-system programming (ISP) capability through their JTAG ports.
This capability has been implemented in a manner that insures that the JTAG port remains
compliant to the IEEE 1149.1 standard. By using JTAG as the communication interface through
which ISP is achieved, customers benefit from a standard, well-defined interface.
MACHxxxSP devices can be programmed across the commercial temperature and voltage range.
These devices tristate the outputs during programming. Lattice/Vantis provides its free PC-based
Lattice/VantisPRO software to facilitate in-system programming. Lattice/VantisPRO software takes
the JEDEC file output produced by Vantis’ design implementation software, along with information
about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. Lattice/
VantisPRO software can use these vectors to drive a JTAG chain via the parallel port of a PC.
Alternatively, Lattice/VantisPRO software can output files in formats understood by common
automated test equipment. This equipment can then be used to program MACHxxxSP devices
during the testing of a circuit board. For more information about in-system programming, refer to
the separate document entitled MACH ISP Manual.
BUS-FRIENDLY INPUTS AND I/Os
The MACH 1 & 2 inputs and I/Os include two inverters in series which loop back to the input.
This double inversion weakly holds the input at its last driven logic state. For the circuit diagram,
please refer to the Input/Output Equivalent Schematics (page 393) in the General Information
Section of the Vantis 1999 Data Book.
PCI COMPLIANT
The MACH 1 & 2 families in -5/-6/-7/-10/-12 speed grades are fully compliant with the PCI Local
Bus Specification published by the PCI Special Interest Group. The MACH 1 & 2 families’
predictable timing ensures compliance with the PCI AC specifications independent of the design.
POWER-DOWN MODE
The MACH 1 & 2 families feature a programmable low-power mode in which individual signal
paths can be programmed for low power. These low-power speed paths will be slower than the
non-low-power paths. This feature allows speed critical paths to run at maximum frequency while
the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If
all of the signals in a PAL block are in low-power mode, then the total power is reduced even
further.
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS
All MACHxxxSP and most of the MACH 1 & 2 devices are safe for mixed supply voltage system
designs. These 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V,
while they can accept inputs from other 3.3-V devices. The MACH 1 & 2 families provide easy-to-
use mixed-voltage design compatibility. For more information, refer to the Technical Note entitled
Mixed Supply Design with MACH 1 & 2 SP Devices.
POWER-UP RESET
All flip-flops power-up to a logic LOW for predictable system initialization. The actual values of
the outputs of the MACH devices will depend on the configuration of the macrocell. To guarantee
MACH 1 & 2 Families
13
initialization values, the V rise must be monotonic and the clock must be inactive until the reset
CC
delay time has elapsed.
SECURITY BIT
A security bit is provided on the MACH devices as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by
a device programmer, securing proprietary designs from competitors. Programming and
verification are also defeated by the security bit. The bit can only be reset by erasing the entire
device.
14
MACH 1 & 2 Families
MACH111(SP) AND MACH131(SP) PAL BLOCK
0
4
8
12
16
20
24
28
32
36
40
47
43
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
I/O
I/O
I/O
I/O
Cell
Output
Macro
Cell
M0
I/O
Cell
Output
Macro
Cell
M1
M2
I/O
Cell
Output
Macro
Cell
I/O
Cell
I/O
Output
Macro
Cell
M3
M4
0
I/O
Cell
I/O
I/O
I/O
C0
Output
Macro
Cell
C1
I/O
Cell
C2
Output
Macro
Cell
M5
M6
M7
M8
M9
C3
I/O
Cell
C4
Output
Macro
Cell
C5
I/O
Cell
I/O
I/O
I/O
C6
Output
Macro
Cell
Switch
Matrix
C7
I/O
Cell
C8
Output
Macro
Cell
C9
I/O
Cell
C10
C11
C12
C13
C14
C15
Output
Macro
Cell
I/O
Cell
I/O
I/O
I/O
I/O
I/O
I/O
Output
Macro
Cell
M10
I/O
Cell
Output
Macro
Cell
M11
M12
M13
63
I/O
Cell
Output
Macro
Cell
I/O
Cell
Output
Macro
Cell
I/O
Cell
Output
Macro
Cell
M14
M15
I/O
Cell
Output
Macro
Cell
for MACH111SP
2
for MACH111, MACH131, MACH131SP
Output Enable
4
Output Enable
0
4
8
16
12
16
16
20
24
28
32
36
40
43
47
51
14051K-013
MACH 1 & 2 Families
15
MACH211(SP) PAL BLOCK
0
4
8
12
16
20
24
28
32
36
40
47
43
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
I/O
Cell
I/O
Output
Macro
Cell
M0
Buried
Macro
Cell
M1
M2
I/O
Cell
I/O
Output
Macro
Cell
Buried
Macro
Cell
M3
M4
0
I/O
Cell
I/O
Output
Macro
Cell
C0
C1
Buried
Macro
Cell
C2
M5
M6
M7
M8
M9
C3
I/O
Cell
I/O
C4
Output
Macro
Cell
C5
C6
Buried
Macro
Cell
Switch
Matrix
C7
I/O
Cell
C8
I/O
Output
Macro
Cell
C9
C10
C11
C12
C13
C14
C15
Buried
Macro
Cell
I/O
I/O
I/O
I/O
Cell
Output
Macro
Cell
M10
Buried
Macro
Cell
M11
M12
M13
63
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
I/O
Cell
Output
Macro
Cell
M14
M15
Buried
Macro
Cell
for MACH211SP
for MACH211
2
4
0
4
8
16
12
8
16
20
24
28
32
36
40
43
47
51
14051K-015
16
MACH 1 & 2 Families
MACH221(SP) PAL BLOCK
0
4
8
12
16
20
24
28
32
36
40
47
43
51
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
I/O
Cell
I/O
Output
Macro
Cell
M0
Buried
Macro
Cell
M1
M2
I/O
Cell
I/O
Output
Macro
Cell
0
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
Buried
Macro
Cell
M3
M4
I/O
I/O
I/O
I/O
I/O
Cell
Output
Macro
Cell
Switch
Matrix
Buried
Macro
Cell
M5
M6
M7
M8
M9
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
I/O
Cell
Output
Macro
Cell
47
Buried
Macro
Cell
I/O
Cell
Output
Macro
Cell
M10
Buried
Macro
Cell
M11
47
51
0
4
8
12
16
20
24
28
32
36
40
43
4
12
6
14051K-016
MACH 1 & 2 Families
17
MACH231(SP) PAL BLOCK
51
55
59
63
0
4
8
12
16
20
24
28
32
36
40
47
43
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
I/O
Cell
I/O
Output
Macro
Cell
M0
Buried
Macro
Cell
M1
M2
I/O
Cell
I/O
Output
Macro
Cell
Buried
Macro
Cell
M3
M4
I/O
Cell
I/O
Output
Macro
Cell
Buried
Macro
Cell
M5
M6
M7
M8
M9
0
C0
I/O
Cell
I/O
Output
Macro
Cell
C1
C2
Buried
Macro
Cell
C3
Switch
Matrix
C4
I/O
Cell
I/O
C5
Output
Macro
Cell
C6
C7
Buried
Macro
Cell
C8
I/O
I/O
I/O
I/O
C9
Cell
Output
Macro
Cell
M10
C10
C11
C12
C13
C14
C15
Buried
Macro
Cell
M11
M12
M13
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
63
I/O
Cell
Output
Macro
Cell
M14
M15
Buried
Macro
Cell
4
0
4
8
16
12
8
16
20
24
28
32
36
40
43
47
51
55
59
63
14051K-017
18
MACH 1 & 2 Families
BLOCK DIAGRAM (MACH111, MACH111SP)
CLK /I
0
1
CLK /I
1
2
MACH111
CLK /I
2
4
CLK /I
Block A
3
5
CLK /I
0
0
I/O – I/O
MACH111SP
0
15
CLK /I
1
1
16
16
16
I/O Cells
4 MACH111
2 MACH111SP
16
4
Macrocells
OE
52 x 70
AND Logic Array
and
Logic Allocator
26
Switch Matrix
26
52 x 70
AND Logic Array
and
Logic Allocator
OE
Macrocells
4
16
16
16
2 MACH111 Only
I/O Cells
16
I/O – I/O
I
0
16
31
14051K-008
MACH111
I
3
Block B
MACH 1 & 2 Families
19
BLOCK DIAGRAM (MACH131, MACH131SP)
Block A
Block B
I
I
5
I/O – I/O
I/O – I/O
31
2,
0
15
16
16
16
16
16
I/O Cells
I/O Cells
4
16
16
4
4
4
Macrocells
Macrocells
OE
OE
52 x 70
AND Logic Array
and
52 x 70
AND Logic Array
and
2
Logic Allocator
Logic Allocator
26
26
26
Sw itch Matrix
26
52 x 70
AND Logic Array
and
52 x 70
AND Logic Array
and
4
Logic Allocator
Logic Allocator
OE
OE
4
4
Macrocells
Macrocells
4
16
16
16
16
4
16
16
I/O Cells
I/O Cells
I/O – I/O
I/O – I/O
47
CLK /I , CLK /I
1 1
48
63
32
0
0
CLK /I , CLK /I
2
3
3 4
Block D
Block C
14051K-009
20
MACH 1 & 2 Families
BLOCK DIAGRAM (MACH211, MACH211SP)
CLK /I
0
1
CLK /I
1
2
MACH211
CLK /I
2
4
CLK /I
3
5
Block A
Block B
CLK /I
0
0
MACH211SP
MACH211 only
CLK /I
1 1
I/O –I/O
I/O –I/O
8 15
0
7
8
8
8
I/O Cells
I/O Cells
8
2 MACH211SP
4 MACH211
8
8
8
8
Macrocells
Macrocells
Macrocells
Macrocells
2
2
OE
OE
52 x 68
AND Logic
Array
52 x 68
AND Logic
Amrray
and
and
26
26
Sw itch Matrix
26
26
52 x 68
52 x 68
AND Logic Array
and
AND Logic Array
and
Logic Allocator
Logic Allocator
OE
2
OE
2
Macrocells
Macrocells
Macrocells
Macrocells
8
8
8
8
8
8
8
8
2 MACH211 only
I/O Cells
I/O Cells
I/O –I/O
I/O –I/O
16 23
24
31
I
0
MACH211
I
3
Block D
Block C
14051K-010
MACH 1 & 2 Families
21
BLOCK DIAGRAM (MACH221, MACH221SP)
14051K-011
22
MACH 1 & 2 Families
BLOCK DIAGRAM (MACH231, MACH231SP)
14051K-012
MACH 1 & 2 Families
23
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
With Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (T )
A
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C
Device Junction Temperature . . . . . . . . . . . . . +150°C
Supply Voltage (V
)
CC
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Input Voltage . . . . . . . . . . . . -0.5 V to V +0.5 V
CC
Industrial (I) Devices
DC Output or I/O Pin Voltage . . -0.5 V to V +0.5 V
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Ambient Temperature (T )
A
Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C
Latchup Current (T = -40°C to +85°C). . . . . . . 200 mA
A
Supply Voltage (V
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
)
CC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability.
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC CHARACTERISTICS OVER OPERATING RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Description
= –3.2 mA, V = Min, V = V or V
IL
Min
Typ
Max
Unit
V
I
2.4
OH
CC
IN
IH
V
OH
I
= –300 µA, V = Max, V = V or V (Note 1)
3.5
0.5
V
OH
CC
IN
IH
IL
V
Output LOW Voltage
Input HIGH Voltage
I
= 16 mA, V = Min, V = V or V (Note 2)
V
OL
OL
CC
IN
IH
IL
Guaranteed Input Logical HIGH Voltage for all Inputs
(Note 3)
V
2.0
V
V
IH
Guaranteed Input Logical LOW Voltage for all Inputs
(Note 3)
V
Input LOW Voltage
0.8
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V = 5.25 V, V V = Max (Note 4)
10
–10
10
µA
µA
µA
µA
IH
IN
CC
I
V = 0 V, V = Max (Note 4)
IN CC
IL
I
Off-State Output Leakage Current HIGH V = 5.25 V, V = Max, V = V or V (Note 4)
OUT CC IN IH IL
OZH
I
Off-State Output Leakage Current LOW V = 0 V, V = Max, V = V or V (Note 4)
–10
OZL
OUT
CC
IN
IH
IL
–130 (Note 6),
–160
I
Output Short-Circuit Current
V
= 0.5 V V = Max (Note 5)
–30
mA
SC
OUT
CC
Notes:
1. This applies to MACH111SP, MACH131SP, and die code “B” or later for MACH211(SP) and MACH231(SP). This does not apply
to MACH111, MACH131, MACH221(SP), and die code “A” for MACH211(SP) and MACH231(SP).
2. Total I for one PAL block should not exceed 64 mA.
OL
3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included.
4. I/O pin leakage is the worst case of I and I
IL OZL
(or I and I ).
IH OZH
5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
V
OUT
6. For commercial temperature range only.
24
MACH 1 & 2 Families
MACH111 AND MACH111SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES1
-5
-7
-10
-12
-14
-15
-18
Parameter
Symbol
Parameter Description
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
t
Input, I/O, or Feedback to Combinatorial Output
5
7.5
10
12
14
10
15
10
18 ns
PD
D-type
T-type
3.5
4
5.5
6.5
0
6.5
7.5
0
7
8
0
8.5
10
0
10
11
0
12
13.5
0
ns
Setup Time from Input, I/O, or Feedback
to Clock
t
S
ns
ns
t
Register Data Hold Time
Clock to Output
0
H
t
3.5
5
6
8
12 ns
ns
CO
t
LOW
HIGH
2.5
2.5
3
5
5
6
6
6
6
7.5
7.5
42
WL
Clock Width
t
3
6
6
ns
WH
D-type 143
T-type 133
D-type 182
95
80
74
100
91
100
66.7
62.5
76.9
71.4
83.3
54
50
69
57
83.3
50
MHz
External
Feedback
1/(t + t )
S
CO
87
47.6
66.6
55.5
83.3
39
MHz
MHz
MHz
MHz
Maximum
Frequency
f
133
125
167
53
MAX
Internal Feedback (f
)
CNT
T-type
167
200
44
No Feedback 1/(t + t
)
66.7
WL WH
t
Asynchronous Reset to Registered Output
Asynchronous Reset Width (Note 2)
7.5
7.5
9.5
9.5
11
11
16
16
19.5
19.5
20
20
24 ns
AR
t
4.5
4.5
5
5
7.5
7.5
12
8
14.5
10
15
10
18
12
ns
ns
ARW
t
Asynchronous Reset Recovery Time (Note 2)
Asynchronous Preset to Registered Output
Asynchronous Preset Width (Note 2)
ARR
t
24 ns
ns
AP
t
4.5
4.5
5
5
7.5
7.5
12
8
14.5
10
15
10
18
12
APW
t
Asynchronous Preset Recovery Time (Note 2)
Input, I/O, or Feedback to Output Enable
Input, I/O, or Feedback to Output Disable
ns
APR
t
7.5
7.5
10
7
9.5
9.5
10
7
10
10
10
7
12
12
10
7
14.5
14.5
10
7
15
15
10
7
18 ns
18 ns
10 ns
EA
t
ER
t
t Increase for Powered-down Macrocell (Note 3)
PD
LP
t
t Increase for Powered-down Macrocell (Note 3)
7
3
ns
ns
LPS
S
t
t
Increase for Powered-down Macrocell (Note 3)
Increase for Powered-down Macrocell (Note 3)
EA
3
3
3
3
3
3
LPCO
CO
t
t
10
10
10
10
10
10
10 ns
LPEA
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
MACH 1 & 2 Families
25
MACH131 AND MACH131SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES1
-5
-7
-10
-12
-14
-15
-18
Parameter
Symbol
Parameter Description
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
t
Input, I/O, or Feedback to Combinatorial Output
5.5
7.5
10
12
14
10
15
10
18 ns
PD
D-type
Setup Time from Input, I/O, or Feedback
T-type
3.0
3.5
0
5.5
6.5
0
6.5
7.5
0
7
8
0
8.5
10
0
10
11
0
12
13.5
0
ns
t
S
ns
ns
t
Hold Time
H
t
Clock to Output
4
5
6
8
12 ns
ns
CO
t
LOW
2.5
2.5
3
3
4
4
6
6
6
7.5
7.5
42
39
53
44
WL
Clock Width
HIGH
t
6
6
6
ns
WH
D-type
143
133
182
167
95
87
133
125
80
74
100
91
66.7
62.5
76.9
71.4
54
50
69
57
50
MHz
External
Feedback
1/(t + t )
S
CO
T-type
D-type
T-type
47.6
66.6
55.5
MHz
MHz
MHz
Maximum
Frequency
f
MAX
Internal Feedback (f
)
CNT
No
Feedback
1/(t + t
)
200
167
125
83.3
83.3
83.3
66.7
MHz
WL WH
t
Asynchronous Reset to Registered Output
Asynchronous Reset Width (Note 2)
8.5
8.5
9.5
9.5
11
11
16
16
19.5
19.5
20
20
24 ns
AR
t
4.5
4.5
5
5
7.5
7.5
12
8
14.5
10
15
10
18
12
ns
ns
ARW
t
Asynchronous Reset Recovery Time (Note 2)
Asynchronous Preset to Registered Output
Asynchronous Preset Width (Note 2)
ARR
t
24 ns
ns
AP
t
4.5
4.5
5
5
7.5
7.5
12
8
14.5
10
15
10
18
12
APW
t
Asynchronous Preset Recovery Time (Note 2)
Input, I/O, or Feedback to Output Enable
Input, I/O, or Feedback to Output Disable
ns
APR
t
7.5
7.5
10
7
9.5
9.5
10
7
10
10
10
7
12
12
10
7
14.5
14.5
10
7
15
15
10
7
18 ns
18 ns
10 ns
EA
t
ER
t
t Increase for Powered-Down Macrocell (Note 3)
PD
LP
t
t Increase for Powered-Down Macrocell (Note 3)
7
3
ns
ns
LPS
S
t
t
Increase for Powered-Down Macrocell (Note 3)
Increase for Powered-Down Macrocell (Note 3)
EA
3
3
3
3
3
3
LPCO
CO
t
t
10
10
10
10
10
10
10 ns
LPEA
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book..
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
3. If a signal is powered down, this parameter must be added to its respective high-speed parameter.
26
MACH 1 & 2 Families
MACH211 AND MACH211SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
1
-6
-7
-10
-12
-14
-15
-18
Parameter
Symbol
Parameter Description
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input, I/O, or Feedback to Combinatorial
Output
6
7.5
10
12
14
10
15
10
18
12
ns
t
PD
D-type
T-type
5
5.5
0
5.5
6.5
0
6.5
7.5
0
7
8
0
8.5
10
0
10
11
0
12
13.5
0
ns
ns
Setup Time from Input, I/O, or Feedback
to Clock
t
S
Register Data Hold Time
Clock to Output
ns
t
H
4
4.5
6
8
ns
t
CO
LOW
HIGH
2.5
2.5
3
5
5
6
6
6
6
6
7.5
7.5
42
ns
t
WL
Clock Width
3
6
ns
t
WH
D-type 111
T-type 105
D-type 166
T-type 150
200
100
91
80
74
100
91
100
6.5
0
66.7
62.5
83.3
76.9
83.3
7
54
50
69
62.5
83.3
8.5
0
50
MHz
MHz
MHz
MHz
MHz
ns
External
Feedback
1/(t + t
)
S
CO
47.6
66.6
62.5
83.3
10
39
Maximum
Frequency
133
125
167
5.5
0
55.6
51.3
66.7
12
f
MAX
Internal Feedback (f
)
CNT
No Feedback 1/(t + t
)
WL WH
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
5
0
t
SL
0
0
0
ns
t
HL
7
7
13
Gate to Output
7
9
10
14
11
17
11
17
ns
ns
ns
t
(note 6)
13.5
7.5
(note 4)
8
GO
(note 5)
Gate Width LOW
2.5
3
5
6
6
6
7.5
t
GWL
20
(note 6)
20.5
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
9.5
11
12
13
t
PDL
Input Register Setup Time
Input Register Hold Time
1.5
1.5
2
2
2
2
2
2
2
2
2.5
3.5
ns
ns
t
SIR
2.5
2.5
t
HIR
20
(note 6)
22
Input Register Clock to Combinatorial Output
10
15
18
18
ns
t
ICO
D-type
T-type
LOW
8
9
9
10
3
10
11
5
12
13
6
14.5
16
6
15
16
6
18
19.5
7.5
ns
ns
ns
ns
Input Register Clock to Output Register
Setup
t
ICS
2.5
2.5
t
WICL
Input Register
Clock Width
HIGH
3
5
6
6
6
7.5
t
WICH
Maximum Input Register
Frequency
1/(t
+ t
)
200
167
100
83.3
83.3
83.3
66.7
MHz
f
WICL WICH
MAXIR
Input Latch Setup Time
Input Latch Hold Time
1.5
1.5
2
2
2
2
2
2
2
2
2.5
3.5
ns
ns
ns
t
SIL
2.5
2.5
t
HIL
Input Latch Gate to Combinatorial Output
12
13
12
14
14
16
17
19
20
22
20
22
24
t
IGO
Input Latch Gate to Output Through Transparent
Output Latch
26.5
ns
ns
t
IGOL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7
7.5
8.5
9
11
12
14.5
t
SLL
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
9
10
3
11
5
13
6
16
6
16
6
19.5
7.5
ns
ns
t
IGS
2.5
t
WIGL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
12
12.5
14
16
19
19
23
ns
t
PDLL
MACH 1 & 2 Families
27
MACH211 AND MACH211SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
1
-6
-7
-10
-12
-14
-15
-18
Parameter
Symbol
Parameter Description
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Asynchronous Reset to Registered or Latched
Output
9
9
9.5
9.5
15
15
16
16
19.5
19.5
20
20
24
24
ns
t
AR
Asynchronous Reset Width (Note 2)
4
4
5
5
10
10
12
10
14.5
10
15
10
18
12
ns
ns
t
ARW
Asynchronous Reset Recovery Time (Note 2)
t
ARR
Asynchronous Preset to Registered or Latched
Output
ns
t
AP
Asynchronous Preset Width (Note 2)
4
4
5
5
10
10
12
10
14.5
10
15
10
18
12
ns
ns
ns
ns
ns
ns
ns
ns
t
APW
Asynchronous Preset Recovery Time (Note 2)
Input, I/O, or Feedback to Output Enable
Input, I/O, or Feedback to Output Disable
t
APR
9
9
9.5
9.5
10
10
0
10
10
10
10
0
12
12
10
10
0
14
14
10
10
0
15
15
10
10
0
18
18
10
10
0
t
EA
t
ER
t
Increase for Powered-down Macrocell (Note 3)
10
10
0
t
PD
LP
t Increase for Powered-down Macrocell (Note 3)
t
S
LPS
t
Increase for Powered-down Macrocell (Note 3)
Increase for Powered-down Macrocell (Note 3)
t
CO
LPCO
t
10
10
10
10
10
10
10
t
EA
LPEA
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
4. MACH211 t = 7 ns. MACH211SP t = 7.5 ns.
GO
GO
5. MACH211, commercial t = 7 ns.
GO
6. The faster -18 t , t , t , apply to MACH211 only, not MACH211SP.
GO PDL ICO
28
MACH 1 & 2 Families
MACH221 and MACH221SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
1
-7
-10
-12
-14
-15
-18
Parameter
Symbol
Parameter Description
Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input, I/O, or Feedback to Combinatorial Output
7.5
10
12
14
15
10
18
12
ns
ns
t
PD
D-type
5.5
6.5
0
6.5
7.5
0
7
8
0
8.5
10
0
10
11
0
12
13.5
0
Setup Time from Input, I/O, or Feedback to
Clock
t
s
T-type
ns
Register Data Hold Time
Clock to Output
ns
t
H
5
6
8
10
ns
t
CO
LOW
3
3
5
5
6
6
6
6
6
7.5
7.5
42
ns
t
WL
Clock Width
HIGH
D-type
T-type
D-type
T-type
6
ns
t
WH
95
87
133
125
167
5.5
0
80
74
100
91
100
6.5
0
66.7
62.5
83.3
76.9
83.3
7
54
50
69
62.5
83.3
8.5
0
50
MHz
MHz
MHz
MHz
MHz
ns
External
Feedback
1/(t + t
)
S
CO
47.6
66.6
62.5
83.3
10
39
Maximum
Frequency
55.6
51.3
66.7
12
f
MAX
Internal Feedback (f
)
CNT
No Feedback 1/(t + t
)
WL WH
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
t
SL
0
0
0
ns
t
HL
7
Gate to Output
7
10
14
11
17
11
17
13.5
20.5
ns
ns
ns
t
GO
(note 2)
Gate Width LOW
3
5
6
6
6
7.5
t
GWL
Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch
9.5
12
13
t
PDL
Input Register Setup Time
2
2
2
2
2
2
2
2
2.5
3.5
ns
ns
ns
ns
ns
ns
ns
t
SIR
Input Register Hold Time
2.5
2.5
t
HIR
Input Register Clock to Combinatorial Output
11
15
18
18
22
t
ICO
D-type
Input Register Clock to Output Register Setup
T-type
9
10
3
10
11
5
12
13
6
14.5
16
6
15
16
6
18
19.5
7.5
t
ICS
Input Register
Clock Width
LOW
HIGH
t
WICL
3
5
6
6
6
7.5
t
WICH
Maximum Input Register
Frequency
1/(t
+ t
)
167
100
83.3
83.3
83.3
66.7
MHz
f
WICL WICH
MAXIR
Input Latch Setup Time
Input Latch Hold Time
2
2
2
2
2
2
2
2
2.5
3.5
ns
ns
ns
t
SIL
2.5
2.5
t
HIL
Input Latch Gate to Combinatorial Output
12
14
14
16
17
19
20
22
20
22
24
t
IGO
Input Latch Gate to Output Through Transparent Output
Latch
26.5
ns
ns
t
IGOL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7.5
8.5
9
11
12
14.5
t
SLL
Input Latch Gate to Output Latch Setup
Input Latch Gate Width LOW
10
3
11
5
13
6
16
6
16
6
19.5
7.5
ns
ns
t
IGS
t
WIGL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
11.5
9.5
14
15
16
16
19
19
20
23
24
ns
t
PDLL
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 3)
19.5
ns
ns
ns
ns
t
AR
5
5
10
8
12
10
14.5
10
15
10
18
12
t
ARW
Asynchronous Reset Recovery Time (Note 3)
Asynchronous Preset to Registered or Latched Output
t
ARR
9.5
15
16
19.5
20
24
t
AP
MACH 1 & 2 Families
29
MACH221 and MACH221SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
1
-7
-10
-12
-14
-15
-18
Parameter
Symbol
Parameter Description
Asynchronous Preset Width (Note 3)
Min Max Min Max Min Max Min Max Min Max Min Max Unit
5
5
10
8
12
10
14.5
10
15
10
18
12
ns
ns
ns
ns
ns
ns
ns
ns
t
APW
Asynchronous Preset Recovery Time (Note 3)
Input, I/O, or Feedback to Output Enable
Input, I/O, or Feedback to Output Disable
t
APR
9.5
9.5
10
10
0
12
12
10
10
0
12
12
10
10
0
14
14
10
10
0
15
15
10
10
0
18
18
10
10
0
t
EA
t
ER
t
Increase for Powered-down Macrocell (Note 4)
t
PD
LP
t Increase for Powered-down Macrocell (Note 4)
t
S
LPS
t
Increase for Powered-down Macrocell (Note 4)
Increase for Powered-down Macrocell (Note 4)
t
CO
LPCO
t
10
10
10
10
10
10
t
EA
LPEA
Notes:
1. See “Switching Test Circuits” in the General Information section of the Vantis 1999 Data Book.
2. MACH221 t = 7 ns. MACH221SP t = 8 ns.
GO
GO
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
4. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
30
MACH 1 & 2 Families
MACH231 AND MACH231SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
1
-6
-7
-10
-12
-14
-15
-18
Parameter
Symbol
Parameter Description
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Input, I/O, or Feedback to Combinatorial Output
6
7.5
10
12
14
10
15
10
18
12
ns
ns
t
PD
D-type
5
6
0
5.5
6.5
0
6.5
7.5
0
7
8
0
8.5
10
0
10
11
0
12
13.5
0
Setup Time from Input, I/O, or Feedback
t
S
to Clock
T-type
ns
Register Data Hold Time
Clock to Output
ns
t
H
4
5
6.5
8
ns
t
CO
LOW
2.5
2.5
3
3
4
4
6
6
6
6
7.5
7.5
42
ns
t
WL
Clock Width
HIGH
6
6
ns
t
WH
D-type
111
100
166
150
95
87
133
125
77
72
100
91
66.7
62.5
83.3
76.9
54
50
69
62.5
50
MHz
MHz
MHz
MHz
External
Feedback
1/(t + t
)
S
CO
T-type
D-type
T-type
47.6
66.6
62.5
39
Maximum
Frequency
55.6
51.3
f
MAX
Internal Feedback (f
)
CNT
No
Feedback
1/(t + t
)
200
167
125
83.3
83.3
83.3
66.7
MHz
WL WH
Setup Time from Input, I/O, or Feedback to Gate
Latch Data Hold Time
5
0
5.5
0
6.5
0
7
0
8.5
0
10
0
12
0
ns
ns
t
SL
t
HL
Gate to Output
5
9
6
7.5
14
8.5
11
17
11
17
13.5 ns
ns
t
GO
Gate Width LOW
2
3
4
6
6
6
7.5
t
GWL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
9.5
14.5
20.5 ns
t
PDL
Input Register Setup Time
1.5
1.5
2
2
2
2
2
2
2.5
3.5
ns
ns
t
SIR
Input Register Hold Time
2.5
2.5
2.5
2.5
t
HIR
Input Register Clock to Combinatorial Output
10
11
15.5
16
18
18
22
ns
ns
t
ICO
D-type
8
9
10
3
11
12
4
12
13
6
14.5
16
6
15
16
6
18
19.5
7.5
Input Register Clock to output Register
t
ICS
Setup
T-type
9
ns
LOW
2.5
2.5
200
1.5
1.5
ns
t
WICL
Input Register
Clock Width
HIGH
3
4
6
6
6
7.5
ns
t
WICH
Maximum Input Register Frequency
Input Latch Setup Time
167
2
125
2
83.3
2.5
3
83.3
2.5
3
83.3
2.5
3
66.7
2.5
MHz
ns
f
MAXIR
t
SIL
Input Latch Hold Time
2
2.5
3.5
ns
t
HIL
Input Latch Gate to Combinatorial Output
11
13
12
14
17
18
17
20
22
20
22
24
ns
t
IGO
Input Latch Gate to Output Through Transparent
Output Latch
19.5
26.5 ns
t
IGOL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
7
9
7.5
10
10
11
10.5
13.5
11
16
12
16
14.5
19.5
ns
ns
t
SLL
Input Latch Gate to Output Latch Setup
t
IGS
MACH 1 & 2 Families
31
MACH231 AND MACH231SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES
1
-6
-7
-10
-12
-14
-15
-18
Parameter
Symbol
Parameter Description
Input Latch Gate Width LOW
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
2
3
4
6
6
6
7.5
ns
ns
t
WIGL
Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches
11
9
12.5
9.5
16
13
17
16
19
19
20
23
24
t
PDLL
Asynchronous Reset to Registered or Latched
Output
19.5
ns
ns
ns
t
AR
Asynchronous Reset Width (Note 2)
4
4
5
5
10
12
8
14.5
10
15
10
18
12
t
ARW
Asynchronous Reset Recovery Time
(Note 2)
7.5
t
ARR
Asynchronous Preset to Registered or Latched
Output
9
9.5
13
16
19.5
20
24
ns
t
AP
Asynchronous Preset Width (Note 2)
4
4
5
5
10
12
8
14.5
10
15
10
18
12
ns
ns
ns
ns
ns
ns
ns
ns
t
APW
Asynchronous Preset Recovery Time (Note 2)
Input, I/O, or Feedback to Output Enable
Input, I/O, or Feedback to Output Disable
7.5
t
APR
9
9
9
6
0
9
9.5
9.5
10
7
10
10
10
7
12
12
10
7
15
15
10
7
15
15
10
7
18
18
10
7
t
EA
t
ER
t
Increase for Powered-down Macrocell (Note 3)
t
PD
LP
t Increase for Powered-down Macrocell (Note 3)
t
S
LPS
t
Increase for Powered-down Macrocell (Note 3)
Increase for Powered-down Macrocell (Note 3)
0
0
0
0
0
0
t
CO
LPCO
t
10
10
10
10
10
10
t
EA
LPEA
Notes:
1. See “Switching Test Circuit” in the General Information section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
CAPACITANCE 1
Parameter Symbol
Parameter Description
Test Conditions
V = 2.0V V = 5.0V,
Typ
Unit
C
Input Capacitance
6
pF
IN
IN
CC
T = 25°C
f = 1 MHz
A
C
Output Capacitance
V
= 2.0V
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
these parameters may be affected.
32
MACH 1 & 2 Families
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system frequency.
The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and
exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type
register.
T = 25°C, V =5V
A
CC
MACH111(SP)
MACH131(SP)
250
225
200
175
150
125
100
75
150
125
100
75
High Speed
Low Power
High Speed
Low Power
50
50
25
25
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Frequency (MHz)
0
10
20
30
40
50
60
70
80
90
Frequency (MHz)
MACH211(SP)
MACH 221(SP)
275
250
225
200
175
150
125
100
75
High Speed
150
125
100
75
High Speed
Low Power
Low Power
50
50
25
25
0
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Frequency (MHz)
0
10
20
30
40
50
60
70
80
90
Frequency (MHz)
400
350
300
250
200
150
100
50
MACH231
MACH231SP
400
350
300
250
200
150
High Speed
High Speed
Low Power
Low Power
100
0
0
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
Frequency (MHz)
Frequency (MHz)
MACH 1 & 2 Families
33
Table 12. I
CC
Parameter
Device
Parameter Symbol
Description
Test Description
Typ
Unit
MACH111(SP)
MACH211(SP)
40
V = 5V,
CC
MACH221(SP)
MACH131(SP)
MACH231SP
MACH231
70
75
Supply Current (Static)
Supply Current (Active)
T = 25°C,
A
f = 0 MHz
80
135
I
mA
CC
MACH111(SP)
MACH211(SP)
45
V = 5V,
CC
MACH221(SP)
MACH131(SP)
MACH231SP
MACH231
75
80
T = 25°C,
A
f = 1 MHz
100
150
34
MACH 1 & 2 Families
44- PIN PLCC CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND
MACH111SP-5/7/10/12/15)
Top View
44-Pin PLCC
40
1 44 43 42 41
6
5
4
3
2
I/O27
39
7
8
I/O5
38
I/O26
I/O6
I/O25
37
36
35
34
I/O7
(TDI) I0
9
I/O24
10
11
12
CLK3/I5 (TDO)
GND
(CLK 0/I0) CLK0/I1
GND
Block B
Block A
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
33
32
31
30
29
(TCK) CLK1/I2
I/O8
13
14
15
16
17
I/O9
I/O22
I/O10
I/O21
I/O11
28
18 19 20 21 22 23 24 25 26 27
14051K-018
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
Note:
1. Pin designators in parentheses ( ) apply to the MACH111SP
MACH 1 & 2 Families
35
44-PIN TQFP CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND
MACH111SP-5/7/10/12/15)
Top View
44-Pin TQFP
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
I/O5
I/O6
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
I/O7
(TDI) I0
(CLK 0/I0) CLK0/I1
GND
Block B
Block A
(TCK) CLK1/I2
I/O8
9
10
11
I/O9
I/O10
I/O11
I/O22
I/O21
14051K-019
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
Note:
1. Pin designators in parentheses ( ) apply to the MACH111SP
36
MACH 1 & 2 Families
84-PIN PLCC CONNECTION DIAGRAM (MACH131-5/7/10/12/15)
Top View
84-Pin PLCC
Block D
Block A
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12
74 GND
73 I/O55
72 I/O54
71 I/O53
70 I/O52
I/O8
I/O9
13
14
15
16
17
18
19
20
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
69
68
I/O51
I/O50
67 I/O49
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O48
CLK3/I4
GND
CLK0/I0
VCC 21
GND
22
CLK1/I1
23
24
VCC
I/O16
CLK2/I3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I/O17 25
26
I/O19 27
I/O20 28
I/O18
29
30
I/O21
I/O22
I/O23 31
GND
32
33 34 35 36 37 38 39 40 41 42 4344 45 46 47 48 49 50 51 52 53
Block C
Block B
14051K-020
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
= Input
I/O
= Input/Output
= Supply Voltage
V
CC
MACH 1 & 2 Families
37
100-PIN PQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15)
Top View
100-Pin PQFP
Block A
Block D
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
GND
GND
TDO
N/C
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND
VCC
GND
GND
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
9
10
11
12
13
14
15
16
17
18
19
20
IO/CLK0
VCC
VCC
GND
GND
VCC
I3/CLK2
I/O47
I1/CLK1
I/O16
I/O17
I/O46
21
22
23
24
25
26
27
28
29
30
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
N/C
TCK
GND
GND
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
GND
GND
60
59
58
57
56
55
54
53
52
51
14051K-021
Block B
Block C
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
38
MACH 1 & 2 Families
100-PIN TQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15)
Top View
100-Pin TQFP
Block A
Block D
TDI
I/5
I/O8
GND
TDO
NC
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O9
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I0/CLK0
VCC
GND
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TCK
TMS
14051K-022
Block B
Block C
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
MACH 1 & 2 Families
39
44-PIN PLCC CONNECTION DIAGRAM (MACH211-7/10/12/15 AND
MACH211SP-6/7/10/12/15)
Top View
44-Pin PLCC
Block A
Block D
40
1 44 43 42 41
6
5
4
3
2
I/O27
39
7
I/O5
I/O6
I/O7
38
I/O26
8
I/O25
37
36
35
34
9
I/O24
(TDI) I
10
11
12
0
CLK3/I5 (TDO)
GND
(CLK 0/I0) CLK0/I1
GND
(TCK) CLK1/I2
I/O8
CLK2/I4 (CLK 1/I1)
33
32
31
30
29
13
14
15
16
17
I
3 (TMS)
I/O23
I/O22
I/O21
I/O9
I/O10
I/O11
28
18 19 20 21 22 23 24 25 26 27
Block B
Block C
14051K-023
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
Note:
1. Pin designators in parentheses ( ) apply to the MACH211SP
40
MACH 1 & 2 Families
44-PIN TQFP CONNECTION DIAGRAM (MACH211-7/10/12/15 AND
MACH211SP-6/7/10/12/15)
Top View
44-Pin TQFP
Block A
Block D
1
2
3
4
5
6
7
8
9
33
I/O5
I/O6
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
32
31
30
29
28
27
26
25
24
23
I/O7
(TDI) I0
(CLK 0/I0) CLK0/I1
GND
(TCK) CLK1/I2
I/O8
I/O9
I/O10
I/O11
10
11
I/O22
I/O21
Block B
Block C
14051K-024
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
Note:
1. Pin designators in parentheses ( ) apply to the MACH211SP
MACH 1 & 2 Families
41
68-PIN PLCC CONNECTION DIAGRAM (MACH221-7/10/12/15)
Top View
68-Pin PLCC
Block H
Block A
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
10
I/O7
I/O8
I/O9
60
I/O41
I/O40
I/O39
I/O38
I/O37
I/O36
I7
GND
VCC
I6
CLK3/I5
CLK2/I4
I/O35
I/O34
I/O33
I/O32
I/O31
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O10
I/O11
CLK0/I0
CLK1/I1
I2
VCC
GND
I3
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Block D
Block E
14051K-025
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
= Input
I/O
= Input/Output
= Supply Voltage
V
CC
42
MACH 1 & 2 Families
100-PIN PQFP CONNECTION DIAGRAM (MACH221SP-7/10/12/15)
Top View
100-Pin PQFP
Block A
Block H
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
GND
GND
TDO
N/C
I6
I/O41
N/C
I/O40
I/O39
I/O38
I/O37
I/O36
I5/CLK3
GND
GND
VCC
GND
GND
TDI
I7
N/C
I/O6
N/C
I/O7
I/O8
I/O9
9
10
11
12
13
14
15
16
17
18
19
20
I/O10
I/O11
IO/CLK0
VCC
VCC
GND
GND
VCC
I4/CLK2
I/O35
I1/CLK1
I/O12
I/O13
I/O34
21
22
23
24
25
26
27
28
29
30
I/O14
I/O15
I/O16
N/C
I/O33
I/O32
I/O31
N/C
60
59
58
57
56
55
54
53
52
51
I/O17
I/O30
I2
N/C
TCK
GND
GND
N/C
I3
TMS
GND
GND
14051K-026
Block D
Block E
PIN DESIGNATIONS
I/CLK = Input or Clock
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
MACH 1 & 2 Families
43
84-PIN PLCC CONNECTION DIAGRAM (MACH231-6/7/10/12/15)
Top View
84-Pin PLCC
Block A
Block H
8
4 3
84 83
8180 78 7776 75
79
82
9
7 6 5
2 1
1110
12
74 GND
73 I/O55
I/O8
I/O9
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
72
71
70
I/O54
I/O53
I/O52
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
69 I/O51
68
67
66
I/O50
I/O49
I/O48
CLK /I
0 0
65 CLK /I
V
3 4
CC
64
63
62
61
60
GND
V
GND
CLK /I
CC
1 1
CLK /I
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
2 3
I/O47
I/O46
59 I/O45
58
I/O44
I/O43
I/O42
I/O41
I/O40
57
56
55
54
33
4142
4546 47
50 5152
48 49
53
3536
39 40
3738
43 44
34
14051K-027
Block D
Block E
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I
= Input
I/O
= Input/Output
= Supply Voltage
V
CC
44
MACH 1 & 2 Families
100-PIN PQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)
Top View
100-Pin PQFP
Block A
Block H
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
GND
GND
TDO
N/C
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND
VCC
GND
GND
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
9
10
11
12
13
14
15
16
17
18
19
20
IO/CLK0
VCC
VCC
GND
GND
VCC
I3/CLK2
I/O47
I1/CLK1
I/O16
I/O17
I/O46
21
22
23
24
25
26
27
28
29
30
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
N/C
TCK
GND
GND
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
GND
GND
60
59
58
57
56
55
54
53
52
51
14051K-028
Block D
Block E
PIN DESIGNATIONS
I/CLK = Input or Clock
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
MACH 1 & 2 Families
45
100-PIN TQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)
Top View
100-Pin TQFP
Block A
Block H
TDI
I5
I/O8
GND
TDO
NC
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O9
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I0/CLK0
VCC
GND
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TCK
TMS
14051K-029
Block D
Block E
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
TDI = Test Data In
TCK = Test Clock
I
= Input
TMS = Test Mode Select
TDO = Test Data Out
I/O
= Input/Output
= Supply Voltage
V
CC
46
MACH 1 & 2 Families
ORDERING INFORMATION
Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is
formed by a combination of:
MACH 131
SP
-5
Y
C
FAMILY TYPE
PROGRAMMING DESIGNATOR
MACH = Macro Array CMOS High-Density
Blank = Initial Algorithm
/1
= First Revision
MACROCELL DENSITY
OPERATING CONDITIONS
111 = 32 Macrocells, 32 I/Os
131 = 64 Macrocells, 64 I/Os
211 = 64 Macrocells, 32 I/Os
221 = 96 Macrocells, 48 I/Os
231 = 128 Macrocells, 64 I/Os
C
I
= Commercial (0°C to +70°C)
= Industrial (-40°C to +85°C)
PACKAGE TYPE
J
= Plastic Leaded Chip Carrier
(PLCC)
V
Y
= Thin Quad Flat Pack (TQFP)
= Plastic Quad Flat Pack (PQFP)
PRODUCT DESIGNATION
SP
= JTAG-compatible, In-system Programmable
SPEED
-5 = 5.0 or 5.5 ns t
PD
-6 = 6.0 ns t
-7 = 7.5 ns t
PD
PD
-10 = 10 ns t
-12 = 12 ns t
-14 = 14 ns t
-15 = 15 ns t
-18 = 18 ns t
PD
PD
PD
PD
PD
Valid Combinations – Commercial
Valid Combinations – Industrial
MACH111
MACH111SP
-5, -7, -10, -12, -15
-5, -7, -10, -12, -15
-5, -7, -10, -12, -15
-5, -7, -10, -12, -15
-7, -10, -12, -15
-6, -7, -10, -12, -15
-7, -10, -12, -15
-7, -10, -12, -15
-6, -7
JC, VC
JC, VC
JC/1
MACH111
-7, -10, -12, -14, -18
JI
JI
MACH111SP
MACH131
-7, -10, -12, -14, -18
-7, -10, -12, -14, -18
-7, -10, -12, -14, -18
-10, -12, -14, -18
-10, -12, -14, -18
-10, -12, -14, -18
-10, -12, -14, -18
-12, -14, -18
JI/1
YI
JI
MACH131
MACH131SP
MACH211
MACH131SP
MACH211
VC, YC
JC, VC
JC, VC
JC
MACH211SP
MACH221
JI
MACH211SP
MACH221
JI
MACH221SP
MACH231
YI
JI/1
YI
MACH221SP
YC
JC
MACH231
MACH231SP
-12, -14, -18
-10, -12, -15
JC/1
MACH231SP
-10, -12, -15
VC, YC
Valid Combinations
The Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local Lattice/
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
Note:
1. All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e.
MACH131SP-5YC-7YI
MACH 1 & 2 Families
47
48
MACH 1 & 2 Families
相关型号：
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