OR3T55-6PS240-DB [LATTICE]
Field Programmable Gate Array, 324 CLBs, 80000 Gates, 80MHz, 2592-Cell, CMOS, PQFP240, PLASTIC, SQFP2-240;
| 型号： | OR3T55-6PS240-DB |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | Field Programmable Gate Array, 324 CLBs, 80000 Gates, 80MHz, 2592-Cell, CMOS, PQFP240, PLASTIC, SQFP2-240 时钟 栅 可编程逻辑 |
| 文件： | 总205页 (文件大小：1403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ORCA™ Series 3C and 3T FPGA Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue select devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
OR3C80
Ordering Part Number
OR3C805PS208-DB
OR3C804PS208-DB
OR3C804PS208I-DB
OR3C804BA352-DB
OR3T206T144-DB
OR3T207S208-DB
OR3T206S208-DB
OR3T206S208I-DB
OR3T207BA256-DB
OR3T206BA256-DB
OR3T307S208-DB
OR3T306S208-DB
OR3T306S208I-DB
OR3T307S240-DB
OR3T306S240-DB
OR3T306S240I-DB
OR3T307BA256-DB
OR3T306BA256-DB
OR3T306BA256I-DB
OR3T557S208-DB
OR3T556S208-DB
OR3T556S208I-DB
OR3T557PS240-DB
OR3T556PS240-DB
OR3T556PS240I-DB
Product Status
Discontinued
Reference PCN
PCN#02-06
OR3T20
OR3T30
OR3T55
Discontinued
PCN#09-10
Active / Orderable
Discontinued
PCN#12A-09
Active / Orderable
Active / Orderable
Discontinued
PCN#06-07
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Product Line
Ordering Part Number
OR3T557BA256-DB
OR3T556BA256-DB
OR3T556BA256I-DB
OR3T557BA352-DB
OR3T556BA352-DB
OR3T556BA352I-DB
OR3T807S208-DB
Product Status
Reference PCN
Active / Orderable
OR3T55
(Cont’d)
Discontinued
Discontinued
Discontinued
PCN#09-10
PCN#09-10
PCN#06-07
OR3T806S208-DB
OR3T806S208I-DB
OR3T807PS240-DB
OR3T806PS240-DB
OR3T806PS240I-DB
OR3T807BA352-DB
OR3T806BA352-DB
OR3T806BA352I-DB
OR3T807BC432-DB
OR3T806BC432-DB
OR3T806BC432I-DB
OR3T1257PS208-DB
OR3T1256PS208-DB
OR3T1256PS208I-DB
OR3T1257PS240-DB
OR3T1256PS240-DB
OR3T1256PS240I-DB
OR3T1257BA352-DB
OR3T1256BA352-DB
OR3T1256BA352I-DB
OR3T1257BC432-DB
OR3T1256BC432-DB
OR3T1256BC432I-DB
OR3T80
Discontinued
PCN#09-10
PCN#06-07
PCN#09-10
OR3T125
Discontinued
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: http://www.latticesemi.com
Data Sheet
November 2006
ORCA® Series 3C and 3T
Field-Programmable Gate Arrays
ble logic cl (PLC), woer 50% speed improvement
typical.
Features
■ Abundanhierarchal routing resoued on rout-
ing o datnibbleand two contret provide
fr fasr place and route implemeless rout-
indela
■ High-performance, cost-effective, 0.35 µm (OR3C) and
0.3 µm (OR3T) 4-level metal technology, (4- or 5-input
look-up table delay of 1.1 ns with -7 speed grade in
0.3 µm).
■ TTor CMOS input levels rogrammabler pin for the
■ Same basic architecture as lower-voltage, advanced
process technology Series 3 architectures. (See ORCA
Series 3L FPGA documentation.)
ORxx (5.0 V) devices.
■ Indiually programmble dre cability:
12 mA sink/6 mA sourcor 6 mink/3 mA source.
■ Up to 186,000 usable gates.
†
■ Built-in boundarscan (IE1149.1 JTAG) and
■ Up to 342 user I/Os. (OR3Txxx I/Os are 5 V tolerant t
allow interconnection to both 3.3 V and 5 V ds,
selectable on a per-pin basis.)
TS_ALL tesability nction o 3-state all I/O pins.
■ Enhanced sysm clouting for low skew, high-speed
clocks originatinon-chip or at any I/O.
■ Pin selectable I/O clamping diodes providV
PCI compliance and 5 V tolerance on OR3Tes.
■ Up to foExpresLK inputs allow extremely fast clock-
ing signs on- and off-chip plus access to internal
generclock outing.
■ Twin-quad programmable functiounit (PFU) aritec-
ture with eight 16-bit look-up tas (LUTs) per PFU,
organized in two nibbles for ue in ibble- or byte-wide
functions. Allows for mixed arithmetind logic functions
in a single PFU.
StopCLK ature to glitchlessly stop/start ExpressCLKs
dependently by user command.
■ Proammable I/O (PIO) has:
■ Nine user registers pePFU, one following each LUT,
plus one extra. All havprogramable clock enaband
local set/reset, pus a gbal seteset that can be
abled per PFU
— Fast-capture input latch and input flip-flop (FF) latch
for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and PAL-like
functions.
■ Flexible inpstruure (FINS) of the PFUa
routability enhement or LUTs with shand
the logic flexibilitof LTs with independ
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain dive capability
■ Fastarry logic and routing to adjt PFUbble-,
byte-we, or loner arithmetic fnctions, with the option
to registthe PFU carry-out.
— Capability to register 3-state enable signal.
■ Baseline FPGA family used in Series 3+ FPSCs (field
programmable system chips) which combine FPGA logic
and standard cell logic on one device.
■ Sowired LUTs (SWL) allow fast ascadiof up to
ree levels of LUT logiin a single for up to 40%
peed mprovement.
* PAL is a trademark of Advanced Micro Devices, Inc.
†IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
■ Suplemental logic and interconct cell (SLIC) pro-
vides 3-statable burs, up to 1-bit decoder, and PAL*-
like AND-OR with opnal INVERT in each programma-
Table 1. Os 3 (3C and 3T) FPGAs
System
Gates
Max User
I/Os
Process
Technology
Device
LUTs
Registers Max User RAM
Array Size
‡
OR3T20
OR3T30
36K
1152
1568
2592
3872
6272
1872
2436
3780
5412
8400
18K
25K
42K
62K
100K
192
221
288
342
342
12 x 12
14 x 14
18 x 18
22 x 22
28 x 28
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
48K
OR3T55
80K
OR3C/3T80
OR3T125
116K
186K
‡The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table of Contents
Contents
Page
Contents
Page
Features ......................................................................1
System-Level Features................................................4
Description...................................................................5
FPGA Overview ..........................................................5
PLC Logic ...................................................................5
Description (continued)................................................6
PIC Logic ....................................................................6
System Features ........................................................6
Routing .......................................................................6
Configuration ..............................................................6
Description (continued)................................................7
ispLEVER Development System ................................7
Architecture .................................................................7
Programmable Logic Cells ..........................................9
Programmable Function Unit ......................................9
Look-Up Table Operating Modes .............................11
Supplemental Logic and Interconnect Cell (SLIC).....19
PLC Latches/Flip-Flops ............................................2
PLC Routing Resources ........................................
PLC Architectural Description ...................................
rogrammable Input/Output Cells................................34
5 V Tolerant I/O .....................................................35
PCI Compliant I/O .................................................35
Inputs .....................................................................36
Outputs ...................................................................39
PIC Routing Resources .......................................42
PIC Architectural Description ..............................43
High-Level Routing Resouces................................45
Interquad Routing .............................................
Programmable Corner Cell outin.....................
PIC Interquad (MID) Routing .............................
Clock Distribution etwork ......................................48
PFU Clock Sources ..........................................48
Clock Disbutioin the PLC Array ....................49
Clock Sourto the PLC Array ...........................50
Clocs in the Cs ..........................................50
ExressInputs ...............................................51
Selecting Cck Input Pins .................................51
SpeciaFnction Blocks ................................52
Single Function Block...............................52
Boundary Scan ..........................................55
Microprocessor Interface () .................................62
PowerPC System .....................................................63
i960 System ..............................................................64
MPI Interface to FPGA .............................................65
MPI Setup and Control .............................................66
Programmable Clock Manager (PCM) ......................70
PCM Registers .........................................................71
Delay-Locked Loop (DLL) Mode ...............................73
Phase-Locked Loop (PLL) Mode ..............................74
PCM/FPGA Internal Interface ...................................77
PCM Operation .........................................................77
2
PCM Detailed Programming .................................... 78
PCM Applications ................................................ 81
PCM Cautions ...................................................... 82
FPGA States of Operation............................... 83
Initialization ........................................................... 83
Configuration ..................................................... 84
Start-Up ........................................................... 85
Reconfiguration .................................................. 86
Partial Reconfiguraon ............................................ 86
Other Configuration ptions .....................86
Using ispLEVER o Geere
Configuratin RAData ..........................87
Configuration ata Frme ................................ 87
Bit StreaErroChecking .................................. 89
FPGA Configurion Modes.............................. 90
asteParallel Mode .......................................... 90
Mer Seal Mode ........................................... 91
Asynhrnous Peripheal Moe ............................ 92
croprocessor Interface MPI) Mode ..................... 92
ve Serial Mod....................................... 95
lave Parallel ode ............................................... 95
Daisy-Chaiing ................................................... 96
Daisy-Cning witBoundary Scan ....................... 97
Absolute Mimum Ratings...................................... 98
RecmmendeOperating Conditions ..................... 98
Electril Characteristics .......................................... 99
iracteristic Description .......................... 101
Decription ............................................................. 101
PFU iming ........................................................... 102
LC Timing ............................................................ 109
LIC Timing ........................................................... 109
PIO Timing ............................................................. 110
Special Function Blocks Timing ............................. 113
Clock Timing .......................................................... 121
Configuration Timing ............................................. 131
Readback Timing ................................................... 140
Input/Output Buffer Measurement Conditions ........ 141
Output Buffer Characteristics ................................. 142
OR3Cxx ................................................................. 142
OR3Txxx ................................................................ 143
Estimating Power Dissipation................................. 144
OR3Cxx ................................................................. 144
OR3Txxx................................................................. 145
Pin Information ....................................................... 147
Pin Descriptions...................................................... 147
Package Compatibility ........................................... 151
Compatibility with OR2C/TxxA Series .................... 152
Package Thermal Characteristics........................... 188
FPGA Maximum Junction Temperature ................ 190
Package Coplanarity .............................................. 191
Package Parasitics................................................. 191
Package Outline Diagrams..................................... 192
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table of Contents
Contents
Page
Contents
Page
Terms and Definitions .............................................192
144-Pin TQFP .........................................................193
208-Pin SQFP ........................................................194
208-Pin SQFP2 ......................................................195
240-Pin SQFP .........................................................196
240-Pin SQFP2 .......................................................197
256-Pin PBGA ........................................................198
352-Pin PBGA ........................................................199
432-Pin EBGA ........................................................200
Ordering Information................................................201
Lattice Semiconductor
3
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
phase and duty cycle for input clock rates from
System-Level Features
5 MHz to 120 MHz. The PCM may be combined with
FPGA logic to create complex functions, such as dig-
ital phase-locked loops (DPLL), frequency counters,
and frequency synthesizers or clock doublers. Two
PCMs are provided per device.
System-level features reduce glue logic requirements
and make a system on a chip possible. These features
in the ORCA Series 3 include:
■ Full PCI local bus compliance.
■ True, internal, 3-state, bidirectionbus ith simple
■ Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA. Glueless interface to i960* and
PowerPC† processors with user-configurable
address space provided.
control provided by the SLIC
■ 32 x 4 RAM per PFU, cogurale as single- or dual-
port at >176 MHz. Create e, fast RAM/ROM
blocks (128 x 8 in oly eight FU) using the SLIC
decoders as bandrivers.
■ Parallel readback of configuration data capability with
* i960 is a regisred tremark of Intel Corporaon.
†PowerPC is a ristered ademark of Interntional Busi
MachiCorpotion.
the built-in microprocessor interface.
■ Programmable clock manager (PCM) adjusts clock
Table 2. ORCA Series 3 System Performance
Spee
Parameter
PFU
Unit
-4
78
78
-5
-6
7
168
168
16-bit Loadable Up/Down Counter
16-bit Accumulator
102
2
131
MHz
MHz
8 x 8 Parallel Multiplier:
Multiplier Mode, Unpipelined1
ROM Mode, Unpipelined2
Multiplier Mode, Pipelined3
32 x 16 RAM (synchronous):
Single-port, 3-state Bus4
Dual-port5
11.5
8
15
19
51
7
25
104
30
80
127
38
102
166
MHz
MHz
MHz
4
97
127
127
166
151
203
192
253
MHz
MHz
128 x 8 RAM (synchronou):
Single-port, 3-state Bu4
Dual-port5
8
88
88
116
116
139
139
176
176
MHz
MHz
8-bit Address Decode (interna
Using Softwired UTs
Using SLIs6
0.25
0
4.87
2.35
3.66
1.82
2.58
1.23
2.03
0.99
ns
ns
32-bit Adess Dcode nternal):
Using Stred LUTs
Ug SLI7
2
0
2
16.06 12.07 9.01
6.91 5.41 4.21
16.06 12.07 9.01
7.03
3.37
7.03
ns
ns
ns
3bit Paty Chck (internal)
1. Implementeusing 8 x 1 multiplier mo(unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Impled using two 32 Ms anone 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x de (fully pipelined), two 8-bit inputs, one 16-bit output (7 of 15 PFUs contain only pipelining registers).
4. Implemented using 32 x 4 with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 duAM mode.
6. Implemented in one partially ocied SLIC with decoded output set up to CE in same PLC.
7. Implemented in five partially occupied SLICs.
4
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
PLC Logic
Description
Each PFU within a PLC contains eight 4-input (16-bit)
look-up tables (LUTs), eight latches/flip-flops (FFs),
and one additional flip-flop that may be used indepen-
dently or with arithmetic functions.
FPGA Overview
The ORCA Series 3 FPGAs are a new generation of
SRAM-based FPGAs built on the successful OR2C/
TxxA FPGA Series, with enhancements and innova-
tions geared toward today’s high-speed designs and
tomorrow’s systems on a single chip. Designed from
the start to be synthesis friendly and to reduce place
and route times while maintaining the complete
routability of the ORCA 2C/2T devices, Series 3 more
than doubles the logic available in each logic block and
incorporates system-level features that can further
reduce logic requirements and increase system speed.
ORCA Series 3 devices contain many new patented
enhancements and are offered in a variety of pack-
ages, speed grades, and temperature ranges.
The PFU is organized in a win-qfashion: two sets
of four LUTs and FFs tat can be cotrolled indepen-
dently. LUTs may alsbe combnefor use in arith-
metic functions usig fa-carry chain logic in either
4-bit or 8-bit modes. Te carr-out of either mode may
be registerein the nintF for pipelining. Each PFU
may also bconfigud as a synchrons 32 x 4 sin-
gle- or ual-rt RAor ROM. Thatches)
may obtainput rom LUT outputs from
inverble Pinputs, or they can be th or tied
low. ThFFs also have prorammable clck polarity,
cloebles, and local seteet.
The ORCA Series 3 FPGAs consist of three basic ee-
ments: programmable logic cells (PLCs), programm
ble input/output cells (PICs), and system-level features.
An array of PLCs is surrounded by PICs. Ea
contains a programmable function unit (PF
plemental logic and interconnect cell (SLIC), lt-
ing resources, and configuration RAM. Most of th
FPGA logic is performed in the Pbut decoders,
PAL-like functions, and 3-state bufferig can be per-
formed in the SLIC.The PICrovide dece inputs and
outputs and can be used o register signals and to per-
form input demultiplexingoutput ultiplexing, and
other functions on wo outpsigals. Some of the s-
tem-level functios inclde the new microprr
interface (MPI) ane prorammable clor
(PCM).
The SLIC is connected to LC ring resources and to
the outputs of the FU. It cotains 3-state, bidirectional
uffers and logc to prform p to a 10-bit AND function
for decoding, or n ANDOR with optional INVERT
(AOI) to pm P-like functions. The 3-state drivers
in the LIC nd their direct connections to the PFU out-
putmafasttrue 3-state buses possible within the
GA, redcing required routing and allowing for real-
wosystem performance.
Lattice Semiconductor
5
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
innovative programmable clock manager. These func-
tional blocks allow for easy glueless system interfacing
and the capability to adjust to varying conditions in
today’s high-speed systems.
Description (continued)
PIC Logic
Series 3 PIC addresses the demand for ever-increas-
ing system clock speeds. Each PIC contains four pro-
grammable inputs/outputs (PIOs) and routing
Routing
resources. On the input side, each PIO contains a fast-
capture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a sys-
tem clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the ORCA 2C/2T capability to use any input
pin as a clock or other global input is maintained.
The abundant routing resourceof the ORCSeries 3
FPGAs are organized to roue signals invidually or as
buses with related control sina. Clocks are routed on
a low-skew, high-speed istribion etwork and may
be sourced from PLlogic, exterally from any I/O
pad, or from the vefast ExessCLK pins. ss-
CLKs may be gchlely anindependen
and disablewith programmable control sg
the new StopLK feare. The improed PIC ro
resourcare ow similar to the penteintra-PLC
roung resouand provide great ibility n moving
gnals to and from the PIOs. Thflexibittranslates
io n improved capabilitto route esigns at the
reqred peeds when the I/signahave been
cked to specific pins.
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The outp
logic associated with each pad allows for multiplexi
of output signals and other functions of two output sig
nals.
Configuratio
The output FF in combination with outpt sial multi-
plexing, is particularly useful for registering adess
signals to be multiplexed with dataallowing a full clock
cycle for the data to propagate to he outp. The I/O
buffer associated with each ad is ery silar to the
ORCA 2C/2T Series buffewith a new, fast, open-drain
option for ease of use on ystm buses.
The FPAfunctionlity is determined by internal
configuration AM. The FPGA’s internal initialization/
confiuration ciuitry loads the configuration data at
poweruor under system control. The RAM is loaded
using e of several configuration modes. The con-
figuation data resides externally in an EEPROM or any
ther storage media. Serial EEPROMs provide a sim-
e, low pin count method for configuring FPGAs. A
ew, easy method for configuring the devices is
through the microprocessor interface.
System Featurs
Series 3 ao proides stem-level functioality by
means of idal-use microprocessr interfaad its
6
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The OR3T55 array in Figure 1 has PLCs arranged in
an array of 18 rows and 18 columns. The location of a
PLC is indicated by its row and column so that a PLC in
the second row and the third column is R2C3. PICs are
located on all four sides of the FPGA between the
PLCs and the device edge. PIs are indicated using
PT and PB to designate PIs on the top and bottom
sides of the array, respectivand L and PR to des-
ignate PICs along the eft and right ides of the array,
respectively. The pition f a PIC on an edge of the
array is indicated by umbecounting from left to
right for PT ad PB and op to bottom for PL and PR
PICs.
Description (continued)
ispLEVER Development System
The ispLEVER Development System is used to pro-
cess a design from a netlist to a configured FPGA.This
system is used to map a design onto the ORCA archi-
tecture and then place and route it using ispLEVER’s
timing-driven tools. The development system also
includes interfaces to, and libraries for, other popular
CAE tools for design entry, synthesis, simulation, and
timing analysis.
The ispLEVER Development System interfaces to
front-end design entry tools and provides the tools to
produce a configured FPGA. In the design flow, the
user defines the functionality of the FPGA at two points
in the design flow: at design entry and at the bit stream
generation stage.
Each PC coains ruting resourcr program-
mabe I/O(PIOs). Each PIO contacessary
I/O bfers tinterface to bond pads. n Series 3
FPGAalso contain input nd oput FFs, fast open-
draiability on output bus, special output logic
functions, and signal miplexig/emultiplexing capa-
bilities.
Following design entry, the development system’s mp,
place, and route tools translate the netlist into a route
FPGA. A static timing analysis tool is provideter-
mine device speed and a back-annotated ne
created to allow simulation. Timing and simu
put files from ispLEVER are also compatible witny
third-party analysis tools. Its bit stram generator is
then used to generate the confiuran data which is
loaded into the FPGA’s internal configation RAM.
When using the bit stream generator, the user selects
options that affect the funtionality of the FPGA. Com-
bined with the front-nd tols, ispEVER produces
configuration data that implements the various logic
and routing optios dcussed in this data
LCs comprisa prorammable function unit (PFU), a
supplemental logand interconnect cell (SLIC), and
routing reese PFU is the main logic element
of the LC, ntaining elements for both combinatorial
anseqntial ogic. Combinatorial logic is done in
k-up tabs (LUTs) located in the PFU.The PFU can
be ed in different modes to meet different logic
requirents. The LUT’s twin-quad architecture pro-
vides a configurable medium-/large-grain architecture
t can be used to implement from one to eight inde-
pendent combinatorial logic functions or a large num-
ber of complex logic functions using multiple LUTs.The
flexibility of the LUT to handle wide input functions, as
well as multiple smaller input functions, maximizes the
gate count per PFU while increasing system speed.
Architeture
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can realize any 4- or 5-input
logic function and many multilevel logic functions using
ORCA’s softwired LUT (SWL) connections. In ripple
mode, the high-speed carry logic is used for arithmetic
functions, comparator functions, or enhanced data path
functions. In memory mode, the LUTs can be used as a
32 x 4 synchronous read/write or read-only memory, in
either single- or dual-port mode.
TORA Series 3 FPGA compriss threbasic ele-
mePLCPICs, and sstem-level functions. Figure
1 shon array of progrmble ogic cells (PLCs)
uounded by programable inpuoutput cells (PICs).
Alsshown are the interuad routing blocks (hIQ, vIQ)
esent in Seristemevel functions (located in
the corners oand the routing resources and
configuration Rot shown in Figure 1.
Lattice Semiconductor
7
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Architecture (continued)
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PT8
PT9
TMID PT10
R1C10
PT11 PT12
PT13
PT14
PT15 PT16
PT17
PT18
R1C11 R1C12 R1C13 R1C14 R1C15 R1CR1C17 C18
R1C1 R1C2 R1C3 R1C4 R1C5 R1C6 R1C7 R1C8 R1C9
R2C1 R2C2 R2C3 R2C4 R2C5 R2C6 R2C7 R2C8 R2C9
R2C10 R2C11 R2C12 R2C13 R2C14 R2CR2C16 R2C17 R18
vIQ
R3C11 R3C12 R3C13 R3C14 R13C16 R17 R3C18
R4C11 R4C12 R4C1R4C14 R4C15 R16 R4C17 R4C18
R5C11 R5C15C13 C14 R15 R5C16 R5C17
R3C1 R3C2 R3C3 R3C4 R3C5 R3C6 R3C7 R3C8 R3C9
R4C1 R4C2 R4C3 R4C4 R4C5 R4C6 R4C7 R4C8 R4C9
R5C1 R5C2 R5C3 R5C4 R5C5 R5C6 R5C7 R5C8 R5C9
R6C1 R6C2 R6C3 R6C4 R6C5 R6C6 R6C7 R6C8 R6C9
R7C1 R7C2 R7C3 R7C4 R7C5 R7C6 R7C7 R7C8 R7C9
R8C1 R8C2 R8C3 R8C4 R8C5 R8C6 R8C7 R8C8 R8C9
R3C10
R4C10
R5C10
R6C10 R6C11 R6R6C13 6C14 R6C15 R6C16 6C17 R6C1
R7CR7C11 R7C13 R7C14 R7C15 R7C16 17 R7
C1
9C10
R8C11 R8C12 R8C13 R8C14 R8C15 R8CR8C17 R8C18
11 R9C12 R9C13 R94 R9CR9CR9C17 R9C18
R9C1 R9C2 R9C3 R9C4 R9C5 R9C6 R9C7 R9C8 R9
hIQ
R10C1 R10C2 R10C3 R10C4 R10C5 R10C6 R10R10C8 R10C9
R10C10 R10C11 0C12 13 R14 R10C15 R10C16 R10C17 R10C18
R11C1 R11C2 R11C3 R11C4 R11C5 R11C6 R11C7 R1R11C9
R12C1 R12C2 R12C3 R12C4 R12C5 R12C6 R12C7 R12C8 R12C9
R13C1 R13C2 R13C3 R13CR13C5 R6 R7 R13C8 R13C9
R11C10 R1C11 R12 R11C13 R11C14 R11C15 R11C16 R11C17 R11C18
R12C10 C11 R12C12 R12C13 R12C14 R12C15 R12C16 R12C17 R12C18
C10 R13C1R13C12 R13C13 R13C14 R13C15 R13C16 R13C17 R13C18
R14C1 R14C2 R14C3 R14C5 RC6 R14C7 R14C8
R15C1 R15CR15C3 R15C4 R5 R15C6 R15C7 8 R1
4C10 R14C11 R14C12 R14C13 R14C14 R14C15 R14C16 R14C17 R14C18
R15C10 R15C11 R15C12 R15C13 R15C14 R15C15 R15C16 R15C17 R15C18
R16R16C2 R16CR4 R16C5 R16C6 R16R16C8 RC9
R17C7C2 R3 R17C4 R17C5 17C6 R17C7 R17C8 R17C9
R16C10 R16C11 R16C12 R16C13 R16C14 R16C15 R16C16 R16C17 R16C18
R17C10 R17C11 R17C12 R17C13 R17C14 R17C15 R17C16 R17C17 R17C18
R18C2 R18C3 R18C4 R5 R18C6 R18R18C8 R18C9
R18C10 R18C11 R18C12 R18C13 R18C14 R18C15 R18C16 R18C17 R18C18
PB
PB2
PB3
PB5
B6
PB7
PB8
PB9
PB10
BMID PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
5-4489(F)
Figure 1. OR3T55 Array
8
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells
F5D
The programmable logic cell (PLC) consists of a pro-
grammable function unit (PFU), a supplemental logic
and interconnect cell (SLIC), and routing resources. All
PLCs in the array are functionally identical with only
minor differences in routing connectivity for improved
routability.The PFU, which contains eight 4-input LUTs,
eight latches/FFs, and one FF for logic implementation,
is discussed in the next section, followed by discus-
sions of the SLIC and PLC routing resources.
K7_0
K7_1
K7_2
K7_3
K6_0
K6_1
K6_2
K6_3
K5_0
K5_1
K5_2
K5_
K0
K4
K4_
4_3
Programmable Function Unit
6
Q5
Q4
Q3
Q2
Q1
The PFUs are used for logic. Each PFU has 50 external
inputs and 18 outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.
F5
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
Q0
The PFU uses 36 data input lines for the LUTs, eigh
data input lines for the latches/FFs, five control inputs
(ASWE, CLK, CE, LSR, SEL), and a carry in)
for fast arithmetic functions and general-pur
input for the ninth FF.There are eight combinata
outputs (one from each LUT), eight ltched/registed
outputs (one from each latch/FF), arry-out (COUT),
and a registered carry-out (REGCOUthat comes from
the ninth FF. The carry-out sials are ud principally
for fast arithmetic function.
PROGRMABLE
FUNCTIUNIT
(P)
COUT
REGCOUT
F5B
F7
F6
F5
F4
F3
F2
F1
F0
_0
K3
K3_2
K3_3
K2_0
K2_1
K2_2
K2_3
Figure 2 and Figure 3 shohigh-leel and detailed
views of the ports the PFUpectively. The eight
sets of LUT inpuare abeled as K0 throug
each of the four inpto ech LUT having
_x, where x is a numbrom 0 to 3. There
inputs labeed A through D. These iputs are usfor a
fifth UT inpufor 5input LUTs or s a selecor for multi-
plxing to 4-inut LUTs. The eight irect da inputs to
the ahes/Fs are labeled s DIN[7:0egistered LUT
outpuarshown as Q[7], ambinatorial LUT
oputs are labeled as F[7:0].
K1_0
K1_1
K1_2
K1_3
K0_0
K0_1
K0_2
K0_3
F5A
LSR CLK
CE
SEL ASWE
The PFU implements cominatorial logic in the LUTs
and sequential he laches/FFs. The LUTs are
static random mory (SRAM) and can be used
for read/write or rly memory.
5-5752(F)
Figure 2. PFU Ports
Each latch/FF can accept data from its associated LUT.
Alternatively, the latches/FFs can accept direct data
from DIN[7:0], eliminating the LUT delay if no combina-
torial function is needed. Additionally, the CIN input can
be used as a direct data source for the ninth FF. The
LUT outputs can bypass the latches/FFs, which reduces
the delay out of the PFU. It is possible to use the LUTs
and latches/FFs more or less independently, allowing,
for instance, a comparator function in the LUTs simulta-
neously with a shift register in the FFs.
The PFU can be configured to operate in four modes:
logic mode, half-logic mode, ripple mode, and memory
(RAM/ROM) mode. In addition, ripple mode has four
submodes and RAM mode can be used in either a
single- or dual-port memory fashion. These submodes
of operation are discussed in the following sections.
Lattice Semiconductor
9
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
F7
F5D
REG7
Q7
0
D0
DIN7
0
K7_0
K7
A
B
D1
DSEL
CE
K7_1
K7_2
CK
S/R
C
D
F6
K7_3
K6_0
REG6
Q6
DIN6
0
K6
D0
D1
A
B
C
K6_1
K6_2
DSEL
CE
1
0
CK
S/R
K6_3
D
F5MODE67
K5
REG5
5
K5_0
K5_1
K5_2
K5_3
DIN5
0
A
B
C
D
D0
L
C
CK
S/R
K4
K4_0
K4_1
K4_2
K4_3
A
B
C
D
1
0
F4
Q4
DIN4
0
F5C
D1
DSEL
CE
F5MODE45
0
CK
S/R
CLK
SEL
0
0
0
CIN
CE
1
FF8
1
1
GCOUT
D
CE
CK
R
ASWE
1
0
LSR
0
0
F3
F5B
REG3
Q3
0
D0
D
0
K3_0
K3
A
B
D1
DSEL
CE
1
K
CK
S/R
C
F2
K3_3
2_0
REG2
DIN2
0
Q2
K2
D0
D1
A
C
K2_1
K2_2
DSEL
CE
1
0
CK
S/R
K2_3
ODE23
F1
K1
A
B
C
D
REG1
K1
K
K1_
DIN1
0
Q1
D0
D1
DSEL
CE
CK
S/R
K0
K0_0
K0_1
K0_2
K0_3
A
B
C
D
1
0
F0
REG0
DIN0
0
Q0
D0
F5A
D1
DSEL
CE
F5MODE01
0
CK
S/R
5-5743(F)
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 3. Simplified PFU Diagram
10
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Look-Up Table Operating Modes
The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam-
ple, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latcheFFs. In memory mode,
the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write addess input bus into LUT
memory.
Table 3 lists the basic operating modes of the LUT. Figure 4—Figure 10 show bck diagramof the LUT operating
modes. The accompanying descriptions demonstrate each mode’s use for genratg logic.
Table 3. Look-Up Table Operating Modes
Mode
Function
Logic
4- and 5-input LUTs; softwired LUTs; latches/FFs ith dect input or LUT input; Cct input to
ninth FF or as pass through to COUT.
Half Logic/ Upper four LUTs and latches/FFs in logic mod; lowefour LUTs and lates/Fs in ripple mode; CIN
Half Rip- and ninth FF for logic or ripple functions.
ple
Ripple
All LUTs combined to perform ripple-thrh data functions. EigLUT resters available for direct-in
use or to register ripple output. NFF dicaed to ripple ot, if ued.Thsubmodes of ripple mode
are adder/subtractor, counter, and comparator.
Memory All LUTs and latches/FFs used a 32 x 4 synchrd-port RAM. Can be used as single-
port or as ROM.
PFU Control Inputs
Each PFU has five routable ntrol inpuand an activ-low, asychronous global set/reset (GSRN) signal that
affects all latches and FFin the device. The five control puts are CLK, LSR, CE, ASWE, and SEL, and their
functionality for each logimode othe PFU (discd suequently) is shown in Table 4. The clock signal to the
PFU is CLK, CE stnds for ock nable, which is its rimary function. LSR is the local set/reset signal that can be
configured as sychroous or asynchronouseleon of set or reset is made for each latch/FF and is not a
function of the sigitself. SWE stands tract/write enable, which are its functions, along with being an
optional clock enablanSEL is used to y select between direct PFU input and LUT output data as the
input to te latches/FFs.
All othe conol sgnals can be dabled ad/or inverted via the configuration logic. A disabled clock enable indi-
ces tht the clock is always enabd. A dabled LSR indicates that the latch/FF never sets/resets (except from
GS). A diabled SEL inut indicates that DIN[7:0] PFU inputs are routed to the latches/FFs. For logic and ripple
modeof he PFU, the LSR, C, ad ASWE (as a clock enable) inputs can be disabled individually for each nibble
h/FF[3:0], latch/F[7:4]) and fothe ninth FF.
Lattice Semiconductor
11
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Table 4. Control Input Functionality
Mode
CLK
CLK to all latches/ LSR to all latches/
FFs FFs, enabled per nib- selectable per nibble selectable per nibble iput and direct input
LSR
CE
ASWE
SEL
Logic
CE to all latches/FFs, CE to all latches/FFs, Select between LUT
ble and for ninth FF
and for ninth FF
and for ninth FF
r et lahes/FFs
Half Logic/ CLK to all latches/ LSR to all latches/FF, CE to all latches/FFs, Ripple logic contr
Select beteen LUT
input and direct input
for eight latches/FFs
Half Ripple FFs
Ripple
enabled per nibble
and for ninth FF
selectable per nibble input
and for ninth FF
CLK to all latches/ LSR to all latches/
FFs
CE to all latches/FFs, Ripple logcontro
Slect between LUT
input and direct input
for eight latFFs
FFs, enabled per nib- selectable per nibble input
ble and for ninth FF
and for ninth FF
Memory CLK to RAM
(RAM)
Port enable 2
Port enable 1
Not used
Wte enble
ot use
Not use
Memory Optional for sync. Not used
Nt used
(ROM)
outputs
Logic Mode
F5D
The PFU diagram of Figure 3 represents the logic
mode of operation. In logic mode, the eight LUTs are
used individually or in flexible groups to implement u
logic functions. The latches/FFs may be used in con
junction with the LUTs or separately with the direct
PFU data inputs. There are three basic subodes of
LUT operation in PFU logic mode: F4 mdeF5 mode,
and softwired LUT (SWL) mode. Combinations f these
submodes are possible in each PF.
F7
6
F5
F4
F3
F2
F1
F0
K6
K
K4
K3
K2
K1
K7
F6
K6
K7/K6
K5/K4
K3/K2
F6
F4
F2
F0
K5
K4
F4 mode, shown simplified in Fige 4, illurates the
uses of the basic 4-input LUs in tPFUThe output
of an F4 LUT can be pased ouof the PFU, capture
at the LUTs associated lah/F, or multiplexed with
adjacent F4 LUT output usinone of the F5[A:D] in
to the PFU. Only djacent LUT airs (K0 and , K2
and K3, K4 and K5, and K) can be mulplexed, and
the output aways goeo he even-numbed outpof
the pair.
F4
F5C
F5B
K3
The subme othe LUT opertion, wn simpli-
fiein Figre 4, ndicates the se of 5-inpuLUTs to
impment lgic. 5-input LUTs acreefrom two
4-input LUs and a multir. ThF5 LUT is the
same as the multiplexF4 LUTs described
previously with the cont the inputs to the F4
LUTs be the same. The F] input is then used as
the fifth LUT input. The equations for the two F4 LUTs
will differ by the assumed value for the F5[A:D] input,
one F4 LUT assuming that the F5[A:D] input is zero,
and the other assuming it is a one. The selection of the
appropriate F4 LUT output in the F5 MUX by the
F5[A:D] signal creates a 5-input LUT. Any combination
of F4 and F5 LUTs is allowed per PFU using the eight
16-bit LUTs. Examples are eight F4 LUTs, four F5
LUTs, and a combination of four F4 plus two F5 LUTs.
K1/K0
F2
K2
K1
F5 MODE
F0
K0
K0
F5A
F4 MODE
MULTIPLEXED F4 MODE
5-5970(F)
Figure 4. Simplified F4 and F5 Logic Modes
12
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Softwired LUT submode uses F4 and F5 LUTs and internal PFU feedback routing to generate complex logic func-
tions up to three LUT-levels deep. Figure 3 shows multiplexers between the KZ[3:0] inputs to the PFU and the
LUTs.These multiplexers can be independently configured to route certain LUT outputs to the input of other LUTs.
In this manner, very complex logic functions, some of up to 21 inputs, can be implementen a single PFU at
greatly enhanced speeds.
Figure 5 shows several softwired LUT topologies. In this figure, each circle represents either an 4 or F5 LUT. It is
important to note that an LUT output that is fed back for softwired use is still avalable to be reistered or output
from the PFU.This means, for instance, that a logic equation that is needed by self nd as a term in a larger equa-
tion need only be generated once and PLC routing resources will not be required o use t in the larger equation.
F4
F4
F4
F4
F4
F4
F4
F4
F5
F5
F5
5
FOUR 7-INPUT FUNCTIONS IN ONE PFU
F5
TWO 9-INUT FUNCONS IN ONE PFU
4
F4
F4
F5
5
F5
F5
ONE 17-PFUNCTION IN ONE
ONE 21-INPUT FUNCTION IN ONE PFU
5-5753(F)
F4
F4
F4
F4
3
F4
F4
F4
TWO OF FOUR 10-INPUT FUNCTIONS IN ONE PFU
KEY:
ONE OF TWO 12-INPUT FUNCTIONS IN ONE PFU
5-5754(F)
F4 4-INPUT LUT
F5 5-INPUT LUT
Figure 5. Softwired LUT Topology Examples
Lattice Semiconductor
13
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
with half-logic ripple connections shown as dashed
lines.
Programmable Logic Cells (continued)
Half-Logic Mode
The result output and ripple output are calculated by
using generate/propagate circuitry. In ripple mode, the
two operands are input into KZ[1] and KZ[0] of each
LUT.The result bits, one per LUT, arF[7:0]/F[3:0] (see
Figure 6). The ripple output from LT K3 an be
routed on dedicated carry circury into any ofour adja-
cent PLCs, and it can be plaed on the U COUT/
FCOUT outputs. This allowthe LCs to be cascaded
in the ripple mode so that nib-widripple functions
can be expanded eaily to any leth.
Series 3 FPGAs are based upon a twin-quad architec-
ture in the PFUs. The byte-wide nature (eight LUTs,
eight latches/FFs) may just as easily be viewed as two
nibbles (two sets of four LUTs, four latches/FFs). The
two nibbles of the PFU are organized so that any nib-
ble-wide feature (excluding some softwired LUT topolo-
gies) can be swapped with any other nibble-wide
feature in another PFU. This provides for very flexible
use of logic and for extremely flexible routing. The half-
logic mode of the PFU takes advantage of the twin-
quad architecture and allows half of a PFU, K[7:4] and
associated latches/FFs, to be used in logic mode while
the other half of the PFU, K[3:0] and associated latches/
FFs, is used in ripple mode. In half-logic mode, the
ninth FF may be used as a general-purpose FF or as a
register in the ripple mode carry chain.
Result outputs and e carryut may optionreg-
istered within thPFUhe apability to rep-
ple results, iludinthe carry output, rovid
improved couer perrmance and implified pin-
ing in aritmetifunctions.
Ripple Mode
REGCOUT
Q
C
The PFU LUTs can be combined to do byte-wide ri
functions with high-speed carry logic. Each LUT has
dedicated carry-out net to route the carry to/fom any
adjacent LUT. Using the internal carry circs, fast
arithmetic, counter, and comparison functioncan be
implemented in one PFU. Similarly, each PFU hs
carry-in (CIN, FCIN) and carry-ou(COUT, FCOUT)
ports for fast-carry routing betweadjacet PFUs.
FCOUT
COUT
F7
K7[
K7[0]
D
D
D
D
D
D
D
D
K7
K6
K5
K4
K3
K2
K1
K0
Q7
Q
Q
Q
Q
Q
Q
Q
Q
F6
K6[
Q6
The ripple mode is generallused in petions on two
data buses. A single PFcan upport an 8-bit rippl
function. Data buses of 4 and less can use the
nibble-wide ripple chain that aailable in half-log
mode. This nibbleide ripple chain is also ueful for
longer ripple hains here he length modlo 8 is four
or less. Foexample, a -bit adder (12 mulo 8 = 4)
can be imemnted in one PFU in ple mo(8 bits)
and oe PFU n ha-logic mode (bits), eing half of
a FU for generl logic mode functions.
F5
[1]
K5[0]
Q5
F4
K4[1]
K4[0]
Q4
F3
K3[1]
K3[0]
Q3
F2
K2[1]
K2[0]
Q2
Each LUT hs two operands and ripple (generally
carry) it, and providult ad ripple (generally
carry) output. A single ed from the previous
LUT and is used as inpucurrent LUT. For LUT
K0, the ripple input is from PFU CIN or FCIN port.
The CIN/FCIN data can come from either the fast-carry
routing (FCIN) or the PFU input (CIN), or it can be tied
to logic 1 or logic 0.
F1
K1[1]
K1[0]
Q1
F0
K0[1]
K0[0]
Q0
CIN/FCIN
5-5755(F)
In the following discussions, the notations LUT K7/K3
and F[7:0]/F[3:0] are used to denote the LUT that pro-
vides the carry-out and the data outputs for full PFU
ripple operation (K7, F[7:0]) and half-logic ripple
operation (K3, F[3:0]), respectively. The ripple mode
diagram in Figure 6 shows full PFU ripple operation,
Figure 6. Ripple Mode
14
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
REGCOUT
D
Q
The ripple mode can be used in one of four submodes.
The first of these is adder-subtractor submode. In
this submode, each LUT generates three separate out-
puts. One of the three outputs selects whether the
carry-in is to be propagated to the carry-out of the cur-
rent LUT or if the carry-out needs to be generated. If
the carry-out needs to be generated, this is provided by
the second LUT output. The result of this selection is
placed on the carry-out signal, which is connected to
the next LUT carry-in or the COUT/FCOUT signal, if it
is the last LUT (K7/K3). Both of these outputs can be
any equation created from KZ[1] and KZ[0], but in this
case, they have been set to the propagate and gener-
ate functions.
C
C
FCOUT
COUT
F7
K7[0]
K6[0]
K5[0]
0]
K
K2[0]
K1[0]
K0[0]
D
D
D
D
D
D
D
K7
K6
K5
K4
K3
K1
K0
Q
Q
Q
Q7
F6
Q6
F5
Q5
F4
Q
Q
Q
Q4
The third LUT output creates the result bit for each LUT
output connected to F[7:0]/F[3:0]. If an adder/subtrac-
tor is needed, the control signal to select addition o
subtraction is input on ASWE, with a logic 0 indicatin
subtraction and a logic 1 indicating addition. Thesult
bit is created in one-half of the LUT from a
from each input bus KZ[1:0], along with the t
bit.
F3
Q3
F2
Q2
F1
Q1
The second submode is the counr submode (see
Figure 7). The present count, which ay be initialized
via the PFU DIN inputs to the latches/Fs, is supplied
to input KZ[0], and then otput F[7:0]/F[3:0] will either
be incremented by one foan up cunter or decre-
mented by one for a down ounteIf an up/down
counter is needethe control signal to select direc
tion (up or down) s iput on ASWE with a i-
cating an up counteand logic 0 indicati
counter. Generally, the atches/FFs in the sa
are used to old the present counvalue.
F0
Q0
Q
CIN/FCIN
5-5756(F)
Figure 7. Counter Submode
Lattice Semiconductor
15
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
D
Q
REGCOUT
COUT
C
C
In the third submode, multiplier submode, a single
PFU can affect an 8 x 1 bit (4 x 1 for half-ripple mode)
multiply and sum with a partial product (see Figure 8).
The multiplier bit is input at ASWE, and the multiplicand
bits are input at KZ[1], where K7[1] is the most signifi-
cant bit (MSB). KZ[0] contains the partial product (or
other input to be summed) from a previous stage. If
ASWE is logical 1, the multiplicand is added to the par-
tial product. If ASWE is logical 0, 0 is added to the par-
tial product, which is the same as passing the partial
product. CIN/FCIN can bring the carry-in from the less
significant PFUs if the multiplicand is wider than 8 bits,
and COUT/FCOUT holds any carry-out from the multi-
plication, which may then be used as part of the prod-
uct or routed to another PFU in multiplier mode for
multiplicand width expansion.
ASWE
K7[1]
F7
1
0
0
0
0
0
0
0
0
D
D
D
D
D
D
+
+
+
+
+
+
+
Q
Q
Q
Q
Q
Q7
K7[0]
K6[1]
K7
K6
K5
K4
K3
K2
K0
F6
1
0
Q6
K6[0]
K5[1]
1
0
F5
Q5
K5[0]
K4[1]
1
0
K4[0]
K3[1]
0
F
Q3
K0]
K2[1]
F2
1
0
Ripple mode’s fourth submode features equality
comparators.The functions that are explicitly available
are A > B, A ≠ B, and A < B, where the value for A is
input on KZ[0], and the value for B is input on KZ[1].
value of 1 on the carry-out signals valid argument. F
example, a carry-out equal to 1 in AB submode indi-
cates that the value on KZ[0] is greater than or equal to
the value on KZ[1]. Conversely, the functinA < B, A +
B, and A > B are available using the same funcons but
with a 0 output expected. For examleA > B wita 0
output indicates A < B. Table 5 shws each function
and the output expected.
Q2
0]
K1
F1
1
0
Q1
K1[0]
K0[1]
F0
0
Q0
K0[0]
5-5757(F)
Key: = configuion data.
Figure 8. Multiplier Submode
If larger than 8 bits, the cary-out signal can be cas-
caded using fast-carry loc tthe carry-in of any a
cent PFU. The use of this smodcould be show
using Figure 6, except that the IN/FCIN input for t
least significant PFis controlled via confiuration.
Table 5. Rpple Mode Equality Comparatr
Fuions nd Outputs
Equaly
Fnctio
ispLEVER
Submode
Tru, if
Cr-Out Is:
A >
A < B
A ≠ B
A < B
A > B
A = B
A
A ≠
A > B
A < B
A ≠ B
1
1
1
0
0
0
16
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
Memory Mode
The Series 3 PFU can be used to implement a 32 x 4 (128-bit) synchronous, dual-port random access memory
(RAM). A block diagram of a PFU in memory mode is shown in Figure 9. This RAM can also be configured to work
as a single-port memory and because initial values can be loaded into the RAM during onfiguration, it can also be
used as a read-only memory (ROM).
F5[A:D]
READ
4
ADDRESS[4:0]
KZ[3:0]
5
WRITE
CIN(WA4)
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
ADDRESS[4:0]
DIN7(WA3)
DIN5(WA2)
DIN3(WA1)
DIN1(WA0)
DIN6(WD3
DIN4D2)
DIN2(WD1)
DIN0WD0)
F6
F4
F2
F0
D
D
Q
Q
Q
Q
Q6
Q4
Q2
Q0
READ
DATA[]
4
WRE
DATA[3:0]
WRITE
ENABLE
ASWEN)
CE(WE1)
D
EN
RAM CLOCK
S/R
LSR(WPE2)
CLK
5-5969(F)
Figure 9. Memory Mode
The PFU memory mode uses all LUTs and latches/FFs including the ninth FF in its implementation as shown in
Figure 9. The read address is input at the KZ[3:0] and F5[A:D] inputs where KZ[0] is the LSB and F5[A:D] is the
MSB, and the write address is input on CIN (MSB) and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write data is
input on DIN[6, 4, 2, 0], where DIN[6] is the MSB, and read data is available combinatorially on F[6, 4, 2, 0] and
registered on Q[6, 4, 2, 0] with F[6] and Q[6] being the MSB. The write enable signal is input at ASWE, and two
write port enables are input on CE and LSR. The PFU CLK signal is used to synchronously write the data. The
polarities of the clock, write enable, and port enables are all programmable. Write-port enables may be disabled if
they are not to be used.
Lattice Semiconductor
17
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
8-bit data path. Depth expansion is applied to achieve
128 words deep using the 32-word deep PFU memo-
ries. In addition to the PFU in each PLC, the SLIC
(described in the next section) in each PLC is used for
read address decodes and 3-state drivers. The 128 x 8
RAM shown could be made to operate s a single-port
RAM by tying (bit-for-bit) the read ad write addresses.
Programmable Logic Cells (continued)
Data is written to the write data, write address, and
write enable registers on the active edge of the clock,
but data is not written into the RAM until the next clock
edge one-half cycle later. The read port is actually
asynchronous, providing the user with read data very
quickly after setting the read address, but timing is also
provided so that the read port may be treated as fully
synchronous for write then read applications. If the
read and write address lines are tied together (main-
taining MSB to MSB, etc.), then the dual-port RAM
operates as a synchronous single-port RAM. If the
write enable is disabled, and an initial memory contents
is provided at configuration time, the memory acts as a
ROM (the write data and write address ports and write
port enables are not used).
To achieve depth expansion, oe or two of twrite
address bits (generally the MSBs) are rd to the
write port enables as in Fige 1. For 2 bits, the bits
select which 32-word bank of AM othe four available
from a decode of twWPE inputs to be written. Simi-
larly, 2 bits of the red addres are decoded ie
SLIC and are ued tcontrothe 3-state b
through whithe ead data passes.The wrs
is common, wh seprate nibbles for width exn,
across l PLCand the read datus icommon
(agin, with rate nibbles) to all s at te output
othe 3-state buffers.
Wider memories can be created by operating two or
more memory mode PFUs in parallel, all with the same
address and control signals, but each with a different
nibble of data. To increase memory word depth above
32, two or more PLCs can be used. Figure 10 show
128 x 8 dual-port RAM that is implemented in eight
PLCs. This figure demonstrates data path width expan
sion by placing two memories in parallel to chieve an
Fie 10 so shows a neoptionacapability to pro-
vide rad enable for AMsOMs n Series 3 using
e SLIC cell. The read eable will 3-state the read
a bus when inaling the write data and
ead data buss to btied together if desired.
8
WD[7:0]
4
4
4
4
PLC
PLC
PLC
PLC
PFU
PFU
U
PFU
WD]
WD[3:0]
WD[7:4]
WD[3:0]
5
5
5
5
5
5
5
WA
WA
RA
WA
RA
WA
RA
WPE0
WPE1
WPE0
W1
WPE0
WPE1
WPE0
WPE1
W
E
WE
WE
RD[4]
[3:0]
RD[7:4]
RD[3:0]
SLIC
SLIC
SLIC
SLIC
4
4
4
8
RD[7:0]
WE
7
7
WA[6:0]
RA[6:0]
CLK
RE
5-5749(F)
Figure 10. Memory Mode Expansion Example—128 x 8 RAM
18
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The SLIC may also be used to generate PAL-like AND-
OR with optional INVERT (AOI) functions or a decoder
of up to 10 bits. Each group of buffers can feed into an
AND gate (4-input AND for the nibble groups and 2-
input AND for the other two buffers). These AND gates
then feed into a 3-input gate tht can be configured as
either an AND gate or an OR gate. The output of the 3-
input gate is invertible and itput the DEC output
of the SLIC. Figure 1shows the SC in full decoder
mode.
Programmable Logic Cells (continued)
Supplemental Logic and Interconnect Cell
(SLIC)
Each PLC contains a supplemental logic and intercon-
nect cell (SLIC) embedded within the PLC routing, out-
side of the PFU. As its name indicates, the SLIC
performs both logic and interconnect (routing) func-
tions. Its main features are 3-statable, bidirectional
buffers, and a PAL-like decoder capability. Figure 11
shows a diagram of a SLIC with all of its features
shown. All modes of the SLIC are not available at one
time.
The functionality of thSLIC s parsed by the two
nibble-wide roups and t2-bit buffer group. Each of
these groumay orate independeas BIDI buff-
ers (wior hout state capabinibble-
widgrous) or as a PAL/decoder.
Each SLIC contains ten bidirectional (BIDI) buffers,
each buffer capable of driving left and/or right out of the
SLIC. These BIDI buffers are twin-quad in nature and
are segregated into two groups of four (nibbles) and a
third group of two for control. Each of these groups
BIDIs can drive from the left (BLI[9:0]) to the right
(BRO[9:0]), the right (BRI[9:0]) to the left (BLO[0]), or
from the central input (I[9:0]) to the left and/
This central input comes directly from the P
(O[9:0]). Each of the BIDIs in the nibble-wide g
also has a 3-state buffer capability, ut not the thd
group.
As disussed n the memormode sec, if the SLIC
is lacinto one of the mdes where it contains both
buffers nd a decode oAOI nctio(e.g.,
BUF_BUF_DEC mode), te DEoutput can be gated
witthe 3-state int signalhis allows up to a 6-input
ecode (e.g., UF_DC_DC mode) plus the 3-state
input to control tenable/disable of up to four buffers
per SLIC. e 1Figure 16 show several configu-
rationof thSLIC, while Table 6 shows all of the pos-
sibe moes.
Tae 6. SLIC Modes
There is one 3-state control (TRI) for eh SLIC, with
the capability to invert or sable the 3-state control for
each group of four BIDIsSeparat3-state control for
each nibble-wide group is chievale by using the
SLIC’s decoder (EC) output, driven by the grup of
two BIDIs, to conol te 3-state of one BID
while using the TRI gnal o control the 3-
other BIDI nibble. Figu12 and Figure 13
SLIC in bur mode with available -state control from
the RI and DC ignals. If the enre SLIC s acting in
a uffer apacity, the DEC output my be ued to gen-
eraconsant logic 1 (VI) or logic 0 (VLO) signal for
generue.
Mode
#
BUF
[3:0]
BUF
[7:4]
BUF
[9:8]
Mode
1
2
3
4
5
6
7
8
BUFFER
Buffer
Buffer
Buffer
Buffer
BUF_BUF_DEC
BUF_DEC_BUF
Buffer Decoder
Buffer Decoder Buffer
BUF_DEC_DEC Buffer Decoder Decoder
DEC_BUF_BUF Decoder Buffer Buffer
DEC_BUF_DEC Decoder Buffer Decoder
DEC_DEC_BUF Decoder Decoder Buffer
DECODER
Decoder Decoder Decoder
Lattice Semiconductor
19
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
BRI9
I9
BL09
BR09
BRI9
BL09
BR09
BLI9
I9
BLI9
BRI8
I8
B8
B8
BRI8
BL08
BR08
I8
BLI8
BLI8
BRI7
I7
BRI7
BL07
B07
BL07
BR07
I7
BLI7
BRI6
BLI7
BL06
BR06
BRI6
I6
BL06
BR06
I6
BLI6
BRI5
BLI6
BL05
BR05
I5
RI5
I5
05
BR0
BLI5
BRI4
DEC
BLI5
BL04
BR04
I4
BLI4
BI4
I4
BL
04
TRI
BLI4
0/1
0/1
0/1
TRI
DEC
HIGH Z WHEN LOW
0/1
0/1
1
0
DEC
0/1
HIGH WHEN LOW
THIS CAN BE USED
TO GENERATE
A VHI OR VLO
BRI3
I3
B3
03
BLI3
BRI2
I2
BL02
BR02
BRI3
I3
BL03
BLI2
BR03
BLI3
BRI1
I1
BL01
BR01
BRI2
I2
BL02
BR02
BLI1
BLI2
BRI0
I0
BL00
BR
BRI1
I1
BLI0
BL01
BR01
5-5744(F)
BLI1
Figre 11. SLIC All Mdes Diagam
BRI0
I0
BL00
BR00
BLI0
5-5745(F)
Figure 12. Buffer Mode
20
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
BRI9
I9
BL09
BR09
BRI9
BLI9
BLI9
BRI8
BRI8
I8
BL08
BR08
BLI8
BLI8
BRI7
BLI7
RI6
BLI6
RI5
BLI5
BRI4
BLI4
BRI7
I7
BLI7
BL07
BR07
BRI6
I6
BLI6
BL06
BR06
BRI5
I5
BLI5
BL05
BR05
BRI4
I4
BLI4
BL04
BR04
1
DEC
DEC
HIGH Z
WHEN LOW
T
TRI
1
1
1
1
GH Z
WEN LOW
HIGH Z WHEN LOW
1
BRI3
I3
BRI3
I3
BLI3
BRI2
BL03
BR03
BL03
BR03
BLI3
BRI2
I2
BL02
BR
BL02
BR02
I
BLI2
BI1
B
BLI2
BL01
R0
BRI1
I1
BL01
BR01
BLI1
BRI0
I0
BLI0
BL00
BR00
BRI0
I0
BL00
BR00
BLI0
5-5746(F)
5-5747(F)
Figure 13. Bfer-Buffer-Decoder Mode
Figure 14. Buffer-Decoder-Buffer Mode
Lattice Semiconductor
21
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
BRI9
BRI9
BLI9
BRI8
BLI9
BRI8
BLI8
BLI8
BRI7
BLI7
BRI6
BLI6
BRI5
BLI5
BRI4
BLI4
BRI7
BLI7
BRI6
BLI6
RI5
BL
RI4
BLI4
D
DEC
TRI
1
HIGH Z WHEN LW
1
BRI3
B
BR03
I3
BRI3
BLI3
BRI2
BLI2
BRI1
BLI1
BRI0
BLI0
BLI3
BRI2
BL
R02
I2
BLI2
BRI1
BL01
BR01
I1
BLI1
B0
BR00
I0
5-5750(F)
5-5748(F)
Figure 15. Buff-Decoder Mode
Figure 16. Decoder Mode
22
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The eight latches/FFs in a PFU share the clock (CLK)
and options for clock enable (CE), local set/reset (LSR),
and front-end data select (SEL) inputs. When CE is dis-
abled, each latch/FF retains its previous value when
clocked. The clock enable, LSR, and SEL inputs can be
inverted to be active-low.
Programmable Logic Cells (continued)
PLC Latches/Flip-Flops
The eight general-purpose latches/FFs in the PFU can
be used in a variety of configurations. In some cases,
the configuration options apply to all eight latches/FFs in
the PFU and some apply to the latches/FFs on a nib-
ble-wide basis where the ninth FF is considered inde-
pendently. For other options, each latch/FF is
The set/reset operation of te lat/is controlled by
two parameters: reset ode and set/set value. When
the global set/reset (SRN) and al set/reset (LSR)
signals are not asseedhe latch/FF operates normally.
The reset mode is useto seect a synchronous or
asynchronos LSR opern. If synchronous, LSR has
the option tbe enabed only if clock le (CE or
ASWEs ace or fLSR to have er the
clocenae input, thereby setting/re FF inde-
pendnt of tstate of the clck enablclock
enable s supported on FFnot ltches. It is imple-
meny using a 2-input mplexer n the FF input,
with one input being the evioustte of the FF and the
other input being the new dta applied to the FF. The
slect of this 2-inpumultipleer is clock enable (CE or
ASWE), which lects ithr the new data or the previ-
ous state. When thclock enable is inactive, the FF out-
put does nchanghen the clock edge arrives.
independently programmable. In addition, the ninth FF
can be used for a variety of functions.
Table 7 summarizes these latch/FF options. The
latches/FFs can be configured as either positive- or
negative-level sensitive latches, or positive or negative
edge-triggered flip-flops (the ninth register can only be
FF). All latches/FFs in a given PFU share the same
clock, and the clock to these latches/FFs can be
inverted. The input into each latch/FF is from either e
corresponding LUT output (F[7:0]) or the direct data
input (DIN[7:0]). The latch/FF input can also be tied to
logic 1 or to logic 0, which is the default.
Table 7. Configuration RAM Controlled Lat
Flip-Flop Operation
Function
Opons
Common to All Latches/FFiPFU
LSR Operation
Clock Polarity
Asynhronous or synchronous
Noninerted oinverted
Front-end SelectDirct (DIN[7:0]) or from
[7:0])
LSR Priority
ithLSR or CE has
Latch or flip-flo
Latch/FF ode
Enable GSR
GSRN enablor has o effect on
PFU latches/Fs
Sedividully in Each Lch/FF in PFU
Set/Rt Mode Set oet
By roup (Latch/FF[3:Latch/FF7:4], and FF[8])
Cck Enable
LSR Control
E or SWE or none
or none
* Not available for FF
Lattice Semiconductor
23
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The latches/FFs can be configured in three basic
modes:
Programmable Logic Cells (continued)
The GSRN signal is only asynchronous, and it sets/
resets all latches/FFs in the FPGA based upon the set/
reset configuration bit for each latch/FF. The set/reset
value determines whether GSRN and LSR are set or
reset inputs. The set/reset value is independent for
each latch/FF. A new option is available to disable the
GSRN function per PFU after initial device configura-
tion.
1. Local synchronous set/reset: the input into the
PFU’s LSR port is used to synchronously set or
reset each latch/FF.
2. Local asynchronous set/reset: thinput into LSR
asynchronously sets or resets ech tchF.
3. Latch/FF with front-end seect, LSR eithsynchro-
nous or asynchronous: e daselect signal
selects the input into the hes/Fs between the
LUT output and diect data i
The latch/FF can be configured to have a data front-
end select. Two data inputs are possible in the front-
end select mode, with the SEL signal used to select
which data input is used. The data input into each
latch/FF is from the output of its associated LUT, F[7:0],
or direct from DIN[7:0], bypassing the LUT. In the front-
end data select mode, both signals are available to the
latches/FFs.
For all three modeseach lath/FF can be indepen-
dently programmed eitheset or reset. F
provides the ogifunctility of the front-
global set/ret, anlocal set/reset oeration
The nintPFU F, which is generay asociated with
regstering thrry-out signal in ripmodfunc-
ns, cn be used as a general-rposF. It is only
aFand is not capable obeing cfigured as a latch.
Becuse he ninth FF is not ssociad with an LUT,
ere is no front-end datseleche data input to the
th FF is limited the Cinput, logic 1, logic 0, or
e carry-out in rippand half-logic modes.
If either or both of these inputs is unused or is unavail-
able, the latch/FF data input can be tied to a logic 0 or
logic 1 instead (the default is logic 0).
CE/ASWE
CE
SEL
CE/ASWE
CE/ASWE
F
DIN
LOGIC 1
LOGIC 0
F
DIN
F
DIN
D
Q
D
Q
Q
D
DIN
LOGIC 1
LOGIC 1
LOGIC 0
LOGIC 0
set
LSR
_ret
CLK
GSRN
LR
GSRN
LSR
CLK
SET RESET
CLK
SET RESET
SET RESET
GSRN
CD
CD
Key: C nfiguration data
Figure 17. Latch/FF Set/Reset Configurations
24
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
PLC Routing Resources
INDEPENDENT CIP
B
Generally, the ispLEVER Development System is used
to automatically route interconnections. Interactive
routing with the ispLEVER design editor (EPIC) is also
available for design optimization. To use EPIC for inter-
active layout, an understanding of the routing
CD
=
A
B
resources is needed and is provided in this section.
TIPLEXD CIP
The routing resources consist of switching circuitry and
metal interconnect segments. Generally, the metal
lines which carry the signals are designated as routing
segments. The switching circuitry connects the routing
segments, providing one or more of three basic func-
tions: signal switching, amplification, and isolation. A
net running from a PFU or PIC output (source) to a
PLC or PIC input (destination) consists of one or more
routing segments, connected by switching circuitry
called configurable interconnect points (CIPs).
CD
A
C
A
C
O
The following sections discuss PLC, PIC, and uad
routing resources. This section discusses t
switching circuitry, intra-PLC routing, inter-PL,
and clock distribution.
Key: C = con .
5-5973(C)
Figu18. Configurable Interconnect Point
Configurable Interconnect Ponts
The process of connecting ting segmnts uses
three basic types of switcing circuits: two types of con-
figurable interconnect pos (CIPand bidirectio
buffers (BIDIs). The basic emenin CIPs is one or
more pass transtors, ach controlled by a ra-
tion RAM bit. The types of CIPs are th
exclusive (or multipleedCIP and the inde
CIP.
3-Statale Bidirectional Buffers
directional buffers, previously described in the SLIC
section of the programmable logic cell discussion, pro-
vide isolation as well as amplification for signals routed
a long distance. Bidirectional buffers are also used to
route signals diagonally in the PLC (described later in
the subsection entitled Intra-PLC Routing), and BIDIs
can be used to indirectly route signals through the
switching routing (xSW) segments. Any number from
zero to ten BIDIs can be used in a given PLC.
A mtually exuse set of CIPs cntains to or more
Cs, oy one of which can be on a timAn inde-
pennt CIP has no such estrictions and can be on
indepdnt of the state otr CPs. Figure 18
ws an example of oth types oCIPs.
Lattice Semiconductor
25
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
General Routing Structure
Routing resources in Series 3 FPGAs generally consist of routing segments in groups of ten, with varying lengths
and connectivity to logic and other routing resources.The varying lengths of routing segments provides a hierarchy
of routing capability from chip-length routes to routes within a PLC. The hierarchical nature of throuting provides
the ispLEVER development tools with the necessary resources to route a design completely ad to mize the
routing for system speed while reducing the overall power required by the device.
Within each group of ten routing segments there is an equivalency of connectivity betwen pars of segments.
These pairs are segments: [0, 4] and [1, 5] and [2, 6] and [3, 7] and [8, 9]. The equivaley n connectivity ensures
that signals on either segment in a pair have the same capability to get to a given stinatn. Tis, in turn, allows
for signal distribution from a source to varying destinations without using speciarouting. It alsprovides for routing
flexibility by ensuring that one segment position will not become so congested ato preclde routing a buroup
of signals and allows easy connectivity from either of the twin quads in a srce FU to either of the tin
any destination PFU.
Having ten segments in a group is significant in that it provides for routing byte f data and twcontrol sigls or
parity. Due to the equivalent pairs of segments, this can also be viewas outing two nibbles acwith a control
signal. Figure 19 is an overview of the routing for a single PLC
hxH[9:0]
hx1U[9:0]
hCK
FC
FC
SLL[9:0]
SLL[9:0]
PFU
SLR[9
C
OUTPUT
SWITCHING
SUR[9:0]
LCK
hx1B[9:0]
hx5[9:0]
hxL[9:0]
BR[9:0]
2
5
BR[9:0]
SUL[9:0]
SUL[9:0]
FC
BL[9:0]
KEY: CONFIGURABLE SIGNAL LINE BREAKS
LINE-BY-LINE
2
2 OF 5
5
5-5766(F)
Figure 19. Single PLC View of Inter-PLC Route Segments
26
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
ally labeled for the upper-left, upper-right, lower-left,
and lower-right sections of the PFUs, respectively. The
xSW routing segments connect to the PFU inputs and
outputs as well as the BIDI routing segments, to be
described later. They also connect to both the horizon-
tal and vertical x1 and x5 routig segments (inter-PLC
routing resources, describelater) in their specific cor-
ner. xSW segments can be d for st connections
between adjacent PLs or PICs witout requiring the
use of inter-PLC roting sources. This capability not
only increases signaeed oadjacent PLC routing,
but also redues routincogestion on the principal
inter-PLC ruting resources. The SLL and SUR seg-
ments comne to prvide connectie PLCs to
the left d rigof he current PLand SUL
segents mbine to provide onnethe PLCs
above and beow the currenPLC.
Programmable Logic Cells (continued)
Intra-PLC Routing
The function of the intra-PLC routing resources is to
connect the PFU’s input and output ports to the routing
resources used for entry to and exit from the PLC. This
routing provides PFU feedback, corner turning, or
switching from one type of routing resource to another.
Flexible Input Structure (FINS)
The flexible input switching structure (FINS) in each
PLC of the ORCA Series 3 provides for the flexibility of
a crossbar switch from the routing resources to the
PFU inputs while taking advantage of the routability of
shared inputs. Connectivity between the PLC routing
resources and the PFU inputs is provided in two
stages. The primary FINS switch has 50 inputs that
connect the PLC routing to the 35 inputs on the sec-
ondary switch. The outputs of the second switch co
nect to the 50 PFU inputs. The switches are
Fast es on switching sents to diagonally adja-
cent PLCs/PICs are posible ung the BIDI routing
segments (discussed belo) and the SLL and SLR
sitching segmentsThe BR BIDI routing segments
combine with thSUL wihing segments of the PLC
below and to the rht of the current PLC to connect to
that PLC. TBL BI routing segments combine with
the SLswitcng segments of the PLC above and to
thright othe current PLC to connect to that PLC.
Thse fast dgonal connections provide a great
amot of flexibility in routing congested areas of logic
and in shifting data on a per-PLC basis such as per-
rming implicit multiplications/divisions in routing
btween functional logic elements.
implemented to provide connectivity for busels
and individual connections.
PFU Output Switching
The PFU outputs are switched otPLC routing
resources via the PFU output multipler (OMUX). The
PFU output switching segmens from the output multi-
plexer provide ten conneions to the PLC routing out
of 18 possible PFU outpu(F[7:0Q[7:0], DOUT,
REGCOUT).Thesoutput stchng segments connet
segment for segent tthe SUR, SUL, SLLL
switching segmenescried below (e.g.
nects only to SUR4, t UR5). The outpu
segments lso feed directly into the SLIC on -
mentby-segent asis. This conctivity is also
decribebelo
Switching routing segments are also the chief means
by which signals are transferred between the inter-PLC
routing resources and the PFU. Each set of switching
segments has connectivity to the x1 routing segments,
and there is varying connectivity to the x5, xH, and xL
inter-PLC routing segments. Detailed information on
switching segment/inter-PLC routing connectivity is
provided later in this section in the Inter-PLC Routing
Resources subsection.
Switing Routing Segents W)
he are four sets of witching roting segments in
eacPLC. Each set consts of ten switching elements:
UL[9:0], SURL[9:, and SLR[9:0], tradition-
Lattice Semiconductor
27
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Control Signal and Fast-Carry Routing
Programmable Logic Cells (continued)
PFU control signal and the fast-carry routing are per-
formed using the FINS structure and several dedicated
routing paths. The fast-carry (FC) routing resources
consist of a dedicated bidirectional segment between
each orthogonal pair of PLCs. This means that a fast-
carry can go to or come from each LC te right or
left, above or below the subject PLC. The FIS struc-
ture is used to control the swtching of te fast-carry
paths between the fast-carrinpt (FCIN) and fast-
carry output (FCOUT) ports ohe PU.
BIDI Routing and SLIC Connectivity
The SLIC is connected to the rest of the PLC by the
bidirectional (BIDI) routing segments and the PFU out-
put switching segments coming from the PFU output
multiplexer. The BIDI routing segments (xBID) are
labeled as BL for BIDI-left and BR for BIDI-right. Each
set of BR and BL xBID segments is composed of ten
bidirectional lines (note that these lines are diagramed
as ten input lines to the SLIC and ten output lines from
the SLIC that can be used in a mutually exclusive fash-
ion). Because the SLIC is connected directly to the out-
puts of the PFU, it provides great flexibility in routing via
the xBID segments.The PFU routing segments, O[9:0],
only connect to their respective line in the SLL, SUL,
SUR, and SLR switching segment groups. That is, O9
only connects to SLL9, SUL9, SUR9, and SLR9. The
BIDI lines provide the capability to connect to the other
member of the routing set. That means, for example,
that O9 can be routed to BR8 or BL8. This connectivity
can be used as a means to distribute or gather sign
on intra-PLC routing without disturbing inter-PLC
resources. As described in the Switching Routing Seg-
ments subsection, the BIDI routing segmens are also
used for routes to a diagonally adjacent F.
The PFU control ints (CE, SEL, LSR, ASWE) and
CIN can be reached ia the FNS by two speing
segments, E1 aE2. he 1 routing seg
vides connevity tween all of the xID ro-
ments and the FINS. is unidirectioal from the DI
routing to e FS. E1 also provideconectivity to the
PFU clock inpuia FINS for a cal cck sinal. The
2 sement connects the SLIC DC outt to the FINS
ao a grup of CIPS thprovide idirectional con-
nectity with all of the IDI rting egments. This
ows the DEC signal to e used in the PFU and/or
ted on the BIDme. It also allows signals to
e routed to thPFU on the xBID segments if the SLIC
DEC outpuis nused
There iao a dedicted routing segment from the
FINS to the SIC TRI input used for BIDI buffer 3-state
contr.
In addition to the intra-PLC connections, the xBD and
output switching segments also hve connectivity to
the x1, x5, and xL inter-PLC routg resoues, provid-
ing an alternate routing path athehan ung PLC
xSW segments.These conections also provide a path
to the 3-state buffers in tSIC without encumbe
the xSW segments. In this nnebuffering or 3-
control can be added to inter-C routing without di
turbing local functioality within a PFU.
28
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
x1 Routing Segments. There are a total of 40 x1 rout-
ing segments per PLC: 20 vertical and 20 horizontal.
Each of these are subdivided into two, 10-bit wide
buses: hx1T[9:0], hx1B[9:0], vx1L[9:0], and vx1R[9:0].
An x1 segment is one PLC long. If a signal net is longer
than one PLC, an x1 segment an be lengthened to n
times its length by turning n n – 1 CIPs. A signal is
routed onto an x1 route segt via he switching rout-
ing segments or BIDI outing segmnts which also
allows the x1 route egmnt to be connected to other
inter-PLC segments f ifferet lengths. Corner turning
between x1 sgments iprvided through direct con-
nections, xW segments, and xBID segments.
Programmable Logic Cells (continued)
Inter-PLC Routing Resources
The inter-PLC routing is used to route signals between
PLCs. The routing segments occur in groups of ten,
and differ in the numbers of PLCs spanned. The x1
routing segments span one PLC, the x5 routing seg-
ments span five PLCs, the xH routing segments span
one-half the width (height) of the PLC array, and the xL
routing segments span the width (height) of the PLC
array. All types of routing segments run in both horizon-
tal and vertical directions.
Table 8 shows the groups of inter-PLC routing seg-
ments in each PLC. In the table, there are two rows/col-
umns for x1 lines.They are differentiated by a T for top,
B for bottom, L for left, and R for right. In the ispLEVER
design editor representation, the horizontal x1 routing
segments are located above and below the PFU. The
two groups of vertical segments are located on the ft
side of the PFU. The xL and x5 routing segments only
run below and to the left of the PFU, while thg-
ments only run above and to the right of th
indexes specify individual routing segments
group. For example, the vx5[2] segment runs veally
to the left of the PFU, spans five PCs, and is the third
line in the 10-bit wide group.
x5 Roug Smnts. There are ten x5
routig segents per PLC. One set () runs ver-
ticallyand thother (hx5[9]) runs horntally. Each
xsegent traverses five Cs before it is broken by a
CIP. Twx5 segments eacroup break in each
PLC. The two that break e in aequivalent pair; for
exmple, x5[0] anx5[4]. Tx5 segments that break
hift by one at he nePLCFor example, if hx5[0] and
hx5[4] are brokeat the current PLC, hx5[1] and hx5[5]
will be brt tPLC to the right of the current
PLC. ere e direct connections to the BIDI routing
semenin thPLC at which the x5 segments break,
both sids of the break. Signal corner turning is
enaed by CIPs in each PLC that allow the broken x5
segmets to directly connect to the broken x5 seg-
ments that run in the orthogonal direction. x5 corner
ning can also be accomplished via the xSW and
xBID segments in a PLC. In addition, the x5 segments
are connected to the FINS and PFU outputs on a bit-
by-bit basis by the xSW segments. x5 segments can be
connected for signal runs in multiples of five PLCs, or
they can be combined with x1 and xH routing segments
for runs of varying distances.
PLCs are arranged like tileon the ORCdevice.
Breaks in routing occur ahe middle of the tile (e.g., x1
lines break in the middle each PC) and run ac
tiles until the next eak.
Table 8. Inter-PLouting Resources
Horizntal
Routin
egments
ertical
Routing
Segments
Dist
Spanned
hxU[9:0]
h1B[:0]
hx5[9:0]
hx5[9:0]
hxL[9:0]
hxH[9:0]
hCLK
vx1R:]
vx[9:0
vx5[9:0]
v[9:0]
vxL[0]
H[9:0]
vCLK
ne PLC
One PLC
Five PLCs
Five PLCs
PLC Array
1/2 PLC Array
PLC Array
Figure 20 provides a global view of inter-PLC routing
resources across multiple PLCs.
Lattice Semiconductor
29
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
hx
hx1[9:0
hCLK
10
10
10
10
10
10
10
10
10
PFU
2
PFU
2
PFU
2
2
2
2
2
2
2
2
2
2
SLIC
SLIC
SLIC
SLIC
SL
SLIC
SLIC
SLIC
SLIC
hx1[9:0]
hx5
hxL[9:0]
10
10
10
hxH[9:0
hx1[9:0]
hCLK
PFU
2
2
FU
2
hx1[9:0]
hx5[9:0]
hxL[9:0]
10
10
10
hxH[9:0]
hx1[9:0]
hCLK
PFU
2
U
2
PFU
2
hx1[9:0]
hx5[9:0]
hxL[9:0]
10
10
10
KEY: CONFIGURABLE SIGNAL-L
LINE-BY-LINE
2
2 OF 10
10
PLC BOUNDARY
5-5767(F)
Figure 20. Multiple PLC View of Inter-PLC Routing
30
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The clock routing segments are designed to be a clock
spine. In each PLC, there is a fast connection available
from the clock segment to a long-line driver (described
earlier). With this connection, one of the clock routing
segments in each PLC can be used to drive one of the
ten xL routing segments perpedicular to it, which, in
turn, creates a clock spine ee. This feature is dis-
cussed in detail in the Cloctribuon Network sec-
tion.
Programmable Logic Cells (continued)
xL Routing Lines. The xL routing lines run vertically
and horizontally the height and width of the array,
respectively. There are a total of 20 xL routing lines per
PLC: ten horizontal (hxL[9:0]) and ten vertical
(vxL[9:0]). Each of the xL lines connects to the PIC
routing at either end. The xL lines are intended prima-
rily for global signals that must travel long distances
and require minimum delay and/or skew, such as
clocks or 3-state buses.
Special connectivits povided in each PLC to connect
the clock enable sign(CE and ASWE) and the LSR
signal to the clock netwofor fast global control signal
distributionCE and SWE have a spl connection
to the rizoal clospine, and special
conectioto the vertical clock spinows both
signato bouted globally ithin the e PLC, if
desirehowever, this will nsue some of the
resos available for clock nal routing.
Each xL line (also called a long line) drives a buffer in
each PLC that can drive onto the horizontal and verti-
cal local clock routing segments (lCLK) in the PLC.
Also, two out of each group of ten xL segments in each
PLC can be driven by a buffer attached to a clock spine
(described later) allowing local distribution of global
clock signals. More general-purpose connections to the
long lines can be made through the xBID segments a
PLC. Each long line is connected to an xBID segme
on a bit-by-bit basis. These BIDI connections aw cor-
ner turning from horizontal to vertical long l
connection between long lines and x1 or x5 .
If using these spines, the lock able signal must
coe from the rigor left ege of the device, and the
SR signal mut comfrom he top or bottom of the
device due to thehorizontal and vertical connectivity,
respectivthock network.
xH Routing Segments. Ten by-hal(xH) routing eg-
ments run horizontally (hxH[9:0]aten xH routing
segments run vertically (vxH[9:0]) in ech row and col-
umn in the array. These roing segmenttravel a dis-
tance of one-half the PLC array before being broken in
the middle of the array in e interqad area (discu
later). They also conect at e priphery of the FPG
to the PICs, like e xL ines. xH routing segcon-
nect to the PLCs oby swtching segmee
intended for fast signierconnect.
Miimizg Roting Delay
ThCIP is aactive element used to connect two rout-
ing sments. As an active element, it adds signifi-
cantly to the resistance and capacitance of a routing
etwork (net), thus increasing the net’s delay. The
avantage of the x1 segment over an x5 segment is
routing flexibility. A net from one PLC to the next is eas-
ily routed by using x1 routing segments. As more CIPs
are added to a net, the delay increases. To increase
speed, routes that are greater than two PLCs away are
routed on the x5 routing segments because a CIP is
located only in every fifth PLC. A net that spans eight
PLCs requires seven x1 routing segments and six
CIPs. Using x5 routing segments, the same net uses
two routing segments and one CIP.
Cloc(and lobaCE and LSR) outing Segments.
Foa very fast d low-skew clock or otheglobal sig-
natre), clock routing segents run e ntire height
and dth the PLC arraThere two clock routing
segmens per PLC: one horizontal CLK) and one ver-
ticavCLK). The sourcfor thse clock routing seg-
mets can be anthe I/buffers in the PIC, the
Series 3 Exprputs, user logic, or the pro-
grammable cloer (PCM).The horizontal clock
routing segments K) are alternately driven by the
left and right PICs. The vertical clock routing segments
(vCLK) are alternately driven by the top and bottom
PICs.
Lattice Semiconductor
31
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
J. These are the ten switched output routing segments
from the PFU. They connect to the PLC switching
segments and are input to the SLIC.
Programmable Logic Cells (continued)
PLC Architectural Description
K. These lines deliver the auxiliary signals clock enable
(CE), local set/reset (LSR), front-end select (SEL),
add/subtract/write enable (ASWE), s well as the
carry signals (CIN and FCIN) to he latches/FFs.
Figure 21 is an architectural drawing of the PLC (as
seen in ispLEVER) that reflects the PFU, the routing
segments, and the CIPs. A discussion of each of the
letters in the drawing follows.
L. This is the local clock buffer. Any the hizontal
and vertical xL lines can dve the clock iput of the
PLC latches/FFs.The clk roing segments (vCLK
and hCLK) and multiplexedrivers are used to con-
nect to the xL routg segmets or low-skew, low-
delay global signls.
A. These are switching routing segments (xSW) that
give the router flexibility. In general switching theory,
the more levels of indirection there are in the routing,
the more routable the network is. The xSW seg-
ments can also connect to the xSW lines in adjacent
PLCs.
M.These routing sements ae used to rout-
carry signal trom e eighboring foue
carry-out OUand registered cry-ou
COUT) can also brouted out othe PFU.
B. These CIPs connect the x1 routing. These are
located in the middle of the PLC to allow the block to
connect to either the left end of the horizontal x1
segment from the right or the right end of the hori-
zontal x1 segment from the left, or both. By symme-
try, the same principle is used in the vertical
direction.
N. This is tEcontrol routing seget. It runs from
the SLIC DEC output to the INS ad alo provides
conectivity to all xBID segmes.
O. e xH routing segmentrun onhalf the length
(wh) of the array fore ing broken by a CIP.
C. This set of CIPs is used to connect the x1 and x5
nets to the xSW segments or to other x1 and x5
nets. The CIPs on the major diagonal allow data to
be transmitted on a bit-by-bit basis from xnets to
the xSW segments and between the xnd x5 nets.
These CIPs conect thxH segments to the xSW
segments.
Q.The xBID segents re used to connect the SLIC to
the xSsegmets, x1 segments, x5 segments, and
xL less well as providing for diagonal PLC to
PLC conntions.
D. This structure is the supplemental logic aninter-
connect cell, or SLIC. It contains tatable birec-
tional buffers and logic for builng decoders and
AND-OR-INVERT type structus.
R. Thee CIPs provide connections from the xBID seg-
eno the E1/E2 routing segments that feed PFU
control inputs CE, LSR, CIN, ASWE, SEL, and the
cck input. Alternatively, these CIPs connect the
BIDI lines to the decoder (DEC) output of the SLIC,
for routing the DEC signal.
E. These are the primary ad seconary lements of
the flexible input strucre or FINS. FINS is a swit
matrix that provides hignnectvity while reta
routing capability. FINS alinludes feedback
paths for softwed LUT implementation.
S. These are clock spines (vCLK and hCLK) with the
multiplexers and drivers to connect to the xL routing
segments.
F. This is the FU ouput sitch matrix. It a complex
switch ntwork whicike the FINS at tinput, ro-
vides hh cnnectivity and maints roubilit
T. These CIPs connect xBID segments to switching
segments in diagonally and orthogonally adjacent
PFUs.
G.Thset of IPs allows an xBID segto transfer
signal to/from xSW segments on each ide. The
Is caaccess the PFU though he xSW seg-
ments. Tese CIPs allata tbe routed through
the BIDIs for amplifi3-stae control and con-
tinue to another PLo provide an alterna-
tive routing resource tve routability.
U. These CIPs connect xSW segments to the PFU out-
put segments.
V. These CIPS connect xSW segments in orthogonally
adjacent PFUs.
W.This is the SLIC 3-state control routing segment
H. These CIPs are used to transfer data from/to the
xBID segments to/from the x1 and xL routing seg-
ments.These CIPs have been optimized to allow the
BIDI buffers to drive the loads usually seen when
using each type of routing segment.
from the FINS to the SLIC 3-state control.
X. This is the E1 control routing segment. It provides a
PFU input path from all xBID segments.
Y. These CIPs are used to select which xBID segments
are connected to the E1/E2 signal as described in
(R).
I. Clock input to PFU.
32
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Logic Cells (continued)
P
A
M
O
H
B
C
C
C
S
M
M
E
E
O
A
G
A
A
C
C
A
A
B
PFU
A
C
Q
B
D
N
K
W
H
H
SLIC
F
OPUT
J
U
U
ITCHING
P
V
C
X
R
R
A
L
C
C
C
H
B
T
H
G
L
Q
Q
Q
H
Q
T
M
S
A
5-5758(F)
Figure 21. PLC Architecture
Lattice Semiconductor
33
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
PICs in the Series 3 FPGAs have significant local rout-
ing resources, similar to routing in the PLCs. This new
routing increases the ability to fix user pinouts prior to
placement and routing of a design and still maintain
routability. The flexibility provided by the routing also
provides for increased signal speed duto a greater
variety of signal paths possible.
Programmable Input/Output Cells
The programmable input/output cells (PICs) are
located along the perimeter of the device. The PIC’s
name is represented by a two-letter designation to indi-
cate on which side of the device it is located followed
by a number to indicate in which row or column it is
located. The first letter, P, designates that the cell is a
PIC and not a PLC.The second letter indicates the side
of the array where the PIC is located. The four sides
are left (L), right (R), top (T), and bottom (B). The indi-
vidual I/O pad is indicated by a single letter (either A, B,
C, or D) placed at the end of the PIC name. As an
example, PL10A indicates a pad located on the left
side of the array in the tenth row.
Included in the PIC routing is a ast path from the input
pins to the SLICs in each of he three aent PLCs
(one orthogonal and two digonl). This feature allows
for input signals to be very quily prcessed by the
SLIC decoder functin and used -chip or sent back
off of the FPGA. Alsnew to he Series 3 PIOe
latches and FFand ptions or using fast
clocks calleExpssCLKs. These features
discussed in ubseqent sections.
Each PIC interfaces to four bond pads and contains the
necessary routing resources to provide an interface
between I/O pads and the PLCs. Each PIC is com-
posed of four programmable I/Os (PIOs) and significant
routing resources. Each PIO contains input buffers,
output buffers, routing resources, latches/FFs, and
logic and can be configured as an input, output, or
bidirectional I/O.
A diagram of a ngle PIO (one of fur ia PIC) is
shwn in Figur2. Table 9 prides oveview of
e prgrammable functions in an /O ce
PIO LOGIC
AND
NAND
OR
NOR
XOR
NOR
PULODE
UP
PUX
T1OUTREG
UT2OUEG
T1T2
OWN
NONE
CLKIN
IN1
OUT1
OUT2
D0
D1 Q
0
PD
Q
D
CK
PAD
ECLK
SCLK
NORMAL
INVERTED
CK
SP
SD
LSR
LEVEL MODE
ECLK
SCLK
CK
SP
TTL
CMOS
INREGMODE
1
SET
SE
BUFFER
MODE
LATCHFF
LATCH
FF
CE
D0 Q
CK
RESET
SET
FAST
SLEW
SINK
1
IN2
LSR
LSR
CE_OVERR
LSR_O
ASY
0
ENABLE_GSR
DISABLE_GSR
5-5805(F).c
Figure 22. OR3C/Txxx Programmable Input/Output (PIO) Image from ispLEVER
34
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
5 V Tolerant I/O
Programmable Input/Output Cells
(continued)
The I/O on the OR3Txxx Series devices allow intercon-
nection to both 3.3 V and 5 V devices (selectable on a
per-pin basis).
Table 9. PIO Options
Input
Input Level
Option
The OR3Txxx devices will drve the pin to the 3.3 V lev-
els when the output buffer ena. If the other
device being driven by he OR3Txxx evice has TTL-
compatible inputs, thn the deve will not dissipate
much input buffer pwerThis is because the OR3Txxx
output is being driven a hiher level than the TTL
level require. If the otheevice has a CMOS-compat-
ible input, te amounof input buffer per will also be
small. oth othese ower values dent upon
the iput uffer caracteristics of thice when
driveat thOR3Txxx outpubuffer vlevels.
TTL, OR3Cxx only
CMOS, OR3Cxx or OR3Txxx
3.3 V PCI Compliant, OR3Txxx
5 V PCI Compliant, OR3Txxx
Input Speed
Float Value
Fast, Delayed
Pull-up, Pull-down, None
Register Mode
Latch, FF, Fast Zero Hold FF,
None (direct input)
Clock Sense
Inverted, Noninverted
Input Selection
Input 1, Input 2, Clock Input
e O3Txxx device has ternl programmable pull-
ups oe I/O buffers. hese ull-up voltages are
always referenced to VDD and aalways sufficient to
pulthe input buffof the O3Txxx device to a high
tate. The pin n the R3Tx device will be at a level
1.0 V below VDD minimm of 2.0 V with a minimum
VDD of 3.Thioltage is sufficient to pull the exter-
nal piup to a 3.3 V CMOS high input level (1.8 V, min)
or TTL igh iput level (2.0 V, min) in a 5 V tolerant
tem. Thefore, in a 5 V tolerant system using 5 V
CMS parts, care must be taken to evaluate the use of
these ull-ups to pull the pin of the OR3Txxx device to
a typical 5 V CMOS high input level (2.2 V, min).
Output
Option
Output Drive
Current
12 mA/6 mA or 6 mA/3 mA
Output Function
Output Speed
Output Source
Output Sense
3-State Sense
FF Clocking
Normal, Fast Open D
Fast, Slewlim, Sinklim
FF Direct-out, General Rog
Active-hightive-low
Active-high, Acti-low (3-state)
ExpessCLK, System Clock
Invted, Nonverted
Clock Sense
Logic Options
See Tle 0.
PCI Compliant I/O
I/O Control
Option
Clock Enable
Acte-high, Active-l
Always Enab
The I/O on the OR3Txxx Series devices allows compli-
ance with PCI Local Bus (Rev. 2.2) 5 V and 3.3 V sig-
naling environments. The signaling environment used
for each input buffer can be selected on a per-pin
basis. The selection provides the appropriate I/O
clamping diodes for PCI compliance. Choosing an IBT
input buffer will provide PCI compliance in OR3Txxx
devices. OR3Cxx devices have PCI Local Bus compli-
ant I/Os for 5 V signaling.
Set/eset Lvel
Active-high, ctive-low,
No Local Rset
Seset Tpe
Syncronous, Achronous
Set/Rst Priority CE veLSRLSR over CE
GR Control
able GSRDisable GSR
Lattice Semiconductor
35
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Warning: During configuration, all OR3Txxx inputs
have internal pull-ups enabled. If these inputs are
driven to 5 V, they will draw substantial current
(≅ 5 mA). This is due to the fact that the inputs are
pulled up to 3 V.
Programmable Input/Output Cells
(continued)
Inputs
As outlined earlier in Table 9, there are six major
options on the PIO inputs that can be selected in the
ispLEVER tools. For OR3Cxx devices, the inputs and
bidirectional buffers can be configured as either TTL or
CMOS compatible. OR3Txxx devices support CMOS
levels only for input or bidirectional buffers, have 5 V
tolerant I/Os as previously explained, but can optionally
be selected on a pin-by-pin basis to be PCI bus 3.3 V
signaling compliant (PCI bus 5 V signaling compliance
occurs in 5 V tolerant operation). The default buffer
upon powerup for the unused sites is 5 V tolerant/5 V
PCI compliant. Consult the ORCA macro library, Series
3 I/O cells, for the appropriate buffers. Inputs may have
a pull-up or pull-down resistor selected on an input for
signal stabilization and power management. Input sig-
nals in a PIO can be passed to PIC routing on any of
three paths, two general signal paths into PIC routin
and/or a fast route into the clock routing system.
Floating inputs increase power consmption, produce
oscillations, and increase system nise. OR3Cxx
inputs have a typical hysteresis of approximely 280
mV (200 mV for the OR3Txx) to reducnsitivity to
input noise. The PIC contais inut circuitry which pro-
vides protection against latch-and electrostatic dis-
charge.
The other features othe PIO nputs relate tw
latch/FF structuin thinpt path. As sh
Figure 23, thinpus optionally passeto a or
latch/register air. Thse structures an operate the
modes lisd in able 9. In latch me, te input signal
is d to a latch at is clocked a sym clck signal.
he clck may be inverted or nonvertefrom its
se in thPIC routing. Tere is alo a local set/reset
signto the latch from the Proutg. The senses of
ese signals are also prgrammable as well as the
pability to enabise the global set/reset sig-
al and select he sereset priority. The same control
signals maalso e usd to control the input latch/FF
when it ionfigureas a FF instead of a latch, with the
addition of other control signal used as a clock
enae.
There is also a programmable delay available on the
input. When enabled, this delay affects the I1 and IN2
signals of each PIO, but not the clock inut. he delay
allows any signal to have a guaranteed zero hd time
when input. This feature is discussd subsequeny.
Inputs should have transition timeof less han 500 ns
and should not be left floatin. If anpin is not used, it
is 3-stated with an internpull-p resistor enabled
automatically after configatn.
36
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells (continued)
Zero-Hold Input
There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from
the input pin, data can be either registered or latched with guaranteed zero-hold time in the PIO using a system
clock.
To guarantee zero hold, the system clock spine structure must be used for clocking, as wll be dcussed later. The
fast zero-hold mode of the PIO input takes advantage of the latch/FF combination and sourcethe input FF data
from a dedicated latch that is clocked by the ExpressCLK from the PIC. The EressLK is a clock from a dedi-
cated input pin designed for fast, low-skew operation at the I/Os and is describeore flly in the Clock Distribu-
tion Network and PIC Interquad (MID) Routing sections that follow. The ombinatiooExpressCLK latch and
system clock FF guarantees a zero-hold capture of input data in the PIFF, while at the same time reducing input
setup time. Figure 23 shows a schematic of the fast-capture latch/FF aa samle timing diag
FF
LTCH
DAA UT
TO PC ROUTING
INPUT DATA
D
D
Q
O
I
EXPRESSCLK
K
1
CE
S
O
I
SYSTEM CLK
CLOCK ENABLE
LOCAL SET/REET
XPRESCLK
SYECLK
INPUT DATA
B
C
D
E
E
D
A
B
C
D
QL
FF
A
B
C
5-5974(F)
Note: CE and LSR signas not shown.
Figure 23. Fast-Capture Latch and Timing
Lattice Semiconductor
37
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells (continued)
Input Demultiplexing
The combination of input register capability and the two inputs, IN1 and IN2, from each PIO to the internal routing
provides for input signal demultiplexing without any additional resources. Figure 24 shows the input configuration
and general timing for demultiplexing a multiplexed address and data signal. The PIO input signl is sent to both
the input latch and directly to IN2. The signal is latched on the falling edge of the clock and outpt toug at IN1.
The address and data are then both available at the rising edge of the system clock. Thessignals may be regis-
tered or otherwise processed in the PLCs at that clock edge. Figure 24 also shows the ossibe use of the SLIC
decoder to perform an address decode to enable which registers are to receive the inpuda. Although the timing
shown is for using the input register as a latch, it may also be used in the same was an F. Aso note that the
signals found in PIO inputs IN1 and IN2 can be interchanged.
OTHEADDSS
LES
PIO
PLC
DEC
N1
2
D
Q
PAD
SLIC
SCLK
D
Q
E
SC
O INPUT
DATA1 ADDDATADR3 DATA3 ADDR4 DATA4 ADDR5
PIO LATCH
OUPUT
ADDR
TA0
AR
DATA1
ADDR3
DATA2
ADDR4
DATA3
ADDR5
DATA4
PLC FF
OUTPUT
5-5798(F)
Figure 24. PIO Input Demultiplexing
38
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
An FF has been added to the output path of the PIO.
The register has a local set/reset and clock enable.The
LSR has the option to be synchronous or asynchro-
nous and have priority set as clock enable over LSR or
LSR over clock enable. Clocking to the output FF can
come from either the system cck or the ExpressCLK
associated with the PIC. Thinput to the FF can come
from either OUT1 or OUT2, t can e tied to VDD or
GND. Additionally, the input to the Fcan be inverted.
Programmable Input/Output Cells
(continued)
Outputs
The PIC’s output drivers have programmable drive
capability and slew rates. Three propagation delays
(fast, slewlim, sinklim) are available on output drivers.
The sinklim mode has the longest propagation delay
and is used to minimize system noise and minimize
power consumption. The fast and slewlim modes allow
critical timing to be met.
Output Multiplexin
The Series PIO output F can be combined with the
new PIO loc block perform output a multiplexing
with no PLC sourcs required. Tic block
has hree multiplexing modes: OUTG,
OUTOUTRG, and OUT1OUT2. OUTREG and
OUT2UTREG are equivnt ecept that either OUT1
or Ois MUXed with the wherthe FF data is
output on the clock phaaftehe active edge. The
simplest multiplexng mods OUT1OUT2. In this
mode, the signal at UT1 is utput to the pad while the
clock is low, anthe sinaon OUT2 is output to the
pad when the clocis high. Figure 25 shows a simple
schematic a PIO OUT1OUT2 mode and a general
timing agrafor multiplexing an address and data
snal.
The drive current is 12 mA sink/6 mA source for the
slewlim and fast output speed selections and
6 mA sink/3 mA source for the sinklim output.Two adja-
cent outputs can be interconnected to increase the out-
put sink/source current to 24 mA/12 mA.
All outputs that are not speed critical should be confi-
ured as sinklim to minimize power and noise. The nm-
ber of outputs that switch simultaneously in the same
direction should be limited to minimize grounce.
To minimize ground bounce problems, loca
loaded output buffers near the ground pads.
bounce is generally a function of the driving circ,
traces on the printed-circuit boardnd loads and is
best determined with a circuit simulan.
Oftan address will be used to generate or read a
data smple from memory with the goal of multiplexing
the data onto a single line. In this case, the address
en precedes the data by one clock cycle.
OUT1OUTREG and OUT2OUTREG modes of the PIO
logic can be used to address this situation.
At powerup, the output driers are in slewlim mode,
and the input buffers are onfigured as TTL-level com-
patible (CMOS for OR3Txx) with pull-up. If an o
is not to be driven the seled configuration mode,
is 3-stated.
The output buffer sial cn be inverted, a
3-state cntrol signal cn be made acve-hie-
low, or alwas enabld. In additionthis 3-state signal
can be registed or nonregistereAdditioally, there
is fasopen-drain output option thdirely connects
the put sgnal to the 3-ate control, allowing the out-
put bufto either drive to a gic or 3-state, but
nevr to drive to a logi1. Becausthere is no explicit
rourequired to create te open-drain output, its
esponse is veike te input side of the PIO,
there are two nections from PIC routing to
the output side oO, OUT1, and OUT2. These
connections providor flexible routing and can be
used in data manipulation in the PIO as described in
subsequent paragraphs.
Because OUT1OUTREG mode is equivalent to
OUT2OUTREG, only OUT2OUTREG mode is
described here. Figure 26 shows a simple PIO sche-
matic in OUT2OUTREG mode and general timing for
multiplexing data with a leading address. The address
signal on OUT1 is registered in the PIO FF.This delays
the address so that it aligns with the data signal. The
PIO logic block then sends the OUTREG signal
(address) to the pad when the clock is high and the
OUT2 signal (data) to the pad when the clock is low,
resulting in an aligned, multiplexed signal.
Lattice Semiconductor
39
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells (continued)
PLC
PIC
ADDRESS
FROM
ROUTING
OUT1
OUT2
DATA
FROM
ROUTING
PIO
LOGIC
PAD
CLK
CLK
OUT1 ADDR1
OUT2 DATA1
ADDR2
ADDR3
AR4
ADDR5
DATA5
ATA4
DATA2
TA3
DATA4
PIC OUTPUT ADDR1
DATA1
ADDR2
AD
DATA3
ADDR4
NOTE: PIO E, OUT1OUT2
5-5799(F)
Figure 2. Oput Multiplexing (OUOUT2 Mde)
PL
P
DDRESS
FROM
UT1
D
ROUNG
CLK
P/O
LOGIC
PAD
DATA
FROM
ROUTING
O2
LK
R ADDR1
ADDR2
ADDR3
ADDR4
DATA3
ADDR3
ADDR5
DATA4
ADDR4
DATA
REG ADDRESS
PAD
DATA1
ADDR1
DATA2
ADDR2
ADDR1 DATA1 ADDR2 DATA2 ADDR3 DATA3 ADDR4
NOTE: PIO LOGIC MODE, OUT1OUT2
5-5797(F)
Figure 26. Output Multiplexing (OUT2OUTREG Mode)
40
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
PIO Register Control Signals
Programmable Input/Output Cells
(continued)
As discussed in the Inputs and Outputs subsections,
the PIO latches/FFs have various clock, clock enable
(CE), local set/reset (LSR), and global set/reset
(GSRN) controls. Table 11 provides a summary of
these control signals and thr effect on the PIO
latches/FFs. Note that all cntroials are optionally
invertible.
PIO Logic Function Generator
The PIO logic block can also generate logic functions
based on the signals on the OUT2 and CLK ports of
the PIO. The functions are AND, NAND, OR, NOR,
XOR, and XNOR. Table 10 is provided as a summary
of the PIO logic options.
Table 11. PIO Regter ontrol Signals
Table 10. PIO Logic Options
Control Sgnal
Effect/Functionality
ExpresCLK
locks input fast-pture latch;
ptionally clocFF, or
3-state FF.
Clocks iput latchoptionally
clockoutpFF, or 3-state FF.
Otionaenabs/disables input
FF (ot avble for input latch
mode)optionally enables/dis-
bles otput FF; separate CE
invion capability for input and
output.
Option
Description
OUT1OUTREG Data at OUT1 output when clock
low, data at FF out when clock
high.
Stem Cock
CLK)
ClEnable
(CE)
OUT2OUTREG Data at OUT2 output when clock
low, data at FF out when clock
high.
Data at OUT1 output when clock
low, data at OUT2 whe
high.
Output logical AND of si
OUT2 and clok.
Output logiNAND of signals
on OUT2 and cck.
Outpt logical OR f signals on
OU2 and clock.
Outt logicNOR of signal
OUT2 d clock.
utput logical XOR oon
OUTand clock.
tput logical XNOR s
on OUT2 anclock.
OUT1OUT2
AND
NAND
OR
Locl Set/eset Option to disable; affects input
(R)
latch/FF, output FF, and 3-state FF
if enabled.
Glbal Set/Reset Option to enable or disable per
(SRN) PIO after initial configuration.
Set/Reset Mode The input latch/FF, output FF, and
3-state FF are individually set or
reset by both the LSR and GSRN
inputs.
NOR
XOR
XNOR
Lattice Semiconductor
41
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
switching segments of the PIC to the right (below).This
means of connectivity between PICs using staggered
connections of groups of switching segments allows a
given PIC to route signals to both adjacent PICs and all
adjacent PLCs efficiently. This provides single signal
routing flexibility and routing of multiple buses on
groups of I/Os without tying up globl routing
resources.
Programmable Input/Output Cells
(continued)
PIC Routing Resources
The PIC routing borrows many of the concepts and
constructs from the PLC routing. It is designed to be
able to gather an 8-bit bidirectional bus from any eight
consecutive I/O pads and route them to either or both
of the two adjacent PLCs. The eight I/O bits do not
need to start at a PIC boundary; that is, they may start
at one of the middle two PIOs in a PIC and span three
PICs.
px1 Routing Segments. Tere ae five px1 routing
segments in each PIC that raralleto the edge of
the chip on which the IC resids, ach broken by a
CIP in each PIC. Thpx1 segments have connectivity
to the pSW segmenand to he x1 routing ts
of the two adjact PLs.
Substantial routing has been added to the PIC to off-
load PLC routing from being used to move signals
around the PLC array perimeter. This saves PLC rout-
ing for logic purposes and provides greater flexibility for
locking design pinouts prior to final placement and rout-
ing of the device, or allowing a change in the pinout late
in the design cycle. The PIC routing has also been
increased substantially to allow routing to the complex
PIO cells that now allow multiple inputs and outputs
device pin, along with new sequential control signal
such as clock enable, LSR, and clock.
px2 Routing egmets. There are ve px2 roug
segmentn eah PIC that run parlel the edge of
thchip on whithe PIC resis. To ovidgreater
utinflexibility, the CIPs that brk the 2 segments
etwo ICs are staggeed acrosthe two PICs in a
pair. nPIC of the par has reak IPs on the even-
mbered px2 segmentsand the other has them on
odd-numbereseents. The px2 segments
ave connectity to e pSW segments and to the x1
routing segmentof thtwo adjacent PLCs.
PICs are grouped in pairs for purposes of scussing
PIC routing. On the sides of a device, the PICin a pair
are referred to as top and bottom. On the top or ottom
of a device, the PICs in a pair are eferred to as left or
right. For example, on the top edof the evice, the
leftmost PIC, PT1, is the left IC of pair, nd PIC PT2
is the right PIC of that pa. The ext PIC to the right,
PT3, is the left PIC of the epair, and so on.
px5 RoutinSegments. There are ten px5 routing
segents in eh PIC that run parallel to the edge of
the chion which the PIC resides. Two of the ten seg-
nbroken in each PIC so that each segment is
brken every five PICs. All ten px5 segments break at
he crners of the chip, allowing independent px5 rout-
g on each edge of the chip. The px5 routing seg-
ents connect to the pSW segments and the x5 and
xH routing segments of the two adjacent PLCs.
The need for PIC pairs stems rom the routing of
switching segmenand PLC half- and longline driv-
ers. As descrbed belw, thconnectivity r these
types of roting igroud across pairs of ICs to o-
vide compe nd fast routing of I/O signals bwen a
given IC anhe hree adjacent LCsorthogo-
naand two diagonal.
pxH Routing Segments. Each PIC contains eight pxH
routing segments that run parallel to the edge of the
chip on which the PIC resides.The pxH segments have
connectivity with the xL, xH, and one set of xBID rout-
ing segments in the immediately adjacent PLC.
PIC routing egments use the sae terminology as
PLC rong segments, prefied with a p to dis-
tinguish them as beloPICs.
pxL Routing Segments. There are ten pxL routing
segments in each PIC that run parallel to the edge of
the chip on which the PIC resides. Each of the xL lines
makes a connection to an xL line from the adjacent
PLC. PIC long lines (xL) can be used for global signal
distribution just as PLC xL lines can.
PIC Switching Segments. ach PIC has two groups
of switching segments (pSW), each group having eight
lines with connectivity to the PIOs in groups of four.
One set of switching segments connects to the PIC to
the left (above), and the other set connects to the
42
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
P. BIDI routing segments from the adjacent PLC rout-
Programmable Input/Output Cells
(continued)
ing.
Q. These are the IN2 routing segments. There is one
IN2 line from each PIO, and all eight IN2 lines from
each PIC pair are present in both PICs of a pair.
PIC Architectural Description
The PIC architecture as seen in ispLEVER is shown in
Figure 27.The figure is the left PIC of a PIC pair on the
top edge of a Series 3 array. Both PICs in a pair are
similar, with the differences mainly lying in the connec-
tions between the PIC switching segments (pSW), the
IN2 connections across PIC boundaries, and the sys-
tem clock spine driver residing in only one PIC of a pair.
R. These CIPs connect the IN1 and IN2 routing seg-
ments from the PIOs to he IC witching seg-
ments.
S. These CIPs brek thPIC switching segments at
the interface betwn a PC pair.
T. These CPs connect adjacent PLC routing
resourcto the IC switching sts.
A. This is a programmable input/output (PIO). There
are four PIOs per PIC. The PIOs contain the PIC
logic and I/O buffers.
U. ThesCIPs nect inter-PIC the PIC
sitchinsegments.
B. This is the PIC output switching block. It connects
the PIC switching segments and local clock lines to
the PIO output and control signals.
. Thee CIPs break the 1, p2, and px5 routing at
thddle of a PIC. The 2 and x5 CIP place-
ment varies dependig on te LC.
C. This is the system clock spine switching block an
buffer.There is only one system clock spine r pair
of PICs. Its inputs can come from the PIg
segments or any of the eight PIO inputs
pair.
WThese mutuallxclusivbuffers can drive one long
line signal nto a IC loal clock routing segment.
X. These mutuallexclusive buffers can select a
source m onf the local system clock routes to
drivthe O 3-state control signal.
D. PIC switching segments (pSWThese routing seg-
ments are used to interconnct ruting resources
within the PIC and to a lesser degr, between
PICs.
These e the four local system clock routing seg-
ents. Two come from connections within the PIC,
onfrom the other PIC in the pair, and one from the
adjacent PLC.
E. px1 routing segmentshe PIC 1 routing segmts
traverse one PIC and brk at CIP in the middle f
each PIC.
These mutually exclusive buffers allow a signal on
the PIC switching segments to be routed to a sys-
tem clock spine or to a PIO system clock.
F. px2 routing segnts. he PICs have
traverses two PICbtween breaks.Thre
stagged among the five px2 sgments.
AA. ExpressCLK routing line.
AB. System clock spine.
G. x5 routing sements. Each ohe ten C x5 rout-
ing egments traverses five PICn beteen breaks
CIP. wo px5 segments break in each PIC.
AC. These various groups of CIPs connect routing
resources from the adjacent PLC to the inter-PIC
routing resources.
H. pxH outing segments. The eighPIC xH routing
gments traverse lf of te rray and break at
CIPs in the inuad ruting region that is in the
middle of t
AD. These buffers provide connectivity between the
PLC xL (xH) lines and the PIC xL (xH) lines or
connectivity between one of the IN2 routing seg-
ments and the PIC and/or PLC xL (xH) routing
segments.
I. (Not used iny for clarity.)
AE. These mutually exclusive buffers and CIPs provide
connectivity to the PLC xL and xH lines from one
of the IN2 input segments.
J. pxL routing segments. The PIC long lines run the
entire length of the side of the array.
K. x5 routing segments from the adjacent PLC routing.
L. xL routing segments from the adjacent PLC routing.
M. x1 routing segments from the adjacent PLC routing.
N. Switching segments from the adjacent PLC routing.
O. xH routing segments from the adjacent PLC routing.
AF. These buffers allow the IN2 signals to drive onto
the BIDI routing of the adjacent PLC, or the BIDI
routing of the adjacent PLC, and the PIC switching
segments and/or PIC half lines may be connected.
Lattice Semiconductor
43
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Input/Output Cells (continued)
5-5823(F)
Figure 27. PIC Architecture
44
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
High-Level Routing Resources
The high-level routing resources in the ORCA Series 3 devices are interquad routing, corner cell routing, and PIC
interquad routing. These resources and their related structures are discussed in the following subsections.
Interquad Routing
In the ORCA Series 3 devices, the PLC array is split into four equal quadrants. In etween these quadrants, routing
has been added to route signals between the quadrants and distribute clocks. addion to general routing, there
are four specialized clock routing spines.The general routing is discussed belowflowed by the special clock rout-
ing.
One of the main purposes of interquad routing is to distribute internally eneratesignals, such aocks and con-
trol signals. There are two types of interquad blocks: vertical and hrizoal. Vercal interquad Q) run
between quadrants on the left and right, while horizontal interquad bcks (hIQ) run between tom quad-
rants. Interquad lines begin and end in the MID cells that are disussed ater. Since hIQ nd vIQ have the
same logic, only the hIQ block is described below. The intquad uting connects to and H segments. It does
not affect other local routing (xsw, x1, fast carry), so locl routins e same, whether PPLC connections cross
quadrants or not. Figure 28 presents a (not to scale) view of interquad routing.
TMID
5 5
5
FAST CLOC
hIQ9[4:0]
5
5
5
5
5
5
hIQ8[4:0]
hIQ6[4:0]
hIQ4[4:0]
hIQ2[4:0]
hIQ0[4:0]
5
5
5
hIQ7[4:0]
hIQ5[4:0
hIQ3[4:0
Q1[
LMID
RMID
FAST CLOCK R
5
5 5 5
5
BMID
5-4538(F)
Figure 28. Interquad Routing
Lattice Semiconductor
45
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
device. Fast clocks and other clock resources are dis-
cussed in the Clock Distribution Network section.
High-Level Routing Resources (continued)
Figure 29 shows the connections from the interquad
routing to the inter-PLC routing for a block of the hori-
zontal interquad. The vertical interquad has similar
connections. The connections shown in Figure 29 are
made with PLCs located above and below the routing
shown in the figure. The interquad routing segments,
prefixed IH for interquad horizontal, are in ten groups of
five lines. Any one line from each group can be routed
to one of the xH segments from the top of the device
(left for vertical interquad), one of the xH segments
from the bottom of the device (right for vertical inter-
quad), and one of the x5 segments crossing the inter-
quad.
Programmable Corner Cell Routing
Programmable Routing
The programmable corner cell (PC) cos the cir-
cuitry to connect the routing of he two PICs each
corner of the device. The PIC px1 and p2 egments
and eight PIC switching semens are directly con-
nected together from one PIC anoter.The px5 lines
are all broken with CPs and the C pxL and pxH
segments are conncted froone block to anher
through programabuffe.
Corner Cell peciaFunctions
Figure 28 shows four fast middle clock (fast clock) sig-
nals with the suffixes T (top), B (bottom), R (right), and
L (left), respectively. Figure 29 also shows the fast
clock R and fast clock L lines; these are dedicated
interquad clock spines. They originate in the CLKCN-
TRL special function blocks in the middle of each edge
of the device, with the name referencing the edge o
origin. For example, fast clock R originates in the
CLKCNTRL block on the right edge of a device. Fast
clock spines traverse the entire PLC array but do not
connect to the PICs on the edge of the dviopposite
to the source. Each fast clock line connects to wo of
the xL lines in each PLC that run ohogonally to he
fast clock. These connections allothe fast clock lines
to generate a clock tree that can rach anPLC in the
In additioto rting functions, spial-urpose func-
tios are locatn each FPGA cornThe pper-left
CC cntains connections to the ound-scan logic
amicropocessor interfe. The uper-right PCC
contns connections tthe adbalogic, connectiv-
to the global 3-state snal (T_ALL), and a pro-
mmable clock agehe lower-left PCC
ontains connctionto the internal oscillator and a
programmable cck mnager. The lower-right PCC
contains nnectioto the start-up and global reset
logic. These unctions are all more completely
desibed in thSpecial Function Blocks section of this
data seet.
IH0[4:0]
IH1[4:0]
IH2[4:0]
IH3[4:0]
IH4[4:0]
FAST CLOCK R
FAST CLOCK L
IH5[4:0]
IH6[4:0]
IH7[4:0]
IH8[4:0]
IH9[4:0]
BL[9:0] vxL[9:0] vx5[9:0] vx1[9:0]
SUL[9:0]
vx1[9:0]
FAST
CARRY
vck vxH[9:0] BL[9:0]
5-5821(F)
Figure 29. hIQ Block Detail
46
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The pxH segments from the one quadrant can be con-
nected through a CIP to its counterpart in the opposite
quadrant, providing a path that spans the array of
PICs. Since a passive CIP is used to connect the two
pxH segments, a 3-state signal can be routed on the
two pxH segments in the oppote quadrants, and then
connected through this CIPAs with the hIQ and vIQ
blocks, CIPs and buffers allibblewide connections
between the interquasegments, te xH segments,
and the x5 segmes.
High-Level Routing Resources (continued)
PIC Interquad (MID) Routing
There is also connectivity between the PICs in each
quadrant, as well as a clock control (CLKCNTRL) mod-
ule (discussed in the Special Function Blocks section)
between the PIC routing and the interquad routing.
These blocks are called LMID (left), TMID (top), RMID
(right), and BMID (bottom). The TMID routing is shown
in Figure 30. As with the hIQ and vIQ blocks, the only
connectivity to the PIC routing is to the global pxH and
px5 segments.
SHUTFF
EXPRESSCLK LEFT
EXPRSCLK RIGHT
PIC LOCAL CLOCKS
FROM RIGHT
PIC LOCAL CLOCKS
FROM LEFT
pxL[9:0]
pxH[7:0]
px5[9:0]
px2[4:0]
px1[4:0]
pSW[7:4]
pSW[3:0]
pSW[7:4]
pSW[3:0]
in2[A:D] FROM LEFT
in[A:D] FROM RIGHT
CORNER ExpressCLK
5-5822(F)
Figure 30.Top (TMID) Routing
Lattice Semiconductor
47
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
is generated from the PLC to the left or right of the cur-
rent PLC, and one is generated from the PLC above or
below the current PLC. The selection decision as to
where these signals come from, above/below and left/
right, is based on the position of the PLC in the array
and has to do with the alternating natue of the source
of the system clock spines (discussd later).The last of
the five clock sources is also generawithithe PLC.
The E1 control signal, describd in the PLC Routing
Resources section, can drithe FU clock. The E1
signal can come from any xBroutinresource in the
PLC. The selection aswitchioclock signals in a
PLC is performed in he FINS. Figure 31 shows the
PFU clock sources r a set four adjacent
Clock Distribution Network
The Series 3 FPGAs provide three types of high-
speed, low-skew clock distributions: system clock, fast
middle clock (fast clock), and ExpressCLK. Because of
the great variety of sources and distribution for clock
signals in the ORCA Series 3, the clock mechanisms
will be described here from the inside out. The clock
connections to the PFU will be described, followed by
clock distribution to the PLC array, clock sources to the
PLC array, and finally ending with clock sources and
distribution in the PICs. The ExpressCLK inputs are
new, dedicated clock inputs in Series 3 FPGAs. They
are mentioned in several of the clock network descrip-
tions and are described fully later in this section.
Global Contol Sials
The foclock gnals in each PLC hat ae generated
from the lonis (xL) in the currenLC or n adja-
cnt PLC can also be used to de the Fclock
abe (CE), local set/reset (LSR) nd add/subtract/
wrienale (ASWE) signalThe clck signals gener-
ted fm vertical long les cadrve CE and ASWE,
d the clocks generated fm horizontal long lines can
ive LSR. This allos for lskew global distribution
of two of these ree ntrol signals with the clock rout-
ing while ill allowg a global clock route to occur.
PFU Clock Sources
Within a PLC there are five sources for the clock signal
of the latches/FFs in the PFU. Two of the signals are
generated off of the long lines (xL) within the PLC: on
from the set of vertical long lines and one from the
of horizontal long lines. For each of these signals, an
one of the ten long lines of each set, vertical or horizon-
tal, can generate the clock signal. Two of thfive PFU
clock sources come from neighboring PCsOne clock
vxL[9:0
vxL[
PLC
PLC
PFU
PFU
E1
E1
hxL[9:0]
PLC
PLC
PFU
PFU
E1
E1
hxL[9:0]
5-6054(F)
Figure 31. PFU Clock Sources
48
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The clock spine structure previously described pro-
vides for complete distribution of a clock from any I/O
pin to the entire PLC array by means of a single clock
spine and long lines (xL). This distribution system also
provides a means to have many different clocks routed
to many different and disperselocations in the PLC
array. Each spine can carra different clock signal, so
for the OR3T55 (which has 18 x 8 array of PLCs,
implying nine clock snes per side36 input clock sig-
nals can be suppoed ung the system clock network.
Clock Distribution Network (continued)
Clock Distribution in the PLC Array
System Clock (SCLK)
The clock distribution network, or clock spine network,
within the PLC array is designed to minimize clock
skew while maximizing clock flexibility. Clock flexibility is
expressed in two ways: the ease with which a single
clock is routed to the entire array, and the capability to
provide multiple clocks to the PLC array.
Fast Clock
There is one horizontal and one vertical clock spine
passing through each PLC. The horizontal clock spine
is sourced from the PIC in the same row on either the
left- or right-hand side of the array, with the source side
(left or right) alternating for each row. The vertical clock
spines are similarly sourced from the PICs alternating
from the top or bottom of a column. Each clock spine i
capable of driving one of the ten xL routing segme
that run orthogonal to it within each PLC. Full connec
tivity to all PFUs is maintained due to the conity
from the xL lines to the PFU clock signals n
the previous section; however, only an xL lin
other row (column) needs to be driven to allow
given clock signal to be distributed o every PFU.
Figure 32 is a high-level diagram of e Series 3 system
clock spine network with sample xL lin
Fast clocks re highpeed, low-skew ck spines that
originae frothe CKCNTRL spon blocks
(deribelater).There are four fasnes—one
origiting othe middle of ech edge e array.The
spines un in the interquaegioof the PLC array
from r source side of the vice tthe last row or
column on the opposite ide ohe device. The fast
clocks connect to two long nes, xL[8] and xL[9], that
rn orthogonal to tspine rection in each PLC.
These long linecan ten e connected to the PFU
clock input in the me manner as the general system
clocks, andike thystem clock connections, xL lines
are onlneedd in every other row (column) to distrib-
ua clocto every PFU. The limited number of long-
linconnectns and the low skew of the CLKCNTRL
sourcombine to make the fast clocks a very robust,
low-skew clock source.
connections for a 4 x 4 arry of PLCs.
UNUSED
SCLK SPINE
RTICAL
SCSPINE
UNUSED
SCLK SPINE
UNED
SCLPINE
(xL)
HORIZONTAL
SCLK SPINE
(xL)
NUSED
SCSPINE
UNUSED
SCLK SPINE
(xL)
UNUSED
SCLK SPINE
(xL)
(xL)
UNUSED
SCLK SPINE
UNUSED
SCLK SPINE
5-5801(F).a
Figure 32. ORCA Series 3 System Clock Distribution Overview
Lattice Semiconductor
49
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Clocks in the PICs
Clock Distribution Network (continued)
Because the Series 3 FPGAs have latches and FFs in
the I/Os, it is necessary to have clock signal distribution
to the PIOs as well as in the PLC array. The system
clock, the fast clock, and the ExpressCLK are available
for PIO clocking.
Clock Sources to the PLC Array
The source of a clock that is globally available to the
PLC array can be from any user I/O pad, any of the
ExpressCLK pads, or an internally generated source.
System Clock
PIC System Clock
As described in the Programmable Input/Output Cells
section, PICs are grouped in adjacent pairs. Any one of
the eight pads in a PIC pair can drive a clock spine in a
row or column. For PIC pairs on the top of the chip, the
column associated with the left PIC has the clock
spine, for pairs on the bottom, the right PIC column has
the spine. The top PIC of the pair sources the spine
from the left side of the array, and the bottom PIC of the
pair sources the spine from the right side of the array.
Clock delay and skew are minimized by having a single
clock buffer per pair of PICs. The clock spine for each
pair can also be driven by one of the four PIC switching
segments (pSW) in each PIC of the pair. This allows a
signal generated in the PLC array to be routed onto
global clock spine network. The system clock output
the programmable clock manager (PCM) may also be
routed to the global system clock spines vithe pSW
segments. Figure 33 shows the clock spne ultiplex-
ing structure for a pair of PICs on the top of tharray.
There are five local system lock lines in each PIC.
Much like the sources for a clin thPFU, two of the
local PIC clocks are enerated wn the PIC from long
lines. One is generaed from he set of ten PIC ong
lines (pxL) that uns arallel the PICs on nd
the other is geneted frothe set of ten lo)
from the PLC rray at terminate in te PIC. r
local PC system clock route comefrom he set f ten
xL lies in tjacent PLC that is rllel to he side
othe array on which the PIC reides. e urth local
C sstem clock route comes frothe set of ten long
lin(xL) om the PLC arrthat teminate in the adja-
ent that is not part f the amPIC pair. Much like
E1 signals in the PLCthat are used to distribute a
al clock to the Psothe fifth local clock line in
each PIC comfrom ocal pSW signals. This clock
signal for ach PIis shwn in Figure 33. One of these
five locC system clocks is selected for the system
clock signal ithe PIO. It is used as the PIO system
clock or both inut and output clocking as selected
within tPIO. All PIOs in a PIC share the same sys-
tm cloc
Fast Clock
The fast clock spines are sourced the PC array
from each side of the devie by the ExressCLK pads
via the CLKCNTRL funcn bck (described in the
Special Function Blocks seon).Te ExpressCLK
fast clock source from the pads shown in Figure
and will be describd further in the ExpresCLK Inputs
subsection.
IC ExpressCLK
he ExpressCLK signal used at the PIC latches/FFs
comes from the CLKCNTRL function block that resides
in the middle of the side on which the PIC resides. A
single signal comes from the CLKCNTRL and is driven
by separate buffers onto two ExpressCLK long wires.
One of these ExpressCLK signals goes to the PICs on
the right of (above) the CLKCNTRL block, and the
other ExpressCLK signal goes to the PICs on the left of
(below) the CLKCNTRL block on that side.
PAD A
PAD B
PAD C
PAD D
pSW[4]
pSW[5]
pSW[6]
pSW[7]
TO LOCAL CLOCKS
TO LOCAL CLOCKS
TPICR
SPINE
TPICL
5-5800(F)
Figure 33. PIC System Clock Spine Generation
50
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
pin is completely arbitrary, but using a pin that is near
the center of an edge of the device will provide the low-
est skew system clock network. The pin-to-pin timing
numbers in the Timing Characteristics section assume
that the clock pin is in one of the PICs at the center of
any side of the device next to n ExpressCLK pad. For
actual timing characteristicfor a given clock pin, use
the timing analyzer results fispLVER.
Clock Distribution Network (continued)
ExpressCLK Inputs
There are four dedicated ExpressCLK pads on each
Series 3 device: one in the middle of each side. Two
other user I/O pads can also be used as corner
ExpressCLK inputs, one on the lower-left corner, and
one on the upper-right corner. The corner ExpressCLK
pads feed the ExpressCLK to the two sides of the array
that are adjacent to that corner, always driving the
same signal in both directions. The ExpressCLK route
from the middle pad and from the corner pad associ-
ated with that side are multiplexed and can be glitch-
lessly stopped/started under user control using the
StopCLK feature of the CLKCNTRL function block
(described under Special Function Blocks) on that side.
The ExpressCLK output of the programmable clock
manager (PCM) is programmably connected to the co-
ner ExpressCLK routes. PCM blocks are found in th
same corners as the corner ExpressCLK signals and
are described in the Special Function Blocks n.
The ExpressCLK structure is shown in FigM
blocks are not shown).
To select subsequenclock pinsertain rules should
be followed. As disssd in the Programmable Input/
Output Cells section, Cs ae grouped into adjacent
pairs. Each f these pairontains eight I/Os, but only
one of the eght I/Os a PIC pair can outed directly
onto a ysteclock pine. Therefoeve top
perfrmae, the next clock input culd not be
one othe ps from a PIC pir previosed for a
lock iput. If it is necessato hve a second input in
the PIC pair route ontobal sstem clock rout-
ing, the input can be roued to fre clock spine using
the PIC switching segmenpSW) connections to the
cck spine network t somsmall sacrifice in speed.
Alternatively, if obal strution of the secondary
clock is not requir, the signal can be routed on long
lines (xL) ainputhe PFU clock input without
using a lock pine.
other rulfor choosing clock pins has to do with the
alteating nature of clock spine connections to the xL
and pxrouting segments. Starting at the left side of
the device, the first vertical clock spine from the top
nnects to hxL[0] (horizontal xL[0]), and the first verti-
cal clock spine from the bottom connects to hxL[5] in all
PLC rows. The next vertical clock spine from the top
connects to hxL[1], and the next one from the bottom
connects to hxL[6]. This progression continues across
the device, and after a spine connects to hxL[9], the
next spine connects to hxL[0] again. Similar connec-
tions are made from horizontal clock spines to vxL (ver-
tical xL) lines from the top to the bottom of the device.
Because the ORCA Series 3 clock routing only
CLKCNTRL
XPRESSCLK PADS
BLOCK
FAST CLOCKS
EXPRKS TO PIOs
requires the use of an xL line in every other row or col-
umn, even two inputs chosen 20 PLCs apart on the
same xL line will not conflict, but it is always better to
avoid these choices, if possible.The fast clock spines in
the interquad routing region also connect to xL[8] and
xL[9] for each set of xL lines, so it is better to avoid user
I/Os that connect to xL[8] or xL[9] when a fast clock is
used that might share one of these connections.
Another reason to use the fast clock spines is that
since they use only the xL[9:8] lines, they will not con-
flict with internal data buses which typically use xL[7:0].
For more details on clock selection, refer to application
notes on clock distribution in ORCA Series 3 devices.
5-5802(F)
N: All multiplexert durconfiguration.
Figure 34. Expand Fast Clock Distribution
Selecting Clock Input Pins
Any user I/O pin on an ORCA FPGA can be used as a
fast, low-skew system clock input. Since the four dedi-
cated ExpressCLK inputs can only be used to distribute
global signals into the FPGA, these pins should be
selected first as clock pins. Within the interquad region
of the device, these clocks sourced by the ExpressCLK
inputs are called fast clocks. Choosing the next clock
Lattice Semiconductor
51
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Readback can be performed via the Series 3 micropro-
cessor interface (MPI) or by using dedicated FPGA
readback controls. If the MPI is enabled, readback via
the dedicated FPGA readback logic is disabled. Read-
back using the MPI is discussed in the Microprocessor
Interface (MPI) section.
Special Function Blocks
Special function blocks in the Series 3 provide extra
capabilities beyond general FPGA operation. These
blocks reside in the corners and MIDs (middle inter-
quad areas) of the FPGA array.
The pins used for dedicated readbk arrdback
data (RD_DATA), read configurtion (RD_CF, and
configuration clock (CCLK). readback ration is
initiated by a high-to-low trasitin on RD_CFG. The
RD_CFG input must remain lodurinthe readback
operation. The readack operatiocan be restarted at
frame 0 by driving te RD_CFpin high, applyat
least two rising dgeof CCK, and then
RD_CFG low gaiOne bit of data is shifte
RD_DATA at e risiedge of CCLKThe firsbit
of the radbacframe is transmitteout everal ycles
aftethe firsg edge of CCLK afRD_CFis input
lw (see the Readback Timing Caractriscs table in
e Tming Characteristics section)To be certain of the
staof threadback framehe data can be monitored
r th1 frame start bipair.
Single Function Blocks
Most of the special function blocks perform a specific
dedicated function. These functions are data/configura-
tion readback control, global 3-state control (TS_ALL),
internal oscillator generation, global set/reset (GSRN),
and start-up logic.
Readback Logic
The readback logic is located in the upper right corner
of the FPGA and can be enabled via a bit stream option
or by instantiation of a library readback component.
Readback is used to read back the configuration data
and, optionally, the state of the PFU outputs. A rea
back operation can be done while the FPGA is in no
mal system operation. The readback operation cannot
be daisy-chained. To use readback, the usselects
options in the bit stream generator in the isEVER
Development System.
adback can be ed an address other than
ame 0 via thnew icroprocessor interface (MPI)
control regiters ee tMicroprocessor Interface
(MPI) seon for me information). In all cases, read-
back is perfmed at sequential addresses from the
staraddress.
Table 12 provides readback optios selected in the bit
stream generator tool. The table ovides e number
of times that the configuratin data an bread back.
This is intended primarily o givthe user control ove
the security of the FPGA’cfiguration program.
user can prohibit readback (, allw a single read
(1), or allow unrericted readbck (U).
t shoulbe noted that the RD_DATA output pin is also
ued as te dedicated boundary-scan output pin, TDO.
If thpin is being used as TDO, the RD_DATA output
om readback can be routed internally to any other pin
sired. The RD_CFG input pin is also used to control
he global 3-state (TS_ALL) function. Before and during
configuration, the TS_ALL signal is always driven by
the RD_CFG input and readback is disabled. After con-
figuration, the selection as to whether this input drives
the readback or global 3-state function is determined
by a set of bit stream options. If used as the RD_CFG
input for readback, the internal TS_ALL input can be
routed internally to be driven by any input pin.
Table 12. Radback ptins
Option
Funcon
Probit Readback
0
1
llow One ReadbaOnly
U
Allow UnreNumer of Readbacks
52
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The following occur when TS_ALL is activated:
Special Function Blocks (continued)
1. All of the user I/O output buffers are 3-stated, the
user I/O input buffers are pulled up (with the pull-
down disabled), and the input buffers are configured
with TTL input thresholds (OR3Cxx only).
The readback frame contains the configuration data
and the state of the internal logic. During readback, the
value of all registered PFU and PIC outputs can be
captured. The following options are allowed when
doing a capture of the PFU outputs.
2. The TDO/RD_DATA outut buffer is 3-stated.
3. The RD_CFG, RESET, and RGM iut buffers remain
active with a pull-p.
1. Do not capture data (the data written to the RAMs,
usually 0, will be read back).
4. The DONE outpt bufer is 3-stated, and the input
buffer is pulled up.
2. Capture data upon entering readback.
3. Capture data based upon a configurable signal
internal to the FPGA. If this signal is tied to
logic 0, capture RAMs are written continuously.
Internal Osillator
The inteal oillar resides in thcorner of
the GA ray. It has output lock fes of
1.25 Hz an10 MHz. The nternal ostor is the
srce f the internal CCLusd for configuration. It
may albe used afteconfigatioas a general-
purpose clock signal.
4. Capture data on either options 2 or 3 above.
The readback frame has an identical format to that of
the configuration data frame, which is discussed later
in the Configuration Data Format section. If LUT mem-
ory is not used as RAM and there is no data captu
the readback data (not just the format) will be identica
to the configuration data for the same frame.
eases a bitwise comparison between the cn
and readback data.The configuration header, g
the length count field, is not part of the readback me.
The readback frame contains bits locations not used
in the configuration. These locaions eed to be
masked out when comparing the configration and
readback frames. The delopment system optionally
provides a readback bit seam to mpare to readback
data from the FPGAAlso ote thif any of the LU
are used as RAM and new data is written to thm,
these bits will noavthe same values as al
configuration data fme ether.
Global Set/Reet (GRN)
The GSRN logic rides in the lower right corner of the
FPGA. GSis avertible, default, active-low signal
that is ed to reset all of the user-accessible latches/
Fs on thdevice. GSRN is automatically asserted at
poerup anduring configuration of the device.
The ting of the release of GSRN at the end of config-
uration can be programmed in the start-up logic
scribed below. Following configuration, GSRN may
be connected to the RESET pin via dedicated routing, or
it may be connected to any signal via normal routing.
Within each PFU and PIO, individual FFs and latches
can be programmed to either be set or reset when
GSRN is asserted. A new option in Series 3 allows
individual PFUs and PIOs to turn off the GSRN signal
to its latches/FFs after configuration.
Global 3-Ste Conrol (TS_ALL
To ncrease the stability of the OCA Ses FPGAs,
thglbal 3-state function (S_ALL) sales the
devicThTS_ALL signis drfrom either an
externapin or an internal signal. Bore and during
conguration, the TS_AL sigal s driven by the input
paRD_CFG. Aftnfiguation, the TS_ALL signal
can be disablfrom the RD_CFG input pad, or
driven by a geg signal in the upper right cor-
ner. Before confign, TS_ALL is active-low; after
configuration, the sense of TS_ALL can be inverted.
The RESET input pad has a special relationship to
GSRN. During configuration, the RESET input pad
always initiates a configuration abort, as described in
the FPGA States of Operation section. After configura-
tion, the global set/reset signal (GSRN) can either be
disabled (the default), directly connected to the RESET
input pad, or sourced by a lower-right corner signal. If
the RESET input pad is not used as a global reset after
configuration, this pad can be used as a normal input
pad.
Lattice Semiconductor
53
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The source clock for the CLKCNTRL block comes
Special Function Blocks (continued)
either from the ExpressCLK pad at the middle of the
side of the FPGA or from the corner ExpressCLK route
that comes from the corner ExpressCLK pad (at the
lower left or upper right of the device, whichever is
closer).The programmable clock manaer ExpressCLK
output can also be sourced to this rner routing for
distribution at the two closest CLKCL blcks.
Start-Up Logic
The start-up logic block is located in the lower right cor-
ner of the FPGA. This block can be configured to coor-
dinate the relative timing of the release of GSRN, the
activation of all user I/Os, and the assertion of the
DONE signal at the end of configuration. If a start-up
clock is used to time these events, the start-up clock
can come from CCLK, or it can be routed into the start-
up block using lower right corner routing resources.
These signals are described in the Start-Up subsection
of the FPGA States of Operation section.
Each CLKCNTRL block also features avertible
StopCLK shutoff input that avlable from local rout-
ing. This feature may be used glitclessly stop and
start the clock at the hree outputof each CLKCNTRL
block and has the oion of dng so on either rising
or falling edge the ock. When the clock
based on its isinedge, it stops and stays
When it is stoped bsed on its fallinedge, it
and stas at GD. If the StopCLK utoff signal meets
the LKCNTetup and hold timehe clok is
sopped on the second clock cye aftethshutoff sig-
l. diagram of the bottom CLKCTRL block and
StoCLK ming is shown in igure 3.
Clock Control (CLKCNTRL) and StopCLK
There is one CLKCNTRL block in the MID section of
the interquad routing on each side of the FPGA. This
block is used to selectively distribute the fast clock to
the PLC array and the left (top) and right (bottom)
ExpressCLKs (ECKL and ECKR) to the side of the
array on which the CLKCNTRL block resides.
CRNER ERESSLK
CLOSHUTOFF
EXPRESSCFT
EXPRESSCLK RIGHT
F
OFF_SET
OFF_SET
OFF_HLD
OFF_HLD
OCK SHUTOFF
CLKCNTRL O
5-5981(F)
Notes:
CLKCNTRL output clocks are ExpressCLK left and right and fast clock.
Clock shutoff shown active-high acting on clock falling edge.
Figure 35. Top CLKCNTRL Function Block
54
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Special Function Blocks (continued)
s
TMS TDI
TCK
TDO
TMS TDI
TCK
Boundary Scan
net a
TDO
net b
U2
U2
net c
The increasing complexity of integrated circuits (ICs)
and IC packages has increased the difficulty of testing
printed-circuit boards (PCBs). To address this testing
problem, the IEEE standard 1149.1/D1 (IEEE Standard
Test Access Port and Boundary-Scan Architecture) is
implemented in the ORCA series of FPGAs. It allows
users to efficiently test the interconnection between
integrated circuits on a PCB as well as test the inte-
grated circuit itself. The IEEE 1149.1/D1 standard is a
well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
from different vendors.
TDI
TMS
TCK
TDO
TMS TDI
TCK
TDO
TMS TDI
TDO
U3
U4
SEE ENLARGED VIEW BE
The IEEE 1149.1/D1 standard defines a test access
port (TAP) that consists of a four-pin interface with an
optional reset pin for boundary-scan testing of inte-
grated circuits in a system. The ORCA Series FPGA
provides four interface pins: test data in (TDI), test
mode select (TMS), test clock (TCK), and teut
(TDO). The PRGM pin used to reconfigure t
also resets the boundary-scan logic.
DO TCK TMS TDI
TAPC
PT
BSC
BDC DCC
SCA
IN
SCAN
OUT
BYPASS
RETER
INSTRUCN
REGISTE
p_in
p_ts
p_out
SC
OUT
SCAN
IN
p
PR[ij]
DC
p_in
BSC
BDC
The user test host serially loads tecommands and
test data into the FPGA through thepins to drive out-
puts and examine inputs. In the configation shown in
Figure 36, where boundascan is used to test ICs,
test data is transmitted sially intTDI of the first
BSCAN device (U1), throuh TDOTDI connections
between BSCAN evices (U2 and U3), and out TDO o
the last BSCAN evic(U4). In this configue
TMS and TCK signare outed to all bon
ICs in parallel so that boundary-scan co
operate in e same state. In other onfigurations, mul-
tiple scan patarused instead a single ring.When
mtiple can paths are used, each ing is depen-
dencontroled by its owTMS and TCK signals.
PLC
ARRAY
p_out
p_in
p_out
p_ts
BDC
DCC
]
AN
IN
SCAN
OUT
p_out
p_ts
p_in
BSC
DCC BDC
SCAN
OUT
SCAN
IN
PB[ij]
5-5972(F)
Key: BSC = boundary-scan cell, BDC = bidirectional data cell,
and DCC = data control cell.
Figure 36. Printed-Circuit Board with Boundary-
Scan Circuitry
Figure provides a systeinterfe for components
usein the boundary-san testing of PCBs. The three
maor componenthown re the test host, boundary-
scan support d the devices under test
(DUTs). The Dn here are ORCA Series
FPGAs with dediboundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a micropro-
cessor.
Lattice Semiconductor
55
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Special Function Blocks (continued)
D[7:0]
D[7:0]
TDI
TDO
TDI
TDO
TDO
ORCA
SERIES
FPGA
RCA
SERIES
GA
BOUNDARY-
SCAN
MASTER
CE
RA
TMS0
TCK
TMS
TCK
TMS
CK
MICRO-
PROCESSOR
(DUT)
(
R/W
DAV
INT
SP
(BSM)
TDI
INTR
TDI
DO
ORC
SERS
FPG
MS
TC
(DU
5-6765(F)
Figure 37. BScan Interface
ble 13. BoundaScastructions
The boundary-scan support circuit shown in Figure 3
is the 497AA Boundary-Scan Master (BSM). The BSM
off-loads tasks from the test host to incretest
throughput. To interface between the test hosand the
DUTs, the BSM has a general microprocessor inrface
and provides parallel-to-serial/serl-to-parallel conver-
sion, as well as three 8K data burs. The SM also
increases test throughput wh a deicateautomatic
test-pattern generator anwith ompression of the te
response with a signaturanlysis register. The P
based boundary-scan test cd/stware allows a
to quickly prototye a boundar-scan test set.
Code
000
001
10
01
100
101
110
111
Instruction
EXTST
PLC Scan Ring 1 (PSR1)/USERCODE
AM Write (RAM_W)
IDCODE
SAMPLE/PRELOAD
PLC Scan Ring 2 (PSR2)
RAM Read (RAM_R)
BYPASS
Boundary-can Instrcons
The ORCA ies boundary-scan rcuitry is efor
three andaty IEE 1149.1/D1 ests TEST,
SAMPLE/RELOAD, BYPAS), the optionIEEE
1141/D1 ICODE instruction, nd fivRCA-defined
instruction.The 3-bit witructn register supports
the nine instructions lie 13, where the use of
PSR1 or USERCODE ile by a bit stream
option.
56
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
operation or written during test operation. The data for
all of the I/Os is captured simultaneously into the BSR,
allowing them to be shifted-out TDO to the test host.
Since each I/O buffer in the PICs is bidirectional, two
pieces of data are captured for each I/O pad: the value
at the I/O pad and the value ohe 3-state control sig-
nal. For preload operation, ata is written from the BSR
to all of the I/Os simultaneo.
Special Function Blocks (continued)
The external test (EXTEST) instruction allows the inter-
connections between ICs in a system to be tested for
opens and stuck-at faults. If an EXTEST instruction is
performed for the system shown in Figure 36, the con-
nections between U1 and U2 (shown by nets a, b, and
c) can be tested by driving a value onto the given nets
from one device and then determining whether the
same value is seen at the other device. This is deter-
mined by shifting 2 bits of data for each pin (one for the
output value and one for the 3-state value) through the
BSR until each one aligns to the appropriate pin. Then,
based upon the value of the 3-state signal, either the
I/O pad is driven to the value given in the BSR, or the
BSR is updated with the input value from the I/O pad,
which allows it to be shifted out TDO.
There are five ORC-defined inuctions. The PLC
scan rings 1 and 2 PS1, PSR2) allow user-defined
internal scan paths ug thPLC latches/FFs. The
RAM_Write Enable (RAW) instruction allows the
user to serlly confiure the FPGA tgh TDI. The
RAM_ead nable RAM_R) allor to read
bacRAcontents on TDO after con. The
IDCODE inuction allows te user to ure a 32-bit
dentifiation code that is ique o each device and
seriutput it at TDO. ThCODformat is shown
in Table 14.
The SAMPLE/PRELOAD instruction is useful for sys-
tem debugging and fault diagnosis by allowing the dta
at the FPGA’s I/Os to be observed during normal
Table 14. Boundary-Scan ID Code
Version
(4 bits)
Part*
(10 its)
F
(6 b)
Manufacturer
LS
1 bit)
Device
(11 bits
OR3T20
OR3T30
0000
0000
0000
0000
00
00100000 110000
1110000110000
010000000 110000
10100000 110000
0011100000
000011101
1
1
1
1
1
000000101
0000011101
00000011101
00000011101
OR3T55
OR3C/T80
OR3T125
* PLC array ze of FPGA, reverse bit order.
Note: ble asses veion 0.
Lattice Semiconductor
57
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
the BSR (which requires a two FF delay for each pad)
is bypassed, test throughput is increased when devices
that are not part of a test operation are bypassed.
Special Function Blocks (continued)
ORCA Boundary-Scan Circuitry
The boundary-scan logic is enabled before and during
configuration. After configuration, a configuration
option determines whether or not bondary-scan logic
is used.
The ORCA Series boundary-scan circuitry includes a
test access port controller (TAPC), instruction register
(IR), boundary-scan register (BSR), and bypass regis-
ter. It also includes circuitry to support the four pre-
defined instructions.
The 32-bit boundary-scan idetification regiter con-
tains the manufacturer’s ID umbr, unique part num-
ber, and version (as describearlier)The
identification register the defalt ource for data on
TDO after RESET ihe TAP controller selects the shift-
data-register (SHIFDR) insuction. If bounan
is not used, TMSTDI, nd CK become ud
TDO is 3-stad or sed in the readbak ope
Figure 38 shows a functional diagram of the boundary-
scan circuitry that is implemented in the ORCA Series.
The input pins’ (TMS, TCK, and TDI) locations vary
depending on the part, and the output pin is the dedi-
cated TDO/RD_DATA output pad. Test data in (TDI) is
the serial input data. Test mode select (TMS) controls
the boundary-scan test access port controller (TAPC).
Test clock (TCK) is the test clock on the board.
An optnal USRCODE is availaif thboundary-
scaPSR1 ction is not used. Tselecton
btween PSR1 and USERCODis a cnfiuration
tioand can be performed in ispEVER. The USER-
COE is n 11-bit value ththe uscan set during
eviconfiguration ancan bwtten to and read
m the FPGA via the bodary-scan logic. The
SERCODE value placehe manufacturer field of
the boundary-sn ID ode when the USERCODE
instructiois issu, allowing users to have configured
deviceidtified in user-defined manner. The manu-
facturer ID fieremains available when the IDCODE
instrution is issued.
The BSR is a series connection of boundary-scan cells
(BSCs) around the periphery of the IC. Each I/O pad on
the FPGA, except for CCLK, DONE, and the boundary-
scan pins (TCK, TDI, TMS, and TDO), is included in the
BSR. The first BSC in the BSR (connected to TDI) i
located in the first PIC I/O pad on the left of the top s
of the FPGA (PTA PIC). The BSR proceeds clockwise
around the top, right, bottom, and left sides f the array.
The last BSC in the BSR (connected to TOis located
on the top of the left side of the array (PL1D).
The bypass instruction uses a sinle FF, which resyn-
chronizes test data that is not paof the crent scan
operation. In a bypass instrution, tst datreceived on
TDI is shifted out of the bpass egister to TDO. Since
FFERS
ATA REGISTERS
BOUNRY-SCAN REGISTER
CODE REGISTER
PSR1 REGISTER (PLCs)
PSR2 REGISTER (PLCs)
DATA
MUX
VDD
CONFIGURATION REGISTER
(RAM_R, RAM_W)
DI
BYPASS REGISTER
INSTRUCTION DECODER
INSTRUCTION REGISTER
TDO
M
U
X
RESET
CLOCK DR
SHIFT-DR
UPDATE-DR
RESET
VDD
CLOCK IR
SHIFT-IR
UPDATE-IR
TMS
TCK
V
DD
DD
SELECT
ENABLE
TAP
CONTROLLER
V
PUR
PRGM
5-5768(F)
Figure 38. ORCA Series Boundary-Scan Circuitry Functional Diagram
Lattice Semiconductor
58
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The TAPC generates control signals that allow capture,
shift, and update operations on the instruction and data
registers. In the capture operation, data is loaded into
the register. In the shift operation, the captured data is
shifted out while new data is shifted in. In the update
operation, either the instructioregister is loaded for
instruction decode, or the bundary-scan register is
updated for control of outpu
Special Function Blocks (continued)
ORCA Series TAP Controller (TAPC)
The ORCA Series TAP controller (TAPC) is a 1149.1/
D1 compatible test access port controller.The 16 JTAG
state assignments from the IEEE 1149.1/D1 specifica-
tion are used.The TAPC is controlled by TCK and TMS.
The TAPC states are used for loading the IR to allow
three basic functions in testing: providing test stimuli
(Update-DR), test execution (Run-Test/Idle), and
obtaining test responses (Capture-DR). The TAPC
allows the test host to shift in and out both instructions
and test data/results. The inputs and outputs of the
TAPC are provided in the table below. The outputs are
primarily the control signals to the instruction register
and the data register.
The test host genertes a test broviding input into
the ORCA Series TS put synchronous with TCK.
This sequences the TC though states in order to
perform the esired funcn on the instruction register
or a data reister. Fiure 39 provides agram of the
state trnsitis for e TAPC. The is deter-
mind by he TMS input value.
TE-LOGIC-
SET
1
Table 15. TAP Controller Input/Outputs
0
1
1
1
RUN-TEST/
IDLE
SELE-
DR-SCA
SELECT-
IR-SCAN
Symbol
I/O
Function
Test Mode Select
Test Clock
Powerup Reset
BSCAN Reset
0
0
0
TMS
TCK
PUR
I
I
I
I
O
O
O
O
O
O
O
O
1
1
CA-DR
CAPTURE-IR
0
0
SHIFT-DR
1
0
0
SHIFT-IR
1
0
0
PRGM
TRESET
Select
Enable
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Update-DR
Update-IR
Test Logic Reet
1
1
EXIT1-DR
0
EXIT1-IR
0
Select IR (ighSelect-DR (Low)
Test Data Out Enale
Capre/Parallel Load-DR
Capre/Parael Load-IR
Shift ta Rgister
Sft Instruction Regist
Updat/Parallel Load
pdate/Parallel Load
PAUSE-DR
PAUSE-IR
1
EXIT2-DR
1
1
EXIT2-IR
1
0
0
UPDATE-DR
UPDATE-IR
1
0
1
0
5-5370(F)
Figure 39.TAP Controller State Transition Diagram
Lattice Semiconductor
59
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
direction control cell is used to access the 3-state
Special Function Blocks (continued)
value. Both cells consist of a flip-flop used to shift scan
data which feeds a flip-flop to control the I/O buffer.The
bidirectional data cell is connected serially to the direc-
tion control cell to form a boundary-scan shift register.
Boundary-Scan Cells
Figure 40 is a diagram of the boundary-scan cell (BSC)
in the ORCA series PICs. There are four BSCs in each
PIC: one for each pad, except as noted above. The
BSCs are connected serially to form the BSR.The BSC
controls the functionality of the in, out, and 3-state sig-
nals for each pad.
The TAPC signals (capture, update, hiftn, treset, and
TCK) and the MODE signal control he orion of the
BSC. The bidirectional data celis also contrled by
the high out/low in (HOLI) sinal generaby the
direction control cell. When OLis low, the bidirec-
tional data cell receives input ffer ata into the BSC.
When HOLI is high, he BSC is lded with functional
data from the PLC.
The BSC allows the I/O to function in either the normal
or test mode. Normal mode is defined as when an out-
put buffer receives input from the PLC array and pro-
vides output at the pad or when an input buffer
provides input from the pad to the PLC array. In the test
mode, the BSC executes a boundary-scan operation,
such as shifting in scan data from an upstream BSC in
the BSR, providing test stimuli to the pad, capturing
test data at the pad, etc.
The MODE signis gered from the de
instruction reisterWhen the MODE sgnal i
(EXTEST), thscan data is propagted to the out
buffer. Wn thMODE signal is lo(BPASS or
SAMPLE), funcnal data from he FA’s nternal
gic ipropagated to the output ffer.
The primary functions of the BSC are shifting scan data
serially in the BSR and observing input (p_in), output
(p_out), and 3-state (p_ts) signals at the pads. The
BSC consists of two circuits: the bidirectional data c
is used to access the input and output data, and the
Thbounary-scan descripon langage (BSDL) is
rovidd for each devicn the RA Series of FPGAs
the ispLEVER CD. The SDL is generated from a
vice profile, pinoand er boundary-scan infor-
mation.
SCAN IN
I/O BUFFER
PAD_IN
p_in
PAD_OUT
BIDIRECTIONCEL
0
1
0
0
1
D
Q
D
PAD_TS
1
p_out
HI
0
1
1
Q
D
Q
D
p_ts
DIRECTION CONTROL CELL
SHIFTN/CAPTURE
TCK
SCAN OUT UPDATE/TCK
MODE
5-2844(F
Figure 40. Boundary-Scan Cell
60
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Special Function Blocks (continued)
Boundary-Scan Timing
To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on
the rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST
instruction, parallel data is output from the BSR to the FPGA pads on the falling edge TCK. The maximum fre-
quency allowed for TCK is 10 MHz.
Figure 41 shows timing waveforms for an instruction scan operation. The diagrashows the ue of TMS to
sequence the TAPC through states. The test host (or BSM) changes data on tfallg edge of TCK, and it is
clocked into the DUT on the rising edge.
TCK
TMS
TDI
5-5971(F)
Figure 41. Instruction Rister ScTiming Diagram
Lattice Semiconductor
61
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
interrupt the host processor either by a hard interrupt or
by having the host processor poll the microprocessor
interface.
Microprocessor Interface (MPI)
The Series 3 FPGAs have a dedicated synchronous
microprocessor interface function block (see
The control portion of the microprocessor interface is
available following powerup of the FPGA if the mode
pins specify MPI mode, even if the FGA is not yet con-
figured. The mode pin (M[2:0]) settgs cn e found in
the FPGA Configuration Modesection of thdata
sheet, and the setup and usof the MPconfigura-
tion is discussed in the MPI etp and Control subsec-
tion. For postconfiguration usehe MPI must be
included in the confiuration bit sam by using an MPI
library element in yur desigfrom the ORCA cro
library, or by seing te MP_SER bit of t-
figuration cotrol gister prior to the start oa-
tion (MPI regters adiscussed late).
Figure 42). The MPI is programmable to operate with
PowerPC MPC800 series microprocessors and Intel*
i960* J core processors; see Table 16 and Table 17,
respectively, for compatible processors. The MPI imple-
ments an 8-bit interface to the host processor (Pow-
erPC or i960) that can be used for configuration and
readback of the FPGA as well as for user-defined data
processing and general monitoring of FPGA function.
In addition to dedicated-function registers, the micro-
processor interface allows for the control of up to 16
user registers (RAM or flip-flops) in the FPGA logic. A
synchronous/asynchronous handshake procedure is
used to control transactions with user logic in the FPGA
array. There is also capability for the FPGA logic to
* Intel and i0 are egistered trademarks ntel orporation.
D[7:0]IN
FPGA
TING
D[7:0]OUT
ORCA
DONE
RD_DATA
INIT
D7IN
D7
D7OUT
D6IN
D6
D5
D4
D
D2
D0
STATUS
D6OUT
D5IN
REGISTER
D5OU
D4IN
D4OU
D3IN
D3OUT
D
2OUT
D1IN
HPAD
ER
1O
DBACK
A REGISTER
D0OUT
READBACK
ADDR REGISTER
A3
A2
RESET
RD_CFG
PRGM
GSR
A1
A0
CONTROL
WOREPC
REGISTERS
RD
CS0
CS1
CCLK
TO GSR BLOCK
IRQ
PART ID
REGISTERS
USER_START
USER_END
WR_CTRL
A[3:0]
TO FPGA
ROUTING
RDYRCV
CLK
ADS
ALE
W/R
M_ACK
MPI_CLK
MPI_STRB
MPI_ALE
MPI_RW
MPI_B1
i960 LOGIC
RD/WR
BT
POWERPC LOGIC
TS
CLKOUT
TA
DEVICE PAD
I/O BUFFER
5-5806(F)
Figure 42. MPI Block Diagram
62
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
(read high, write low) signals are set up at the FPGA
pins by the PowerPC. The PowerPC then asserts its
transfer start signal (TS) low. Data is available to the
MPI during a write at the rising clock edge after the
clock cycle during which TS is low. Thetransfer is
acknowledged to the PowerPC by the low assertion of
the TA signal. The MPI PowrPC interface does not
support burst transfers, so burst hibit signal, BI, is
also asserted low durng the transfeacknowledge.The
same process apps to read from the MPI except
that the read data is ected at the FPGA data pins by
the PowerPC at the risg dge of the clock when TA is
low. The Monly drives TA low for one clock cycle.
Microprocessor Interface (MPI) (continued)
PowerPC System
In Figure 43, the ORCA FPGA is a memory-mapped
peripheral to the PowerPC processor. The PowerPC
interface uses separate address and data buses and
has several control lines. The ORCA chip select lines,
CS0 and CS1, are each connected to an address line
coming from the PowerPC. In this manner, the FPGA is
capable of a transaction with the PowerPC whenever
the address line connected to CS0 is low, the address
line for CS1 is high, and there is a valid address on
PowerPC address lines A[27:31]. Other forms of selec-
tion are possible by using the FPGA chip selects in a
different way. For example, PowerPC address bits
A[0:26] could be decoded to select CS0 and CS1, or if
the FPGA is the only peripheral to the PowerPC, CS0
and CS1 could be tied low and high, respectively, to
cause them to always be selected. If the MPI is not
used for FPGA configuration, decoding logic can be
implemented internal or external to the FPGAic
internal to the FPGA is used, the chip sele
routed out on an output pin and then connec
nally to CS0 and/or CS1. If the MPI is to be use
configuration, any decode logic usd must be imple-
mented external to the FPGA sice te FPGA logic has
not been configured yet.
Interrureqsts cbe sent to tC asyn-
chroousto the read/write procesrequests
are surced y the user-logic n the FPhe MPI will
assert he request to the PwerPC as a direct interrupt
signd/or a pollable bit ie MPI status register
(discussed in the MPI Sup aControl section). The
MPI will continue o assert he interrupt request until
te user-logic deasrts its terrupt request signal.
Table 16. PowerP/MPI Configuration
PowPC
Signa
ORCA Pin
Name
Function
MPI
I/O
D[0:7]
D[7:0]
A[4:0]
I/O
I
8-bit data bus
A[231]
5-bit MPI address
bus
TS
—
RD/MPI_STRB
CS0
I
I
Transfer start signal
TO DAI
DOUT
CHAINED
CCLK
Active-low MPI
select
ES
8
D[7:0]
A[27:31]
CLKOUT
RD/WR
TA
D[7:0]
A[0]
—
CLKOUT
RD/WR
TA
CS1
I
I
Active-high MPI
select
PI_CLK
MPI_RW
MPI_ACK
MPI_BI
MPI_IRQ
MPI_STRB
C0
RIES 3
FPGA
POWERPC
A7/MPI_CLK
A8/MPI_RW
A9/MPI_ACK
A10/MPI_BI
PowerPC interface
clock
BI
IRQ
TS
26
A25
I
Read (high)/write
(low) signal
INIT
HDC
LDC
S1
O
O
Active-low transfer
acknowledge signal
5-5761(F)
BI
Active-low burst
transfer inhibit
signal
Note: FPGA shory-mapped peripheral using CS0 and
CS1. Othehemes are possible using CS0 and/or
CS1.
Any of
IRQ[7:0]
A11/MPI_IRQ
O
Active-low interrupt
request signal
Figure 43. PowerPC/MPI
The basic flow of a transaction on the PowerPC/MPI
interface is given below. Pin descriptions are shown in
Table 16 and timing is shown in the Timing Characteris-
tics section of this data sheet. For both read and write
transactions, the address, chip select, and read/write
Lattice Semiconductor
63
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
set up at the FPGA pins by the i960 at the next rising
edge of the clock. At this same rising clock edge, the
i960 asserts its address/data strobe (ADS) low. Data is
available to the MPI during a write at the rising clock
edge of the following clock cycle. The transfer is
acknowledged to the i960 by the low assertion of the
ready/recover (RDYRCV) signal. The same process
applies to a read from the MPI excet at thread
data is expected at the FPGA data pins by te i960 at
the rising edge of the clock hen DYRCV is low. The
MPI only drives RDYRCV low one clck cycle.
Microprocessor Interface (MPI) (continued)
i960 System
Figure 44 shows a schematic for connecting the ORCA
MPI to supported i960 processors. In the figure, the
FPGA is shown as the only peripheral, with the FPGA
chip select lines, CS0 and CS1, tied low and high,
respectively. The i960 address and data are multi-
plexed onto the same bus. This precludes memory
mapping of the FPGA in the i960 memory space of a
multiperipheral system without some form of address
latching to capture and hold the address signals to
drive the CS0 and/or CS1 signals. Multiple address sig-
nals could also be decoded and latched to drive the
CS0 and/or CS1 signals. If the MPI is not used for
FPGA configuration, decoding/latching logic can be
implemented internal or external to the FPGA. If logic
internal to the FPGA is used, the chip selects must be
routed out an output pin and then connected externally
to CS0 and/or CS1. If the MPI is to be used for configu-
ration, any decode/latch logic used must be imple-
mented external to the FPGA since the FPGA logic
not been configured yet.
Interrupts can be set to the i96synchronously to
the read/write procs. Interrpt requests are rced
by the user-login tFPG. The MPI wile
request to thi96as a direct interrupt signa
pollable bit in he Mstatus register discusshe
MPI Seup and Control section). TMPI will continue
to asert the nrupt request until tuser-logic deas-
srts its interrupt request signal
Ta17. 960/MPI Configation
i960
Signal
ORCA Pin MI
Function
Nam
AD[7:0]
D:0]
I/O Multiplexed 5-bit address/
8-bit data bus.The address
appears on D[4:0].
i960 SYSTEM CLOCK
8
LE
R/RCLK/
MPI_ALE
I
Address latch enable used
to capture address from
AD[4:0] on falling edge of
clock.
TO ISY-
CHAINED
DEVICES
DOUT
CCLK
AD[7:0]
D[7:0]
CLKIN
W/R
RDYRCV
XINTx
ALE
MPI_CLK
MPI_W
MACK
PI_IRQ
DS
RD/
MPI_STRB
I
Address/data strobe to
indicate start of transac-
tion.
ORCA
SEIES 3
FPGA
_E
MPTRB
MPI_
MPI_BE1
i960
ADS
BE0
BE1
CS0
CS1
—
—
I
I
I
Active-low MPI select.
Active-high MPI select.
DONE
INIT
HDC
DC
1
CS0
System
Clock
A7/
MPI_CLK
i960 system clock. This
clock is sourced by the
system and not the i960.
W/R
A8/MPI_RW
I
Write (high)/read (low)
signal.
5-5762(F)
NoteFPGA sown as only system pereral fixed-chip select
signalFor multiperiphtemsddress decoding and/or
latching can be used t chiselects.
RDYRCV
A9/
MPI_ACK
O
Active-low ready/recover
signal indicating acknowl-
edgment of the transac-
tion.
Figure 0/MPI
Any of
XINT[7:0]
A11/
MPI_IRQ
O
I
Active-low interrupt
request signal.
The basic flow of a transaction on the i960/MPI inter-
face is given below. Pin descriptions are shown in
Table 17, and timing is shown in the ORCA Timing
Characteristics section of this data sheet. For both read
and write transactions, the address latch enable (ALE)
is set up by the i960 at the FPGA to the falling edge of
the clock. The address, byte enables, chip selects, and
read/write (read low, write high) signals are normally
BE0
A0/
MPI_BE0
Byte-enable 0 used as
address bit 0 in i960 8-bit
mode.
BE1
A1/
MPI_BE1
I
Byte-enable 1 used as
address bit 1 in i960 8-bit
mode.
64
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
data written by the host processor from the D[7:0] pins
once the USTART signal is asserted. The user logic
ends a transaction by asserting an active-high user
end (UEND) signal to the MPI.
Microprocessor Interface (MPI) (continued)
MPI Interface to FPGA
The MPI interfaces to the user-programmable FPGA
logic using a 4-bit address, read/write control signal,
interrupt request signal, and user start and user end
handshake signals. Timing numbers are provided so
that the user-logic data transfers can be performed syn-
chronously with the host processor (PowerPC or i960)
interface clock or asynchronously. Table 18 shows the
internal interface signals between the MPI and the
FPGA user-programmable logic. All of the signals are
connected to the MPI in the upper-left corner of the
device except for the D[7:0] and CLK signals that come
directly from the I/O pin.
The MPI will insert wait-states in the host processor
bus cycles, holding the host processor until the user-
logic completes its task anretus UEND signal,
upon which the MPI generates an anowledge signal.
If the host processois reading m the FPGA, the
user logic must hathread data available on the
D[7:0] pins of the FPwhen the UEND signal is
asserted. If he user logis fast or if the MPI user
address is eing deded for use as ntrol signal,
the MPtranction me can be my routing
the STAT signal directly to the Ut of the
MPI. he timng section of thdata shontains a
paramter table with delasetuand hold timing
requents to operate the er-logeither synchro-
nously or asynchronouswith he MPI host interface
clock.
The 4-bit addressing from the MPI to the PLCs allows
for up to 16 locations to be addressed by the host pro-
cessor. The user address space of the MPI does no
address any hard register. Rather, the user is free to
construct registers from FFs, latches, or RAM that can
be selected by the addressing. Alternately, ted
address signals may be used as control sig
other functions such as state machines or tim
he user-logic may so asert an active-low interrupt
request (UIRQ) the MPI, which, in turn, asserts an
interrupt hoprocessor. Assertion of an inter-
rupt rquest s asynchronous to the host processor
clok anany rad or write transaction occurring in the
I. The ur-logic is responsible for providing any
reqred interrupt vectors for the host processor, and
the us-logic must deassert the interrupt request once
serviced. If the interrupt request is not deasserted in
user logic, it will continue to be asserted to the host
processor via the MPI_IRQ pin.
The transaction sequence betweethe MPI and the
user-logic is as follows. When the hot processor ini-
tiates a transaction as discussed in the receding sec-
tions, the MPI outputs the -bit user address (UA[3:0])
and the read/write controsignal (RDWR, which is
read-high, write-low egaress of ost processor), d
then asserts the uer start signal, USTART. During a
write from the hoprcessor, the user logiept
Table 18. MPI InternIterface Signals
Signa
MPI I/O
Function
UA3:0]
O
Ur LogAddress. Addresses up to 16 unique user registers or use as control
signals.
URWRN
USTART
UEND
O
O
I
Ur Logic Read/Write Control Signal. High indicates a read from user logic by
thhost processor, low indicates a write to user-logic by the host processor.
Active-High User Start Signal. Indicates the start of an MPI transaction between
the host processor and the user logic.
Active-High User End Signal. Indicates that the user-logic is finished with the
current MPI transaction.
UIRQ
I
Active-Low Interrupt. Sends request from the user-logic to the host processor.
D[7:0]
FPGA I/O User Data. Eight data bits come directly from the FPGA pins—not through the
MPI.
MPI_CLK
FPGA I
MPI Clock. The MPI clock is sourced by the host processor and comes directly
from the FPGA pin—not through the MPI.
Lattice Semiconductor
65
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI) (continued)
MPI Setup and Control
The MPI has a series of addressable registers that provide MPI control and status, configuration and readback data
transfer, FPGA device identification, and a dedicated user scratchpad register. All registers are 8 s wide. The
address map for these registers and the user-logic address space are shown in Table 19, folloed by descriptions
of the register and bit functions. Note that for all registers, the most significant bit is bit 7, and the st sigficant bit
is bit 0.
Table 19. MPI Setup and Control Registers
Address
Register
(Hex)
00
01
Control Register 1.
Control Register 2.
02
Scratchpad Register.
03
Status Register.
04
05
06
07
08
09
0A
Configuration/Readback Data Register.
Readback Address Register 1 (bits [7:0]).
Readback Address Register 2 (bit]).
Device ID Register 1 (bits [7:0]).
Device ID Register 2 (bits [15:8]).
Device ID Register 3 (bit[23:16]).
Device ID Register 4 bit[31:24]).
Reserved.
0B—0F
10—1F
User-definable ddress Space.
Control Register 1
The MPI control register is a ead/write register. Tprocssor writes a control byte to configure the MPI. It
is readable by the host prossor tverify the statol bits previously written.
Table 20. MPI Setp and Control Registes Descrips
Bit #
Description
Bit 0
R Input. Setting this bit to a 1 ioes a global set/reset on the FPGA. The host processor must
rern tis bit to a 0 to emoe GSR signal. GSR does not affect the registers at MPI addresses 0
through F hexadecmal or any cnfiguration registers. Default state = 0.
Bit 1
Bit
Bit 3
Bit 4
Bit 5
eserved.
Reserved.
Reserved
Reserved.
RD_CFG Input. Changing this bit to a 0 after configuration will initiate readback. The host processor
must return this bit to a 1 to remove the RD_CFG signal. Since this bit works exactly like the RD_CFG
input pin, please see the FPGA pin descriptions for more information on this signal. Default state = 1.
Bit 6
Bit 7
Reserved.
PRGM Input. Setting this bit to a 0 causes the FPGA to begin configuration and resets the boundary-
scan circuitry. The host processor must return this bit to a 1 to remove the PRGM signal. Since this bit
works exactly like the PRGM input pin (except that it does not reset the MPI), please see the FPGA pin
descriptions for more information on this signal. Default state = 1.
66
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI) (continued)
Scratchpad Register
The MPI scratchpad register is an 8-bit read/write register with no defined operation. It may be used for any user-
defined function.
Control Register 2
The MPI control register 2 is a read/write register. The host processor writes a cntrol byte to onfigure the MPI. It
is readable by the host processor to verify the status of control bits it had prevusly written.
Table 21. MPI Control Register 2
Bit #
Bit Name
Descption
Bit 0
EN_IRQ_CFG Enable IRQ for Configuration Da Rquest in Daisy-Chain Cion
Mode. Setting this bit to a 1 prior to configation enables he IRQ sio go active
when new data is requested r conguration writes or avaiable for configuration
reads to/from the configration dagister. A 0 clears thRQ enble. This bit is
only valid for daisy-chin cofiguration. Default = 0.
Bit 1
EN_IRQ_ERR Enable IRQ for Bit Strm Errr. Setting this to a 1 por to configuration
enables the IRal to o ctive on the ocurrece of bit stream error during
configuratios the IRQ enable. This t only has effect while in configura-
tion mode. De
Bit 2
Bit 3
Bit 4
EN_IRQ_USR EnablIRQ from User FPGA Sace. etting this bit to a 1 allows user-defined
circry in the FPGA to generae an inrrupto the host processor by sourcing a
logic lon the UIRQ signal e user loic. Default = 0.
MP_DAISY
MPI DaisChain OutpuEnable. etting this bit to a 1 enables daisy-chain output
of the configuration data. Se the Configuration section of this data sheet for daisy-
chaconfiguration ils. Dault = 0.
MP_HLD_BUS Enable Bus Holding Dring Daisy-Chain Configuration Mode. Setting this bit to
a 1 will causI to ait until the FPGA configuration logic has serialized a
byte of confiata before acknowledging the transaction. The data is only
serialized if tAISY (bit 3 above) control bit is set to 1. If MP_HOLD_BUS is
set t0, the MPI ill immediately acknowledge a configuration data byte transfer.
Immediate acknowledgment allows the host processor to perform other tasks during
FPGconfigration by polling the MPI status register (or by interrupt) and only write
configurton data when the FPGA is ready. Default = 0.
Bit
MP_USER
MPI ser Mode Enable. Setting this bit to a 1 will enable the MPI for user mode
opetion. MP_USER must be set prior to the FPGA DONE signal going high during
configuration. The MPI may also be enabled for user operation via the configuration
bit stream. Default = 0.
Bit 6
Bit 7
Reed
—
—
Lattice Semiconductor
67
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI) (continued)
Status Register
The microprocessor interface status register is a read-only register, providing information to the host processor.
Table 22. Status Register
Bit #
Description
Bit 0 Reserved.
Bit 1 Data Ready. Set by the MPI, a 1 on this bit during configuration alerts the host cessr that the FPGA
is ready for another byte of configuration data. During byte-wide readbck, the Msts this bit to a 1 to
tell the host processor that a byte of configuration data is available freading. This bit is cleared by a
host processor access (read or write) to the configuration data registr.
Bit 2 IRQ Pending. The MPI sets this bit to 1 to indicate to the host prossor t the FPGA has
interrupt request. This bit may be used for the host processor poll r interrupts if the MPI_IRt-
put of the FPGA has been masked at the host processor. This t is seto 0 when thstatus regir is
read. Interrupt requests from the FPGA user space must cleed in FPGA user lgic n addition to
reading this bit.
Bits
[4:3]
Bit Stream Error Flags. Bits 3 and 4 are set by e MI to indicate any error durinFPGconfigura-
tion. See bit 2 of control register 2 for the capability alert he host procesr of an ror via the IRQ
signal during configuration. In the truth tablw, bi3 ithe LSB (bit n righ.Thee bits are cleared
to 0 when PRGM goes active:
00 = No error
01 = ID error
10 = Checksum error
11 = Stop-bit/alignment erro
Bit 5 Reserved.
Bit 6 INIT. This bit reflects the binary value of the FPGA INIpin.
Bit 7 DONE. This bit reflects he binavalue of the FPGA DOE pin.
Configuration Data Regster
The MPI configuration data gister is a writable renfiguration mode and a readable register in readback
mode. For FPGA configuratiotis is where the con data bytes are sequentially written by the host pro-
cessor. Similarly, freadback mode, the MI provides readback data bytes in this register for the host proces-
sor.
Readback dress Register 1
ThMPI readbaddress registes a wtable register used to accept the least significant address byte
(b[7]) othe configuration ata locatioto be read back.
Readback Address R
The MPI readback addrer 2 is a writable register used to accept the most significant address byte
(bits [15:8]) of the configudata location to be read back.
68
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Microprocessor Interface (MPI) (continued)
Device ID Registers
The MPI device ID is broken into four registers holding 1 byte each.The device ID that is available through the MPI
is the same as the boundary-scan ID code, except that the device ID in the MPI has a reverse bit order.There is no
means to overwrite any of the device ID as can be done with the boundary-scan ID, but e MPI scratchpad register
can be used as a personalization register.The format for the entire device ID is shown lofollwed by family and
device values and the partitioning of the device ID into the four device ID register
Table 23. Device ID Code
Version
Part*
Family
Manfacturer
MSB
4 bits
10 bits
6 bits
1 bits
1 bit
Example: (First version of OR3C80)
0000 0110100000 1100000001101 1
* PLC array size of FPGA.
Table 24 shows the family and device values for all parts coved this data sheet.
Table 24. Series 3 Family and Device ID Values
Family ID
(Hex)
DevicD
Part Name
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
03
03
03
03
03
0E
12
16
1C
Table 25 describes the dece IDs or all parts covtdata sheet as they are partitioned into the four regis-
ters found in the MPI.
Table 25. ORCA Sies 3 Device ID Des
Device IRegister 1
Bit 0
gic 1. This bit is always a one.
Bits [7:1]
01101, he 7 least significant bits of the manufacturer ID.
Dee ID Register 2
Bits [3:0]
Bits [7:4]
000, the 4 most significant bits of the manufacturer ID.
The 4 least significant bits of the 10-bit part number.
Device ID Re
Bit
Bits [
The 6 most significant bits of the 10-bit part number.
The 2 least significant bits of the device family code.
Device ID Register 4
Bits [3:0]
Bits [7:4]
The 4 most significant bits of the device family code.
The 4-bit device version code.
Lattice Semiconductor
69
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
ner ExpressCLK that feeds the CLKCNTRL blocks on
the two sides adjacent to the PCM, and one to the sys-
tem clock spine network through general routing. Fig-
ure 45 shows a high-level block diagram of the PCM.
Programmable Clock Manager (PCM)
The ORCA programmable clock manager (PCM) is a
special function block that is used to modify or condi-
tion clock signals for optimum system performance.
Some of the functions that can be performed with the
PCM are clock skew reduction (both internal and board
level), duty-cycle adjustment, clock delay reduction,
clock phase adjustment, and clock frequency multipli-
cation/division. Due to the different capabilities
required by customer application, each PCM contains
both a PLL (phase-locked loop) and a DLL (delayed-
locked loop) mode. By using PLC logic resources in
conjunction with the PCM, many other functions, such
as frequency synthesis, are possible.
Functionality of the PCM is programmed during opera-
tion through a read/write interface inrnal to the FPGA
array or via the configuration bit stram. hnternal
FPGA interface comprises writenable and ead
enable signals, a 3-bit addres bus, an t input (to
the PCM) data bus, and an -bit utput data bus.There
is also a PCM output signal, LCK, tat indicates a sta-
ble output clock stat. These sigs are used to pro-
gram a series of resters to onfigure the PC
functional core or thdesirefunctionality
Operation of he PM is divided into to moy-
locked loop (DL) anphase-lockeloop (PLL)ome
operationcan e performed by eiter mode and some
arspecific to articular mod. Thewill e
escried in each individual modsecti. In general,
Dmode s preferable to LL modfor the same
funcn because it is lss sesitive o input clock
ise.
There are two PCMs on each Series 3 device, one in
the lower left corner and one in the upper right corner.
Each can drive two different, but interrelated clock net-
works inside the FPGA. Each PCM can take a clock
input from the ExpressCLK pad in its corner or from
general routing resources. There are also two input
sources that provide feedback to the PCM from the
PLC array. One of these is a dedicated corner Expre
CLK feedback, and the other is from general routing.
Each PCM sources two clock outputs, one the cor-
the discussions t follothe duty cycle is the per-
cent of the clocperioduring which the output clock is
high.
USER CONTROL SNALS
PGA
FACE
CORR EXRESSCLK IN
EXPRESSCLK OUT
PCM CORE
FUNCTIONS
SYSTEM CLOCK OUT
(TO GENERAL ROUTING)
GERACLOCKIN
FROM GENEL ROUTING)
FEEDBACK
ExpressCLK
FEEDBACK CLOCK
FROM ROUTING
5-5828(F)
Figure 45. PCM Block Diagram
70
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM) (continued)
PCM Registers
The PCM contains eight user-programmable registers used for configuring the PCM’s functionality. Table 26 shows
the mapping of the registers and their functions. See Figure 46 for more information on thlocation of PCM ele-
ments that are discussed in the table. The PCM registers are referenced in the discusons that follow. Detailed
explanations of all register bits are supplied following the functional description of the P.
Table 26. PCM Registers
Address
Function
0
Divider 0 Programming. Programmable divider, DIV0, vue and DIV0 reset bit. DIV0 can
divide the input clock to the PCM or can be bypassed.
1
2
Divider 1 Programming. Programmable divider, IV1alue d DIV1 reset bit.
divide the feedback clock input to the PCM or can bypsed. Valid only iPLL m
Divider 2 Programming. Programmable diver, DI, value and DIV2 set bt. DIV2 can
divide the output of the tapped delay line r can bassed and is only d for te
ExpressCLK output.
3
4
DLL 2x Duty-Cycle Programming. Dode clock doubler (2) duty-cle selection.
DLL 1x Duty-Cycle ProgrammiDepedinon the settings in her reisters, this regis-
ter is for:
a. PLL mode phase/delay s
b. DLL mode 1x duty cycle sel; and
c. DLL mode progrmmable delay.
5
6
Mode Programmng. LL/PLL mode selectioDLL 1x/2clock selection, phase detector
feedback selection.
Clock Soure Status/Output Clock Seletion Proamming. Input clock selection, feed-
back clock lection, xpressCLK output soue selection, system clock output source selec-
tion.
7
PCConrol Programming. Ppowereset, and configuration control.
Lattice Semiconductor
71
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM) (continued)
PCM
INPUT
CLOCK
CHARGE PUMP
AND
LOW-PASS FILTER
PHASE
DETECTOR
0
EXPRESSCLK
PAD
FROM
ROUTING
PROGRAMMABLE
DIVIDER
1
2
S0
DIV0
0
S4
1
PROGRAMMABLE DELAY
LINES (32 TAPS)
3
1
S2
FBACK
CLOCK
0
EK
0
REGISTER 7
REGISTER 6
REGISTER 5
REGISTER 4
REGISTER 3
REGISTER 2
REGISTER 1
PROGMMLE
1...7 1...7 1...7 1...7
1
S3
2
DIVIDER
DIV1
RO
S5
S6
S7
S8
0
0
1
1
2
EXRESSCLK
OUTPUT
S4
S
PROGRAMMABLE
3
DIVIDER
DIV2
COMBINATOR
LOGIC
REGISTER 0
0
1
2
FPGA-PCM INTERFACE
SYSTEM CLOCK
OUTPUT
S10
3
0
5-5829(F)
Figure 46CM nal Block Diagram
72
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
1x Clock Duty-Cycle Adjustment
Programmable Clock Manager (PCM)
(continued)
A duty-cycle adjusted replica of the input clock can be
constructed in DLL mode. The duty cycle can be
adjusted in 1/32 (3.125%) increments of the input clock
period. DLL 1x clock mode is selected by setting bit 4
of register five to a 1, and ouput clock source selection
is selected by setting regisr sib[5:4] to 01 for
ExpressCLK output, and/or bits [7:6o 01 for system
clock output. The duy-cycle petage value is
entered in register ur. ee register four programming
details for more informtion. uty cycle values are also
shown in ththird columof Table 27.
Delay-Locked Loop (DLL) Mode
DLL mode is used for implementing a delayed clock
(phase adjustment), clock doubling, and duty cycle
adjustment. All DLL functions stem from a delay line
with 32 taps. The delayed input clock is pulled from var-
ious taps and processed to implement the desired
result. There is no feedback clock in DLL mode, provid-
ing a very stable output and a fast lock time for the out-
put clock.
Table . DModDelay/1x D
DLL mode is selected by setting bit 0 in PCM register
five to a 0. The settings for the various submodes of
DLL mode are described in the following paragraphs.
Divider DIV0 may be used with any of the DLL modes
to divide the input clock by an integer factor of 1 to 8
prior to implementation of the DLL process.
Programming Values
Rester 4 [7:0]
6 4 3 2 1 0
elay
Duty Cycle
(CL_IN/32) (% of CLK_IN)
0 0 X X X 0 0 0
0 0 X X X 0 0
0 0 X X X 1 0
0 0 X X X 0 1
0 0 X X 1
0 0 X X 0 1
0 0 X X 1 1 0
0 X X X 1 1 1
0 1 X X X 0 0 0
0 1 X X X 0 0 1
0 1 X X X 0 1 0
0 1 X X X 0 1 1
0 1 X X X 1 0 0
0 1 X X X 1 0 1
0 1 X X X 1 1 0
0 1 1 1 1 X X X
1 0 0 0 0 X X X
1 0 0 0 1 X X X
1 0 0 1 0 X X X
1 0 0 1 1 X X X
1 0 1 0 0 X X X
1 0 1 0 1 X X X
1 0 1 1 0 X X X
1 0 1 1 1 X X X
1 1 0 0 0 X X X
1 1 0 0 1 X X X
1 1 0 1 0 X X X
1 1 0 1 1 X X X
1 1 1 0 0 X X X
1 1 1 0 1 X X X
1 1 1 1 0 X X X
1
2
3
4
5
6
7
8
3.125
6.250
9.375
Delayed Clock
12.500
15.625
18.750
21.875
25.000
28.125
31.250
34.375
37.500
40.625
43.750
46.875
50.000
53.125
56.250
59.375
62.500
65.625
68.750
71.875
75.000
78.125
81.250
84.375
87.500
90.625
93.750
96.875
A delayed version of the input clock can be d
in DLL mode.The output clock can be delayee-
ments of 1/32 of the input clock perid. Express K
and system CLK outputs in delay odes are selected
by setting register six, bits [5:4] to 10 r 11 for Express-
CLK output, and/or bits [7:6] to 10 for stem clock out-
put. The delay value is enered in register four. See
register four programmindetails r more informaion.
Delay values are alo shoin thsecond column
Table 27.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Note that when reer sixbits [5:4] are se
ExpressCLK output is iided by an integem
1 to 8 whithe system clock cannbe dividehe
ExprssCLK ivideis provided so hat the I/O clocking
prvided by the xpressCLK can oerate swer than
the nrnal system clock. Tis allows r ery fast inter-
nal pcesing while maiaininower interface
seeds ff-chip for imroved noise nd power perfor-
mae or to interoperatwith oer devices in the sys-
te. The divisor ExpessCLK frequency is
selected in reSee the register two program-
ming details for rmation.
Lattice Semiconductor
73
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Clock Delay Minimization
Programmable Clock Manager (PCM)
(continued)
PLL mode can be used to minimize the effects of the
input buffer and input routing delay on the clock signal.
PLL mode causes a feedback clock signal to align in
phase with the input clock (refer back to the block dia-
gram in Figure 45) so that the delay etween them is
effectively eliminated.
2x Clock Duty-Cycle Adjustment
A doubled-frequency, duty-cycle adjusted version of
the input clock can be constructed in DLL mode. The
first clock cycle of the 2x clock output occurs when the
input clock is high, and the second cycle occurs when
the input clock is low.The duty cycle can be adjusted in
1/32 (6.25%) increments of the input clock period.
Additionally, each of the two doubled-clock cycles that
occurs in a single input clock cycle may be adjusted to
have different duty cycles. DLL 2x clock mode is
selected by setting bit 4 of register five to a 1, and by
setting register six, bits [5:4] to 01 for ExpressCLK out-
put, and/or bits [7:6] to 01 for system clock output. The
duty-cycle percentage value is entered in register
three. See register three programming details for more
information. Duty-cycle values where both cycles of the
doubled clock have the same duty cycle are also
shown in Table 28.
There is a dedicated feedbacpath from an adjacent
middle CLKCNTRL block to he PM. Using the corner
ExpressCLK pad as the input he PCM and using this
dedicated feedback pththe clck om the Express-
CLK output of the PM, as viewed at the CLKCNTRL
block, will be phaseligned th the Expresput
to the PCM. Thee relonips are diagr
Figure 47.
A feedck clok can also be inpuo the PCM from
genral routghis allows for comsating or delay
btween the PCM input and a pnt in te eneral rout-
ig. he use of this routed-feedbacpath is not gener-
ally ecommended. Becauscompesation is based
n the rogrammable rting, e mount of clock
ay compensation can vry between FPGA lots and
brication process, and vary each time that the
feedback line is outeusing different resources. Con-
tact Latticfor apcation notes regarding the use of
routed-eeback delcompensation.
Table 28. DLL Mode Delay/2x Duty Cycle
Programming Values
Register 3 [7:0]
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
y Cycle
()
6.25
0 0 0 0 1 0 0 1
0 0 0 1 0 0 1 0
0 0 0 1 1 0 1 1
0 0 1 0 0 1 0
0 0 1 0 1 1 0 1
0 0 1 0 1 1 0
0 1 1 1 1 1
1 1 0 0 0 0 0 0
0 0 1 0 1
1 1 0 0 1 0
1 0 1 1 0 1 1
1 1 0 0 1 0 0
1 1 1 0 1 1
1 1 1 1 0 1 1
12.50
18.75
25.00
31.25
37.50
75
50.00
56.25
62.50
8.75
75.00
81.25
87.50
93.75
DELAY
COMPENSATION EQUALS DELAY
CORNER
RESSCLK
INPUT
CLKCNTRL
EXPRESSCLK
OUTPUT WITHOUT
USING PCM
DELAY IS COMPENSATED
CLKCNTRL
EXPRESSCLK
OUTPUT
USING PCM
5-5980(F)
Figure 47. ExpressCLK Delay Minimization
Using the PCM
Phase-Locked Loop (PLL) Mode
The PLL mode of the PCM is used for clock multiplica-
tion (1/8x to 64x) and clock delay minimization func-
tions. PLL functions make use of the PCM dividers and
use feedback signals, often from the FPGA array. The
use of feedback is discussed with each PLL submode.
PLL mode is selected by setting bit 0 of register five to
1.
74
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The multiplied output is selected by setting register six,
bits [5:4] to 10 or 11 for ExpressCLK output and/or bits
[7:6] to 10 for system clock output. Note that when reg-
ister six, bits [5:4] are set to 11, the ExpressCLK output
is divided by DIV2, while the system clock cannot be
divided.The ExpressCLK dividis provided so that the
I/O clocking provided by thExpressCLK can operate
slower than the internal sysclocThis allows for
very fast internal procssing while aintaining slower
interface speeds ochip r improved noise and power
performance or to inperatwith slower devices in
the system.
Programmable Clock Manager (PCM)
(continued)
Clock Multiplication
An output clock that is a multiple (not necessarily an
integer multiple) of the input clock can be generated in
PLL mode. The multiplication ratio is programmed in
the division registers DIV0, DIV1, and DIV2. Note that
DIV2 applies only to the ExpressCLK output of the
PCM and any reference to DIV2 is implicitly 1 for the
system clock output of the PCM. The clock multiplica-
tion formulas when using ExpressCLK feedback are:
It is also neessary configure the ial PCM oscil-
lator fooperion in he proper frenge.
Tabl29 d Table 30 show the seired for
regisr four or a given frequncy ranSeries 3C
and 3T devices. In additiothe cquisition time is
shoeach frequency rae.This s the time that is
required for the PCM to cquirLOCK. The PCM oscil-
lator frequency range is chsen based on the desired
otput frequency at he sysm clock output. If using
the ExpressCLoutputhequivalent system clock
frequency can be elected by multiplying the expected
ExpressCLoutpuequency by the value for DIV2.
Chooshe nminal frequency from the table that is
csest to e desired frequency, and use that value to
prram regter four. Minor adjustments to match the
exacnput frequency are then performed automatically
by the PCM.
DIV1
FExpressCLK_OUT = FINPUT_CLOCK •
DIV0
FSYSTEM_CLOCK_OUT = FExpressCLK_OUT • DIV2
Where the values of DIV0, DIV1, and DIV2 range from
1 to 8.
The ExpressCLK multiplication range of output clock
frequencies is, therefore, from 1/8x up to 8x
system clock range up to 8x the ExpressCLy
or 64x the input clock frequency. If system clo
back is used, the formulas are:
DIV1
FSYSTEM_CLOCK_OUT = FINPUT_CLOC•
DIV0
FExpressCLK_OUT = FSYTEM_CLOK/DIV2
The divider values, DIV0, D1, ad DIV2 are pro-
grammed in regiers zro, one, and two, reely.
Lattice Semiconductor
75
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM)
(continued)
Table 29. PCM Oscillator Frequency Range 3Txxx
Table 30. PCM Oscillator Frequency Range 3Cxx
System
Clock
System
Clock
Output
Output
Frequency
(MHz)
T
Frequecy
(M)
T
Register 4 Min
76543210 (MHz)
Max Acquisition
Register 4 Min
76543210 (MHz)
Max Acquisition
NOM
(MHz)
(µs)
NOM
(Mz)
(µs)
00XXX010 17.00
00XXX011 16.10
00XXX100 15.17
00XXX101 14.25
00XXX110 13.33
00XXX111 12.40
01XXX000 12.20
01XXX001 12.10
01XXX010 11.90
01XXX011 11.70
01XXX100 11.10
01XXX101 10.50
01XXX110 10.00
01XXX111 9.40
10000XXX 9.20
10001XXX 9.00
10010XXX 8.80
10011XXX 8.60
10100XXX 8.40
10101XXX 8.10
10110XXX 7.9
10111XXX 7.70
11000X760
11001XXX 7.45
1010XXX 0
1XXX 7.20
11100XX6.60
11101XXX 6.00
11110XXX 5.50
11111XXX 5.00
58.50
52.50
49.00
45.00
41.50
38.00
36.75
35.00
33.00
31.30
30.00
29.15
28.10
27.00
26.25
25.65
25.0
4.45
2.0
22.9
22.20
2.50
20.80
20.10
19.45
18.85
160
100.00
89.00
82.80
76.50
70.30
64.00
61.30
58.00
54.30
51.00
49.40
47.80
46.20
44.60
43.30
42.30
1.30
40.30
9.00
37.70
36.50
35.20
34.00
32.80
.60
30.50
0.00
29.40
28.60
28.00
36.00
37.00
38.00
39.00
40.00
41.00
43.75
46.50
49.25
52.
54.75
57.50
60.25
63.00
65.40
67.80
70.10
72.50
74.
77.
79.60
82.0
84.
86.50
88.80
91.00
93.30
95.50
97.80
100.00
00XXX010 10.50
00XXX011 10.00
00XXX100 90
00XXX101 9.10
00XXX110 .60
00XX111 0
1XXX000 7.80
1XX001 7.60
01X10 7.30
1XXX011 7.10
1XXX100 6.80
01XXX101 50
01XXX10 6.3
01XX116.00
1000XXX 90
10001XX 5.90
00105.80
1011XXX 5.80
0100XXX 5.70
0101XXX 5.60
10110XXX 5.60
10111XXX 5.50
11000XXX 5.40
11001XXX 5.40
11010XXX 5.30
11011XXX 5.30
11100XXX 5.20
11101XXX 5.10
11110XXX 5.10
11111XXX 5.00
73.00
68.0
63.0
58.50
53.80
49.00
47.70
430
45.0
4.60
40.75
39.40
38.00
37.40
36.70
36.00
35.40
35.00
34.10
33.50
32.80
32.10
31.50
30.70
30.10
29.50
28.80
28.20
27.50
35.00
126.00
117.00
1080
9.00
90
87.5
.00
8.50
80.00
77.50
75.00
72.50
70.00
68.80
67.50
66.30
65.00
63.80
62.50
61.30
60.00
58.80
57.50
56.30
55.00
53.80
52.50
51.30
50.00
36.00
0
40
41.00
43.80
46.50
49.30
52.00
55.00
57.50
60.30
63.00
65.40
67.80
70.10
72.50
74.90
77.30
79.60
82.00
84.30
86.50
88.80
91.00
93.30
95.50
97.80
100.00
Note: Use of settings in the first three rows is not recommended.
X means don’t care.
Note: Use of settings in the first three rows is not recommended.
X means don’t care.
76
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
PCM Operation
Programmable Clock Manager (PCM)
(continued)
Several features are available for the control of the
PCM’s overall operation. The PCM may be programma-
bly enabled/disabled via bit 0 of register 7. When dis-
abled, the analog power supply of the PCM is turned
off, conserving power and iminating the possibility of
inducing noise into the systm owebuses. Individual
bits (register 7, bits [2]) are providd to reset the DLL
and PLL functions the CM.These resets affect only
the logic generating hDLL oPLL function; they do
not reset the der vaes DIV0, DIV1, DIV2) or reg-
isters [7:0]. he global set/reset (GSRN) is also pro-
grammably ontrollevia register 7, register 7,
bit 7 is t to GSN will have nhe PCM
logicallowng the clock to opeate dlobal
set/reet. Thifunction allows the FPGbe reset
houffecting a clock this ent off-chip and used
elsewe in the syste. Bit f regster 7 affects the
functionality of the PCM dring cfiguration. If set to 1,
thibit enables thPCM to perate during configura-
on, after the CM hs beeconfigured. The PCM
functionality is pgramed via the bit stream. If regis-
ter 7, bit , thCM cannot function and its power
supplis disbled until after the configuration DONE
sigal gs hig.
PCM/FPGA Internal Interface
Writing and reading the PCM registers is done through
a simple asynchronous interface that connects with the
FPGA routing resources. Reads from the PCM by the
FPGA logic are accomplished by setting up the 3-bit
address, A[2:0], and then applying an active-high read
enable (RE) pulse. The read data will be available as
long as RE is held high. The address may be changed
while RE is high, to read other addresses. When RE
goes low, the data output bus is 3-stated.
Writes to the PCM by the FPGA logic are performed by
applying the write data to the data input bus of the
PCM, applying the 3-bit address to write to, and assert-
ing the write enable (WE) signal high. Data will be writ
ten by the high-going transition of the WE pulse.
The read enable (RE) and write enable (WE) signals
may not be active at the same time. For detang
information and specifications, see the Tim-
teristics section of this data sheet.
The LOCK signal output from the PCM to the FPGA
routing indicates a stable output clok signal from the
PCM. The LOCK signal is high when tPCM output
clock parameters fall withithe programmed values
and the PCM specificatios for jitter. Due to phase cor-
rections that occur internto the CM, the LOCK
nal might occasionlly pulse w when the output cloc
is out of specificion r only one or two cls
(high jitter due to tperatre, voltage fluc.)
To accommodate theulses, it is suggee
user integte the LOCK signal ovea period ble
to thir applition o achieve the esired usage of the
LCK sinal.
Wen the PM is powered up via register 7, bit 0, there
is a ake-up time associated with its operation. Follow-
ing the ake-up time, the PCM will begin to fully func-
on, and, following an acquisition time during which the
put clock may be unstable, the PCM will be in
steady-state operation. There is also a shutdown time
associated with powering off the PCM.The output clock
will be unstable during this period. Waveforms and tim-
ing parameters can be found in the Timing Characteris-
tics section of this data sheet.
The OCK gnal will also pulse high and low during
the aciition time as the put cck stabilizes. True
LOK is only achieved when the LCK signal is a solid
higAgain, it is suggestthat the user integrate the
OCK signal oe peod suitable to the subject
application.
Lattice Semiconductor
77
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM) (continued)
PCM Detailed Programming
Descriptions of bit fields and individual control bits in the PCM control registers are provided in Table 31. Refer to
Figure 46 for more information on the location of the PCM elements that are discussed. In the follong discussion,
the duty cycle is in the percentage of the clock period where the clock is high.
Table 31. PCM Control Registers
Bit #
Function
Register 0 Divider 0 Programming
Bits [3:0]
4-Bit Divider, DIV0, Value. This value enables the input clock o immeately be divide
value from 1 to 8. A 0 value (the default) indicates that DI0 is passd (no division
incurs less delay than dividing by 1. Hexadecimal valugreter than 8 for bits [3:0] yi
modulo 8 value. For example, if bits [3:0] are 1001 (9 he), the sult is divide y 1 (remar
9/8 = 1).
Bits [6:4]
Bit 7
Reserved.
DIV 0 Reset Bit. DIV0 may not be reset bGSRdepending on the value regisr 7, bit 7.
This bit may be set to 1 to reset DIV0 to its ult vaue. Bit 0 must set to (the default) to
remove the reset.
Register 1 Divider 1 Programming
Bits [3:0]
4-Bit Divider, DIV1, Value.This valus the feedback ck to ivided by a value from 1
to 8. A 0 value (the default) ndicates thDIV1 is bypassd (no ivision). Bypass incurs less
delay than dividing by 1. exadecimal values greatethan 8 or bit[3:0] yield their modulo 8
value. For example, if bits [3] are 1001 (9 hex), te esult is dide by 1 (remainder 9/8 = 1).
Bits [6:4]
Bit 7
Reserved.
DIV1 Reset BitDIV1 may not be reset by GSR, depending on the value of register 7, bit 7.
This bit may be t to 1 treset DIV1 to ifaulalue. Bit 0 must be set to 0 (the default) to
remove threset.
Register 2 Divider 2 Pgraming
Bits [3:0]
4-Bit Divir, DI2, Value. This es the tapped delay line output clock driven onto
ExpressCLK be divided by a vato 8. A 0 value (the default) indicates that DIV2 is
bpassed (no division). Bpass incurs less delay than dividing by 1. Hexadecimal values greater
than 8 fobits [3:0] yield eir modlo 8 value. For example, if bits [3:0] are 1001 (9 hex), the
result idivide by 1 (remader 9/= 1).
Bits [6:4
Bit 7
Reerved.
IV2 Reset Bit. Imanot be reset by GSRN, depending on the value of register 7, bit 7.
This bit may e set to 1 treset DIV2 to its default value. Bit 7 must be set to 0 (the default) to
remove the res
Register 3 DLL 2x De Prgramming
Bits [2:0]
Bits [5:3]
Bit 6
Duty-ction for the doubled clock period associated with the input clock high. The duty
cycle is of bit 6) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 6.
Duty-cycle selection for the doubled clock period associated with the input clock low. The duty
cycle is (value of bit 7) * 50% + ((value of bits [2:0]) + 1) * 6.25%. See the description for bit 7.
Master duty-cycle control for the first clock period of the doubled clock: 0 = less than or equal to
50%, 1 = greater than 50%.
Bit 7
Master duty-cycle control for the second clock period of the doubled clock: 0 = less than or equal
to 50%, 1 = greater than 50%. Example: Both clock periods having a 62.5% duty cycle, bits [7:0]
are 11 001 001.
78
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM) (continued)
Table 31. PCM Control Registers (continued)
Bit #
Function
Register 4 DLL 1x Duty-Cycle Programming
Bits [2:0]
Duty-Cycle/Delay Selection for Duty Cycle/Delays Less Than or quato 50%. The duty-
cycle/delay is (value of bits [7:6]) * 25% + ((value of bits [2:0]) + 1* 3.125%. Se the description
for bits [7:6].
Bits [5:3]
Bits [7:6]
Duty-Cycle/Delay Selection for Duty Cycle/Delays GreateThn 50%. The duty-cycle/delay
is (value of bits [7:6]) * 25% + ((value of bits [5:3]) + 1) * 3.125%. ee te description for bits [7:6].
Master Duty Cycle Control:
00: duty cycle 3.125% to 25%
01: duty cycle 28.125% to 50%
10: duty cycle 53.125% to 75%
11: duty cycle 78.125% to 96.875%
Example: A 40.625% duty cycle, bits [7:0] a01 XX 100, where X a on’t care because the
duty cycle is not greater than 50%.
Example: The PCM output clock soulbe delayed 96.875% (31/32of the input clock period.
Bits [7:0] are 11110XXX, which is 7825% rom bits [7:6] an18.75% rom bits [5:3]. Bits [2:0]
are don’t care (X) because ay is eater than 50%
Register 5 Mode Programming
Bit 0
Bit 1
Bit 2
DLL/PLL Mode Selection BDLL, 1 = PLL. Deflt is DLL mode.
Reserved.
PLL Phase Dtecor Feedback Input Section Bit0 = feedback signal from routing/
ExpressCLK, 1 = feeack from programmabdelay line output. Default is 0. Has no effect in
DLL mo.
Bit 3
Bit 4
Reservd.
1x2x Clk Section Bit for DLMode= 1x clock output, 1 = 2x clock output. Default is 1x
lock utput. Has no effect iLL me.
Bits [7:5]
eerved
Lattice Semiconductor
79
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Programmable Clock Manager (PCM) (continued)
Table 31. PCM Control Registers (continued)
Bit #
Function
Bits [5:4]
ExpressCLK Output Source Selector. Default is 00.
00: PCM input clock, bypass path through PCM
01: DLL output
10: tapped delay line output
11: divided (DIV2) delay line output
Bits [7:6]
System Clock Output Source Selector. Default is 00.
00: PCM input clock, bypass path through PCM
01: DLL output
10: tapped delay line output
11: reserved
Register 7 PCM Control Programming
Bit 0
Bit 1
Bit 2
PCM Analog Power Supply Switch. 1 = power suply o, 0 = power supplff.
PCM Reset. A value of 1 resets all PCM logifor PLL anLL modes.
DLL Reset. A value of 1 resets the clock nerion logic for DLL mode. No ivideror user reg-
isters are affected.
Bits [5:3]
Bit 6
Reserved.
PCM Configuration Operation E0 = normal configuratiooperation. During configu-
ration (DONE = 0), the PCM analog ppply will be off, tPCM put data bus is 3-stated,
and the LOCK signal is aserted to logi0. The PCM will ower p when DONE = 1.
1 = PCM operation durig onfiguration. The PCM ay be poered up (see bit 0) and begin
operation, or continue operatn.The setup of the PCcan be performed via the configuration bit
stream.
Bit 7
PCM GSRN Enble Bit. 0 = normal GSRN operion. 1 = GSRN has no effect on PCM logic, so
clock processing will not e interrupted bp et. Default is 0.
80
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
clock setup time and some margin, is the amount less
than one full clock cycle that the output clock is delayed
from the input clock.
Programmable Clock Manager (PCM)
(continued)
In some systems, it is desirable to operate logic from
several clocks that operate at different phases. This
technique is often used in mcroprocessor-based sys-
tems to transfer and proces dasnchronously
between functional areas, but withoincurring exces-
sive delays. Figure 8B shows nput clock and an
output clock operatg 10° out of phase. It also shows
a version of the input ock tat was shifted approxi-
mately 180using logic tes to create an inverter.
Note that tinverteclock is really ed more than
180° de to e progation delay erter. The
PCoutt clock does not suffer frelay. Addi-
tionay, the 80° shifted PCoutput be shifted
by some smaller amount teffecan eary 180° shifted
cloctt also accounts for ding efects.
PCM Applications
The applications discussed below are only a small
sampling of the possible uses for the PCM. Check the
Lattice website for additional application notes.
Clock Phase Adjustment
The PCM may be used to adjust the phase of the input
clock. The result is an output clock which has its active
edge either preceding or following the active edge of
the input clock. Clock phase adjustment is accom-
plished in DLL mode by delaying the clock. This is dis-
cussed in the Delay-Locked Loop (DLL) Mode section.
Examples of using the delayed clock as an early or late
phase-adjusted clock are outlined in the following par-
graphs.
In terms of degrees of phse shthe phase of a clock
is djustable in DLmode wh resolution relative to the
elay incremet (seTable 7):
An output clock that precedes the input clock can be
used to compensate for clock delay that is lae
to excessive loading. The preceding output
really not early relative to the input clock, but id
almost a full cycle. This is shown in igure 48A. e
amount of delay that is being comnsated for, plus
Phase Adjustment Delay)* 11.25,
Delay < 16
Phase Adjusent = ((Delay)* 11.25) – 360, Delay > 16
CLOCK DELAY AND SETUP
BEING COMPENSATED
DLL DELAY
INT CLOCK
OUTPUT CLCK
A. Generating an Early Clock
UNINTENDED PHASE
SHIFT DUE TO
INVERTER DELAY
DLL DELAY
CK
PCM OUTPUT CLOCK
INVERTED INPUT CLOCK
B. Multiphase Clock Generation Using the DLL
5-5979(F)
Figure 48. Clock Phase Adjustment Using the PCM
Lattice Semiconductor
81
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Resultant signals from the PCM must meet the FPGA
timing specifications. It is possible to specify pulses by
using duty-cycle adjustments that are too narrow to
function in the FPGA. For instance, if a 40 MHz clock is
doubled to 80 MHz and a 6.25% duty cycle is selected,
the result will be a 780 ps pulse that repeats every
12.5 ns.This pulse falls outside of te clock pulse width
specification and is not valid.
Programmable Clock Manager (PCM)
(continued)
High-Speed Internal Processing with Slow I/Os
The PCM PLL mode provides two outputs, one sent to
the global system clock routing of the FPGA and the
other to the ExpressCLK(s) that serve the FPGA I/Os.
The ExpressCLK output of the PCM has a divide capa-
bility (DIV2) that the system clock output does not.This
feature allows an input clock to be multiplied up to a
higher frequency for high-speed internal processing,
and also allows the ExpressCLK output to be divided
down to a lower frequency to accommodate off-FPGA
data transfers. For example, a 10 MHz input clock may
be multiplied (see Clock Multiplication in the Phase-
Locked Loop (PLL) Mode subsection) to 25 MHz (DIV0
= 4, DIV1 = 5, DIV2 = 2) and output to the FPGA
ExpressCLK.This allows the I/Os of the circuit to run at
25 MHz ((2 * 5)/4 * 10 MHz). The system clock will run
at DIV2 times the ExpressCLK rate, which is 2 times
25 MHz, or 50 MHz. This setup allows for internal pro-
cessing to occur at twice the rate of on/off device I/
transfers.
Using divider DIV2, it is possble to spea clock mul-
tiplication factor of 64 betwn te input clock and the
output system clock. As mentied aove, the resultant
frequency must meeall FPGA ting specifications.
The input clock mualso mt the minimum cifica-
tions. An input ock te thais below the
minimum canot used even if the multiplis
within the alloable nge.
The use the CM to tweak a clocsigal to eliminate
a articular proem, such as a single etup ime viola-
n, is discouraged. A small shift idelauty cycle, or
pe to crrect a single-int probm is in essence
an anhronous patcto a nchroous system, mak-
g the system less stablThis type of local problem,
opposed to a gclocontrol issue like device-
ide clock dely, causually be eliminated through
more robusdesn pratices. If this type of change is
made, thdesigner must be aware that depending on
the extent ohe change made, the design may fail to
opete correcy in a different speed grade or voltage
grade .g., 3C vs. 3T), or even in a different production
ohame device.
PCM Cautions
Cautions do apply when using the M. There ae a
number of configurations that are possible in the PCM
that are theoretically valid, but manot prouce viable
results. This section descries somf thse situa-
tions, and should leave tusewith an understandi
of the types of pitfalls that st be voided when
fying clock signals.
Diver DIV2 is available in DLL mode for the Express-
LK output, but its use is not recommended with duty-
cle adjusted clocks.
82
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Initialization
FPGA States of Operation
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When VDD reaches the
voltage at which portions of the FPGA begin to operate
(2.5 V to 3 V for the OR3Cx, 2.2 V to 2.7 V for the
OR3Txxx), the I/Os are conged bsed on the con-
figuration mode, as dermined by te mode select
inputs M[2:0]. A tim-out elay is initiated when VDD
reaches between 3.V and 4.V (OR3Cxx) or 2.7 V to
3.0 V (OR3Txto allthpower supply voltage to
stabilize. ThINIT and DONE outputs are low. At pow-
erup, if VDD oes noise from 2.0 V in less than
25 ms, e usshold delay coninputting
a lointo IT, PRGM, or RESET untireater
than te recomended minmum opervoltage
(75 V or OR3Cxx commciadevices and 3.0 V for
OR3Tdevices).
Prior to becoming operational, the FPGA goes through
a sequence of states, including initialization, configura-
tion, and start-up. Figure 49 outlines these three FPGA
states.
POWERUP
– POWER-ON TIME DELAY
INITIALIZATION
– CLEAR CONFIGURATION
MEMORY
– INIT LOW, HDC HIGH, LDC LOW
RESET,
INIT,
OR
PRGM
LOW
BIT
ERROR
YES
YES
NO
NO
At the end of initialization, he default configuration
otion is that the cfiguratin RAM is written to a low
state. This prevnts srts rior to configuration. As a
configuration opti, after the first configuration (i.e., at
reconfigurn), ser can reconfigure without
clearinthe iernal configuration RAM first. The
aive-lowopendrain initialization signal INIT is
eased anmust be pulled high by an external resis-
tor wen initialization is complete. To synchronize the
configuation of multiple FPGAs, one or more INIT pins
hould be wire-ANDed. If INIT is held low by one or
re FPGAs or an external device, the FPGA remains
in the initialization state. INIT can be used to signal that
the FPGAs are not yet initialized. After INIT goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled, and the FPGA enters the configuration
state.
CONFIGURATION
– M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME
WRITTEN
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
RESET
OR
P
LO
START-UP
PRGM
LOW
– ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
OPATION
4529(F
Figure 49. GA States of Oper
The high during configuration (HDC), low during config-
uration (LDC), and DONE signals are active outputs in
the FPGA’s initialization and configuration states. HDC,
LDC, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
Lattice Semiconductor
83
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
not used during the configuration process are
3-stated with internal pull-ups.
FPGA States of Operation (continued)
If configuration has begun, an assertion of RESET or
PRGM initiates an abort, returning the FPGA to the ini-
tialization state. The PRGM and RESET pins must be
pulled back high before the FPGA will enter the config-
uration state. During the start-up and operating states,
only the assertion of PRGM causes a reconfiguration.
Warning: During configuration, all OR3Txxx inputs
have internal pull-ups enabled. If these inputs are
driven to 5V, they will draw substantial current (≅ 5 ma).
This is due to the fact that the inputs are pulled up to
3V.
During configuration, the PIC nd PLC latchs/FFs are
held set/reset and the interal BII buffers are 3-
stated. The combinatorial logegins o function as
the FPGA is configurd. Figure 0 hows the general
waveform of the initlization, configuration, and start-
up states.
In the master configuration modes, the FPGA is the
source of configuration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after INIT goes high.
Configuraon
When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count configuration clock
cycles applied to the FPGA. As each configuration data
frame is supplied to the FPGA, it is internally assem-
bled into data words. Each data word is loaded into the
internal configuration memory. The configuration load
ing process is complete when the internal length c
equals the loaded length count in the length count fiel
and the required end of configuration frame iwritten.
The ORSers FPGA functionay is determined by
the state of intal configuratin RAThis onfigura-
n RM can be loaded in a numer of ferent
ms. In tese configuraon mode, the FPGA can
act a master or a slve of ther dvices in the sys-
m. The decision as to ich cfiguration mode to
e is a system diss. Configuration is dis-
ussed in deta, inclding the configuration data format
and the configurion mdes used to load the configu-
ration dain the FGA, following a description of the
start-up sta.
All OR3Cxx I/Os operate as TTL inputs durg configu-
ration (OR3Txxx I/Os are CMOS-only). All I/Ohat are
V
DD
SET
PRGM
INI
M[3:0]
CCLK
HDC
USER I/O
INTERNAL
RESET
(gsrn)
INITIALIZATION
CONFIGURATION
START-UP
OPERATION
5-4482(F)
Figure 50. Initialization/Configuration/Start-Up Waveforms
84
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
DONE is an open-drain bidirectional pin that may
include an optional (enabled by default) pull-up resistor
to accommodate wired ANDing.The open-drain DONE
signals from multiple FPGAs can be tied together
(ANDed) with a pull-up (internal or external) and used
as an active-high ready signalan active-low PROM
enable, or a reset to other ortions of the system.
When used in SYNC modese ADed DONE pins
can be used to synchonize the othr two start-up
events, since they n all e synchronized to the same
external signal. This nal wilnot rise until all FPGAs
release their ONE pin, aowing the signal to be
pulled high
FPGA States of Operation (continued)
Start-Up
After configuration, the FPGA enters the start-up
phase. This phase is the transition between the config-
uration and operational states and begins when the
number of CCLKs received after INIT goes high is
equal to the value of the length count field in the config-
uration frame and when the end of configuration frame
has been written. The system design issue in the start-
up phase is to ensure the user I/Os become active
without inadvertently activating devices in the system
or causing bus contention. A second system design
concern is the timing of the release of global set/reset
of the PLC latches/FFs.
The deult fORCis the CCLKnchro-
nizestaup mode where DONE ion the
first CCLK ring edge, C1 (se Figure ince this is
a syncronized start-up mde, the open-drain DONE
signn be held low extery to stp the occurrence
of the other two start-up ventOce the DONE pin
has been released and puld up to a high level, the
oher two start-up eents cabe programmed individu-
ally to either hapen imeiately or after up to four ris-
ing edges of CCL(Di, Di + 1, Di + 2, Di + 3, Di + 4).
The defaulfor bevents to happen immediately
after DNE is eleased and pulled high.
There are configuration options that control the relative
timing of three events: DONE going high, release of the
set/reset of internal FFs, and user I/Os becoming
active. Figure 51 shows the start-up timing for ORC
FPGAs. The system designer determines the reative
timing of the I/Os becoming active, DONE g,
and the release of the set/reset of internal
ORCA Series FPGA, the three events can occy
arbitrary sequence. This means thathey can ocr
before or after each other, or then occur simulta-
neously.
ommonused design technique is to release
DOE one or more clock cycles before allowing the I/O
to becme active. This allows other configuration
devices, such as PROMs, to be disconnected using the
NE signal so that there is no bus contention when
the I/Os become active. In addition to controlling the
FPGA during start-up, other start-up techniques that
avoid contention include using isolation devices
between the FPGA and other circuits in the system,
reassigning I/O locations, and maintaining I/Os as 3-
stated outputs until contentions are resolved.
There are four main start-p modes: CCLK_NOSYNC,
CCLK_SYNC, UCLK_NOSYNC, ad UCLK_SYNC.
The only difference etwen the modes starting wi
CCLK and those arting with UCLK is that for the
UCLK modes, a ser lock must be suppli
start-up logic. The ting ostart-up event
based upon this user ck, rather than CCif-
ference beeen the SYNC and NSYNC modes is
that or SYNC moe, the timing owo of thstart-up
ents, elease of the set/reset of iernal Fs, and the
I/Oecomig active is trigered by the rise of the
externDONE pin followd ba viable number of
g clock edges (eier CCLK or UCLK). For the
NOYNC mode, the timg of tese two events is
bsed only on eCLK r UCLK.
Each of these start-up options can be selected during
bit stream generation in ispLEVER, using Advanced
Options. For more information, please see the
ispLEVER documentation.
Lattice Semiconductor
85
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Reconfiguration
FPGA States of Operation (continued)
To reconfigure the FPGA when the device is operating
in the system, a low pulse is input into PRGM. The con-
figuration data in the FPGA is cleared, and the I/Os not
used for configuration are 3-stated. The FPGA then
samples the mode select inputs anbegins reconfigu-
ration. When reconfiguration is comle, DONE is
released, allowing it to be pulld high.
CCLK_NOSYNC
F
DONE
C1
C1
C1
C2
C2
C2
C3
C3
C3
C4
C4
C4
I/O
Partial Reconfiguration
GSRN
ACTIVE
All ORCA device failies habeen designeallow
a partial reconuratn of tFPGA at ans
is done by sting bit stream option in the
configuration equee that tells the PGA to set
all of thconfigration RAM durinrecnfiguration.
Theonly thfiguration frames tare tbe modi-
fid need to be rewritten, therebredug he configu-
riotime.
CCLK_SYNC
DONE IN
DONE
F
Di + 4
Di + 4
C1, C2, C3, OR C4
I/O
Di Di + 1
Di Di + 1
Di + 2
Di + 2
Di + 3
Di + 3
Othebistream optioare so avilable that allow
e portion of the FPGA remain in operation while a
tial reconfigurabg done. If this is done, the
ser must be reful o not cause contention between
the two cofigurons (e bit stream resident in the
FPGA athe partireconfiguration bit stream) as the
second recofiguration bit stream is being loaded.
GSRN
ACTIVE
UCLK
UCLK_NOSYNC
F
DONE
I/O
C1
U1
U2
U2
U3
U4
U4
her nfiguration Options
U1
U1
U3
U3
GSRN
ACTIVE
Theare many other configuration options available to
e user that can be set during bit stream generation in
pLEVER. These include options to enable boundary
scan and/or the microprocessor interface (MPI) and/or
the programmable clock manager (PCM), readback
options, and options to control and use the internal
oscillator after configuration.
U
U4
UCLK_SYNC
ONE IN
DONE
/O
F
C1
1, U2, U3, OR U4
Di Di +
Other useful options that affect the next configuration
(not the current configuration process) include options
to disable the global set/reset during configuration, dis-
able the 3-state of I/Os during configuration, and dis-
able the reset of internal RAMs during configuration to
allow for partial configurations (see above). For more
information on how to set these and other configuration
options, please see the ispLEVER documentation.
Di
Di + 3
Di + 3
Di + 4
GSR
ACTIVE
Di + 2
IOD
SYNCHRONON UNCERTAINTY
Note: F = finished, no more CLKs required.
5-2761(F)
Figure 51. Start-Up Waveforms
86
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Configuration Data Frame
Configuration Data Format
Configuration data can be presented to the FPGA in
two frame formats: autoincrement and explicit. A
detailed description of the frame formats is shown in
Figure 52, Figure 53, and Table 32.The two modes are
similar except that autoincrment mode uses assumed
address incrementation to de thbit stream size,
and explicit mode reqires an addres for each data
frame. In both case, the eader frame begins with a
series of 1s and a pamble o0010, followed by a
24-bit length nt fielrepesenting the total number
of configuraon clocks needed to complete the loading
of the FPG.
The ispLEVER Development System interfaces with
front-end design entry tools and provides tools to pro-
duce a fully configured FPGA. This section discusses
using the ispLEVER Development System to generate
configuration RAM data and then provides the details
of the configuration frame format.
The ORCA OR3Cxx and OR3Txxx Series FPGAs are
bit stream compatible.
Using ispLEVER to Generate
Configuration RAM Data
Follwing he heder frame is a maframe.
(Nothat tID frame was optional iORCA 2C
and 2TxxA Series.)
The configuration data bit stream defines the I/O func-
tionality, logic, and interconnections within the FPGA.
The bit stream is generated by the development sys-
tem. The bit stream created by the bit stream genera
tion tool is a series of 1s and 0s used to write the FPA
configuration RAM. It can be loaded into the FPGA
using one of the configuration modes discusr.
The ID ame contains ata ud to etermine if the bit
stream is being loaded to he coct type of ORCA
FPGA (i.e., a bit seam gerated for an OR3T55 is
eing sent to n ORT55). rror checking is always
enabled for Seri3 dees, through the use of an
8-bit chem. Obit in the ID frame also selects
betwen the utoincrement and explicit address modes
for his ld of e configuration data.
In the bit stream generator, the designer sel
options that affect the FPGA’s functionality. Usie
output of the bit stream generator, ircuit_name.bit,
the development system’s downoaool can load the
configuration data into the ORCA serieFPGA evalua-
tion board from a PC or wrkstation.
A onfiguratn data frame follows the ID frame. A data
framstarts with a 01-start bit pair and ends with
enough 1-stop bits to reach a byte boundary. If using
utoincrement configuration mode, subsequent data
fmes can follow. If using explicit mode, one or more
address frames must follow each data frame, telling the
FPGA at what addresses the preceding data frame is
to be stored (each data frame can be sent to multiple
addresses).
Alternatively, a user can ogram PROM (such aa
Serial ROM or a stadard ERO) and load the FP
from the PROM. he dvelopment system’s
programming tool rduces a file in .mks o
mat.
Following all data and address frames is the postam-
ble. The format of the postamble is the same as an
address frame with the highest possible address value
with the checksum set to all ones.
Lattice Semiconductor
87
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Configuration Data Format (continued)
CONFIGURATION DATA
CONFIGURATION DATA
0
0 1 0
0 1
0 1
0 0
PREAMBLE LENGTH
COUNT
ID FRAME
CONFIGURATION
DATA FRAME 1
CONFIGURATION
DATA FRAME 2
POSMBLE
CONFIGURATION HEADER
5-5759(F)
Figure 52. Serial Configuration Data Format—Autoincrement Me
CONFIGURATION DATA
NFIGATION DA
0
0
1
0
0
1
0 0
0 1
0 0
0 0
LENGTH
COUNT
PREAMBLE
CONFIGURATION
DATA FRAME 1
ADESS
AME 1
CONFIGURATION
DATA FRAME 2
ADDRE
RAME 2
ID FRAME
POSTAMBLE
CONFIGURATION HEADER
5-5760(F)
Figure 53. Serial Configurta Format—ExM
Table 32. Configuration Frame Format ad Contents
11110010 Preamble
24-bit Lengtount
1111111
Header
Cnfiguration frame length.
Trailing header—8 ts.
0101 1111 111 111ID frame he
Cofiguration de
Resrved [41:0]
ID
00 = autoincrent, 01 = explicit.
Resset 0.
ID Frame
20-
Chcksum
11111111
01
8-bit m.
Eight stop bits (high) to separate frames.
Data rame header.
Confiratin
Dat
Frame
(ped r each
Data Bs
Nuber of data bits depends upon device.
String of 0 bits added to bit stream to make frame header, plus data
bits reach a byte boundary.
Alignmeni= 0
Cheksum
1111
8-bit checksum.
data frame)
Eight stop bits (high) to separate frames.
Address frame header.
0
Configuration
Address
ress Bits
hecksum
14-bit address of location to start data storage.
8-bit checksum.
Frame
11111111
Eight stop bits (high) to separate frames.
Postamble header.
00
Postamble
11111111 111111
1111111111111111
Dummy address.
16 stop bits.*
* In MPI configuration mode, the number of stop bits = 32.
Note: For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must
be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive
integer. The number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. Note also that the bit
stream generator tool supplies a bit stream that is compatible with all configuration modes, including slave parallel mode.
88
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Configuration Data Format (continued)
The length and number of data frames and information on the PROM size for the Series 3 FPGAs are given in
Table 33.
Table 33. Configuration Frame Size
Devices
OR3T20
856
OR3T30
984
OR3T55
124
C/T8
49
OR3T125
1880
# of Frames
Data Bits/Frame
202
232
29
352
442
Configuration Data (# of frames x # of data
bits/frame)
172,912
228,288
362,080
526,592
830,960
Maximum Total # Bits/Frame (align bits, 01
frame start, 8-bit checksum, 8 stop bits)
224
256
312
37
464
Maximum Configuration Data (# bits/frame
x # of frames)
191,744
191,912
251,94
252,072
386,880
387,048
562,496
2,64
872,320
872,488
Maximum PROM Size (bits)
(add configuration header and postamble)
Bit Stream Error Checking
There are three different types of bit stream erecking perfored ithe ORCA Series 3 FPGAs:
ID frame, frame alignment, and CRC checking.
The ID data frame is sent to a dedicad location in the FPAThis ID frme contains a unique code for the device
for which it was generated. Ts device ode is compared to the ternal code of the FPGA. Any differences are
flagged as an ID error. Ths frame is automatically createby the bstream generation program in ispLEVER.
Each data and address frme in thFPGA begins fre start pair of bits and ends with eight stop bits set to
1. If any of the preious stop twere a 0 when a frae start pair is encountered, it is flagged as a frame align-
ment error.
Error checking is aldoe on the FPGA me by means of a checksum byte. If an error is found on eval-
uation of he checksum byte, then a ecksty error is flagged. The checksum is the XOR of all the data
bytes, from he starof frame up tand including the bytes before the checksum. It applies to the ID, address, and
datframes.
Wany of the three posible errors cur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will
remain his state until her e ESET or PRGM pins are asserted.
If ung either of the MI modes to configure the FPGA, the specific type of bit stream error is written to one of the
MPregisters by the FPGconfiguration logic. The PGRM bit of the MPI control register can also be used to reset
out of the erron anrestart configuration.
Lattice Semiconductor
89
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Master Parallel Mode
FPGA Configuration Modes
The master parallel configuration mode is generally
used to interface to industry-standard, byte-wide mem-
ory, such as the 2764 and larger EPROMs. Figure 54
provides the connections for master parallel mode.The
FPGA outputs an 18-bit address on A[17:0] to memory
and reads 1 byte of configuration da n thrising
edge of RCLK. The parallel byes are internly serial-
ized starting with the least gnificnt bit, D0. D[7:0] of
the FPGA can be connected o D[7:0] of the micropro-
cessor only if a standprom le fmat is used. If a
.bit or .rbt file is usefrom ispLEVER, then the user
must mirror the bytein the .t or .rbt file OR the
.bit or .rbt file uhand anconnect D[7
FPGA to D[07] of e microprocessor.
There are eight methods for configuring the FPGA.
Seven of the configuration modes are selected on the
M0, M1, and M2 inputs. The eighth configuration mode
is accessed through the boundary-scan interface. A
fourth input, M3, is used to select the frequency of the
internal oscillator, which is the source for CCLK in
some configuration modes.The nominal frequencies of
the internal oscillator are 1.25 MHz and 10 MHz. The
1.25 MHz frequency is selected when the M3 input is
unconnected or driven to a high state.
There are three basic FPGA configuration modes:
master, slave, and peripheral. The configuration data
can be transmitted to the FPGA serially or in parallel
bytes. As a master, the FPGA provides the control sig-
nals out to strobe data in. As a slave device, a clock is
generated externally and provided into the CCLK input.
In the three peripheral modes, the FPGA acts as a
microprocessor peripheral. Table 34 lists the functions
of the configuration mode pins. Note that two configura-
tion modes previously available on the OR2Cxx and
OR2C/TxxA devices (master parallel down and syn
chronous peripheral) have been removed for Series 3
devices.
UT
CC
TO DAISY-
CHAINED
DEVICES
A:0]
A[17:0]
D[7:0]
D[7:0]
DONE
ORCA
SERIES
FPGA
PROM
OE
C
Table 34. Configuration Modes
ROGRAM
PRGM
M2
M1
HDC
LDC
RCLK
VDD
VDD OR GND
Confguration
M2 M1 M0 CCLK
Data
ode
Output aster Seal
Input SlaParallel
Output Mroprcessor:
Motola* Pow-
erPC
M0
0
0
0
0
0
1
0
1
0
Serial
Para
Par
igure 54. Master Parallel Configuration Schematic
In master parallel mode, the starting memory address
is 00000 Hex, and the FPGA increments the address
for each byte loaded.
0
1
1
OutpMicroprocessor
Parael
Parallel
Intel i960
1
1
1
0
0
1
1
1
0
1
Ouput Master arallel
Output Async PepheraParallel
eservd
One master mode FPGA can interface to the memory
and provide configuration data on DOUT to additional
FPGAs in a daisy-chain. The configuration data on
DOUT is provided synchronously with the falling edge
of CCLK. The frequency of the CCLK output is eight
times that of RCLK.
Input
e Sial
Serial
* Motorola is a registered trotorola, Inc.
90
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
configuration, the high on the FPGA's DONE disables
the serial ROM.
FPGA Configuration Modes (continued)
Master Serial Mode
Serial ROMs can also be cascaded to support the con-
figuration of multiple FPGAs or to load a single FPGA
when configuration data requirements exceed the
capacity of a single serial RM. After the last bit from
the first serial ROM is readthe rROM outputs
CEO low and 3-states te DATA outpt. The next serial
ROM recognizes the low on CE ut and outputs con-
figuration data on te DTA output. After configuration
is complete, the FPGDOE output into CE disables
the serial RMs.
In the master serial mode, the FPGA loads the configu-
ration data from an external serial ROM. The configura-
tion data is either loaded automatically at start-up or on
a PRGM command to reconfigure. The ATT1700A
Series Serial PROMs can be used to configure the
FPGA in the master serial mode. This provides a sim-
ple 4-pin interface in a compact package.
Configuration in the master serial mode can be done at
powerup and/or upon a configure command. The sys-
tem or the FPGA must activate the serial ROM's
RESET/OE and CE inputs. At powerup, the FPGA and
serial ROM each contain internal power-on reset cir-
cuitry that allows the FPGA to be configured without
the system providing an external signal. The power-on
reset circuitry causes the serial ROM's internal addrss
pointer to be reset. After powerup, the FPGA automi-
cally enters its initialization phase.
This FPGA/erial ROM interface is d in applica-
tions in hich seal ROM stores onfigura-
tion ogras. In these applictions,
configration rogram to be loaded is sed at the
RM lation that follows te lat address for the previ-
ous coguration progm. Treaon the interface in
Figure 55 will not work in is apcation is that the low
ouput on the INIT ignal wold reset the serial ROM
ddress point, caung thfirst configuration to be
reloaded.
The serial ROM/FPGA interface used depeh
factors as the availability of a system reset pl-
ability of an intelligent host to generae a config
command, whether a single serial OM is used or mul-
tiple serial ROMs are cascadedwhher the serial
ROM contains a single or multiple conuration pro-
grams, etc. Because of diering system requirements
and capabilities, a single PGA/seal ROM interface is
generally not appropiate r all aplications.
In some apcatiothere can be contention on the
FPGA'DIN pn. During configuration, DIN receives
cnfiguratn data, and after configuration, it is a user
I/OIf there icontention, an early DONE at start-up
(seleed in ispLEVER) may correct the problem. An
alternatve is to use LDC to drive the serial ROM's CE
n. In order to reduce noise, it is generally better to run
thmaster serial configuration at 1.25 MHz (M3 pin
tied high), rather than 10 MHz, if possible.
Data is read in tFPA sequentially from tial
ROM. The DATA out from the serial RO
nected directly into tDN input of the FP
CCLK ouut from the FPGA is coned to LK
input f the rial ROM. During thconfiguration pro-
ces, CCLK cls one data bit on each risg edge.
TO DAISY-
CHAINED
DEVICES
DOUT
DATA
CLK
DIN
CCLK
ATT1700A
Sinhe daa and clock ae direct connects, the
FPGAeral ROM design ass tuse the system or
A to enable the RSET/OE anCE of the serial
RO(s). There are sevel metods for enabling the
srial ROM’s RE anCE inputs. The serial
ROM’s RESEgrammable to function with
RESET active-hOE active-low or RESET active-
low and OE activeh.
CE
DONE
INIT
RESET/OE
CEO
ORCA
SERIES
FPGA
DATA
CLK
PRGM
ATT1700A
CE
M2
M1
M0
In Figure 55, serial ROMs are cascaded to configure
multiple daisy-chained FPGAs. The host generates a
500 ns low pulse into the FPGA's PRGM input. The
FPGA’s INIT input is connected to the serial ROMs’
RESET/OE input, which has been programmed to
function with RESET active-low and OE active-high.
The FPGA DONE is routed to the CE pin. The low on
DONE enables the serial ROMs. At the completion of
RESET/OE
CEO
TO MORE
SERIAL ROMs
AS NEEDED
PROGRAM
5-4456.1(F)
Figure 55. Master Serial Configuration Schematic
Lattice Semiconductor
91
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA Configuration Modes (continued)
DOUT
CCLK
TO DAISY-
CHAINED
DEVICES
Asynchronous Peripheral Mode
PRGM
D[7:0]
8
Figure 56 shows the connections needed for the asyn-
chronous peripheral mode. In this mode, the FPGA
system interface is similar to that of a microprocessor-
peripheral interface.The microprocessor generates the
control signals to write an 8-bit byte into the FPGA.The
FPGA control inputs include active-low CS0 and active-
high CS1 chip selects and WR and RD inputs. The chip
selects can be cycled or maintained at a static level
during the configuration cycle. Each byte of data is writ-
ten into the FPGA’s D[7:0] input pins. D[7:0] of the
FPGA can be connected to D[7:0] of the microproces-
sor only if a standard prom file format is used. If a .bit
or .rbt file is used from ispLEVER, then the user must
mirror the bytes in the .bit or .rbt file OR leave the .bit or
.rbt file unchanged and connect D[7:0] of the FPGA to
D[0:7] of the microprocessor.
RDY/BUSY
INIT
DONE
MICRO-
PROCESSOR
ORCA
ADDRESS
C
DECODE LOGIC
S1 SERIE
FPGA
BUS
CONTROLL
WR
DD
2
1
M0
HDC
LD
Figure 56. Asnchronous Peripral Configuation
icrprocessor Interface (MPI) Mode
The FPGA provides an RDY/BUSY status output to indi-
cate that another byte can be loaded. A low on RDY
BUSY indicates that the double-buffered hold/shift r
isters are not ready to receive data, and this pin must
be monitored to go high before another byte of data
can be written. The shortest time RDY/BUis low
occurs when a byte is loaded into the hold regter and
the shift register is empty, in which e the byte s
immediately transferred to the shregister. The long-
est time for RDY/BUSY to remain w occuwhen a
byte is loaded into the holdig regisr anthe shift
register has just started ifting configuration data in
configuration RAM.
The i-in MPI in Seris 3 FGAs s designed for use
configuring the FPGA. gure 57 and Figure 58 show
glueless interffA configuration and read-
back from the owerC and i960 processors, respec-
tively. Wheenabd by he mode pins, the MPI
handles configurion/readback control and hand-
shaking with he host processor. For single FPGA con-
figurion, the st sets the configuration control
registeRGM bit to zero then back to a one and, after
dint the INIT signal is high in the MPI status
rester, transfers data 8 bits at a time to the FPGA’s
[7:0input pins.
configuring multiple FPGAs through daisy-chain
operation is desired, the MP_DAISY bit must be set in
the configuration control register of the MPI. Because
of the latency involved in a daisy-chain configuration,
the MP_HOLD_BUS bit may be set to zero rather than
one for daisy-chain operation. This allows the MPI to
acknowledge the data transfer before the configuration
information has been serialized and transferred on the
FPGA daisy-chain. The early acknowledgment frees
the host processor to perform other system tasks. Con-
figuring with the MP_HOLD_BUS bit at zero requires
that the host microprocessor poll the RDY/BUSY bit of
the MPI status register and/or use the MPI interrupt
capability to confirm the readiness of the MPI for more
configuration data.
The RDY/BUSY status is also ailable on the D7 pin
enabling the chip slects, setting WR high, nd apply-
ing RD low, here the D put provides aoutput
enable fohe Dpin when RD is low. The 6:0] pis
are not enad to drve when RD ilow and, therefore,
only act as inpt pns in asynchroous erheral
mde. Onally, the user caignore the RDY/BUSY
status and mply wait until the ximutime it would
take fothRDY/BUSY lgo hih, indicating the
FPGA is ready for mofore writing the next
data byte.
92
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Configuration readback can also be performed via the
MPI when it is in user mode.The MPI is enabled in user
mode by setting the MP_USER bit to 1 in the configura-
tion control register prior to the start of configuration or
through a configuration option. To perform readback,
the host processor writes the -bit readback start
address to the readback adress registers and sets the
RD_CFG bit to 0 in the confition ontrol register.
Readback data is retuned 8 bits at time to the read-
back data register d is alid when the DATA_RDY bit
of the status register 1. Thee is no error checking
during readbck. A flow cht of the MPI readback
operation is shown in Figure 60. The RD_DATA pin
used for decated FGA readback d during
MPI reaback
FPGA Configuration Modes (continued)
There are two options for using the host interrupt
request in configuration mode. The configuration con-
trol register offers control bits to enable the interrupt on
either a bit stream error or to notify the host processor
when the FPGA is ready for more configuration data.
The MPI status register may be used in conjunction
with, or in place of, the interrupt request options. The
status register contains a 2-bit field to indicate the bit
stream error status. As previously mentioned, there is
also a bit to indicate the MPI’s readiness to receive
another byte of configuration data. A flow chart of the
MPI configuration process is shown in Figure 59. The
MPI status and configuration register bit maps can be
found in the Special Function Blocks section and MPI
configuration timing information is available in the Tim-
ing Characteristics section of this data sheet.
PWER ITH
LID M:0]
TO DA-
DOUT
CHAINE
CCLK
DEVICES
8
D[7:0]
A[27:31]
CLKOUT
RD/WR
TA
D[7:0]
A[4:0]
WE ONFIGURATION
CONTROL REGISTER BITS
MPI_CLK
MPI_RW
MPI_ACK
MPI_BI
MPI_IRQ
MPI_STB
CS0
ORCA
POWERPC
SEES 3
PGA
READ STATUS REGISTER
BI
IRQx
TS
A26
A25
NE
NO
INIT = 1?
I
HDC
LDC
C
YES
5-57F)
READ STATUS REGISTER
Note: FPGA shown s a mory-mapped peripheral and
CS1. Other dedischemes are possible uor
CS1.
YES
DONE
DONE = 1?
Figure 5. PowerPC/MPI Configuaton Satic
NO
BIT STREAM ERROR?
NO
i960 YSTEM CLOCK
YES
ERROR
8
TO DAISY-
CHAINED
DEVICES
DOUT
CCLK
AD[7:0]
D[
CLKIN
W/R
MPI_CL
I_RW
MACK
MPI_RQ
RDYRCV
XIN
A
NO
ORCA
SERIES 3
FPGA
DATA_RDY = 1?
YES
MPI_ALE
MPI_STRB
MPI_BE0
MPI_BE1
i960
ADS
BE0
BE1
VDD
DONE
INIT
HDC
LDC
WRITE DATA TO
CONFIGURATION DATA REG
CS1
CS0
5-5762(F)
5-5763(F)
Note: FPGA shown as only system peripheral with fixed chip select
signals. For multiperipheral systems, address decoding and/or
latching can be used to implement chip selects.
Figure 59. Configuration Through MPI
Figure 58. i960/MPI Configuration Schematic
Lattice Semiconductor
93
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA Configuration Modes (continued)
ENABLE MICROPROCESSOR
INTERFACE IN USER MODE
SET READBACK ADDRESS
WRITE RD_CFG TO 0
IN CONTROL REGISTER 1
READ STATUS REGISTER
DATA_RDY = 1
NO
YES
READATA REGISTER
NO
ERROR
TA = 0xFF?
YES
READ DATA RISTER
NO
ERRR
DATA = xFF?
YES
DATA REGISTER
NO
START OF FRAME
FOUND?
ERRR
YES
READ UNTIL END OF FRAME
WRIRD_CFG
YES
NO
FINISHED
READBACK?
TO IN
CONTROL
EGISTER 1
ST
5-5764(F)
Figure 60. Readback Through MPI
94
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Slave Parallel Mode
FPGA Configuration Modes (continued)
The slave parallel mode is essentially the same as the
slave serial mode except that 8 bits of data are input on
pins D[7:0] for each CCLK cycle. Due to 8 bits of data
being input per CCLK cycle, the DOUT pin does not
contain a valid bit stream foslave parallel mode. As a
result, the lead device cannt usin the slave
parallel mode in a daiy-chain confiuration.
Slave Serial Mode
The slave serial mode is primarily used when multiple
FPGAs are configured in a daisy-chain (see the Daisy-
Chaining section). It is also used on the FPGA evalua-
tion board that interfaces to the download cable. A
device in the slave serial mode can be used as the lead
device in a daisy-chain. Figure 61 shows the connec-
tions for the slave serial configuration mode.
Figure 62 is a scheatiof the connections for the
slave parallel configuion mode. WR and CS0 are
active-low cp select sils, and CS1 is an active-
high chip sect sign. These chip selts allow the
user to confiure muiple FPGAs irallel
modusg an 8bit data bus comof the
FPGs. Thee chip selects cn then d to select
the FPA(s) to be configud wita given bit stream.
The hselects must be avfor each valid CCLK
cycle until the device habeen opletely pro-
grammed. They can be inative between cycles but
mst meet the setuand hotimes for each valid pos-
itive CCLK. D[7] of te FGA can be connected to
D[7:0] of the micrrocessor only if a standard prom
file format used.bit or .rbt file is used from
ispLEVR, thn the user must mirror the bytes in the
.bor .rbt le OR leave the .bit or .rbt file unchanged
aconnect D[7:0] of the FPGA to D[0:7] of the micro-
procsor.
The configuration data is provided into the FPGA’s DIN
input synchronous with the configuration clock CCLK
input. After the FPGA has loaded its configuration data,
it retransmits the incoming configuration data on
DOUT. CCLK is routed into all slave serial mode
devices in parallel.
Multiple slave FPGAs can be loaded with identical co-
figurations simultaneously. This is done by loading e
configuration data into the DIN inputs in parallel.
C
DEV
DUT
INI
ORCA
SERIES
FGA
MICRO-
PROCESSOR
OR
DOWNLOAD
CABLE
GM
NE
CC
DIN
8
D[7:0]
DONE
INIT
ORCA
SERIES
FPGA
CCLK
MICRO-
PROCESSOR
OR
VDD
PRGM
M2
M1
M0
VDD
HDC
LDC
SYSTEM
CS1
CS0
WR
5-4485(F)
Fure 61. Slave Serl Cofiuration Schematic
M2
M1
M0
HDC
LDC
5-4487(F)
Figure 62. Slave Parallel Configuration Schematic
Lattice Semiconductor
95
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The loading of configuration data continues after the
lead device has received its configuration data if its
internal frame bit counter has not reached the length
count. When the configuration RAM is full and the num-
ber of bits received is less than the length count field,
the FPGA shifts any additional data ouon DOUT.
FPGA Configuration Modes (continued)
Daisy-Chaining
Multiple FPGAs can be configured by using a daisy-
chain of the FPGAs. Daisy-chaining uses a lead FPGA
and one or more FPGAs configured in slave serial
mode. The lead FPGA can be configured in any mode
except slave parallel mode. (Daisy-chaining is available
with the boundary-scan ram_w instruction discussed
later.)
The configuration data is read into N ole devices
on the positive edge of CCLK, nd shifted oDOUT
on the negative edge of CCK. Figure 6hows the
connections for loading muple PGAs in a daisy-
chain configuration.
All daisy-chained FPGAs are connected in series.
Each FPGA reads and shifts the preamble and length
count in on positive CCLK and out on negative CCLK
edges.
The generation of CCLK for the daisy-chained devices
that are in slave serl mode iffers dependie
configuration me of e lad device. A m-
lel mode deve usits internal timingene
produce an inrnal CCLK at eight tmes its mery
address re (RLK). The asynchrouperipheral
mde device outs eight CCKs for ach rite cycle.
the lad device is configured in lave de, CCLK
mbe roted to the lead evice ato all of the
daischined devices
An upstream FPGA that has received the preamble
and length count outputs a high on DOUT until it has
received the appropriate number of data frames so that
downstream FPGAs do not receive frame start bit
pairs. After loading and retransmitting the preamble
and length count to a daisy-chain of slave devices, th
lead device loads its configuration data frames.
CCLK
CCLK
CCLK
DIN
DOUT
DIN
DOUT
A[17:0]
DT
A[17:0]
EPROM
RCA
OR
ORCA
ERIES
PGA
SERI
F
SERIES
FPGA
D[7:0]
D[7:0]
DON
MA
LAVE #1
SLAVE #2
VDD
VDD
OE
CE
E
DONE
PRGM
GM
VDD
INIT
INIT
INIT
PROGRAM
VDD
M2
M1
M0
LDC
RCLK
HDC
LDC
RCLK
M1
M0
M2
M1
M0
HDC
LDC
OR
D
RCLK
5-4488(F
Fure 63. Daisy-Chain Configuration Schematic
As seen in Figure 63, ths for all of the FPGAs are connected together. This is required to guarantee that
powerup and initialization work correctly. In general, the DONE pins for all of the FPGAs are also connected
together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be
required, depending upon the start-up sequence desired.
96
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
FPGA Configuration Modes (continued)
Daisy-Chaining with Boundary Scan
Multiple FPGAs can be configured through the JTAG ports by using a daisy-chain of the FPGAs. This daisy-chain-
ing operation is available upon initial configuration after powerup, after a power-on reset, ter pulling the program
pin to reset the chip, or during a reconfiguration if the EN_JTAG RAM has been set.
All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts thpreamble ad length count in
on the positive TCK and out on the negative TCK edges.
An upstream FPGA that has received the preamble and length count outputs a h on TDO until it has received
the appropriate number of data frames so that downstream FPGAs do nt receive ae start bit pairs. After load-
ing and retransmitting the preamble and length count to a daisy-chain downstream devices, the lead device
loads its configuration data frames.
The loading of configuration data continues after the lead devichad eceived its configuration TDI of
downstream devices on the positive edge of TCK, and shifted ouTDO n the negative dge of Tigure 63
shows the connections for loading multiple FPGAs in a JTdaischain configuratio
Lattice Semiconductor
97
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series FPGAs include circuitry designed to protect the chips from damaging substte jecn cur-
rents and to prevent accumulations of static charge. Nevertheless, conventional precautios should be bserved
during storage, handling, and use to avoid exposure to excessive electrical stress.
Table 35. Absolute Maximum Ratings
Parameter
Storage Temperature
Symbol
Tstg
VDD
—
Min
–65
–0
–0.5
–0
—
Mx
50
U
Supply Voltage with Respect to Ground
Input Signal with Respect to Ground
Signal Applied to High-impedance Output
Maximum Package Body Temperature
7.0
VDD + 0.3
VDD + 0.3
220
V
—
V
—
°C
Recommended Operating Conditions
Table 36. Recommended Operating Conditions
OR3Cxx
OR3Txx
Temperatur
Rnge
(Ambnt)
Temperature
Range
Mode
upply Vtage
Supply Voltage
(VDD)
(VDD)
(Ambient)
Commercial
Industrial
0 °C to 7°C
V 5%
C to C
3.0 V to 3.6 V
3.0 V to 3.6 V
–40 °C +85 C
5 V 10%
40 °to +85 °C
Note: The maximum recommendjunctitemperature (TJ) on is 125 °C.
98
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Electrical Characteristics
Table 37. Electrical Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
OR3Cxx
Min Max
O3Txxx
Min Max
Sym-
bol
Parameter
Input Voltage:
High
Low
Test Conditions
Unit
Input configured as CMOS
(includes OR3Txxx)
50% VDD VD0.5 5% VDD VDD + 0.5
GND – 20% D GND – 0.5 30% VDD
V
V
VIH
VIL
Input Voltage:
High
Low
OR3Txxx 5 V Tolerant
—
—
—
50% V
V
VIH
VIL
V
V
GND – D
Input Voltage:
High
Low
Input configured as TTL
(not valid for OR3Txx
VIH
VIL
2.0
–0.5
VDD +0.
0.8
—
—
—
V
V
Output Voltage:
High
Low
VOH
VOL
VDD = min, IOH = 6 or 3 mA
VDD = min, I12 mor mA
2.4
—
—
.4
2.4
—
—
0.4
V
V
Input Leakage Current
IL
VDD = SS or VDD
–10
10
–10
10
µA
Standby Current:
OR3T20
IDDSB
OR325 °C,
VDD 5.0 V)
—
—
—
—
—
—
4.06
4.56
—
—
—
—
—
—
4.70
4.90
5.30
5.80
6.70
mA
mA
mA
mA
mA
OR3T30
OR3T55
OR3C/T80
OR3T125
OR3Txxx (TA = 25 °C,
VDD = 3.3 V)
internoscillator running, no ou
put loads, inputs VDD r GND
(after configuration
Standby Current:
OR3T20
IDSB
OR3Cxx (TA 25 °C,
5.0 )
—
—
—
—
—
—
—
3.05
3.42
—
—
—
—
—
—
3.52
3.68
3.98
4.35
5.02
mA
mA
mA
mA
mA
OR3T30
OR3T55
OR3C/T80
OR3T125
O= 25 °C,
V)
internal r stopped, no
output loads, inputs VDD or GND
(aer configuration)
werp Current:
OT20
OR3
Ip
Poer suply current @ approxi-
mately 1 V, within a recommended
power supply ramp rate of
1 ms—200 ms
—
—
3.2
5.4
—
—
—
—
—
—
1.2
1.6
2.7
4.0
6.5
—
—
—
—
—
mA
mA
mA
mA
mA
O3T55
O3C/T80
OR3T125
Data Retentio
Input Capacitanc
VDR
CIN
TA = 25 °C
2.3
—
—
9
2.3
—
—
8
V
OR3Cxx (TA = 25 °C,
VDD = 5.0 V)
pF
OR3Txxx (TA = 25 °C,
VDD = 3.3 V)
Test frequency = 1 MHz
Output Capacitance
COUT
OR3Cxx (TA = 25 °C,
VDD = 5.0 V)
—
9
—
8
pF
OR3Txxx (TA = 25 °C,
VDD = 3.3 V)
Test frequency = 1 MHz
Lattice Semiconductor
99
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Electrical Characteristics (continued)
Table 37. Electrical Characteristics (continued)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
OR3Cxx
O3Tx
Parameter
DONE Pull-up
Symbol
Test Conditions
Unit
Min
Max
Min
Ma
RDONE
—
100
100
14.
—
10
1
14.4
—
kΩ
Resistor*
M[3:0] Pull-up
Resistors*
RM
IPU
—
—
—
kΩ
I/O Pad Static Pull-up
Current*
OR3Cxx (VDD = 5.25 V,
VIN = VSS, TA = 0 °C)
OR3Txxx (VDD = 3.6 V,
VIN = VSS, TA = 0 °C)
.9
5
I/O Pad Static
Pull-down Current
IPD
OR3Cxx (VDD = 5.25 V
VIN = VSS, TA = 0 °
OR3Txxx (VDD = 3.6
VIN = VSS, TA °C)
2
103
26
103
µA
I/O Pad Pull-up
Resistor*
RPU
RPD
VDD = all, VIN 0 °C
100
5
—
—
100
50
—
—
kΩ
kΩ
I/O Pad Pull-down
Resistor
VDD = a, VIN = VDD= 0 °C
* On the OR3Txxx devices, the pull-up resistor will externy pull the pin to a level .0 V low VDD.
Note: For 3T devices driven to 5 V.
100
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
mercial and industrial devices. Table 40 provides the
same information for the OR3Txxx devices (both com-
mercial and industrial). The delay values in this data
sheet and reported by ispLEVER are shown as 1.00 in
the tables. The method for determining the maximum
junction temperature is defined n the Package Thermal
Characteristics section. Takn cumulatively, the range
of parameter values for besse vsworst-case pro-
cessing, supply voltae, and junctiotemperature can
approach 3 to 1.
Timing Characteristics
Description
To define speed grades, the ORCA Series part number
designation (see Ordering Information) uses a single-
digit number to designate a speed grade. This number
is not related to any single ac parameter. Higher num-
bers indicate a faster set of timing parameters. The
actual speed sorting is based on testing the delay in a
path consisting of an input buffer, combinatorial delay
through all PLCs in a row, and an output buffer. Other
tests are then done to verify other delay parameters,
such as routing delays, setup times to FFs, etc.
Table 38. Deating for omercial Devices
OR3Cxx)
Power Supp
.0 V
TJ
(¡)
The most accurate timing characteristics are reported
by the timing analyzer in the ispLEVER Development
System. A timing report provided by the development
system after layout divides path delays into logic and
routing delays. The timing analyzer can also provide
logic delays prior to layout. While this allows routing
budget estimates, there is wide variance in routing
delays associated with different layouts.
4.75 V
5.25 V
0
2
85
100
125
0.81
0.85
1.00
1.05
1.12
0.79
.83
97
1.02
1.09
0.77
0.81
0.95
1.00
1.07
Table 39. Deratifor Industrial Devices (OR3Cxx)
The logic timing parameters noted in the Ele
Characteristics section of this data sheet are thme
as those in the design tools. In the FU timing given in
Table 41—Table 48, symbol names e generally a
concatenation of the PFU operating me (as defined
in Table 3) and the paramter type. The setup, hold,
and propagation delay pametersdefined below, are
designated in the symbol me bthe SET, HLD, a
DEL characters, rspectively.
Power Supply Voltage
TJ
¡C)
4.5 4.75 V 5.0 V 5.25 V 5.5 V
—40
0
25
85
100
125
71
0.80
0.84
1.00
1.05
1.12
0.70
0.78
0.82
0.97
1.01
1.09
0.68
0.76
0.80
0.94
0.99
1.06
0.66
0.74
0.78
0.93
0.97
1.04
0.65
0.73
0.77
0.91
0.95
1.02
The values given he paameters are th
those used during prdution testing and
ning of thdevices. The junction temrature up-
ply votage ued to haracterize tdevices are listed
in e delay tab. Actual delays nominatempera-
tuad voltage for best-caprocees an be much
bettethan he values givn.
Table 40. Derating for Commercial/Industrial
Devices (OR3Txxx)
Power Supply Voltage
3.3 V
TJ
(¡C)
3.0 V
3.6 V
—40
0
25
85
100
125
0.73
0.82
0.87
1.00
1.04
1.10
0.66
0.73
0.78
0.90
0.94
1.00
0.61
0.68
0.72
0.83
0.87
0.92
ould be noted thahe junction emperature used in
the bles is generally 8°C. Te junction temperature
fthe FPGA don te power dissipated by the
device, the pmal characteristics (ΘJA), and
the ambient tem, as calculated in the following
equation and as dissed further in the Package
Thermal Characteristics section:
Note: The derating tables shown above are for a typical critical path
that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay, paths
with more than 66% routing delay will derate at a higher rate
than shown in the table. The approximate derating values vs.
temperature are 0.26% per °C for logic delay and 0.45% per °C
for routing delay. The approximate derating values vs. voltage
are 0.13% per mV for both logic and routing delays at 25 °C.
TJmax = TAmax + (P • ΘJA) °C
Note: The user must determine this junction tempera-
ture to see if the delays from ispLEVER should
be derated based on the following derating
tables.
Table 38 and Table 39 provide approximate power sup-
ply and junction temperature derating for OR3Cxx com-
Lattice Semiconductor
101
Data Sheet
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
November 2006
The waveform test points are given in the Input/Output
Buffer Measurement Conditions section of this data
sheet. The timing parameters given in the electrical
characteristics tables in this data sheet follow industry
practices, and the values they reflect are described
below.
In addition to supply voltage, process variation, and
operating temperature, circuit and process improve-
ments of the ORCA Series FPGAs over time will result
in significant improvement of the actual performance
over those listed for a speed grade. Even though lower
speed grades may still be available, the distribution of
yield to timing parameters may be several speed
grades higher than that designated on a product brand.
Design practices need to consider best-case timing
parameters (e.g., delays = 0), as well as worst-case
timing.
Propagation Delay—The time beteen e pecified
reference points. The delays prvided are thworst
case of the tphh and tpll delys for nonirting func-
tions, tplh and tphl for inverg fnctions, and tphz and
tplz for 3-state enable.
Setup Time—The ierval immediately preceding the
transition of a clock latch eable signal, dich
the data must bstablto nsure it is rec
the intended alue
The routing delays are a function of fan-out and the
capacitance associated with the CIPs and metal inter-
connect in the path. The number of logic elements that
can be driven (fan-out) by PFUs is unlimited, although
the delay to reach a valid logic level can exceed timing
requirements. It is difficult to make accurate routing
delay estimates prior to design compilation based on
fan-out. This is because the CAE software may delete
redundant logic inserted by the designer to reduce
out, and/or it may also automatically reduce fan-out
net splitting.
Hold Te—Te interval immedialy folwing the
tranition of ck or latch enable sal, durng which
te data must be held stable to sure is ecognized
thintended value.
3-Ste nable—The me frm whn a 3-state control
nal becomes active anthe output pad reaches the
h-impedance s
PFU Timing
Table 41. Combinatorial PFU Timing Characristics
OR3Cxx Commercial: VDD = 5.0 V %, 0 °C < TA < 70 °C; Industrial: VD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V t3.6 V, 0 < TA < 70 °C; rial: D = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Paramet
S
Unit
-4
-5
-6
-7
Min Max Min Max Min Max Min Max
Combinatorial DelayTJ = +8°C, VDD = min
Four-input ariables ([3] to F[z])*
Five-inpVariales (F5[A:D] to F[0, 2, 4, 6])
Two-level Delay Kz[3:0] to F weedbk)*
Twlvel LUDely (F5[A:D] to F /fee)
hree-leel LUT Delay (Kz[3:0] to F w/feedbk
FDEL
F_DEL
WL2_DEL
SWL2F5_DEL
SWL3_DEL
—
—
—
—
—
—
—
2.34
2.11
4.87
4.69
6.93
6.89
3.47
—
—
—
—
—
—
—
1.80
1.57
3.66
3.51
5.15
5.08
2.65
—
—
—
—
—
—
—
1.32
1.23
2.58
2.48
3.63
3.54
1.79
—
—
—
—
—
—
—
1.05
0.99
2.03
1.94
2.82
2.75
1.43
ns
ns
ns
ns
ns
ns
ns
T-leveUT Delay (F5[A:D] F w/fedk) SWL3F5_DEL
CIN to COT Delay (logic e) CO_DEL
* Four-input variables’ (KZ[3ys are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.
102
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
FDBK–DEL
PFU
F[7:0]
F4_DEL
LUT
8
4
KZ[3:0]
F[6, 4,
2, 0]
F5–DEL
LUT
KZ[3:0], F5[A:D]
F4_DEL/
F5_DEL
LUT
F[7:0]
F4_DEL/
LUT
KZ[3:0]
SWL2_L
L/
F[7:0]
OM_DEL
O[9:0]
FL/
F5DEL
LUT
F4_DEL/
LUT
KZ[3:0]
SWL3
L/
F[7:0]
F4_DEL/
F5_DEL
LUT
F5[A
SWL2F5_DEL
F4_DEL/
F5_DEL
LUT
F[7:0]
F4_DEL/
F5_DEL
LUT
F4_DEL/
F5_DEL
LUT
F5[A:D]
SWL3F5_DEL
Note: See Table 46 for an explanation of FDBK_DEL and OMUX_DEL.
5-5751(F)
Figure 64. Combinatorial PFU Timing
Lattice Semiconductor
103
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 42. Sequential PFU Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Parameter
Symbol
Unit
-4
-5
-6
-7
Min Max Min MMn Max Min Max
Input Requirements
Clock Low Time
CLKL_MPW
CLKH_MPW
GSR_MPW
LSR_MPW
3.36
1.61
3.36
3.36
—
—
—
—
.07
6
2.07
27
—
—
—
—
0.94
0.54
0.94
0.94
—
—
—
—
0.72
0.
0.
0.72
—
ns
ns
ns
ns
Clock High Time
Global S/R Pulse Width (GSRN)
Local S/R Pulse Width
Combinatorial Setup Times (TJ = +85 °C, VDD = min):
Four-input Variables to Clock (Kz[3:0] to CLK)*
Five-input Variables to Clock (F5[A:D] to CLK)
Data In to Clock (DIN[7:0] to CLK)
Carry-in to Clock, DIRECT to REGCOUT (CIN to CLK)
Clock Enable to Clock (CE to CLK)
Clock Enable to Clock (ASWE to CLK)
Local Set/Reset to Clock (SYNC) (LSR to CLK)
Data Select to Clock (SEL to CLK)
Two-level LUT to Clock (Kz[3:0] to CLK w/febk)*
Two-level LUT to Clock (F5[A:D] to CLK wfeed)
Three-level LUT to Clock (Kz[3:0] to CLK w/feedb*
Three-level LUT to Clock (F5[A:D] tCLK w/feedbk)
F4_SE
F5_ET
DIN_
CDIR_ST
SET
ET
ET
_SET
SWL2_SET
SWL2F5_SET
SWL3_SET
SWL3F5_ST
1.99
1.79
0.47
25
2.86
1.68
1.86
1.37
3.8
6
6.4
6.39
—
—
—
—
—
—
—
—
—
1.47
1.33
0.32
0.99
2.15
1.30
36
10
2.99
97
4.81
4.73
—
—
—
—
—
—
—
—
—
—
.08
1.
0.18
0.71
8
0.95
0.86
0.92
2.13
2.29
3.42
3.34
—
—
—
—
—
—
—
—
—
—
—
0.8
.81
0.16
0.58
1.37
0.77
0.68
0.70
1.63
1.68
2.64
2.57
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Combinatorial Hold Times (TJ = all, D = all):
Data In (DIN[7:0] from CLK)
Carry-in from Clock, DIRET to REGCOT (CIN from
CLK)
DINLD
CINDIR_LD
0
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
ns
ns
LD
LD
_HLD
SEL_HLD
—
Clock Enable (CE from CLK
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
ns
ns
ns
ns
ns
Clock Enable from Clock (ASom CLK)
Local Set/Reset fm Clock (sync) (LSR from LK)
Data Select om Clk (SEfrom CLK)
All Others
Output Chaeristics
Seqential Dels (J = +85 °C, VDD mi
cal Sasync) to PFU Out SR to Q[7:0]REG-
UT)
Global S/to PFU Out (to Q:0], REGCOUT)
Clock to PFU Out—Rto Q[7:0], REG-
COUT)
LSR_DEL
—
7.02
—
5.29
—
3.64
—
2.90 ns
GSR_DEL
REG_DEL
—
—
5.21
2.38
—
—
3.90
1.75
—
—
2.55
1.26
—
—
2.00 ns
0.97 ns
LTCH_DEL
LTCHD_DEL
Clock to PFU Out—Latch Q[7:0])
Transparent Latch (DIN[7:0] Q[7:0])
—
—
2.51
2.73
—
—
1.88
2.10
—
—
1.21
1.38
—
—
0.96 ns
1.12 ns
* Four-input variables’ (KZ[3:0]) setup times are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.
Note: The table shows worst-case delays. ispLEVER reports the delays for individual paths within a group of paths representing the same
timing parameter and may accurately report delays that are less than those listed.
104
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 43. Ripple Mode PFU Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Seed
Parameter
(TJ = +85 °C, VDD = min)
Symbol
Unit
-4
-5
-6
-7
Min Max n ax Min Max Min Max
Full Ripple Setup Times (byte wide):
Operands to Clock (Kz[1:0] to CLK)
Bitwise Operands to Clock (Kz[1:0] to CLK at F[z])
Fast Carry-in to Clock (FCIN to CLK)
Carry-in to Clock (CIN to CLK)
RIP_SET
FRIP_SET
FCIN_SET
CIN_SET
3.50
1.9
2.55
30
8.8
2.09
.29
.09
8.14
—
—
—
—
—
—
—
—
—
2.50
1.7
17
2.79
6.18
1.61
1.76
2.36
5.73
—
—
—
—
—
—
—
1.96
1.08
1.34
1.97
.68
1.19
1.8
73
4.5
—
—
—
—
—
—
1.48
85
93
1.02
1.35
3.39
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
AS_SET
Add/Subtract to Clock (ASWE to CLK)
RIPRC_SET
FCINRC_
INRC_SET
ASR_SET
Operands to Clock (Kz[1:0] to CLK at REGCOUT)
Fast Carry-in to Clock (FCIN to CLK at REGCOUT)
Carry-in to Clock (CIN to CLK at REGCOUT)
Add/Subtract to Clock (ASWE to CLK at REGCOUT)
Full Ripple Hold Times (TJ = all, VDD = all):
Fast Carry-in from Clock (FCIN from CLK at RE
FCR_HLD
0.00
0
0.0
0
—
—
0.00
0.00
—
—
0.00
0.00
—
—
ns
ns
COUT)
All Others
ENERIC_HLD
Half Ripple Setup Times (nibble wide):
Operands to Clock (Kz[1:0] to CLK
Bitwise Operands to Clock (Kz[10] to LK at F[z])
Fast Carry-in to Clock (FCIN to CLK)
Carry-in to Clock (CIN to CK)
HRIP_SE
HFRIPT
HFCIN_SE
HIN_SET
31
1.9
2.55
3.80
8.82
3.03
2.29
3.09
8.14
—
—
—
—
—
—
—
—
—
2.81
1.47
1.87
2.79
6.18
2.31
1.76
2.36
5.73
—
—
—
—
—
—
—
—
—
2.21
1.08
1.34
1.97
4.68
1.68
1.28
1.73
4.54
—
—
—
—
—
—
—
—
—
1.66
0.85
1.04
1.56
3.50
1.32
1.02
1.35
3.39
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
HASET
Add/Subtract to Clock (AWE to CLK)
IPRET
FCINRC_SET
HNRC_SET
HASRC_SET
Operands to Clock (Kz[1:to CLK REGCOUT)
Fast Carry-in to Clck (FCIN o Cat REGCOUT)
Carry-in to Cloc(CIN CLK at REGCOUT)
Add/Subtract to o(ASWE to CLK at RE
Half Ripple Hold TimeT= all, VDD = all):
Fast Cay-in from Clock (HFCIN froK at R
CUT)
Al Others
HFCINRC_HLD
GENERIC_HLD
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
ns
ns
Noe table hows worst-casdelay for the le chain. ispLEVER reports the delay for individual paths within the ripple chain that will be
ss tn or equal to tholistee.
Lattice Semiconductor
105
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 43. Ripple Mode PFU Timing Characteristics (continued)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Parameter
(TJ = +85 °C, VDD = min)
Unit
Symbol
-4
-5
-6
7
Min Max Min Max in Max Min Max
Full Ripple Delays (byte wide):
RIPCO_DEL
RIPFCO_DEL
RIP_DEL
Operands to Carry-out (Kz[1:0] to COUT)
Operands to Carry-out (Kz[1:0] to FCOUT)
Operands to PFU Out (Kz[1:0] to F[7:0])
Bitwise Operands to PFU Out (Kz[1:0] to F[z])
Fast Carry-in to Carry-out (FCIN to COUT)
Fast Carry-in to Fast Carry-out (FCIN to FCOUT)
Carry-in to Carry-out (CIN to COUT)
Carry-in to Fast Carry-out (CIN to FCOUT)
Fast Carry-in PFU Out (FCIN to F[7:0])
Carry-in PFU Out (CIN to F[7:0])
—
—
—
—
—
—
—
—
—
—
—
—
—
5.32
5.30
7.37
2.4
2.5
2.57
47
3.46
6.03
691
8.28
8.11
10.66
—
—
—
—
—
—
—
—
—
—
—
4.11
4.10
.60
1.8
1.99
1.98
2.65
2.64
4.55
5.21
589
5.7
7.55
—
—
—
—
—
—
—
—
—
—
98
2.98
4.18
1.32
1.43
1.1
19
1.78
.21
3.
4.5
48
5.85
—
—
—
—
—
—
—
—
—
—
—
—
2.32 ns
ns
ns
s
ns
1.ns
1.43 ns
1.43 ns
2.51 ns
3.05 ns
3.45 ns
3.38 ns
4.38 ns
FRIP_DEL
FCINCO_DEL
FCINFCO_DEL
CINCO_DEL
CINFCO_DEL
FCIN_DEL
CIN_DEL
ASCOL
AS
Add/Subtract to Carry-out (ASWE to COUT)
Add/Subtract to Carry-out (ASWE to FCOUT)
Add/Subtract to PFU Out (ASWE to F[7:0])
Half Ripple Delays (nibble wide):
HRIPCO_EL
HRIPFCO_DEL
HRIP_DEL
Operands to Carry-out (Kz[1:0] to COUT)
Operands to Fast Carry-out (Kz[1:0] to FCU
Operands to PFU Out (Kz[1:0] to F[3:0])
Bitwise Operands to PFU Out (Kz[1:0F[z])
Fast Carry-in to Carry-out (FCIN to COUT)
Fast Carry-in to Fast Carry-out (FCN to FCOT)
Carry-in to Carry-out (CIN to OUT
Carry-in to Carry-out (CIN o FCOUT)
Fast Carry-in PFU Out (FIN tF[3:0])
Carry-in PFU Out (CIN to F0])
—
—
—
—
—
—
—
—
—
—
—
5.32
.30
0
2.3
2.59
2.57
.47
3.46
3.76
4.65
8.28
8.11
9.12
—
—
—
—
—
—
—
—
—
—
—
—
—
41
4.10
4.07
1.80
1.99
1.98
2.65
2.64
2.84
3.50
5.89
5.78
6.49
—
—
—
—
—
—
—
—
—
—
—
—
—
2.98
2.98
3.20
1.32
1.43
1.41
1.79
1.78
2.01
2.33
4.58
4.48
4.86
—
—
—
—
—
—
—
—
—
—
—
—
—
2.32 ns
2.32 ns
2.40 ns
1.05 ns
1.14 ns
1.13 ns
1.43 ns
1.43 ns
1.58 ns
2.12 ns
3.45 ns
3.38 ns
3.69 ns
HFRIP_DEL
HFCINCO_DEL
HFCINFCO_DEL
HCINCO_DE
HCINFC_DEL
H
H
HASFEL
HAS_DEL
Add/Subtract to Carry-out (ASE to COUT)
Add/Subtract to Cry-out (ASWE to FCOUT)
Add/Subtracto PFU ut (AWE to F[3:0])
Note: The te shs worst-case delay for the ripple ain. ispEVER reports the delay for individual paths within the ripple chain that will be
less thaequal tthose listed abe.
106
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 44. Synchronous Memory Write Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Spe
Unit
Parameter
Symbol
-4
-5
-6
-7
Min
Max
Min
Max
Min
Max
Min
Max
Write Operation for RAM Mode:
Maximum Frequency
Clock Low Time
Clock High Time
Clock to Data Valid (CLK to F[6, 4, 2, 0])*
SMCLK_FRQ
SMCLKL_MPW
SMCLKH_MPW
MEM_DEL
—
2.34
3.79
—
151.00
—
—
1.80
2.77
—
197.
—
—
1.32
2.13
—
254.00
—
—
—
1.05
.62
315.00 MHz
ns
ns
10
14
4.08
ns
Write Operation Setup Time:
Address to Clock (CIN to CLK)
Address to Clock (DIN[7, 5, 3, 1] to CLK)
Data to Clock (DIN[6, 4, 2, 0] to CLK)
Write Enable (WREN) to Clock (ASWE to CLK)
Write-port Enable 0 (WPE0) to Clock (CE to
CLK)
WA4_SET
WA_SET
WD_SET
WE_SE
1.25
72
0.02
0.18
2.25
—
—
—
.99
0.52
0.06
0.16
1.69
—
—
—
—
—
0.1
.35
0
0.1
1.16
—
—
—
—
8
0.28
0.00
0.12
0.84
—
—
—
—
—
ns
ns
ns
ns
ns
WPE0_T
Write-port Enable 1 (WPE1) to Clock (LSR to
CLK)
29
—
23
158
—
1.31
—
ns
ET
Write Operation Hold Time:
Address from Clock (CIN from CLK)
Address from Clock (DIN[7, 5, 3, 1] froCLK)
Data from Clock (DIN[6, 4, 2, 0] from LK)
Write Enable (WREN) from Clock ASWrom
CLK)
WD
WALD
WD_HLD
WE_HLD
0.00
0.00
0.5
0
—
—
—
0.00
00
0.42
.00
—
—
—
—
0.00
0.00
0.40
0.08
—
—
—
—
0.00
0.00
0.32
0.06
—
—
—
—
ns
ns
ns
ns
Write-port Enable 0 (WPE0from Clock (CE
from CLK)
Write-port Enable 1 (WPE1from Clo(LSR
from CLK)
0.00
—
0.00
0.00
—
—
0.00
0.00
—
—
0.00
0.00
—
—
ns
ns
WPE0_HLD
WPE1_
* The RAM is written n thinactive clock edge followve ede that latches the address, data, and control signals.
Note: The table shows st-casdelays. ispLEVER elays for individual paths within a group of paths representing the same tim-
ing parameter and mccurately report delays than those listed.
WA4_SET
WA_SET
WA4_HLD
WA_HLD
N, N[7, 5, , 1]
DIN[6, 4, 2, 0]
WD_SET
WD_HLD
WE_HLD
WE_SET
ASWE (WR
WPE0_HLD
WPE1_HLD
WPE0_SET
WPE1_SET
CE (WPE0),
LSR (WPE1)
TSCH
TSCL
CK
MEM_DEL
F[6, 4, 2, 0]
5-4621(F)
Figure 65. Synchronous Memory Write Characteristics
Lattice Semiconductor
107
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 45. Synchronous Memory Read Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Parameter
(TJ = 85 °C, VDD = min)
Unit
Symbol
-4
-5
-6
Min Max Min Max Min ax Min Max
Read Operation:
Data Valid After Address (Kz[3:0] to F[6, 4, 2, 0])
Data Valid After Address (F5[A:D] to F[6, 4, 2, 0])
RA_DEL
RA4_DEL
—
—
2.34
2.11
—
—
1.80
1.57
—
—
1.2
1.23
—
—
1.05 ns
0.99 ns
Read Operation, Clocking Data into Latch/FF:
Address to Clock Setup Time (Kz[3:0] to CLK)
Address to Clock Setup Time (F5[A:D] to CLK)
Address from Clock Hold Time (Kz[3:0] from CLK)
Address from Clock Hold Time (F5[A:D] from CLK)
Clock to PFU Output—Register (CLK to Q[6, 4, 2, 0])
Read Cycle Delay
RA_SET
RA4_SET
RA_HLD
RA4_HLD
REG_DEL
SMRD_C
1.99
1.79
0.00
0.00
—
—
—
—
—
2.3
10.48
.47
1.
0.00
0.00
—
—
—
—
1.75
7.66
.08
1.03
0.00
0.00
—
—
—
—
1.2
7.53
0.8
0.81
0.00
00
—
—
s
s
ns
ns
0.97 ns
5.78 ns
—
—
—
—
Note:The table shows worst-case delays. ispLEVER reports the delays for inual pas within a group of ths reprenting the same timing
parameter and may accurately report delays that are less thae liste
Kz[3:0], F5[A:D]
RA_DEL
RA4_DEL
F[6, 4, 2, 0]
R_HLD
RA4_HLD
RA_SET
RA4_
CLK
REG_DEL
SMRD_CYC
Q[3:0]
5-4622(F)
gure 66. Synchronous Memory Read Cycle
108
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
PLC Timing
Table 46. PFU Output MUX and Direct Routing Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V40 < A < +85 °C.
peed
Parameter
Symbol
Unit
-7
-4
-5
-
(TJ = 85 °C, VDD = min)
Min Max in Max n Max Min Max
PFU Output MUX (Fan-out = 1)
OMUX_DEL
COO9_DEL
RCOO8_DEL
Output MUX Delay (F[7:0]/Q[7:0] to O[9:0])
Carry-out MUX Delay (COUT to O9)
Registered Carry-out MUX Delay (REGCOUT
to O8)
—
—
—
0.5
.34
34
—
—
0.9
0.26
0.26
—
—
—
0.3
0.24
0.24
.28
18
0.18
ns
ns
ns
Direct Routing
FDBK_EL
ODIR_D
DEL
PFU Feedback (xSW)*
PFU to Orthogonal PFU Delay (xSW to xSW)
PFU to Diagonal PFU Delay (xBID to xSW)
—
—
1.74
2.21
2.69
—
—
—
1.41
77
2.1
—
—
18
1.75
2.53
—
—
—
1.14
1.39
1.98
ns
ns
ns
* This is general feedback using switching segments. inatorial PFU timing table for oftwired look-up table feedback timing.
SLIC Timing
Table 47. Supplemental Logic and Inerconnect Cell (SLIC) iming Characteristics
OR3Cxx Commercial: VDD 5.0 V 5%, 0 °C < TA < 70 °C; Inustrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD 3.0 V to .6 V, 0 °C < TA °C; Iustrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Pameter
(TJ = °C, VD = min)
Unit
ymbol
-4
-5
-6
-7
Min Max Min Max Min Max Min Max
3-Statable IDIs
BUF_DEL
OBUF_DEL
TRI_DEL
BII Delay (BtBLx, BLx to BRx
DI Day (Ox to BRx, Ox to BLx)
BI-state nable/Disable Delay (TRI to BL, BR)
BIDI ste Enable/DisablDe
—
—
—
—
0.84
0.72
2.55
3.59
—
—
—
—
0.70
0.61
1.90
2.65
—
—
—
—
0.94
0.87
1.31
1.91
—
—
—
—
0.77 ns
0.70 ns
1.01 ns
1.48 ns
DECTRI_DEL
L, BR via DEC, TRo BL, BR)
Deoder
DEC98_DEL
DEC_DEL
Decoder Delay BL[9] to DEC)
Decoder DelaL[7:0] to DEC)
—
—
2.39
2.35
—
—
1.85
1.82
—
—
1.27
1.23
—
—
1.02 ns
0.99 ns
Lattice Semiconductor
109
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
PIO Timing
Table 48. Programmable I/O (PIO) Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < 8C.
Speed
Parameter
Symbol
Unit
-4
-5
-6
-7
Min Max Min Max Min Max Min Max
Input Delays (TJ = 85 °C, VDD = min)
Input Rise Time
—
—
500
500
—
—
00
50
—
—
500
500
—
—
ns
s
IN_RIS
IN_FAL
Input Fall Time
PIO Direct Delays:
—
—
—
.41
2.1
9.05
—
1.26
1.87
7.83
—
—
—
0.
1.2
6.64
—
—
—
0.4
.90
7.27
ns
ns
ns
Pad to In (pad to CLK IN)
Pad to In (pad to IN1, IN2)
Pad to In Delayed (pad to IN1, IN2)
CKIN_DEL
IN_DEL
IND_DEL
PIO Transparent Latch Delays:
Pad to In (pad to IN1, IN2)
Pad to In Delayed (pad to IN1, IN2)
—
4.
0.58
—
—
3.25
9.0
—
2.5
7.6
—
—
1.82
7.65
ns
ns
LATCH_DEL
LATCHD
Input Latch/FF Setup Timing:
Pad to ExpressCLK (fast-capture latch/FF)
Pad Delayed to ExpressCLK
INREGE93
NREGED_12.86
4.82
103
9.18
3.23
9.68
—
—
—
—
—
—
—
ns
ns
(fast-capture latch/FF)
Pad to Clock (input latch/FF)
Pad Delayed to Clock (input latch/FF)
Clock Enable to Clock (CE to CLK)
Local Set/Reset (sync) to Clock (LR to CLK)
INREG_SET
IREGD_SET 8.57
INE_SET
INLSR_SET
1.62
1.42
7.36
64
1.45
0.71
5.91
1.29
1.14
0.50
7.06
1.00
0.89
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
2.0
1.79
Input FF/Latch Hold Timing:
INREGE_HLD 0
INREG0.0
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
—
—
—
ns
ns
Pad from ExpressCLK (fascapture latch/FF)
Pad Delayed from ExpreCLK
(fast-capture latch/FF)
Pad from Clock (input latch/FF
Pad Delayed from lock (input latch/FF)
Clock Enablfrom Cck (Cfrom CLK)
Local Seteset sync) m Clock
(LSR frm CK)
INRE
.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
REGD0.00
INCE_HLD
INLS_HLD
0.00
0.00
INREG_DEL
INLTCH_DEL
INLSR_DEL
INLSRL_DEL
—
—
—
—
4.05
4.08
6.11
5.89
—
—
—
—
3.14
3.19
4.76
4.66
—
—
—
—
2.53
2.62
3.81
3.57
—
—
—
—
2.05
2.14
3.17
2.98
ns
ns
ns
ns
Cloc-in Dey (FCLK to IN1, IN
Clck-to-in Delay atch CLK to IN1, IN)
LoR (anc) to IN (LSR to IN, IN2)
Local S/R (aync) to IN (LSR o IN1, 2)
LatchFF in Latch Mod
INGSR_DEL
—
5.38
—
4.22
—
3.44
—
2.88
ns
Global S/R to In (GSRN
Note: The delays for all input busume an input rise/fall time of <1 V/ns.
110
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 48. Programmable I/O (PIO) Timing Characteristics (continued)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Spee
Parameter
Symbol
Unit
-4
-5
-6
-7
Min Max Min Max Min ax Min Max
Output Delays (TJ = 85 °C, VDD = min, CL = 50 pF)
Output to Pad (OUT2, OUT1 direct to pad):
Fast
Slewlim
Sinklim
OUTF_DEL
OUTSL_DEL
OUTSI_DEL
—
—
—
5.09
7.8
9.41
—
—
—
4.21
49
98
—
—
—
2.63
3.49
8.
—
2.17 ns
2.91 ns
7.32 ns
3-state Enable/Disable Delay (TS to pad):
Fast
Slewlim
Sinklim
TSF_DEL
TSSL_DEL
TSSI_DEL
—
—
—
4.93
7.70
.25
—
—
—
4.09
6.37
7.86
—
—
2.33
300
7.95
—
1.88 ns
2.41 ns
7.23 ns
Local Set/Reset (async) to Pad (LSR to pad):
Fast
Slewlim
Sinklim
OUTLF_D
OUTLSRLDEL
OUTLSRSEL
—
—
—
9.03
11.79
13.35
—
—
—
7.25
9.53
.02
—
96
5.82
10.38
—
—
—
3.94 ns
4.67 ns
9.10 ns
Global Set/Reset to Pad (GSRN to pad):
Fast
Slewlim
Sinklim
_DEL
L_DEL
ORSI_DEL
—
—
—
8.0
11.
2.62
—
—
—
6.69
97
10.46
—
—
—
4.39
5.07
10.02
—
—
—
3.46 ns
3.99 ns
8.81 ns
Output FF Setup Timing:
Out to ExpressCLK (OUT[2:1] to ECL)
Out to Clock (OUT[2:1] to CLK)
Clock Enable to Clock (CE CLK)
Local Set/Reset (sync) to Clock (LSR to CLK)
OUTE_SET
OUT_SET
OUTCE_T
OUTLSR_S
.00
0.
0.91
0.41
—
—
—
—
0.00
0.00
0.67
0.32
—
—
—
—
0.00
0.00
0.56
0.26
—
—
—
—
0.00
0.00
0.45
0.24
—
—
—
—
ns
ns
ns
ns
Output FF Hold Timing:
OUTHLD
UT_H
E_HL
_HLD
Out from ExpressCK (OU:1] fm ECLK)
Out from Clock (UT[2] from CLK)
Clock Enable frCck (CE from CLK)
Local Set/Reset (sc) froClock (LSR fro
CLK)
.73
0.73
0.00
0.00
—
—
—
—
0.58
0.58
0.00
0.00
—
—
—
—
0.36
0.36
0.00
0.00
—
—
—
—
0.29
0.29
0.00
0.00
—
—
—
—
ns
ns
ns
ns
Clock to PDelay (ECLK, SCLK to pd):
Fa
ewlim
inkl
OUTREGF_DEL
OUTREGSL_DEL
OUTREGSI_DEL
—
—
—
6.71
9.47
11.03
—
—
—
5.44
7.71
9.20
—
—
—
3.56
4.42
8.98
—
—
—
2.78 ns
3.52 ns
7.94 ns
OD_DEL
Addnal Dlay If Using On Drai
—
0.20
—
0.16
—
0.10
—
0.08 ns
Ne: The delays for all inpt buffers assuman input rise/fall time of <1 V/ns.
Lattice Semiconductor
111
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 48. Programmable I/O (PIO) Timing Characteristics (continued)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Parameter
Symbol
Unit
-4
-5
-6
-7
Min Max Min Max MiMaMiMax
PIO Logic Block Delays
Out to Pad (OUT[2:1] via logic to pad):
Fast
Slewlim
Sinklim
OUTLF_DEL
OUTLSL_DEL
OUTLSI_DEL
—
—
—
5.09
7.86
9.41
—
—
—
41
69
7.
—
—
—
2.3
3.49
8.08
—
—
—
2.17
2
ns
ns
Outreg to Pad (OUTREG via logic to pad):
Fast
Slewlim
Sinklim
OUTRF_DEL
OUTRSL_DEL
OUTRSI_DEL
—
—
—
6.71
947
11.0
—
—
54
7.71
9.20
—
—
—
3.56
4.42
8.98
—
—
2.
3.52
7.94
s
ns
ns
Clock to Pad (ECLK, CLK via logic to pad):
Fast
Slewlim
Sinklim
OUTCF_DEL
OUTCSL_DEL
OUTCSI_DEL
—
—
97
9.74
11.2
—
—
—
5.68
7.96
9.45
—
—
3.
4.57
9.13
—
—
—
2.91
3.64
8.07
ns
ns
ns
3-State FF Delays
3-state Enable/Disable Delay (TS direct to
pad):
Fast
Slewlim
Sinklim
TSF_DEL
TSSL_DEL
SSI_DEL
—
—
—
4.93
7.70
9.
—
—
—
4.0
.37
76
—
—
—
2.33
3.00
7.95
—
—
—
1.88
2.41
7.23
ns
ns
ns
Local Set/Reset (async) to Pad (LSR to
pad):
Fast
Slewlim
Sinklim
TSLSRF_DEL
SLSRSL_DEL
TSLSRSI_DEL
—
25
11
12.57
—
—
—
6.65
8.92
10.41
—
—
—
4.24
4.92
9.87
—
—
—
3.39
3.92
8.74
ns
ns
ns
Global Set/Reset to Pad (GRN tpad):
Fast
Slewlim
Sinklim
TSGSR
TSGSRS
TSGSRSI
—
—
7.52
10.28
11.84
—
—
—
6.09
8.36
9.85
—
—
—
3.88
4.55
9.51
—
—
—
3.11
3.64
8.45
ns
ns
ns
3-State FF Setup Timng:
TS to ExpresCLK (Tto CLK)
TS to Clok (TS o CLK
Local Seet (sync) to Clock (LSR o
CLK)
TSE_ST
TS_S
LSSET
0.00
0.00
0.28
—
—
—
0.00
0.00
0.21
—
—
—
0.00
0.00
0.17
—
—
—
0.00
0.00
0.18
—
—
—
ns
ns
ns
3-ate FF Hold ming:
TSE_HLD
TS_HLD
TSLSR_HLD
S frEressCLK (TS from CLK)
TS from Cck (TS from CLK)
Local Reset (sync) fck
(LSR from CLK)
0.85
0.85
0.00
—
—
—
0.68
0.68
0.00
—
—
—
0.44
0.44
0.00
—
—
—
0.34
0.34
0.00
—
—
—
ns
ns
ns
Clock to Pad Delay (ECLKpad):
Fast
Slewlim
Sinklim
TSREGF_DEL
TSREGSL_DEL
TSREGSI_DEL
—
—
—
5.94
8.70
10.26
—
—
—
4.82
7.10
8.59
—
—
—
2.84
3.52
8.47
—
—
—
2.23
2.76
7.58
ns
ns
ns
Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns.
112
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Special Function Blocks Timing
Table 49. Microprocessor Interface (MPI)Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °< TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V40 °C < TA < +85 °C.
Spee
Parameter
Symbol
–4
–5
–6
–7
Unit
Min Max MiMax Min Max Min Max
PowerPC Interface Timing (TJ = 85 °C, VDD = min)
Transfer Acknowledge Delay (CLK to TA)
Burst Inhibit Delay (CLK to BIN)
Transfer Acknowledge Delay to High Impedance
Burst Inhibit Delay to High Impedance
Write Data Setup Time (data to TS)
Write Data Hold Time (data from CLK while MPI_ACK l)
Address Setup Time (addr to TS)
Address Hold Time (addr from CLK while MPI_A)
Read/Write Setup Time (R/W to TS)
Read/Write Hold Time (R/W from CLK while MP)
Chip Select Setup Time (CS0, CS1 to TS)
Chip Select Hold Time (CS0, CS1 froCLK)
User Address Delay (pad to UA[3:])
TA_DEL
BI_EL
—
—
1.6
11.6
(2)
—
—
—
9.3
.3
(2)
—
—
—
—
6.8 ns
6.8 ns
(2)
TA_DEZ
BDEL
WD_S
WD_HLD
ASET
ns
ns
(2)
(2
(2)
(2)
—
—
—
—
0.0
0.0
0.0
0
0.0
0
0.3
0
—
—
—
—
—
—
—
3.3
7.0
0.0
0
0.0
0.0
0.0
0.0
.25
0.0
—
—
—
—
—
—
—
—
—
2.6
5.4
0
0.0
0.0
0.0
0.0
0.0
.14
0.0
—
—
—
—
—
—
—
—
—
2.3
4.2
0.0
0.0
0.0
0.0
0.0
0.0
.12
0.0
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
A_HLD
RW_SET
RW_HLD
CS_ST
CSHLD
_DEL
URDW_DEL
1.9 ns
3.6 ns
User Read/Write Delay (pad to URDWR_EL)
—
—
—
—
i960 Interface Timing (TJ 85 °C, VDD = min)
Addr/Data Select to ALE (AS, to Alow)
Addr/Data Select to ALE (ADfroALE low)
Ready/Receive lay (K to RDYRCV)
Ready/Receive Deo High Impedance
Write Data Setup Tim
SN_SET
ADSN_HLD
RDYRCV_DEL
RDYRCV_DELZ
WD_SET
2.0
0.0
—
—
—
1.8
0.0
—
—
—
1.6
0.0
—
—
—
1.4
0.0
—
—
—
ns
ns
11.6
9.3
8.0
6.8 ns
(2)
(2)
(2)
(2)
—
—
—
—
ns
ns
ns
(3)
(3)
(3)
(3)
—
—
—
—
—
—
—
—
—
—
6.6
7.0
—
—
—
—
—
—
—
—
—
—
4.3
5.4
—
—
—
—
—
—
—
—
—
—
4.1
4.2
—
—
(4)
(4)
(4)
(4)
Write DaHold Time
WD_HLD
A_SET
A_HLD
BE_SET
BE_HLD
RW_SET
RW_HLD
CS_SET
CS_HLD
Address Sep Time addr to ALE lo)
Adress Hold m(addr from ALE w)
te Eble Setup Time (BE0, BE1 tLE lo
Bynable old Time (BEBE1 from Alow)
ReadWritSetup Time
2.0
2.0
2.0
1.8
1.8
1.8
0.50
0.51
0.50
—
—
—
0.42 ns
0.44 ns
0.42 ns
0.44 ns
—
—
2.0
1.8
0.51
—
(3)
(3)
(3)
(3)
ns
ns
(4)
(4)
(4)
(4)
ad/Write Hold Time
ChSelect Setup Time S0, C1 o CLK)
Cp Select Hold (CSCS1 from CLK)
(1)
2.0
0.0
—
1.8
0.0
—
0.45
0.0
—
—
0.0
—
0.38 ns
ns
(1)
—
User Address low o UA[3:0])
User Read/Wrad to URDWR_DEL)
UA_DEL
URDWR_DEL
3.5 ns
3.6 ns
—
—
—
—
1. For user system fle, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when
MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and CS1 may go
inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
Lattice Semiconductor
113
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 49. Microprocessor Interface (MPI)Timing Characteristics (continued)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Parameter
Symbol
–4
–5
–6
7
Unit
Min Max Min MaMin Max in Max
(5)
User Logic Delay
User Logic Delay
USTART_DEL
—
—
—
—
—
3.6
7.5
—
—
—
—
—
3.4
7.3
—
—
—
—
3.3
7.1
—
—
—
—
—
—
2.8
6.0
ns
ns
ns
ns
(6)
User Start Delay (MPI_CLK falling to USTART)
User Start Clear Delay (MPI_CLK to USTART)
USTARTCLR_DEL
UEND_DEL
(7)
User End Delay (USTART low to UEND low)
Synchronous User Timing:
User End Setup (UEND to MPI_CLK)
User End Hold (UEND to MPI_CLK)
UEND_SET
UEND_HLD
RDS_SET
RDS_HL
0.00
1.0
—
—
—
00
0.95
—
—
—
—
—
0.00
0.88
—
—
—
0.00
.75
—
—
—
ns
ns
ns
ns
(9)
Data Setup for Read (D[7:0] to MPI_CLK)
(9)
Data Hold for Read (D[7:0] from MPI_CLK)
—
—
—
Asynchronous User Timing:
User End to Read Data Delay (UEND to
RDDEL
—
—
—
—
—
—
—
ns
(10)
D[7:0])
(9)
Data Hold from User Start (low)
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
(8)
Interrupt Request Pulse Width
TUW
1. For user system flexibility, CS0 and CS1 may be up to any one of the three rising lock es, benning with the rising clock edge when
MPI_STRB is low. If both chip selects are valid nd setup time is met, the MPl latch the ip select state, and CS0 and CS1 may go
inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid arting from the clock cycle after both AS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held uil the micprocessor receivevalid RRCV.
5. User Logic Delay has no predened va. The er must generate a ND so complete the cycle.
6. USTART_DEL is based on tfalling clock ge.
7. There is no specific time aociatd with this delay. The useert UD low to complete this cycle.
8. The user must assert interruquest lw until a service ruted.
9. This should be at least one MPLK ycle.
10. User should set uread data so tht RDS_SET and S_Hmet for the microprocessor timing.
Notes:
Read and writdescriptions referenced to the homicroproessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA.
PowerPC ai960 mings to/from the clock aelativo the ock at the FPGA microprocessor interface clock pin (MPI_CLK).
114
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
UEND_SET
RDS_HLD
CS_SET
RW_SET
A_SET
CS_HLD
A_HLD
RW_HLD
RDS_SET
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
RDA_DEL
RDA_HLD
D[7:0]
MPI_STRB (TS)
UA[3:0]
UA_DEL
URDWRDEL
URDWRN
USTARTDEL
USTA_DEL
USTART
USOGILAY
UEND_DL
TA_DE
UEND
TA_DEL
_DEL
MPI_ACK (TA)
MPI_BI (BI)
BI_DEL
BI_DEL
BI_DELZ
5-5832(F)
Figure 7. MPI PowerPC ser pace Read Timing
C
WD_HLD
CS_HLD
RW_HLD
RW_
A_SET
UE
A_HLD
MPI_
A[4:0]
PI_RW (RD/WR)
CS0, CS1
WD_SET
7:0]
MTRB (TS)
U]
UA_DEL
URDWR_DEL
DWRN
USTARTCLR_DEL
USTART_DEL
USTART
USER LOGIC DELAY
UEND_DEL
TA_DEL
UEND
TA_DELZ
TA_DEL
MPI_ACK (TA)
MPI_BI (BI)
BI_DEL
BI_DEL
BI_DELZ
5-5840(F)
Figure 68. MPI PowerPC User Space Write Timing
Lattice Semiconductor
115
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
UEND_SET
RDS_HLD
CS_HLD
CS_SET
RW_SET
A_SET
A_HLD
RW_HLD
RDS_SET
MPI_CLK
A[4:0]
MPI_RW (RD/WR)
CS0, CS1
RDA_DEL
RDA_HLD
D[7:0]
MPI_STRB (TS)
UA_DEL
UA[3:0]
URDWR_DEL
URDWRN
TA_DELZ
A_DEL
T
_DEL
MPI_ACK (TA)
MPI_BI (BI)
BI_D
DELZ
5-5832(F).c
Figure 9MPI PowerPC Internal ead Timng
CS_SET
WD_HLD
CS_HLD
RW_HLD
RW_SET
A_SET
A_HLD
MPI_CLK
A[4:0]
MPI_RW (RR)
CS0, CS1
WD_SET
D[7:0]
MPI_STRB (TS)
U
UA_DEL
URDWR_DEL
URDWR
TA_DELZ
TA_DEL
BI_DEL
TA_DEL
BI_DEL
MPI_ACK (TA)
MPI_BI (BI)
BI_DELZ
5-5840(F).e
Figure 70. MPI PowerPC Internal Write Timing
116
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
CS_SET
A_HLD
A_SET
ADSN_HLD
RDS_HLD
ADSN_SET
RDS_SET
RW_HL
_HLD
UEND_SET
RW_SET
MPI_CLK
RDA_HLD
RDA_DEL
ADDR
DAT
D[7:0]
MPI_RW (W/R)
CS0, CS1
BE0, BE1
BE_SET
BE_HLD
MPI_ALE (ALE)
MPI_STRB (ADS)
UA[3:0]
UA_DEL
URDWR_DEL
URDWRN
USTACLR_DEL
USTADEL
USTART
UEND_DEL
GIC DELAY
UEND
RCV_
RDYRCV_DEL
RDYRCV_DEL
MPI_ACK (RDYRCV)
5-5831(F).b
Figu71. MPI i960 User Spce Read Timing
SET
A_HLD
WD_HLD
RW_HLD
CS_HLD
A_SET
_HLD
ADSN_SET
RW_SET
UEND_SET
MPI_CLK
D[7:0]
ADDR
DATA
MPI_RW (W/R
CCS1
_ALE (ALE)
PI_STRDS)
UA[3:0]
UA_DEL
URDWR_DEL
URDWRN
USTART
USTARTCLR_DEL
USTART_DEL
UEND_DEL
USER LOGIC DELAY
UEND
RDYRCV_DEL
RDYRCV_DELZ
RDYRCV_DEL
MPI_ACK (RDYRCV)
5-5830(F).b
Figure 72. MPI i960 User Space Write Timing
Lattice Semiconductor
117
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
CS_SET
A_HLD
A_SET
ADSN_HLD
RDS_HLD
RW_HLD
ADSN_SET
RW_SET
RDS_SET
RDA_DEL
CS_HLD
MPI_CLK
A_HLD
ADDR
DATA
D[7:0]
MPI_RW (W/R)
CS0, CS1
BE0, BE1
BE_SET
BE_HLD
MPI_ALE (ALE)
MPI_STRB (ADS)
UA[3:0]
UA_DEL
URDWR_DEL
URDWRN
RDYRC
RDV_DEL
_DEL
MPI_ACK (RDYRCV)
5-5831(F).c
Figu3. MPI i960 Internal ReTimin
CSET
A_HLD
ADSN_HLD
WD_HLD
RW_HLD
CS_HLD
A_SET
ADSN_T
RSET
WD_
MPI_C
ADDR
DATA
D[7:0]
MPW (R)
CS0, CS1
MPI_ALE (ALE)
MPI_STRB (ADS)
UA_DEL
URDWR_DEL
U
RDYRCV_DEL
RDYRCV_DELZ
RDYRCV_DEL
MPI_ACK (RDYRCV)
5-5830(F).c
Figure 74. MPI i960 Internal Write Timing
118
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 50. Programmable Clock Manager (PCM) Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C ≤TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Parameter
Symbol
-4
-5
6
-7
Unit
Min
Max
Min
Mx
Min
ax
Min
Max
Input Clock Frequency:
OR3Cxx
OR3Txxx
FPCMI
5
—
133
—
5
5
133
133
5
—
133
—
5
—
MHz
133 MHz
Output Clock Frequency:
OR3Cxx
OR3Txxx
FPCMO
5
—
135
5
5
35
100
—
5
100
—
MHz
100 MHz
Input Clock Duty Cycle
Output Clock Duty Cycle
Input Frequency Tolerance*
PCM Acquisition Time (CLK In to
LOCK)
PCMI_DUTY
PCMO_DUTY
FTOL
30.00 700 30.0 70.00 3000 70.00 00 70.00
3.13 6.93.13 96.90 33 96.90 3.13 96.90
%
%
—
2640
100
—
26400
100
—
2640
100
—
26400 ppm
100 µs
PCM_ACQ
6
36
6
36
PCM Off Delay (config. Done-L, WE to
PCM power off)
PCM Delay in DLL Mode (propagation
delay)
PCM Delay in PLL Mode (propagatio
delay)
PCMOL
PCM
PCMPLL_DEL
CMBYE_DEL
PCMBYS_DEL
RTCKD_DEL
—
—
—
—
—
100.0
1.95
0.00
47
0.47
1.30
2.70
—
—
—
—
—
—
100
2
0.00
0.36
0.36
1.10
2.20
—
—
—
—
—
—
100.0
1.63
0.00
0.26
0.26
0.90
1.90
—
—
—
—
—
—
—
100.0 ns
1.50
0.00
0.24
0.24
TBD
ns
ns
ns
ns
ns
PCM Clock In to PCM Clock Out
‡
(CLK In to ECLK)
PCM Clock In to PCM CloOut
‡
(CLK In to SCLK)
Routed Clock-in Day (routing CM
phase detect, ug D0)
System Clock-out lay (PM oscilla- PC
tor to SCLK output aPM)
TBD ns
Parameter
Symbol
fOUT (MHz)
PLL Mode
DLL Mode
Unit
Otput Jitter
UTJIT
5—20
21—30
31—40
41—50
51—60
61—70
71—80
81—90
91—100
250
210
180
155
130
110
95
200
170
145
123
105
90
75
65
55
ps
ps
ps
ps
ps
ps
ps
ps
ps
80
70
* Input frequency tolerance is the allowed input clock frequency change in parts per million.
† See Table 29 and Table 30 for acquisition times for individual frequencies.
‡ PLL mode, divider reg = 1111111 (input freq. = output freq.).
Lattice Semiconductor
119
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 51. Boundary-Scan Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Parameter
TDI/TMS to TCK Setup Time
TDI/TMS Hold Time from TCK
TCK Low Time
Symbol
TS
Min
25.0
0.0
Max
—
Unit
s
TH
—
ns
TCL
50.0
50.0
—
—
ns
TCK High Time
TCH
TD
—
ns
TCK to TDO Delay
20.
10
n
TCK Frequency
TTCK
—
TCK
TS
TH
TMS
TDI
TD
TDO
5-6764(F)
Figure 75. Boundcan ming Diagram
120
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Clock Timing
Table 52. ExpressCLK (ECLK) and Fast Clock (FCLK) Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V40 A < +85 °C.
Seed
Device
(TJ = 85 °C, VDD = min)
Symbol
Unit
-4
-5
-6
-7
Min Max Min Max Min Max Min Max
ECLKC_DEL
ECLKM_DEL
Clock Control Timing Delay Through
CLKCNTRL (input from corner)
0.31
1.54
—
—
31
1.
—
—
31
1.00
—
—
0.31
—
—
ns
ns
Delay Through CLKCNTRL (input from inter-
nal clock controller PAD)
Clock Shutoff Timing:
OFFM_SET
OFFM_HLD
OFFC_ST
OFFC_D
ECLKM_DE
Setup from Middle ECLK (shut off to CLK)
Hold from Middle ECLK (shut off from CLK)
Setup from Corner ECLK (shut off to CLK)
Hold from Corner ECLK (shut off from CLK)
7
0.00
0.77
0.00
—
—
—
0.51
0.00
0.51
0.00
—
—
—
—
0.
0.0
0.44
00
—
—
0.41
.00
0.41
0.00
—
—
—
—
ns
ns
ns
ns
ECLK Delay (middle pad):
OR3T20
—
—
—
—
—
—
3.50
37
—
—
—
—
2.5
.62
2.86
3.06
—
—
—
—
—
2.05
2.08
2.13
2.19
2.29
—
—
—
—
—
1.78
1.80
1.85
1.90
1.98
ns
ns
ns
ns
ns
OR3T30
OR3T55
OR3C/T80
OR3T125
ECLKC_DEL
_DEL
FCLKC_DEL
ECLK Delay (corner pad):
OR3T20
OR3T30
OR3T55
OR3C/T80
—
—
—
—
—
5.47
5.64
—
—
—
—
—
—
4.48
4.53
4.64
4.77
4.96
—
—
—
—
—
3.85
3.97
4.22
4.47
4.85
—
—
—
—
—
3.36
3.47
3.69
3.92
4.27
ns
ns
ns
ns
ns
OR3T125
FCLK Delay (mide pa:
OR3T20
OR3T30
OR3T5
OR3C/T8
—
—
—
—
—
—
—
8.24
8.87
—
—
—
—
—
—
5.91
6.12
6.59
7.11
7.98
—
—
—
—
—
4.59
4.66
4.83
5.01
5.33
—
—
—
—
—
3.81
3.89
4.06
4.26
4.59
ns
ns
ns
ns
ns
OR3T125
LK elay (corner pad):
T20
OR3
R3T55
O3C/T80
—
—
—
—
—
—
—
10.34
11.01
—
—
—
—
—
—
7.88
8.11
8.60
9.15
10.07
—
—
—
—
—
6.41
6.58
6.95
7.34
7.96
—
—
—
—
—
5.40
5.58
5.94
6.33
6.94
ns
ns
ns
ns
ns
R3T125
Notes:
The ECLK delays ahe PICs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay
includes both the inpur delay and the clock routing to the PIC clock input.
The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer
delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
Lattice Semiconductor
121
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 53. General-Purpose Clock Timing Characteristics (Internally Generated Clock)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Device
(TJ = 85 °C, VDD = min)
Symbol
Unit
-4
-5
-6
-7
Min
—
Max
—
Min
—
Max
4.22
4.29
4.41
4.52
4.80
Min
—
Max
3.46
48
3.53
3.57
7
Mn
—
ax
2.84
2.87
2.93
2.9
3.
OR3T20
OR3T30
CLK_DEL
CLK_DEL
CLK_DEL
CLK_DEL
CLK_DEL
ns
ns
ns
s
—
—
—
—
—
OR3T55
—
5.34
5.49
—
—
—
—
OR3C/T80
OR3T125
—
—
—
—
—
—
—
Notes:
This table represents the delay for an internally generated clock from the clock tree put in oe of the four middle PIC(using SW roung) on
any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock e iut used is located at aoter PIC, ee the
results reported by ispLEVER.
This clock delay is for a fully routed clock tree that uses the general clock workhe delay will be reduced if any of e clock ranches are not
used. See pin-to-pin timing in Table 56 for clock delays of clocks input on gel I/O pi.
122
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 54. OR3Cxx ExpressCLK to Output Delay (Pin-to-Pin)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C; CL = 50 pF.
OR3Txxx Commercial:VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial:VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C;CL = 50
pF.
Speed
Description
(TJ = 85 °C, VDD = min)
Device
Unit
-4
-5
-6
-7
Min
Max
Min
Mx
Min
Max
Min
Max
ECLK Middle Input Pin→OUTPUT Pin
(Fast)
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
9.93
10.1
—
—
—
—
7.78
7.84
7.9
8.0
28
—
—
—
—
5.40
5.43
5.48
5.5
5.6
—
—
4.38
4.40
4.44
4.49
4.58
ns
ns
ns
ns
ns
ECLK Middle Input Pin→OUTPUT Pin
(Slewlim)
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T12
—
—
—
—
—
.3
12.54
—
—
—
—
—
9.77
9.83
9.95
10.07
10.27
—
—
—
6.07
6.0
6.15
6.21
61
—
—
—
4.91
4.93
4.97
5.02
5.11
ns
ns
ns
ns
ns
ECLK Middle Input Pin→OUTPUT Pin
(Sinklim)
OR3T20
O
OR
OR3
—
—
—
—
—
—
13.73
13.90
—
—
—
—
112
11.1
.30
12
11.62
—
—
—
—
—
10.92
10.95
11.00
11.06
11.16
—
—
—
—
—
9.65
9.67
9.71
9.76
9.85
ns
ns
ns
ns
ns
Additional Delay if ECLK Corner Pin ed
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
—
—
—
—
97
1.9
—
—
—
—
—
1.91
1.91
1.91
1.91
1.90
—
—
—
—
—
1.80
1.90
2.09
2.28
2.57
—
—
—
—
—
1.58
1.67
1.84
2.02
2.29
ns
ns
ns
ns
ns
Notes:
Timing is without the e of the programmable clock maner (PC.
This clock delay is fofurouted clock tree that usssCLK network. It includes both the input buffer delay, the clock routing to the
PIO CLK input, the clocQ of e FF, and the delautput buffer. The given timing requires that the input clock pin be located at
one of the six ExpressCLK uts of the device, and tbe used.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
CLKCNTRL
ECLK
EC
5-4846(F).a
Figure 76. ExpressCLK to Output Delay
Lattice Semiconductor
123
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 55. OR3Cxx Fast Clock (FCLK) to Output Delay (Pin-to-Pin)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C; CL = 50 pF.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C;
CL = 50 pF.
Speed
Description
(TJ = 85 °C, VDD = min)
Device
Unit
-4
-5
-7
Min
Max
Min
Max
Min
x
Mn
Max
Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpresCLK Inpts)
ECLK Middle Input Pin →OUTPUT Pin
(Fast)
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
14.68
15.30
—
—
—
—
—
—
11.1
11.35
181
12.
13.20
—
—
—
—
7.94
8.01
8.18
8.36
8.68
—
—
—
—
6.40
6
7.19
ns
s
ns
ECLK Middle Input Pin →OUTPUT Pin
(Slewlim)
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
—
—
—
—
17.1
4
—
—
—
—
3.12
.33
13.80
14.32
15.19
—
—
—
—
—
8.61
88
8.85
9.04
9.35
—
—
—
—
6.93
.01
7.19
7.38
7.72
ns
ns
ns
ns
ns
ECLK Middle Input Pin →OUTPUT Pin
(Sinklim)
OR3T20
OR3T30
OR3T55
ORC/T80
R125
—
—
—
—
18.47
19.10
—
—
—
—
—
—
14.47
14
15.15
167
16.
—
—
—
—
—
13.46
13.53
13.70
13.88
14.20
—
—
—
—
—
11.67 ns
11.75 ns
11.93 ns
12.12 ns
12.46 ns
Additional Delay if ECLK Corner Pin
Used
OR3T
OR3T30
OR3T55
ORC/T80
R3T125
—
—
—
—
—
—
2.10
4
—
—
—
—
—
—
1.97
1.99
2.01
2.04
2.09
—
—
—
—
—
1.82
1.92
2.12
2.33
2.63
—
—
—
—
—
1.60
1.69
1.88
2.07
2.39
ns
ns
ns
ns
ns
Notes:
Timing is without the use of the prammle clock manager
This clock delay is for fully routed clotree that uses thprimatwork. It includes both the input buffer delay, the clock routing to the
PIO CLK input, the clocQ of the FF, and the delay rough the output buffer. The delay will be reduced if any of the clock branches are not
used. The given ming reqes tt the input clock pbe locateat one of the six ExpressCLK inputs of the device and that a PIO FF be used.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
CLKCNTRL
FCLK
CLK
5-4846(F).b
Figure 77. Fast Clock to Output Delay
124
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 56. OR3Cxx General System Clock (SCLK) to Output Delay (Pin-to-Pin)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C; CL = 50 pF.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C;
CL = 50 pF.
Sped
Description
(TJ = 85 °C, VDD = min)
Device
Unit
-4
Min Max Min MMin Max Min Max
Output On Same Side of Device As Input Clock (System Clock Delays UsiGeneral seI/O Inputs)
-5
-6
-7
Clock Input Pin (mid-PIC) →OUTPUT Pin (Fast) OR3T20
—
—
—
—
—
—
—
14.9
5.71
—
—
—
11.5
11.3
.17
12.80
13.69
—
—
—
—
—
7.74
7.93
8.2
8.66
9.24
—
6.10 ns
6.27 ns
.59 ns
6.95 ns
7.49 ns
OR3T30
OR3T55
OR3C/T80
OR3T125
Clock Input Pin (mid-PIC) →OUTPUT Pin
(Slewlim)
OR3T20
OR3T3
OR35
OR3C/T
T125
—
—
—
—
—
17.34
18.14
—
—
—
—
—
—
13.34
13.62
14.16
.79
158
—
—
—
—
.42
8.60
85
9.34
9.91
—
—
—
—
—
6.63 ns
6.80 ns
7.12 ns
7.48 ns
8.02 ns
Clock Input Pin (mid-PIC) →OUTPUT Pin
(Sinklim)
0
55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
170
19.
—
—
—
—
—
4.69
7
15.51
16.14
17.03
—
—
—
—
—
13.26
13.45
13.80
14.18
14.76
—
—
—
—
—
11.37 ns
11.54 ns
11.86 ns
12.22 ns
12.76 ns
Additional Delay if Non-mid-PIC Used as ock
Pin
OR3T20
OR3T30
OR3T55
OR3
OR3T15
—
—
—
—
—
0.41
0.63
—
—
—
—
—
—
0.16
0.20
0.36
0.55
1.11
—
—
—
—
—
0.18
0.21
0.37
0.57
1.05
—
—
—
—
—
0.17 ns
0.20 ns
0.35 ns
0.55 ns
1.02 ns
Output Not on Sme Sde of Device
As InpuSystm Clock Delays Using General User I/O Inputs)
Additional Delay if Out Nt on Same Side a
Input Clock Pin
0
30
OR3T55
OR3C/T80
OR3T125
—
—
—
—
—
—
—
0.41
0.63
—
—
—
—
—
—
0.16
0.20
0.36
0.55
1.11
—
—
—
—
—
0.18
0.21
0.37
0.57
1.05
—
—
—
—
—
0.17 ns
0.20 ns
0.35 ns
0.55 ns
1.02 ns
Note
This clodlay is for a fully roud ck trthat uses the primary clock network. It includes both the input buffer delay, the clock routing to the
CLK input, the clock→of the FF, and he delay through the output buffer. The delay will be reduced if any of the clock branches are not
useThe given timing requirthat tput clock pin be located at one of the four center PICs on any side of the device and that a PIO FF be
us. For clock pins d at aother PIO, see the results reported by ispLEVER.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
SCLK
5-4846(F)
Figure 78. System Clock to Output Delay
Lattice Semiconductor
125
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Description
Device
Unit
-4
-5
-6
-7
(TJ = 85 °C, VDD = min)
Min
Max
Min
Max
Min
Mx
Min
Max
Input to ECLK Setup Time (middle
ECLK pin)
ns
ns
ns
ns
s
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
1.36
1.25
—
—
—
—
—
—
1.34
1.30
1.22
1.14
1.03
—
—
—
—
—
0.88
0.86
083
80
0.
—
—
0.83
0.2
0.80
0.77
0.74
—
—
—
—
Input to ECLK Setup Time (middle
ECLK pin, delayed data input)
s
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
6.91
6.79
—
—
—
—
—
—
6.30
6.27
6.1
.11
6.00
—
—
—
.32
50
5.27
5.24
5.20
—
—
—
—
—
5.98
5.7
95
5
5.90
—
—
—
—
Input to ECLK Setup Time (corner
ECLK pin)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
0.00
0.0
—
—
—
000
00
0.
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0
—
—
—
00
00
00
0.00
0.00
—
—
—
—
—
Input to ECLK Setup Time (corner
ECLK pin, delayed data input)
ns
ns
ns
ns
ns
OR3T20
OR3T
OR3T55
OR3C/T80
OR3T125
—
—
4.94
82
—
—
—
—
—
4.39
4.35
4.28
4.21
40
—
—
—
—
3.5
3.40
38
2.98
2.63
—
—
—
—
—
4.41
4.31
4.11
3.91
3.61
—
—
—
—
—
Input to ECLK Hold
ECLK pin)
Time (middle
ns
ns
ns
ns
ns
OR3T2
R3T3
OR3T55
OR3C/T80
OR3T125
—
—
0.00
0.0
—
—
—
—
0.00
0.00
.00
0.0
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
Input to ECLK Hold Time (middle
ECLK pin, delayedata input)
ns
ns
ns
ns
ns
OR3T20
OR3T3
OR3T5
OR3C/T8
OR3T125
—
—
0.0
0.0
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
No
Thpinpin ming parameters in thable should e used instead of results reported by ispLEVER.
The ECLK delys are to all of thIOs on ne side of the device for middle pin input, or two sides of the device for corner pin input. The delay
includes bh the input buffethe cck routing to the PIO clock input.
126
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin) (continued)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Description
(TJ = 85 °C, VDD = min)
Device
Unit
-4
-5
-6
-7
Min
Max
Min
Max
in
Max
Min
Max
Input to ECLK Hold Time (corner
ECLK pin)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.0
—
—
—
—
00
0.0
0.80
00
00
—
—
—
—
0.00
0.00
1.10
0.0
—
—
—
—
—
Input to ECLK Hold Time (corner
ECLK pin, delayed data input)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
—
—
—
—
—
00
00
0.0
0
0.00
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
0
0.0
0.00
0.0
00
—
—
—
—
Notes:
The pin-to-pin timing parameters in this table should be usinsteaf relts reported by ispLEVR.
The ECLK delays are to all of the PIOs on one side oor middle pin input, or two sis of thvice for corner pin input. The delay
includes both the input buffer delay and the clock routclock input.
PIO ECLATH
PUT
CLK
D
Q
CLKCTRL
LK
5-4847(F).b
Figure 79. xpressCLK Setup/Hold Time
Lattice Semiconductor
127
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Description
Device
Unit
-4
-5
-6
-7
(TJ = 85 °C, VDD = min)
Min
Max
Min
Max
Min
Mx
Min
Max
Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK nuts)
Input to FCLK Setup Time (middle
ECLK pin)
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
0.0
000
00
0.0
.00
—
—
—
—
00
0.00
0.00
0.00
0.00
—
—
—
—
Input to FCLK Setup Time (middle
ECLK pin, delayed data input)
s
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
0.29
0.14
—
—
—
—
—
—
0.80
0.74
.62
0.5
02
—
—
—
—
—
0.
0.55
0.51
0.46
0.33
—
—
—
—
—
2.0
17
2.1
2.06
10
—
—
—
—
—
Input to FCLK Setup Time (corner
ECLK pin)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
00
0.0
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
.00
0
0.0
—
—
—
0.
.00
0.00
0.00
0.00
—
—
—
—
—
Input to FCLK Setup Time (corner
ECLK pin, delayed data input)
ns
ns
ns
ns
ns
OR3T0
OR3T30
3T55
OR3C/T80
OR3T12
—
—
00
0.00
—
—
—
—
—
—
0.00
0.0
0.00
0.0
0.00
—
—
—
—
00
0.0
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
Input to FCLK Hold
ECLK pin)
Time (midle
ns
ns
ns
ns
ns
R3T0
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
6.3
6.9
—
—
4.29
50
4.97
5.49
6.36
—
—
—
—
—
3.72
3.80
3.96
4.15
4.47
—
—
—
—
—
3.27
3.35
3.52
3.72
4.05
—
—
—
—
—
Notes:
The pin-to-ptiminarametrs in this table should used inead of results reported by ispLEVER.
The FCLK delare for ully routed cloctree that uses e ExpressCLK input into the fast clock network. It includes both the input buffer
delay the cloroung to the PFU CLinpudelay will be reduced if any of the clock branches are not used.
128
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin) (continued)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Description
Device
Unit
-4
-5
-6
-7
(TJ = 85 °C, VDD = min)
Min
Max
Min
Max
in
Max
Min
Max
Input to FCLK Hold Time (middle
ECLK pin, delayed data input)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.0
—
—
—
—
00
0.0
0.00
00
00
—
—
—
—
0.00
0.00
0.00
0.0
—
—
—
—
Input to FCLK Hold Time (corner
ECLK pin)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
8.43
9.09
—
—
—
—
—
—
26
69
6.9
5
8.45
—
—
—
—
5.54
5.72
6.09
6.47
7.10
—
—
—
—
4
5.04
5.40
5.7
640
—
—
—
—
Input to FCLK Hold Time (corner
ECLK pin, delayed data input)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T
OR3T125
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
0.00
00
0.0
0.00
0
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
Notes:
The pin-to-pin timing parameters in this tshould be used instead of ress reporteby ispLEVER.
The FCLK delays are for a fully routed clock trthat uses the ExpressK iut into the ast clock network. It includes both the input buffer
delay and the clock routing to the CLK inputhe delay will be rduced if aof the clock branches are not used.
PIO FF
INPU
ECL
D
Q
CLKCNTRL
FCLK
5-4847(F).a
Figure 80. Input to Fast Clock Setup/Hold Time
Lattice Semiconductor
129
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 59. OR3C/Txxx Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Speed
Description
Device
Unit
-4
-5
-6
-7
(TJ = 85 °C, VDD = min)
Min
Max
Min
Max
Min
Ma
Min
ax
Input to SCLK Setup Time
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
0.00
0.00
0.0
0.0
0.0
—
—
—
—
—
0.00
0.0
00
0.00
0.00
—
—
—
—
Input to SCLK Setup Time
(delayed data input)
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
0.99
0.79
—
—
—
—
—
—
1.33
1.22
1.09
03
0.78
—
—
—
—
47
1.4
1.33
1.26
1.19
—
—
—
—
—
3.09
3.03
27
2.9
2.86
—
—
—
—
—
Input to SCLK Hold Time
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
—
—
6.82
7.62
—
—
—
4.4
1
5.5
6.19
7.07
—
—
—
—
—
3.64
3.83
4.18
4.56
—
—
—
3.
3.2
3.4
3.89
4.44
—
—
—
—
—
Input to SCLK Hold Time
(delayed data input)
ns
ns
ns
ns
ns
OR3T20
OR3T30
OR3T55
OR3C/T80
R3T125
—
—
0.00
0
—
—
—
—
—
—
0.00
0.00
0.00
0.00
0.
—
—
—
—
—
0.00
00
0.0
0.00
0.00
—
—
—
—
—
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
Additional Hold
mid-PIC Used as SCLK Pin
(no delay on data input)
Time if Non-
ns
ns
ns
ns
ns
R3T20
O3T30
OR3T55
OR3C/T80
O3T125
—
—
0.41
0.63
—
—
—
0.16
0.20
36
0.5
1.11
—
—
—
—
—
0.18
0.21
0.37
0.57
1.05
—
—
—
—
—
0.17
0.20
0.35
0.55
1.02
—
—
—
—
—
Notes:
The pin-to-pin timng pareters ihis table should e used instead of results reported by ispLEVER.
This clock dey is for a fully ed clock tree that usthe clocetwork. It includes both the input buffer delay and the clock routing to the PIO
FF CLK inpThe elay will be reduced if anthe clbrahes are not used. The given setup (delayed and no delay) and hold (delayed)
timing allows tnput clk pin to be locad in any PIO on any side of the device, but a PIO FF must be used. The hold (no delay) timing
assues the clocin s located at one of e mile PICs on any side of the device and that a PIO FF is used. If the clock pin is located
elswheren the ast parameter in he table must badded to the hold (no delay) timing.
PIO FF
INPUT
SCLK
D
Q
5-4847(F)
Figure 81. Input to System Clock Setup/Hold Time
130
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Configuration Timing
Table 60. General Configuration Mode Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, 40 °C < TA < +85 °C.
Parameter
All Configuration Modes
Symbol
Min
Max
Unit
M[3:0] Setup Time to INIT High
TSMODE
THMODE
TRW
0.00
00.00
50.00
.00
—
—
—
—
ns
ns
ns
ns
M[3:0] Hold Time from INIT High
RESET Pulse Width Low to Start Reconfiguration
PRGM Pulse Width Low to Start Reconfiguration
Master and Asynchronous Peripheral Modes
TPGW
Power-on Reset Delay
TPO
15.70
60.00
52.0
20.00
00.00
ms
ns
ns
CCLK Period (M3 = 0)
(M3 = 1)
TCCL
480.00
Configuration Latency (autoincrement mode):
TCL
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
11.50
92.10
38.40*
307.00*
50.40*
403.30*
77.40*
619.00*
113.00*
900.00*
175.00*
1395.00*
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
110
121.0
23.20
85.
3.70
2700
52.30
18.00
Microprocessor (MPI) Moe
Power-on Reset Delay
Configuration Latency (auoincremnt mode):
TO
T
15.70
52.40
ms
OR3T20
OR3T30
OR3T55
OR3C/T80
OR3T125
27413
35445
53341
76317
116581
—
—
—
—
—
write cycles
write cycles
write cycles
write cycles
write cycles
Partial Ronfiguration (explicit mo):
TPR
R3T20
OR3T30
ORT55
R3C/T0
3T25
32
36
43
51
62
—
—
—
—
—
write cycles
write cycles
write cycles
write cycles
write cycles
ve Serial Mode
Poer-on Reset Delay
TPO
3.90
13.10
ms
CLK Period
TCCLK
OR3Cxx
OR3Txxx
40
15
—
—
ns
ns
Configuration Lautoincrement mode):
TCL
OR3T20
OR3T30
OR3T55
OR3C80
OR3T80
OR3T125
2.80
3.80
—
—
—
—
—
—
ms
ms
ms
ms
ms
ms
5.80
22.50
8.40
13.09
* Not applicable to asynchronous peripheral mode.
Lattice Semiconductor
131
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 60. General Configuration Mode Timing Characteristics (continued)
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Parameter
Slave Parallel Mode
Symbol
Min
Max
Unit
Power-on Reset Delay
TPO
3.90
13.0
ms
CCLK Period:
TCCLK
OR3Cxx
OR3Txxx
40.00
15.00
—
ns
ns
Configuration Latency (normal mode):
TCL
TPR
OR3T20
OR3T30
OR3T55
OR3C80
OR3T80
OR3T125
0.3
47
02
2.
1.
1.64
—
—
—
—
—
—
ms
ms
ms
Partial Reconfiguration (explicit mode):
—
—
—
—
—
—
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
OR3T20
OR3T30
OR3T55
OR3C80
OR3T80
OR3T125
0.48
0.54
0.65
2.4
0.77
0.93
INIT Timing
INIT High to CCLK Delay:
Slave Parallel
Slave Serial
Master Serial:
(M3 = 1)
TINIT_CCLK
1.00
1.00
—
—
µs
µs
1.00
0.50
3.40
2.00
µs
µs
(M3 = 0)
Master Parallel
(M3 = 1)
(M3 = )
4.80
1.00
16.20
3.60
µs
µs
Initializatiatency (PRGM high tINIT high
TIL
ms
ms
ms
ms
ms
3T20
OR3T30
R3T5
OR3CT80
OR3T125
0.21
0.24
0.30
0.36
0.45
0.68
0.79
1.00
1.20
1.50
INIT High to WR, AsyncPeripheral
TINIT_WR
2.00
—
µs
Note: TPO is triggered when VDD reches between 3.0 V to 4.0 V for the OR3Cxx and between 2.7 V and 3.0 V for the OR3Txxx.
132
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
VDD
TPO + TIL
PRGM
TPGW
TIL
INIT
TINIT_CLK
CCLK
CCLK
D
TSMODE
M[3:0]
TC
DONE
5-4531(F)
Figure 82. Gneral Configration Mde Timing Diagram
Lattice Semiconductor
133
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 61. Master Serial Configuration Mode Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Parameter
DIN Setup Time*
Symbol
TS
Min
60.00
0.00
5.00
0.63
—
Max
—
nit
s
DIN Hold Time
TH
—
ns
CCLK Frequency (M3 = 0)
CCLK Frequency (M3 = 1)
CCLK to DOUT Delay
FC
16.67
2.08
5.00
MHz
MHz
FC
TD
* Data gets clocked out from an external serial ROM.The clock to data delay of the serial OM mt be less than the CCLK freque
data available out of the serial ROM must be setup and waiting to be clocked into the FPGbefore e next CCLK rising dge.
Note: Serial configuration data is transmitted out on DOUT on the falling edge of CK after is input on DIN.
CCLK
TS
TH
DIN
BIT N
D
DOUT
N
5-4532(F)
Figure 8. MasteSerial Configation de Timing Diagram
134
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 62. Master Parallel Configuration Mode Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Parameter
RCLK to Address Valid
D[7:0] Setup Time to RCLK High
D[7:0] Hold Time to RCLK High
RCLK Low Time (M3 = 0)
RCLK High Time (M3 = 0)
RCLK Low Time (M3 = 1)
RCLK High Time (M3 = 1)
CCLK to DOUT
Symbol
TAV
Min
—
Mx
60.00
—
Unit
ns
TS
60.00
0.00
7.00
1.00
7.
1.00
—
ns
TH
—
ns
TCL
TCH
TCL
TCH
TD
00
1.00
7.00
1.0
50
CCLK cycles
LK cycles
cycles
K cycles
ns
Notes:
The RCLK period consists of seven CCLKs for RCLK low and CCfor RCLK high.
Serial data is transmitted out on DOUT 1.5 CCLK cycles after the is inpon D[7:0].
A[17:0]
TAV
TCH
TCL
RCLK
T
TH
D[7:0]
CCLK
BYTE N + 1
BYTE N
DOUT
D0
D1
D2
D3
D4
D5
D6 D7
TD
5-6764(F)
Figre 84. aster Parallel Configuration Mode Timing Diagram
Lattice Semiconductor
135
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 63. Asynchronous Peripheral Configuration Mode Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Parameter
Symbol
TWR
Min
Max
nit
WR, CS0, and CS1 Pulse Width
50.00
—
s
D[7:0] Setup Time:
3Cxx
3Txxx
TS
20.00
10.50
—
—
ns
ns
D[7:0] Hold Time
TH
TRDY
TB
0.00
—
—
ns
RDY Delay
40.00
80
—
RDY Low
1.00
0.00
—
CCL
Earliest WR After RDY Goes High*
RD to D7 Enable/Disable
CCLK to DOUT
TWR2
TDEN
TD
ns
ns
ns
40.00
5.00
—
* This parameter is valid whether the end of not RDY is determined from thRpin or from the D7 pin.
Notes:
Serial data is transmitted out on DOUT on the falling edge of CCbyte input on D[7:0].
D[6:0] timing is the same as the write data portion of the D7 wae D[6:0] are not ebled by
CS0
CS1
TWR
WR
TS
H
TWR2
D7
WRITE DATA
TDEN
TDEN
RD
RDY
TB
TRDY
CCLK
DOUT
TD
D0
D1
D2
PREVIOUS BYTE
D3
D7
5-4533(F)
Figure 85. Asynchronous Peripheral Configuration Mode Timing Diagram
Lattice Semiconductor
136
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 64. Slave Serial Configuration Mode Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Parameter
Symbol
Min
Max
Unit
DIN Setup Time:
3Cxx
3Txxx
TS
20.00
10.50
—
—
ns
ns
DIN Hold Time
TH
0.00
—
ns
CCLK High Time:
3Cxx
3Txxx
TCH
20.00
7.00
—
—
s
CCLK Low Time:
3Cxx
3Txxx
TCL
FC
200
7.00
—
—
ns
ns
CCLK Frequency:
3Cxx
3Txxx
—
—
25.00
600
MHz
MHz
CCLK to DOUT
TD
—
20.00
ns
Note: Serial configuration data is transmitted out on DOUfalling edge of CLK aer it is input on DIN.
BIT N
DIN
TS
CLK
DOU
TCL
TCH
TD
BIT N
5-4535(F).
igure 6. Slave Serial Configuration Mode Timing Diagram
Lattice Semiconductor
137
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 65. Slave Parallel Configuration Mode Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.
Parameter
CS0, CS1, WR Setup Time
CS0, CS1, WR Hold Time
Symbol
TS1
Min
Max
—
nit
s
40.00
20.00
TH1
—
ns
D[7:0] Setup Time:
3Cxx
3Txxx
TS2
20.00
7.00
—
—
ns
ns
D[7:0] Hold Time
TH2
TCH
0.00
—
CCLK High Time:
3Cxx
3Txxx
20.00
7.00
—
—
ns
ns
CCLK Low Time:
3Cxx
3Txxx
TCL
FC
200
.00
—
—
ns
ns
CCLK Frequency:
3Cxx
3Txxx
—
—
25.
66.00
MHz
MHz
Note: Daisy-chaining of FPGAs is not supported in tmode.
CS0
CS1
WR
TS1
TCL
TH1
TCH
CLK
TH2
S2
D[7:0]
5-2848(F)
Figure 87. Slave Parallel Configuration Mode Timing Diagram
138
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Microprocessor Interface (MPI) Configuration Timing Characteristics
For configuration timing using the MPI, consult Table 49. See Figures 67 through 74 for MPI timing diagrams.
Lattice Semiconductor
139
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Readback Timing
Table 66. Readback Timing Characteristics
OR3Cxx Commercial: VDD = 5.0 V 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V 10%, –40 °C < TA < +85 °C.
OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < 8C.
Parameter
RD_CFG to CCLK Setup Time
RD_CFG High Width to Abort Readback
CCLK Low Time
Symbol
TS
Min
50.00
2
Mx
—
Unit
ns
TRBA
TCL
—
CCLK cycles
40.00
40.00
—
—
ns
CCLK High Time
TCH
FC
—
CCLK Frequency
12.50
40.00
ns
CCLK to RD_DATA Delay
TD
—
TRBA
RD_CFG
TCL
TS
CCLK
TCH
TD
RD_DATA
BIT 0
BIT 0
BIT 1
5-4536(F)
Figure 88. RTimig Diagram
140
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Input/Output Buffer Measurement Conditions
VCC
GND
1 kΩ
TO THE OUTPUT UNDER TEST
50 pF
TO THE OUTPUT UNER TST
50 pF
A. Load Used to Measure Propagation Delay
B. Load Used to easurRisinFalling Edges
Note: Switch to VDD for TPLZ/TPZL; switch to GND for TPHZ/TPZH.
5-3234(F)
Figure . c TesLoads
ts[i]
PAD
OUT
ou]
ac T LOADS HOWN ABOVE)
VDD
VDD/2
VSS
out[i]
PAD
OUT
1.5 V
0.0 V
TPLL
TPHH
5-3233.a(F)
Figure 90. Output Buffer Delays
PAD
IN
in[i]
3.0 V
PAD IN 1.5 V
0.0 V
VDD
in[i] VDD/2
VSS
TPLL
TPHH
5-3235(F)
Figure 91. Input Buffer Delays
Lattice Semiconductor
141
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Output Buffer Characteristics
OR3Cxx
70
50
40
I
OL
IOL
60
50
40
30
20
30
20
IOH
IOH
10
10
0
1
2
3
4
5
0
1
2
3
4
5
OUTPUT VOAGE, V
OUTPUT VOLTAGE, VO (V)
5-4634(F)
5-4635(C)
Figure 92. Sinklim (TJ = 25 ¡C, VDD = 5.0 V)
gure 95. Sinklim (TJ = 125 , VDD = 4.5 V)
150
250
225
IOL
IOL
1
200
175
150
125
100
100
IOH
50
75
IOH
50
25
0
25
0
0
1
2
3
4
0
1
2
4
5
OUTPUT VOLTAGE, VO (V)
OUTPUT VOLTAGE, VO (V)
5-4636(F)
5-4637(F)
Figur93. SlewliTJ = 25 ¡C, VDD 5.0 V)
Figure 96. Slewlim (TJ = 125 ¡C, VDD = 4.5 V)
250
175
150
5
IOL
0
175
150
125
100
IOL
125
100
75
IOH
75
50
IOH
50
25
0
25
0
0
1
2
3
4
5
0
1
2
3
4
OUTPUT VOLTAGE, VO (V)
OUTPUT VOLTAGE, VO (V)
5-4638(F)
5-4639(F)
Figure 94. Fast (TJ = 25 ¡C, VDD = 5.0 V)
Figure 97. Fast (TJ = 125 ¡C, VDD = 4.5 V)
Lattice Semiconductor
142
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Output Buffer Characteristics (continued)
OR3Txxx
90
80
70
60
50
4
0
2
0
0
110
100
IOL
IOL
90
80
70
60
IOH
50
IOH
40
30
20
10
0
0.0 0.5
1.0
1
2.0
2.5
3.0
0.0 0.5 1.0
1.5
2.0
2.5
3.0 3.5
OUUT VOAGVO (V)
OUTPUT VOLTAGE, VO (V)
5-5(F)
5-6866(F)
Figure 98. Sinklim (TJ = 25 ¡C, VDD = 3.3 V)
Figure 101. Silim (TJ = 125 ¡C, VDD = 3.0 V)
120
140
IOL
IOL
120
100
80
1
0
60
60
IOH
IOH
40
40
20
0
20
0
0.0 0.5
1.0
1.5
2.0
2.5 3.0
0.0 0.5
1.0 1.5
2.0
2.5 3.0 3
OUTPUT VOLTAGE, VO (V)
OUTPUT VOLTA, VO (V)
5-6967(F)
5-6868(F)
gure 9. Slewlim (J = 25 ¡C, VDD = 3.3 V)
Figure 102. Slewlim (TJ = 125 ¡C, VDD = 3.0 V)
140
120
IOL
IOL
120
1
80
100
80
60
60
IOH
IOH
40
40
20
0
20
0
0.0 0.5
1.0 1.5
2.0
2.5 3.0 3.5
0.0 0.5
1.0
1.5
2.0
2.5 3.0
OUTPUT VOLTAGE, VO (V)
OUTPUT VOLTAGE, VO (V)
5-6868(F)
5-6867(F)
Figure 103. Fast (TJ = 125 ¡C, VDD = 3.0 V)
Figure 100. Fast (TJ = 25 ¡C, VDD = 3.3 V)
Lattice Semiconductor
143
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
The power dissipated by an input buffer is estimated
as:
Estimating Power Dissipation
OR3Cxx
PCMOS = 0.17 mW/MHz
The ac power dissipation from an output or bidirec-
tional is estimated by the following:
The total operating power dissipated is estimated by
summing the standby (IDDSB), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
POUT = (CL + 8.8 pF) x VDx F ts
where the unit for CL is faradsand the unit r F is Hz.
As an example of estimatinpoer dissipation, sup-
pose that a fully utilized OR3C0 has an average of six
outputs for each of te 484 PFUhat 10 clock
brances are used sthat the lock is driven to
entire PLC arra, tha150 of he 484 PFUs
clocked at 4MHand that the PFUoutput
average activy factof 20%.
PT = Σ PPLC + Σ PPIC
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU out-
put power can be estimated based upon the number of
PFU outputs switching when driving an average fan-out
of two:
Twenty T-cogured inputs, 20 MO-configured
inputs, 32 outpdriving 30 ploadsand 6 biderec-
nal Os driving 50 pF loads aralso gerated from
th0 MHclock with an erage aivity factor of
20%Alof the ouptut IOs e regtered, and 30 of
PPFU = 0.136 mW/MHz
For each PFU output that switches, 0.136 mW/MHz
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can be esti-
mated by using one-half the clock rate, multiplied b
some activity factor; for example, 20%.
e input PIOs are registed. The worst-case (V
=
DD
5 V) power disn stimated as follows:
PPFU = 484 x 0.13mW/MHz x 20 MHz x 20%)
= 579.78 W
The power dissipated by the clock generation circuitry
is based upon four parts: the fixed clock er, the
power/clock branch row or column, the clock wer dis-
sipated in each PFU that uses this pcular cloc, and
the power from the subset of thosPFUs that are con-
figured as synchronous memory. hereforthe clock
power can be calculated for the fouarts using the fol-
lowing equations:
PCLK [4X [0.224 mW/MHz + (0.288 mW/MHz/Branch)
(10 Bnches)
+ (0.033 mW/MHz/PFU) (150 PFUs)
.008 mW/MHz/PIO) (58 PIOs)]
= 340.72 mW
PTTL
= 20 x [2.2 mW + (0.17 mW/MHz x 20 MHz x 20%)]
= 57.6 mW
OR3C80 Clock Power
CMOS = 20 x [0.17 mW x 20 MHz x 20%]
= 13.6 mW
POUT = 32 x [(30 pF + 8.8 pF) x (5.25)2 x 20 MHz x 20%]
P
= [0.224 mWMHz
+ (0.28 mW/Mz/Banch) (# Brances)
+ (033 W/MHz/PFU) (# PFUs)
+ (0.mW/MHz/PIO (# PIs)]
= 136.89 mW
PBID
Total
= 16 x [(50 pF + 8.8 pF) x (5.25)2 x 20 MHz x 20%]
= 103.72 mW
Foa quick estiate, the worst-castypiccircuit)
ORC0 clk power ≈ 21.06 W/MHz.
= 2.23 W
The poedissipated in is thsum of the power
dissipated in the four PIC. This consists of
power dissipated by inpc power dissipated by
outputs.The power dissipain each PIO depends on
whether it is configured as an input, output, or input/
output. If a PIO is operating as an output, then there is
a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the
input.
The power dissipated by a TTL input buffer is estimated
as:
PTTL = 2.2 mW + 0.17 mW/MHz
144
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T55 Clock Power
= [0.88 mW/MHz
Estimating Power Dissipation (continued)
P
OR3Txxx
+ (0.102 mW/MHz/Branch) (# Branches)
+ (0.015 mW/MHz/PFU) (# PFUs)
+ (0.004 mW/MHz/PIO (# PIOs)]
The total operating power dissipated is estimated by
summing the standby (IDDSB), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
For a quick estimate, the wrst-case (typical circuit)
OR3T55 clock power ≈ 6.58 W/MH.
OR3T80 Clock Powr
P
= [0.107 mW/
PT = Σ PPLC + Σ PPIC
+ (0.12mW/MH/Brnch) (# Branches)
+ (0.5 mW/MHz/PFU) (# PFUs)
+ (0.04 mW/Hz/PIO (# PIO
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU out-
put power can be estimated based upon the number of
PFU outputs switching when driving an average fan-out
of two:
For quiestimate, the worst-cascircuit)
OR380 clopower ≈ 9.47 W/MHz
OR3Clock Power
PPFU = 0.068 mW/MHz
P
= [0.167 mW/MHz
For each PFU output that switches, 0.068 mW/MH
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can b
mated by using one-half the clock rate, mu
some activity factor; for example, 20%.
+ (0.193 mMHz/Brnch) (# Branches)
+ (0.015 mW/Hz/PFU) (# PFUs)
+ (0.004 m/MHz/PIO (# PIOs)]
For a quick stimathe worst-case (typical circuit)
OR3T15 clopower ≈ 15.44 mW/MHz.
The power dissipated by the clock generation ciritry
is based upon four parts: the fixeock power, the
power/clock branch row or column, thclock power dis-
sipated in each PFU that usthis particar clock, and
the power from the subseof those PFUs configured as
synchronous memory. Thefore, te clock power
be calculated for thfour ps ung the following
equations.
e power ssipated in a PIC is the sum of the power
dissated in the four PIOs in the PIC. This consists of
power issipated by inputs and ac power dissipated by
outputs.The power dissipated in each PIO depends on
ether it is configured as an input, output, or input/
output. If a PIO is operating as an output, then there is
a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the
input.
OR3T20 Clock Pow
P
= [0.8 mW/MHz
The power dissipated by an input buffer (VIH = VDD –
0.3 V or higher) is estimated as:
+ (0.04mW/MHz/Branch) Brancs)
+ 0.015 mW/MHz/PFU) (# PUs)
+ (0.04 mW/MHz/PO (# PIOs)]
PIN = 0.09 mW/MHz
The ac power dissipation from an output or bidirec-
tional is estimated by the following:
For a qk estimate, the wst-cas(typical circuit)
ORT20 clock power ≈ .92 mW/Hz.
2
POUT = (CL + 8.8 pF) x VDD x F Watts
3T30 Clock
where the unit for CL is farads, and the unit for F is Hz.
P
= [0.53
+ (0.061 mz/Branch) (# Branches)
+ (0.015 mW/MHz/PFU) (# PFUs)
+ (0.004 mW/MHz/PIO (# PIOs)]
For a quick estimate, the worst-case (typical circuit)
OR3T30 clock power ≈ 3.98 mW/MHz.
Lattice Semiconductor
145
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Estimating Power Dissipation (continued)
As an example of estimating power dissipation, suppose that a fully utilized OR3T80 has an average of
six outputs for each of the 484 PFUs, that 12 clock branches are used so that the clock is driven to the entire PLC
array, that 250 of the 484 PFUs have FFs clocked at 40 MHz, and that the PFU outputs have an average activity
factor of 20%.
Eighty inputs, 40 of them used as 5 V tolerant inputs, 50 outputs driving 30 pF loads, and 30 bireion
I/Os driving 50 pF loads are also generated from the
40 MHz clock with an average activity factor of 20%. All of the output PIOs are registere, and 30 of the input PIOs
are registered.
The worst-case (VDD = 3.6 V) power dissipation is estimated as follows:
PPFU = 484 x 6 (0.068 mW/MHz x 20 MHz x 20%)
= 789.9 mW
PCLK = [0.107 mW/MHz + (0.09 mW/MHz – Branch)
(12 Branches)
+ (0.015 mW/MHz – PFU) (250 PFUs)
+ (0.004 mW/MHz/PIO) (110 PIOs)]
= 230.43 mW
PIN
= 80 x [0.09 mW/MHz x 20 MHz x 20%]
= 28.8 mW
POUT = 50 x [(30 pF + 8.8 pF) x (3.6)2 x 20 MHz x 20%
= 100.57 mW
PBID
= 30 x [(50 pF + 8.8 pF) x (3.6)2 x 20 MHz x 20%]
= 91.45 mW
TOTAL = 1.241 W
146
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Pin Information
Pin Descriptions
This section describes the pins found on the Series 3 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During configuration, the user-programmable I/Os are 3-stated with an internaull-up resistor enabled.
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an interal pull-up resistor enabled
after configuration.
Table 67. Pin Descriptions
Symbol
I/O
Descripn
Dedicated Pins
VDD
—
—
—
Positive power supply.
Ground supply.
GND
VDD5
5 V tolerant select. VDD5 pin locatioare shown for pacage compatility with
OR2TxxA devices. Connections 5 power sources arnused for 5 V tolerant
I/Os in the OR3Txxx dvices.
RESET
CCLK
I
I
During configuration, ST forces the restart configution and a pull-up is
enabled. After configuratn, RSET can be used s a genral FPGA input or as a
direct input, wses aPLC latches/FFto be snchronously set/reset.
In the master hronous periphmo, CCLK is an output which
strobes configuraata in. In the lave r synchronous peripheral mode, CCLK
is inpt synchronous with the daton IN or [7:0]. In microprocessor mode, CCLK
is seinternally and output fdaisy-chn operation.
DONE
I
As an inp, a low level on DONE elays FPGA start-up after configuration (see
Note).
I
As aactive-high, orain utput, a high level on this signal indicates that config-
uraion is complete. DOE has an optional pull-up resistor.
PRGM
PRGM is an ainputhat forces the restart of configuration and resets the
boundary-sc. This pin always has an active pull-up.
R_CFG
I
This pimust high during device initialization until the INIT pin goes high.
This pin always has an active pull-up.
Duriconfigration, RD_CFG is an active-low input that activates the TS_ALL func-
tion and -tates all of the I/O.
After onfiguration, RD_CFG can be selected (via a bit stream option) to activate the
TS_LL function as described above, or, if readback is enabled via a bit stream
option, a high-to-low transition on RD_CFG will initiate readback of the configuration
data, including PFU output states, starting with frame address 0.
RD_DATA/
O
I
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides con-
figuration data out. If used in boundary scan, TDO is test data out.
Special-Purpose Pins
M0, M1, M2
During powerup and initialization, M0—M2 are used to select the configuration
mode with their values latched on the rising edge of INIT; see Table 34 for the config-
uration modes. During configuration, a pull-up is enabled.
I/O After configuration, these pins are user-programmable I/O (see Note).
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
Lattice Semiconductor
147
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Pin Information (continued)
Table 67. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
M3
I
During powerup and initialization, M3 is used to select the speed of the intrnl oscator dur-
ing configuration with their values latched on the rising edge of INIT. When M3 is lowthe oscil-
lator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 Hz. uring configuration,
a pull-up is enabled.
I/O After configuration, this pin is a user-programmable I/O pin see Note).
TDI, TCK,
TMS
I
If boundary scan is used, these pins are test data in, test cck, and st mode selecs. If
boundary scan is not selected, all boundary-scan funcns ae inhiited once cos
complete. Even if boundary scan is not used, eitheTCK r TMS must be held at lo-
ing configuration. Each pin has a pull-up enabled dung coguration.
I/O After configuration, these pins are user-programbl/O (see Note).
RDY/RCLK/
MPI_ALE
O
During configuration in peripheral modeRDYRCLK indicates another yte cbwritten to
the FPGA. If a read operation is done wethe device is selected, the sae status is also
available on D7 in asynchronous periphermoe.
O
I
During the master parallel conmode, RCLK is a read utput nal to an external
memory. This output is not nor
In i960 microprocessor mode, this cts as the adess ltch enable (ALE) input.
I/O After configuration, if e MPI is not used, this piis a ur-prorammable I/O pin (see Note).
HDC
LDC
O
High During Configuratiois output high until onuration is complete. It is used as a control
output, indicatig hat confiration is not omplete.
I/O After configuation, this pin is a user-programable I/O pin (see Note).
O
Low Durg Coguratiois output low unconfition is complete. It is used as a control out-
put, idicatng that configuration iot coplete.
I/O After figuraon, this pin is grammable I/O pin (see Note).
INIT
I/O INIT is a rectional signal beuring configuration. During configuration, a pull-up is
enabled, but an exterl pull-up resistor is recommended. As an active-low open-drain out-
t, IIT is held low dring power stabilization and internal clearing of memory. As an active-
low input, INIT holds thFPGA n the wait-state before the start of configuration.
I/O After configution, this pin is a user-programmable I/O pin (see Note).
No: The GA Stes of Operatiosection containmore information on how to control these signals during start-up. The timing of DONE
ease controlled by one set bit stream ptions, and the timing of the simultaneous release of all other configuration pins (and the
activatiof all user I/Os) controd by a second set of options.
148
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Pin Information (continued)
Table 67. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
CS0, CS1
I
CS0 and CS1 are used in the asynchronous peripheral, slave pareand icroprocessor
configuration modes. The FPGA is selected when CS0 is low and CS1 is hh. During config-
uration, a pull-up is enabled.
I/O After configuration, these pins are user-programmable I/O ps (seNote).
RD/
MPI_STRB
I
RD is used in the asynchronous peripheral configuation mode. low on RD changes D7 into
a status output. As a status indication, a high indites reay, and a low inds busy. WR
and RD should not be used simultaneously. If ey a, the write strobe o
I
This pin is also used as the microprocessointerce (MPI) data tranfer str
PowerPC, it is the transfer start (TS). For i96, it is te address/daa strobe (A).
I/O After configuration, if the MPI is not usedhis in is a user-programable I/O pin (see Note).
WR
I
WR is used in the asynchronouperipheral configuration modeWhehFPGA is selected,
a low on the write strobe, WR, adthe data on D[7:0] iputs into an internal data buffer. WR
and RD should not be used simulneosly. If they are, the write stbe overrides.
I/O After configuration, thiuser-programmable I/O pin (sNote).
A[17:0]
O
During master parallel cion mode, A[17athe configuration EPROM. In
microprocessor interface (mode, many the n] pins have alternate uses as described
below. See thSpecial Function Blocks section or me MPI information. During configura-
tion, if not n mter parallel or an MPI nfiguratiomode, these pins are 3-stated with a pull-
up enabled.
I/O Afteconfiguration, the pins are us-programmable I/O pins (see Note).
Note: The FPGA States of Opation secn contains more ition how to control these signals during start-up. The timing of DONE
release is controd by onet of t stream options, and e timing the simultaneous release of all other configuration pins (and the
activation of auser I/s) is controlled by a secoof opns.
Lattice Semiconductor
149
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Pin Information (continued)
Table 67. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
A11/MPI_IRQ
A10/MPI_BI
A9/MPI_ACK
O
I/O
MPI active-low interrupt request output.
After configuration, if the MPI is not used, this pin is a user-programable I/O pin see Note).
PowerPC mode MPI burst inhibit output.
O
I/O
After configuration, if the MPI is not used, this pin is a user-prrammble O pin (see Note).
O
In PowerPC mode MPI operation, this is the active-high trasfer acknowledge (TA) output. For
i960 MPI operation, it is the active-low ready/record (RDYRV) outp.
I/O After configuration, if the MPI is not used, this pin ia ur-proammable I/O pin .
A8/MPI_RW
A7/MPI_CLK
A[4:0]
I
In PowerPC mode MPI operation, this is the active-lw writactive-high reacontrol ls.
For i960 operation, it is the active-high write/ave-loread control signa
After configuration, if the MPI is not used, this pin is a er-programmble I/pin (ee Note).
I/O
I
This is the clock used for the synchronus PI interface. For PowerPC, it s the CLKOUT
signal. For i960, it is the system clock thachoen for the i960 eternal bs interface.
After configuration, if the MPI is d, thipin is a user-prorammblI/O pin (see Note).
I/O
I
For PowerPC operation, these awerPC addrests. e address bit mapping (in
PowerPC/FPGA notation) is A[31]A[30]/A[1], A9]/A], A[28]/A[3], A[27]/A[4]. Note
that A[27]/A[4] is the SB of the address. The A[42] inuts anot used in i960 MPI mode.
After configuration, if thMPI is not used, this iis a userrogrammable I/O pin (see Note).
I/O
I
A[1:0]/
MPI_BE[1:0]
For i960 operao, MPI_BE[0] provide the i960 byte nable signals, BE[1:0], that are used as
address bits [1:0] in i960 byte-wide operatin.
After configution, if e MPI is not uis is a user-programmable I/O pin (see Note).
I/O
I
D[7:0]
Durig mater parallel, peripherand slae parallel configuration modes, D[7:0] receive con-
figuriodata, and each pin up enabled. During serial configuration modes, D0 is
the DIN npuD[7:0] are also ns for PowerPC microprocessor mode and the
address/dta pins for i960 micrsor mode.
fter cnfiguration, thpins are user-programmable I/O pins (see Note).
I/O
DIN
Dung slave serial or aster rial configuration modes, DIN accepts serial configuration
ata synchronus with CK. During parallel configuration modes, DIN is the D0 input. Dur-
ing configuraon, p-up is enabled.
After conguration, thpin is a user-programmable I/O pin (see Note).
I/O
O
DOUT
Duriconfigration, DOUT is the serial data output that can drive the DIN of daisy-chained
sdevices. Data out on DOUT changes on the falling edge of CCLK.
I/O
Afuration, DOUT is a user-programmable I/O pin (see Note).
Note: The FPGA States of Opersection contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
150
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Pin Information (continued)
Package Compatibility
Table 68 provides the number of user I/Os available for the ORCA Series 3 FPGAs for each available package.
Each package has six dedicated configuration pins.
Tables 70—75 provide the package pin and pin function for the ORCA Series 3 FPGAanpaages. The bond
pad name is identified in the PIC nomenclature used in the ispLEVER design editr.
When the number of FPGA bond pads exceeds the number of package pins, nd pds are unused. When the
number of package pins exceeds the number of bond pads, package pins are lenconected (no connects).
When a package pin is to be left as a no connect for a specific die, it is idicated aa ote in the device pad col-
umn for the FPGA. The tables provide no information on unused pads.
Table 68. ORCA I/Os Summary
144-Pin
TQFP
208-Pin
SQFP/SQPF2 SQFP/SQ2
240-Pin
56-Pin
BGA
352-Pin
PBGA
432-Pi
EBGA
Device
OR3T20
User I/Os*
VDD/VSS
Configuration
Unused
114
24
6
171
31
6
—
—
—
192
26
6
—
—
—
—
—
—
—
0
0
32
OR3T30
User I/Os*
VDD/VSS
Configuration
Unused
—
—
—
—
171
31
6
192
40
6
221
6
6
—
—
—
—
—
—
—
—
0
2
3
OR3T55
User I/Os*
VDD/VSS
Configuration
Unused
—
—
171
31
6
192
42
6
223
26
6
288
48
6
—
—
—
—
0
0
1
10
OR3C/T80
User I/Os*
VDD/VS
Congurati
Uused
—
—
—
—
171
31
6
192
42
6
—
—
—
—
298
48
6
342
84
6
0
0
0
0
R325
UsI/Os*
VDD/V
Cfiguration
Uused
—
—
171
31
6
192
42
6
—
—
—
—
298
48
6
342
84
6
0
0
0
0
*User I/O count ExpressCLK inputs.
Lattice Semiconductor
151
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Pin Information (continued)
Compatibility with OR2C/TxxA Series
The pinouts shown for the OR3Cxx and OR3Txxx devices are consistent with the OR2C/TxxA Series for all devices
offered in the same packages.This includes the following pins:VDD, VSS, VDD5 (OR2TxxA Series y), and all con-
figuration pins.
The following restrictions apply:
1. There are two configuration modes supported in the OR2C/TxxA Series that are nouppted in Series 3: mas-
ter parallel down and synchronous peripheral modes. The Series 3 FPGAs have two nmicrprocessor inter-
face (MPI) configuration modes that are unavailable in the OR2C/TxxA Series
2. There are four pins—one per each device side—that are user I/O in the ORC/TxxA eries which can ly be
used as fast dedicated clocks or global inputs in Series 3. These pins aralsused tdrive the Expto
the I/O FFs on their given side of the device. These four middle ExpresCLpins ould not be uset
to a programmable clock manager (PCM). A corner ExpressCLK input houlbe used instead see ite
below). See Table 69 for a list of these pins in each package.
3. There are two other pins that are user I/O in both the OR2CxxA and ies 3 but also have tional added
functionality. Each of these pins drives the ExpressCLKs n two sides of the device. They lso he ast connec-
tivity to the programmable clock manager (PCM). See Tab6for a list of these pis in eacpackage.
Table 69. Series 3 ExpressCLK Pins
Pin Name/
Package
144-Pin
TQFP
208-Pin
SQFP/SQFP2 SQFP/SQ
240-
256-Pin
PBGA
3Pin
PBA
432-Pin
EBGA
I-ECKL
I-ECKB
15
55
22
80
26
91
K3
W1
K18
1
W
N2
AE14
N23
B14
AB4
A25
R29
AH16
T2
I-ECKR
92
1
178
49
152
207
56
I-ECKT
124
33
C15
AG29
D5
I/O-SECKLL
I/O-SECKUR
111
184
A19
152
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table 70. OR3T20 144-Pin TQFP Pinout
OR3T20
Pin
Pad
Function
1
VDD
VSS
PL1A
VDD
VSS
2
3
I/O-A0/MPI_BE0
4
PL2D
PL2A
PL3D
PL3A
PL4D
PL4C
PL4A
PL5D
PL5C
PL5A
VSS
I/O
5
I/O-A1/MPI_BE1
6
I/O-A2
7
I/O-A3
8
I/O
9
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
7
28
9
3
31
32
33
34
35
36
37
38
39
40
41
42
I/O-A4
I/O-A5
I/O
I/O-A6
VSS
PECKL
PL6C
PL6A
VDD
I-ECKL
I/O
I/O-A7/MPI_CL
VDD
PL7D
PL7C
PL7A
VSS
I/O
I/O
I/O-A8/MPI_RW
VSS
PL8D
PLA
PL9D
PL9C
PL9A
PL0D
PL10C
PL10A
PL11A
PL
PL
VSS
I/OA9/MPI_ACK
I/O-A10/MPI_
I/O
I/O
I/O-11/MPI_IRQ
I/O-A2
I/O
/O-A3
I/O-14
I/O
I/O-SECKLL
I/O-A15
VSS
PCCLK
VDD
CCLK
VDD
VSS
VSS
PB1A
PB1D
PB2A
PB3A
I/O-A16
I/O
I/O-A17
I/O
Lattice Semiconductor
153
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pin
Pad
Function
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
4
75
76
77
78
79
80
81
82
83
84
85
PB3B
I/O
I/O
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
PB3D
VDD
PB4A
PB4D
PB5A
PB5C
PB5D
PB6A
PB6C
PB6D
VSS
PECKB
PB7C
PB7D
PB8A
I-ECKB
I/O
I/O
I/O
PB8D
PB9A
I/O
I/O-HDC
I/O
PB9C
PB9D
VDD
I/O
VDD
I/O-DC
I/O
PB10A
PB10C
PB10D
PB11A
PB11D
PB1A
SS
I/O
O-INIT
I/O
I/O
VSS
DONE
VDD
VSS
RSET
RG
M0
PDNE
DD
V
PRESETN
PPRGMN
PR12A
PR12D
PR11A
PR10A
PR10C
PR10D
PR9A
PR9B
PR9D
PR8A
I/O
I/O-M1
I/O
I/O
I/O-M2
I/O
I/O
I/O-M3
154
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
Pin
Function
86
87
PR8D
I/O
VSS
VSS
I/O
88
PR7A
PR7C
PR7D
VDD
89
I/O
90
I/O
91
VDD
92
PECKR
PR6C
PR6D
VSS
I-ECKR
93
I/O
94
I/O
95
VSS
96
PR5A
PR5C
PR5D
PR4A
PR4D
PR3A
PR3D
PR2A
PR2C
PR2D
PR1A
VSS
I/O
97
I/O
98
I/O
99
I/O-CS1
100
101
102
103
104
105
106
107
108
109
110
111
112
I/O
I/O-CS0
I/O
I/O-RD/MPI_S
I/O
I/O
I/O-WR
VSS
PRD_CFG
VDD
RD_FG
VD
VS
VSS
PT12
PT12A
I/O-SECKU
I/O-RDY/RCL
MPIALE
113
14
5
116
117
118
119
120
121
122
123
124
125
126
127
128
P1D
PT11A
PT10D
PT10C
PT10A
I/O
O-D7
I/
I/O
I/O-D6
VDD
I/O
P
PT9A
PT8D
PT8B
PT8A
PECKT
PT7C
PT7A
VSS
I/O-D5
I/O
I/O
I/O-D4
I-ECKT
I/O
I/O-D3
VSS
I/O
PT6D
Lattice Semiconductor
155
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pin
Pad
Function
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
PT6C
I/O
PT6A
PT5D
PT5C
PT5A
PT4D
PT4A
VDD
I/O-D2
I/O-D1
I/O
I/O-D0/DIN
I/O
I/O-DOUT
VDD
PT3D
PT3C
PT3A
PT2A
PT1D
PT1A
VSS
I/O
I/O
I/O-TDI
I/O-TMS
I/O
I/O-TCK
VSS
PRD_DATA
RD_DATA/TDO
156
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table 71. OR3T20, OR3T30, OR3T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
VSS
3
PL1D
PL1A
PL2D
PL2C
PL2A
PL3D
PL3C
PL3B
PL3A
VDD
PL1D
PL2D
PL3D
PL3C
PL3A
PL4D
PL4C
PL4B
PL4A
VDD
PL1D
PL2D
PL3D
PL3A
PL4A
PL5A
PL6D
PL6B
PL6A
VDD
PL1D
PL2D
PL4D
PL4A
PL5A
PL6
PL7
P7B
PL7
VDD
PL1
PLD
PL4D
PL5D
PL7
P8A
I/O
4
/O-A0/MPI_BE0
5
I/O
6
I/O
7
I/O-A1/MPI_BE1
8
I/O-A2
9
PL9D
PL9B
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3
31
32
33
34
35
36
37
38
39
40
41
42
O
PL9A
O-A3
VD
VDD
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
VSS
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
L6B
PL6
VSS
PLD
7C
PL7
7A
D
L8C
PL8B
PL8A
VSS
L8D
PL8A
PL9D
PL9B
P
L10
PL0B
PL10A
VSS
PL10
PL0A
PL1
1A
PL12D
PL12A
PL13D
PL13A
VSS
I/O
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O-A6
VSS
PECKL
P6C
PL6
PA
VDD
PCKL
PL7C
PL7B
PL7A
VDD
PECKL
PC
PL9B
9A
DD
PECKL
PL11C
PL11B
PL11A
VDD
PECKL
PL14C
PL14B
PL14A
VDD
I-ECKL
I/O
I/O
I/O-A7/MPI_CLK
VDD
P7D
PL7C
PL7B
PL7A
VSS
L8D
L8C
PL8
8A
VSS
PL10D
PL10C
PL10B
PL10A
VSS
PL12D
PL12C
PL12B
PL12A
VSS
PL15D
PL15C
PL15B
PL15A
VSS
I/O
I/O
I/O
I/O-A8/MPI_RW
VSS
8D
PA
PL9D
PL9C
PL9B
PL9A
VDD
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
VDD
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
VDD
PL13D
PL13B
PL13A
PL14C
PL14B
PL15C
PL15B
PL15A
VDD
PL16D
PL16A
PL17D
PL17A
PL18D
PL18A
PL19D
PL19A
VDD
I/O-A9/MPI_ACK
I/O
I/O
I/O-A10/MPI_BI
I/O
I/O
I/O
I/O-A11/MPI_IRQ
VDD
PL10D
PL10C
PL11D
PL11C
PL13D
PL13B
PL16D
PL16B
PL20D
PL20B
I/O-A12
I/O
Lattice Semiconductor
157
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
75
76
77
78
79
80
81
82
83
84
85
PL10B
PL10A
PL11D
PL11A
PL12D
PL12C
PL12B
PL12A
VSS
PL11B
PL11A
PL12D
PL12A
PL13D
PL13A
PL14C
PL14A
VSS
PL14D
PL14B
PL15D
PL16D
PL17D
PL17A
PL18C
PL18A
VSS
PL17D
PL17B
PL18D
PL19D
PL20D
PL21D
PL21A
PL22A
VSS
PL21D
PL21B
PL22D
PL24A
PL26D
PL27
PL2A
L28A
VSS
I/O
I/O-A13
I/O
I/O-A14
IO
/O
I/O-SECKLL
I/O-A15
VSS
C
VS
I/O-A16
/O
PCCLK
VSS
PCCLK
VSS
PCCLK
VSS
PCCLK
VSS
PCCL
VSS
VSS
VSS
VSS
VSS
VSS
PB1A
PB1B
PB1C
PB1D
PB2A
PB2D
PB3A
PB3B
PB3C
PB3D
VDD
PB1A
PB1D
PB2A
PB2D
PB3A
PB3D
PB4A
PB4B
PB4C
B4D
VDD
PB1A
PB1D
PB2A
PB2D
PB
PB5B
PB5D
PB6B
PB6D
VDD
P1A
PB2A
PB2D
P3D
PB4D
PB5D
PB6B
P6D
PB7
PB7D
DD
PB1A
PB2A
PB2D
PB3
P4D
PB6D
PB7D
PB8D
PB9D
VDD
I/O
I/O
I/O-A17
I/O
I/O
I/O
I/O
I/O
VDD
I/O
PB4A
PB4B
PB4C
B4D
PBA
PB5B
PBC
PB5D
VSS
P5A
PB5B
B5C
PB5D
PB6A
PB6B
B6C
D
VS
PB7A
P
P
PB8A
B8B
PB8C
PB8D
VSS
PB8A
PB8D
PB9A
PB9C
PB9D
PB10A
PB10B
PB10D
VSS
PB10A
PB10D
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
PB6A
PB
PB6C
PB6D
VSS
B7A
PB7B
PB7C
PB7D
VSS
PB9A
PB9B
PB9C
PB9D
VSS
PB11A
PB11B
PB11C
PB11D
VSS
PB14A
PB14B
PB14C
PB14D
VSS
I/O
I/O
I/O
VSS
I-ECKB
I/O
PECKB
PB7B
PB7C
PB7D
VSS
PECKB
PB8B
PB8C
PB8D
VSS
PECKB
PB10B
PB10C
PB10D
VSS
PECKB
PB12B
PB12C
PB12D
VSS
PECKB
PB15B
PB15C
PB15D
VSS
I/O
I/O
VSS
I/O
PB8A
PB9A
PB11A
PB13A
PB16A
158
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
OR3C/T80
OR3T125
Pad
Pin
Pad
Function
86
87
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
VDD
PB13B
PB13C
PB14A
PB14B
PB14D
PB15A
PB15D
VD
PB16D
PB17A
PB1D
PB8A
PB18D
P19A
PB19D
DD
I/O
I/O
88
PB9D
I/O
89
PB10A
PB10B
PB10C
PB10D
VDD
I/O-HDC
I/O
90
PB9B
91
PB9C
PB9D
VDD
I/O
92
I/O
93
VDD
O-LDC
O
94
PB10A
PB10B
PB10C
PB10D
PB11A
PB11C
PB11D
PB12A
PB12D
VSS
PB11A
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13D
PB14D
VS
PB13A
PB13D
PB14A
PB14D
PB5A
16A
PB1A
18A
8D
VSS
PB1A
P16D
PB1
B17D
B18A
PB19A
PB20A
PB21D
P
VSS
PB20A
PB21D
PB22
PB3D
PB24
P25A
PB2A
27D
PB28D
VSS
95
96
I/O
97
I/O
98
I/O-INIT
I/O
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
14
15
116
117
118
119
120
121
122
123
124
125
126
127
I/O
I/O
I/O
VSS
DONE
VSS
RESET
PRGM
I/O-M0
I/O
PDONE
VSS
ONE
V
PDONE
VSS
PDNE
VSS
PDONE
VSS
PRESETN
PPRGMN
PR12A
R12
P1A
PR1
PR10A
PR10B
PR10C
PR10D
VD
PRESETN
PRGMN
R14A
PR13A
PR13D
PR12A
R11A
R11B
PR1
P11D
VDD
PRESN
PPRGMN
P8A
PR18
17B
R16A
PR15D
PR14A
PR14D
PR13A
VDD
ESETN
PPRGMN
PR22A
PR21A
PR20A
PR19A
PR18D
PR17A
PR17D
PR16A
VDD
PRESETN
PPRGMN
PR28A
PR27A
PR26A
PR25A
PR22D
PR21A
PR21D
PR20A
VDD
I/O
I/O
I/O-M1
I/O
I/O
I/O
VDD
I/O-M2
I/O
R9A
P9D
PR8A
PR8B
PR8C
PR8D
VSS
PR10A
PR10B
PR10C
PR10D
PR9A
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
VSS
PR15A
PR15D
PR14A
PR14C
PR14D
PR13A
PR13B
PR13D
VSS
PR19A
PR19D
PR18A
PR18D
PR17A
PR17D
PR16A
PR16D
VSS
I/O
I/O
I/O-M3
I/O
PR9B
PR9C
I/O
PR9D
I/O
VSS
VSS
I/O
PR7A
PR7B
PR8A
PR10A
PR10B
PR12A
PR12B
PR15A
PR15B
PR8B
I/O
Lattice Semiconductor
159
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
9
160
161
162
163
164
165
166
167
168
169
170
PR7C
PR7D
VDD
PR8C
PR8D
VDD
PR10C
PR10D
VDD
PR12C
PR12D
VDD
PR15C
PR15D
VDD
I/O
I/O
VDD
PECKR
PR6B
PR6C
PR6D
VSS
PECKR
PR7B
PR7C
PR7D
VSS
PECKR
PR9B
PR9C
PR9D
VSS
PECKR
PR11B
PR11C
PR11D
VSS
PECKR
PR14B
PR14
PRD
VSS
I-ECKR
IO
/O
I/O
VSS
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
VDD
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
VDD
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR10A
PR10C
PR10
PR9B
P9C
PR9D
PR8A
P8D
VDD
PR13A
PR13
PR12A
PR12D
PR11A
PR11D
PR10A
PR1D
DD
I/O
I/O
I/O-CS1
/O
I/O
I/O
VDD
PR3A
PR3B
PR3C
PR3D
PR2A
PR2C
PR2D
PR1A
PR1C
R1D
V
PR4A
PR4B
PR4C
PR4D
R3A
PR3C
P3D
PR2A
R2D
PR1A
VSS
PR
PR6B
PR5B
PR5D
PR4A
PR4D
PR3A
P
P
VSS
PR7A
PR7B
P6B
PR6
PR5A
R5D
PR4A
PR3A
PR2A
PR1A
VSS
PR9B
PR8B
PR8D
PR7A
PR5A
PR4A
PR3A
PR2A
PR1A
VSS
I/O-CS0
I/O
I/O
I/O
I/O-RD/MPI_STRB
I/O
I/O
I/O-WR
I/O
I/O
VSS
PD_CFN
VS
PRD_CFGN
VSS
PR_CFGN
VSS
PRD_CFGN
VSS
PRD_CFGN
VSS
RD_CFG
VSS
VSS
VSS
VSS
VSS
VSS
PT12D
PT12A
PT1
PT11C
PT11A
PT10D
PT10C
PT10B
PT10A
VDD
PT14D
P13D
PT13A
PT12D
PT12C
PT12A
PT11D
PT11C
PT11B
VDD
PT18D
PT17D
PT16D
PT16A
PT15D
PT14D
PT14A
PT13D
PT13B
VDD
PT22D
PT21A
PT19D
PT19A
PT18D
PT17D
PT17A
PT16D
PT16B
VDD
PT28D
PT27A
PT25D
PT25A
PT24D
PT23D
PT22D
PT21D
PT20D
VDD
I/O-SECKUR
I/O-RDY/RCLK/MPI_ALE
I/O
I/O
I/O-D7
I/O
I/O
I/O
I/O-D6
VDD
I/O
PT9D
PT9C
PT10D
PT10C
PT12D
PT12C
PT15D
PT15B
PT19D
PT19A
I/O
160
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
OR3C/T80
OR3T125
Pad
Pin
Pad
Function
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
98
19
0
20
202
203
204
205
206
207
208
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
VSS
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
VSS
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
VSS
PT15A
PT14C
PT14B
PT13D
PT13C
PT13A
VSS
PT18D
PT18A
PT17D
PT1A
PT1
PT16A
VSS
I/O
I/O-D5
I/O
I/O
I/O
I/O-D4
VSS
PECKT
PT7C
PT7B
PT7A
VSS
PECKT
PT8C
PT8B
PT8A
VSS
PECKT
PT10C
PT10B
PT10A
VSS
PECK
PT1C
T12
PT2A
VSS
ECKT
PT15C
PT15B
PT15A
VS
I-ECKT
I/O
/O
-D3
VSS
PT6D
PT6C
PT6B
PT6A
VSS
PT7D
PT7C
PT7B
PT7A
VSS
PT9D
P9C
P9
PT9
S
T11D
PT11C
PT11B
PT11A
VSS
PTD
T14C
PTB
PT1A
VSS
I/O
I/O
I/O
I/O-D2
VSS
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
T4B
PTA
VD
PT6D
PT6C
P6B
PT6
PT5D
T5C
PT5B
PT5A
VDD
8D
PT8C
PT8B
PT8A
PT7D
7C
PTB
T7A
DD
PTD
T10B
PT1A
PT9C
PT9B
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
PT10D
PT10A
VDD
I/O-D1
I/O
I/O
I/O-D0/DIN
I/O
PT8D
PT8C
PT8A
I/O
I/O
I/O-DOUT
VDD
VDD
PT3D
T3C
PT3B
PT3A
PT2D
PT2A
D
PT1A
VSS
PD
PT4C
4B
PT4A
T3D
PT3A
PT2D
PT2A
PT1D
PT1A
VSS
PT6D
PT6A
PT5C
PT5A
PT4A
PT3A
PT2C
PT2A
PT1D
PT1A
VSS
PT7D
PT7A
PT9D
I/O
PT8A
I/O
PT6C
PT6A
PT7A
I/O
PT6A
I/O-TDI
I/O
PT5A
PT5A
PT4A
PT4A
I/O-TMS
I/O
PT3A
PT3A
PT2A
PT2A
I/O
PT1D
PT1A
PT1D
I/O
PT1A
I/O-TCK
VSS
VSS
VSS
PRD_DATA
PRD_DATA
PRD_DATA
PRD_DATA
PRD_DATA
RD_DATA/TDO
Lattice Semiconductor
161
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table 72. OR3T30, OR3T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout
OR3T30
Pad
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
1
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
I/O
2
3
PL1D
PL1B
PL1A
PL2D
VSS
PL1D
PL1C
PL1B
PL2D
VSS
PL1D
PL1C
PL1B
PL2D
VSS
PL1D
PL1C
PL1B
PL2D
VSS
4
I/O
5
IO
6
I/O-A0/_BE0
7
VSS
8
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
VDD
PL3D
PL3A
PL4D
PL4A
PL5A
PL6D
PL6B
PL6A
VDD
PL4D
PL4A
PL5D
PL5A
PL6A
PL7D
PL7B
PL
PL4D
PL5D
PL6
PL7D
PL8
PL9D
PL9B
L9A
VDD
I/
9
IO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
I/O
IO-A1/MPI_BE
I/O-A2
I/O
I/O
I/O3
VDD
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
VSS
PL7D
PL7C
PL7B
PL7A
PL8D
L8C
PL8B
PL8A
VSS
PL8
PL8A
PL9D
PL9B
PL9A
PL10C
PL10B
PL10D
PL1A
P1D
PL11
PL12D
2A
PL13D
PL13A
VSS
I
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O-A6
VSS
PCKL
PL7
PL7B
P7A
VDD
PECKL
PL9C
PL9B
PL9A
VDD
PEC
P11C
L11B
PL11A
VDD
PECKL
PL14C
PL14B
PL14A
VDD
I-ECKL
I/O
I/O
I/O-A7/MPI_CLK
VDD
PL8D
PL8C
PL8
PL8A
VSS
PL10
P0C
PL10B
PL10A
VSS
PL12D
PL12C
PL12B
PL12A
VSS
PL15D
PL15C
PL15B
PL15A
VSS
I/O
I/O
I/O
I/O-A8/MPI_RW
VSS
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL13D
PL13B
PL13A
PL14C
PL14B
PL15C
PL16D
PL16A
PL17D
PL17A
PL18D
PL18A
I/O-A9/MPI_ACK
I/O
I/O
I/O-A10/MPI_BI
I/O
I/O
162
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T30
Pad
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pin
Pad
Function
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
9
70
1
7
73
74
75
76
77
78
79
80
81
82
83
84
PL10B
PL10A
VDD
PL12B
PL12A
VDD
PL15B
PL15A
VDD
PL19D
PL19A
VDD
I/O
I/O-A11/MPI_IRQ
VDD
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
VSS
PL13D
PL13B
PL14D
PL14B
PL14A
PL15D
PL15B
PL16D
VSS
PL16D
PL16B
PL17D
PL17B
PL17A
PL18D
PL18B
PL19D
VSS
PL20D
PL20B
PL21D
PL21B
PL21A
PL2D
PL2
P24A
VSS
I/OA12
/O
I/O
/O-A13
IO
I/O
I/O
I/O-A14
VS
PL13D
PL13A
PL14C
PL14A
VSS
PL17D
PL17A
PL18C
PL18A
VSS
PL20D
PL1D
P21
PL2A
SS
L26D
L27D
PL27A
PL28A
VSS
/O
I/
I/OECKLL
I/OA15
VSS
PCCLK
VDD
PCCLK
VDD
LK
VDD
PC
VDD
CCLK
VDD
VSS
SS
VSS
VS
VSS
VSS
VS
VSS
VSS
VSS
PB1A
PB1D
P2A
PB2
S
PB1A
B1D
PB2A
PB2D
VSS
PB1
PB2A
P2D
PB3
SS
PB1A
PB2A
PB2D
PB3D
VSS
I/O-A16
I/O
I/O
I/O
VSS
PB3
P3B
PB3C
PB3D
PB4A
PB4
4C
PB3D
B4D
B5A
PB5B
B5D
PB6A
PB6B
PB6D
VDD
B4D
PB5D
PB6A
PB6B
PB6D
PB7A
PB7B
PB7D
VDD
PB4D
PB5D
PB6A
PB6D
PB7D
PB8A
PB8D
PB9D
VDD
I/O-A17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
P5A
PB5B
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB8A
PB8D
PB9A
PB9C
PB9D
PB10A
PB10B
PB10D
PB10A
PB10D
PB11A
PB11D
PB12A
PB12D
PB13A
PB13D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Lattice Semiconductor
163
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T30
Pad
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
85
86
VSS
PB7A
PB7B
PB7C
PB7D
VSS
VSS
PB9A
VSS
PB11A
PB11B
PB11C
PB11D
VSS
VSS
PB14A
PB14B
PB14C
PB14D
VSS
VSS
I/O
87
PB9B
I/O
88
PB9C
I/O
89
PB9D
I/O
90
VSS
VS
I-CKB
I/O
91
PECKB
PB8B
PB8C
PB8D
VSS
PECKB
PB10B
PB10C
PB10D
VSS
PECKB
PB12B
PB12C
PB12D
VSS
PECKB
PB15B
PB15C
PB15D
VSS
92
93
I/O
94
I/
95
VSS
I/O
96
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
VDD
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
VDD
PB13A
PB13B
PB13C
PB14A
PB14B
P
PB
PB15
VDD
PB16A
P16D
PB17A
PB17D
PB8A
PB18D
PB19A
PB19D
VD
97
I/O
98
I/O
99
I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
11
117
118
119
120
121
122
123
124
125
126
127
I/OHDC
I/O
O
I/O
VDD
I/O-LDC
I/O
PB11A
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB3B
—
PB13A
PB13D
B14A
P14D
PB15A
P15D
PB16A
PB16D
VSS
PB16A
PB16D
PB17A
PB17D
P
P
PB19D
SS
PB2A
PB21D
B22A
PB3D
PB24A
PB24D
PB25A
PB25D
VSS
I/O
I/O
I/O-INIT
I/O
I/O
I/O
VSS
I/O
PB13D
B14A
PB14B
PB14D
VS
P17A
B1D
PB18A
B18D
VSS
PB20A
PB21A
PB21D
PB22D
VSS
PB26A
PB27A
PB27D
PB28D
VSS
I/O
I/O
I/O
VSS
DONE
VDD
VSS
RESET
PRGM
I/O-M0
I/O
PDONE
VDD
PDONE
VDD
PDONE
VDD
PDONE
VDD
VSS
VSS
VSS
VSS
PRESETN
PPRGMN
PR14A
PR14D
PR13A
PR13D
PRESETN
PPRGMN
PR18A
PR18C
PR18D
PR17B
PRESETN
PPRGMN
PR22A
PR22D
PR21A
PR20A
PRESETN
PPRGMN
PR28A
PR28D
PR27A
PR26A
I/O
I/O
164
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T30
Pad
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pin
Pad
Function
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
7
1
159
160
161
162
163
164
165
166
167
168
169
170
VSS
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
VDD
VSS
PR16A
PR16D
PR15A
PR15C
PR15D
PR14A
PR14D
PR13A
VDD
VSS
VSS
VSS
I/O
PR19A
PR19D
PR18A
PR18C
PR18D
PR17A
PR17D
PR16A
VDD
PR25A
PR24A
PR23A
PR23D
PR22D
PR21A
PR21D
PR2A
VD
I/O
O
O
I/O-M1
I/O
IO
I/O
VDD
I/O-M2
I/O
PR10A
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
VSS
PR12A
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
VSS
PR15A
PR15D
PR14A
PR4C
P14
PR1A
13B
3D
VSS
P19A
PR19
R18A
R18D
PR17A
PR17D
PR16A
PR
VSS
/O
I/
O-M3
O
I/O
I/O
VSS
I/O
PR8A
PR8B
PR8C
PR8D
DD
10A
PR1B
PR10C
R10D
VDD
PR12A
PR12B
PR12
PR12D
D
PR5A
PR15B
R15C
PR15D
VDD
I/O
I/O
I/O
VDD
I-ECKR
I/O
ECR
P7B
PR7
P7D
VSS
PECKR
PR9B
PR9C
R9D
VSS
ECK
11B
R11C
PR11D
VSS
PECKR
PR14B
PR14C
PR14D
VSS
I/O
I/O
VSS
I/O
PR6A
PR6B
PR6
6D
P5C
PR5D
VDD
PR8
R8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
VDD
PR10A
PR10C
PR10D
PR9B
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
PR10A
PR10D
VDD
I/O
I/O
I/O
PR9C
PR9D
PR8A
I/O-CS1
I/O
I/O
PR8D
VDD
I/O
VDD
I/O-CS0
I/O
PR4A
PR4B
PR4C
PR4D
PR3A
PR6A
PR6B
PR5B
PR5D
PR4A
PR7A
PR9A
PR7B
PR9B
PR6B
PR8B
I/O
PR6D
PR5A
PR8D
I/O
PR7A
I/O-RD/MPI_STRB
Lattice Semiconductor
165
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T30
Pad
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
20
202
203
204
205
206
207
208
209
210
211
212
PR3B
PR3C
PR3D
VSS
PR4B
PR4D
PR3A
VSS
PR5B
PR5D
PR4A
VSS
PR6A
PR5A
PR4A
VSS
I/O
I/O
I/O
VSS
PR2A
PR2D
PR1A
PR1D
VSS
PR2A
PR2C
PR1A
PR1D
VSS
PR3A
PR2A
PR1A
PR1D
VSS
PR3A
PR2A
PR1A
PR1D
VSS
I/O-R
O
I/O
I/O
VS
PRD_CFGN
VSS
PRD_CFGN
VSS
_CFG
VSS
PRD_CFGN
VSS
PRD_CFGN
VSS
VDD
VDD
VDD
DD
VDD
VSS
VSS
VSS
VSS
VSS
PT14D
PT14C
PT14A
PT13D
—
PT18D
PT18B
PT18A
PT17D
VSS
PT22D
PT22A
P
PT
VSS
PT28D
PT8A
PT27D
PT27A
VSS
I/O-SECKU
O
I/O
/K/MPI_ALE
VSS
I/O
PT13B
PT13A
PT12D
PT12C
PT12A
PT11D
PT11C
PT11B
VD
PT16D
PT16C
PT16A
T15D
P14D
PT14A
P13D
PT13B
VDD
PT19D
PT19C
PT19A
PT18D
PT17D
P
P
VDD
PT5D
T2C
PT25A
T24D
P3D
PT22D
PT21D
PT20D
VDD
I/O
I/O
I/O-D7
I/O
I/O
I/O
I/O-D6
VDD
I/O
PT10
PT10C
T10B
PT10A
PT9D
PT9
PT9B
PT9A
VSS
PT12D
P12C
T1B
PT12A
T11D
PT11C
PT11B
PT11A
VSS
P15D
PT15B
PT15A
PT14C
PT14B
PT13D
PT13C
PT13A
VSS
PT19D
PT19A
PT18D
PT18A
PT17D
PT17A
PT16D
PT16A
VSS
I/O
I/O
I/O-D5
I/O
I/O
I/O
I/O-D4
VSS
I-ECKT
I/O
PECKT
PT8C
PT8B
PT8A
VSS
PECKT
PT10C
PT10B
PT10A
VSS
PECKT
PT12C
PT12B
PT12A
VSS
PECKT
PT15C
PT15B
PT15A
VSS
I/O
I/O-D3
VSS
I/O
PT7D
PT9D
PT11D
PT14D
166
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T30
Pad
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pin
Pad
Function
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
PT7C
PT7B
PT7A
VSS
PT9C
PT9B
PT9A
VSS
PT11C
PT11B
PT11A
VSS
PT14C
PT14B
PT14A
VSS
I/O
I/O
I/OD2
SS
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
VDD
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
VDD
PT10D
PT10B
PT10A
PT9C
PT9B
PT8D
PT8C
PT8A
VD
PT13D
PT13A
PT12D
PT1A
PT1D
P11A
PT1
T10A
VDD
I/O-D1
I/O
I/
I/-D0/DIN
I/O
I/O
I/
I/DOUT
V
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
VSS
PT6D
PT6A
PT5C
PT5A
PT4D
T4A
PTD
PT3A
VSS
T7D
PT
T6C
6A
T5D
PT5A
PT4D
PT4
VSS
PT9D
PT8A
I/O
O
PT7A
I/O
P
I/O-TDI
I/O
PT5
P5A
I/O
PT4D
PT4A
I/O
I/O-TMS
VSS
VSS
P2D
PT2
1D
PT1
VSS
PT2C
PT2A
PT1D
PT1A
VSS
P3A
PT2
1D
T1A
VSS
PT3A
I/O
PT2A
I/O
PT1D
PT1A
I/O
I/O-TCK
VSS
VSS
D_DATA
PR_DATA
PRD_DATA
PRD_DATA
RD_DATA/TDO
Lattice Semiconductor
167
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table 73. OR3T20, OR3T30, and OR3T55 256-Pin PBGA Pinout
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
Pin
Function
B1
C2
D2
D3
E4
C1
D1
E3
E2
E1
F3
G4
F2
F1
G3
G2
G1
H3
H2
H1
J4
J3
J2
J1
K2
K3
K1
L1
L2
L3
VDD
PL1D
PL1C
PL1B
PL1A
—
VDD
PL1D
PL1B
PL1A
PL2D
PL2C
PL2B
PL2A
PL3D
PL3C
PL3B
PL3A
—
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6
PLA
PECK
PL7C
PL7B
P7A
PL8D
PL8C
PL8B
PL8A
PL9
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
VDD
PL1D
PL1C
PL1B
PL2D
PL2C
PL2B
PL2A
PL3D
PL3A
PL4D
PL4A
PL5D
PL5A
PL6D
PL6B
PL6A
PL7D
PL7C
PL7B
PA
PL8D
L8C
PLB
PL8A
ECKL
PL9C
PL9B
PL9A
PL10D
L1C
PL10B
L10A
PL11D
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13B
PL14D
VDD
I/O
I/O
I/O
I/O-A0/MPI_BE0
I/O
I/O
I/O
I/O
I/O
I/O
—
—
PL2D
PL2C
PL2B
PL2A
—
I/O-A1/MPI_BE1
I/O
I/O-A2
I/O
I/
I/O-
I/O
I/O
I/O
O-A4
I/O-A5
I/O
I/O
I/O
I-E
I/O
I/O
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PECKL
PL6C
PLB
L6A
PD
PL7
P7B
P7A
PL8D
PL8C
PL8B
PL8A
PL9D
PL9C
PL9B
PL9A
PL10D
PL10C
PL10B
I/O-A7/PI_CLK
I/O
I/O
I/O
L
1
M2
M3
M4
N1
N2
N3
P1
P2
R1
P3
R2
T1
I/O-A8/MPI_RW
I/O-A9/MPI_ACK
I/O
I/O
I/O-A10/MPI_BI
I/O
I/O
I/O
I/O-A11/MPI_IRQ
I/O-A12
I/O
I/O
168
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
Pin
Function
P4
R3
T2
U1
T3
U2
V1
T4
U3
V2
W1
V3
W2
Y1
W3
Y2
W4
V4
U5
Y3
Y4
V5
W5
Y5
V6
U7
W6
Y6
V7
7
7
V8
8
Y
U9
V9
W9
Y9
W10
V10
Y10
Y11
PL10A
PL11D
PL11C
PL11B
PL11A
—
PL12D
PL12C
—
—
PL12B
—
PL12A
PCCLK
—
PB1A
—
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
PL14D
PL14C
PL14B
PL14A
PCCLK
—
PB1A
PB1C
PB1D
PB2A
PB2B
PB2C
PB2D
PBA
PBB
PB3C
PB3D
PBA
B4B
PB4C
PB4D
PB5
PBB
B5C
PBD
B6A
6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PECKB
PB8B
PB8C
PL14B
PL14A
PL15D
PL15B
PL16D
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL18B
PL18A
PCCLK
—
PB1A
PB1C
PB1D
PB2A
B2B
P2C
PB2
PB3D
B4D
PB5A
PB5B
PB5D
PB6A
PB6B
B6D
PBA
B7B
B7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PECKB
PB10B
PB10C
I/O-A13
I/O
I/O
I/O
I/O-A14
I/O
I/O
I/O
I/O
I/O
I/O-SECKLL
I/O
I/O-A15
CCL
N
I/O-A1
PB1B
PB1C
PB1D
—
I/O
I/O
—
I/O
PB2A
PB2B
PB2C
PB2D
PB3A
PB3B
P3C
PB3
PB4A
B4B
PB4C
PB4D
PB5
PB5
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
I/O-A17
I/O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
W11 PECKB
V11
U11
I-ECKB
I/O
I/O
PB7B
PB7C
Lattice Semiconductor
169
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
Pin
Function
Y12
W12
V12
U12
Y13
W13
V13
Y14
W14
Y15
V14
W15
Y16
U14
V15
W16
Y17
V16
W17
Y18
U16
V17
W18
Y19
V18
W19
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PB10A
PB10B
PB10C
PB10D
—
PB8D
PB9A
PB9B
PB9C
PB9D
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14D
PB15A
PB15D
PB16A
PB16D
PB17A
PB17
PB17D
B18A
B18B
PB8C
PB18D
PDONE
PRESETN
PPRGMN
PR18A
P18C
R1
PR17A
R17B
P17C
PR17D
PR16A
PR16D
PR15A
PR15C
PR15D
PR14A
PR14D
PR13A
PR12A
I/O
I/O
I/O
I/O
I/O
PB10A
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
—
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
PB14C
PB4D
PDON
PRESETN
PRGM
P4A
PR14C
PR14D
PR13A
PR13B
P
P
PR1
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
I/O-HDC
I/O
I/O
I/O
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/O-INIT
I/O
I/
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/
D
RES
PRGM
I/OM0
/O
I/O
I/O
I/O
I/O
—
PB11A
—
—
PB11B
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
—
Y20 PDONE
W20 PRESETN
V19
U19
U18
T1
V0
U20
T18
T19
T20
R18
P17
R19
R20
P18
P19
P20
N18
PPRGMN
P12A
—
—
—
P12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PR9A
I/O
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O
I/O
I/O-M2
170
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
Pin
Function
N19
N20
M17
M18
M19
M20
L19
L18
L20
K20
K19
K18
K17
J20
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PECKR
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PR2A
R2B
PRC
PR2D
P1A
PR1B
PR1C
PR1D
—
PR10B
PR10C
PR10D
PR9A
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PECKR
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5
PRA
PR
PR4C
PR4D
PR3A
PR3B
PR3C
PR3D
PRA
PR
R2C
PR
R1A
R1B
PR1C
PR1D
PR12B
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PECKR
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
P7A
R7B
PRC
PR7D
PR6A
R6B
PR5B
PR5D
PR4A
PR4B
PR4D
R3A
PR2A
R2B
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I-ECKR
I/O
I/O
I/O
I/
I/O
J19
J18
J17
H20
H19
H18
G20
G19
F20
G18
F19
E20
G17
F18
E19
D2
18
D
C20
E7
D18
C19
B20
C18
B19
A20
A19
B18
B17
C17
D16
A18
CS1
I/O
I/O
I/O
I/O-CS0
I
I/O
_STRB
/O
I/O
I/O
I/O-WR
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
I/O
RD_CFG
I/O-SECKUR
I/O
PRD_CFGN PRD_CFGN PRD_CFGN
PT12D
—
PT12C
PT12B
PT12A
—
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
PT18D
PT18C
PT18B
PT18A
PT17D
PT17A
I/O
I/O
I/O-RDY/RCLK/MPI_ALE
I/O
Lattice Semiconductor
171
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
Pin
Function
A17
C16
B16
A16
C15
D14
B15
A15
C14
B14
A14
C13
B13
A13
D12
C12
B12
A12
B11
C11
A11
A10
B10
C10
D10
A9
B9
C9
D9
A8
B8
C8
A
7
A6
C7
B6
A5
D7
C6
B5
A4
PT11D
PT11C
PT11B
PT11A
—
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
—
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PECKT
PT8C
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PTD
PT6C
PT6B
PT6
P5D
PT5C
PT5B
PT5A
PT4D
P
PT4
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
PT16D
PT16C
PT16A
PT15D
PT15A
PT14D
PT14A
PT13D
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PECKT
PT10C
PT10B
PT10A
PD
PT9C
T9B
I/O
I/O
I/O
I/O-D7
I/O
I/O
I/O
I/O
I/O-D6
I/O
I/O
I/O
I/O
I/O-D5
I/O
I/O
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PECKT
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PTA
T4D
PC
PT4
P4A
P3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
—
I/O
I/O
I-EC
I/O
I/O
I/O-D3
I/O
I/O
I/O
I/O-D2
I/O
I/O
I/O-D0/DIN
I
I/O
I/O
I/O-DOUT
I/O
I/O
I/O
I/O-TDI
I/O
I/O
I/O
I/O-TMS
I/O
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
T7C
TB
PT7A
T6D
PT6A
PT5C
PT5A
PT4D
PT4A
PT3D
PT3A
PT2D
PT2C
PT2B
C5
B4
A3
D5
PT1D
PT1C
PT1B
I/O
I/O
I/O
PT2A
172
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T20
Pad
OR3T30
Pad
OR3T55
Pad
Pin
Function
C4
B3
B2
—
—
—
PT1D
PT1C
PT1B
PT1A
PT1D
PT1C
PT1B
PT1A
I/O
I/O
I/O
A2
PT1A
I/O-TCK
C3
PRD_DATA PRD_DATA PRD_DATA RD_DATA/TDO
A1
D4
D8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VDD
V
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
VS
VS
VSS
VSS
VS
VSS
VSS
VSS
VS
VS
SS
VD
DD
DD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V
VSS
VSS
VSS
VSS
VSS
VSS
S
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
V
VSS
S*
VSS*
VSS*
VSS*
VSS*
V
VSS*
*
*
SS*
VSS*
VSS*
VSS*
VSS*
VSS*
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D13
D17
H4
H17
N4
N17
U4
U8
U13
U17
J9
J10
J11
J12
K9
K10
K11
K12
L9
L10
L11
L1
9
M
M11
M2
6
D11
D15
F4
F17
K4
L17
R4
R17
U6
U10
U15
Lattice Semiconductor
173
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table 74. OR3T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
B1
C2
C1
D2
D3
D1
E2
E4
E3
E1
F2
G4
F3
F1
G2
G1
G3
H2
J4
H1
H3
J2
J1
K2
J3
K1
K4
L2
K3
L1
M2
M1
L
PL1D
PL1C
PL1B
PL1A
PL2D
PL2C
PL2B
—
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PD
PL7C
L7B
PL7
PL8D
PL8A
PL9D
PL9B
PL9A
P10C
L1B
PL10A
ECKL
PL11C
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13B
PL13A
PL14C
PL1D
PL1C
PL1B
PL1A
PL2D
PL2A
PL3D
PL3B
PL3A
PL4D
PL4C
PL4B
PL5D
PL6D
PL6C
PL6B
I/O
I/O
I/O
I/O
I/O-A0/MPI_BE0
I/O
I/O
I/O
I/O
I/O
I/
I/O
/O
PL2A
PL3D
PL3C
PL3B
PL3A
PL4D
PL4C
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
L7B
PLA
PL8D
PLC
L8B
PL8A
PECKL
PL9
PL9B
PL9A
PL10D
PL10C
PL10B
PL10A
PL11D
PL11C
PL11B
PL11A
I/O
I/O
I/O
P
P
PL8
PL8B
I/O-A1/MPI_BE1
I/O
I/O
/O
I-A2
I/O
I/O
I/O
I/O-A3
I/O
I/O
I/O
I/O-A4
I/O-A5
I/O
I/O
I/O-A6
PL8A
PL9D
PL9C
PL9B
PL9A
P
PL
PL11A
P12D
PL12A
PL13D
PL13A
PECKL
PL14C
PL14B
PL14A
PL15D
PL15C
PL15B
PL15A
PL16D
PL16A
PL17D
PL17A
N2
M4
N1
M3
P2
P4
P1
N3
R2
P3
R1
T2
I-ECKL
I/O
I/O
I/O-A7/MPI_CLK
I/O
I/O
I/O
I/O-A8/MPI_RW
I/O-A9/MPI_ACK
I/O
I/O
I/O-A10/MPI_BI
174
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
R3
T1
R4
U2
T3
U1
U4
V2
U3
V1
W2
W1
V3
Y2
W4
Y1
W3
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
PL13B
PL13A
PL14D
PL14C
PL14B
PL14A
PL15D
PL15C
PL15B
PL15A
PL16D
PL16C
PL16B
PL16A
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL1B
PL14B
PL15C
PL15B
PL15A
PL16D
PL16C
PL16B
PL16A
PL17D
PL17C
PL17B
PL17A
PL18D
PL18C
PL18B
PL18A
PL19D
PL19C
PL19B
PL19A
20D
PL0C
PL20
PL21D
L21C
PL21A
PL22D
PL22C
PL2B
L22A
CCLK
PB
B1B
B1C
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PL18D
PL18A
PL19D
PL19A
PL20D
PL20C
PL20B
PL20A
PL21D
PL21C
PL21B
PL21A
PL22D
PL22C
PL3D
24D
PL2A
25C
5B
25A
PL26D
PL26C
PL26A
PL27D
C
PL7A
L28
28C
L28B
PL28A
PCCLK
PB1A
PB1B
PB1C
PB1D
PB2A
PB2D
PB3A
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
I/O
I/O
I/O
I/O-A11/MPI_IRQ
I/O-A12
I/O
I/O
I/O
I/
O
I/O-13
I/O
I/
I/O
I/O
I/O
I/O-A14
I/O
AA2
Y4
AA1
Y3
O
I
I/O
I
I/O
I/O
I/O
AB2
AB1
AA3
AC2
AB4
AC1
AB3
AD2
AC3
AD1
A2
A3
AF3
AE4
AD4
AF4
AE5
AC5
AD5
AF5
AE6
AC7
AD6
AF6
AE7
I/O-SECKLL
I/O
I/O
I/O
I/O-A15
CCLK
I/O-A16
I/O
—
P18A
PCCLK
PB1A
—
PB
PB1C
B
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A17
I/O
I/O
Lattice Semiconductor
175
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
AF7
AD7
PB4C
PB4D
PB5C
PB5D
PB5C
PB5D
I/O
I/O
AE8
PB5A
PB6A
PB6A
I/O
AC9
PB5B
PB6B
PB6D
I/O
AF8
PB5C
PB6C
PB7A
I/O
AD8
PB5D
PB6D
PB7D
I/O
AE9
PB6A
PB7A
PB8A
I/O
AF9
PB6B
PB7B
PB8D
I/O
AE10
AD9
PB6C
PB6D
PB7C
PB7D
PB9A
PB9D
I/O
I/O
AF10
AC10
AE11
AD10
AF11
AE12
AF12
AD11
AE13
AC12
AF13
AD12
AE14
AC14
AF14
AD13
AE15
AD14
AF15
AE16
AD15
AF16
AC15
17
AD16
AF17
AC17
AE18
AD17
AF18
AE19
AF19
AD18
AE20
AC19
AF20
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
PECKB
PB10B
PB10C
PB10D
PB11A
PB11B
P11C
PB1D
PB12A
PB2B
PB12C
PB12D
PB13A
PB1
PB13C
PB13D
PB14A
PB14B
PB14C
PB14D
PB15A
PB15B
PB15C
PB15D
PB8A
PB8D
PB9A
PB9C
PB10A
PB10D
PB11A
PB11D
PB12A
PB12D
PB1
P
PB
PB14B
PB14C
PB14D
PECKB
PB15B
PB15C
PB
P
PB1
P17D
PB18A
PB18D
PB19A
PB19D
PB20A
PB20D
PB21A
PB21D
PB22A
PB23A
PB23C
PB23D
PB24A
PB24B
PB24C
PB24D
I/O
I/
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PB9D
PB10A
PB10B
PB10D
PB11A
PB11B
PB11C
PB11D
PCKB
B12B
P12C
PB12D
PB13A
PB13B
PB13C
PB14A
PB14B
B14D
P5A
PB15D
P16A
PB16B
PB16C
PB16D
PB17A
PB17B
PB17C
PB17D
PB18A
PB18B
PB18C
PB18D
I-ECK
I/O
/O
I/O
I/O
I/O
I/O
I/O
I/O-HDC
I/O
I/O
I/O
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-INIT
I/O
I/O
I/O
176
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
AD19
AE21
AC20
AF21
AD20
AE22
AF22
AD21
AE23
AC22
AF23
AD22
AE24
AD23
AF24
AE26
AD25
AD26
AC25
AC24
AC26
AB25
AB23
AB24
AB26
AA25
Y23
AA24
AA26
Y25
Y26
Y4
W5
V23
W26
W24
V25
V26
U25
V24
U26
U23
T25
U24
T26
PB16A
PB16B
PB16C
PB16D
PB17A
PB17B
PB17C
PB17D
—
PB18A
PB18B
PB18C
—
PB19A
PB19B
PB19C
PB19D
PB20A
PB20B
PB20D
PB21A
PB21B
PB21D
PB22A
PB22B
PB22C
PB22D
PDONE
PRESETN
PPRGMN
PR22A
PR22C
PR22D
R21A
PR1D
PR20
PR20B
R20D
PR19A
PR19B
PR19C
PRD
R18A
R18B
PR1
P18D
R17A
PR17B
PR17C
PR17D
PR16A
PR16B
PR16C
PR16D
PR15A
PR15D
PR14A
PR14C
PR14D
PB25A
PB25B
PB25C
PB25D
PB26A
PB26B
PB26D
PB27A
PB27B
PB27D
PB28A
PB28B
PB28C
PB28D
PDNE
PSE
PPRGN
28A
8C
R28D
PR27A
PR27D
PR26A
PR26B
D
PR5A
R25
25C
R24A
PR23A
PR23B
PR23D
PR22D
PR21A
PR21B
PR21C
PR21D
PR20A
PR20B
PR20C
PR20D
PR19A
PR19D
PR18A
PR18D
PR17A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/
O
I/
I/O
I/
PB18D
PDONE
PRESETN
PPRGMN
PR18A
PR18B
PR18C
PR18D
PR17A
PR17B
PR17C
PR17D
PR16A
R1B
PR6C
PR16D
P15A
PR15B
PR15C
PR15D
PR1A
PR14B
C
A
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
PR11A
I/O
DONE
RESET
PRGM
I/O-M0
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M2
I/O
I/O
I/O
R25
I/O-M3
Lattice Semiconductor
177
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
R26
T24
P25
R23
P26
R24
N25
N23
N26
P24
M25
N24
M26
L25
M24
L26
M23
K25
L24
K26
K23
J25
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
PECKR
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
PR5A
PR5B
PR5C
PR5D
PR4A
R4B
PRC
PR4D
PRA
R3B
PR3C
PR3D
PR2
PR2B
—
PR13A
PR13B
PR13D
PR12A
PR12B
PR12C
PR12D
PECKR
PR11B
PR11C
PR11D
PR10A
PR10C
PR10D
PR9B
PR17D
PR16A
PR16D
PR15A
PR15B
PR15C
PR15D
PECKR
PR14B
PR14C
PR14D
PR13A
PR13D
PR12A
PR12D
PR11A
PR11D
P
P
PR9
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
P
PR6C
R5A
PR4A
PR4B
PR4C
PR4D
PR3A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I-ECKR
I/O
I/O
I/O
I/
I/O
/O
I/O
PR9C
PR9D
PR8A
PR8D
PR7A
I/O-CS1
I/O
I/O
I/O
I/O-C
/O
/O
I/O
I/O
PR7B
PR7C
PD
PR6A
K24
J26
H25
H26
J24
R6B
I/O
I/O
I/O
PR
PR6D
PR5A
G25
H23
G26
H24
F25
G23
F2
G24
E25
E26
F24
D25
E23
D26
E24
C25
D24
C26
A25
I/O-RD/MPI_STRB
PR5B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-WR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PR5C
PR5D
R4A
R
PR4C
R4D
PR3A
PR3B
PR3D
PR2A
PR2D
PR1A
PR1B
PR3B
PR3D
PR2A
PR2D
PR1A
PR1B
PR1C
PR1D
PR2C
PR2D
PR1A
PR1B
PR1C
PR1D
PRD_CFGN
PT18D
PR1C
PR1D
PRD_CFGN
PT22D
PRD_CFGN
PT28D
RD_CFG
I/O-SECKUR
178
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
B24
A24
B23
C23
A23
PT18C
—
PT18B
PT18A
PT17D
PT22C
PT22B
PT22A
PT21D
PT21A
PT28C
PT28B
PT28A
PT27D
PT27A
I/O
I/O
I/O
I/O
I/O-RDY/RCLK/
MPI_ALE
B22
D22
C22
A22
B21
D20
C21
A21
B20
A20
C20
B19
D18
A19
C19
B18
A18
B17
C18
A17
D17
B16
C17
A16
B15
A5
6
B14
D15
A14
C15
B13
D13
A13
C14
B12
C13
A12
B11
C12
A11
PT17C
PT17B
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
PT15B
PT15A
PT14D
PT14C
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
P12D
PT12C
P2B
PT1
PT11D
PT11C
PT11B
PT11A
PECT
PT10C
B
PT20D
PT20C
PT20A
PT19D
PT19C
PT19B
PT19A
PT18D
PT18C
PT18B
PT18A
PT17D
PT17C
PT17B
P17A
P6D
PT16
PT16B
T16A
PT15D
PT15B
PT15A
PT14C
T14B
T13D
PT3C
T13A
PCKT
PT12C
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT10D
PT10B
PT10A
PT9C
PT26D
PT26C
PT26A
PT25D
PT25C
PT25B
PT25A
PT24D
PT2C
P24B
PTA
T23D
3C
23B
PT22D
PT21D
PT21A
PT20
T20A
PT9D
T19
18D
T18A
PT17D
PT17A
PT16D
PT16A
PECKT
PT15C
PT15B
PT15A
PT14D
PT14C
PT14B
PT14A
PT13D
PT13A
PT12D
PT12A
PT11D
PT11A
I/O
I/O
I/O
O
I
I/O
I
I/O-D7
I/O
I/O
I/O
I/O
I/O
O
I/O
O
I/O
I/O-D6
I/O
I/O
I/O
I/O
I/O-D5
I/O
I/O
I/O
I/O-D4
I-ECKT
I/O
I/O
I/O-D3
I/O
I/O
I/O
I/O-D2
I/O-D1
I/O
I/O
I/O-D0/DIN
I/O
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT9B
PT8D
PT7C
I/O
Lattice Semiconductor
179
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
D12
B10
C11
A10
D10
B9
C10
A9
B8
A8
C9
B7
D8
A7
C8
B6
D7
A6
C7
B5
A5
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
—
PT8C
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT6B
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
PT4B
PT4A
PT3D
PT3A
PT2D
PT2C
PT2B
PT2A
PD
PT1C
T1B
PT1A
PRD_DATA
VSS
PT10D
PT10A
PT9D
PT9A
PT8D
PT8A
PT7D
PT7A
PT6D
PT6A
PT5D
PT5C
PT5B
PT5A
PT4D
PT4C
P
PT3
PT3A
PT2D
PT2C
PT2B
PT2A
PT1D
P
P
PRD_DATA
SS
I/O
I/O-DOUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TDI
I/
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TMS
I/O
IO
I/O
I/
I/O
I/O
I/O
I/O
I/O
C6
B4
D5
A4
C5
B3
C4
A3
—
PT2A
PT1D
PT1C
PT1B
PT1A
PRDDATA
VSS
I/O-TCK
RD_DATA/TDO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A1
A2
VSS
SS
VSS
6
AC1
AC18
AC2
AC4
AC8
AD24
AD3
AE1
AE2
AE25
AF1
AF25
AF26
SS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
180
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
B2
B25
B26
C24
C3
D14
D19
D23
D4
D9
H4
J23
N4
P23
V4
W23
L11
L12
L13
L14
L15
L16
M11
M12
M13
M14
M15
M16
N11
N12
N3
N4
N15
N16
P11
P12
P13
P14
P15
P16
R11
R12
R13
R14
R15
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SS
VS
S
VS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
SS
V
VSS
S
SS
VSS
VSS
VSS
VSS
S
VS
VSS
SS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
SS
VS
VSS
V
VSS
VSS
VSS
VSS
VSS*
VSS*
VS*
VSS
VS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
Lattice Semiconductor
181
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3T55
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
R16
T11
T12
T13
T14
T15
T16
AA23
AA4
AC11
AC16
AC21
AC6
D11
D16
D21
D6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VD
VDD
VDD
VDD
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VDD
VDD
VDD
VDD
VD
VD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DD
DD
VD
F23
F4
L23
L4
T23
T4
*Thermally enhanced connection.
182
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Table 75. OR3C/T80 and OR3T125 432-Pin EBGA
Pinout
OR3C/T80
OR3T125
Pad
Pin
Function
Pad
V1
V2
V3
W1
V4
W2
W3
Y2
W4
Y3
AA1
AA2
Y
PR13C
PR13B
PR13A
PR14D
PR14C
PR14B
PR14A
PR15D
PR15A
R16D
R16C
P16B
PR16A
P17D
PR17C
PR17B
PR17A
PR18D
PR8C
PR18
R1
P19D
PR19C
PR19B
PR19A
PR20D
PR20C
PR20B
PR20A
PR21D
PR21C
PR21B
PR21A
PR22D
PR22C
PR22B
PR22A
PPRGMN
PRESETN
PDONE
PB22D
PB22C
PB22B
PB22A
PB21D
PB21C
PB21B
PB21A
PB20D
PB20C
PR16B
PR16A
PR17D
PR17A
P18D
PB
PR18A
PR19D
PR9A
R20D
PR20C
PR20B
PR20A
PR1D
21
PRB
R21A
P2D
P23D
PR23B
PR23A
PR24A
PR25C
PR25B
PR25A
PR26D
PR26C
PR26B
PR26A
PR27D
PR27C
PR27B
PR27A
PR28D
PR28C
PR28B
PR28A
PPRGMN
PRESETN
PDONE
PB28D
PB28C
PB28B
PB28A
PB27D
PB27C
PB27B
PB27A
PB26D
PB26C
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
I/O
I/O-M2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
E4
D3
D2
D1
F4
E3
E2
E1
F3
F2
F1
H4
G3
G2
G1
J4
PRD_CFGN
PR1D
PR1C
PR1B
PR1A
PR2D
PR2C
PR2B
PR2A
PR3D
PR3C
PR3B
PR3A
PR4D
PR4C
PR4B
PR4A
PR5D
PR5C
PR5B
PR5A
PR6D
PR6C
PR6B
PR6A
PR7D
PR7
PR7B
PR7A
R8D
PR
PR9D
PR9C
PR9B
PR9A
PR1
P
PR1
PR10A
PR11D
PR11C
PR11B
PECKR
PR12D
PR12C
PR12B
PR12A
PR13D
PRD_CFGN
PR1D
PR1C
PR1B
RD_CFG
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-WR
I/O
I/O
I/O
PR1A
PR2D
PR2C
PR2B
PR2A
PR3D
PR3C
PR3B
AA
AB1
AB2
AB3
C1
AC2
AB4
AC3
AD2
D3
C4
AE
AE2
AE3
AD4
AF1
AF2
AF3
AG1
AG2
AG3
AF4
AH1
AH2
AH3
AG4
AH5
AJ4
AK4
AL4
AH6
AJ5
AK5
AL5
AJ6
AK6
AL6
PR3A
PR4D
PR4C
PR4B
PR4A
PR5A
PR6C
PR6A
PR7A
PR8D
R8C
PR8B
H3
H2
J3
K4
J2
I/O
I/O-RD/MPI_STRB
I/O
J1
K3
K2
K1
L3
M4
L2
I/O
I/O
I/O
I/O
I/O
I/O
R8A
PR9D
PR9C
R9B
L1
PR9A
M3
4
M2
N
N2
P
1
P3
P2
P1
R3
R2
R1
T2
T4
T3
U1
U2
U3
PR10D
PR10A
PRD
R11A
PR12D
PR1C
P12A
PR13D
PR13C
PR13A
PR14D
PR14C
PR14B
PECKR
PR15D
PR15C
PR15B
PR15A
PR16D
I/O
I/O-CS1
I/O
I/O-M0
PRGM
RESET
DONE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I-ECKR
I/O
I/O
I/O
I/O
I/O
I/O
Lattice Semiconductor
183
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3C/T80
Pad
OR3T125
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
Pin
Function
AH8
AJ7
AK7
AL7
AH9
AJ8
AK8
AJ9
AH10
AK9
PB20B
PB20A
PB19D
PB19C
PB19B
PB19A
PB18D
PB18C
PB18B
PB18A
PB17D
PB17C
PB17B
PB17A
PB16D
PB16C
PB16B
PB16A
PB15D
PB15B
PB15A
PB14D
PB14C
PB14B
PB14A
PB13D
PB13C
PB13B
PB13A
PB12D
PB12C
PB12B
ECKB
PB1D
P11C
PB1B
B11A
PB10D
PB10C
PB10B
PB10A
PB9D
PB26B
PB26A
PB25D
PB25C
PB25B
PB25A
PB24D
PB24C
PB24B
PB24A
PB23D
PB23C
PB23A
PB22A
PB21D
PB21A
PB20D
PB20A
PB19D
PB19B
PB19A
PB18D
PB18B
PB18A
PB17D
PB17B
PB17A
PB16D
B1A
P5D
PB15
PB15B
ECKB
PB14D
PB14C
PB14B
PB14
3D
PD
PB12A
PB11D
PB11B
PB11A
PB10D
PB10B
PB10A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-INIT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AK21
AH20
AJ21
AL22
AK22
AJ22
AL23
AK23
AH22
AJ23
AK24
AJ24
AH23
AL25
AK25
AJ25
AH2
6
AK2
J26
L27
AK27
AJ27
AH26
AL28
AK2
8
A27
AG2
AH29
AH30
AH31
AF28
AG29
AG30
AG31
AF29
AF30
AF31
AD28
AE29
AE30
AE31
AC28
AD29
AD30
AC29
AB28
PB7D
PB7C
PB7B
PB7A
PB6D
PB6C
PB6B
PB6A
PB5D
PB5C
PB5B
PBA
B4D
P4C
PBB
PB
PB3D
PB3C
PB3B
PB3A
PB2D
PBC
PB2B
PB2A
P1D
PB1C
PB1B
PB1A
PCCLK
PL22A
PL22B
PL22C
PL22D
PL21A
PL21B
PL21C
PL21D
PL20A
PL20B
PL20C
PL20D
PL19A
PL19B
PL19C
PL19D
PL18A
PL18B
PL18C
PB9D
PB9A
PB8D
PB8A
PB7D
PB7A
PBD
6A
PB5
PB5C
PBB
P5A
PB4D
PB4C
PB4B
PB4
PB3D
B3C
PB
B3A
D
PB2C
PB2B
PB2A
PB1D
PB1C
PB1B
PB1A
PCCLK
PL28A
PL28B
PL28C
PL28D
PL27A
PL27B
PL27C
PL27D
PL26A
PL26B
PL26C
PL26D
PL25A
PL25B
PL25C
PL24A
PL24D
PL23D
PL22C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AL9
AJ10
AK10
AL10
AJ11
AH12
AK11
AL11
AJ12
AH13
AK12
AJ13
AK13
AH14
AL13
AJ14
AK14
AL14
AJ15
AK15
AL15
AK16
AH16
AJ16
AL17
A17
A
AL18
AK18
AJ18
AL19
AH18
AK19
AJ19
AK20
AH19
AJ20
AL21
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-LDC
I/O
I/O
I/O
I/O
I/O
I/OHDC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-A16
CCLK
I/O-A15
I/O
I/O
I/O
I-ECKB
I/O
I/O-SECKLL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PB9C
PB9B
PB9A
PB8D
PB8B
PB8A
I/O
I/O-A14
I/O
I/O
I/O
184
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3C/T80
OR3T125
Pad
OR3C/T80
OR3T125
Pad
Pin
Function
Pin
Function
Pad
Pad
AC30
AC31
AB29
AB30
AB31
AA29
Y28
AA30
AA31
Y29
W28
Y30
W29
W30
V28
W31
V29
V30
V31
U29
U30
U31
T30
PL18D
PL17A
PL17B
PL17C
PL17D
PL16A
PL16B
PL16C
PL16D
PL15A
PL15B
PL15C
PL14A
PL14B
PL14C
PL14D
PL13A
PL13B
PL13C
PL13D
PL12A
PL12B
PL12C
PL12D
PL11A
PL11B
PL11C
PECKL
PL1
PL10B
PL10C
L10D
PA
PL9B
PL9C
PL9D
PL8A
PL8
P
PL
PL7B
PL7C
PL7D
PL6A
PL6B
PL6C
PL6D
PL5A
PL5B
PL22D
PL21A
PL21B
PL21C
PL21D
PL20A
PL20B
PL20C
PL20D
PL19A
PL19D
PL18A
PL18C
PL18D
PL17A
PL17C
PL17D
PL16A
PL16C
PL16D
PL15A
PL15B
PL15C
PL15D
P1A
PL14B
L14C
PE
PL13A
L13D
PL12A
PL12C
PL12D
PLA
L11C
P1D
PL10A
10C
PL10D
PL9A
I/O
I/O
I/O-A13
H29
J28
PL5D
PL4A
PL4B
PL4C
PL4D
PL3A
PL3B
PL3C
PL3D
L2A
PL2B
P2C
PL2D
1A
PL1B
PL1C
PL1D
PL6D
PL5D
PL4B
PL4C
PL4D
PA
PL3B
PL3C
PLD
PL2A
PL2B
PL2C
PL2D
P1A
L1B
PL
PL1D
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G31
G30
G29
H28
F31
F30
F29
E31
E30
E29
F
D3
D30
D29
E28
I/O
I/O
I/O
I/O
I/O
I/O-A12
I/O-A11/MPI_IRQ
I/O
I/O
I/O
I/O
0/MPI_BE0
I/O
I/O
I/O
I/O
I/O-A10/MPI_BI
I/O
I/O
I/O
27 PRD_DAPRDDATA
RD_DATA/TDO
C28
B28
A28
D26
C27
7
A2
C26
B26
A26
D24
C25
B25
A25
D23
C24
B24
C23
D22
B23
A23
C22
B22
A22
C21
D20
B21
A21
C20
D19
B20
C19
PTA
PT1B
T1C
P1D
PT2A
PT2B
PT2C
PT2D
PT3A
PT3B
PT3C
PT3D
PT4A
PT4B
PT4C
PT4D
PT5A
PT5B
PT5C
PT5D
PT6A
PT6B
PT6C
PT6D
PT7A
PT7B
PT7C
PT7D
PT8A
PT8C
PT8D
PT9A
PT1A
PT1B
PT1C
PT1D
PT2A
PT2B
PT2C
PT2D
PT3A
PT3B
PT3C
PT3D
PT4A
PT4B
PT4C
PT4D
PT5A
PT5B
PT5C
PT5D
PT6A
PT6D
PT7A
PT7D
PT8A
PT8D
PT9A
PT9D
PT10A
PT10D
PT11A
PT11C
I/O-TCK
I/O
I/OK
I/O-AW
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
T28
T29
I/-A7/MPI_CL
R31
R30
R29
P31
P30
P29
N31
P8
30
N2
M30
N8
29
L31
L30
M28
L29
K31
K30
K29
J31
I/O
I/O
I-ECKL
I/O
I/O-A5
I/O-A4
I/O
I/O
I/O
I/O
I/O
I/O-A3
I/O
I/O
I/O
I/O-A2
I/O
I/O
I/O
I/O-TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-TDI
I/O
I/O
I/O
I/O
I/O
I/O
PL9B
PL9C
PL9D
PL8A
PL8B
PL8C
PL8D
PL7D
I/O
I/O
I/O
I/O-DOUT
I/O
J30
K28
J29
I/O-A1/MPI_BE1
I/O
PL6B
PL6C
I/O
I/O
H30
PL5C
I/O
Lattice Semiconductor
185
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3C/T80
Pad
OR3T125
Pad
OR3C/T80
Pad
OR3T125
Pad
Pin
Function
Pin
Function
B19
D18
A19
C18
B18
A18
C17
B17
A17
B16
D16
C16
A15
B15
C15
A14
B14
C14
A13
D14
B13
C13
B12
D13
C12
A11
B11
D12
C11
A10
B10
C10
A9
B9
D10
9
C8
D9
A7
B7
C7
D8
A6
B6
C6
A5
B5
C5
D6
PT9B
PT9C
PT9D
PT11D
PT12A
PT12C
PT12D
PT13A
PT13C
PT13D
PT14A
PT14B
PT14C
PT14D
PT15A
PT15B
PT15C
PECKT
PT16A
PT16B
PT16D
PT17A
PT17B
PT17D
PT18A
PT18B
PT18D
PT19A
PT19D
PT20A
T20D
T2A
P1D
PT22
PT23B
T23C
PT23D
PT24A
PT24B
PT24
4D
PC
PT25D
PT26A
PT26B
PT26C
PT26D
PT27A
PT27B
PT27C
PT27D
I/O
I/O-D0/DIN
A4
B4
C4
PT22A
PT22B
PT22C
PT22D
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VS
SS
VS
VS
VS
VSS
VSS
VSS
VSS
VSS
VS
VSS
VSS
VS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
PT28A
PT28B
PT28C
PT28D
VSS
VSS
VS
SS
VS
VSS
VS
VS
VSS
VSS
VSS
VSS
VSS
SS
VS
VSS
S
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D1
I/O-D2
I/O
I/O
I/O
I/O-D3
I/O
I/O
I-ECKT
I/O-D4
I/O
I/O
I/O
I/O
I/O
/O-D5
I/O
O
I/O
I/O
I/O
I/O-D6
I/O
I/O
/O
I/O
I/O
I/O
PT10A
PT10B
PT10C
PT10D
PT11A
PT11B
PT11C
PT11D
PT12A
PT12B
PT12C
PECKT
PT13A
PT13B
PT13C
PT13D
PT14A
PT14B
PT14C
PT14D
PT15A
PT15B
PT15D
PT16A
PT16B
PT16C
PT16D
PT17
PT17B
T17C
PT7D
P18A
PT1B
T18C
PT18D
PT19A
PT19B
PT19C
PT19D
PT20A
PT20B
PT20C
PT20D
PT21A
PT21B
PT21C
PT21D
D5
I/O-SECKUR
VSS
VSS
VSS
VSS
VSS
VSS
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
A12
A16
A2
A20
A24
A29
A3
A30
A8
AD1
AD31
J1
AJ2
A0
AJ3
K1
K29
AK3
AK31
AL12
AL6
AL2
L
A24
AL2
AL3
AL30
AL8
B1
B29
B3
B31
C1
I/O
I/O
I/O
I/O-D7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
C2
C30
C31
H1
H31
M1
M31
T1
T31
Y1
I/O-RDY/RCLK/MPI_ALE
I/O
I/O
I/O
Y31
A1
A31
186
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
OR3C/T80
OR3T125
Pad
Pin
Function
Pad
AA28
AA4
AE28
AE4
AH11
AH15
AH17
AH21
AH25
AH28
AH4
AH7
AJ29
AJ3
AK2
AK30
AL1
AL31
B2
B30
C29
C3
D11
D15
D17
D21
D25
D28
D4
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
VDD
VDD
VDD
VDD
VD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DD
VDD
VDD
VDD
VDD
VDD
VDD
D
VDD
VDD
VD
DD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VD
VDD
VDD
VDD
VDD
VDD
V
VDD
VDD
VDD
VDD
VDD
VDD
VDD
D7
G28
G4
28
4
R2
R4
U8
U4
Lattice Semiconductor
187
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Thermal Characteristics
There are four thermal parameters that are in common use: ΘJA, ψ
JC, ΘJC, and ΘJB. It should be noted that all the
parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials,
the amount of copper in the test board or system board, and system airflow.
Table 76 contains the currently available thermal specifications for FPGA packages mounted oboth JEDEC and
non-JEDEC test boards. The thermal values for the newer package types correspond to those acgemounted
on a JEDEC four-layer board.The values for the older packages, however, correspond to tose packagemounted
on a non-JEDEC, single-layer, sparse copper board (see Note 2). It should also be notd that he vaues for the
older packages are considered conservative.
Θ
JA
This is the thermal resistance from junction to ambient (a.k.a. theta-JA, -thea, etc.).
TJ – TA
ΘJA =
-------------------
Q
where TJ is the junction temperature, TA is the ambient air tmpeature, and Q is the chip pow.
Experimentally, ΘJA is determined when a special therest dis assembled ino the ackagof interest, and
the part is mounted on the thermal test board.The he test chip are separaly calibrated in an oven.The
package/board is placed either in a JEDEC natural cbox or in the wunnthe latter for forced con-
vection measurements. A controlled amount of power (dissipated in he techip’s heater resistor, the chip’s
temperature (TJ) is determined by the forwd drop on the diodes, and he abient emperature (TA) is noted. Note
that ΘJA is expressed in units of °C/watt
188
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
ψ
JC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally
used to infer the junction temperature while the device is operating in the system. It is not considered a true ther-
mal resistance, and it is defined by:
TJ – TC
ψ
JC =
-------------------
Q
where TC is the case temperature at top dead center, TJ is the junction temperaure, and Q he chip power. Dur-
ing the ΘJA measurements described above, besides the other parameters mesurd, an additional temperature
ψ
reading, TC, is made with a thermocouple attached at top-dead-center of the caseJC is also expressed in units of
°C/watt.
Θ
JC
This is the thermal resistance from junction to case. It is most oftused when attachig a hat sinto the top of
the package. It is defined by:
TJ – TC
Θ=
----------------
Q
The parameters in this equation have been ove. However, mearements are performed with the
case of the part pressed against a water-coolesink so as to draw most of the heat generated by the chip out
ψ
the top of the package. It is this diffrence in the easurement pross tht differentiates ΘJC from JC. ΘJC is a
true thermal resistance and is eprssed in units of °C/watt.
ΘJB
This is the thermal esistae frojunction to board a.k.a. ΘL). It is defined by:
TJ – TB
B =
-------------------
Q
where TB s the tempeature of the bd ado a lead measured with a thermocouple. The other parameters
on the rightand sie have been efined above. This is considered a true thermal resistance, and the measure-
met is made ita water-cooled eat sinpressed against the board so as to draw most of the heat out of the
leds. ote that ΘJB is expresed in nits f °C/watt, and that this parameter and the way it is measured is still in
JEDC committee.
Lattice Semiconductor
189
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Thermal Characteristics (continued)
FPGA Maximum Junction Temperature
Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the
maximum junction temperature of the FPGA can be found. This is needed to determine if speed dating of the
device from the 85 °C junction temperature used in all of the delay tables is needed. Using the maximum ambient
temperature, TAmax, and the power dissipated by the device, Q (expressed in °C), the maximum nction empera-
ture is approximated by:
TJmax = TAmax + (Q • ΘJA)
Table 76 lists the plastic package thermal characteristics for the ORCA Series FGAs.
Table 76. Plastic Package Thermal Characteristics for the ORCA Series1
ΘJA (°C/W)
TA = 70 °C max
T= 125 °C max
@ 0 fpm (W)
Package
144-Pin TQFP1
0 fpm
200 fpm
500 fpm
52.0
26.5
12.8
25.5
13.0
22.5
26.0
19.0
25.5
10
39.0
23.0
10.3
22.5
10.0
19.0
22.0
16.0
2.0
8.5
–
21
.1
2
9.0
17.5
20.5
15.0
20.5
5
1.1
2.1
3
2.2
.2
2
2.1
2.9
2.1
5.0
208-Pin SQFP1
208-Pin SQFP21
240-Pin SQFP1
240-Pin SQFP21
256-Pin PBGA1, 2
256-Pin PBGA1, 3
352-Pin PBGA1, 2
352-Pin PBGA1, 3
432-Pin EBGA1
1. Mounted on 4-layer JEDEC standard teboard wtwo power/grouns.
2. With thermal balls connected to oard grod plae.
3. Without thermal balls conneced to bard ground plane.
190
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Coplanarity
The coplanarity limits of the ORCA Series 3 packages are as follows.
Table 77. Package Coplanarity
Coplanarity Limit
Package Type
(mils)
EBGA
PBGA
8.0
8.0
SQFP/SQFP2
4.0
3.15
TQFP
3.15
Package Parasitics
The electrical performance of an IC package, such as signal qualitand noise senitivity, diretly affected by the
package parasitics. Table 78 lists eight parasitics aociad with the ORCA packag. Theparasitics represent
the contributions of all components of a package, whinclude the bond wir, all inteal package routing, and
the external leads.
Four inductances in nH are listed: LSW and lf-inductance of the leaand LMW and LML, the mutual
inductance to the nearest neighbor lead.Theseters are importt in dmining ground bounce noise and
inductive crosstalk noise. Three capcitances in are listed: CM, e mual capacitance of the lead to the near-
est neighbor lead; and C1 and Ce total capacitance of thlead to ll other leads (all other leads are assumed
to be grounded). These parameters e important in detering capacve crosstalk and the capacitive loading
effect of the lead. The lead ristance vue, RW, is in MΩ.
The parasitic values in Tble 78 are for the circuit model obond wire and package lead parasitics. If the mutual
capacitance value is not ed in te designer’s mo, e value listed as mutual capacitance should be
added to each of e C1 and capacitors.
Table 78. Packaarasitcs
Package Type
LSW
LW
C1
C2
CM
LSL
LML
144-in TQP
28-Pin SQFP
2-in SQFP2
240-n QFP
2-Pin SQFP2
25-Pin PBGA
352-Pin PBG
432-Pin EBG
3
4
4
4
5
5
4
1
2
2
2
2
2
1.5
140
200
200
200
200
220
220
500
1
1
1
1
1
1
1.5
1
1
1
1
1
1
1
1.5
1
0.6
1
1
1
1
1
1.5
0.3
4—6
7—10
6—9
8—12
7—11
5—8
2—2.5
4—6
4—6
5—8
4—7
2—4
3—6
0.5—1
7—12
3—5.5
Lattice Semiconductor
191
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
LSW
RW
LSL
BOARD PAD
C2
PAD N
C1
LMW
LSW
LML
LSL
CM
PAD N + 1
RW
C1
C2
5-3862(F).a
Figure 104. Package Parasitics
Package Outline Diagrams
Terms and Definitions
Basic Size (BSC):
The basic size of a ension is the size from wich thimits for that dimension are derived
by the application of thallowance and the tence.
Design Size:
The design sze of a dimenion is the actal size of e design, including an allowance for fit
and tolerane.
Typical (TYP):
When pecifid aftea dimension, this dicatthe repeated design size if a tolerance is
speified r repeated basic size tolernce is not specified.
Reference (REF):
The rencdimension is nced dimension used for informational purposes only.
It is a reted dimension or an be derived from other values in the drawing.
Minimum (MIN) or
Maximum (AX):
Idiates the minimm or mamum allowable size of a dimension.
192
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Outline Diagrams (continued)
144-Pin TQFP
Dimensions are in millimeters.
22.00 0.20
20.00 0.20
PIN #1 IDENTIFIER ZONE
144
109
1
108
20.00
20
22.00
0.20
36
73
72
DETAIL A
TAIL B
1.40 0.05
1.60 MAX
SEATING PLANE
0.08
0.05/0.15
0.50 P
1.00 REF
0.25
0.106/0.200
GAGE PLANE
0.19/0.27
SEATING PLANE
0.45/0.75
0.08
M
DETAIL A
DETAIL B
Lattice Semiconductor
193
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Outline Diagrams (continued)
208-Pin SQFP
Dimensions are in millimeters.
30.60 0.20
28.00 0.20
1.30 F
PIN #1 IDENTIFIER ZONE
208
157
0.2
1
156
AGE PLANE
SEANG PLAE
5
TAIL A
2800
0.20
30.60
0.20
0.090/0.200
0.17/0.27
M
0.10
DETAIL B
105
52
53
DETAIL A
DETAIL B
3.40 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TP
0.25 MIN
Note: The dimensions in this outline diagram are intended for informational purposes only.
194
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Outline Diagrams (continued)
208-Pin SQFP2
Dimensions are in millimeters.
30.60 0.20
28.00 0.20
21.0 REF
PIN #1 IDENTIFIER ZONE
208
1.30 REF
157
156
0
GAGE PLANE
SEATING PLNE
0.50/0.75
.0
REF
28.00
0.20
DETAIL A
30.6
0.20
0.090/0.200
0.17/0.2
M
0.10
DETAIL B
53
104
EXPD HEAT SINK APPEARS
SURFE: CHP BONDED FACE TAIL C.)
ETAIL A
DAIL B
3.40 0.20
4.10 MAX
SEATING PLANE
0.08
5-3828(F)
0.50 TYP
0.25 MIN
CHIP BONDED FACE UP
CHIP
COPPER HEAT SINK
DETAIL C (SQFP2 CHIP-UP)
5-3828(F).a
Lattice Semiconductor
195
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Outline Diagrams (continued)
240-Pin SQFP
Dimensions are in millimeters.
34.60 0.20
32.00 0.20
1.30 REF
PIN #1 IDENTIFIER ZONE
240
181
1
180
0.25
GAGE ANE
ATING LANE
5
DETA
32.00
0.20
34.60
0.20
0.090/0.200
0.17/0.27
M
0.10
DETAIL B
60
61
DETA
ETAIL
3.40 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
Note: The dimensions in this outline diagram are intended for informational purposes only.
196
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Outline Diagrams (continued)
240-Pin SQFP2
Dimensions are in millimeters.
34.60 0.20
32.00 0.20
24. 2 REF
1.3REF
PIN #1 IDENTIFIER ZONE
240
181
1
180
0.25
GAGE PLANE
SEATING PLAN
0.50/0.75
4.2
E F
DETAIL A
32.00
0.20
34.6
0.20
0.090/0.200
0.17/0.27
M
0.10
DETAIL B
60
121
61
120
EXPD HEASINK APPEARS
SURFA: CP BONDED FACE TAIL C.)
DETAIL
DETAIA
3.40 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TY
0.25 MIN
CHIP BONDED FACE UP
CHIP
COPPER HEAT SINK
DETAIL C (SQFP2 CHIP-UP)
5-3825(F).a
Lattice Semiconductor
197
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Outline Diagrams (continued)
256-Pin PBGA
Dimensions are in millimeters.
27.00 0.20
+0.70
24.00
–0.00
A1 BALL
IDENTIFIER ZONE
+0.70
–0.00
24.00
200
0.
MOLD
COMPOUND
PWB
1.17 0.
2.13 0.19
0.36 0.04
SEATING PLANE
0.20
R BALL
19 SP@ 1.2= 24.13
0.60.10
Y
W
V
U
T
P
0.75 0.15
N
L
K
J
19 SPACES
@ 1.27 = 24.13
G
F
CENTE
FOR THAL
E
D
C
B
A
ENHANCEENT
(OPTIONAL)
(SEE NOTE BELOW)
1
2
3 4 5 6
7
8 9 10 12 14 16 18 20
11 13 15 17 19
A1 BALL
CORNER
5-4406(F)
Note: Although the 16 thermal enhancement balls are stated as an option, they are standard on the 256 FPGA package.
198
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Outline Diagrams (continued)
352-Pin PBGA
Dimensions are in millimeters.
35.00 0.20
+0.70
30.00
–0.00
A1 BALL
IDENTIFIER ZONE
+0.70
30.00
–0.0
50
20
MOLD
COMPOUND
PWB
.17 .05
0.06
2.33 0.21
SEATING PLANE
0.20
SOLDER BALL
25 SPAC@ 1.27 = 31.75
0.60 0.10
AF
AE
AD
AC
A
A
0.75 0.15
V
U
T
P
N
25 SPACES
@ 1.27 = 31.75
L
K
J
H
ARRAY
ERMAL
EMENT
PTIONAL)
G
F
E
D
C
B
A
(SEE NOTE BELOW)
1 2 3
4
5 6
7
8 9 10 12 14 16 18 20 22 24 26
11 13 15 17 19 21 23 25
A1 BALL
CORNER
5-4407(F)
Note: Although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 FPGA package.
Lattice Semiconductor
199
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Package Outline Diagrams (continued)
432-Pin EBGA
Dimensions are in millimeters.
40.00 0.10
A1 BALL
IDENTIFIER ZONE
40.00
0.10
0.91 0.06
1.54 0.13
SEATING PLANE
0.20
SOLDER BA
0.63 0.07
30 SPACES @ 1.2= 38.10
AJ
A
AH
AG
AE
AC
AF
AD
0.75 0.15
AB
Y
A
W
V
U
R
30 SPACES
@ 1.27 = 38.10
T
M
L
J
F
G
E
D
C
A
B
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31
10 12 14 16 18 20 22 24 26 28 30
A1 BALL
CORNER
2
4
6
8
5-4409(F)
200
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Ordering Information
OR3XXXX X XX XXX X XX
Packing Designator
DB = Dry Packed Tray
Device Family
OR3T20
OR3T30
OR3T55
Grade
Blank = Commeral
I = Industrial
OR3C80
OR3T80
OR3T125
Pin/Ball Count
Speed Grade
Package Type
BA = PlasBall rid Array (PB
B= Ehanced Ball Grid Array (
PS PowQuad Shrink lat PackSQFP2)
S = hrink Quad Flat Pkag(SQFP)
T = n Quad Flat acka(TQFP)
Table 79. Ordering Information
Comcial
Speed
Grade
Page
Tye
Pin/Ball
Count
Packing
Designator
Device Family
Part Number
Grade
OR3C80
OR3C805PS8-DB2
OR3C805BA35DB2
OR3C0PS208-D2
OR3804BA352-DB2
OR3T07S20-DB
OR3T207BA256-DB
OR3T206S208-DB
OT206T144-DB
OR3T206BA26-DB
OR3T307S20-DB
OR3T37S240-B
OR33076-DB
O3T306S20-DB
OR3306S240-DB
3T306BA256-DB
5
5
4
4
7
6
6
6
7
7
7
6
6
6
SFP2
PBGA
SQFP2
PBGA
SQFP
PBGA
SQFP
TQFP
PBGA
SQFP
SQFP
PBGA
SQFP
SQFP
PBGA
208
352
208
352
208
256
208
144
256
208
240
256
208
240
256
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
OR3T20
O3T30
Lattice Semiconductor
201
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Commercial
Speed
Grade
Package
Type
Pin/Ball
Count
Packing
Designator
Device Family
Part Number
Grade
1
OR3T55
OR3T557PS208-DB
7
7
7
7
7
6
6
6
6
6
7
7
7
7
6
6
6
7
7
6
6
6
SQFP2
SQFP
SQFP2
PBGA
PBGA
SQFP2
SQFP
SQFP2
PBGA
PBG
QFP2
SQF
SQFP2
PGA
EBGA
SQFP2
SQFP
SQFP2
PA
EBGA
SQFP2
FP2
PBGA
EBGA
SQFP2
SQFP2
PBGA
EBGA
208
208
240
256
352
208
208
240
56
352
208
208
240
352
42
208
208
20
352
432
208
240
352
432
208
240
352
432
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
OR3T557S208-DB
3
OR3T557PS240-DB
OR3T557BA256-DB
OR3T557BA352-DB
1
OR3T556PS208-DB
OR3T556S208-DB
3
OR3T556PS240-DB
OR3T556BA256-DB
OR3T556BA352-DB
1
OR3T80
OR3T807PS208-DB
OR3T807S208-DB
3
OR3T807PS240-DB
OR3T807BA352-DB
OR3T807BC432-DB
1
OR3T806PS208-DB
OR3T806S208-DB
3
OR3T806PS240-DB
OR3T806BA352-DB
OR3T806BC42-DB
3
OR3T125
OR3T1257P208-DB
OR3T157PS40-DB
OR31257A352-DB
OR3T7BC432-DB
3
OR3T125S208-DB
OR3T1256PS240-DB
O31256BA352-DB
3
OR3T1256BC42DB
202
Lattice Semiconductor
Data Sheet
November 2006
ORCA Series 3C and 3T FPGAs
Industrial
Speed
Grade
Package
Type
Pin/Ball
Count
Packing
Designator
Device Family
Part Number
Grade
2
OR3C80
OR3C804PS208I-DB
OR3C804BA352I-DB
OR3T206S208I-DB
OR3T306S208I-DB
OR3T306S240I-DB
OR3T306BA256I-DB
4
4
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
SQFP2
PBGA
SQFP
SQFP
SQFP
PBGA
SQFP2
SQP
QFP
PBA
PBGA
QFP2
SQFP
SQFP2
PBGA
EA
SQF2
SFP2
PBGA
EBGA
208
352
208
208
24
56
20
208
240
256
352
08
20
240
52
432
208
240
352
432
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
2
OR3T20
OR3T30
1
OR3T55
OR3T80
OR3T125
OR3T556PS208I-DB
OR3T556S208I-DB
OR3T556PS240I-DB
OR3T556BA256I-DB
OR3T556BA352I-DB
OR3T806PS208I-DB
OR3T806S208I-DB
OR3T806PS240I-DB
OR3T806BA352I-DB
3
1
3
OR3T806BC432I-DB
OR3T1256PS208I-DB
OR3T1256P40I-DB
OR3T1256BA35-DB
3
3
OR3T256BC432I-B
1. Converted to S208 pacage vice per CN#11A-06.
2. Discontinued per PC#02-06. CtacRochester Electronics favailable inventory.
2. Discontinued per CN#07. Contact Rochester Elfor ailable inventory.
Lattice Semiconductor
203
相关型号：
OR3T55-6PS240I-DB
Field Programmable Gate Array, 324 CLBs, 40000 Gates, 80MHz, CMOS, PQFP240
LATTICE
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