OR4E02-2BM416C [LATTICE]
ORCASeries 4 FPGAs; ORCASeries 4 FPGA的
| 型号： | OR4E02-2BM416C |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | ORCASeries 4 FPGAs |
| 文件： | 总152页 (文件大小：2702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
May, 2006
®
ORCA Series 4 FPGAs
■ Traditional I/O selections:
— LVTTL (3.3V) and LVCMOS (2.5 V and 1.8 V)
I/Os.
Introduction
Built on the Series 4 reconfigurable embedded sys-
tem-on-a-chip (SoC) architecture, Lattice introduces
its new family of generic Field-Programmable Gate
Arrays (FPGAs). The high-performance and highly
versatile architecture brings a new dimension to
bringing network system designs to market in less
time than ever before. This new device family offers
many new features and architectural enhancements
not available in any earlier FPGA generations. Bring-
ing together highly flexible SRAM-based programma-
ble logic, powerful system features, a rich hierarchy
of routing and interconnect resources, and meeting
multiple interface standards, the Series 4 FPGA
accommodates the most complex and high-perfor-
mance intellectual property (IP) network designs.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-lim-
ited).
— Fast-capture input latch and input flip-flop
(FF)/latch for reduced input setup time and zero
hold time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
■ New programmable high-speed I/O:
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I and II), HSTL (Class I, III, and IV), ZBT,
and DDR.
— Double-ended: LDVS, bused-LVDS, and
LVPECL. Programmable (on/off) internal parallel
termination (100 Ω) also supported for these
I/Os.
Programmable Features
■ High-performance platform design:
— 0.16 μm 7-level metal technology.
— Internal performance of >250 MHz.
— I/O performance of >420 MHz.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V
operation) translates to greater performance.
Table 1. ORCA Series 4—Available FPGA Logic
EBR
Blocks
EBR Bits
(K)
Usable*
Gates (K)
Device
Rows
Columns
PFUs
User I/O
LUTs
OR4E02
OR4E04
OR4E06
26
36
46
24
36
44
624
405
466
466
4,992
10,368
16,192
8
74
201—397
333—643
471—899
1,296
2,024
12
16
111
148
* The embedded system bus and MPI are not included in the above gate counts. The System Gate ranges are derived from the following:
minimum system gates assumes 100% of the PFUs are used for logic only (no PFU RAM) with 40% EBR usage and 2 PLLs. Maximum
system gates assumes 80% of the PFUs are for logic, 20% are used for PFU RAM, with 80% EBR usage and 6 PLLs.
Note: Devices are not pinout compatible with ORCA Series 2/3.
© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All
other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to
change without notice.
www.latticesemi.com
1
or4e_05
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table of Contents
Contents
Page
Contents
Page
Introduction ................................................................ 1
Programmable Features ............................................ 1
System Features ....................................................... 4
Product Description ................................................... 5
Architecture Overview ..........................................5
Programmable Logic Cells ........................................ 6
Programmable Function Unit ...............................7
Look-Up Table Operating Modes .......................10
Supplemental Logic and Interconnect Cell ........20
PLC Latches/Flip-Flops ......................................24
Embedded Block RAM (EBR) .................................. 26
EBR Features ....................................................26
Routing Resources .................................................. 31
Clock Distribution Network ...................................... 31
Global Primary Clock Nets .................................31
Secondary Clock and Control Nets ....................31
Secondary Edge Clock Nets and
Fast Edge Clock Nets ...................................31
Cycle Stealing ....................................................32
Programmable Input/Output Cells (PIC) .................. 32
Programmable I/O ..............................................32
Inputs .................................................................35
Outputs ..............................................................36
I/O Banks and Groups ....................................... 37
Special Function Blocks .......................................... 39
Single Function Blocks .......................................47
Microprocessor Interface (MPI) ............................... 49
Embedded System Bus (ESB) ...........................49
Phase-Locked Loops (PLLs) ................................... 53
FPGA States of Operation ....................................... 56
Initialization ........................................................56
Power Supply Sequencing .................................57
Configuration ......................................................57
Start-Up ..............................................................57
Reconfiguration ..................................................61
Partial Reconfiguration .......................................61
Other Configuration Options ..............................61
Configuration Data Format .................................61
Using ispLEVER to Generate
FPGA Configuration Modes ..................................... 64
Master Parallel Mode .........................................65
Master Serial Mode ............................................66
Asynchronous Peripheral Mode .........................67
Microprocessor Interface Mode ..........................68
Slave Serial Mode ..............................................72
Slave Parallel Mode ...........................................72
Daisy-Chaining ...................................................73
Daisy-Chaining with Boundary-Scan ..................74
Absolute Maximum Ratings ..................................... 75
Recommended Operating Conditions ................75
Electrical Characteristics ......................................... 76
Power Estimation ..................................................... 77
Estimating Power Dissipation .................................. 77
Timing Characteristics ............................................. 78
Configuration Timing ..........................................92
Readback Timing ............................................ 100
Pin Information ...................................................... 101
Pin Descriptions .............................................. 101
Package Compatibility ..................................... 105
352-Pin PBGA Pinout ...................................... 107
416-Pin BGAM Pinout ..................................... 116
680-Pin PBGAM Pinout ................................... 126
Package Thermal Characteristics Summary ......... 142
ΘJA ................................................................. 142
ψJC ................................................................. 142
ΘJC ................................................................. 143
ΘJB ................................................................. 143
Package Thermal Characteristics .......................... 144
Package Coplanarity ............................................. 144
Heat Sink Vendors for BGA Packages .................. 144
Package Parasitics ................................................ 145
Package Outline Diagrams .................................... 146
Terms and Definitions ..................................... 146
352-Pin PBGA ................................................. 147
416-Pin PBGAM .............................................. 148
680-Pin PBGAM .............................................. 149
Ordering Information .............................................. 150
Configuration RAM Data ...............................61
Configuration Data Frame ..................................62
Bit Stream Error Checking .................................64
2
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
■ Improved built-in clock management with program-
mable phase-locked loops (PPLLs) provide optimum
clock modification and conditioning for phase, fre-
quency, and duty cycle from 15 MHz up to 420 MHz.
Multiplication of the input frequency up to 64x, and
division of the input frequency down to 1/64x possi-
ble.
Programmable Features (continued)
■ New capability to (de)multiplex I/O signals:
— New double data rate on both input and output at
rates up to 350 MHz (700 MHz effective rate).
— New 2x and 4x downlink and uplink capability per
I/O (i.e., 50 MHz internal to 200 MHz I/O).
■ New 200 MHz embedded quad-port RAM blocks, two
read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be config-
ured as:
— 1-512 x 18 (quad-port, two read/two write) with
optional built in arbitration.
— 1-256 x 36 (dual-port, one read/one write).
— 1-1K x 9 (dual-port, one read/one write).
— 2-512 x 9 (dual-port, one read/one write for each).
— 2 RAMS with arbitrary number of words whose
sum is 512 or less by 18 (dual-port, one read/one
write).
— Supports joining of RAM blocks.
— Two 16 x 8-bit content addressable memory
(CAM) support.
— FIFO 512 x 18, 256 x 36, 1K x 9 or dual 512 x 9.
— Constant multiply (8 x 16 or 16 x 8).
— Dual-variable multiply (8 x 8).
■ Enhanced twin-quad programmable function unit
(PFU):
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each
LUT and organized to allow two nibbles to act
independently, plus one extra for arithmetic opera-
tions.
— New register control in each PFU has two inde-
pendent programmable clocks, clock enables,
local set/reset, and data selects.
— New LUT structure allows flexible combinations of
LUT4, LUT5, new LUT6, 4 to 1 MUX, new
8 to 1 MUX, and ripple mode arithmetic functions
in the same PFU.
— 32 x 4 RAM per PFU, configurable as single- or
dual-port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Soft-wired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU
through fast internal routing which reduces routing
congestion and improves speed.
— Flexible fast access to PFU inputs from routing.
— Fast-carry logic and routing to all four adjacent
PFUs for nibble-, byte-wide, or longer arithmetic
functions, with the option to register the PFU
carry-out.
■ Embedded 32-bit internal system bus plus 4-bit par-
ity interconnects FPGA logic, microprocessor inter-
face (MPI), embedded RAM blocks, and embedded
standard cell blocks with 100 MHz bus performance.
Included are built-in system registers that act as the
control and status center for the device.
■ Built-in testability:
— Full boundary scan (IEEE ®1149.1 and Draft
1149.2 joint test access group (JTAG)).
— Programming and readback through boundary
scan port compliant to IEEE Draft 1532:D1.7.
— TS_ALL testability function to 3-state all I/O pins.
— New temperature sensing diode.
■ Abundant high-speed buffered and nonbuffered rout-
ing resources provide 2x average speed improve-
ments over previous architectures.
■ Hierarchical routing optimized for both local and glo-
bal routing with dedicated routing resources. This
results in faster routing times with predictable and
efficient performance.
■ New cycle stealing capability allows a typical 15% to
40% internal speed improvement after final place
and route. This feature also enables compliance with
many setup/hold and clock-to-out I/O specifications
and may provide reduced ground bounce for output
buses by allowing flexible delays of switching output
buffers.
■ SLIC provides eight 3-statable buffers, up to 10-bit
decoder, and PAL™-like and-or-invert (AOI) in each
programmable logic cell.
Lattice Semiconductor
3
Data Sheet
May, 2006
ORCA Series 4 FPGAs
■ New double-data rate (DDR) and zero-bus turn-
around (ZBT) memory interfaces support the latest
high-speed memory interfaces.
System Features
■ PCI local bus compliant.
®
■ New 2x/4x uplink and downlink I/O capabilities inter-
face high-speed external I/Os to reduced speed
internal logic.
■ Improved PowerPC /PowerQUICC MPC860 and
PowerPC II MPC8260 high-speed synchronous
microprocessor interface can be used for configura-
tion, readback, device control, and device status, as
well as for a general-purpose interface to the FPGA
logic, RAMs, and embedded standard cell blocks.
Glueless interface to synchronous PowerPC proces-
sors with user-configurable address space provided.
■ Meets universal test and operations PHY interface
for ATM (UTOPIA) Levels 1, 2, and 3. Also meets
proposed specifications for UTOPIA level 4, POS-
PHY Level 3 (2.5 Gbits/s), and POS-PHY 4 (10
Gbits/s) interface standards for packet-over-SONET
as defined by the Saturn Group.
■ New embedded AMBA™ specification 2.0 AHB sys-
tem bus (ARM ™ processor) facilitates communica-
tion among the microprocessor interface,
configuration logic, embedded block RAM, FPGA
logic, and embedded standard cell blocks.
■ ispLEVER development system software. Supported
by industry-standard CAE tools for design entry, syn-
thesis, simulation, and timing analysis.
■ New network PLLs meet ITU-T G.811 specifications
and provide clock conditioning for DS-1/E-1 and
STS-3/STM-1 applications.
■ Variable size bused readback of configuration data
capability with the built-in microprocessor interface
and system bus.
■ Internal, 3-state, bidirectional buses with simple con-
trol provided by the SLIC.
■ New clock routing structures for global and local
clocking significantly increases speed and reduces
skew (<200 ps for OR4E04).
■ New local clock routing structures allow creation of
localized clock trees.
■ Two new edge clock routing structures allow up to six
high-speed clocks on each edge of the device for
improved setup/hold and clock to out performance.
4
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
provide the global routing and clocking elements. Each
PLC contains a PFU, SLIC, local routing resources,
and configuration RAM. Most of the FPGA logic is per-
formed in the PFU, but decoders, PAL-like functions,
and 3-state buffering can be performed in the SLIC.
The PIOs provide device inputs and outputs and can
be used to register signals and to perform input demul-
tiplexing, output multiplexing, uplink and downlink func-
tions, and other functions on two output signals.
Product Description
Architecture Overview
The ORCA Series 4 architecture is a new generation of
SRAM-based programmable devices from Lattice. It
includes enhancements and innovations geared toward
today’s high-speed systems on a single chip. Designed
with networking applications in mind, the Series 4 fam-
ily incorporates system-level features that can further
reduce logic requirements and increase system speed.
ORCA Series 4 devices contain many new patented
enhancements and are offered in a variety of pack-
ages, and speed grades.
The Series 4 architecture integrates macrocell blocks
of memory known as EBR. The blocks run horizontally
across the PLC array and provide flexible memory
functionality. Large blocks of 512x18 quad-port RAM
compliment the existing distributed PFU memory. The
RAM blocks can be used to implement RAM, ROM,
FIFO, multiplier, and CAM, typically without the use of
PFUs for implementation.
The hierarchical architecture of the logic, clocks, rout-
ing, RAM and system level blocks create a seamless
merge of FPGA and ASIC designs. Modular hardware
and software technologies enable system-on-chip inte-
gration with True Plug and Play design implementation.
System-level functions such as a microprocessor inter-
face, PLLs, embedded system bus elements (located in
the corners of the array), the routing resources, and
configuration RAM are also integrated elements of the
architecture.
The architecture consists of four basic elements: pro-
grammable logic cells (PLCs), programmable input/out-
put cells (PIOs), embedded block RAMs (EBRs), and
system-level features. A high-level block diagram is
shown in Figure 1. These elements are interconnected
with a rich routing fabric of both global and local wires.
An array of PLCs and its associated resources are sur-
rounded by common interface blocks (CIBs) which pro-
vide an abundant interface to the adjacent PIOs or
system blocks. Routing congestion around these criti-
cal blocks is eliminated by the use of the same routing
fabric implemented within the programmable logic core.
PICS provide the logical interface to the PIOs which
provide the boundary interface off and onto the device.
Also the interquad routing blocks
For Series 4 FPSCs, all PIO buffers and logic are
replaced by the embedded logic core on the side of the
device. The four PLLs on the right side of the device
(two in the upper right corner and two in the lower right
corner) are removed and the embedded system bus
extends into the FPSC section.
(hIQ, vIQ) separate the quadrants of the PLC array and
Lattice Semiconductor
5
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Product Description (continued)
EMBEDDED
BLOCK RAM
HIGH-SPEED I/Os
EMBEDDED
MICROPROCESSOR
INTERFACE (MPI)
REPLACED BY
EMBEDDED IP
CORE FOR FPSCs
SYSTEM BUS
CLOCK PINS
(ALL 4 SIDES)
PFU
SLIC
PLC
PIO
FPGA/SYSTEM
BUS INTERFACE
PLLs
(ALL 4
CORNERS)
Note: For FPSCs, all I/Os and the four PLLs on the right side of the device are replaced with the embedded core.
5-7536(F)a
Figure 1. Series 4 Top Level Diagram
Programmable Logic Cells
The PLCs are arranged in an array of rows and columns. The location of a PLC is indicated by its row and column
so that a PLC in the second row and the third column is R2C3. The array of actual PLCs for every device begins
with R3C2 in all Series 4 generic FPGAs. PIOs are located on all four sides of the FPGA. Every group of four PIOs
on the device edge have an associated PIC.
The PLC consists of a PFU, SLIC, and routing resources. Each PFU within a PLC contains eight
4-input (16-bit) LUTs, eight latches/FFs, and one additional FF that may be used independently or with arithmetic
functions.The PFU is the main logic element of the PLC, containing elements for both combinatorial and sequential
logic. Combinatorial logic is done in LUTs located in the PFU. The PFU can be used in different modes to meet dif-
ferent logic requirements. The LUTs twin-quad architecture provides a configurable medium-/large-grain architec-
ture that can be used to implement from one to eight independent combinatorial logic functions or a large number
of complex logic functions using multiple LUTs. The flexibility of the LUT to handle wide input functions, as well as
multiple smaller input functions, maximizes the gate count per PFU while increasing system speed.
The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently.
Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects.
LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit
modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be con-
figured as a synchronous 32x4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT
outputs or directly from invertible PFU inputs, or they can be tied high or tied low.The FFs also have programmable
clock polarity, clock enables, and local set/reset.
6
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Figure 2 and Figure 3 show high-level and detailed
views of the ports in the PFU, respectively. The eight
sets of LUT inputs are labeled as K0 through K7 with
each of the four inputs to each LUT having a suffix
of _x, where x is a number from 0 to 3.
Programmable Logic Cells (continued)
The LUTs can be programmed to operate in one of
three modes: combinatorial, ripple, or memory. In com-
binatorial mode, the LUTs can realize any 4-, 5-, or
6-input logic function and many multilevel logic func-
tions using ORCA’s SWL connections. In ripple mode,
the high-speed carry logic is used for arithmetic func-
tions, comparator functions, or enhanced data path
functions. In memory mode, the LUTs can be used as a
32x4 synchronous read/write or ROM, in either single-
or dual-port mode.
There are four F5 inputs labeled A through D. These
are used for additional LUT inputs for 5- and 6-input
LUTs or as a selector for multiplexing two 4-input LUTs.
Four adjacent LUT4s can also be multiplexed together
with a 4 to 1 MUX to create a 6-input LUT. The eight
direct data inputs to the latches/FFs are labeled as
DIN[7:0]. Registered LUT outputs are shown as Q[7:0],
and combinatorial LUT outputs are labeled as F[7:0].
The SLIC is connected from PLC routing resources
and from the outputs of the PFU. It contains eight
3-state, bidirectional buffers and logic to perform up to
a 10-bit AND function for decoding, or an AND-OR with
optional INVERT to perform PAL-like functions. The
3-state drivers in the SLIC and their direct connections
from the PFU outputs make fast, True 3-state buses
possible within the FPGA.
The PFU implements combinatorial logic in the LUTs
and sequential logic in the latches/FFs. The LUTs are
static random access memory (SRAM) and can be
used for read/write or ROM.
Each latch/FF can accept data from its associated LUT.
Alternatively, the latches/FFs can accept direct data
from DIN[7:0], eliminating the LUT delay if no combina-
torial function is needed. Additionally, the CIN input can
be used as a direct data source for the ninth FF. The
LUT outputs can bypass the latches/FFs, which
Programmable Function Unit
reduces the delay out of the PFU. It is possible to use
the LUTs and latches/FFs more or less independently,
allowing, for instance, a comparator function in the
LUTs simultaneously with a shift register in the FFs.
The PFUs are used for logic. Each PFU has 53 exter-
nal inputs and 20 outputs and can operate in several
modes. The functionality of the inputs and outputs
depends on the operating mode.
The PFU uses 36 data input lines for the LUTs, eight
data input lines for the latches/FFs, eight control inputs
(CLK[1:0], CE[1:0], LSR[1:0], SEL[1:0]), and a carry
input (CIN) for fast arithmetic functions and general-
purpose data input for the ninth FF. There are eight
combinatorial data outputs (one from each LUT), eight
latched/registered outputs (one from each latch/FF), a
carry-out (COUT), and a registered carry-out (REG-
COUT) that comes from the ninth FF. The carry-out sig-
nals are used principally for fast arithmetic functions.
There are also two dedicated F6 mode outputs which
are for the 6-input LUT function and 8 to 1 MUX.
Lattice Semiconductor
7
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
F5D
K7_0
K7_1
K7_2
K7_3
K6_0
K6_1
K6_2
K6_3
K5_0
K5_1
K5_2
K5_3
LUT603
LUT647
K4_0
K4_1
K4_2
K4_3
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
F5C
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN0
PROGRAMMABLE
FUNCTION UNIT
(PFU)
COUT
REGCOUT
CIN
F5B
F7
F6
F5
F4
F3
F2
F1
F0
K3_0
K3_1
K3_2
K3_3
K2_0
K2_1
K2_2
K2_3
K1_0
K1_1
K1_2
K1_3
K0_0
K0_1
K0_2
K0_3
F5A
LSR[0:1]
CLK[0:1]
CE[0:1]
SEL[0:1]
5-5752(F)a
Figure 2. PFU Ports
The PFU can be configured to operate in four modes: logic mode, half-logic mode, ripple mode, and memory
(RAM/ROM) mode. In addition, ripple mode has four submodes and RAM mode can be used in either a single- or
dual-port memory fashion. These submodes of operation are discussed in the following sections.
8
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
FSDMUX
F7
AMUX
F5D
0
REG7
Q7
DIN7
K7_0
D0
D1
SD
SP
CK
LSR
K7_0MUX
K7
K6
0
A
B
C
D
A
B
C
D
RESET
K7_1
K7_2
DEL0
DIN7MUX
SET
DEL1
K7_2MUX
K6_0MUX
K6_2MUX
DEL2
DEL3 F6
H7H6MUX
K7_3
K6_0
REG6
Q6
LUT6MUX
DIN6
D0
D1
SD
SP
CK
LSR
K6_1
K6_2
0
RESET
SET
DEL0
DEL1
DEL2
DEL3
F5
DIN6MUX
K6_3
LUT647
K5_0
K5_1
K5_2
K5_3
K5
K4
A
B
C
D
REG5
Q5
DIN5
DIN4
D0
D1
SD
SP
CK
LSR
0
RESET
SET
DEL0
DEL1
DEL2
K4_0
K4_1
K4_2
K4_3
H5H4MUX
DIN5MUX
A
B
C
D
F4
DEL3
FSCMUX
REG4
F5C
Q4
0
D0
D1
SD
SP
CK
LSR
0
RESET
SET
DEL0
DEL1
DEL2
DEL3
CLK1MUX
DIN4MUX
CLK1
SR1MODEATTR
SR1MODE
0
0
1
CE1_OVER_LSR1
LSR1_OVER_CE1
RSYNC1
SEL1MUX
CE1MUX
SEL1
CE1
REGMODE_TOP
FF
REG 4 THROUGH 7
CE47MUX
LATCH
1
0
LSR47MUX
LSR1MUX
CINMUX
LSR1
0
0
0
CIN
COUT
CLK0MUX
CLK0
SEL0
CE0
SEL0MUX
CE0MUX
THIS IS ALWAYS A FLIPFLOP
0
1
CEBMUX
1
0
CE03MUX
LSRBMUX
LSR03MUX
REG8
RECCOUT
SR0MODEATTR
SR0MODE
D0
SP
CK
LSR
RESET
SET
DEL0
DEL1
DEL2
DEL3
1
0
CE0_OVER_LSR0
LSR0_OVER_CE0
ASYNC0
LSR0MUX
LSR0
0
FSBMUX
F3
BMUX
F5B
0
REG3
Q3
DIN3
K3_0
D0
D1
SD
SP
CK
LSR
K3_0MUX
K3
A
0
RESET
SET
K3_1
K3_2
DEL0
DIN3MUX
B
DEL1
K3_2MUX
DEL2
DEL3 F2
C
H3H2MUX
K3_3
K2_0
D
K2_0MUX
REG2
K2
A
Q2
LUT6MUX
DIN2
D0
D1
SD
SP
CK
LSR
K2_1
K2_2
0
B
RESET
SET
DEL0
DEL1
DEL2
DEL3
F1
K2_2MUX
DIN2MUX
C
K2_3
D
LUT603
K1_0
K1_1
K1_2
K1_3
K1
K0
A
B
C
D
REG1
Q1
DIN1
DIN0
D0
D1
SD
SP
CK
LSR
0
K0_0
K0_1
K0_2
RESET
SET
DEL0
DEL1
DEL2
H1H0MUX
DIN1MUX
A
B
C
D
K0_3
DEL3
F0
F5AMUX
F5A
REG0
Q0
D0
D1
SD
SP
CK
LSR
0
0
RESET
SET
DEL0
DEL1
DEL2
DEL3
DIN0MUX
LOGIC
MLOGIC
RIPPLE
RAM
GSR
ENABLED
DISABLED
REGMODE_BOT
ROM
FF
REG 0 THROUGH 3
LATCH
PFU MODES
5-9714(F)
Note: All multiplexers without select inputs are configuration selector multiplexers.
Figure 3. Simplified PFU Diagram
Lattice Semiconductor
9
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
Look-Up Table Operating Modes
The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam-
ple, in some operating modes, the DIN[7:0] inputs are direct data inputs to the PFU latches/FFs. In memory mode,
the same DIN[7:0] inputs are used as a 4-bit write data input bus and a 4-bit write address input bus into LUT
memory.
Table 2 lists the basic operating modes of the LUT. Figure 4—Figure 7 show block diagrams of the LUT operating
modes. The accompanying descriptions demonstrate each mode’s use for generating logic.
Table 2. Look-Up Table Operating Modes
Mode
Function
Logic
4-, 5-, and 6-input LUTs; softwired LUTs; latches/FFs with direct input or LUT input; CIN as direct
input to ninth FF or as pass through to COUT.
Half Logic/ Upper four LUTs and latches/FFs in logic mode; lower four LUTs and latches/FFs in ripple mode;
Half Ripple CIN and ninth FF for logic or ripple functions.
Ripple
All LUTs combined to perform ripple-through data functions. Eight LUT registers available for
direct-in use or to register ripple output. Ninth FF dedicated to ripple out, if used. The submodes of
ripple mode are adder/subtractor, counter, multiplier, and comparator.
Memory All LUTs and latches/FFs used to create a 32x4 synchronous dual-port RAM. Can be used as
single-port or as ROM.
PFU Control Inputs
Each PFU has eight routable control inputs and an active-low, asynchronous global set/reset (GSRN) signal that
affects all latches and FFs in the device. The eight control inputs are CLK[1:0], LSR[1:0], CE[1:0], and SEL[1:0],
and their functionality for each logic mode of the PFU is shown in Table 3. The clock signal to the PFU is CLK, CE
stands for clock enable, which is its primary function. LSR is the local set/reset signal that can be configured as
synchronous or asynchronous. The selection of set or reset is made for each latch/FF and is not a function of the
signal itself. SEL is used to dynamically select between direct PFU input and LUT output data as the input to
the latches/FFs.
All of the control signals can be disabled and/or inverted via the configuration logic. A disabled clock enable
indicates that the clock is always enabled. A disabled LSR indicates that the latch/FF never sets/resets (except
from GSRN). A disabled SEL input indicates that DIN[7:0] PFU inputs are routed to the latches/FFs.
Table 3. Control Input Functionality
Mode
CLK[1:0]
LSR[1:0]
CE[1:0]
SEL[1:0]
Logic
CLK to all latches/
FFs
LSR to all latches/FFs, CE to all latches/FFs,
enabled per nibble and selectable per nibble
Select between LUT
input and direct input for
eight latches/FFs
for ninth FF
and for ninth FF
Half Logic/ CLK to all latches/
Half Ripple FFs
LSR to all latches/FF,
enabled per nibble and selectable per nibble
for ninth FF and for ninth FF
CE to all latches/FFs,
Select between LUT
input and direct input for
eight latches/FFs
Ripple
CLK to all latches/
FFs
LSR to all latches/FFs, CE to all latches/FFs,
enabled per nibble and selectable per nibble
Select between LUT
input and direct input for
eight latches/FFs
for ninth FF
and for ninth FF
Memory CLK to RAM
(RAM)
LSR0 Port enable 2
CE1 RAM write enable Not used
CE0 Port enable 1
Memory Optional for
Not used
Not used
Not used
(ROM)
synchronous outputs
10
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
K7_0
K7_1
K7_2
K7_3
K7
K6
K5
K4
K3
K2
K1
K0
F7
F6
F5
F4
F3
F2
F1
F0
LUT4
LUT4
Logic Mode
F5D
The PFU diagram of Figure 3 represents the logic
mode of operation. In logic mode, the eight LUTs are
used individually or in flexible groups to implement user
logic functions. The latches/FFs may be used in con-
junction with the LUTs or separately with the direct
PFU data inputs. There are three basic submodes of
LUT operation in PFU logic mode: F4 mode, F5 mode,
and the F6 mode. Combinations of the submodes are
possible in each PFU.
K6_0
K6_1
K6_2
K6_3
2x1
MUX
F6
F4
F2
K5_0
K5_1
K5_2
K5_3
LUT4
LUT4
F5C
K4_0
K4_1
K4_2
K4_3
2x1
MUX
F4 mode, shown simplified in Figure 4, illustrates the
uses of the basic 4-input LUTs in the PFU. The output
of an F4 LUT can be passed out of the PFU, captured
at the LUTs associated latch/FF, or multiplexed with the
adjacent F4 LUT output using one of the F5[A:D] inputs
to the PFU. Only adjacent LUT pairs (K0 and K1, K2
and K3, K4 and K5, K6 and K7) can be multiplexed, and
the output always goes to the even-numbered output of
the pair.
K3_0
K3_1
K3_2
K3_3
LUT4
LUT4
F5B
K2_0
K2_1
K2_2
K2_3
2x1
MUX
The F5 submode of the LUT operation, shown simpli-
fied in Figure 4, indicates the use of 5-input LUTs to
implement logic. 5-input LUTs are created from two
4-input LUTs and a multiplexer. The F5 LUT is the
same as the multiplexing of two F4 LUTs described
previously with the constraint that the inputs to the F4
LUTs be the same. The F5[A:D] input is then used as
the fifth LUT input. The equations for the two F4 LUTs
will differ by the assumed value for the F5[A:D] input,
one F4 LUT assuming that the F5[A:D] input is zero,
and the other assuming it is a one. The selection of the
appropriate F4 LUT output in the F5 MUX by the
F5[A:D] signal creates a 5-input LUT. Any combination
of F4 and F5 LUTs is allowed per PFU using the eight
16-bit LUTs. Examples are eight F4 LUTs, four F5
LUTs, and a combination of four F4 plus two F5 LUTs.
K1_0
K1_1
K1_2
K1_3
LUT4
LUT4
F5A
K0_0
K0_1
K0_2
K0_3
2x1
MUX
F0
5-9733(F)
Figure 4. Simplified F4 and F5 Logic Modes
Two 6-input LUTs are created by shorting together the
input of four 4-input LUTs (K0:3 and K4:7) which are
multiplexed together. The F5 inputs of the adjacent F4
LUTs derive the fifth and sixth inputs of the F6 mode.
The F6 outputs, LUT603 and LUT647, are dedicated to
the F6 mode or can be used as the outputs of
MUX8x1. MUX8x1 modes are created by programming
adjacent 4-input LUTs to 2x1 MUXs and multiplexing
down to create MUX8x1. Both F6 mode and MUX8x1
are available in the upper and lower PFU nibbles.
Lattice Semiconductor
11
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
K7_0
K7_1
K7_2
LUT4
LUT4
K7_0
K7_1
K7_2
F5D
LUT4
K6_0
K6_1
K6_2
2x1
MUX
F4
F3
F2
F0
K7_3
F5D
K6_0
K6_1
K6_2
LUT4
K6_3
K5_0
K5_1
K5_2
4x1
MUX
LUT4
LUT4
K5_0
K5_1
K5_2
K5_3
LUT647
LUT4
LUT4
F5C
K4_0
K4_1
K4_2
F5C
2x1
MUX
K4_0
K4_1
K4_2
K4_3
K3_0
K3_1
K3_2
LUT4
LUT4
K3_0
K3_1
K3_2
K3_3
LUT4
LUT4
LUT4
LUT4
F5B
K2_0
K2_1
K2_2
F5B
2x1
MUX
K2_0
K2_1
K2_2
K2_3
4x1
MUX
K1_0
K1_1
K1_2
K1_3
LUT603
K1_0
K1_1
K1_2
LUT4
LUT4
F5A
F5A
K0_0
K0_1
K0_2
K0_3
K0_0
K0_1
K0_2
2x1
MUX
5-9734(F)a
5-9735(F)
Figure 5. Simplified F6 Logic Modes
Figure 6. MUX 4x1
12
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
K7_0
K7_1
K7_2
LUT4
LUT4
LUT4
F5D
K6_0
K6_1
K6_2
4x1
MUX
MUX8x1
[LUT647]
K5_0
K5_1
K5_2
F5C
K4_0
K4_1
K4_2
LUT4
K3_0
K3_1
K3_2
LUT4
LUT4
LUT4
F5B
K2_0
K2_1
K2_2
4x1
MUX
MUX8x1
[LUT603]
K1_0
K1_1
K1_2
F5A
K0_0
K0_1
K0_2
LUT4
5-9736(F)a
Figure 7. MUX 8x1
Softwired LUT submode uses F4, F5 and F6 LUTs and internal PFU feedback routing to generate complex logic
functions up to three LUT-levels deep. Multiplexers can be independently configured to route certain LUT outputs to
the input of other LUTs. In this manner, very complex logic functions, some of up to 22 inputs, can be implemented
in a single PFU at greatly enhanced speeds.
It is important to note that an LUT output that is fed back for softwired use is still available to be registered or output
from the PFU. This means, for instance, that a logic equation that is needed by itself and as a term in a larger equa-
tion need only be generated once, and PLC routing resources will not be required to use it in the larger equation.
Lattice Semiconductor
13
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
F4
F4
F4
F4
F4
F4
F4
F4
F5
F5
F5
F5
FOUR 7-INPUT FUNCTIONS IN ONE PFU
F5
TWO 9-INPUT FUNCTIONS IN ONE PFU
F4
F4
F4
F4
F5
F5
F5
F5
F5
ONE 17-INPUT FUNCTION IN ONE PFU
ONE 21-INPUT FUNCTION IN ONE PFU
5-5753(F)
F4
F4
F4
F4
F4
F4
F4
F4
3
TWO 10-INPUT FUNCTIONS IN ONE PFU
F4
ONE OF TWO 21-INPUT FUNCTIONS IN ONE PFU
F4
F4
F4
F5
F6
ONE 22-INPUT FUNCTION IN ONE PFU
6-INPUT LUT
F4 4-INPUT LUT
F5 5-INPUT LUT
F6
5-5754(F)
Figure 8. Softwired LUT Topology Examples
14
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
ripple operation (K7, F[7:0]) and half-logic ripple
Programmable Logic Cells (continued)
operation (K3, F[3:0]), respectively. The ripple mode
diagram (Figure 9) shows full PFU ripple operation,
with half-logic ripple connections shown as dashed
lines.
Half-Logic Mode
Series 4 FPGAs are based upon a twin-quad architec-
ture in the PFUs. The byte-wide nature (eight LUTs,
eight latches/FFs) may just as easily be viewed as two
nibbles (two sets of four LUTs, four latches/FFs). The
two nibbles of the PFU are organized so that any nib-
ble-wide feature (excluding some softwired LUT topolo-
gies) can be swapped with any other nibble-wide
feature in another PFU. This provides for very flexible
use of logic and for extremely flexible routing. The half-
logic mode of the PFU takes advantage of the twin-
quad architecture and allows half of a PFU, K[7:4] and
associated latches/FFs, to be used in logic mode while
the other half of the PFU, K[3:0] and associated
The result output and ripple output are calculated by
using generate/propagate circuitry. In ripple mode, the
two operands are input into KZ[1] and KZ[0] of each
LUT.The result bits, one per LUT, are F[7:0]/F[3:0] (see
Figure 9). The ripple output from LUT K7/K3 can be
routed on dedicated carry circuitry into any of four adja-
cent PLCs, and it can be placed on the PFU COUT/
FCOUT outputs. This allows the PLCs to be cascaded
in the ripple mode so that nibble-wide ripple functions
can be expanded easily to any length.
Result outputs and the carry-out may optionally be reg-
istered within the PFU. The capability to register the
ripple results, including the carry output, provides for
improved counter performance and simplified pipelin-
ing in arithmetic functions.
latches/FFs, is used in ripple mode. In half-logic mode,
the ninth FF may be used as a general-purpose FF or
as a register in the ripple mode carry chain.
Ripple Mode
REGOUT
D
Q
The PFU LUTs can be combined to do byte-wide ripple
functions with high-speed carry logic. Each LUT has a
dedicated carry-out net to route the carry to/from any
adjacent LUT. Using the internal carry circuits, fast
arithmetic, counter, and comparison functions can be
implemented in one PFU. Similarly, each PFU has
carry-in (CIN, FCIN) and carry-out (COUT, FCOUT)
ports for fast-carry routing between adjacent PFUs.
C
C
FCOUT
COUT
F7
K7[1]
K7[0]
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
K7
K6
K5
K4
K3
K2
K1
K0
Q7
F6
K6[1]
K6[0]
The ripple mode is generally used in operations on two
data buses. A single PFU can support an 8-bit ripple
function. Data buses of 4 bits and less can use the
nibble-wide ripple chain that is available in half-logic
mode. This nibble-wide ripple chain is also useful for
longer ripple chains where the length modulo 8 is four
or less. For example, a 12-bit adder (12 modulo 8 = 4)
can be implemented in one PFU in ripple mode (8 bits)
and one PFU in half-logic mode (4 bits), freeing half of
a PFU for general logic mode functions.
Q6
F5
K5[1]
K5[0]
Q5
F4
K4[1]
K4[0]
Q4
F3
K3[1]
K3[0]
Q3
F2
Each LUT has two operands and a ripple (generally
carry) input, and provides a result and ripple (generally
carry) output. A single bit is rippled from the previous
LUT and is used as input into the current LUT. For LUT
K0, the ripple input is from the PFU CIN or FCIN port.
The CIN/FCIN data can come from either the fast-carry
routing (FCIN) or the PFU input (CIN), or it can be tied
to logic 1 or logic 0.
K2[1]
K2[0]
Q2
F1
K1[1]
K1[0]
Q1
F0
K0[1]
K0[0]
Q0
CIN/FCIN
In the following discussions, the notations LUT K7/K3
and F[7:0]/F[3:0] are used to denote the LUT that pro-
vides the carry-out and the data outputs for full PFU
5-5755(F).
Figure 9. Ripple Mode
Lattice Semiconductor
15
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
REGCOUT
D
Q
C
C
The ripple mode can be used in one of four submodes.
The first of these is adder-subtractor submode. In
this submode, each LUT generates three separate out-
puts. One of the three outputs selects whether the
carry-in is to be propagated to the carry-out of the cur-
rent LUT or if the carry-out needs to be generated. If
the carry-out needs to be generated, this is provided by
the second LUT output. The result of this selection is
placed on the carry-out signal, which is connected to
the next LUT carry-in or the COUT/FCOUT signal, if it
is the last LUT (K7/K3). Both of these outputs can be
any equation created from KZ[1] and KZ[0], but in this
case, they have been set to the propagate and gener-
ate functions.
FCOUT
COUT
F7
K7[0]
K6[0]
K5[0]
K4[0]
K3[0]
K2[0]
K1[0]
K0[0]
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
K7
K6
K5
K4
K3
K2
K1
K0
Q7
F6
Q6
F5
Q5
F4
Q4
F3
The third LUT output creates the result bit for each LUT
output connected to F[7:0]/F[3:0]. If an adder/subtrac-
tor is needed, the control signal to select addition or
subtraction is input on F5A/F5C inputs. These inputs
generate the controller input AS. When AS = 0 this
function performs the adder, A + B. When AS = 1 the
function performs the subtractor, A – B.The result bit is
created in one-half of the LUT from a single bit from
each input bus KZ[1:0], along with the ripple input bit.
Q3
F2
Q2
F1
Q1
F0
Q0
The second submode is the counter submode (see
Figure 10). The present count, which may be initialized
via the PFU DIN inputs to the latches/FFs, is supplied
to input KZ[0], and then output F[7:0]/F[3:0] will either
be incremented by one for an up counter or decre-
mented by one for a down counter. If an up/down
counter is needed, the control signal to select the direc-
tion (up or down) is input on F5A and F5C. When
F5[A:C], respectively per nibble, is a logic 1, this indi-
cates a down counter and a logic 0 indicates an up
counter.
CIN/FCIN
5-5756(F)
Figure 10. Counter Submode
16
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
D
Q
REGCOUT
COUT
In the third submode, multiplier submode, a single
PFU can affect an 8x1 bit (4x1 for half-ripple mode)
multiply and sum with a partial product (see Figure 11).
The multiplier bit is input at F5[A:C], respectively per
nibble, and the multiplicand bits are input at KZ[1],
where K7[1] is the most significant bit (MSB). KZ[0] con-
tains the partial product (or other input to be summed)
from a previous stage. If F5[A:C] is logical 1, the multi-
plicand is added to the partial product. If F5[A:C] is log-
ical 0, 0 is added to the partial product, which is the
same as passing the partial product. CIN/FCIN can
bring the carry-in from the less significant PFUs if the
multiplicand is wider than 8 bits, and COUT/FCOUT
holds any carry-out from the multiplication, which may
then be used as part of the product or routed to another
PFU in multiplier mode for multiplicand width expan-
sion.
C
C
F5[A:C]
K7[1]
F7
1
0
0
0
0
0
0
0
0
0
D
D
D
D
D
D
D
D
+
+
+
+
+
+
+
+
Q7
Q
Q
Q
Q
Q
Q
Q
Q
K7[0]
K6[1]
K7
K6
K5
K4
K3
K2
K1
K0
F6
1
0
Q6
K6[0]
K5[1]
F5
1
0
Q5
K5[0]
K4[1]
F4
1
0
Q4
K4[0]
K3[1]
F3
1
0
Q3
K3[0]
K2[1]
1
0
F2
Ripple mode’s fourth submode features equality
comparators.The functions that are explicitly available
are A ≥ B, A ≠ B, and A ≤ B, where the value for A is
input on KZ[0], and the value for B is input on KZ[1]. A
value of 1 on the carry-out signals valid argument. For
example, a carry-out equal to 1 in AB submode indi-
cates that the value on KZ[0] is greater than or equal to
the value on KZ[1]. Conversely, the functions A ≤ B,
A + B, and A > B are available using the same func-
tions but with a 0 output expected. For example, A > B
with a 0 output indicates A ≤ B. Table 4 shows each
function and the output expected.
Q2
K2[0]
K1[1]
F1
1
0
Q1
K1[0]
K0[1]
F0
1
0
Q0
K0[0]
5-5757(F)
Key: C = configuration data.
Note: F5[A:C] shorted together
If larger than 8 bits, the carry-out signal can be cas-
caded using fast-carry logic to the carry-in of any adja-
cent PFU. The use of this submode could be shown
using Figure 9, except that the CIN/FCIN input for the
least significant PFU is controlled via configuration.
Figure 11. Multiplier Submode
Table 4. Ripple Mode Equality Comparator
Functions and Outputs
Equality
Function
ispLEVER
Submode
True, if
Carry-Out Is:
A ≥ B
A ≤ B
A ≠ B
A < B
A > B
A = B
A ≥ B
A ≤ B
A ≠ B
A ≥ B
A ≤ B
A ≠ B
1
1
1
0
0
0
Lattice Semiconductor
17
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
Memory Mode
The Series 4 PFU can be used to implement a 32x4 (128-bit) synchronous, dual-port RAM). A block diagram of a
PFU in memory mode is shown in Figure 12. This RAM can also be configured to work as a single-port memory
and because initial values can be loaded into the RAM during configuration, it can also be used as a ROM.
F5[A:D]
READ
4
ADDRESS[4:0]
KZ[3:0]
5
WRITE
ADDRESS[4:0]
CIN(WA1)
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
DIN7(WA3)
DIN5(WA2)
DIN3(WA1)
DIN1(WA0)
DIN6(WD3)
DIN4(WD2)
DIN2(WD1)
DIN0(WD0)
F6
F4
F2
F0
D Q
D Q
D Q
D Q
Q6
Q4
Q2
Q0
4
READ
DATA[3:0]
4
WRITE
DATA[3:0]
CE0, LSR0
(SEE NOTE 2.)
WRITE
ENABLE
D Q
S/E
RAM CLOCK
CE1
CLK[0:1]
5-5969(F)a
1. CLK[0:1] are commonly connected in memory mode.
2. CE1 = write enable = wren; wren = 0 (no write enable); wren = 1 (write enabled).
CE0 = write port enable 0; CE0 = 0, wren = 0; CE0 = 1, wren = CE1.
LSR0 = write port enable 1; LSR0 = 0, wren = CE0; LSR0 = 1, wren = CE1.
Figure 12. Memory Mode
18
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Wider memories can be created by operating two or
more memory mode PFUs in parallel, all with the same
address and control signals, but each with a different
nibble of data. To increase memory word depth above
32, two or more PLCs can be used. Figure 12 shows a
128x8 dual-port RAM that is implemented in eight
PLCs. This figure demonstrates data path width expan-
sion by placing two memories in parallel to achieve an
8-bit data path. Depth expansion is applied to achieve
128 words deep using the 32-word deep PFU memo-
ries. In addition to the PFU in each PLC, the SLIC
(described in the next section) in each PLC is used for
read address decodes and 3-state drivers. The 128x8
RAM shown could be made to operate as a single-port
RAM by tying (bit-for-bit) the read and write addresses.
Programmable Logic Cells (continued)
The PFU memory mode uses all LUTs and latches/FFs
including the ninth FF in its implementation as shown in
Figure 12. The read address is input at the KZ[3:0] and
F5[A:D] inputs where KZ[0] is the LSB and F5[A:D] is
the MSB, and the write address is input on CIN (MSB)
and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write
data is input on DIN[6, 4, 2, 0], where DIN[6] is the
MSB, and read data is available combinatorially on
F[6, 4, 2, 0] and registered on Q[6, 4, 2, 0] with F[6] and
Q[6] being the MSB. The write enable controlling ports
are input on CE0, CE1, and LSR0. CE1 is the active-
high write enable (CE1 = 1, RAM is write enabled).The
first write port is enabled by CE0. The second write
port is enabled with LSR0.The PFU CLK (CLK0) signal
is used to synchronously write the data. The polarities
of the clock, write enable, and port enables are all pro-
grammable. Write-port enables may be disabled if they
are not to be used.
To achieve depth expansion, one or two of the write
address bits (generally the MSBs) are routed to the
write port enables as in Figure 12. For 2 bits, the bits
select which 32-word bank of RAM of the four available
from a decode of two WPE inputs is to be written. Simi-
larly, 2 bits of the read address are decoded in the
SLIC and are used to control the 3-state buffers
through which the read data passes.The write data bus
is common, with separate nibbles for width expansion,
across all PLCs, and the read data bus is common
(again, with separate nibbles) to all PLCs at the output
of the 3-state buffers.
Data is written to the write data, write address, and
write enable registers on the active edge of the clock,
but data is not written into the RAM until the next clock
edge one-half cycle later. The read port is actually
asynchronous, providing the user with read data very
quickly after setting the read address, but timing is also
provided so that the read port may be treated as fully
synchronous for write then read applications. If the
read and write address lines are tied together (main-
taining MSB to MSB, etc.), then the dual-port RAM
operates as a synchronous single-port RAM. If the
write enable is disabled, and an initial memory contents
is provided at configuration time, the memory acts as a
ROM (the write data and write address ports and write
port enables are not used).
Figure 13 also shows the capability to provide a read
enable for RAMs/ROMs using the SLIC cell. The read
enable will 3-state the read data bus when inactive,
allowing the write data and read data buses to be tied
together if desired.
Lattice Semiconductor
19
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
8
WD[7:0]
4
4
4
4
PLC
PLC
PLC
PLC
WD[7:4]
WD[3:0]
WD[7:4]
WD[3:0]
WA RA
5
5
5
5
5
5
5
5
WA
RA
WA
RA
WA
RA
WPE 1
WPE 2
WPE 1
WPE 2
WPE 1
WPE 2
WPE 1
WPE 2
WE
WE
WE
WE
RD[7:4]
RD[3:0]
RD[7:4]
RD[3:0]
RE
RE
RE
RE
4
4
4
4
8
RD[7:0]
WE
7
7
WA[6:0]
RA[6:0]
CLK
RE
5-5749(F)
Figure 13. Memory Mode Expansion Example—128x8 RAM
while using the TRI signal to control the 3-state of the
other BIDI nibble. Figure 15 shows the SLIC in buffer
mode with available 3-state control from the TRI and
DEC signals. If the entire SLIC is acting in a buffer
capacity, the DEC output may be used to generate a
constant logic 1 (VHI) or logic 0 (VLO) signal for general
use.
Supplemental Logic and Interconnect Cell
Each PLC contains a SLIC embedded within the PLC
routing, outside of the PFU. As its name indicates, the
SLIC performs both logic and interconnect (routing)
functions. Its main features are 3-statable, bidirectional
buffers, and a PAL-like decoder capability. Figure 14
shows a diagram of a SLIC with all of its features
shown. All modes of the SLIC are not available at one
time.
The SLIC may also be used to generate PAL-like AND-
OR with optional INVERT (AOI) functions or a decoder
of up to 10 bits. Each group of buffers can feed into an
AND gate (4-input AND for the nibble groups and
2-input AND for the other two buffers). These AND
gates then feed into a 3-input gate that can be config-
ured as either an AND gate or an OR gate. The output
of the 3-input gate is invertible and is output at the DEC
output of the SLIC. Figure 19 shows the SLIC in full
decoder mode.
The ten SLIC inputs can be sourced directly from the
PFU or from the general routing fabric. SI[0:9] inputs
can come from the horizontal or vertical routing and
I[0:9} comes from the PFU outputs O[9:0].These inputs
can also be tied to a logical 1 or 0 constant. The inputs
are twin-quad in nature and are segregated into two
groups of four nibbles and a third group of two inputs
for control. Each input nibble groups also have
The functionality of the SLIC is parsed by the two nib-
ble-wide groups and the 2-bit buffer group. Each of
these groups may operate independently as BIDI buff-
ers (with or without 3-state capability for the nibble-
wide groups) or as a PAL/decoder.
3-state capability, however the third pair does not.
There is one 3-state control (TRI) for each SLIC, with
the capability to invert or disable the 3-state control for
each group of four BIDIs. Separate 3-state control for
each nibble-wide group is achievable by using the
SLICs decoder (DEC) output, driven by the group of
two BIDIs, to control the 3-state of one BIDI nibble
20
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
SIN9
I9
SOUT09
SOUT08
As discussed in the memory mode section, if the SLIC
is placed into one of the modes where it contains both
buffers and a decode or AOI function (e.g.,
LOGIC 1 OR 0
SIN8
I8
BUF_BUF_DEC mode), the DEC output can be gated
with the 3-state input signal. This allows up to a 6-input
decode (e.g., BUF_DEC_DEC mode) plus the 3-state
input to control the enable/disable of up to four buffers
per SLIC Figure 15—Figure 19 show several configura-
tions of the SLIC, while Table 5 shows all of the possi-
ble modes.
LOGIC 1 OR 0
SIN7
I7
SOUT07
LOGIC 1 OR 0
SIN6
I6
SOUT06
SOUT05
LOGIC 1 OR 0
Table 5. SLIC Modes
SIN5
I5
Mode
No.
Mode
BUF
[3:0]
BUF
[7:4]
BUF
[9:8]
LOGIC 1 OR 0
DEC
SIN4
I4
SOUT04
1
2
3
4
5
6
7
8
BUFFER
Buffer
Buffer
Buffer
LOGIC 1 OR 0
TRI
BUF_BUF_DEC Buffer
Buffer Decoder
BUF_DEC_BUF Buffer Decoder Buffer
BUF_DEC_DEC Buffer Decoder Decoder
0/1
0/1
DEC
DEC_BUF_BUF Decoder Buffer
Buffer
DEC_BUF_DEC Decoder Buffer Decoder
DEC_DEC_BUF Decoder Decoder Buffer
0/1
0/1
DECODER
Decoder Decoder Decoder
SIN3
I3
SOUT03
SOUT02
LOGIC 1 OR 0
SIN2
I2
LOGIC 1 OR 0
SIN1
I1
SOUT01
LOGIC 1 OR 0
SIN0
I0
SOUT00
LOGIC 1 OR 0
5-5744(F).a.
Figure 14. SLIC All Modes Diagram
Lattice Semiconductor
21
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
SIN9
I9
SIN9
LOGIC 1 OR 0
SOUT09
I9
SIN8
I8
LOGIC 1 OR 0
SIN8
LOGIC 1 OR 0
SOUT08
I8
LOGIC 1 OR 0
SIN7
I7
SOUT07
SOUT06
SOUT05
SOUT04
SIN7
SOUT07
I7
LOGIC 1 OR 0
LOGIC 1 OR 0
SIN6
SIN6
I6
SOUT06
I6
LOGIC 1 OR 0
LOGIC 1 OR 0
SIN5
SIN5
I5
SOUT05
I5
LOGIC 1 OR 0
LOGIC 1 OR 0
SIN4
SIN4
I4
SOUT04
I4
LOGIC 1 OR 0
LOGIC 1 OR 0
1
DEC
TRI
0/1
TRI
1
1
1
1
DEC
0
THIS CAN BE USED TO GENERATE
A VHI OR VLO
0/1
SIN3
I3
SOUT03
SOUT02
SOUT01
SOUT00
SIN3
SOUT03
I3
LOGIC 1 OR 0
LOGIC 1 OR 0
SIN2
SIN2
I2
SOUT02
I2
LOGIC 1 OR 0
LOGIC 1 OR 0
SIN1
SIN1
I1
SOUT01
I1
LOGIC 1 OR 0
LOGIC 1 OR 0
SIN0
SIN0
I0
SOUT00
LOGIC 1 OR 0
I0
LOGIC 1 OR 0
5-5746(F).a
5-5745(F).a
Figure 16. Buffer-Buffer-Decoder Mode
Figure 15. Buffer Mode
22
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Logic Cells (continued)
SIN9
SIN9
LOGIC 1 OR 0
SIN8
SOUT09
I9
LOGIC 1 OR 0
SIN8
LOGIC 1 OR 0
SIN7
SOUT08
I8
LOGIC 1 OR 0
SIN7
LOGIC 1 OR 0
SIN6
LOGIC 1 OR 0
SIN6
LOGIC 1 OR 0
SIN5
LOGIC 1 OR 0
SIN5
LOGIC 1 OR 0
SIN4
LOGIC 1 OR 0
TRI
LOGIC 1 OR 0
SIN4
DEC
LOGIC 1 OR 0
1
DEC
TRI
IF LOW THEN 3 STATE BUFFERS ARE HIGH Z
SOUT03
1
SIN3
I3
LOGIC 1 OR 0
1
1
SIN2
I2
SOUT02
SOUT01
LOGIC 1 OR 0
SIN3
I3
SIN1
I1
SOUT03
SOUT02
SOUT01
SOUT00
LOGIC 1 OR 0
LOGIC 1 OR 0
SIN2
I2
SIN0
I0
SOUT00
LOGIC 1 OR 0
LOGIC 1 OR 0
5-5750(F)
SIN1
I1
Figure 18. Buffer-Decoder-Decoder Mode
LOGIC 1 OR 0
SIN0
I0
LOGIC 1 OR 0
5-5747(F).a
Figure 17. Buffer-Decoder-Buffer Mode
Lattice Semiconductor
23
Data Sheet
May, 2006
ORCA Series 4 FPGAs
PLC Latches/Flip-Flops
Programmable Logic Cells (continued)
The eight general-purpose latches/FFs in the PFU can
be used in a variety of configurations. In some cases,
the configuration options apply to all eight latches/FFs
in the PFU and some apply to the latches/FFs on a nib-
ble-wide basis where the ninth FF is considered inde-
pendently. For other options, each latch/FF is
SIN9
LOGIC 1 OR 0
SIN8
LOGIC 1 OR 0
SIN7
independently programmable. In addition, the ninth FF
can be used for a variety of functions.
Table 6 summarizes these latch/FF options. The
latches/FFs can be configured as either positive- or
negative-level sensitive latches, or positive or negative
edge-triggered FFs (the ninth register can only be a
FF). All latches/FFs in a given PFU share the same
clock, and the clock to these latches/FFs can be
inverted. The input into each latch/FF is from either the
corresponding LUT output (F[7:0]) or the direct data
input (DIN[7:0]). The latch/FF input can also be tied to
logic 1 or to logic 0, which is the default.
LOGIC 1 OR 0
SIN6
LOGIC 1 OR 0
SIN5
LOGIC 1 OR 0
SIN4
LOGIC 1 OR 0
Table 6. Configuration RAM Controlled Latch/
Flip-Flop Operation
DEC
Function
Options
Common to All Latches/FFs in PFU
LSR Operation
Clock Polarity
Asynchronous or synchronous.
Noninverted or inverted.
SIN3
Front-end Select* Direct (DIN[7:0]) or from LUT
(F[7:0]).
LOGIC 1 OR 0
SIN2
LSR Priority
Either LSR or CE has priority.
Latch or FF.
Latch/FF Mode
Enable GSRN
GSRN enabled or has no effect on
PFU latches/FFs.
LOGIC 1 OR 0
SIN1
Set Individually in Each Latch/FF in PFU
Set/Reset Mode Set or reset.
LOGIC 1 OR 0
SIN0
By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8])
Clock Enable
CE or none.
LOGIC 1 OR 0
LSR Control
LSR or none.
* Not available for FF[8].
5-5748(F)
Figure 19. Decoder Mode
Each PFU has two independent programmable clocks,
clock enable CE[1:0], local set/reset LSR[1:0], and
front end data selects SEL[1:0]. When CE is disabled,
each latch/FF retains its previous value when clocked.
The clock enable, LSR, and SEL inputs can be inverted
to be active-low.
24
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
latch/FF is from the output of its associated LUT,
F[7:0], or direct from DIN[7:0], bypassing the LUT. In
the front-end data select mode, both signals are avail-
able to the latches/FFs.
Programmable Logic Cells (continued)
The set/reset operation of the latch/FF is controlled by
two parameters: reset mode and set/reset value. When
the GSRN and local set/reset (LSR) signals are not
asserted, the latch/FF operates normally. The reset
mode is used to select a synchronous or asynchronous
LSR operation. If synchronous, LSR has the option to
be enabled only if clock enable (CE) is active or for LSR
to have priority over the clock enable input, thereby set-
ting/resetting the FF independent of the state of the
clock enable.The clock enable is supported on FFs, not
latches. It is implemented by using a 2-input multiplexer
on the FF input, with one input being the previous state
of the FF and the other input being the new data
applied to the FF. The select of this 2-input multiplexer
is clock enable (CE), which selects either the new data
or the previous state.When the clock enable is inactive,
the FF output does not change when the clock edge
arrives.
If either or both of these inputs is unused or is unavail-
able, the latch/FF data input can be tied to a logic 0 or
logic 1 instead (the default is logic 0).
The latches/FFs can be configured in three basic
modes:
■ Local synchronous set/reset: the input into the PFU’s
LSR port is used to synchronously set or reset each
latch/FF.
■ Local asynchronous set/reset: the input into LSR
asynchronously sets or resets each latch/FF.
■ Latch/FF with front-end select, LSR either synchro-
nous or asynchronous: the data select signal selects
the input into the latches/FFs between the LUT out-
put and direct data in.
The GSRN signal is only asynchronous, and it sets/
resets all latches/FFs in the FPGA based upon the set/
reset configuration bit for each latch/FF. The set/reset
value determines whether GSRN and LSR are set or
reset inputs. The set/reset value is independent for
each latch/FF. An option is available to disable the
GSRN function per PFU after initial device configura-
tion.
For all three modes, each latch/FF can be indepen-
dently programmed as either set or reset. Figure 20
provides the logic functionality of the front-end select,
global set/reset, and local set/reset operations.
The ninth PFU FF, which is generally associated with
registering the carry-out signal in ripple mode func-
tions, can be used as a general-purpose FF. It is only
an FF and is not capable of being configured as a
latch. Because the ninth FF is not associated with an
LUT, there is no front-end data select.The data input to
the ninth FF is limited to the CIN input, logic 1, logic 0,
or the carry-out in ripple and half-logic modes.
The latch/FF can be configured to have a data front-
end select.Two data inputs are possible in the front-end
select mode, with the SEL signal used to select which
data input is used. The data input into each
CE
CE
CE
CE
SEL
F
DIN
LOGIC 1
LOGIC 0
F
DIN
F
DIN
LOGIC 1
LOGIC 0
CE
CE
D
Q
D
Q
D
Q
LOGIC 1
LOGIC 0
DIN
S_SET
LSR
S_RESET
CLK
GSRN
LSR
GSRN
LSR
CLK
SET RESET
CLK
SET RESET
SET RESET
GSRN
CD
CD
CD
5-9737(F).a
Key: C = configuration data.
Figure 20. Latch/FF Set/Reset Configurations
Lattice Semiconductor
25
Data Sheet
May, 2006
ORCA Series 4 FPGAs
■ One 256 x 36 RAM.
■ One 1K x 9 RAM.
Embedded Block RAM (EBR)
The ORCA Series 4 devices compliment the distributed
PFU RAM with large blocks of memory macrocells.The
memory is available in 512 words by 18 bits/word
blocks with 2 read and 2 write ports with two byte lane
enables which operate with quad-port functionality.
Additional logic has been incorporated for FIFO, multi-
plier, and CAM implementations. The RAM blocks are
organized along the PLC rows and are added in pro-
portion to the FPGA array sizes as shown in Table 7.
The contents of the RAM blocks may be optionally ini-
tialized during FPGA configuration.
■ Two independent 512 x 9 RAMs built in one EBR with
separate read clocks, write clocks and enables.
■ Two independent RAMS with arbitrary number of
words whose sum is 512 words or less by 18 bits/
word or less.
The joining of RAM blocks is supported to create wider
deeper memories. The adjacent routing interface pro-
vided by the CIBs allow the cascading of blocks
together with minimal penalties due to routing delays.
It is also possible to connect any or all of the EBR RAM
blocks together through the embedded system bus,
which is discussed in a later section of this data sheet.
Table 7. ORCA Series 4— Available Embedded
Block RAM
Device
Number of
Blocks
Number of
EBR Bits
Arbitration logic is optionally programmed by the user
to signal occurrences of data collisions as well as to
block both ports from writing at the same time. The
arbitration logic prioritizes PORT1. When utilizing the
arbiter, the signal BUSY indicates data is being written
to PORT1.This BUSY output signals PORT1 activity by
driving a high output. If the arbiter is turned off both
ports could be written at the same time and the data
would be corrupt. In this scenario the BUSY signal will
indicate a possible error.
OR4E02
OR4E04
OR4E06
8
74K
111K
147K
12
16
Each highly flexible 512x18 (quad-port, two read/two
write) RAM block can be programmed by the user to
meet their particular function. Each of the EBR configu-
rations use the physical signals as shown in
There is also a user option which dedicates PORT 1 to
communications to the system bus. In this mode the
user logic only has access to PORT0 and arbitration
logic is enabled. The system bus utilizes the priority
given to it by the arbiter therefore the system bus will
always be able to write to the EBR.
Table 8. Quad-port addressing permits simultaneous
read and write operations on all four ports.
The EBR ports are written synchronously on the posi-
tive-edge of CKW. Synchronous read operations uses
the positive-edge of CKR. Options are available to use
synchronous read address registers and read output
registers, or to bypass these registers and have the
RAM read operate asynchronously. Detailed informa-
tion about the EBR blocks is found in various applica-
tion notes.
ispLEVER provides SCUBA as a RAM generation tool
for EBR RAMs. Many of the EBR sub-modes are sup-
ported and the initialization values can also be defined.
EBR Features
Quad Port RAM Modes (Two Read/Two Write)
■ One 512 x 18 RAM with optional built-in write arbitra-
tion.
■ One 1024 x 18 RAM built on two blocks with built-in
decode logic for simplified implementation.
Dual Port RAM Modes (One Read/One Write)
26
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
An 8 x 8 MULTIPLY mode is configurable to either a
pipelined or combinatorial multiplier function of two 8-
bit numbers. Two 8-bit operands are multiplied to yield
a 16-bit product.The input can be registered in pipeline
mode.
Embedded Block RAM (EBR) (continued)
FIFO Modes
FIFOs can be configured to 256, 512, or 1K depths and
36, 18, or 9 widths respectively but also can be
expanded using multiple blocks. FIFO works synchro-
nously with the same read and write clock where the
read port can be registered on the output or not regis-
tered. It can also be optionally configured asynchro-
nously with different read and write clocks and the
same read port register options.
CAM Mode
The CAM block is a binary content address memory
that provides fast address searches by receiving data
input and returning addresses that contain the data.
Implemented in each EBR are two 16-word x 8-bit CAM
function blocks.
Integrated flags allow the user the ability to fully utilize
the EBR for FIFO, without the need to dedicate an
address for providing distinct full/empty status. There
are four programmable flags provided for each FIFO:
Empty, partially empty, full, and partially full FIFO sta-
tus. The partially empty and partially full flags are pro-
grammable with the flexibility to program the flags to
any value from the full or empty threshold. The pro-
grammed values can be set to a fixed value through the
bitstream or a dynamic value can be controlled by input
pins of the EBR FIFO. When the FIFO is in asynchro-
nous mode, the FIFO flags use grey code counters to
ensure proper glitch-free operation.
The CAM has three modes, single match, multiple
match and clear, which are all achieved in one clock
cycle. In single match mode, a 8-bit data input is inter-
nally decoded and reports a match when data is
present in a particular RAM address. Its result is
reported by a corresponding single address bit. In mul-
tiple match the same occurs with the exception of multi-
ple address lines report the match. Clear mode is used
to clear the CAM contents by erasing all locations one
cycle per location. The EBR blocks in CAM mode may
be cascaded to produce larger CAMs.
Multiplier Modes
The ORCA Series 4 EBR supports two variations of
multiplier functions. Constant coefficient MULTIPLY
[KCM] mode will produce a 24-bit output of a fixed 8-bit
constant multiply of a 16-bit number or a fixed 16-bit
constant multiply of an 8-bit number. This KCM multi-
plies a constant times a 16- or 8-bit number and pro-
duces a product as a 24-bit result. The coefficient and
multiplication tables are stored in memory. The input
can be configured to be registered for pipelining. Both
write ports are available during MULTIPLY mode so
that the user logic can update and modify the coeffi-
cients for dynamic coefficient updates. The SCUBA
program in ispLEVER should be used to create the
KCM multipliers, including the input of initial coeffi-
cients.
Lattice Semiconductor
27
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Embedded Block RAM (EBR) (continued)
Table 8. RAM Signals
Port Signals
I/O
Function
PORT 0
AR0[#:0]
AW0[#:0]
BW0<1:0>
I
I
I
Address to be read (variable width depending on RAM size).
Address to be written (variable width depending on RAM size).
Byte-write enable.
Byte = 8-bits + parity bit.
<1> = bits[17, 15:9] <0> = bits[16, 7:0]
CKR0
CKW0
CSR0
CSW0
D [#:0]
Q [#:0]
I
I
Positive-edge asynchronous read clock.
Positive-edge synchronous write clock.
I
Enables read to output. Active high.
I
Enables write to output. Active high.
I
Input data to be written to RAM (variable width depending on RAM size).
O
Output data of memory contents at referenced address (variable width depending on
RAM size).
PORT 1
AR1[#:0]
AW1[#:0]
BW1<1:0>
I
I
I
Address to be read (variable width depending on RAM size).
Address to be written (variable width depending on RAM size).
Byte-write enable.
Byte = 8-bits + parity bit.
<1> = bits[17, 15:9] <0> = bits[16, 7:0]
CKR1
CKW1
CSR1
CSW1
D [#:0]
Q [#:0]
I
I
Positive-edge asynchronous read clock.
Positive-edge synchronous write clock.
I
Enables read to output. Active high.
I
Enables write to output. Active high.
I
Input data to be written to RAM (variable width depending on RAM size).
O
Output data of memory contents at referenced address (variable width depending on
RAM size).
Control
BUSY
O
I
PORT1 writing. Active high.
RESET
Data output registers cleared. Memory contents unaffected. Active-low.
28
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Embedded Block RAM (continued)
CKWPL
CKWPH
CKW
CSWSU
AWSU
DSU
CSWH
AWH
DH
CSW
AW
D
c
d
BWSU
BWH
BW
AR
Q
a
b
c
AQH
AQ
CKWQ
a
b
c
d
0308(F)
Figure 21. EBR Read and Write Cycles with Write Through and Nonregistered Read Port
Table 9. FIFO Signals
Port Signals
I/O
Function
AR0[5:0]
AR1[9:0]
FF
I
I
Programs FIFO flags. Used for partially empty flag size.
Programs FIFO flags. Used for partially full flag size.
Full Flag.
O
O
O
O
I
PFF
Partially Full Flag.
PEF
Partially Empty Flag.
EF
Empty Flag.
D0[17:0]
D1[17:0]
CKW[0:1]
CKR[0:1]
CSW[1:0]
CSR[1:0]
RESET
Q0[17:0]
Q1[17:0]
Data inputs for all configurations.
I
Data inputs for 256x36 configurations only.
Positive-edge write port clock. Port 1 only used for 256x36 configurations.
Positive-edge read port clock. Port 1 only used for 256x36 configurations.
Active-high write enable. Port 1 only used for 256x36 configurations.
Active-high read enable. Port 1 only used for 256x36 configurations.
Active-low Resets FIFO pointers.
I
I
I
I
I
O
O
Data outputs for all configurations.
Data outputs for 256x36 configurations.
Lattice Semiconductor
29
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Embedded Block RAM (continued)
Table 10. Constant Multiplier Signals
Port Signals
I/O
Function
AR0[15:0]
AW(1:0)[8:0]
D(1:0)[17:0]
CKW[0:1]
CKR[0:1]
I
I
Data input–operand.
Address bits.
I
Data inputs to load memory or change coefficient.
Positive-edge write port clock.
I
I
Positive-edge read port clock. Used for synchronous multiply mode.
Active-high write enable.
CSW[1:0]
CSR[1:0]
I
I
Active-high read enable.
Q[23:0]
O
Data outputs–product result.
Table 11. 8x8 Multiplier Signals
Port Signals
I/O
Function
AR0[7:0]
AR1[7:0]
CKR[0:1]
CSR[1:0]
Q[15:0]
I
I
Data input-Multiplicand.
Data input-Multiplier.
I
Positive-edge read port clock. Used for synchronous multiply mode.
Active-high read enable.
I
O
Data outputs-product.
Table 12. CAM Signals
Port Signals
I/O
Function
AR(1:0)[7:0]
AW(1:0)[8:0]
D(1:0)[17]
D(1:0)[16]
D(1:0)[3:0]
CSW[1:0]
I
I
Data Match.
Data Write.
I
Clear data active high.
I
Single match active high.
I
CAM address for data write.
Active-high write enable. Enable for CAM data write.
Active-high read enable. Enable for CAM data match.
I
CSR[1:0]
I
Q(1:0)15:0]
O
Decoded Data outputs. “1” corresponds to a data match at that address location.
30
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Global Primary Clock Nets
Routing Resources
The Series 4 FPGAs provide eight fully distributed glo-
bal primary clock net routing resources. The scheme
dedicates four of the eight resources to provide fast pri-
mary nets and four are available for general primary
nets. The fast primary nets are targeted toward low-
skew and small injection times while the general pri-
mary nets are also targeted toward low-skew but have
more source connection flexibility. Fast access to the
global primary nets can be sourced from two pairs of
pads located in the center of each side of the device,
from the programmable PLLs and dedicated network
PLLs located in the corners, or from general routing at
the center of the device or at the middle of any side of
the device.The I/O pads are semi-dedicated in pairs for
use of differential I/O clocking or single-ended I/O clock
sources. However if these pads are not needed to
source the clock network they can be utilized for gen-
eral I/O. The clock routing scheme is patterned using
vertical and horizontal routes which provide connectiv-
ity to all PLC columns.
The abundant routing resources of the Series 4 archi-
tecture are organized to route signals individually or as
buses with related control signals. Both local and glo-
bal signals utilize high-speed buffered and nonbuffered
routes. One PLC segmented (x1), six PLC segmented
(x6), and bused half chip (xHL) routes are patterned
together to provide high connectivity with fast software
routing times and high-speed system performance.
x1 routes cross width of one PLC and provide local
connectivity to PFU and SLIC inputs and outputs. x6
lines cross width of 6 PLCs and are unidirectional and
buffered with taps in the middle and on the end. Seg-
ments allow connectivity to PFU/SLIC outputs (driven
at one end-point), other x6 lines (at end-points), and
x1 lines for access to PFU/SLIC inputs. xH lines run
vertically and horizontally the distance of half the
device and are useful for driving medium/long distance
3-state routing.
The improved routing resources offer great flexibility in
moving signals to and from the logic core. This flexibil-
ity translates into an improved capability to route
designs at the required speeds even when the I/O sig-
nals have been locked to specific pins. The buffered
routing capability also allows a very large fanout to be
driven from each logic output, thus greatly reducing the
amount of logic replication required by synthetic tools.
Secondary Clock and Control Nets
Secondary clock control and routing provides flexible
clocking and control signalling for local regions. Since
secondary nets usually have high fanouts and require
low skew, the Series 4 devices utilize a spine and
branch that uses x6 segments with high-speed connec-
tions provided from the spines to the branches. The
branches then have high-speed connections to PLC,
PIO, and EBR clock and control signals. This strategy
provides a flexible connectivity and routes can be
sourced from any I/O pin, all PLLs, or from PLC or EBR
logic.
Generally, the ispLEVER Development System is used
to automatically route interconnections. Interactive
routing with the ispLEVER design editor (EPIC) is also
available for design optimization.
The routing resources consist of switching circuitry and
metal interconnect segments. Generally, the metal
lines which carry the signals are designated as routing
segments. The switching circuitry connects the routing
segments, providing one or more of three basic func-
tions: signal switching, amplification, and isolation. A
net running from a PFU, EBR, or PIO output (source) to
a PLC, EBR, or PIO input (destination) consists of one
or more routing segments, connected by switching cir-
cuitry called configurable interconnect points (CIPs).
Secondary Edge Clock Nets and Fast Edge
Clock Nets
Six secondary edge clock nets per side are distributed
around the edges of the device and are available for
every PIO. All PIOs and PLLs can drive the secondary
edge clocks and are used in conjunction with the sec-
ondary spines discussed above to drive the same edge
clock signal into the internal logic array. The edge sec-
ondary clocks provide fast injection to the PLC array
and I/O registers. One of the six secondary edge
clocks provided per side of the device is a special fast
edge clock net that only clocks input registers for fur-
ther reduced setup/hold times.This timing path can only
be driven from one of the four PIO input pins in each
PIC.
Clock Distribution Network
Clock distribution is made up of three types of clock
networks: primary, secondary, and edge clocks. these
are described below and more information is available
in the Series 4 Clocking Strategies application note.
Lattice Semiconductor
31
Data Sheet
May, 2006
ORCA Series 4 FPGAs
ated with each pad allows for multiplexing of output sig-
nals and other functions of two output signals.
Routing Resources (continued)
Cycle Stealing
The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The out-
put buffer signal can be inverted, and the 3-state con-
trol can be made active-high, active-low, or always
enabled. In addition, this 3-state signal can be regis-
tered or nonregistered.
A new feature in Series 4 FPGAs is the ability to steal
time from one register-to-register path and use that
time in either the previous path before the first register
or in a later path after the last register. This is done
through selectable clock delays for every PLC register,
EBR register, and PIO register. There are four pro-
grammable delay settings, including the default zero
added delay value. This allows performance increases
on typical critical paths from 15% to 40%. ispLEVER
includes software to automatically take advantage of
this capability to increase overall system speed. This is
done after place and route is completed and uses tim-
ing driven algorithms based on the customer’s prefer-
ence file. A hold time check is also performed to verify
no minimum hold time issues are introduced. More
information on this clocking feature, including how it
can be used to improve device setup times, hold times,
clock-to-out delays and can reduce ground bounce
caused by switching outputs can be found in the Cycle
Stealing application note.
The Series 4 I/O logic has been enhanced to include
modes for high-speed uplink and downlink capabilities.
These modes are supported through shift register logic
which divides down incoming data or multiplies up out-
going data. This new logic block also supports high-
speed DDR mode requirements where data is clocked
into and out of the I/O buffers on both edges of the
clock.
The new programmable I/O cell allows designers to
select I/Os which meet many new communication stan-
dards permitting the device to hook up directly without
any external interface translation. They support tradi-
tional FPGA standards as well as high-speed single-
ended and differential pair signaling (as shown in
Table 13). Based on a programmable, bank-oriented
I/O ring architecture, designs can be implemented
using 3.3 V, 2.5 V, 1.8 V, and 1.5 V I/O levels.
Programmable Input/Output Cells (PIC)
Programmable I/O
The I/O on the OR4Exx Series devices allows compli-
ance with PCI local bus (Rev. 2.2) 3.3 V signaling envi-
ronments. The signaling environment used for each
input buffer can be selected on a per-pin basis. The
selection provides the appropriate I/O clamping diodes
for PCI compliance.
The Series 4 programmable I/O addresses the demand
for the flexibility to select I/O that meets system inter-
face requirements. I/Os can be programmed in the
same manner as in previous ORCA devices with the
addition of new features which allow the user the flexi-
bility to select new I/O types that support high-speed
interfaces.
More information on the Series 4 programmable I/O
structure is available in the various application notes.
Each PIC contains up to four programmable I/O (PIO)
pads and are interfaced through a common interface
block (CIB) to the FPGA array. The PIC is split into two
pairs of I/O pads with each pair having independent
clocks, clock enables, local set/reset, and global
set/reset enable/disable.
On the input side, each PIO contains a programmable
latch/FF which enables very fast latching of data from
any pad. The combination provides for very low setup
requirements and zero hold times for signals coming
on-chip. It may also be used to demultiplex an input sig-
nal, such as a multiplexed address/data signal, and
register the signals without explicitly building a demulti-
plexer with a PFU.
On the output side of each PIO, an output from the PLC
array can be routed to each output FF, and logic can be
associated with each I/O pad. The output logic associ-
32
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Input/Output Cells (continued)
Table 13. Series 4 Programmable I/O Standards
Standard
VDDIO (V) VREF (V)
Interface Usage
LVTTL
LVCMOS2
LVCMOS18
PCI
3.3
2.5
1.8
3.3
2.5
2.5
NA
NA
NA
NA
NA
NA
General purpose.
PCI.
LVDS
Point to point and multi-drop backplanes, high noise immunity.
Bused-LVDS
Network backplanes, high noise immunity, bus architecture
backplanes.
LVPECL
3.3
NA
Network backplanes, differential 100 MHz+ clocking, optical
transceiver, high-speed networking.
PECL
GTL
3.3
3.3
3.3
1.5
1.5
3.3
2.5
2.0
0.8
Backplanes.
Backplane or processor interface.
GTL+
1.0
HSTL-class I
HTSL-class III and IV
STTL3-class I and II
SSTL2-class I and II
0.75
0.9
High-speed SRAM and networking interfaces.
Synchronous DRAM interface.
1.5
1.25
Note: interfaces to DDR and ZBT memories are supported through the interface standards shown above.
The PIOs are located along the perimeter of the device.The PIO name is represented by a two-letter designation to
indicate the side of the device on which it is located followed by a number to indicate the row or column in which it is
located.The first letter, P, designates that the cell is a PIO and not a PLC.The second letter indicates the side of the
array where the PIO is located. The four sides are left (L), right (R), top (T), and bottom (B). A number follows to
indicate the PIC row or column. The individual I/O pad is indicated by a single letter (either A, B, C, or D) placed at
the end of the PIO name. As an example, PL10A indicates a pad located on the left side of the array in the tenth
row.
Each PIC interfaces to four bond pads through four PIOs and contains the necessary routing resources to provide
an interface between I/O pads and the CIBs. Each PIC contains input buffers, output buffers, routing resources,
latches/FFs, and logic and can be configured as an input, output, or bidirectional I/O. Any PIO is capable of sup-
porting the I/O standards listed in Table 13.
The CIBs that connect to the PICs have significant local routing resources, similar to routing in the PLCs. This new
routing increases the ability to fix user pinouts prior to placement and routing of a design and still maintain routabil-
ity.The flexibility provided by the routing also provides for increased signal speed due to a greater variety of optimal
signal paths.
Included in the routing interface is a fast path from the input pins to the PFU logic. This feature allows for input sig-
nals to be very quickly processed by the SLIC decoder function and used on-chip or sent back off of the FPGA.
A diagram of a single PIO is shown in Figure 22, and Table 14 provides an overview of the programmable functions
in an I/O cell.
Lattice Semiconductor
33
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Input/Output Cells (continued)
LVDS
RESISTOR
LEVELMODE
OUTPUT SIDE
INPUT SIDE
LVTTL
LVCMOS2
LVCMOS18
PCI
OFF
ON
AND
OUTSH
NAND
OUTDD
BUFMODE
KEEPERMODE
OR
SSTL2
SSTL3
HSTL1
HSTL3
GTL
PLOGIC
MILLIAMPS
SIX
SLEW
FAST
NA
CLK
NOR
XOR
XNOR
OFF
ON
TWELVE
TWENTYFOUR
NA
FAST INPUT
INCK
PMUX
OUTDDMUX
OUTSH
GTLPLUS
PECL
OUTMUX
OUTSHMUX
OUTDD
0
LVPECL
LVDS
CLK
LATCHFF
INMUX
DELAY
CELL
OUTDD
D0
D1
OUTFFMUX
INFF
D0
CK
TSMUX
OUTFF
P2MUX
OUTDD
OUTREG
EC
SC
NORMAL
USRTS
TSREG
IOPAD
0
INVERTED
CK
CE
1
1
OUTREG
DO
CLK4MUX
PULLMODE
DEL0
DEL1
DEL2
DEL3
EC
SC
SP
DO
CK
0
UP
LSR
CK
DOWN
NONE
NA
CEMUXI
DEL0
DEL1
DEL2
DEL3
LATCHFF
LATCH
FF
RESET
SET
RESET
SET
LSR
CEMUX0
SP
RESET
SET
LATCH
FF
CE
INDDMUX
LSR
INDD
1
LSRMUX
LSR
0
SRMODE
GSR
CE_OVER_LSR
LSR_OVER_CE
ASYNC
ENABLED
DISABLED
5-9732(F)
Figure 22. Series 4 PIO Image from ispLEVER Design Software
34
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FF which is clocked by a global primary system clock.
Programmable Input/Output Cells
(continued)
The combination of input register capability with non-
registered inputs provides for input signal demultiplex-
ing without any additional resources. The PIO input
signal is sent to both the input register and directly to
the unregistered input (INDD). The signal is latched
and output to routing at INFF. These signals may then
be registered or otherwise processed in the PLCs.
Inputs
There are many major options on the PIO inputs that
can be selected in the ispLEVER tools listed in Table
14. Inputs may have a pull-up or pull-down resistor
selected on an input for signal stabilization and power
management. Input signals in a PIO are passed to CIB
routing and/or a fast route into the clock routing sys-
tem. A fast input from one PIO per PIC is also available
to drive the edge clock network for fast I/O timing to
other nearby PIOs.
Every PIO input can also perform input double data
rate (DDR) functions with no PLC resources required.
This type of scheme is necessary for DDR applications
which require data to be clocked in from the I/O on both
edges of the clock. In this scheme the input of INFF
and INSH are captured on the positive and negative
edges of the clock.
There is also a programmable delay available on the
input. When enabled, this delay affects the INFF and
INDD signals of each PIO, but not the clock input. The
delay allows any signal to have a guaranteed zero hold
time when input.
Table 14. PIO Options
Input
Option
Input Speed
Float Value
Fast, Delayed, Normal
Inputs should have transition times of less than 100 ns
and should not be left floating. For full swing inputs, the
timing characterization is done for rise/fall times of
≥ 1 V/ns. If any pin is not used, it is 3-stated with an
internal pull-up resistor enabled automatically after
configuration. Floating inputs increase power con-
sumption, produce oscillations, and increase system
noise. The inputs in LVTTL, LVCMOS2, and
Pull-up, Pull-down, None
Register Mode
Latch, FF, Fast Zero Hold FF,
None (direct input)
Clock Sense
Keeper Mode
Inverted, Noninverted
on, off
LVDS Resistor
on, off
LVCMOS18 modes have a typical hysteresis of approx-
imately 250 mV to reduce sensitivity to input noise.The
PIC contains input circuitry which provides protection
against latch-up and electrostatic discharge.
Output
Option
Output Speed
Fast, Slew
Output Drive
Current
12 mA/6 mA, 6 mA/3 mA, or
24 mA/12 mA
The other features of the PIO inputs relate to the latch/
FF structure in the input path. In latch mode, the input
signal is fed to a latch that is clocked by either the pri-
mary, secondary, or edge clock signal. The clock may
be inverted or noninverted. There is also a local set/
reset signal to the latch. The senses of these signals
are also programmable as well as the capability to
enable or disable the global set/reset signal and select
the set/reset priority. The same control signals may
also be used to control the input latch/FF when it is
configured as a FF instead of a latch, with the addition
of another control signal used as a clock enable. The
PIOs are paired together and have independent CE,
Set/reset, and GSRN control signals per PIO pair.
Output Function Normal, Fast Open Drain
Output Sense
3-State Sense
Clock Sense
Logic Options
Active-high, Active-low
Active-high, Active-low
Inverted, Noninverted
See Table 15
I/O Controls
Option
Clock Enable
Active-high, Active-low,
Always Enabled
Set/Reset Level
Set/Reset Type
Active-high, Active-low,
No Local Reset
Synchronous, Asynchronous
Set/Reset Priority CE over LSR, LSR over CE
GSR Control Enable GSR, Disable GSR
There are two options for zero-hold input capture in the
PIO. If input delay mode is selected to delay the signal
from the input pin, data can be either registered or
latched with guaranteed zero-hold time in the PIO
using a global primary system clock.The fast zero-hold
mode of the PIO input takes advantage of a latch/FF
combination to latch the data quickly for zero-hold
using a fast edge clock before passing the data to the
Lattice Semiconductor
35
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 15. PIO Logic Options
Option Description
Programmable Input/Output Cells
(continued)
AND Output logical AND of signals on OUTDD
and clock.
Outputs
NAND Output logical NAND of signals on OUTDD
and clock.
The PIO’s output drivers have programmable drive
capability and slew rates.Two propagation delays (fast,
slewlim) are available on output drivers. There are
three combinations of programmable drive currents
(24 mA sink/12 mA source, 12 mA sink/6 mA source,
and 6 mA sink/3 mA source). At powerup, the output
drivers are in slewlim mode with 12mA sink/6 mA
source. If an output is not to be driven in the selected
configuration mode, it is 3-stated with a pullup resistor.
OR
Output logical OR of signals on OUTDD
and clock.
NOR Output logical NOR of signals on OUTDD
and clock.
XOR Output logical XOR of signals on OUTDD
and clock.
XNOR Output logical XNOR of signals on OUTDD
and clock.
The output buffer signal can be inverted, and the
3-state control signal can be made active-high, active-
low, or always enabled. In addition, this 3-state signal
can be registered or nonregistered. Additionally, there
is a fast, open-drain output option that directly connects
the output signal to the 3-state control, allowing the out-
put buffer to either drive to a logic 0 or 3-state, but
never to drive to a logic 1.
PIO Register Control Signals
The PIO latches/FFs have various clock, clock enable
(CE), local set/reset (LSR), and GSRN controls. Table
16 provides a summary of these control signals and
their effect on the PIO latches/FFs. Note that all control
signals are optionally invertible.
Every PIO output can perform output data multiplexing
with no PLC resources required.This type of scheme is
necessary for DDR applications which require data
clocking out of the I/O on both edges of the clock. In
this scheme the OUTFF and OUTSH are registered
and sent out on both the positive and negative edges of
the clock using an output multiplexor. This multiplexor
is controlled by either the edge clock or system clock.
This multiplexor can also be configured to select
between one registered output from OUTFF and one
nonregistered output from OUTDD.
Table 16. PIO Register Control Signals
Control
Effect/Functionality
Signal
Edge Clock Clocks input fast-capture latch; option-
(ECLK)
ally clocks output FF, or
3-state FF, or PIO shift registers.
System
Clock
(SCLK)
Clocks input latch/FF; optionally clocks
output FF, or 3-state FF, or PIO shift
registers.
The PIC logic block can also generate logic functions
based on the signals on the OUTDD and CLK ports of
the PIO. The functions are AND, NAND, OR, NOR,
XOR, and XNOR. Table 15 is provided as a summary
of the PIO logic options.
Clock
Optionally enables/disables input FF
Enable (CE) (not available for input latch mode);
optionally enables/disables output FF;
separate CE inversion capability for
input and output.
Local Set/ Option to disable; affects input latch/FF,
Reset (LSR) output FF, and 3-state FF if enabled.
Global Set/ Option to enable or disable per PIO
Reset
after initial configuration.
(GSRN)
Set/Reset The input latch/FF, output FF, and 3-
Mode
state FF are individually set or reset by
both the LSR and GSRN inputs.
36
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
I/O Banks and Groups
BANK 0
(TL)
BANK 1
(TC)
BANK 2
(TR)
Flexible I/O features allow the user to select the type of
I/O needed to meet different high-speed interface
requirements and these I/Os require different input ref-
erences or supply voltages.The perimeter of the device
is divided into eight banks of PIO buffers, as shown in
Figure 23, and for each bank there is a separate VDDIO
that supplies the correct input and output voltage for a
particular standard. The user must supply the appropri-
ate power supply to the VDDIO pin. Within a bank, sev-
eral I/O standards may be mixed as long as they use a
common VDDIO.The shaded section of the I/O banks in
Figure 23 (banks 2, 3, and 4) are removed for FPSCs,
to allow the embedded block to be placed on the side
of the FPGA array. Bank 1 and bank 5 are also
extended to the corners in FPSCs to incorporate more
FPGA I/Os.
PLC ARRAY
BANK 4
(BR)
BANK 6
(BL)
BANK 5
(BC)
0205(F).
Figure 23. ORCA High-Speed I/O Banks
Differential I/O (LVDS and LVPECL)
Some interface standards require a specified threshold
voltage known as VREF. To accommodate various VREF
requirements, each bank is further divided into groups.
In these modes, where a particular VREF is required,
the device is automatically programmed to dedicate a
VREF pin for each group of PIOs within a bank. The
appropriate VREF voltage must be supplied by the user
and connected to the VREF pin for each group. The
VREF is dedicated exclusively to the group and cannot
be intermixed within the group with other signaling
requiring other VREF voltages. However, pins not
requiring VREF can be mixed in the same group. When
used to supply a reference voltage the VREF pad is no
longer available to the user for general use. The VREF
inputs should be well isolated to keep the reference
voltage at a consistent level.
Series 4 devices support differential input, output, and
input/output capabilities through pairs of PIOs.The two
standards supported are LVDS and LVPECL.
The LVDS differential pair I/O standard allows for high-
speed, low-voltage swing and low-power interfaces
defined by industry standards: ANSI/TIA/EIA-644 and
IEEE 1596.3 SSI-LVDS.The general purpose standard
is supplied without the need for an input reference sup-
ply and uses a low switching voltage which translates
to low ac power dissipation.
The ORCA LVDS I/O provides an integrated 100 Ω ter-
mination resistor used to provide a differential voltage
across the inputs of the receiver. The on-chip integra-
tion provides termination of the LVDS receiver without
the need of discrete external board resistors. The user
has the programmable option to enable termination per
receiver pair for point-to-point applications or in multi-
point interfaces limit the use of termination to bussed
pairs. If the user chooses to terminate any differential
receiver, a single LVDS_R pin is dedicated to connect a
single 100 Ω (± 1%) resistor to VSS which then enables
an internal resistor matching circuit to provide a bal-
ance 100 Ω (± 10%) termination across all process,
voltage, and temperature. Experiments have also
shown that enabling this 100 Ω matching resistor for
LVDS outputs also improves performance.
Table 17. Compatible Mixed I/O Standards
VDDIO Bank
Voltage
Compatible Standards
3.3 V
LVTTL, SSTL3-I, SSTL3-II, GTL+,
GTL, LVPECL, PECL
2.5 V
1.8 V
1.5 V
LVCMOS2, SSTL2-I, SSTL2-II, LVDS
LVCMOS18
HSTL I, HSTL III, HSTL IV
Lattice Semiconductor
37
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Bus Hold
Programmable Input/Output Cells
(continued)
Each PIO can be programmed with a KEEPERMODE
feature. This element is user programmed for bus hold
requirements.This mode retains the last known state of
a bus when the bus goes into 3-state. It prevents float-
ing busses and saves system power.
High-Speed Memory Interfaces
PIO features allow high-speed interfaces to external
SRAM and/or DRAM devices. Series 4 I/O meet
200 MHz ZBT requirements when switching between
write and read cycles. ZBT allows 100% use of bus
cycles during back-to-back read/write and write/read
cycles. However this maximum utilization of the bus
increases probability of bus contention when the inter-
faced devices attempt to drive the bus to opposite logic
values. The LVTTL I/O interfaces directly with commer-
cial ZBT SRAMs signalling and allows the versatility to
program the FPGA drive strengths from 6 mA to
24 mA.
PIO Downlink/Uplink (Shift Registers)
Each group of four PIOs in a PIC have access to an
input/output shift register as shown in Figure 24. This
feature allows high-speed input data to be divided
down by 1/2 or 1/4 and output data can be multiplied by
2x or 4x its internal speed. Both the input and output
shift registers can be programmed to operate at the
same time and are controlled by the same clock and
control signals.
For input shift mode, the data from INDD from the PIO
is connected to the input shift register.The input data is
divided down and is driven to the routing through the
INSH nodes. For output shift mode, the data from the
OUTSH nodes are driven from the internal routing and
connects to the output shift register. This output data is
multiplied up and driven to the OUTDD signal on the
PIOs.
DDR allows data to be read on both the rising and the
falling edge of the clock which delivers twice the band-
width. DDR doubles the memory speed from SDRAMs
or SRAMs without the need to increase clock fre-
quency. The flexibility of the PIO allows at least
156 MHz/312 Mbits per second performance using the
SSTL I/O or HSTL I/O features of the Series 4 devices.
High-Speed Networking Interfaces
In 2x output mode or input mode, two of the four I/Os in
a PIC can use the shift registers. While in 4x mode,
only one I/O can use the shift registers. This also
means that all differential I/Os on a Series 4 device can
use 2x shift register mode, but 4x mode is only avail-
able for half of the differential I/Os.
Series 4 devices support many I/O standards used in
networking. Two examples of this are the XGMII stan-
dard for 10 GbE (HSTL or SSTL I/Os) and the SPI-4
standard for various 10 Gbits/s network interfaces
(LVDS I/Os). Both operate as a point-to-point link
between devices that are forward clocked and transmit
data on both clock edges (DDR). The XGMII interface
is 36-bits wide per data flow direction and the SPI-4
interface is a 16-bit interface. The XGMII specification
is 156 MHz/312 Mbits/s and the SPI-4 specification that
can be met is 325 MHz/650 Mbits/s. More information
about using ORCA for these applications can be found
in the associated application note.
In 4x input mode, all the INSH nodes are used, while 2x
mode uses INSH4 and INSH3 for one shift register and
INSH2 and INSH1 for the second shift register. Simi-
larly, the output shift register in 4x mode uses all the
OUTSH signals. OUTSH2 and OUTSH1 are used for
2x output mode for one shift register and OUTSH4 and
OUTSH3 are used for the other output shift register.
38
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Programmable Input/Output Cells
(continued)
PIO
PIO
PIO
PIO
SHIFT REGISTER
INTO FPGA
SHIFT REGISTER
OUT FROM FPGA
CLK
0204(F).
Figure 24. PIO Shift Register
The timing of the release of GSRN at the end of config-
uration can be programmed in the start-up logic
described below. Following configuration, GSRN may
be connected to the RESET pin via dedicated routing, or
it may be connected to any signal via normal routing.
GSRN can also be controlled via a system bus register
command. Within each PFU and PIO, individual FFs
and latches can be programmed to either be set or
reset when GSRN is asserted. Series 4 allows individ-
ual PFUs and PIOs to turn off the GSRN signal to its
latches/FFs after configuration.
Special Function Blocks
Special function blocks in the Series 4 provide extra
capabilities beyond general FPGA operation. These
blocks reside in the corners and MIDs (middle inter-
quad areas) of the FPGA array.
Internal Oscillator
The internal oscillator resides in the upper left corner of
the FPGA array. It has output clock frequencies of
1.25 MHz and 10 MHz. The internal oscillator is the
source of the internal CCLK used for configuration. It
may also be used after configuration as a general-
purpose clock signal.
The RESET input pad has a special relationship to
GSRN. During configuration, the RESET input pad
always initiates a configuration abort, as described in
the FPGA States of Operation section. After configura-
tion, the GSRN can either be disabled (the default),
directly connected to the RESET input pad, or sourced
by a lower-right corner signal. If the RESET input pad is
not used as a global reset after configuration, this pad
can be used as a normal input pad.
Global Set/Reset (GSRN)
The GSRN logic resides in the upper-left corner of the
FPGA. GSRN is an invertible, default, active-low signal
that is used to reset all of the user-accessible latches/
FFs on the device. GSRN is automatically asserted at
powerup and during configuration of the device.
Lattice Semiconductor
39
Data Sheet
May, 2006
ORCA Series 4 FPGAs
test data is transmitted serially into TDI of the first
Special Function Blocks (continued)
BSCAN device (U1), through TDO/TDI connections
between BSCAN devices (U2 and U3), and out TDO of
the last BSCAN device (U4). In this configuration, the
TMS and TCK signals are routed to all boundary-scan
ICs in parallel so that all boundary-scan components
operate in the same state. In other configurations, mul-
tiple scan paths are used instead of a single ring.When
multiple scan paths are used, each ring is indepen-
dently controlled by its own TMS and TCK signals.
Start-Up Logic
The start-up logic block can be configured to coordi-
nate the relative timing of the release of GSRN, the
activation of all user I/Os, and the assertion of the
DONE signal at the end of configuration. If a start-up
clock is used to time these events, the start-up clock
can come from CCLK, or it can be routed into the start-
up block using upper-left corner routing resources.
Figure 26 provides a system interface for components
used in the boundary-scan testing of PCBs. The three
major components shown are the test host, boundary-
scan support circuit, and the devices under test
(DUTs). The DUTs shown here are ORCA Series
FPGAs with dedicated boundary-scan circuitry. The
test host is normally one of the following: automatic test
equipment (ATE), a workstation, a PC, or a micropro-
cessor.
Temperature Sensing
The built –in temperature sensing diodes allow junction
temperature to be measured during device operation. A
physical pin (PTEMP) is dedicated for monitoring
device junction temperature. PTEMP works by forcing
a 10 μA current in the forward direction, and then mea-
suring the resulting voltage. A 250 kΩ resistor tied to
3.3 V will approximate the needed 10 μA. The voltage
decreases with increasing temperature at a rate of
approximately –1.44 mV/°C. A typical device with an
85°C device temperature will measure about 640 mV.
S
TMS TDI
TCK
TMS TDI
TCK
net a
net b
TDO
TDO
U1
U2
net c
Boundary-Scan
TDI
TMS
TCK
The IEEE standards 1149.1 and 1149.2 (IEEE Stan-
dard test access port and boundary-scan architecture)
are implemented in the ORCA series of FPGAs. It
allows users to efficiently test the interconnection
between integrated circuits on a PCB as well as test
the integrated circuit itself. The IEEE 1149 standard is
a well-defined protocol that ensures interoperability
among boundary-scan (BSCAN) equipped devices
from different vendors.
TDO
TMS TDI
TCK
TMS TDI
TCK
TDO
TDO
U3
U4
SEE ENLARGED VEIW BELOW
TDI
TCK TMS
TDO
Series 4 FPGAs are also compliant to IEEE standard
1532/D1. This standard for boundary-scan based in-
system configuration of programmable devices pro-
vides a standardized programming access and meth-
odology for FPGAs. A device, or set of devices,
implementing this standard may be programmed, read
back, erased verified, singly or concurrently, with a
standard set of resources.
PT[ij]
TAPC
BSC
BDC
SCAN
IN
SCAN
OUT
BYPASS
REGISTER
DCC
p_ts
p_in
INSTRUCTION
REGISTER
p_out
SCAN
OUT
SCAN
IN
PR[ij]
p_ts
p_in
BSC
DCC
BSC
BDC
PLC
ARRAY
p_out
p_in
p_out
p_ts
DCC
BDC
The IEEE 1149 standards define a test access port
(TAP) that consists of a four-pin interface with an
optional reset pin for boundary-scan testing of inte-
grated circuits in a system. The ORCA Series FPGA
provides four interface pins: test data in (TDI), test
mode select (TMS), test clock (TCK), and test data out
(TDO). The PRGM pin used to reconfigure the device
also resets the boundary-scan logic.
PL[ij]
SCAN
IN
SCAN
OUT
p_out
p_ts
p_in
BSC
DCC BDC
SCAN
OUT
SCAN
IN
PB[ij]
5-5972(F)
Key:BSC = boundary-scan cell, BDC = bidirectional data cell, and
DCC = data control cell.
The user test host serially loads test commands and
test data into the FPGA through these pins to drive out-
puts and examine inputs. In the configuration shown in
Figure 26, where boundary-scan is used to test ICs,
Figure 25. Printed-Circuit Board with
Boundary-Scan Circuitry
40
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
D[7:0]
D[7:0]
BOUNDARY-
TDI
TDO
TDI
TDO
TDO
ORCA
SERIES
FPGA
ORCA
SERIES
FPGA
SCAN
MASTER
CE
TMS0
TCK
TMS
TCK
TMS
TCK
MICRO-
PROCESSOR
(DUT)
(DUT)
RA
R/W
DAV
INT
SP
(BSM)
TDI
INTR
TDI
TDO
ORCA
SERIES
FPGA
TMS
TCK
(DUT)
5-6765(F)
Figure 26. Boundary-Scan Interface
The boundary-scan support circuit shown in Figure 26
is the 497AA boundary-scan master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general MPI and provides paral-
lel-to-serial/serial-to-parallel conversion, as well as
three 8K data buffers. The BSM also increases test
throughput with a dedicated automatic test-pattern
generator and with compression of the test response
with a signature analysis register. The PC-based
boundary-scan test card/software allows a user to
quickly prototype a boundary-scan test setup.
Table 18. Boundary-Scan Instructions
Code
Instruction
000000
000001
000011
000100
000101
000110
001000
001001
001010
001011
001101
001110
010001
010010
010011
010100
010101
111111
EXTEST
SAMPLE
PRELOAD
RUNBIST
IDCODE
USERCODE
ISC_ENABLE
ISC_PROGRAM
ISC_NOOP
ISC_DISABLE
Boundary-Scan Instructions
ISC_PROGRAM_USERCODE
ISC_READ
The Series 4 boundary-scan circuitry supports a total
of 18 instructions. This includes ten IEEE 1149.1,
1149.2, and 1532/D1 instructions, one optional IEEE
1149.3 instruction, two IEEE 1532/D1 optional instruc-
tions, and five ORCA-defined instructions. There are
also 16 other scan chain instructions that are used only
during factory device testing and will not be discussed
in this data sheet. A 6-bit wide instruction register sup-
ports all the instructions listed in Table 18.
PLC_SCAN_RING1
PLC_SCAN_RING2
PLC_SCAN_RING3
RAM_WRITE
RAM_READ
BYPASS
The BYPASS instruction passes data intentionally from
TDI to TDO after being clocked by TCK.
Lattice Semiconductor
41
Data Sheet
May, 2006
ORCA Series 4 FPGAs
defined internal scan paths using the PLC latches/FFs
and routing interface. The RAM_Write Enable
Special Function Blocks (continued)
(RAM_W) instruction allows the user to serially config-
ure the FPGA through TDI. The RAM_Read Enable
(RAM_R) allows the user to read back RAM contents
on TDO after configuration. The IDCODE instruction
allows the user to capture a 32-bit identification code
that is unique to each device and serially output it at
TDO. The IDCODE format is shown in Table 19.
The external test (EXTEST) instruction allows the inter-
connections between ICs in a system to be tested for
opens and stuck-at faults. If an EXTEST instruction is
performed for the system shown in Figure 25, the con-
nections between U1 and U2 (shown by nets a, b,
and c) can be tested by driving a value onto the given
nets from one device and then determining whether
this same value is seen at the other device. This is
determined by shifting 3 bits of data for each pin (one
for the output value, one for captured input value, and
one for the 3-state value) through a boundary scan reg-
ister (BSR) until each one aligns to the appropriate pin.
Then, based upon the value of the 3-state data bit for
each pin, either the I/O pad is driven to the value given
in the output register of the BSR, or an input signal is
applied at the pin. In either case, the BSR input register
is updated with the input value from the I/O pad, which
allows it to be shifted out TDO. Typically, the user will
use the PRELOAD instruction to shift in the first test
stimulus for the EXTEST instruction. Note that Series 4
boundary scan includes the ability to perform a self-
monitor on each I/O pin by driving out a value from the
output register and checking for this value at the input
register of the same I/O pad.
An optional IEEE 1149.3 instruction RUNBIST has
been implemented. This instruction is used to invoke
the built in self test (BIST) of regular structures like
RAMs, ROMs, FIFOs, etc., and the surrounding ran-
dom logic in the circuit.
The USERCODE instruction shifts out a 32-bit ID seri-
ally at TDO. At powerup, a default value of the IDCODE
with the manufacturer field (11-bits) set to all zeros is
loaded. The user can set this 11-bit value to a user-
defined number during device configuration. It may
also be changed by the ISC_PROGRAM_USERCODE
instruction, described later.
Also implemented in Series 4 devices is the IEEE
1532/D1 standards for in-system configuration for pro-
grammable logic devices. Included are 4 mandatory
and 2 optional instructions defined in the standards.
ISC_ENABLE, ISC_PROGRAM, ISC_NOOP, and
ISC_DISABLE are the four mandatory instructions.
ISC_ENABLE initializes the devices for all subsequent
ISC instructions. The ISC_PROGRAM instruction is
similar to the RAM_WRITE instruction implemented in
all ORCA devices where the user must monitor the
PINITN pin for a high indicating the end of initialization
and a successful configuration can be started. The
ISC_PROGRAM instruction is used to program the
configuration memory through a dedicated ISC_Pdata
register. The ISC_NOOP instruction is user when pro-
gramming multiple devices in parallel. During this mode
TDI and TDO behave like BYPASS. The data shifted
through TDI is shifted out through TDO. However the
output pins remain in control of the BSR unlike
The SAMPLE instruction is useful for system debug-
ging and fault diagnosis by allowing the data at the
FPGA’s I/Os to be observed during normal operation.
The data for all of the I/Os is captured simultaneously
into the BSR, allowing them to be shifted-out TDO to
the test host. Since each I/O buffer in the PIOs is bidi-
rectional, two pieces of data are captured for each I/O
pad: the value at the I/O pad and the value of the 3-
state control signal.
The PRELOAD instruction is used to allow the scan-
ning of the boundary-scan register without causing
interference to the normal operation of the on-chip sys-
tem logic. In turn it allows an initial data pattern to be
placed at the latched parallel outputs of BSR prior to
selection of another boundary scan test operation. For
example, prior to selection of the EXTEST instruction,
data can be loaded onto the latched parallel outputs
using PRELOAD. As soon as the EXTEST instruction
has been transferred to the parallel output of the
instruction register, the preloaded data is driven
through the system output pins. This ensures that
known data, consistent at the board level, is driven
immediately when the EXTEST instruction is entered.
Without PRELOAD, indeterminate data would be
driven until the first scan sequence had been com-
pleted.
BYPASS where they are driven by the system logic.
The ISC_DISABLE is used upon completion of the ISC
programming. No new ISC instructions will be operable
without another ISC_ENABLE instruction.
Optional 1532/D1 instructions include
ISC_PROGRAM_USERCODE.When this instruction is
loaded, the user shifts all 32-bits of a user-defined ID
(LSB first) through TDI. This overwrites any ID previ-
ously loaded into the ID register. This ID can then be
read back through the USERCODE instruction defined
in IEEE 1149.2.
There are six ORCA-defined instructions. The PLC
scan rings 1, 2, and 3 (PSR1, PSR2, PSR3) allow user-
42
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
ISC_READ is similar to the ORCA RAM_Read instruction which allows the user to readback the configuration RAM
contents serially out on TDO. Both must monitor the PDONE signal to determine weather or not configuration is
completed. ISC_READ used a 1-bit register to synchronously readback data coming from the configuration mem-
ory.The readback data is clocked into the ISC_READ data register and then clocked out TDO on the falling edge or
TCK.
Table 19. Series 4E Boundary-Scan Vendor-ID Codes
Device
Version (4 bit)
Part* (10 bit)
Family (6 bit)
Manufacturer (11 bit)
LSB (1 bit)
OR4E02
0000
0011100000
001000
00000011101
1
OR4E04
OR4E06
0000
0000
0001010000
0000110000
001000
001000
00000011101
00000011101
1
1
* PLC array size of FPGA, reverse bit order.
Note: Table assumes version 0.
ORCA Boundary-Scan Circuitry
The bypass instruction uses a single FF, which resyn-
chronizes test data that is not part of the current scan
operation. In a bypass instruction, test data received on
TDI is shifted out of the bypass register to TDO. Since
the BSR (which requires a two FF delay for each pad)
is bypassed, test throughput is increased when devices
that are not part of a test operation are bypassed.
The ORCA Series boundary-scan circuitry includes a
test access port controller (TAPC), instruction register
(IR), boundary-scan register (BSR), and bypass regis-
ter. It also includes circuitry to support the four pre-
defined instructions.
Figure 27 shows a functional diagram of the boundary-
scan circuitry that is implemented in the ORCA Series.
The input pins’ (TMS, TCK, and TDI) locations vary
depending on the part, and the output pin is the dedi-
cated TDO/RD_DATA output pad. Test data in (TDI) is
the serial input data. Test mode select (TMS) controls
the boundary-scan test access port controller (TAPC).
Test clock (TCK) is the test clock on the board.
The boundary-scan logic is enabled before and during
configuration. After configuration, a configuration
option determines whether or not boundary-scan logic
is used.
The 32-bit boundary-scan identification register con-
tains the manufacturer’s ID number, unique part num-
ber, and version (as described earlier). The
identification register is the default source for data on
TDO after RESET if the TAP controller selects the shift-
data-register (SHIFT-DR) instruction. If boundary scan
is not used, TMS, TDI, and TCK become user I/Os, and
TDO is 3-stated or used in the readback operation.
The BSR is a series connection of boundary-scan cells
(BSCs) around the periphery of the IC. Each I/O pad on
the FPGA, except for CCLK, DONE, and the boundary-
scan pins (TCK, TDI, TMS, and TDO), is included in the
BSR. The first BSC in the BSR (connected to TDI) is
located in the first PIO I/O pad on the left of the top side
of the FPGA (PTA PIO). The BSR proceeds clockwise
around the top, right, bottom, and left sides of the array.
The last BSC in the BSR (connected to TDO) is located
on the top of the left side of the array (PL1D).
Lattice Semiconductor
43
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
I/O BUFFERS
DATA REGISTERS
BOUNDARY-SCAN REGISTER
IDCODE/USER CODE REGISTER
PSR1,PSR2,PSR3 REGISTERS (PLCs)
ISC READ/WRITE REGISTERS
DATA
MUX
VDD
CONFIGURATION REGISTER
(RAM_R, RAM_W)
TDI
BYPASS AND ISC_DEFAULT REGISTER
INSTRUCTION DECODER
INSTRUCTION REGISTER
TDO
M
U
X
RESET
CLOCK DR
SHIFT-DR
UPDATE-DR
RESET
VDD
CLOCK IR
SHIFT-IR
UPDATE-IR
TMS
TCK
VDD
VDD
SELECT
ENABLE
TAP
CONTROLLER
PUR
PRGM
5-5768(F).b
Figure 27. ORCA Series Boundary-Scan Circuitry Functional Diagram
ORCA Series TAP Controller (TAPC)
Table 20.TAP Controller Input/Outputs
Symbol
I/O
Function
Test Mode Select
Test Clock
Powerup Reset
BSCAN Reset
Test Logic Reset
Select IR (High); Select-DR (Low)
Test Data Out Enable
Capture/Parallel Load-DR
Capture/Parallel Load-IR
Shift Data Register
Shift Instruction Register
Update/Parallel Load-DR
Update/Parallel Load-IR
The ORCA Series TAP controller (TAPC) is a 1149
compatible test access port controller. The 16 JTAG
state assignments from the IEEE 1149 specification
are used.The TAPC is controlled by TCK and TMS.The
TAPC states are used for loading the IR to allow three
basic functions in testing: providing test stimuli
(Update-DR), test execution (Run-Test/Idle), and
obtaining test responses (Capture-DR). The TAPC
allows the test host to shift in and out both instructions
and test data/results. The inputs and outputs of the
TAPC are provided in the table below. The outputs are
primarily the control signals to the instruction register
and the data register.
TMS
TCK
PUR
I
I
I
I
O
O
O
O
O
O
O
O
O
PRGM
TRESET
Select
Enable
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Update-DR
Update-IR
44
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
The TAPC generates control signals that allow capture, shift, and update operations on the instruction and data
registers. In the capture operation, data is loaded into the register. In the shift operation, the captured data is
shifted out while new data is shifted in. In the update operation, either the instruction register is loaded for instruc-
tion decode, or the boundary-scan register is updated for control of outputs.
The test host generates a test by providing input into the ORCA Series TMS input synchronous with TCK. This
sequences the TAPC through states in order to perform the desired function on the instruction register or a data
register. Figure 28 provides a diagram of the state transitions for the TAPC. The next state is determined by the
TMS input value.
TEST-LOGIC-
RESET
1
0
1
1
1
RUN-TEST/
IDLE
SELECT-
DR-SCAN
SELECT-
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
1
0
0
SHIFT-IR
1
0
0
1
1
EXIT1-DR
0
EXIT1-IR
0
PAUSE-DR
PAUSE-IR
1
EXIT2-DR
1
1
EXIT2-IR
1
0
0
UPDATE-DR
UPDATE-IR
1
0
1
0
5-5370(F)
Figure 28.TAP Controller State Transition Diagram
Boundary-Scan Cells
(p_out), and 3-state (p_ts) signals at the pads. The
BSC consists of three circuits: the bidirectional data
cell is used to access the input and output data, the
capture cell is used to capture the status of the I/O pad,
and the direction control cell is used to access the 3-
state value. All three cells consist of a FF used to shift
scan data which feeds a FF to control the I/O buffer.
The capture cell is connected serially to the bidirec-
tional data cell, which is connected serially to the direc-
tion control cell to form a boundary-scan shift register.
Figure 29 is a diagram of the boundary-scan cell (BSC)
in the ORCA series PIOs. There are four BSCs in each
PIC: one for each pad, except as noted above. The
BSCs are connected serially to form the BSR.The BSC
controls the functionality of the in, out, and 3-state sig-
nals for each I/O pad.
The BSC allows the I/O to function in either the normal
or test mode. Normal mode is defined as when an out-
put buffer receives input from the PLC array and pro-
vides output at the pad or when an input buffer
provides input from the pad to the PLC array. In the test
mode, the BSC executes a boundary-scan operation,
such as shifting in scan data from an upstream BSC in
the BSR, providing test stimuli to the pad, capturing
test data at the pad, etc.
The TAPC signals (capture, update, shiftn, treset, and
TCK) and the MODE signal control the operation of the
BSC. The bidirectional data cell is also controlled by
the high out/low in (HOLI) signal generated by the
direction control cell. When HOLI is low, the bidirec-
tional data cell receives input buffer data into the BSC.
When HOLI is high, the BSC is loaded with functional
data from the PLC.
The primary functions of the BSC are shifting scan data
serially in the BSR and observing input (p_in), output
Lattice Semiconductor
45
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
The MODE signal is generated from the decode of the instruction register. When the MODE signal is high
(EXTEST), the scan data is propagated to the output buffer. When the MODE signal is low (BYPASS or SAMPLE),
functional data from the FPGA’s internal logic is propagated to the output buffer.
The boundary-scan description language (BSDL) is provided for each device in the ORCA Series of FPGAs on the
ispLEVER CD. The BSDL is generated from a device profile, pinout, and other boundary-scan information.
SCAN IN
CAPTURE CELL
0
Q
D
Q
D
INBS (TO FPGA ARRAY)
1
I/O BUFFER
PAD_IN
P_IN
PAD_OUT
BIDIRECTIONAL DATA CELL
0
0
1
0
1
1
Q
D
Q
D
PAD_TS
P_OUT
HOLI
0
0
1
1
Q
D
Q
D
P_TS
DIRECTION CONTROL CELL
SHIFTN/CAPTURE
TCK
SCAN OUT UPDATE/TCK
MODE
5-2844(F).a
Figure 29. Boundary-Scan Cell
Boundary-Scan Timing
To ensure race-free operation, data changes on specific clock edges.The TMS and TDI inputs are clocked in on the
rising edge of TCK, while changes on TDO occur on the falling edge of TCK. In the execution of an EXTEST
instruction, parallel data is output from the BSR to the FPGA pads on the falling edge of TCK. The maximum fre-
quency allowed for TCK is 20 MHz.
Figure 30 shows timing waveforms for an instruction scan operation. The diagram shows the use of TMS to
sequence the TAPC through states. The test host (or BSM) changes data on the falling edge of TCK, and it is
clocked into the DUT on the rising edge.
46
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Special Function Blocks (continued)
TCK
TMS
TDI
5-5971(F)
Figure 30. Instruction Register Scan Timing Diagram
Table 21. Readback Options
Single Function Blocks
Option
Function
Most of the special function blocks perform a specific
dedicated function. These functions are data/configura-
tion readback control, global 3-state control (TS_ALL),
internal oscillator generation, GSRN, and start-up
logic.
0
1
Prohibit Readback
Allow One Readback Only
Allow Unrestricted Number of Readbacks
U
Readback Logic
Readback can be performed via the Series 4 MPI or by
using dedicated FPGA readback controls. If the MPI is
enabled, readback via the dedicated FPGA readback
logic is disabled. Readback using the MPI is discussed
in the MPI section.
The readback logic can be enabled via a bit stream
option or by instantiation of a library readback compo-
nent.
Readback is used to read back the configuration data
and, optionally, the state of the PFU outputs. A read-
back operation can be done while the FPGA is in nor-
mal system operation. The readback operation cannot
be daisy-chained. To use readback, the user selects
options in the bit stream generator in the ispLEVER
development system.
The pins used for dedicated readback are readback
data (RD_DATA), read configuration (RD_CFG), and
configuration clock (CCLK). A readback operation is
initiated by a high-to-low transition on RD_CFG. The
RD_CFG input must remain low during the readback
operation. The readback operation can be restarted at
frame 0 by driving the RD_CFG pin high, applying at
least two rising edges of CCLK, and then driving
RD_CFG low again. One bit of data is shifted out on
RD_DATA at the rising edge of CCLK. The first start bit
of the readback frame is transmitted out several cycles
after the first rising edge of CCLK after RD_CFG is input
low (see the readback timing characteristics table in the
timing characteristics section).To be certain of the start
of the readback frame, the data can be monitored for
the 01 frame start bit pair.
Table 21 provides readback options selected in the bit
stream generator tool. The table provides the number
of times that the configuration data can be read back.
This is intended primarily to give the user control over
the security of the FPGA’s configuration program. The
user can prohibit readback (0), allow a single readback
(1), or allow unrestricted readback (U).
Lattice Semiconductor
47
Data Sheet
May, 2006
ORCA Series 4 FPGAs
The readback frame has an identical format to that of
the configuration data frame, which is discussed later
in the Configuration Data Format section. If LUT mem-
ory is not used as RAM and there is no data capture,
the readback data (not just the format) will be identical
to the configuration data for the same frame. This
eases a bitwise comparison between the configuration
and readback data.The configuration header, including
the length count field, is not part of the readback frame.
The readback frame contains bits in locations not used
in the configuration. These locations need to be
masked out when comparing the configuration and
readback frames. The development system optionally
provides a readback bit stream to compare to readback
data from the FPGA. Also note that if any of the LUTs
are used as RAM and new data is written to them,
these bits will not have the same values as the original
configuration data frame either.
Special Function Blocks (continued)
Readback can be initiated at an address other than
frame 0 via the new MPI control registers (see the MPI
section for more information). In all cases, readback is
performed at sequential addresses from the start
address.
It should be noted that the RD_DATA output pin is also
used as the dedicated boundary-scan output pin, TDO.
If this pin is being used as TDO, the RD_DATA output
from readback can be routed internally to any other pin
desired. The RD_CFG input pin is also used to control
the global 3-state (TS_ALL) function. Before and during
configuration, the TS_ALL signal is always driven by
the RD_CFG input and readback is disabled. After con-
figuration, the selection as to whether this input drives
the readback or global 3-state function is determined
by a set of bit stream options. If used as the RD_CFG
input for readback, the internal TS_ALL input can be
routed internally to be driven by any input pin.
Global 3-State Control (TS_ALL)
To increase the testability of the ORCA Series FPGAs,
the global 3-state function (TS_ALL) disables the
device. The TS_ALL signal is driven from either an
external pin or an internal signal. Before and during
configuration, the TS_ALL signal is driven by the input
pad RD_CFG. After configuration, the TS_ALL signal
can be disabled, driven from the RD_CFG input pad, or
driven by a general routing signal in the upper right cor-
ner. Before configuration, TS_ALL is active-low; after
configuration, the sense of TS_ALL can be inverted.
The readback frame contains the configuration data
and the state of the internal logic. During readback, the
value of all registered PFU and PIO outputs can be
captured. The following options are allowed when
doing a capture of the PFU outputs.
■ Do not capture data (the data written to the RAMs,
usually 0, will be read back).
■ Capture data upon entering readback.
■ Capture data based upon a configurable signal inter-
nal to the FPGA. If this signal is tied to logic 0, cap-
ture RAMs are written continuously.
The following occur when TS_ALL is activated:
■ All of the user I/O output buffers are 3-stated, the
user I/O input buffers are pulled up (with the pull-
down disabled), and the input buffers are configured
with TTL input thresholds.
■ Capture data on either options two or three above.
■ The TDO/RD_DATA output buffer is 3-stated.
■ The RD_CFG, RESET, and PRGM input buffers
remain active with a pull-up.
■ The DONE output buffer is 3-stated, and the input
buffer is pulled up.
48
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
nects all the FPGA elements together with a standard-
ized bus framework. The ESB facilitates
Microprocessor Interface (MPI)
communication among MPI, configuration, EBRs, and
user logic in all the generic FPGA devices. AHB serves
the need for high-performance system-on-chip
(SoC) as well as aligning with current synthesis design
flows. Multiple bus masters optimizes system perfor-
mance by sharing resources between different bus
masters such as the MPI and configuration logic. The
wide data bus configuration of 32-bits with 4-bit parity
supports the high-bandwidth of data-intensive applica-
tions of using the wide on-chip memory. AMBA
enhances a reusable design methodology by defining a
common backbone for IP modules.
The Series 4 FPGAs have a dedicated synchronous
MPI function block. The MPI is programmable to oper-
ate with PowerPC/PowerQUICC MPC860/MPC8260
series microprocessors. The MPI implements an 8-,
16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to
the host processor (PowerPC) that can be used for
configuration and readback of the FPGA as well as for
user-defined data processing and general monitoring
of FPGA functions. In addition to dedicated-function
registers, the MPI bridges to the AMBA embedded sys-
tem bus through which the PowerPC bus master can
access the FPGA configuration logic, EBR and other
user logic. There is also capability to interrupt the host
processor either by a hard interrupt or by having the
host processor poll the MPI and the embedded system
bus.
The ESB is a synchronous bus that is driven by either
the MPI clock, internal oscillator, CCLK (slave configu-
ration modes), TCK (JTAG configuration modes), or by
a user clock from routing. In FPSCs, a clock from the
embedded block can also drive the MPI clock. During
initial configuration and reconfiguration the bus clock is
defaulted to the configuration clock. The post configu-
ration clock source is set during configuration.The user
has the ability to program several slaves through the
user logic interface. Embedded block RAM also inter-
faces seamlessly to the system bus.
The control portion of the MPI is available following
powerup of the FPGA if the mode pins specify MPI
mode, even if the FPGA is not yet configured. The
width of the data port is selectable among 8-, 16-, or
32-bit and the parity bus can be 1-, 2-, or 4-bit. In con-
figuration mode the data and parity bus width are
related to the state of the M[0:3] mode pins. For post-
configuration use, the MPI must be included in the con-
figuration bit stream by using an MPI library element in
your design from the ORCA macro library, or by setting
the bit of the MPI configuration control register prior to
the start of configuration.The user can also enable and
disable the parity bus through the configuration bit
stream. These pads can be used as general I/O when
they are not needed for MPI use.
A single bus arbiter controls the traffic on the bus by
ensuring only one master has access to the bus at any
time. The arbiter monitors a number of different
requests to use the bus and decides which request is
currently the highest priority. The configuration modes
have the highest priority and overrides all normal user
modes. Priority can be programmed between MPI and
user logic at configuration in generic FPGAs. If no pri-
ority is set a round-robin approach is used by granting
the next requesting master in a rotating fixed order.
Table 22 shows the interface signals that are used to
interface Series 4 devices to a PowerPC MPC860/
MPC8260 device. More information is available in the
Series 4 MPI and System Bus application note.
Several interfaces exist between the ESB and other
FPGA elements. The MPI interface acts as a bridge
between the external microprocessor bus and ESB.
The MPI may work in an independent clock domain
from the ESB if the ESB clock is not sourced from the
external microprocessor clock. Pipelined operation
allows high-speed memory interface to the EBR and
peripheral access without the requirement for addi-
tional cycles on the bus. Burst transfers allow optimal
use of the memory interface by giving advance infor-
mation of the nature of the transfers.
The ORCA FPGA is a memory-mapped peripheral to
the PowerPC processor. The MPI interfaces to the
user-programmable FPGA logic using the AMBA
embedded system bus.The MPI has access to a series
of addressable registers made accessible by the AMBA
system bus that provide MPI control and status, config-
uration and readback data transfer, FPGA device iden-
tification, and a dedicated user scratchpad register. All
registers are 8 bits wide. The address map for these
registers and the user-logic address space utilize the
same registers as the AMBA embedded system bus.
Table 23 is a listing of the ESB register file and brief
descriptions. Table 24 shows the system interrupt reg-
isters and Table 25 and Table 26 show the FPGA status
and command registers, all with brief descriptions.
More information is available in the Series 4 MPI and
System Bus application note.
Embedded System Bus (ESB)
Implemented using the open standard, on-chip AMBA-
AHB 2.0 specification bus, the Series 4 devices con-
Lattice Semiconductor
49
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Microprocessor Interface (continued)
Table 22. MPC 860 to ORCA MPI Interconnection
PowerPC
Signal
ORCA Pin
MPI
I/O
Function
Name
D[0:n]
D[0:n]
I/O 8, 16, 32-bit data bus.
DP[0:m]
DP[0:m]
I/O Selectable parity bus width from1, 2, and 4-bit.
A[14:31] PPC_A[14:31]
I
I
I
32-bit MPI address bus.
Transfer start signal.
TS
MPI_STRB
BURST
MPI_BURST
Active-low indicates burst transfer in-progress. High indicates current transfer
not a burst.
—
—
CS0
I
I
Active-low MPI select.
CS1
Active-high MPI select.
CLKOUT
RD/WR
TA
MPI_CLK
MPI_RW
MPI_ACK
MPI_BDIP
I
PowerPC interface clock.
I
Read (high)/write (low) signal.
Active-low transfer acknowledge signal.
O
I
BDIP
Active-low burst transfer in progress signal indicates that the second beat in
front of the current one is requested by the master. Negated before the burst
transfer ends to abort the burst data phase.
Any of
IRQ[7:0]
MPI_IRQ
MPI_TEA
MPI_RTRY
O
O
Active-low interrupt request signal.
TEA
Active-low indicates MPI detects a bus error on the internal system bus for
current transaction.
RETRY
O
I
Requests the MPC860/MPC8260 to relinquish the bus and retry the cycle.
TSZ[0:1] MPI_TSZ[0:1]
Driven to indicate the data transfer size for the transaction (byte, half-word,
word).
50
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Microprocessor Interface (continued)
Table 23. Embedded System Bus/MPI Registers
Register
Byte
Read/Write Initial Value
Description
00
01
02
03
04
03-00
07-04
0B-08
0F-0C
13
RO
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
RO
R/W
RO
RO
RO
RO
RO
RO
RO
RO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32-bit device ID
Scratchpad register
Command register
Status register
Interrupt enable register – MPI
Interrupt enable register – USER
12
11
Interrupt enable register – FPSC (unused for FPGAs)
Interrupt cause register
10
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
14
18
19
1C
17-14
1B-18
1F-1C
23-20
27-24
2B-28
2F-2C
33-30
37-34
3B-38
3F-3C
43—40
47—44
53—50
63—60
67—64
73—70
Readback address register (14 bits)
Readback data register
Configuration data register
Trap address register
Bus error address register
Interrupt vector 1 predefined by configuration bit stream
Interrupt vector 2 predefined by configuration bit stream
Interrupt vector 3 predefined by configuration bit stream
Interrupt vector 4 predefined by configuration bit stream
Interrupt vector 5 predefined by configuration bit stream
Interrupt vector 6 predefined by configuration bit stream
Top-left PPLL
—
Top-left HPLL
—
Top-right PPLL
—
Bottom-left PPLL
—
Bottom-left HPLL
—
Bottom-right PPLL
Note: RO = Read Only, R/W = Read/Write
Table 24. Interrupt Register Space Assignments
Byte
bit
Read/Write
Description
13
12
11
10
7-0
7-0
7-0
R/W
R/W
R/W
Interrupt Enable Register – MPI
Interrupt Enable Register – USER
Interrupt Enable Register – FPSC
Interrupt Cause Registers
USER_IRQ_GENERAL;
USER_IRQ_SLAVE;
USER_IRQ_MASTER;
CFG_IRQ_DATA;
7
6
5
4
3
2
1
0
RO
RO
RO
RO
RO
RO
RO
RO
ERR_FLAG 1
MPI_IRQ
FPSC_IRQ_SLAVE;
FPSC_IRQ_MASTER
Note: RO = Read Only, R/W = Read/Write.
For internal system bus, bit 7 is most significant bit, for MPI bit 0 is most significant bit.
Lattice Semiconductor
51
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Microprocessor Interface (continued)
Table 25. Status Register Space Assignments
Byte bit
Read/Write
Description
0F
0E
7:0
7:0
7
—
Reserved
Reserved
—
OD
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Configuration Write Data Acknowledge
Readback Data Ready
6
5
Unassigned (Zero)
4
Unassigned (Zero)
3
FPSC_BIT_ERR
2
RAM_BIT_ERR
1
Configuration Write Data Size (1, 2, or 4 bytes)
Use with above for HSIZE[1:0] (byte, half-word, word)
Readback Addresses Out of Range
Error Response Received by CFG From System Bus
Error Responses Received by CFG From System Bus
CFG_DATA_LOST
0
0C
7
6
5
4
3
DONE
2
INIT_N
1
ERR_FLAG 1
0
ERR_FLAG 0
Notes: RO = Read Only. For internal system bus, bit 7 is most significant bit, for MPI bit 0 is most significant bit.
Table 26. Command Register Space Assignments
Byte bit Read/Write
Description
0B
0A
09
7:0
7:0
7
—
Reserved
—
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SYS_GSR (GSR Input)
6
SYS_RD_CFG (similar to FPGA pin RD_CFGN, but active high)
PRGM from MPI > (similar to FPGA pin, but active high)
PRGM from USER > (similar to FPGA pin, but active high)
PRGM from FPSC > (similar to FPGA pin, but active high)
LOCK from MPI
5
4
3
2
1
LOCK from USER
0
LOCK from FPSC
08
7
Bus Reset from MPI (resets system bus and registers)
Bus Reset from USER (resets system bus and registers)
Bus Reset from FPSC (resets system bus and registers)
SYS_DAISY
6
5
4
3
REPEAT_RDBK (don't increment readback address)
MPI_USR_ENABLE
2
1
Readback Data Size (1, 2, or 4 bytes)
Use with above for HSIZE[1:0]
0
Note: R/W = Read/Write. For internal system bus; bit 7 is most significant bit, for MPI bit 0 is most significant bit.
52
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Phase-Locked Loops (PLLs)
There are eight PLLs available to perform many clock modification and clock conditioning functions on the Series 4
FPGAs. Six of the PLLs are programmable allowing the user the flexibility to configure the PLL to manipulate the
frequency, phase, and duty cycle of a clock signal. Four of the programmable PLLs (PPLLs) are capable of manipu-
lating and conditioning clocks from 15 MHz to 200 MHz and two others (HPPLLs) are capable of manipulating and
conditioning clocks from 60 MHz to 420 MHz. Frequencies can be adjusted from 1/64x to 64x the input clock fre-
quency. Each programmable PLL provides two outputs that have different multiplication factors with the same
phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An
automatic delay compensation mode is available for phase delay. Each PPLL and HPPLL provides two outputs that
can have programmable (45 degree increments) phase differences.
The PPLLs and HPPLLs can be utilized to eliminate skew between the clock input pad and the internal clock inputs
across the entire device. Both the PPLLS or the HPPLLs can drive onto the primary and secondary clock networks
inside the FPGA. Each can take a clock input from the dedicated pad or differential pair of pads in its corner or from
general routing resources.
Functionality of the PPLLs and HPPLLs is programmed during operation through a control register internal to the
FPGA array or via the configuration bit stream. The embedded system bus enables access to these registers (see
Table 23). There is also a PLL output signal, LOCK, that indicates a stable output clock state.
Table 27. PPLL Specifications
Parameter
Min
Nom
Max
Unit
VDD15
1.425
3.0
–40
2.0
7.5
15
1.5
1.575
3.6
V
V
VDD33
3.3
Operating Temp
—
125
200
420
200
420
70
C
Input Clock Frequency
(No division)
PPLL
—
MHz
HPPLL
PPLL
—
Output Clock Frequency
—
MHz
HPPLL
60
—
—
Input Duty Cycle
30
%
%
Output Duty Cycle
45
50
55
Lock Time
—
<50
—
μs
Frequency Multiplication
Frequency Division
Up to 64x
Down to 1/64x
—
—
Duty Cycle Adjust of Output Clock
Delay Adjust of Output Clock
12.5, 25, 37.5, 50, 62.5, 75, 87.5
0, 45, 90, 135, 180, 225, 270, 315
0, 45, 90, 135, 180, 225, 270, 315
%
degrees
degrees
Phase Shift Between MCLK and NCLK
Additional highly tuned and characterized dedicated phase-locked loops (DPLLs) are included to ease system
designs. These DPLLs meet ITU-T G.811 primary clocking specifications and enable system designers to target
very tightly specified clock conditioning not available in the programmable PPLLs.They also provide enhanced jitter
filtering to reduce the amount of input jitter that is transferred to the PLL output when used in any application.
DPLLs are targeted to low-speed DS1 and E1 networking systems (PLL1) and high-speed SONET/SDH network-
ing STS-3 and STM-1 networking systems (PLL2).
Lattice Semiconductor
53
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Phase-Locked Loops (continued)
Table 28. DS-1/E-1 PLL1 Specifications
Parameter
Min
Nom
Max
Unit
VDD15
VDD33
1.425
3.0
–40
1.0
1.0
30
1.5
3.3
—
1.575
3.6
125
2.5
2.5
70
V
V
Operating Temp
C
Input Clock Frequency
Output Clock Frequency
Input Duty Cycle
Output Duty Cycle
Lock Time
—
MHz
MHz
%
—
—
47
50
53
%
—
<1200
—
μs
A dedicated pin PLL_VF is needed for externally connecting a low pass filter circuit.
This provides the specified DS–1/E–1 PLL operating condition.
PLL_VF
R1
C2
C1
VSS
R1 = 6 kΩ ± 1%
C1 = 100 pF ± 5%
C2 = 0.01 μF ± 5%
0203(F).
Figure 31. PLL_VF External Requirements
54
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Phase-Locked Loops (continued)
Table 29. STS-3/STM-1 PLL2 Specifications
Parameter
Min
Nom
Max
Unit
VDD15
VDD33
1.425
3.0
–40
140
140
30
1.5
3.3
1.575
3.6
125
170
170
70
V
V
Operating Temp
—
C
Input Clock Frequency
Output Clock Frequency
Input Duty Cycle Tolerance
Output Duty Cycle
Lock Time
155.52
155.52
—
MHz
MHz
%
47
50
53
%
—
<50
—
μs
All Series 4 PLLs operate from the VDD33 power supply. Care needs to be taken during board layout to properly iso-
late and filter this power supply. More information about the PLLs is available in the Series 4 FPGA PLL Elements
application note. The location of all eight PLLs on Series 4 FPGAs is shown in Figure 32 and Table 30.
ULPPLL ULHPPLL
URPPLL URPLL1
LLPPLL LLHPPLL
LRPPLL LRPLL2
0045(F)
Figure 32. PLL Naming Scheme
Description
Table 30. Phase-lock Loops Index
Name
[UL][LL][UR][LR]PPLL
[UL][LL]HPPLL
URPLL1
Universal user programmable PLL (15—200 MHz)
Universal user programmable PLL (60—420 MHz)
DS-1/E-1 dedicated PLL
LRPLL2
STS-1/STM-1 dedicated PLL
Lattice Semiconductor
55
Data Sheet
May, 2006
ORCA Series 4 FPGAs
tor when initialization is complete. To synchronize the
configuration of multiple FPGAs, one or more INIT pins
should be wire-ANDed. If INIT is held low by one or
more FPGAs or an external device, the FPGA remains
in the initialization state. INIT can be used to signal that
the FPGAs are not yet initialized. After INIT goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled, and the FPGA enters the configuration
state.
FPGA States of Operation
Prior to becoming operational, the FPGA goes through
a sequence of states, including initialization, configura-
tion, and start-up. Figure 33 outlines these three states.
POWERUP
– POWER-ON TIME DELAY
The high during configuration (HDC), low during config-
uration (LDC), and DONE signals are active outputs in
the FPGA’s initialization and configuration states. HDC,
LDC, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during configuration. For parallel master
configuration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
INITIALIZATION
– CLEAR CONFIGURATION MEMORY
– INIT LOW, HDC HIGH, LDC LOW
RESET,
INIT,
OR
BIT
ERROR
YES
YES
PRGM
LOW
NO
NO
If configuration has begun, an assertion of RESET or
PRGM initiates an abort, returning the FPGA to the ini-
tialization state. The PRGM and RESET pins must be
pulled back high before the FPGA will enter the config-
uration state. During the start-up and operating states,
only the assertion of PRGM causes a reconfiguration.
CONFIGURATION
– M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME WRITTEN
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
RESET
OR
PRGM
LOW
START-UP
In the master configuration modes, the FPGA is the
source of configuration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after INIT goes high.
PRGM
LOW
– ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
OPERATION
5-4529(F).
When configuration is initiated, a counter in the FPGA
is set to 0 and begins to count configuration clock
cycles applied to the FPGA. As each configuration data
frame is supplied to the FPGA, it is internally assem-
bled into data words. Each data word is loaded into the
internal configuration memory. The configuration load-
ing process is complete when the internal length count
equals the loaded length count in the length count field,
and the required end of configuration frame is written.
Figure 33. FPGA States of Operation
Initialization
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When VDD15 and VDD33
reach the voltage at which portions of the FPGA begin
to operate, the I/Os are configured based on the config-
uration mode, as determined by the mode select inputs
M[3:0]. A time-out delay is then initiated to allow the
power supply voltage to stabilize. The INIT and DONE
outputs are low.
During configuration, the PIO and PLC latches/FFs are
held set/reset and the internal SLIC buffers are
3-stated. The combinatorial logic begins to function as
the FPGA is configured. Figure 34 shows the general
waveform of the initialization, configuration, and start-
up states.
At the end of initialization, the default configuration
option is that the configuration RAM is written to a low
state. This prevents internal shorts prior to configura-
tion. As a configuration option, after the first configura-
tion (i.e., at reconfiguration), the user can reconfigure
without clearing the internal configuration RAM first.
The active-low, open-drain initialization signal INIT is
released and must be pulled high by an external resis-
56
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
erly power up without any adverse effects.
FPGA States of Operation (continued)
In cases where the power up ramps are greater than 50
mS, it is recommended that PRGM pin be held low dur-
ing power up. However, this work around is only valid if
the power supplies meet the above mentioned current
and voltage requirements. The assertion of the PRGM
will hold off the device from configuration while the
device stabilizes and will not counter act any internal
power up requirements.
Power Supply Sequencing
FPGAs are CMOS static RAM (SRAM) based program-
mable logic devices. The circuitry that the user designs
for the FPGA is implemented within the FPGA by set-
ting multiple SRAM configuration memory cells. This
unique structure as compared with typical CMOS cir-
cuits lends to having certain powerup voltage and cur-
rent requirements.This section describes these related
power issues for the ORCA Series 4 FPGAs and
FPSCs.
Configuration
The ORCA Series FPGA functionality is determined by
the state of internal configuration RAM. This configura-
tion RAM can be loaded in a number of different
modes. In these configuration modes, the FPGA can
act as a master or a slave of other devices in the sys-
tem. The decision as to which configuration mode to
use is a system design issue. Configuration is dis-
cussed in detail, including the configuration data format
and the configuration modes used to load the configu-
ration data in the FPGA, following a description of the
start-up state.
The flexibility of Series 4 FPGAs lends itself to more
power up considerations as it mixes many power sup-
plies to meet today’s versatile system standards. The
board designer must account for the relationship of the
supplies early in board development. The proper
sequence of supplies insures that the board will not be
troubled with power up issues.
The Series 4 devices have many new design improve-
ments to prevent short-circuit contention. This conten-
tion is typically caused by configuration RAM cells in
the device not all powering up to a Q = 0 RAM state. In
order for this to occur, a minimum current was needed
to push the internal circuitry beyond the initial short-cir-
cuit-like condition to become a full CMOS circuit.
Series 4 has overcome this requirement through many
improvements which have dramatically decreased the
adverse effects of internal power up memory conten-
tion.
Start-Up
After configuration, the FPGA enters the start-up
phase. This phase is the transition between the config-
uration and operational states and begins when the
number of CCLKs received after INIT goes high is
equal to the value of the length count field in the config-
uration frame and when the end of configuration frame
has been written. The system design issue in the start-
up phase is to ensure the user I/Os become active
without inadvertently activating devices in the system
or causing bus contention. A second system design
concern is the timing of the release of global set/reset
of the PLC latches/FFs.
At power up, the internal VDD ramp and the duration of
the ramp will depend on the amount of dynamic current
available from the power supply. If a large amount of
current is available, the voltage ramp seen by the
device will be very fast. When final voltage has been
reached, this high quiescent current is no longer
required. If the available current is limited, the time for
the device power to rise will be longer. The voltage
ramp should be monotonic with very little or no flatten-
ing as the supply ramps up. It is also recommended
that the supply should not rise and fall as it is powering
up as this will cause improper power up behavior.
In Series 4 devices, it is required that the VDD15 supply
pass through its operational threshold voltage of
approximately 1 V before the VDD33 supply reaches its
operational threshold of 2.3 V. The current required by
both VDD15 and VDD33 supplies while it passes
through their operational thresholds is approximately
between 1 and 2 amperes each. The powering of the
VDDIO supplies should be after the VDD15 and VDD33
supplies reach operational levels. This sequence and
supply currents can guarantee that the device will prop-
Lattice Semiconductor
57
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA States of Operation (continued)
VDD15, VDD33
RESET
PRGM
INIT
M[3:0]
CCLK
HDC
LDC
DONE
USER I/O
INTERNAL
RESET
(gsm)
INITIALIZATION
CONFIGURATION
START-UP
OPERATION
5-4482(F)
Figure 34. Initialization/Configuration/Start-Up Waveforms
58
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
An example of using the synchronized modes are the
CCLK_SYNC synchronized start-up mode where
DONE is released on the first CCLK rising edge, C1
(see Figure 35).
FPGA States of Operation (continued)
There are configuration options that control the relative
timing of three events: DONE going high, release of the
set/reset of internal FFs, and user I/Os becoming
active. Figure 35 shows the start-up timing for ORCA
FPGAs. The system designer determines the relative
timing of the I/Os becoming active, DONE going high,
and the release of the set/reset of internal FFs. In the
ORCA Series FPGA, the three events can occur in any
arbitrary sequence. This means that they can occur
before or after each other, or they can occur simulta-
neously.
Since this is a synchronized start-up mode, the open-
drain DONE signal can be held low externally to stop
the occurrence of the other two start-up events. Once
the DONE pin has been released and pulled up to a
high level, the other two start-up events can be pro-
grammed individually to either happen immediately or
after up to four rising edges of CCLK (Di, Di + 1, Di + 2,
Di + 3, Di + 4). The default is for both events to happen
immediately after DONE is released and pulled high.
There are four main start-up modes: CCLK_NOSYNC,
CCLK_SYNC, UCLK_NOSYNC, and UCLK_SYNC.
The only difference between the modes starting with
CCLK and those starting with UCLK is that for the
UCLK modes, a user clock must be supplied to the
start-up logic. The timing of start-up events is then
based upon this user clock, rather than CCLK. The dif-
ference between the SYNC and NOSYNC modes is
that for SYNC mode, the timing of two of the start-up
events, release of the set/reset of internal FFs, and the
I/Os becoming active is triggered by the rise of the
external DONE pin followed by a variable number of
rising clock edges (either CCLK or UCLK). For the
NOSYNC mode, the timing of these two events is
based only on either CCLK or UCLK.
A commonly used design technique is to release
DONE one or more clock cycles before allowing the I/O
to become active. This allows other configuration
devices, such as PROMs, to be disconnected using the
DONE signal so that there is no bus contention when
the I/Os become active. In addition to controlling the
FPGA during start-up, other start-up techniques that
avoid contention include using isolation devices
between the FPGA and other circuits in the system,
reassigning I/O locations, and maintaining I/Os as
3-stated outputs until contentions are resolved.
Each of these start-up options can be selected during
bit stream generation in ispLEVER, using Advanced
Options. For more information, please see the
ispLEVER documentation.
DONE is an open-drain bidirectional pin that may
include an optional (enabled by default) pull-up resistor
to accommodate wired ANDing.The open-drain DONE
signals from multiple FPGAs can be tied together
(ANDed) with a pull-up (internal or external) and used
as an active-high ready signal, an active-low PROM
enable, or a reset to other portions of the system.
When used in SYNC mode, these ANDed DONE pins
can be used to synchronize the other two start-up
events, since they can all be synchronized to the same
external signal. This signal will not rise until all FPGAs
release their DONE pins, allowing the signal to be
pulled high.
Lattice Semiconductor
59
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA States of Operation (continued)
CCLK
PERIOD
ORCA CCLK_NOSYNC
F
DONE
C1
I/O
C2
C2
C2
C3
C3
C3
C4
C4
C4
C1
GSRN
ACTIVE
C1
ORCA CCLK_SYNC
DONE IN
DONE
F
Di + 4
Di + 4
C1, C2, C3, OR C4
I/O
Di Di + 1
Di + 2
Di + 2
Di + 3
Di + 3
GSRN
ACTIVE
Di Di + 1
UCLK
ORCA UCLK_NOSYNC
F
DONE
I/O
C1
U1
U1
U2
U2
U3
U3
U4
U4
GSRN
ACTIVE
U1
U2
U3
U4
ORCA UCLK_SYNC
DONE IN
DONE
I/O
F
C1
U1, U2, U3, OR U4
Di Di + 1 Di + 2 Di + 3 Di + 4
GSRN
ACTIVE
Di Di + 1 Di + 2 Di + 3
UCLK PERIOD
SYNCHRONIZATION UNCERTAINTY
F = FINISHED, NO MORE CLKS REQUIRED.
5-2761(F)
Figure 35. Start-Up Waveforms
60
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
information on how to set these and other configuration
options, please see the ispLEVER documentation.
FPGA States of Operation (continued)
Reconfiguration
Configuration Data Format
To reconfigure the FPGA when the device is operating
in the system, a low pulse is input into PRGM or one of
the program bits in the embedded system bus control
register must be set. The configuration data in the
FPGA is cleared, and the I/Os not used for configura-
tion are 3-stated with a pullup.The FPGA then samples
the mode select inputs and begins reconfiguration.
When reconfiguration is complete, DONE is released,
allowing it to be pulled high.
The ispLEVER Development System interfaces with
front-end design entry tools and provides tools to pro-
duce a fully configured FPGA. This section discusses
using the ispLEVER Development System to generate
configuration RAM data and then provides the details
of the configuration frame format.
Using ispLEVER to Generate Configuration
RAM Data
Partial Reconfiguration
The configuration data bit stream defines the I/O func-
tionality, logic, and interconnections within the FPGA.
The bit stream is generated by the development sys-
tem. The bit stream created by the bit stream genera-
tion tool is a series of 1s and 0s used to write the FPGA
configuration RAM. It can be loaded into the FPGA
using one of the configuration modes discussed later.
All ORCA device families have been designed to allow
a partial reconfiguration of the FPGA at any time. This
is done by setting a bit stream option in the previous
configuration sequence that tells the FPGA to not reset
all of the configuration RAM during a reconfiguration.
Then only the configuration frames that are to be modi-
fied need to be rewritten, thereby reducing the configu-
ration time.
In bit stream generator, the designer selects options
that affect the FPGA’s functionality. Using the output of
the bit stream generator, circuit_name.bit, the devel-
opment system’s download tool can load the configura-
tion data into the ORCA series FPGA evaluation board
from a PC or workstation.
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial reconfiguration is being done. If this is done, the
user must be careful to not cause contention between
the two configurations (the bit stream resident in the
FPGA and the partial reconfiguration bit stream) as the
second reconfiguration bit stream is being loaded.
A download cable that can be used to download from
any PC or workstation supported by ispLEVER is avail-
able. This cable allows download to an FPGA that can
be programmed via the serial configuration interface
(requiring the mode pins to be set) or the JTAG bound-
ary scan interface (not requiring the setting of mode
pins). The lead device can then program other FPGAs
or FPSCs on the board via daisy-chaining.
During a partial re-configuration where the configura-
tion option is set to have the internal logic remain active
during configuration the internal SLJC BIDI signals will
always be 3-stated. Previous families of ORCA FPGAs
would allow the BIDIs to continue to be under user
logic control during a partial re-configuration.
Alternatively, a user can program a PROM (such as a
Serial ROM or a standard EPROM) and load the FPGA
from the PROM. The development system’s PROM
programming tool produces a file in .mcs, .tek or .exo
format.
Other Configuration Options
There are many other configuration options available to
the user that can be set during bit stream generation in
ispLEVER. These include options to enable boundary-
scan and/or the MPI and/or the programmable PLL
blocks, readback options, and options to control and
use the internal oscillator after configuration.
Other useful options that affect the next configuration
(not the current configuration process) include options
to disable the global set/reset during configuration, dis-
able the 3-state of I/Os during configuration, and dis-
able the reset of internal RAMs during configuration to
allow for partial configurations (see above). For more
Lattice Semiconductor
61
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Configuration Data Format (continued)
Configuration Data Frame
Configuration data can be presented to the FPGA in two frame formats: autoincrement and explicit. A detailed
description of the frame formats is shown in Figure 36, Figure 37, and Tables Table 31 and Table 31A. The two
modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream
size, and explicit mode uses an optional address frame. In both cases, the header frame begins with a series of 1s
and a preamble of 0010, followed by a 24-bit length count field representing the total number of configuration
clocks needed to complete the loading of the FPGAs. If only Series 4 devices are used, a second preamble value
of 0100 is supported. If this preamble is found, the Series 4 device will expect an expanded length count field of 32-
bits. This allows more larger Series 4 FPGAs to be configured through daisy-chaining.
Following the header frame is a mandatory ID frame. The ID frame contains data used to determine if the bit
stream is being loaded to the correct type of ORCA FPGA (i.e., a bit stream generated for an OR4E06 is being sent
to an OR4E06). Error checking is always enabled for Series 4 devices through the use of an 8-bit checksum. Fol-
lowing the ID frame is a 16-bit header to select the portion of the device to be configured with the following data. the
options are an FPGA header (shown in Table 32), an embedded RAM header (shown in Table 32A), and an FPSC
embedded block header (not shown).
A configuration data frame follows the header frame. A data frame starts with a 01-start bit pair and ends with
enough 1-stop bit to reach a byte boundary. If subsequent data frames follow the frame address is auto-incre-
mented. If using explicit mode, an address frame can follow a data frame, telling the FPGA at what address to
update the auto-increment counter to for the next data frame. Address frame starts with 00.
Following all data and address frames is the postamble. The format of the postamble is the same as an address
frame with the highest possible address value with the checksum set to all ones, if no other sections of configura-
tion data follow. If another section is to follow, the header starts with 10.
CONFIGURATION DATA
CONFIGURATION DATA
0
0 1 0
0 1
0 1
0 0
PREAMBLE LENGTH
COUNT
ID FRAME
CONFIGURATION
DATA FRAME 1
CONFIGURATION
DATA FRAME 2
POSTAMBLE
CONFIGURATION HEADER
5-5759(F)
Figure 36. Serial Configuration Data Format—Autoincrement Mode
CONFIGURATION DATA
CONFIGURATION DATA
0
0
1
0
0
1
0 0
0 1
0 0
LENGTH
COUNT
PREAMBLE
CONFIGURATION
DATA FRAME 1
ADDRESS
FRAME 1
CONFIGURATION
DATA FRAME 2
ID FRAME
POSTAMBLE
CONFIGURATION HEADER
5-5760(F).a
Figure 37. Serial Configuration Data Format—Explicit Mode
62
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Configuration Data Format (continued)
Table 31. Configuration Frame Format and Contents
Frame
Contents
Description
Preamble for generic FPGA.
11110010
24-bit length count
11111111
Header
Configuration bitstream length.
8-bit trailing header.
0101 1111 1111 1111
44 reserved bits
Part ID
ID frame header.
ID Frame
Reserved bits set to 0.
20-bit part ID.
Checksum
11111111
8-bit checksum.
8 stop bits (high) to separate frames.
This is a new mandatory header for generic portion.
8 stop bits (high) to separate frames.
Address frame header.
1111 0010
11111111
FPGA Header
00
FPGA Address Frame
14-bit address
Checksum
11111111
14-bit address of generic FPGA.
8-bit checksum.
Eight stop bits (high) to separate frames.
Data frame header. same as generic.
01
FPGA Data Frame
Alignment bits
String of 0 bits added to frame to reach a byte bound-
ary.
Data bits
Checksum
Number of data bits depends upon device.
8-bit checksum.
11111111
Eight stop bits (high) to separate frames.
Postamble header, 00 = finish, 10 = more bits coming.
Dummy address.
00 or 10
Postamble for Generic
FPGA
11111111 111111
11111111 11111111
16 stop bits (high).
Table 31A. Configuration Frame Format and Contents for Embedded Block RAM
Frame
RAM Header
Contents
Description
11110001
11111111
00
A mandatory header for RAM bitstream portion.
8 stop bits (high) to separate frames.
Address frame header. same as generic.
6-bit address of RAM blocks.
RAM Address Frame
6-bit address
Checksum
11111111
01
8-bit checksum.
Eight stop bits (high) to separate frames.
Data frame header. same as generic.
Six of 0 bits added to reach a byte boundary.
Exact number of bits in a RAM block.
8-bit checksum.
RAM Data Frame
000000
512x18 data bits
Checksum
11111111
00 or 10
Eight stop bits (high) to separate frames.
Postamble header. 00 = finish, 10 = more bits coming.
Dummy address.
Postamble for RAM
111111
11111111 11111111
16 stop bits (high).
Lattice Semiconductor
63
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Configuration Data Format (continued)
The number of frames, number of bits/frame, total number of bits and the required PROM size for each Series 4
device is shown in Table 32
Table 32. Configuration Frame Size
Devices
OR4E02
1796
OR4E04
2436
OR4E06
3076
Number of Frames
Data Bits/Frame
900
1284
1540
Maximum Configuration Data (Number of bits/frame x Number of frames) 1,616,400 3,127,824 4,737,040
Maximum PROM Size (bits) (add configuration header and postamble) 1,616,648 3,128,072 4,737,288
Bit Stream Error Checking
There are three different types of bit stream error checking performed in the ORCA Series 4 FPGAs:
ID frame, frame alignment, and CRC checking.
The ID data frame is sent to a dedicated location in the FPGA. This ID frame contains a unique code for the device
for which it was generated. This device code is compared to the internal code of the FPGA. Any differences are
flagged as an ID error. This frame is automatically created by the bit stream generation program in ispLEVER.
Each data and address frame in the FPGA begins with a frame start pair of bits and ends with eight stop bits set to
1. If any of the previous stop bits were a 0 when a frame start pair is encountered, it is flagged as a frame alignment
error.
Error checking is also done on the FPGA for each frame by means of a checksum byte. If an error is found on eval-
uation of the checksum byte, then a checksum/parity error is flagged. The checksum is the XOR of all the data
bytes, from the start of frame up to and including the bytes before the checksum. It applies to the ID, address, and
data frames.
When any of the three possible errors occur, the FPGA is forced into an idle state, forcing INIT low. The FPGA will
remain in this state until either the RESET or PRGM pins are asserted The PGRM bits of the MPI control register can
also be used to reset out of the error condition and restart configuration.
If using any of the MPI modes to configure the FPGA, the specific type of bit stream error is written to one of the
MPI registers by the FPGA configuration logic.This same information can also be read from the data register when
in asynchronous peripheral mode.
FPGA Configuration Modes
There are twelve methods for configuring the FPGA as show in Table 33. Eleven of the configuration modes are
selected on the M0, M1, M2, and M3 inputs. The twelfth configuration mode is accessed through the boundary-
scan interface. Some modes are used to select the frequency of the internal oscillator, which is the source for
CCLK in some configuration modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz.
There are three basic FPGA configuration modes: master, slave, and peripheral which includes MPI mode. The
configuration data can be transmitted to the FPGA serially or in parallel bytes. As a master, the FPGA provides the
control signals out to strobe data in. As a slave device, a clock is generated externally and provided into the CCLK
input. In the five peripheral modes, the FPGA acts as a microprocessor peripheral. Table 33 lists the functions of
the configuration mode pins.
64
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
Table 33. Configuration Modes
M3
M2
M1
M0
CCLK
Configuration Mode
Data
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Output. High-frequency.
Output. High-frequency.
Output. High-frequency.
NA
Master Serial
Serial
8-bit
Master Parallel
Asynchronous Peripheral
Reserved
8-bit
NA
Output. Low-frequency.
Input.
Master Serial
Serial
8-bit
Slave Parallel
Output.
MPC860 MPI
8-bit
Output.
MPC860 MPI
16-bit
8-bit
Output. Low-frequency.
Output. Low-frequency.
Output.
Master Parallel
Asynchronous Peripheral
MPC860 MPI
8-bit
32-bit
Serial
Input.
Slave Serial
Master Parallel Mode
The master parallel configuration mode is generally used to interface to industry-standard, byte-wide memory. Fig-
ure 38 provides the connections for master parallel mode. The FPGA outputs an 22-bit address on A[21:0] to mem-
ory and reads 1 byte of configuration data on the rising edge of RCLK. The parallel bytes are internally serialized
starting with the least significant bit, D0. D[7:0] of the FPGA can be connected to D[7:0] of the microprocessor only
if a standard prom file format is used. If a .bit or .rbt file is used from ispLEVER, then the user must mirror the bytes
in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA to D[0:7] of the micro-
processor.
DOUT
CCLK
TO DAISY-
CHAINED
DEVICES
A[17:0]
D[7:0]
A[17:0]
D[7:0]
DONE
EPROM
ORCA
SERIES
FPGA
OE
CE
PRGM
M2
PROGRAM
VDD
HDC
LDC
M1
M0
RCLK
Note: M3 = GND for high-speed CCLK; M3 = VDD for low-frequency CCLK.
5-9738(F).a
Figure 38. Master Parallel Configuration Schematic
In master parallel mode, the starting memory address is 00000 hex, and the FPGA increments the address for each
byte loaded.
Lattice Semiconductor
65
Data Sheet
May, 2006
ORCA Series 4 FPGAs
500 ns low pulse into the FPGA's PRGM input. The
FPGA Configuration Modes (continued)
FPGA’s INIT input is connected to the serial ROMs’
RESET/OE input, which has been programmed to
function with RESET active-low and OE active-high.
The FPGA DONE is routed to the CE pin. The low on
DONE enables the serial ROMs. At the completion of
configuration, the high on the FPGAs DONE disables
the serial ROM.
One master mode FPGA can interface to the memory
and provide configuration data on DOUT to additional
FPGAs in a daisy-chain. The configuration data on
DOUT is provided synchronously with the rising edge
of CCLK. The frequency of the CCLK output is eight
times that of RCLK.
Serial ROMs can also be cascaded to support the con-
figuration of multiple FPGAs or to load a single FPGA
when configuration data requirements exceed the
capacity of a single serial ROM. After the last bit from
the first serial ROM is read, the serial ROM outputs
CEO low and 3-states the DATA output. The next serial
ROM recognizes the low on CE input and outputs con-
figuration data on the DATA output. After configuration
is complete, the FPGA’s DONE output into CE disables
the serial ROMs.
Master Serial Mode
In the master serial mode, the FPGA loads the configu-
ration data from an external serial ROM. The configura-
tion data is either loaded automatically at start-up or on
a PRGM command to reconfigure. Serial PROMs can
be used to configure the FPGA in the master serial
mode.
Configuration in the master serial mode can be done at
powerup and/or upon a configure command. The sys-
tem or the FPGA must activate the serial ROM's
RESET/OE and CE inputs. At powerup, the FPGA and
serial ROM each contain internal power-on reset cir-
cuitry that allows the FPGA to be configured without
the system providing an external signal. The power-on
reset circuitry causes the serial ROM's internal address
pointer to be reset. After powerup, the FPGA automati-
cally enters its initialization phase.
This FPGA/serial ROM interface is not used in applica-
tions in which a serial ROM stores multiple configura-
tion programs. In these applications, the next
configuration program to be loaded is stored at the
ROM location that follows the last address for the previ-
ous configuration program. The reason the interface in
Figure 39 will not work in this application is that the low
output on the INIT signal would reset the serial ROM
address pointer, causing the first configuration to be
reloaded.
The serial ROM/FPGA interface used depends on such
factors as the availability of a system reset pulse, avail-
ability of an intelligent host to generate a configure
command, whether a single serial ROM is used or mul-
tiple serial ROMs are cascaded, whether the serial
ROM contains a single or multiple configuration pro-
grams, etc. Because of differing system requirements
and capabilities, a single FPGA/serial ROM interface is
generally not appropriate for all applications.
In some applications, there can be contention on the
FPGA's DIN pin. During configuration, DIN receives
configuration data, and after configuration, it is a user
I/O. If there is contention, an early DONE at start-up
(selected in ispLEVER) may correct the problem. An
alternative is to use LDC to drive the serial ROM's CE
pin. In order to reduce noise, it is generally better to run
the master serial configuration at 1.25 MHz (M3 pin
tied high), rather than 10 MHz, if possible.
Data is read in the FPGA sequentially from the serial
ROM. The DATA output from the serial ROM is con-
nected directly into the DIN input of the FPGA. The
CCLK output from the FPGA is connected to the CLK
input of the serial ROM. During the configuration pro-
cess, CCLK clocks one data bit on each rising edge.
One FPGA in master serial mode can provide configu-
ration data out on DOUT to additional FPGAs in a
daisy-chain configuration. The configuration data on
DOUT is provided synchronously with the rising edge
of CCLK.
Since the data and clock are direct connects, the
FPGA/serial ROM design task is to use the system or
FPGA to enable the RESET/OE and CE of the serial
ROM(s). There are several methods for enabling the
serial ROM’s RESET/OE and CE inputs. The serial
ROM’s RESET/OE is programmable to function with
RESET active-high and OE active-low or RESET active-
low and OE active-high.
In Figure 39, serial ROMs are cascaded to configure
multiple daisy-chained FPGAs. The host generates a
66
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
TO DAISY-
CHAINED
DEVICES
DOUT
DATA
CLK
DIN
CCLK
CE
DONE
PRGM
RESET/OE
CEO
ORCA
SERIES
FPGA
DATA
CLK
CE
M2
M1
M0
RESET/OE
CEO
TO MORE
SERIAL ROMs
AS NEEDED
PROGRAM
Note: M3 = GND for high-speed CCLK; M3 = VDD for low-frequency CCLK.
5-4456(F).a
Figure 39. Master Serial Configuration Schematic
byte is loaded into the holding register and the shift
register has just started shifting configuration data into
configuration RAM.
Asynchronous Peripheral Mode
Figure 40 shows the connections needed for the asyn-
chronous peripheral mode. In this mode, the FPGA
system interface is similar to that of a microprocessor-
peripheral interface.The microprocessor generates the
control signals to write an 8-bit byte into the FPGA.The
FPGA control inputs include active-low CS0 and active-
high CS1 chip selects and WR and RD inputs. The chip
selects can be cycled or maintained at a static level
during the configuration cycle. Each byte of data is writ-
ten into the FPGA’s D[7:0] input pins. D[7:0] of the
FPGA can be connected to D[7:0] of the microproces-
sor only if a standard prom file format is used. If a .bit
or .rbt file is used from ispLEVER, then the user must
mirror the bytes in the .bit or .rbt file OR leave the .bit or
.rbt file unchanged and connect D[7:0] of the FPGA to
D[0:7] of the microprocessor.
The RDY/BUSY status is also available on the D7 pin by
enabling the chip selects, setting WR high, and apply-
ing RD low, where the RD input provides an output
enable for the D[7:3] when RD is low. The D[2:0] pins
are not enabled to drive when RD is low and, therefore,
only act as input pins in asynchronous peripheral
mode. Optionally, the user can ignore the RDY/BUSY
status and simply wait until the maximum time it would
take for the RDY/BUSY line to go high, indicating the
FPGA is ready for more data, before writing the next
data byte.
The following signals are also available on D[6:3] when
WR is high and RD is low:
■ D[6:5] is a 2-bit configuration bitstream error descrip-
tion flag: 00= no error, 01 = ID error, 10 = checksum
error, 11 = stop bit/frame alignment error.
The FPGA provides an RDY/BUSY status output to indi-
cate that another byte can be loaded. A low on RDY/
BUSY indicates that the double-buffered hold/shift reg-
isters are not ready to receive data, and this pin must
be monitored to go high before another byte of data
can be written. The shortest time RDY/BUSY is low
occurs when a byte is loaded into the hold register and
the shift register is empty, in which case the byte is
immediately transferred to the shift register. The long-
est time for RDY/BUSY to remain low occurs when a
■ D[4:3] is a 2-bit system bus error flag: 00 = no error,
01 = one error occurred, 11 = multiple errors
occurred.
One FPGA in asynchronous peripheral mode can pro-
vide configuration data out on DOUT to additional
FPGAs in a daisy-chain configuration. The configura-
tion data on DOUT is provided synchronously with the
rising edge of CCLK.
Lattice Semiconductor
67
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
DOUT
CCLK
TO DAISY-
CHAINED
DEVICES
PRGM
D[7:0]
8
RDY/BUSY
INIT
DONE
MICRO-
PROCESSOR
ORCA
SERIES
FPGA
ADDRESS
DECODE LOGIC
CS0
CS1
BUS
RD
CONTROLLER
WR
VDD
M2
M1
M0
HDC
LDC
Note: M3 = GND for high-speed CCLK; M3 = VDD for low-frequency CCLK.
5-9739(F).a
Figure 40. Asynchronous Peripheral Configuration
Microprocessor Interface Mode
The built-in MPI in Series 4 FPGAs is designed for use in configuring the FPGA. Figure 41 show the glueless inter-
face for FPGA configuration and readback from the PowerPC processor. When enabled by the mode pins, the MPI
handles all configuration/readback control and handshaking with the host processor. For single FPGA configura-
tion, the host sets the configuration control register MPI_PRGM to one then back to zero and, after reading that the
configuration write data acknowledge register is high, transfers data 8, 16, or 32 bits at a time to the FPGA’s D[#:0]
input pins. If configuring multiple FPGAs through daisy-chain operation is desired, the SYS_DAISY bit must be set
in the configuration control register of the MPI.
The configuration control register offers control bits to enable the interrupt on a bit stream error. The MPI status
register may be used in conjunction with, or in place of, the interrupt request option. The status register contains a
2-bit field to indicate the bit stream error status. A flow chart of the MPI configuration process is shown in Figure 42.
68
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
TSZ[0:1]
RETRY
TEA
MPI_TSZ[0:1]
MPI_RTRY
MPI_TEA
BURST
MPI_BURST
1, 2, 4
DP[0:m]
DP[0:m]
TO DAISY-
CHAINED
DEVICES
DOUT
CCLK
8, 16, 32
D[0:n]
A[14:31]
CLKOUT
RD/WR
TA
D[0:n]
PPC_A[14:31]
MPI_CLK
MPI_RW
MPI_ACK
MPI_BDIP
MPI_IRQ
MPI_STRB
CS0
ORCA
SERIES 4
FPGA
POWERPC
BDIP
IRQx
TS
DONE
INIT
HDC
LDC
CS1
BUS
CONTROLLER
5-9738(F).b
Figure 41. PowerPC/MPI Configuration Schematic
Configuration readback can also be performed via the MPI when it is in user mode. The MPI is enabled in user
mode by setting the MP_USER_ENABLE bit to 1 in the configuration control register prior to the start of configura-
tion or through a configuration option. To perform readback, the host processor writes the 14-bit readback start
address to the readback address registers and sets the SYS_RD_CFG bit to one, then back to zero in the configu-
ration control register. Readback data is returned 8 bits at a time to the readback data register and is valid when the
DATA_RDY bit of the status register is 1. There is no error checking during readback. A flow chart of the MPI read-
back operation is shown in Figure 43. The RD_DATA pin used for dedicated FPGA readback is invalid during MPI
readback.
Lattice Semiconductor
69
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
POWER ON WITH
VALID M[3:0]
WRITE CONFIGURATION
CONTROL REGISTER BITS
READ STATUS REGISTER
NO
INIT = 1?
YES
WRITE CONFIGURATION
DATA REGISTER
READ STATUS REGISTER
YES
YES
DONE
DONE = 1?
NO
BIT STREAM ERROR?
NO
ERROR
NO
DATA_RDY = 1?
YES
WRITE DATA TO
CONFIGURATION DATA REG
5-5763(F)
Figure 42. Configuration Through MPI
70
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
ENABLE MICROPROCESSOR
INTERFACE IN USER MODE
SET READBACK ADDRESS
WRITE RD_CFG TO 0
IN CONTROL REGISTER 1
READ STATUS REGISTER
DATA_RDY = 1?
NO
YES
READ DATA REGISTER
NO
ERROR
DATA = 0xFF?
YES
READ DATA REGISTER
NO
ERROR
DATA = 0xFF?
YES
READ DATA REGISTER
NO
START OF FRAME
FOUND?
ERROR
YES
READ UNTIL END OF FRAME
INCREMENT ADDRESS
COUNTER IN SOFTWARE
YES
NO
FINISHED
READBACK?
WRITE RD_CFG TO 1
IN CONTROL REGISTER 1
STOP
5-5764(F)
Figure 43. Readback Through MPI
Lattice Semiconductor
71
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
Slave Serial Mode
The slave serial mode is primarily used when multiple FPGAs are configured in a daisy-chain (see the Daisy-
Chaining section). It is also used on the FPGA evaluation board that interfaces to the download cable. A device in
the slave serial mode can be used as the lead device in a daisy-chain. Figure 44 shows the connections for the
slave serial configuration mode.
The configuration data is provided into the FPGA’s DIN input synchronous with the configuration clock CCLK input.
After the FPGA has loaded its configuration data, it retransmits the incoming configuration data on DOUT at the ris-
ing edge of CCLK. CCLK is routed into all slave serial mode devices in parallel.
Multiple slave FPGAs can be loaded with identical configurations simultaneously. This is done by loading the con-
figuration data into the DIN inputs in parallel.
TO DAISY-
CHAINED
DEVICES
DOUT
INIT
ORCA
SERIES
FPGA
MICRO-
PROCESSOR
OR
DOWNLOAD
CABLE
PRGM
DONE
CCLK
DIN
VDD
M3
M2
M1
M0
HDC
LDC
5-4485(F).a
Figure 44. Slave Serial Configuration Schematic
Slave Parallel Mode
The slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins
D[7:0] for each CCLK cycle. Due to 8 bits of data being input per CCLK cycle, the DOUT pin does not contain a
valid bit stream for slave parallel mode. As a result, the lead device cannot be used in the slave parallel mode in a
daisy-chain configuration.
Figure 45 is a schematic of the connections for the slave parallel configuration mode. WR and CS0 are active-low
chip select signals, and CS1 is an active-high chip select signal.These chip selects allow the user to configure mul-
tiple FPGAs in slave parallel mode using an 8-bit data bus common to all of the FPGAs. These chip selects can
then be used to select the FPGAs to be configured with a given bit stream.The chip selects must be active for each
valid CCLK cycle until the device has been completely programmed.They can be inactive between cycles but must
meet the setup and hold times for each valid positive CCLK. D[7:0] of the FPGA can be connected to D[7:0] of the
microprocessor only if a standard prom file format is used. If a .bit or .rbt file is used from ispLEVER, then the user
must mirror the bytes in the .bit or .rbt file OR leave the .bit or .rbt file unchanged and connect D[7:0] of the FPGA
to D[0:7] of the microprocessor.
72
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
8
D[7:0]
DONE
INIT
ORCA
SERIES
FPGA
CCLK
MICRO-
PROCESSOR
OR
PRGM
VDD
SYSTEM
CS1
CS0
WR
M3
M2
M1
M0
HDC
LDC
5-4487(F).a
Figure 45. Slave Parallel Configuration Schematic
Daisy-Chaining
Multiple FPGAs can be configured by using a daisy-chain of the FPGAs. Daisy-chaining uses a lead FPGA and one
or more FPGAs configured in slave serial mode. The lead FPGA can be configured in any mode except slave paral-
lel mode.
All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on
positive CCLK and out on positive CCLK edges.
An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received
the appropriate number of data frames so that downstream FPGAs do not receive frame start indications. After
loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its
configuration data frames. The loading of configuration data continues after the lead device has received its config-
uration data if its internal frame bit counter has not reached the length count. When the configuration RAM is full
and the number of bits received is less than the length count field, the FPGA shifts any additional data out on
DOUT.
The configuration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the
positive edge of CCLK. Figure 46 shows the connections for loading multiple FPGAs in a daisy-chain configuration.
The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the config-
uration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an
internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode and MPI mode
device outputs eight CCLKs for each write cycle. If the lead device is configured in slave mode, CCLK must be
routed to the lead device and to all of the daisy-chained devices.
Lattice Semiconductor
73
Data Sheet
May, 2006
ORCA Series 4 FPGAs
FPGA Configuration Modes (continued)
CCLK
CCLK
DIN
CCLK
DIN
DOUT
DOUT
DOUT
A[17:0]
A[17:0]
ORCA
SERIES
FPGA
ORCA
SERIES
FPGA
ORCA
SERIES
FPGA
EPROM
D[7:0]
D[7:0]
DONE
MASTER
SLAVE 1
SLAVE 2
VDD
OE
CE
DONE
PRGM
DONE
PRGM
PRGM
INIT
INIT
INIT
VDD
VDD
PROGRAM
VDD
M2
M1
M0
M3
M2
M1
M0
M3
M2
M1
M0
HDC
LDC
RCLK
HDC
LDC
RCLK
VDD
HDC
LDC
RCLK
5-4488(F).a
Figure 46. Daisy-Chain Configuration Schematic
As seen in Figure 46, the INIT pins for all of the FPGAs are connected together. This is required to guarantee that
powerup and initialization will work correctly. In general, the DONE pins for all of the FPGAs are also connected
together as shown to guarantee that all of the FPGAs enter the start-up state simultaneously. This may not be
required, depending upon the start-up sequence desired.
Daisy-Chaining with Boundary-Scan
Multiple FPGAs can be configured through the JTAG ports by using a daisy-chain of the FPGAs. This daisy-chain-
ing operation is available upon initial configuration after powerup, after a power-on reset, after pulling the program
pin to reset the chip, or during a reconfiguration if the EN_JTAG RAM has been set.
All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in
on the positive TCK and out on the negative TCK edges.
An upstream FPGA that has received the preamble and length count outputs a high on TDO until it has received
the appropriate number of data frames so that downstream FPGAs do not receive frame start bit pairs. After load-
ing and retransmitting the preamble and length count to a daisy-chain of downstream devices, the lead device
loads its configuration data frames.
The loading of configuration data continues after the lead device had received its configuration read into TDI of
downstream devices on the positive edge of TCK, and shifted out TDO on the negative edge of TCK.
74
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series FPGAs include circuitry designed to protect the chips from damaging substrate injection currents
and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed during
storage, handling, and use to avoid exposure to excessive electrical stress.
Table 34. Absolute Maximum Ratings
Parameter
Storage Temperature
Symbol
Tstg
Min
–65
Max
150
Unit
°C
V
Power Supply Voltage with Respect to Ground
VDD33
VDDIO
VDD15
VIN
–0.3
–0.3
–0.3
– 0.3
– 0.3
—
4.2
4.2
V
2.0
V
Input Signal with Respect to Ground
VDDIO + 0.3
VDDIO + 0.3
220
V
Signal Applied to High-impedance Output
Maximum Package Body (Soldering) Temperature
—
V
—
°C
Note: Overshoot and undershoot of -2V to (V
+2) volts is permitted for a duration of <20ns.
IHMAX
Recommended Operating Conditions
Table 35. Recommended Operating Conditions
Parameter
Symbol
VDD33
VDDIO
VDD15
VIN
Min
3.0
Max
3.6
Unit
V
Power Supply Voltage with Respect to Ground
1.4
3.6
V
1.425
– 0.3
–40
1.575
VDDIO + 0.3
125
V
Input Signal with Respect to Ground
Junction Temperature
V
TJ
°C
Note:
1. The maximum recommended junction temperature (TJ) during operation is 125 °C.
2. Timing parameters in this data sheet an ispLEVER are characterized under higher voltage and temperature conditions than the recom-
mended operating conditions in this table.
3. The internal PLLs operate from the VDD33 power supply. This power supply should be well isolated from all other power supplies on the board
for proper operation.
Lattice Semiconductor
75
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Electrical Characteristics
Table 36. Electrical Characteristics
OR4Exx Industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TA < +125 °C;
CL = 30 pF.
OR4Exx
Parameter
Symbol
Test Conditions
Unit
Min
Typ
Max
Input Leakage Current
VDDIO = max, VIN = VSS or VDDIO
– 10
—
10
µA
IL
Standby Current (VDD15): IDDSB15
TA = 25 °C, VDD15 = 1.6 V,
VDD33 = 3.6 V, VDDIO = 3.6 V,
internal oscillator running, no output loads,
inputs VDDIO or VSS (after configuration)
OR4E02
OR4E04
OR4E06
—
—
—
5
10
15
200
200
200
mA
mA
mA
Same conditions except TA = 85 °C
—
—
500
mA
Standby Current (VDD33): IDDSB33
TA = 25 °C, VDD15 = 1.6 V,
VDD33 = 3.6 V, VDDIO = 3.6 V,
internal oscillator stopped, no output loads,
inputs VDDIO or GND (after configuration)
OR4E02
OR4E04
OR4E06
—
—
—
4
7
10
100
100
100
mA
mA
mA
Same conditions except TA = 85 °C
TJ = –40 °C to 125 °C
—
—
—
300
—
mA
V
Data Retention Voltage
(VDD33)
VDR33
VDR15
2.3
Data Retention Voltage
(VDD15)
TJ = –40 °C to 125 °C
1.1
—
—
—
—
—
V
V
V
DC Input Levels
VIL
VIH
Input levels vary per input standard. See the Various
Series 4 IO Application Note for details
Various
Various
DC Output Levels
Output Drive Currents
VOL
VOH
Output levels vary per output standard. See Various
the Series 4 IO Application Note for details
IOL
IOH
Output currents vary per output standard.
See the Series 4 IO Application Note for
details
Various
Various mA
Input Capacitance
Output Capacitance
CIN
COUT
RDONE
RM
TA = 25 °C, VDDIO = 3.6 V,
Test frequency = 1 MHz
—
—
—
—
—
—
—
—
—
—
5
5
pF
pF
kΩ
kΩ
µA
µA
kΩ
kΩ
TA = 25 °C, VDDIO = 3.6 V,
Test frequency = 1 MHz
DONE Pull-up
Resistor*
VDDIO = 3.0 V to 3.6 V, VIN = VSS,
TJ = –40 °C to 125 °C
100
100
14.4
26
—
M[3:0] Pull-up
Resistors*
VDDIO = 3.0 V to 3.6 V, VIN = VSS,
TJ = –40 °C to 125 °C
—
I/O Pad Static Pull-up
Current*
IPU
VDDIO = 3.0 V to 3.6 V, VIN = VSS,
TJ = –40 °C to 125 °C
50.9
103
—
I/O Pad Static
Pull-down Current
IPD
VDDIO = 3.0 V to 3.6 V, VIN = VSS,
TJ = –40 °C to 125 °C
I/O Pad Pull-up
Resistor*
RPU
RPD
VDDIO = 3.0 V to 3.6 V, VIN = VSS,
TJ = –40 °C to 125 °C
100
50
I/O Pad Pull-down
Resistor
VDDIO = 3.0 V to 3.6 V, VIN = VDD,
TJ = –40 °C to 125 °C
—
*
The pull-up resistor will externally pull the pin to a level 1.0 V below VDDIO.
Note: 1. The Standby Current for VDDIO is variable depending upon I/O types. For LVTTL I/O held at VDDIO or GND, this value is typically less
than 1 mA.
76
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
■ Primary: 0.143 mW/MHz + (0.0033mW/MHz x num-
ber of blocks driven)
Power Estimation
A spreadsheet is available in ispLEVER for detailed
power estimates based on circuit implementation
details from ispLEVER and user inputs. A quick esti-
mate of power dissipation for a Series 4 device is now
presented.
■ Secondary: 0.06 mW/MHz + (0.0029mW/MHz x
number of blocks driven)
Clock power is calculated from these equations by mul-
tiplying times the clock frequency in MHz. Note that an
activity factor (i.e., 100% activity) is not used to calcu-
late clock power.
Estimating Power Dissipation
The device I/O power dissipated is the sum of the
power dissipated in the four PIOs in the PIC. This con-
sists of power dissipated by inputs and ac power dissi-
pated by outputs. The power dissipated in each PIO
depends on whether it is configured as an input, out-
put, or input/output. If a PIO is operating as an output,
then there is a power dissipation component for PIN, as
well as POUT. This is because the output feeds back to
the input.
The total operating power dissipated is estimated by
adding the standby (IDDSB), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
PT = Σ PINT + Σ PIO + PCLK
The power dissipated by a LVCMOS2 input buffer is
(VIH = VDD – 0.3 V or higher) estimated as:
The internal operating power is made up of two parts:
clock generation and PFU/EBR/PIO power. The PFU/
EBR/PIO power can be estimated per output based
upon the number of PFU/EBR/PIO outputs switching
when driving a typical fanout (three X6 lines and nine
X1 lines).
PIN = 0.09 mW/MHz
The ac power dissipation from a LVCMOS2 output or
bidirectional is estimated by the following:
2
POUT = (CL + 5.0 pF) x VDD x F Watts
PINT = 0.015 mW/MHz
where the unit for CL (the output capacitive load) is Far-
ads, and the unit for F is Hz.
For each PFU/EBR/PIO output that switches, 0.015
mW/MHz needs to be multiplied times the frequency (in
MHz) that the output switches. Generally, this can be
estimated by using the clock rate multiplied by some
activity factor; for example, 20%.
For all other I/O buffer types other than LVCMOS2, see
the detailed power estimation spreadsheet available in
ispLEVER.
The power dissipated by clocks is due to either global
primary clock networks or secondary/edge clock net-
works. Their power has a fixed component and a vari-
able component based on the number of PFUs, PIOs,
or EBRs that use that clock as follows:
Lattice Semiconductor
77
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics
To define speed grades, the ORCA series part number designation (see Ordering Information) uses a single-digit
number to designate a speed grade. This number is not related to any single ac parameter. Higher numbers indi-
cate a faster set of timing parameters. The actual speed sorting is based on testing the delay in a path consisting of
an input buffer, combinatorial delay through all PLCs in a row, and an output buffer. Other tests are then done to
verify other delay parameters, such as routing delays, setup times to FFs, etc.
The most accurate timing characteristics are reported by the timing analyzer in ispLEVER™ design software. A
timing report provided by the development system after layout divides path delays into logic and routing delays.
The timing analyzer can also provide logic delays prior to layout. While this allows routing budget estimates, there
is wide variance in routing delays associated with different layouts.
The logic timing parameters noted in the Electrical Characteristics section of this data sheet are the same as those
in ispLEVER. In the timing tables that follow, symbol names are generally a concatenation of the PFU operating
mode (as defined in Table 3) and the parameter type. The setup, hold, and propagation delay parameters, defined
below, are designated in the symbol name by the SET, HLD, and DEL characters, respectively. The values given
for the parameters are the same as those used during production testing and speed binning of the devices. The
junction temperature and supply voltage used to characterize the devices are listed in the delay tables and the
delay values in this data sheet are from ispLEVER. Actual delays at nominal temperature and voltage for best-case
processes can be much better than the values given.
It should be noted that the junction temperature used in the tables is generally 85 °C or 100 °C, based on the tem-
perature grade of the device. The junction temperature for the FPGA depends on the power dissipated by the
device, the package thermal characteristics (ΘJA), and the ambient temperature, as calculated in the following
equation and as discussed further in the Package Thermal Characteristics section:
TJmax = TAmax + (P • ΘJA) °C
Note: The user must determine this junction temperature to see if the delays from ispLEVER should be derated
based on the following derating tables.
Table 37—Table 38 provide approximate power supply and junction temperature derating for Series 4 commercial
and industrial devices. The delay values in this data sheet and reported by ispLEVER are shown as 1.00 in the
tables. The method for determining the maximum junction temperature is defined in the Package Thermal Charac-
teristics section. Taken cumulatively, the range of parameter values for best-case vs. worst-case processing, sup-
ply voltage, and junction temperature can approach 3 to 1.
The typical timing path in Series 4 is made up of both 3.3 V (VDDIO and/or VDD33) components and 1.5 V (VDD15)
components. For example, all I/O circuits use VDDIO at the device interface but all internal routing and I/O register
logic use VDD15. Thus actual voltage derating needs to be done based on multiple parameters. A simple approxi-
mation is that 50% of the delay path is due to each of these parameters. All internal paths use VDD15 for logic and
VDD33 for routing, but if VDD33 remains above 3.0 V the internal delays can be assumed to be dependent on
VDD15 derating values only. Note however that temperature derating is approximately the same percentage for all
three supply voltages thus allowing one temperature derating value to be used. For the most accurate results, volt-
age and temperature derating capabilities to be released in ispLEVER should be used.
78
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 37. I/O Derating for 3.3 V I/Os (VDDIO)—Only valid for TTL/CMOS I/Os
Power Supply Voltage
TJ (°C)
TJ (°C)
Commercial
Industrial
3.0 V
3.15 V
3.3 V
3.45 V
3.6 V
–
–40
–25
15
0.82
0.83
0.87
0.91
1.00
1.02
1.05
1.07
0.80
0.81
0.84
0.88
0.97
0.99
1.01
1.03
0.77
0.78
0.81
0.85
0.93
0.96
0.97
0.99
0.75
0.76
0.80
0.82
0.91
0.93
0.95
0.97
0.74
0.75
0.78
0.81
0.88
0.90
0.92
0.94
–40
0
25
40
85
100
115
125
–
100
110
125
Table 38. Internal Derating for 1.5V (VDD15)
Power Supply Voltage
1.500 V
TJ (°C)
Commercial
TJ (°C)
Industrial
1.40 V
1.425 V
1.575 V
1.6 V
–
–40
–25
15
0.87
0.89
0.93
0.96
1.02
1.04
1.05
1.06
0.85
0.87
0.91
0.94
1.00
1.02
1.03
1.05
0.82
0.83
0.87
0.89
0.95
0.97
0.98
1.00
0.79
0.80
0.82
0.85
0.91
0.93
0.94
0.96
0.78
0.79
0.81
0.84
0.90
0.92
0.93
0.95
–40
0
25
40
85
100
115
125
–
100
110
125
In addition to supply voltage, process variation, and operating temperature, circuit and process improvements of
the ORCA Series FPGAs over time will result in significant improvement of the actual performance over those listed
for a speed grade. Even though lower speed grades may still be available, the distribution of yield to timing param-
eters may be several speed grades higher than that designated on a product brand. Design practices need to con-
sider best-case timing parameters (e.g., delays = 0), as well as worst-case timing.
The routing delays are a function of fan-out and the capacitance associated with the CIPs and metal interconnect in
the path. The number of logic elements that can be driven (fan-out) by PFUs is unlimited, although the delay to
reach a valid logic level can exceed timing requirements. It is difficult to make accurate routing delay estimates prior
to design compilation based on fan-out. This is because the CAE software may delete redundant logic inserted by
the designer to reduce fan-out, and/or it may also automatically reduce fan-out by net splitting.
The waveform test points are given in the Input/Output Buffer Measurement Conditions section of this data sheet.
The timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and
the values they reflect are described below.
Lattice Semiconductor
79
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Propagation Delay—The time between the specified reference points. The delays provided are the worst case of
the tphh and tpll delays for noninverting functions, tplh and tphl for inverting functions, and tphz and tplz for 3-state
enable.
Setup Time—The interval immediately preceding the transition of a clock or latch enable signal, during which the
data must be stable to ensure it is recognized as the intended value.
Hold Time—The interval immediately following the transition of a clock or latch enable signal, during which the
data must be held stable to ensure it is recognized as the intended value.
3-State Enable—The time from when a 3-state control signal becomes active and the output pad reaches the
high-impedance state.
Table 39. PFU Timing Parameters
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 ˚C
OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 ˚C
Speed
Parameter
Symbol
Unit
–1
–2
–3
Min Max Min Max Min Max
Combinatorial Delays:
Four-input Variables to LUT out
Five-input Variables to LUT out
Six-input Variables to LUT out
F4_DEL
F5_DEL
F6_DEL
—
—
—
0.66
0.77
1.10
—
—
—
0.55
0.64
0.81
—
—
—
0.50
0.58
0.74
ns
ns
ns
Sequential Delays:
CLK Low Time
CLK High Time
CLKL_MPW 0.36
CLKH_MPW 0.40
—
—
0.35
0.38
—
—
0.32
0.35
—
—
ns
ns
Four-input Variables to Register CLK setup
Five-input Variables to Register CLK setup
Six-input Variables to Register CLK setup
Data In to Register CLK setup
F4_SET
F5_SET
F6_SET
DIN_SET
0.28
0.38
0.71
0.00
—
—
—
—
0.23
0.28
0.63
0.00
—
—
—
—
0.21
0.25
0.57
0.00
—
—
—
—
ns
ns
ns
ns
Four-input Variables from Register CLK hold
Five-input Variables from Register CLK hold
Six-input Variables from Register CLK hold
Data In from Register CLK hold
F4_HLD
F5_HLD
F6_HLD
DIN-HLD
0.00
0.10
0.00
0.25
—
—
—
—
0.00
0.16
0.10
0.24
—
—
—
—
0.00
0.15
0.09
0.22
—
—
—
—
ns
ns
ns
ns
Register CLK to Out
REG_DEL
1.03
—
0.92
—
0.84
—
ns
PFU CLK to Out (REG_DEL) Delay Adjustments
from Cycle Stealing:
One Delay Cell
Two Delay Cells
Three Delay Cells
CYCDEL1
CYCDEL2
CYCDEL3
0.89
1.64
2.43
—
—
—
0.70
1.29
1.98
—
—
—
0.64
1.18
1.80
—
—
—
ns
ns
ns
Note:
A complete listing of PFU Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.
80
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 40. PFU used as Dual-Port RAM: Sync. Write and Sync. or Async. Read Timing Characteristics
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 ˚C
OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 ˚C
Speed
Unit
Parameter
Symbol
-1
-2
-3
Min
Max
Min
Max
Min
Max
Write Operation for RAM Mode:
Maximum Write Clock Frequency
Write Data to CLK Setup Time
Write CLK to Data Out
SMWCLK_FRQ
WD_SET
—
0.00
—
300.00
—
2.21
—
0.00
—
382.00
—
1.89
—
0.00
—
422.00 MHz
—
ns
ns
MEM_DEL
1.71
Async Read Operation for RAM Mode:
Data Out Valid After Address
RA_DEL
—
0.66
—
0.55
—
0.50
ns
Sync Read Operation for RAM Mode:
Maximum Read Clock Frequency
Read CLK to Data Out
SMRCLK_FRQ
REG_DEL
—
—
300.00
1.03
—
—
382.00
0.92
—
—
422.00 MHz
0.84 ns
Note: A complete listing of PFU timing parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.
Lattice Semiconductor
81
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 41. Embedded Block RAM (EBR) Timing Characteristics (512 x 18) Quad-Port RAM Mode
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 ˚C
OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 ˚C
Speed
Parameter
Symbol
Unit
-1
-2
-3
Min
Max
Min
Max
Min
Max
Write Operation for RAM Mode:
Maximum Write Clock Frequency
Write Data to Write Clock Setup Time
Write Address to Write Clock Setup Time
EBRWCLK_FRQ
D*_CKW*_SET
A*_CKW*_SET
—
0.39
0.60
200.0
—
—
—
0.37
0.58
217.0
—
—
—
0.34
0.52
225.0 MHz
—
—
ns
ns
Async Read Operation for RAM Mode:
Data Out Valid After Read Address
EBR_RA_DEL
—
4.72
—
4.48
—
4.06
ns
Sync Read Operation for RAM Mode:
Maximum Read Clock Frequency
Read Address to Read Clock Setup Time AR*_CKR*_SET 0.59
(OUTREG Mode)
EBRRCLK_FRQ
—
200.0
—
—
0.56
217.0
—
—
0.51
225.0 MHz
—
ns
Read Clock to Data Out (IOREG or OUT-
REG modes)
CKR*_Q*_DEL
—
2.39
—
2.27
—
2.06
ns
Note: A complete listing of EBR Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.
Table 42. Supplemental Logic and Interconnect Cell (SLIC) Timing Characteristics
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +85 ˚C
OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, TJ = +100 ˚C
Speed
Parameter
Symbol
Unit
-1
-2
-3
Min Max Min Max Min Max
3-Statable BIDIs
BIDI Buffer Delay
BIDI 3-state Enable/Disable Delay
BUF_DEL
TRI_DEL
—
—
0.35
0.39
—
—
0.35
0.35
—
—
0.32 ns
0.32 ns
Decoder
Decoder Delay (BR[9:8], BL[9:8] to DEC)
DEC_DEL
—
0.89
—
0.81
—
0.73
—
Note: A complete listing of SLIC Timing Parameters can be displayed in ispLEVER. This is a sampling of the key timing parameters.
82
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 43. PIO Input Buffer Timing Characteristics
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +85 ˚C
OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +100 ˚C
Speed
-2
Min Max Min Max
Parameter
Symbol
Unit
-1
-3
Min
Max
Input Delays
Input Rise Time
Input Fall Time
IN_RIS
IN_FAL
—
—
100
100
—
—
100
100
—
—
100
100
ns
ns
Input Delay Adjustments from LVTTL:
LVCMOS2 (2.5 V)
LVCMOS18 (1.8 V)
LVDS
LVDSE
LVPECL
PCI_33 (3.3 V)
PCI_66 (3.3 V)
GTL
GTLP (GTL+)
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
PECL
IN_LVCMOS25
IN_LVCMOS15
IN_LVDS
IN_LVDSE
IN_LVPECL
IN_PCI_33
IN_PCI_66
IN_GTL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.54
1.91
–0.04
0.30
–0.31
0.59
0.59
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.44
1.50
0.10
0.32
–0.21
0.50
0.50
4.68
2.04
–0.06
–0.06
–0.13
–0.13
1.66
1.66
0.69
0.69
0.72
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.40
1.36
0.09
0.29
–0.19
0.45
0.45
4.26
1.86
–0.06
–0.06
–0.12
–0.12
1.51
1.51
0.63
0.63
0.65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.32
1.87
IN_GTLP
IN_HSTL_I
IN_HSTL_II
IN_HSTL_III
IN_HSTL_IV
IN_SSTL2_I
IN_SSTL2_II
IN_SSTL3_I
IN_SSTL3_II
IN_PECL
–0.05
–0.05
–0.20
–0.20
2.28
2.28
0.78
0.78
0.83
Notes:
The delays for all input buffers assume an input rise/fall time of <1 V/ns.
The values in the above table should be used to modify the information in Table 46 through Table 52, which are all based on LVTTL input timing.
Lattice Semiconductor
83
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 44. PIO Output Buffer Timing Characteristics
OR4Exx commercial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +85 ˚C
OR4Exx industrial: VDD15 = 1.425 V, VDD33 = 3.0 V, VDDIO = Min, TJ = +100 ˚C
Speed
-2
Output
Unit Load
(pF)
Parameter
Symbol
-1
-3
Min Max Min Max Min Max
Output Delays
Output Delay Adjustments from OLVTTL_F12:
LVTTL_S6 (Slew Limited, 6 mA)
OUT_LVTTL_S6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2.01
1.25
0.76
0.72
–0.35
6.91
6.23
4.50
4.75
2.38
1.23
3.26
2.09
1.58
1.80
0.61
0.03
0.07
-0.09
–0.57
4.84
4.84
3.22
3.60
1.89
1.89
2.78
2.78
–0.15
–0.15
–0.50
–0.50
0.12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.72
1.06
0.60
0.68
–0.32
5.36
3.90
3.29
3.83
1.86
0.90
2.66
1.69
1.23
1.59
0.50
–0.03
0.00
0.02
–0.55
3.42
3.42
2.45
2.76
1.30
1.30
1.78
1.78
–0.18
–0.18
–0.41
–0.41
0.16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.56
0.97
0.55
0.61
–0.29
4.87
3.55
2.99
3.48
1.69
0.82
2.42
1.54
1.12
1.44
0.45
–0.03
0.00
0.02
–0.50
3.11
3.11
2.23
2.51
1.18
1.18
1.62
1.62
–0.16
–0.16
–0.37
–0.37
0.15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
30 pF
*
LVTTL_S12 (Slew Limited, 12 mA)
LVTTL_S24 (Slew Limited, 24 mA)
LVTTL_F6 (Fast, 6 mA)
LVTTL_F24 (Fast, 24 mA)
LVCMOS18_S6 (Slew Limited, 6 mA)
LVCMOS18_S12 (Slew Limited, 12 mA)
LVCMOS18_S24 (Slew Limited, 24 mA)
LVCMOS18_F6 (Fast, 6 mA)
LVCMOS18_F12 (Fast, 12 mA)
LVCMOS18_F24 (Fast, 24 mA)
LVCMOS2_S6 (Slew Limited, 6 mA)
LVCMOS2_S12 (Slew Limited, 12 mA)
LVCMOS2_S24(Slew Limited, 24 mA)
LVCMOS2_F6 (Fast, 6 mA)
LVCMOS2_F12 (Fast, 12 mA)
LVCMOS2_F24 (Fast, 24 mA)
LVDS
OUT_LVTTL_S12
OUT_LVTTL_S24
OUT_LVTTL_F6
OUT_LVTTL_F24
OUT_CMOS18_S6
OUT_CMOS18_S12
OUT_CMOS18_S24
OUT_CMOS18_F6
OUT_CMOS18_F12
OUT_CMOS18_F24
OUT_CMOS18_S6
OUT_CMOS18_S12
OUT_CMOS18_S24
OUT_CMOS18_F6
OUT_CMOS18_F12
OUT_CMOS18_F24
OUT_LVDS
LVDSE
OUT_LVDSE
*
LVPECL
OUT_LVPECL
*
PCI_33 (3.3V)
OUT_PCI_33
10 pF
10 pF
*
PCI_66 (3.3V)
OUT_PCI_66
GTL
OUT_GTL
GTLP (GTL+)
OUT_GTLP
*
HSTL_I
OUT_HSTL_I
20 pF
20 pF
20 pF
20 pF
30 pF
30 pF
30 pF
30 pF
25 pF
HSTL_II
OUT_HSTL_II
HSTL_III
OUT_HSTL_III
HSTL_IV
OUT_HSTL_IV
OUT_SSTL2_I
SSTL2_I
SSTL2_II
OUT_SSTL2_II
OUT_SSTL3_I
SSTL3_I
SSTL3_II
OUT_SSTL3_II
OUT_PECL
PECL
Output Delay Adjustments from Cycle Stealing (typically used to adjust setup vs. clk->out):
One Delay Cell
Two Delay Cells
Three Delay Cells
OCYCDEL1
OCYCDEL2
OCYCDEL3
0.89
1.64
2.43
—
—
—
0.70
1.29
1.98
—
—
—
0.64
1.18
1.80
—
—
—
ns
ns
ns
—
—
—
*
See the Series 4 PIO Application note for output load conditions on these output buffer types.
Note: The values in the above table should be used to modify the information in Table 46 through Table 48, which are all based on OLVTTL_F12
outputs.
84
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 45. Primary Clock Skew to any PFU or PIO Register
OR4Exx commercial/industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, –40 °C < TJ < +125 °C.
Speed
Description
Device
Unit
-1
-2
-3
Min Max Min Max Min Max
Primary Clock Skew Information (pos edge to
pos edge or neg edge to neg edge)
OR4E02
OR4E04
OR4E06
—
—
—
85
110
120
—
—
—
75
95
105
—
—
—
70
90
100
ps
ps
ps
Primary Clock Skew Information (pos edge to
pos edge, neg edge to neg edge, pos edge to
neg edge or neg edge to pos edge)
OR4E02
OR4E04
OR4E06
—
—
—
265
285
300
—
—
—
190
210
220
—
—
—
180
200
210
ps
ps
ps
Table 46. Secondary Clock to Output Delay without on-chip PLLs (Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +85 °C.;
CL = 30 pF
OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +100 °C.;
CL = 30 pF.
Speed
Description
Device
Unit
-1
-2
-3
Min Max Min Max Min Max
SCLK → OUTPUT Pin (LVTTL-12 mA Fast,
Output within 6 PICs of SCLK input)
All
All
—
—
7.22
0.36
—
—
6.70
0.38
—
—
6.06
0.34
ns
ns
Additional Delay per each extra 6 PICs per
clock route direction.
Notes:
1. Timing is without the use of the phase-locked loops (PLLs).
2. This clock delay is for a fully routed clock tree that uses the secondary clock network. It includes the LVTTL (3.3 V) input clock buffer, the clock
routing to the PIO CLK input, the clock→Q of the FF, and the delay through the LVTTL (3.3 V) data output buffer. An SCLK input clock can be
at any input pin.
3. For timing improvements using other I/O buffer types for the input clock buffer or output data buffer, see Table 53 and Table 55.
PIO FF
D
Q
OUTPUT (30 pF LOAD)
SCLK
5-4846(F).a
Figure 47. Secondary CLK to Output Delay
Lattice Semiconductor
85
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 47. Primary CLK (PCLK) to Output Delay without on-chip PLLs (Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +85 °C; CL = 30 p.
OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +100 °C; CL = 30 p.
Speed
Description
Device
Unit
-1
-2
-3
Min Max Min Max Min Max
PCLK Input Pin →OUTPUT Pin (LVTTL-12 mA Fast) OR4E02
—
—
—
9.00
9.24
9.42
—
—
—
8.03
8.23
8.41
—
—
—
7.28 ns
7.46 ns
7.62 ns
OR4E04
OR4E06
Notes:
1. Timing is without the use of the phase-locked loops (PLLs).
2. This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the LVTTL (3.3 V) input clock buffer delay,
the clock routing to the PIO CLK input, the clock→Q of the FF, and the delay through the LVTTL (3.3 V) data output buffer. The PCLK input
clock is connected at the semi-dedicated primary clock input pins.
3. For timing improvements using other I/O buffer types for the input clock buffer or output data buffer, see Table 53 and Table 55.
PIO FF
D
Q
OUTPUT (30 pF LOAD)
PCLK
5-4846(F).b
Figure 48. Primary Clock to Output Delay
Table 48. Primary CLK (PCLK) to Output Delay using on-chip PLLs (Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +85 °C;
CL = 30 p.
OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +100 °C;
CL = 30 p.
Speed
Description
Device
-1
-2
-3
Unit
Min Max Min Max Min Max
PCLK Input Pin →OUTPUT Pin (LVTTL-12 mA Fast) OR4E02
—
—
—
5.53
5.54
5.53
—
—
—
5.00
5.00
5.00
—
—
—
4.54 ns
4.55 ns
4.54 ns
OR4E04
OR4E06
PLL Delay Adjustments from Cycle Stealing (used to
reduce clk->out by the min delay value shown):
One Delay Cell
Two Delay Cells
Three Delay Cells
All
All
All
—
—
—
0.89
1.64
2.43
—
—
—
0.70
1.29
1.98
—
—
—
0.64 ns
1.18 ns
1.80 ns
Notes:
1. Timing uses the automatic delay compensation mode of the PLLs. The feedback to the PLL is provided by the global system clock routing.
Other delay values are possible by using the phase modifications mode of the PLL instead.
2. This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the LVTTL (3.3 V) input clock buffer delay,
a PLL block, the clock routing to the PIO CLK input, the clock→Q of the FF, and the delay through the LVTTL (3.3 V) data output buffer. The
PCLK input clock is connected at the semi-dedicated PLL input pin.
3. For timing improvements using other I/O buffer types for the input clock buffer or output data buffer, see Table 53 and Table 55.
86
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 49. Secondary CLK (SCLK) Setup/Hold Time without on-chip PLLs (Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +85 °C
OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +100 °C
Speed
Description
Device
-1
-2
-3
Unit
Min
Max
Min
Max
Min
Max
Input to SCLK Setup Time (Input within 6
PICs of SCLK input), Fast Capture Enabled
All
All
All
All
All
All
5.99
—
5.60
—
5.11
—
ns
ns
ns
ns
ns
ns
Input to SCLK Setup Time (Input within 6
PICs of SCLK input), No Input Data Delay
0.00
0.36
0.00
3.12
0.36
—
—
—
—
—
0.00
0.38
0.00
3.09
0.38
—
—
—
—
—
0.00
0.34
0.00
2.79
0.34
—
—
—
—
—
Reduced Setup Time per each extra 6 PICs
per clock route direction.
Input to SCLK Hold Time (Input within 6
PICs of SCLK input), Fast Capture Enabled
Input to SCLK Hold Time (Input within 6
PICs of SCLK input), No Input Data Delay
Additional Hold Time per each extra 6 PICs
per clock route direction.
Input Delay Adjustments from PIO Cycle
Stealing (typically used to reduce setup time
by the min value shown):
One Delay Cell
Two Delay Cells
Three Delay Cells
All
All
All
—
—
—
0.89
1.64
2.43
—
—
—
0.70
1.29
1.98
—
—
—
0.64
1.18
1.80
ns
ns
ns
Notes:
1. The pin-to-pin timing parameters in this table will match ispLEVER if the clock delay multiplier in the setup preference is set to 0.95 for setup
time and 1.05 for hold time.
2. Timing is without the use of the phase-locked loops (PLLs) or PIO input FF cycle stealing delays (which can provide reductions in setup time
at the expense of hold time).
3. This setup/hold time is for a fully routed clock tree that uses the secondary clock network. It includes both the LVTTL (3.3 V) input clock buffer
delay, the clock routing to the PIO CLK input, the setup/hold time of the PIO FF (with the data input delay disabled) and the
LVTTL (3.3 V) input data buffer to PIO FF delay. An SCLK input clock can be at any input pin.
4. For timing improvements using other I/O buffer types for the input clock buffer or input data buffer, see Table 53.
5. The ORT8850H FPSC has slightly reduced performance from the values in this table. ispLEVER will report the actual delay values for all
devices, including the ORT8850H in this arrangement.
PIO FF
INPUT
SCLK
D
Q
5-4847(F).b
Figure 49. Input to Secondary CLK Setup/Hold Time
Lattice Semiconductor
87
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 50. Edge CLK (ECLK) Setup/Hold Time without on-chip PLLs (Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +85°C
OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +100°C
Speed
Device
Unit
Description
-1
-2
-3
Min
Max
Min
Max
Min
Max
Input to ECLK Setup Time (Input within 6
PICs of ECLK input), Fast Capture Enabled
All
All
All
All
All
All
1.13
—
1.17
—
1.08
—
ns
ns
ns
ns
ns
ns
Input to ECLK Setup Time (Input within 6
PICs of ECLK input), Fast Input Enabled
0.00
0.36
0.00
1.68
0.36
—
—
—
—
—
0.00
0.38
0.00
1.65
0.38
—
—
—
—
—
0.00
0.34
0.00
1.40
0.34
—
—
—
—
—
Reduced Setup Time per each extra 6 PICs
per clock route direction.
Input to ECLK Hold Time (Input within 6 PICs
of ECLK input), Fast Capture Enabled
Input to ECLK Hold Time (Input within 6 PICs
of ECLK input), Fast Input Enabled
Additional Hold Time per each extra 6 PICs
per clock route direction.
Input Delay Adjustments from PIO Cycle
Stealing (typically used to reduce setup time
by the min value shown):
One Delay Cell
Two Delay Cells
Three Delay Cells
All
All
All
—
—
—
0.89
1.64
2.43
—
—
—
0.70
1.29
1.98
—
—
—
0.64
1.18
1.80
ns
ns
ns
Notes:
1. The pin-to-pin timing parameters in this table will match ispLEVER if the clock delay multiplier in the setup preference is set to 0.95 for setup
time and 1.05 for hold time.
2. Timing is without the use of the phase-locked loops (PLLs) or PIO input FF cycle stealing delays (which can provide reductions in setup time
at the expense of hold time).
3. This setup/hold time is for a fully routed clock tree that uses the Edge Clock network. It includes both the LVTTL (3.3 V) input clock buffer
delay, the clock routing to the PIO CLK input, the setup/hold time of the PIO FF (with the data input delay disabled) and the LVTTL (3.3 V)
input data buffer to PIO FF delay. Edge clocks can only be connected to one pin or pin-pair per PIC, those ending in the letter C for singled-
ended and those ending in C and D for differential inputs. See the pinout section for more details.
4. For timing improvements using other I/O buffer types for the input clock buffer or input data buffer, see Table 53.
5. The ORT8850H FPSC has slightly reduced performance from the values in this table. ispLEVER will report the actual delay values for all
devices, including the ORT8850H in this arrangement.
PIO FF
INPUT
ECLK
D
Q
5-4847(F).b
Figure 50. Input to Edge CLK Setup/Hold Time
88
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 51. Primary CLK (PCLK) Setup/Hold Time without on-chip PLLs (Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +85°C
OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +100°C
Speed
Device
Unit
Description
-1
-2
-3
Min
Max
Min
Max
Min
Max
Input to PCLK Setup Time, Input Data Delay
Enabled
OR4E02
OR4E04
OR4E06
4.42
4.24
4.11
—
—
—
4.41
4.26
4.14
—
—
—
4.04
3.90
3.80
—
—
—
ns
ns
ns
Input to PCLK Setup Time, No Input Data
Delay
OR4E02
OR4E04
OR4E06
0.00
0.00
0.00
—
—
—
0.00
0.00
0.00
—
—
—
0.00
0.00
0.00
—
—
—
ns
ns
ns
Input to PCLK Hold Time, Input Data Delay
Enabled
OR4E02
OR4E04
OR4E06
0.00
0.00
0.00
—
—
—
0.00
0.00
0.00
—
—
—
0.00
0.00
0.00
—
—
—
ns
ns
ns
Input to PCLK Hold Time, No Input Data
Delay
OR4E02
OR4E04
OR4E06
4.98
5.22
5.43
—
—
—
4.50
4.71
4.89
—
—
—
4.07
4.26
4.42
—
—
—
ns
ns
ns
Input Delay Adjustments from PIO Cycle
Stealing (used to reduce setup time by the
min value shown):
One Delay Cell
Two Delay Cells
Three Delay Cells
All
All
All
—
—
—
0.89
1.64
2.43
—
—
—
0.70
1.29
1.98
—
—
—
0.64
1.18
1.80
ns
ns
ns
Notes:
1. The pin-to-pin timing parameters in this table will match ispLEVER if the clock delay multiplier in the setup preference is set to 0.95 for setup
time and 1.05 for hold time.
2. Timing is without the use of the phase-locked loops (PLLs) or PIO input FF cycle stealing delays (which can provide reductions in setup time
at the expense of hold time).
3. This setup/hold time is for a fully routed clock tree that uses the primary clock network. It includes both the LVTTL (3.3 V) input clock buffer
delay, the clock routing to the PIO CLK input, the setup/hold time of the PIO FF (with the data input delay disabled) and the LVTTL (3.3 V)
input data buffer to PIO FF delay. The PCLK input clock is connected at the semi-dedicated primary clock input pins.
4. For timing improvements using other I/O buffer types for the input clock buffer or input data buffer, see Table 53.
PIO FF
INPUT
PCLK
D
Q
5-4847(F).a
Figure 51. Input to Primary Clock Setup/Hold Time
Lattice Semiconductor
89
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 52. Primary CLK (PCLK) Setup/Hold Time using on-chip PLLs (Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +85 °C
OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +100 °C
Speed
Description
Device
-1
-2
-3
Unit
Min Max Min Max Min Max
Input to PCLK Setup Time, Input Data Delay Enabled
OR4E02
OR4E04
OR4E06
7.92
8.01
8.08
—
—
—
7.48
7.56
7.62
—
—
—
6.81
6.88
6.94
—
—
—
ns
ns
ns
Input to PCLK Setup Time, No Input Data Delay
Input to PCLK Hold Time, Input Data Delay Enabled
Input to PCLK Hold Time, No Input Data Delay
OR4E02
OR4E04
OR4E06
0.00
0.00
0.00
—
—
—
0.00
0.00
0.00
—
—
—
0.00
0.00
0.00
—
—
—
ns
ns
ns
OR4E02
OR4E04
OR4E06
0.00
0.00
0.00
—
—
—
0.00
0.00
0.00
—
—
—
0.00
0.00
0.00
—
—
—
ns
ns
ns
OR4E02
OR4E04
OR4E06
1.55
1.56
1.57
—
—
—
1.50
1.51
1.52
—
—
—
1.36
1.37
1.38
—
—
—
ns
ns
ns
Input Delay Adjustments from PIO Cycle Stealing
(typically used to reduce setup time by the min value
shown):
One Delay Cell
Two Delay Cells
Three Delay Cells
All
All
All
—
—
—
0.89
1.64
2.43
—
—
—
0.70
1.29
1.98
—
—
—
0.64 ns
1.18 ns
1.80 ns
PLL Delay Adjustments from Cycle Stealing (used to
reduce hold by the min delay value shown):
One Delay Cell
Two Delay Cells
Three Delay Cells
All
All
All
—
—
—
0.89
1.64
2.43
—
—
—
0.70
1.29
1.98
—
—
—
0.64 ns
1.18 ns
1.80 ns
Notes:
1. The pin-to-pin timing parameters in this table will match ispLEVER if the clock delay multiplier in the setup preference is set to 0.95 for setup
time and 1.05 for hold time.
2. Timing uses the automatic delay compensation mode of the PLLs. The feedback to the PLL is provided by the global system clock routing.
Other delay values are possible by using the phase modifications mode of the PLL instead.
3. This setup/hold time is for a fully routed clock tree that uses the primary clock network. It includes both the LVTTL (3.3 V) input clock buffer
delay, PLL block, the clock routing to the PIO CLK input, the setup/hold time of the PIO FF (with the data input delay disabled) and the
LVTTL (3.3 V) input data buffer to PIO FF delay. The PCLK input clock is connected at the semi-dedicated PLL input pin.
4. Note that the PIO cycle stealing delay adjustments and the PLL cycle stealing delay adjustments are each attempting to pull the same clock
in both directions. If both are being used, then the difference between them will provide the basis for PIO setup and hold times.
5. For timing improvements using other I/O buffer types for the input clock buffer or input data buffer, see Table 53.
90
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 53. Microprocessor Interface (MPI) Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO= 3.0 V to 3.6 V, –40 °C < TJ < + 125 °C
Parameter
MPI Control (STRB, WR, etc.) to MPI_CLK Setup Time
MPI Address to MPI_CLK Setup Time
MPI Write Data to MPI_CLK Setup Time
All Hold Times
Symbol
Min
7.7
3.5
3.4
0.0
—
Max
—
Unit
ns
MPICTRL_SET
MPIADR_SET
MPIDAT_SET
MPI_HLD
—
ns
—
ns
—
ns
MPI_CLK to MPI Control (TA, TEA, RETRY)
MPI_CLK to MPI Data (8-bit)
MPICTRL_DEL
MPIDAT8_DEL
MPIDAT16_DEL
MPIDAT32_DEL
MPI_CLK_FRQ
8.3
9.2
10.0
10.6
66
ns
—
ns
MPI_CLK to MPI Data (16-bit)
—
ns
MPI_CLK to MPI Data (32-bit)
—
ns
MPI_CLK Frequency
—
MHz
Table 54. Embedded System Bus (ESB) Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO= 3.0 V to 3.6 V, –40 °C < TJ < + 125 °C
Parameter
Symbol
Min
Max
Unit
ESB_CLK Frequency (no wait states)
ESB_CLK Frequency (with wait states)
ESB_CLK_FRQ
ESB_CLK_FRQ
—
—
66
100
MHz
MHz
Table 55. Phase-Locked Loop (PLL) Timing Characteristics
See the section on PLLs in this data sheet and in the PLL application note for timing information.
Table 56. Boundary-Scan Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO= 3.0 V to 3.6 V, –40 °C < TJ < +125 °C;
CL = 30 pF.
Parameter
TDI/TMS to TCK Setup Time
TDI/TMS Hold Time from TCK
TCK Low Time
Symbol
TS
Min
10.0
0.0
Max
—
Unit
ns
TH
—
ns
TCL
25.0
25.0
—
—
ns
TCK High Time
TCH
TD
—
ns
TCK to TDO Delay
10.0
20.0
ns
TCK Frequency
TTCK
—
MHz
TCK
TS
TH
TMS
TDI
TD
TDO
5-6764(F)
Figure 52. Boundary-Scan Timing Diagram
Lattice Semiconductor
91
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Configuration Timing
Table 57. General Configuration Mode Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +125 °C;CL = 30 pF
Parameter
Symbol
Min
Max
Unit
All Configuration Modes
M[3:0] Setup Time to INIT High
TSMODE
THMODE
TRW
0.00
600.00
50.00
50.00
—
—
—
—
ns
ns
ns
ns
M[3:0] Hold Time from INIT High
RESET Pulse Width Low to Start Reconfiguration
PRGM Pulse Width Low to Start Reconfiguration
Master and Asynchronous Peripheral Modes
TPGW
Power-on Reset Delay
CCLK Period (M3 = 0)
TPO
TCCLK
15.70
60.00
480.00
52.40
200.00
1,600.00
ms
ns
ns
(M3 = 1)
Configuration Latency (autoincrement mode, no EBR initialization):
TCL
OR4E02
OR4E04
OR4E06
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
(M3 = 0)
(M3 = 1)
69.7
557.6
187.7
1,501.5
284.2
2,273.9
232.3
1,858.6
625.6
5,004.9
947.5
ms
ms
ms
ms
ms
ms
7,579.7
Microprocessor (MPI) Mode†
Power-on Reset Delay
MPI Clock Period
TPO
TCL
15.70
15.00
52.40
—
ms
Configuration Latency (autoincrement mode, no EBR initialization):
OR4E02
OR4E04
OR4E06
290,412
782,018
1,184,322
—
—
—
MPI clk cycles
MPI clk cycles
MPI clk cycles
Partial Reconfiguration (per data frame):
TPR
OR4E02
OR4E04
OR4E06
225
321
385
—
—
—
MPI clk cycles
MPI clk cycles
MPI clk cycles
Slave Serial Mode
Power-on Reset Delay
CCLK Period
Configuration Latency (autoincrement mode, no EBR initialization):
TPO
TCCLK
TCL
3.90
10.00
13.10
—
ms
ns
OR4E02
OR4E04
OR4E06
11.6
31.3
47.4
—
—
—
ms
ms
ms
Partial Reconfiguration (per data frame):
TPR
OR4E02
OR4E04
OR4E06
9.0
12.8
15.4
—
—
—
μs
μs
μs
* Not applicable to asynchronous peripheral mode.
†Values are shown for the MPI in 32-bit mode with daisy-chaining through the DOUT pin disabled.
92
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 58. General Configuration Mode Timing Characteristics (continued)
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +125 ° C;CL = 30 pF.
Parameter
Slave Parallel Mode
Symbol
Min
Max
Unit
Power-on Reset Delay
CCLK Period:
Configuration Latency (normal mode):
OR4E02
OR4E04
OR4E06
TPO
TCCLK
TCL
3.90
10.00
13.10
—
ms
ns
1.5
3.9
5.9
—
—
—
ms
ms
ms
Partial Reconfiguration (per data frame):
TPR
OR4E02
OR4E04
OR4E06
1.1
1.6
1.9
—
—
—
μs
μs
μs
INIT Timing
INIT High to CCLK Delay:
Slave Parallel
Slave Serial
Master Serial
Master Parallel
TINIT_CCLK
0.50
0.50
0.50
0.50
1.60
1.60
1.60
1.60
μs
μs
μs
μs
Initialization Latency (PRGM high to INIT high):
TIL
OR4E02
OR4E04
OR4E06
0.43
0.58
0.74
1.44
1.95
2.46
ms
ms
ms
INIT High to WR, Asynchronous Peripheral
TINIT_WR
2.00
—
μs
Note: TPO is triggered when VDD33 reaches between 2.7 V and 3.0 V.
Lattice Semiconductor
93
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
VDD15, VDD33
TPO + TIL
PRGM
INIT
TPGW
TIL
TINIT_CLK
TCCLK
CCLK
THMODE
TSMODE
M[3:0]
DONE
TCL
5-4531(F).a
Figure 53. General Configuration Mode Timing Diagram
94
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 59. Master Serial Configuration Mode Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +125 °C;
CL = 30 pF.
Parameter
DIN Setup Time*
Symbol
TS
Min
10.00
0.00
5.00
0.63
—
Max
—
Unit
ns
DIN Hold Time
TH
—
ns
CCLK Frequency (M3 = 0)
CCLK Frequency (M3 = 1)
CCLK to DOUT Delay
FC
16.67
2.08
5.00
MHz
MHz
ns
FC
TD
Note: Serial configuration data is transmitted out on DOUT on the rising edge of CCLK after it is input on DIN.
*
Data gets clocked out from an external serial ROM. The clock to data delay of the serial ROM must be less than the CCLK frequency since
the data available out of the serial ROM must be setup and waiting to be clocked into the FPGA before the next CCLK rising edge.
CCLK
TS
TH
DIN
BIT N
TD
DOUT
BIT N
5-4532(F).b
Figure 54. Master Serial Configuration Mode Timing Diagram
Lattice Semiconductor
95
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 60. Master Parallel Configuration Mode Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ <
+125 °C; CL = 30 pF.
Parameter
RCLK to Address Valid
D[7:0] Setup Time to RCLK High
D[7:0] Hold Time to RCLK High
RCLK Low Time
Symbol
TAV
Min
—
Max
10.00
—
Unit
ns
TS
10.00
0.00
7.00
1.00
—
ns
ns
TH
—
TCL
TCH
TD
7.00
1.00
5.00
CCLK cycles
CCLK cycles
ns
RCLK High Time
CCLK to DOUT
Note:
The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high.
Serial data is transmitted out on DOUT two CCLK cycles after the byte is input on D[7:0].
A[21:0]
TAV
TCH
TCL
RCLK
TS
TH
D[7:0]
CCLK
BYTE N + 1
BYTE N
DOUT
D0
D1
D2
D3
D4
D5
D6 D7
TD
2706(F)
Figure 55. Master Parallel Configuration Mode Timing Diagram
96
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 61. Asynchronous Peripheral Configuration Mode Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ <
+125 °C; CL = 30 pF.
Parameter
WR, CS0, and CS1 Pulse Width
D[7:0] Setup Time:
Symbol
TWR
TS
Min
10.00
0.00
—
Max
Unit
60.00 / 500.00*
ns
—
ns
RDY Delay
TRDY
TB
10.00
8.00
—
ns
RDY Low
1.00
0.00
—
CCLK Periods
Earliest WR After RDY Goes High†
RD to D[7:0] Enable/Disable
CCLK to DOUT
TWR2
TDEN
TD
ns
ns
ns
10.00
5.00
—
*
The smaller delay is for fast asynchronous peripheral mode (mode pins M[3:0]=”0101”) and the larger delay is for slow asynchronous periph-
eral mode (mode pins M[3:0]=”1101”).
† This parameter is valid whether the end of not RDY is determined from the RDY pin or from the D7 pin.
Note: Serial data is transmitted out on DOUT on the rising edge of CCLK after the byte is input on D[7:0].
D[2:0] timing is the same as the write data portion of the D[7:3] waveform because D[2:0] are not enabled by RD.
5-4533(F).b
CS0
CS1
TWR
WR
TS
TWR2
D[7:3]
WRITE DATA
TDEN
TDEN
RD
RDY
TB
TRDY
CCLK
DOUT
TD
D0
D1
D2
PREVIOUS BYTE
D3
D7
Figure 56. Asynchronous Peripheral Configuration Mode Timing Diagram
Lattice Semiconductor
97
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 62. Slave Serial Configuration Mode Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +125 °C; CL = 30 pF.
Parameter
DIN Setup Time
DIN Hold Time
Symbol
TS
Min
5.00
0.00
5.00
5.00
—
Max
—
Unit
ns
TH
—
ns
CCLK High Time
CCLK Low Time
CCLK Frequency
CCLK to DOUT
TCH
TCL
FC
—
ns
—
ns
100.00
5.00
MHz
ns
TD
—
Note: Serial configuration data is transmitted out on DOUT on the rising edge of CCLK after it is input on DIN.
BIT N
DIN
TS
TD
TH
CCLK
DOUT
TCL
TCH
BIT N
5-4535(F).b
Figure 57. Slave Serial Configuration Mode Timing Diagram
98
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Table 63. Slave Parallel Configuration Mode Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ < +125 °C;
CL = 30 pF.
Parameter
CS0, CS1, WR Setup Time
CS0, CS1, WR Hold Time
D[7:0] Setup Time
Symbol
TS1
Min
5.00
2.00
5.00
0.00
5.00
5.00
—
Max
—
Unit
ns
TH1
TS2
—
ns
—
ns
D[7:0] Hold Time
TH2
TCH
TCL
FC
—
ns
CCLK High Time
—
ns
CCLK Low Time
—
ns
CCLK Frequency
100.00
MHz
Note: Daisy-chaining of FPGAs is not supported in this mode.
CS0
CS1
WR
TS1
TCL
TH1
TCH
CCLK
TH2
TS2
D[7:0]
5-2848(F)
Figure 58. Slave Parallel Configuration Mode Timing Diagram
Lattice Semiconductor
99
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Timing Characteristics (continued)
Readback Timing
Table 64. Readback Timing Characteristics
OR4Exx commercial/industrial: VDD15 = 1.4 V to 1.6 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C < TJ
< +125 °C; CL = 30 pF.
Parameter
RD_CFG to CCLK Setup Time
RD_CFG High Width to Abort Readback
CCLK Low Time
Symbol
TS
Min
5.00
2
Max
—
Unit
ns
TRBA
TCL
—
CCLK cycles
5.00
5.00
—
—
ns
ns
CCLK High Time
TCH
FC
—
CCLK Frequency
100.00
5.00
MHz
ns
CCLK to RD_DATA Delay
TD
—
TRBA
RD_CFG
TCL
TS
CCLK
TCH
TD
RD_DATA
BIT 0
BIT 0
BIT 1
5-4536(F)
Figure 59. Readback Timing Diagram
100
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Pin Information
Pin Descriptions
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During configuration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled
after configuration. The pin descriptions in Table 65 and throughout this data sheet show active-low signals with an
overscore. The package pinout tables that follow, show this as a signal ending with _N, for LDC and LDC_N are
equivalent.
Table 65. Pin Descriptions
Symbol
I/O
Description
Dedicated Pins
VDD33
— 3.3 V positive power supply. This power supply is used for 3.3 V configuration RAMs and
internal PLLs. When using PLLs, this power supply should be well isolated from all other
power supplies on the board for proper operation.
VDD15
VDDIO
VSS
— 1.5 V positive power supply for internal logic.
— Positive power supply used by I/O banks.
— Ground.
PTEMP
RESET
I
I
Temperature sensing diode pin. Dedicated input.
During configuration, RESET forces the restart of configuration and a pull-up is enabled.
After configuration, RESET can be used as a general FPGA input or as a direct input,
which causes all PLC latches/FFs to be asynchronously set/reset.
CCLK
DONE
O
I
In the master and asynchronous peripheral modes, CCLK is an output which strobes con-
figuration data in.
In the slave or readback after configuration, CCLK is input synchronous with the data on
DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in
master, peripheral, or system bus modes.
I
As an input, a low level on DONE delays FPGA start-up after configuration.*
O
As an active-high, open-drain output, a high level on this signal indicates that configura-
tion is complete. DONE has an optional pull-up resistor.
PRGM
I
I
PRGM is an active-low input that forces the restart of configuration and resets the bound-
ary-scan circuitry. This pin always has an active pull-up.
RD_CFG
This pin must be held high during device initialization until the INIT pin goes high. This pin
always has an active pull-up.
During configuration, RD_CFG is an active-low input that activates the TS_ALL function
and 3-states all of the I/O.
After configuration, RD_CFG can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream option, a
high-to-low transition on RD_CFG will initiate readback of the configuration data, including
PFU output states, starting with frame address 0.
RD_DATA/TDO
O
O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configura-
tion data out. If used in boundary-scan, TDO is test data out.
CFG_IRQ/MPI_IRQ
During JTAG, slave, master, and asynchronous peripheral configuration assertion on this
CFG_IRQ (active-low) indicates an error or errors for block RAM or FPSC initialization. MPI
active-low interrupt request output, when the MPI is used.
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
Lattice Semiconductor
101
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Pin Information (continued)
Table 65. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins
During powerup and initialization, M0—M3 are used to select the configuration mode with their val-
ues latched on the rising edge of INIT. During configuration, a pull-up is enabled.
M[3:0]
I
After configuration, these pins are user-programmable I/O.*
I/O
Semi-dedicated PLL clock pins. During configuration they are 3-stated with a pull up.
These pins are user-programmable I/O pins if not used by PLLs after configuration.
Pins dedicated for the primary clock. Input pins on the middle of each side with differential pairing.
After configuration these pins are user programmable I/O, if not used for clock inputs.
PLL_CK[0:7][TC]
I
I/O
I
P[TBLR]CLK[1:0][TC]
I/O
I
Before configuration these pins are test data in, test clock, and test mode select inputs. If bound-
ary-scan is enabled after configuration, these pins remain test data in, test clock, and test mode
select inputs. If boundary-scan is not enabled after configuration, all boundery-scan functions are
inhibited once configuration is complete. During configuration, either TCK or TMS must be held at a
logic 1. Each pin has a pull-up enabled during configuration. To enable boundary-scan after config-
uration, a BNDSCAN library element must be instantiated in the user's design and the appropriate
bitgen setting must be enabled in the ispLEVER software.
TDI, TCK, TMS
After configuration, these pins are user-programmable I/O in boundary scan is not used.*
I/O
O
RDY/BUSY/RCLK
During configuration in asynchronous peripheral mode, RDY/RCLK indicates another byte can be
written to the FPGA. If a read operation is done when the device is selected, the same status is also
available on D7 in asynchronous peripheral mode.
During the master parallel configuration mode, RCLK is a read output signal to an external memory.
This output is not normally used.
After configuration this pin is a user-programmable I/O pin.*
I/O
O
High during configuration is output high until configuration is complete. It is used as a control output,
indicating that configuration is not complete.
HDC
LDC
INIT
After configuration, this pin is a user-programmable I/O pin.*
I/O
O
Low during configuration is output low until configuration is complete. It is used as a control output,
indicating that configuration is not complete.
After configuration, this pin is a user-programmable I/O pin.*
I/O
I/O
INIT is a bidirectional signal before and during configuration. During configuration, a pull-up is
enabled, but an external pull-up resistor is recommended. As an active-low open-drain output, INIT
is held low during power stabilization and internal clearing of memory. As an active-low input, INIT
holds the FPGA in the wait-state before the start of configuration.
After configuration, this pin is a user-programmable I/O pin.*
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configu-
ration modes. The FPGA is selected when CS0 is low and CS1 is high. During configuration, a pull-
up is enabled.
CS0, CS1
I
After configuration, if MPI is not used, these pins are user-programmable I/O pins.*
I/O
I
RD is used in the asynchronous peripheral configuration mode. A low on RD changes D[7:3] into a
RD/MPI_STRB
status output. WR and RD should not be used simultaneously. If they are, the write strobe overrides.
This pin is also used as the MPI data transfer strobe. As a status indication, a high indicates ready,
and a low indicates busy.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
I/O
* The FPGA States of Operation section contains more information on how to control these signals during start-up.The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
102
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Pin Information (continued)
Table 65. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
WR/MPI_RW
I
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the
FPGA.
In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write
transfer to the FPGA.
I/O After configuration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.*
PPC_A[14:31]
MPI_BURST
MPI_BDIP
I
I
I
During MPI mode the PPC_A[14:31] are used as the address bus driven by the PowerPC
bus master utilizing the least-significant bits of the PowerPC 32-bit address.
MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high
indicates that the current transfer is not a burst.
MPI_BDIP is driven by the PowerPC processor in MPI mode. Assertion of this pin indicates
that the second beat in front of the current one is requested by the master. Negated before
the burst transfer ends to abort the burst data phase.
MPI_TSZ[0:1]
A[21:0]
I
MPI_TSZ[0:1] signals are driven by the bus master in MPI mode to indicate the data transfer
size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
O During master parallel mode A[21:0] address the configuration EPROMs up to 4M bytes.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
MPI_ACK
MPI_CLK
O In MPI mode this is driven low indicating the MPI received the data on the write cycle or
returned data on a read cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
I
This is the PowerPC synchronous, positive-edge bus clock used for the MPI interface. It can
be a source of the clock for the embedded system bus. If MPI is used this will be the AMBA
bus clock.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
MPI_TEA
O A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on
the internal system bus for the current transaction.
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
O This pin requests the MPC860 to relinquish the bus and retry the cycle.
MPI_RTRY
D[0:31]
I/O If not used for MPI these pins are user-programmable I/O pins after configuration.*
I/O Selectable data bus width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write
transaction and driven by MPI in a read transaction.
I
D[7:0] receive configuration data during master parallel, peripheral, and slave parallel config-
uration modes when WR is low and each pin has a pull-up enabled. During serial configura-
tion modes, D0 is the DIN input.
O D[7:3] output internal status for asynchronous peripheral mode when RD is low.
I/O After configuration, if MPI is not used, the pins are user-programmable I/O pins.*
DP[0:3]
I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15],
DP[2] for D[16:23], and DP[3] for D[24:31].
After configuration, if MPI is not used, the pins are user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up.The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
Lattice Semiconductor
103
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Pin Information (continued)
Table 65. Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
DIN
I
During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. Dur-
ing configuration, a pull-up is enabled.
I/O After configuration, this pin is a user-programmable I/O pin.*
DOUT
O During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave devices. Data out on DOUT changes on the rising edge of CCLK.
After configuration, DOUT is a user-programmable I/O pin.*
I/O
I
TESTCFG
During configuration this pin should be held high, to allow configuration to occur. A pull up is
enabled during configuration.
I/O After configuration, TESTCFG is a user programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up.The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
104
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Pin Information (continued)
Package Compatibility
Table 66 provides the number of user I/Os available for the ORCA Series 4 FPGAs for each available package.
Each package has six dedicated configuration pins.
Table 67 thru Table 69 provide the package pin and pin function for the Series 4 FPGAs and packages. The bond
pad name is identified in the PIO nomeclature used in the ispLEVER design editor. The Bank column provides
information as to which output voltage level bank the given pin is in. The Group column provides information as to
the group of pins the given pin is in. This is used to show which VREF pin is used to provide the reference voltage
for single-ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL) are used in a given
group, then the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
In order to allow pin-for-pin compatible board layouts that can accommodate both devices, some key compatibility
issues include the following.:
■ Shared Control Signals on I/O Registers. The ORCA Series 4 architecture shares clock and control signals
between two adjacent I/O pads. If I/O registers are used, incompatibilities may arise between devices when dif-
ferent clock or control signals are needed on adjacent package pins. This is because one device may allow inde-
pendent clock or control signals on these adjacent pins, while the other may force them to be the same. There
are two ways to avoid this issue.
— Always keep an open bonded pin (non-bonded pins do not count) between pins that require different clock or
control signals. Note that this open pin can be used to connect signals that do not require the use of I/O regis-
ters to meet timing.
— Place and route the design in all target devices to verify they produce valid designs. Note that this method
guarantees the current design, but does not necessarily guard against issues that can occur when design
changes are made that affect I/O registers.
— 2X/4X I/O Shift Registers. If 2X I/O shift registers or 4X I/O shift registers are used in the design, this may
cause incompatibilities between the devices because only the A and C I/Os in a PIC support 2X I/O shift regis-
ters and only A I/Os supports 4X I/O shift register mode. A and C I/Os are shown in the following pinout tables
under the I/O pad columns as those ending in A or C.
■ Edge Clock Input Pins. The input buffers for fast edge clocks are only available at the C I/O pad. The C I/Os are
shown in the following pinout tables under the I/O pad columns as those ending in C.
■ 680 PBGAM Differential I/O Pairs. Note that the OR4E02 device in the 680 PBGAM package has two less dif-
ferential I/O pairs available than the OR4E04 or OR4E06, even though the total number of user I/Os are the same
for all three devices.
Lattice Semiconductor
105
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Pin Information (continued)
Table 66. ORCA Series 4 I/Os Summary
Device
352 PBGA 416 PBGAM
680 PBGAM
OR4E02/OR4E04/OR4E06
User I/O Single Ended
262
128
290
139
466 (4E4, 4E6)
405 (4E2)
User I/O Differential Pairs (LVDS,
LVPECL)
197 (4E4, 4E6)
195 (4E2)
Configuration
7
3
7
3
7
3
Dedicated Function
VDD15
16
8
28
8
48
8
VDD33
VDDIO
24
68
32
48
60
88
VSS
Single-ended/Differential I/O per Bank
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
39/19
26/13
32/16
33/16
34/16
24/12
40/19
34/17
46/22
28/14
35/17
37/18
38/17
24/12
45/21
37/18
68/32
47/20
54/24 (23 for 4E2)
63/22 (21 for 4E2)
52/22
44/18
76/32
62/27
Note: Each VREF pin required reduces the available user I/Os.
As shown in the Pair column, differential pairs and physical locations are numbered within each bank (e.g.,
L19C_A0 is the nineteenth pair in an associated bank). The C indicates complementary differential whereas a T
indicates true differential.The _A0 indicates the physical location of adjacent balls in either the horizontal or vertical
direction. Other physical indicators are as follows:
■ _A1 indicates one ball between pairs.
■ _A2 indicates two balls between pairs.
■ _D0 indicates balls are diagonally adjacent.
■ _D1 indicates diagonally adjacent separated by one physical ball.
VREF pins, shown in the Additional Function column, are associated to the bank and group (e.g., VREF_TL_01 is
the VREF for group one of the top left (TL) bank).
106
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
352-Pin PBGA Pinout
Table 67. 352-Pin PBGA Pinout
VDDIO VREF
Bank Group
Additional
Function
BA352
I/O
OR4E02 OR4E04
OR4E06
Pair
A1
B1
C2
—
—
—
—
—
—
Vss
VDD33
O
Vss
Vss
Vss
—
—
—
—
—
VDD33
VDD33
VDD33
PRD_DA PRD_DAT PRD_DAT
RD_DATA/TDO
TA
A
A
AA23
C1
—
—
—
—
VDD15
I
VDD15
VDD15
VDD15
—
—
—
PRESET PRESET_ PRESET_
_N
PRD_CF PRD_CFG PRD_CFG
G_N _N _N
PPRGR PPRGRM PPRGRM
RESET_N
N
N
D2
D3
—
—
—
—
I
I
RD_CFG_N
PRGRM_N
—
—
M_N
_N
_N
D1
E2
E4
A2
E3
E1
F2
0 (TL)
0 (TL)
0 (TL)
—
—
7
VDDIO0 VDDIO0
VDDIO0
PL2D
PL2C
Vss
VDDIO0
PL2D
PL2C
Vss
—
—
PLL_CK0C/HPPLL
IO
IO
PL2D
PL2C
Vss
L12C_A1
L12T_A1
—
PLL_CK0T/HPPLL
7
—
7
Vss
IO
—
D5
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PL3D
PL3C
PL4D
PL4C
Vss
PL4D
PL4C
PL5D
PL5C
Vss
PL4D
PL4C
PL6D
PL6C
Vss
L13C_A1
L13T_A1
L14C_D1
L14T_D1
—
7
IO
D6
8
IO
HDC
G4
A26
F3
8
IO
LDC_N
—
—
9
Vss
IO
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PL5D
PL5C
PL6D
PL6C
VDDIO0
PL7D
PL7C
PL8D
PL8C
Vss
PL8D
PL8C
VDDIO0
PL9D
PL9C
PL10D
PL10C
Vss
TESTCFG
D7
L15C_A1
L15T_A1
—
F1
9
IO
G2
G1
G3
H2
J4
—
9
VDDIO0 VDDIO0
—
IO
IO
PL5B
PL5A
PL6D
PL6C
Vss
VREF_0_09
A17/PPC_A31
CS0_N
CS1
L16C_A1
L16T_A1
L17C_D1
L17T_D1
—
9
9
IO
9
IO
AC13
H1
H3
AA4
J2
—
10
10
—
10
10
1
Vss
IO
—
0 (TL)
0 (TL)
—
PL7D
PL7C
VDD15
PL7B
PL7A
PL8D
PL8C
PL9D
PL9C
Vss
PL10D
PL10C
VDD15
PL11D
PL11C
PL12D
PL12C
PL13D
PL13C
Vss
PL12D
PL12C
VDD15
PL13D
PL13C
PL14D
PL14C
PL16D
PL16C
Vss
INIT_N
DOUT
L18C_A1
L18T_A1
—
IO
VDD15
IO
—
0 (TL)
0 (TL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
VREF_0_10
A16/PPC_A30
A15/PPC_A29
A14/PPC_A28
VREF_7_01
D4
L19C_A0
L19T_A0
L1C_D0
L1T_D0
L2C_A2
L2T_A2
—
J1
IO
K2
J3
IO
1
IO
K1
K4
AD3
L2
1
IO
1
IO
—
2
Vss
IO
—
RDY/BUSY_N/RCLK
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
PL10D
PL10C
PL14D
PL14C
VDDIO7
PL15D
PL15C
PL18D
PL18C
VDDIO7
PL19D
PL19C
L3C_D0
L3T_D0
—
K3
L1
2
IO
VREF_7_02
—
—
2
VDDIO7 VDDIO7
M2
M1
IO
IO
PL10B
PL10A
A13/PPC_A27
A12/PPC_A26
L4C_A0
L4T_A0
2
Lattice Semiconductor
107
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout
VDDIO VREF
Additional
Function
BA352
I/O
OR4E02 OR4E04
OR4E06
Pair
Bank Group
AE1
L3
—
—
3
Vss
IO
Vss
Vss
Vss
—
—
7 (CL)
7 (CL)
—
PL11B
PL11A
VDD15
PL13D
PL13C
Vss
PL17D
PL17C
VDD15
PL19D
PL19C
Vss
PL21D
PL21C
VDD15
PL23D
PL23C
Vss
A11/PPC_A25
VREF_7_03
—
L5C_D1
L5T_D1
—
N2
3
IO
AC11
M4
N1
—
4
VDD15
IO
RD_N/MPI_STRB_N
7 (CL)
7 (CL)
—
L6C_D2
L6T_D2
—
4
IO
VREF_7_04
—
AE2
M3
P2
—
4
Vss
IO
7 (CL)
7 (CL)
7 (CL)
—
PL14D
PL14C
PL20D
PL20C
VDDIO7
VDD15
Vss
PL24D
PL24C
VDDIO7
VDD15
Vss
PLCK0C
PLCK0T
—
L7C_D1
L7T_D1
—
4
IO
P4
—
—
—
5
VDDIO7 VDDIO7
AC16
AE25
P1
VDD15
Vss
IO
VDD15
Vss
—
—
—
—
—
7 (CL)
7 (CL)
—
PL15D
PL15C
Vss
PL21D
PL21C
Vss
PL25D
PL25C
Vss
A10/PPC_A24
A9/PPC_A23
—
L8C_D1
L8T_D1
—
N3
5
IO
AF1
R2
—
5
Vss
IO
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
PL16D
PL16C
PL17D
PL17C
Vss
PL22D
PL22C
PL24D
PL24C
Vss
PL26D
PL26C
PL28D
PL28C
Vss
A8/PPC_A22
VREF_7_05
PLCK1C
PLCK1T
—
L9C_D0
L9T_D0
L10C_D0
L10T_D0
—
P3
5
IO
R1
6
IO
T2
6
IO
AF25
R3
—
6
Vss
IO
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
6 (BL)
6 (BL)
—
PL17B
PL17A
PL18D
PL18C
PL25D
PL25C
PL26D
PL26C
VDDIO7
PL27D
PL27C
PL28D
PL28C
PL29D
PL29C
PL30D
PL30C
PL31D
PL31C
PL32D
PL32C
Vss
PL29D
PL29C
PL30D
PL30C
VDDIO7
PL32D
PL32C
PL34D
PL34C
PL35D
PL35C
PL36D
PL36C
PL37D
PL37C
PL38D
PL38C
Vss
VREF_7_06
A7/PPC_A21
A6/PPC_A20
A5/PPC_A19
—
L11C_D1
L11T_D1
L12C_D1
L12T_D1
—
T1
6
IO
R4
6
IO
U2
6
IO
T3
—
7
VDDIO7 VDDIO7
U1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Vss
IO
IO
IO
PL19D
PL19C
PL20D
PL20C
PL20B
PL20A
PL21D
PL21C
PL21B
PL21A
PL22D
PL22C
Vss
WR_N/MPI_RW
VREF_7_07
A4/PPC_A18
VREF_7_08
A3/PPC_A17
A2/PPC_A16
A1/PPC_A15
A0/PPC_A14
DP0
L13C_A2
L13T_A2
L14C_D1
L14T_D1
L15C_D0
L15T_D0
L16C_D1
L16T_D1
L17C_D1
L17T_D1
L1C_D1
L1T_D1
—
U4
7
V2
8
U3
8
V1
8
W2
W1
V3
8
8
8
Y2
8
W4
Y1
8
DP1
1
D8
W3
B25
AA2
Y4
1
VREF_6_01
—
—
1
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
PL22B
PL22A
PL23C
PL33D
PL33C
PL34C
VDDIO6
PL35B
PL35A
PL39D
PL39C
PL40C
VDDIO6
PL42D
PL42C
D9
L2C_D1
L2T_D1
—
1
D10
AA1
Y3
2
VREF_6_02
—
—
3
VDDIO6 VDDIO6
—
AB2
AB1
IO
IO
PL24D
PL24C
D11
L3C_A0
L3T_A0
3
D12
108
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout
VDDIO VREF
Additional
Function
BA352
I/O
OR4E02 OR4E04
OR4E06
Pair
Bank Group
B26
AA3
AC2
C24
AB4
AC1
C3
—
—
3
Vss
IO
Vss
PL25D
PL25C
Vss
Vss
PL36B
PL36A
Vss
Vss
PL44D
PL44C
Vss
—
VREF_6_03
D13
—
L4C_D1
L4T_D1
—
6 (BL)
6 (BL)
—
3
IO
—
4
Vss
IO
—
PLL_CK7C/HPPLL
6 (BL)
6 (BL)
—
PL27D
PL27C
Vss
PL39D
PL39C
Vss
PL47D
PL47C
Vss
L5C_D2
L5T_D2
—
PLL_CK7T/HPPLL
4
IO
—
—
—
—
—
—
—
—
—
—
5
Vss
Vss
I
—
D14
AB3
AD2
AC21
AC3
AD1
D19
AF2
AC6
AE3
AF3
AE4
AD4
AF4
D23
AE5
AC5
AD5
AF5
AE6
AC7
AD6
D4
—
Vss
Vss
Vss
—
—
—
PTEMP
PTEMP
VDDIO6
VDD15
PTEMP
VDDIO6
VDD15
LVDS_R
VDD33
Vss
PTEMP
—
6 (BL)
—
VDDIO6 VDDIO6
—
—
VDD15
IO
VDD15
—
—
—
LVDS_R LVDS_R
LVDS_R
—
—
VDD33
Vss
VDD33
VDD15
IO
VDD33
Vss
VDD33
Vss
—
—
—
—
—
—
VDD33
VDD15
PB2A
PB2C
PB2D
PB3C
PB3D
Vss
VDD33
VDD15
PB2A
PB2C
PB2D
PB4A
PB4B
Vss
VDD33
VDD15
PB2A
PB2C
PB2D
PB4C
PB4D
Vss
—
—
—
—
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
DP2
—
PLL_CK6T/PPLL
5
IO
L6T_A0
L6C_A0
L7T_A1
L7C_A1
—
PLL_CK6C/PPLL
5
IO
5
IO
VREF_6_05
5
IO
DP3
—
—
6
Vss
IO
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
PB4C
PB4D
PB5C
PB5D
VDDIO6
PB6C
PB6D
PB7C
PB7D
Vss
PB6C
PB6D
VDDIO6
PB8C
PB8D
PB9C
PB9D
Vss
VREF_6_06
D14
L8T_A1
L8C_A1
—
6
IO
—
7
VDDIO6 VDDIO6
—
IO
IO
IO
IO
Vss
IO
IO
IO
IO
IO
IO
Vss
IO
IO
IO
IO
IO
IO
PB5C
PB5D
PB6A
PB6B
Vss
D15
L9T_D0
L9C_D0
L10T_D0
L10C_D0
—
7
D16
7
D17
7
D18
—
7
—
AF6
AE7
AF7
AD7
AE8
AC9
D9
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
Vss
PB8C
PB8D
PB9C
PB9D
PB10C
PB10D
Vss
PB10C
PB10D
PB11C
PB11D
PB12C
PB12D
Vss
VREF_6_07
D19
L11T_D0
L11C_D0
L12T_A1
L12C_A1
L13T_D1
L13C_D1
—
7
8
D20
8
D21
8
VREF_6_08
D22
8
—
9
—
AF8
AD8
AE9
AF9
6 (BL)
6 (BL)
6 (BL)
6 (BL)
PB8C
PB8D
PB9C
PB9D
PB10C
PB10D
PB11C
PB11D
PB12C
PB12D
PB13C
PB13D
VDDIO6
PB13C
PB13D
PB14C
PB14D
PB16C
PB16D
VDDIO6
D23
L14T_A1
L14C_A1
L15T_A0
L15C_A0
L16T_D0
L16C_D0
—
9
D24
9
VREF_6_09
D25
9
AE10 6 (BL)
AD9 6 (BL)
AF10 6 (BL)
10
10
—
D26
D27
VDDIO6 VDDIO6
—
Lattice Semiconductor
109
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout
VDDIO VREF
Additional
Function
BA352
I/O
OR4E02 OR4E04
OR4E06
Pair
Bank Group
AC10 6 (BL)
AE11 6 (BL)
AD10 6 (BL)
AF11 6 (BL)
AE12 6 (BL)
AF12 6 (BL)
AD11 5 (BC)
AE13 5 (BC)
10
10
11
11
11
11
1
IO
IO
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
VDD15
PB13C
PB13D
Vss
PB14C
PB14D
PB15C
PB15D
PB16C
PB16D
PB17C
PB17D
VDD15
PB18C
PB18D
Vss
PB18C
PB18D
PB19C
PB19D
PB20C
PB20D
PB21C
PB21D
VDD15
PB22C
PB22D
Vss
VREF_6_10
L17T_D1
L17C_D1
L18T_D1
L18C_D1
L19T_A0
L19C_A0
L1T_D1
L1C_D1
—
D28
IO
D29
IO
D30
IO
VREF_6_11
IO
D31
IO
—
1
IO
—
D11
—
—
1
VDD15
IO
—
AC12 5 (BC)
AF13 5 (BC)
VREF_5_01
L2T_D2
L2C_D2
—
1
IO
—
H4
—
—
2
Vss
IO
—
AD12 5 (BC)
AE14 5 (BC)
AC14 5 (BC)
AF14 5 (BC)
AD13 5 (BC)
PB14C
PB14D
PB19C
PB19D
VDDIO5
PB20C
PB20D
VDD15
PB21C
PB21D
PB22C
PB22D
Vss
PB23C
PB23D
VDDIO5
PB24C
PB24D
VDD15
PB26C
PB26D
PB27C
PB27D
Vss
PBCK0T
L3T_D1
L3C_D1
—
2
IO
PBCK0C
—
2
VDDIO5 VDDIO5
—
IO
IO
PB15C
PB15D
VDD15
PB16C
PB16D
PB17A
PB17B
Vss
VREF_5_02
L4T_D1
L4C_D1
—
2
—
D16
—
—
3
VDD15
IO
—
AE15 5 (BC)
AD14 5 (BC)
AF15 5 (BC)
AE16 5 (BC)
—
L5T_D0
L5C_D0
L6T_D0
L6C_D0
—
3
IO
VREF_5_03
3
IO
—
3
IO
—
J23
—
—
3
Vss
IO
—
AD15 5 (BC)
AF16 5 (BC)
AC15 5 (BC)
AE17 5 (BC)
AD16 5 (BC)
AF17 5 (BC)
AC17 5 (BC)
PB17C
PB17D
PB18A
PB18B
PB23C
PB23D
PB24C
PB24D
VDDIO5
PB25C
PB25D
Vss
PB28C
PB28D
PB29C
PB29D
VDDIO5
PB30C
PB30D
Vss
PBCK1T
L7T_D1
L7C_D1
L8T_D1
L8C_D1
—
3
IO
PBCK1C
4
IO
—
4
IO
—
—
4
VDDIO5 VDDIO5
—
IO
IO
PB18C
PB18D
Vss
—
L9T_A2
L9C_A2
—
4
VREF_5_04
N4
—
—
—
—
5
Vss
Vss
IO
—
P23
Vss
Vss
Vss
—
—
AE18 5 (BC)
AD17 5 (BC)
AF18 5 (BC)
AE19 5 (BC)
AF19 5 (BC)
AD18 5 (BC)
AE20 4 (BR)
AC19 4 (BR)
PB19C
PB19D
PB20C
PB20D
PB21A
PB21B
PB22A
PB22B
Vss
PB26C
PB26D
PB27C
PB27D
PB28C
PB28D
PB30C
PB30D
Vss
PB32C
PB32D
PB34C
PB34D
PB35C
PB35D
PB37C
PB37D
Vss
—
L10T_D0
L10C_D0
L11T_D0
L11C_D0
L12T_D1
L12C_D1
L1T_D1
L1C_D1
—
5
IO
VREF_5_05
5
IO
—
5
IO
—
6
IO
—
6
IO
VREF_5_06
1
IO
—
1
IO
—
L13
—
—
1
Vss
IO
—
AF20 4 (BR)
AD19 4 (BR)
AE21 4 (BR)
PB22C
PB22D
PB23A
PB31C
PB31D
PB32C
PB38C
PB38D
PB39C
VREF_4_01
L2T_D1
L2C_D1
L3T_D1
1
IO
—
—
1
IO
110
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout
VDDIO VREF
Additional
Function
BA352
I/O
OR4E02 OR4E04
OR4E06
Pair
Bank Group
AC20 4 (BR)
AF21 4 (BR)
AD20 4 (BR)
AE22 4 (BR)
1
—
2
IO
PB23B
PB32D
VDDIO4
PB33C
PB33D
Vss
PB39D
VDDIO4
PB40C
PB40D
Vss
—
L3C_D1
—
VDDIO4 VDDIO4
—
IO
IO
PB23C
PB23D
Vss
—
L4T_D1
L4C_D1
—
2
VREF_4_02
L14
—
—
2
Vss
IO
—
AF22 4 (BR)
AD21 4 (BR)
AE23 4 (BR)
AC22 4 (BR)
PB24C
PB25A
PB25C
PB25D
Vss
PB34C
PB35A
PB35C
PB35D
Vss
PB42C
PB43A
PB44C
PB44D
Vss
—
—
3
IO
—
—
3
IO
—
L5T_D1
L5C_D1
—
3
IO
VREF_4_03
L15
—
—
3
Vss
IO
—
AF23 4 (BR)
AD22 4 (BR)
PB26C
PB26D
Vss
PB36C
PB36D
Vss
PB45C
PB45D
Vss
—
L6T_D1
L6C_D1
—
3
IO
—
L16
—
—
4
Vss
IO
—
PLL_CK5T/PPLL
AE24 4 (BR)
AD23 4 (BR)
PB27C
PB27D
VDD15
VDD33
Vss
PB37C
PB37D
VDD15
VDD33
Vss
PB47C
PB47D
VDD15
VDD33
Vss
L7T_D0
L7C_D0
—
PLL_CK5C/PPLL
4
IO
D21
AF24
M11
M12
D6
—
—
—
—
—
—
—
—
—
—
—
—
—
5
VDD15
VDD33
Vss
Vss
VDD15
VDD33
—
—
—
—
—
Vss
Vss
Vss
—
—
VDD15
VDD33
VDD15
VDD33
VDDIO4
PR38A
PR38B
Vss
VDD15
VDD33
VDDIO4
PR46C
PR46D
Vss
—
—
AE26
—
—
AD25 4 (BR)
AD26 4 (BR)
AC25 4 (BR)
VDDIO4 VDDIO4
—
—
IO
IO
PR26A
PR26B
Vss
PLL_CK4T/PLL2
L8T_D0
L8C_D0
—
PLL_CK4C/PLL2
5
M13
—
—
5
Vss
IO
—
AC24 4 (BR)
AC26 4 (BR)
PR25A
PR25B
Vss
PR37A
PR37B
Vss
PR44C
PR44D
Vss
VREF_4_05
L9T_A1
L9C_A1
—
5
IO
—
M14
—
—
6
Vss
IO
—
AB25 4 (BR)
AB23 4 (BR)
AB24 4 (BR)
AB26 4 (BR)
AA25 4 (BR)
PR25C
PR25D
PR36A
PR36B
VDDIO4
PR35C
PR35D
PR34C
PR34D
Vss
PR43C
PR43D
VDDIO4
PR41C
PR41D
PR40C
PR40D
Vss
—
L10T_A1
L10C_A1
—
6
IO
—
—
6
VDDIO4 VDDIO4
—
IO
IO
IO
IO
Vss
IO
IO
IO
IO
IO
IO
IO
IO
PR24C
PR24D
PR23A
PR23B
Vss
VREF_4_06
L11T_D0
L11C_D0
L12T_D0
L12C_D0
—
6
—
Y23
AA24 4 (BR)
M15
AA26 4 (BR)
4 (BR)
7
—
7
—
—
—
7
—
PR23C
PR23D
PR22A
PR22B
PR22C
PR22D
PR21C
PR21D
PR33C
PR33D
PR32C
PR32D
PR31C
PR31D
PR30C
PR30D
PR39C
PR39D
PR38C
PR38D
PR37C
PR37D
PR36C
PR36D
—
L13T_D0
L13C_D0
L14T_A1
L14C_A1
L15T_D1
L15C_D1
L16T_A1
L16C_A1
Y25
Y26
Y24
W25
V23
W26
W24
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
7
VREF_4_07
7
—
7
—
8
—
8
VREF_4_08
8
—
—
8
Lattice Semiconductor
111
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout
VDDIO VREF
Additional
Function
BA352
I/O
OR4E02 OR4E04
OR4E06
Pair
Bank Group
V25
V26
M16
U25
V24
U26
U23
T25
U24
T26
N11
R25
R26
F23
T24
P25
R23
P26
R24
N25
N23
N12
F4
3 (CR)
3 (CR)
—
1
1
IO
IO
PR20C
PR20D
Vss
PR29C
PR29D
Vss
PR35C
PR35D
Vss
—
L1T_A0
L1C_A0
—
—
—
1
Vss
IO
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PR19C
PR19D
PR28C
PR28D
VDDIO3
PR26A
PR26B
PR25A
PR25B
Vss
PR33C
PR33D
VDDIO3
PR31C
PR31D
PR30C
PR30D
Vss
VREF_3_01
L2T_D0
L2C_D0
—
1
IO
—
—
2
VDDIO3 VDDIO3
—
IO
IO
PR18C
PR18D
PR17A
PR17B
Vss
—
L3T_D1
L3C_D1
L4T_D1
L4C_D1
—
2
VREF_3_02
2
IO
—
2
IO
—
—
3
Vss
IO
—
3 (CR)
3 (CR)
—
PR17C
PR17D
VDD15
PR16C
PR16D
PR15A
PR15B
PR25C
PR25D
VDD15
PR23C
PR23D
PR22C
PR22D
VDDIO3
PR21C
PR21D
Vss
PR29C
PR29D
VDD15
PR27C
PR27D
PR26C
PR26D
VDDIO3
PR25C
PR25D
Vss
—
L5T_A0
L5C_A0
—
3
IO
VREF_3_03
—
4
VDD15
IO
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PRCK1T
L6T_D1
L6C_D1
L7T_D2
L7C_D2
—
4
IO
PRCK1C
4
IO
—
4
IO
VREF_3_04
—
5
VDDIO3 VDDIO3
—
IO
IO
PR15C
PR15D
Vss
—
L8T_A1
L8C_A1
—
5
—
—
—
5
Vss
VDD15
IO
—
—
VDD15
PR14A
PR14B
PR14C
PR14D
Vss
VDD15
PR20C
PR20D
PR19C
PR19D
Vss
VDD15
PR24C
PR24D
PR23C
PR23D
Vss
—
—
N26
P24
M25
N24
N13
M26
L25
M24
L26
M23
K25
L24
K26
N14
K23
J25
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PRCK0T
L9T_D1
L9C_D1
L10T_D0
L10C_D0
—
5
IO
PRCK0C
5
IO
VREF_3_05
5
IO
—
—
6
Vss
IO
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PR13C
PR13D
PR12A
PR12B
PR17C
PR17D
PR16C
PR16D
VDDIO3
PR15A
PR15B
PR14B
Vss
PR21C
PR21D
PR20C
PR20D
VDDIO3
PR19C
PR19D
PR18D
Vss
—
L11T_D0
L11C_D0
L12T_D1
L12C_D1
—
6
IO
VREF_3_06
6
IO
—
6
IO
—
—
7
VDDIO3 VDDIO3
—
IO
IO
PR12C
PR12D
PR11B
Vss
—
L13T_D0
L13C_D0
—
7
—
7
IO
—
—
7
Vss
IO
—
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PR11C
PR11D
PR10C
PR10D
Vss
PR14C
PR14D
PR13C
PR13D
Vss
PR17C
PR17D
PR15C
PR15D
Vss
VREF_3_07
L14T_D1
L14C_D1
L15T_D1
L15C_D1
—
7
IO
—
K24
J26
8
IO
—
8
IO
—
N15
H25
H26
—
8
Vss
IO
—
VREF_3_08
—
3 (CR)
3 (CR)
PR9C
PR9D
PR12C
PR12D
PR14C
PR14D
L16T_A0
L16C_A0
8
IO
112
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout
VDDIO VREF
Additional
Function
BA352
I/O
OR4E02 OR4E04
OR4E06
Pair
Bank Group
L23
J24
—
—
1
VDD15
IO
VDD15
PR8C
PR8D
PR7A
PR7B
Vss
VDD15
PR11C
PR11D
PR10C
PR10D
Vss
VDD15
PR13C
PR13D
PR12C
PR12D
Vss
—
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
—
L1T_D1
L1C_D1
L2T_D2
L2C_D2
—
G25
H23
G26
P12
H24
F25
G23
F26
G24
E25
E26
P13
F24
D25
E23
D26
P14
E24
C25
D24
C26
L4
1
IO
VREF_2_01
1
IO
—
1
IO
—
—
1
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PR7C
PR7D
PR6A
PR6B
PR9C
PR9D
PR7A
PR7B
VDDIO2
PR6A
PR6B
Vss
PR11C
PR11D
PR10C
PR10D
VDDIO2
PR9C
PR9D
Vss
—
L3T_D1
L3C_D1
L4T_D2
L4C_D2
—
1
IO
—
2
IO
—
2
IO
—
—
2
VDDIO2 VDDIO2
—
IO
IO
PR6C
PR6D
Vss
VREF_2_02
L5T_A0
L5C_A0
—
2
—
—
3
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PR5C
PR5D
PR4C
PR4D
Vss
PR5A
PR5B
PR4C
PR4D
Vss
PR7C
PR7D
PR5C
PR5D
Vss
—
L6T_D1
L6C_D1
L7T_D2
L7C_D2
—
3
IO
VREF_2_03
3
IO
—
3
IO
—
—
4
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
—
PR3C
PR3D
PR3C
PR3D
VDDIO2
VDD33
VDD15
Vss
PR3C
PR3D
VDDIO2
VDD33
VDD15
Vss
PLL_CK3T/PLL1
L8T_D1
L8C_D1
—
PLL_CK3C/PLL1
4
IO
—
—
—
—
—
—
—
5
VDDIO2 VDDIO2
—
VDD33
VDD15
Vss
Vss
VDD33
IO
VDD33
VDD15
Vss
—
—
—
—
—
P15
P16
A25
B24
A24
B23
R11
C23
A23
B22
D22
C22
A22
R12
B21
D20
C21
A21
B20
A20
—
—
—
—
Vss
Vss
Vss
—
—
—
VDD33
PLL_VF
PT27D
PT27C
Vss
VDD33
PLL_VF
PT37D
PT37C
Vss
VDD33
PLL_VF
PT47D
PT47C
Vss
—
—
—
PLL_VF
—
PLL_CK2C/PPLL
2 (TR)
2 (TR)
—
IO
L9C_A0
L9T_A0
—
PLL_CK2T/PPLL
5
IO
—
5
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PT26D
PT26C
PT26B
PT26A
PT25D
PT25C
Vss
PT36D
PT36C
PT35B
PT35A
PT34D
PT34C
Vss
PT45D
PT45C
PT43D
PT43C
PT42D
PT42C
Vss
VREF_2_05
L10C_A1
L10T_A1
L11C_A1
L11T_A1
L12C_A1
L12T_A1
—
5
IO
—
6
IO
—
6
IO
—
6
IO
VREF_2_06
6
IO
—
—
7
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
PT24D
PT24C
PT33D
PT33C
VDDIO2
PT32D
PT32C
PT31D
PT40D
PT40C
VDDIO2
PT39D
PT39C
PT38D
—
L13C_D1
L13T_D1
—
7
IO
VREF_2_07
—
7
VDDIO2 VDDIO2
—
—
—
—
IO
IO
IO
PT24B
PT24A
PT23D
L14C_D0
L14T_D0
L15C_A1
7
8
Lattice Semiconductor
113
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout
VDDIO VREF
Additional
Function
BA352
I/O
OR4E02 OR4E04
OR4E06
Pair
Bank Group
C20
R13
B19
D18
A19
C19
R15
B18
A18
B17
C18
A17
D17
R16
T11
T23
B16
C17
A16
B15
A15
C16
B14
T12
D15
A14
T4
2 (TR)
—
8
—
8
IO
Vss
IO
PT23C
Vss
PT31C
Vss
PT38C
Vss
VREF_2_08
L15T_A1
—
—
2 (TR)
2 (TR)
1 (TC)
1 (TC)
—
PT22D
PT22C
PT21D
PT21C
Vss
PT29D
PT29C
PT28D
PT28C
Vss
PT36D
PT36C
PT35D
PT35C
Vss
—
L16C_D1
L16T_D1
L1C_A1
L1T_A1
—
8
IO
—
1
IO
—
1
IO
—
—
1
Vss
IO
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
PT20D
PT20C
PT20B
PT20A
PT19D
PT19C
Vss
PT27D
PT27C
PT27B
PT27A
PT26D
PT26C
Vss
PT34D
PT34C
PT33D
PT33C
PT32D
PT32C
Vss
VREF_1_01
L2C_A0
L2T_A0
L3C_D0
L3T_D0
L4C_A2
L4T_A2
—
1
IO
—
1
IO
—
1
IO
—
2
IO
—
2
IO
VREF_1_02
—
—
—
2
Vss
Vss
VDD15
IO
—
—
Vss
Vss
Vss
—
—
—
VDD15
PT18D
PT18C
VDD15
PT25D
PT25C
VDDIO1
PT24D
PT24C
PT23D
PT23C
Vss
VDD15
PT30D
PT30C
VDDIO1
PT29D
PT29C
PT28D
PT28C
Vss
—
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
—
L5C_D0
L5T_D0
—
2
IO
—
—
3
VDDIO1 VDDIO1
—
IO
IO
PT18B
PT18A
PT17D
PT17C
Vss
—
L6C_A0
L6T_A0
L7C_D1
L7T_D1
—
3
VREF_1_03
3
IO
—
3
IO
—
—
4
Vss
IO
—
1 (TC)
1 (TC)
—
PT16D
PT16C
VDD15
PT15D
PT15C
PT21D
PT21C
VDD15
PT19D
PT19C
VDDIO1
PT18D
PT18C
Vss
PT26D
PT26C
VDD15
PT24D
PT24C
VDDIO1
PT23D
PT23C
Vss
—
L8C_D2
L8T_D2
—
4
IO
—
—
4
VDD15
IO
—
—
C15
B13
D13
A13
C14
T13
B12
C13
A12
B11
T14
C12
A11
D12
B10
C11
A10
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
L9C_D1
L9T_D1
—
4
IO
VREF_1_04
—
—
5
VDDIO1 VDDIO1
IO
IO
PT14D
PT14C
Vss
PTCK1C
PTCK1T
—
L10C_D1
L10T_D1
—
5
—
5
Vss
IO
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
PT13D
PT13C
PT13B
PT13A
Vss
PT17D
PT17C
PT16D
PT16C
Vss
PT22D
PT22C
PT21D
PT21C
Vss
PTCK0C
PTCK0T
VREF_1_05
—
L11C_D0
L11T_D0
L12C_D0
L12T_D0
—
5
IO
5
IO
5
IO
—
6
Vss
IO
—
1 (TC)
1 (TC)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
PT12B
PT12A
PT11D
PT11C
PT14D
PT14C
PT13D
PT13C
VDDIO0
PT12D
PT19D
PT19C
PT18D
PT18C
VDDIO0
PT16D
—
L13C_D1
L13T_D1
L1C_D2
L1C_D2
—
6
IO
VREF_1_06
MPI_RTRY_N
MPI_ACK_N
—
1
IO
1
IO
—
1
VDDIO0 VDDIO0
IO PT10D
M0
L2C_A2
114
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 67. 352-Pin PBGA Pinout
VDDIO VREF
Additional
Function
BA352
I/O
OR4E02 OR4E04
OR4E06
Pair
Bank Group
D10
AC18
B9
0 (TL)
—
1
—
2
IO
Vss
IO
IO
IO
IO
IO
IO
IO
IO
IO
Vss
IO
IO
IO
IO
PT10C
Vss
PT12C
Vss
PT16C
Vss
M1
—
L2T_A2
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PT10B
PT10A
PT9D
PT9C
PT9B
PT9A
PT8B
PT7D
PT7C
Vss
PT12B
PT12A
PT11D
PT11C
PT11B
PT11A
PT9D
PT8D
PT8C
Vss
PT15D
PT15C
PT14D
PT14C
PT13D
PT13C
PT11D
PT10D
PT10C
Vss
MPI_CLK
A21/MPI_BURST_N
L3C_D0
L3C_D0
L4C_D0
L4T_D0
L5C_D1
L5T_D1
—
C10
A9
2
2
M2
B8
2
M3
A8
2
VREF_0_02
C9
2
MPI_TEA_N
B7
3
VREF_0_03
D8
3
D0
L6C_D2
L6T_D2
—
A7
3
TMS
AC23
C8
—
4
—
A20/MPI_BDIP_N
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PT7B
PT7A
PT6D
PT6C
PT7D
PT7C
PT6D
PT6C
VDDIO0
PT5D
PT5C
Vss
PT9D
PT9C
PT8D
PT8C
VDDIO0
PT6D
PT6C
Vss
L7C_D2
L7T_D2
L8C_D2
L8T_D2
—
B6
4
A19/MPI_TSZ1
D7
4
A18/MPI_TSZ0
A6
4
D3
C7
—
5
VDDIO0 VDDIO0
—
B5
IO
IO
PT5D
PT5C
Vss
D1
L9C_A0
L9T_A0
—
A5
5
D2
AC4
C6
—
5
Vss
IO
—
TDI
0 (TL)
0 (TL)
—
PT4D
PT4C
Vss
PT4D
PT4C
Vss
PT4D
PT4C
Vss
L10C_D2
L10T_D2
—
B4
5
IO
TCK
AC8
D5
—
6
Vss
IO
—
PLL_CK1C/PPLL
PLL_CK1T/PPLL
0 (TL)
0 (TL)
—
PT2D
PT2C
PCFG_
PT2D
PT2C
PCFG_
PT2D
PT2C
PCFG_
L11C_D2
L11T_D2
—
A4
6
IO
C5
—
O
CFG_IRQ_N/
MPI_IRQ_N
MPI_IRQ MPI_IRQ MPI_IRQ
B3
C4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IO
IO
PCCLK
PDONE
VDD33
Vss
PCCLK
PDONE
VDD33
Vss
PCCLK
PDONE
VDD33
Vss
CCLK
DONE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A3
VDD33
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
AD24
AF26
B2
—
Vss
Vss
Vss
—
Vss
Vss
Vss
—
V4
Vss
Vss
Vss
—
W23
L11
L12
N16
P11
R14
T15
T16
Vss
Vss
Vss
—
Vss
Vss
Vss
—
Vss
Vss
Vss
—
Vss
Vss
Vss
—
Vss
Vss
Vss
—
Vss
Vss
Vss
—
Vss
Vss
Vss
—
Vss
Vss
Vss
—
Lattice Semiconductor
115
Data Sheet
May, 2006
ORCA Series 4 FPGAs
416-Pin BGAM Pinout
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
A2
D4
D3
A1
C1
E4
—
—
—
—
—
—
—
—
—
—
—
—
Vss
Vss
Vss
—
—
—
—
—
—
—
—
VDD33
VDD33
VDD33
O
PRD_DATA
VDD15
PRD_DATA
VDD15
RD_DATA/TDO
—
VDD15
I
I
PRESET_N
PRESET_N
RESET_N
RD_CFG_N
PRD_CFG_ PRD_CFG_N
N
F4
C2
D2
E3
A25
D1
E2
F3
E1
F2
B1
G4
H4
G3
F1
G2
H2
H3
G1
H1
J4
—
—
—
7
I
VDDIO0
IO
PPRGRM_N PPRGRM_N
PRGRM_N
—
0 (TL)
0 (TL)
0 (TL)
—
VDDIO0
PL2D
PL2C
Vss
VDDIO0
PL2D
PL2C
Vss
—
—
PLL_CK0C/HPPLL
L14C_D0
L14T_D0
—
7
IO
PLL_CK0T/HPPLL
—
7
Vss
IO
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PL2A
PL3D
PL3C
PL4D
PL4C
Vss
PL3C
PL4D
PL4C
PL5D
PL5C
Vss
VREF_0_07
—
7
IO
D5
L15C_D0
L15T_D0
L16C_D0
L16T_D0
—
7
IO
D6
8
IO
HDC
LDC_N
—
8
IO
—
9
Vss
IO
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PL5D
PL5C
VDDIO0
PL5B
PL5A
PL6D
PL6C
PL6B
PL6A
PL7D
PL7C
VDD15
PL7B
PL7A
PL8D
PL8C
VDDIO7
PL9D
PL9C
Vss
PL6D
PL6C
VDDIO0
PL7D
PL7C
PL8D
PL8C
PL9D
PL9C
PL10D
PL10C
VDD15
PL11D
PL11C
PL12D
PL12C
VDDIO7
PL13D
PL13C
Vss
TESTCFG
D7
L17C_A0
L17T_A0
—
9
IO
—
9
VDDIO0
IO
—
VREF_0_09
A17/PPC_A31
CS0_N
CS1
L18C_D0
L18T_D0
L19C_A0
L19T_A0
L20C_A0
L20T_A0
L21C_A0
L21T_A0
—
9
IO
9
IO
9
IO
10
10
10
10
—
10
10
1
IO
—
IO
—
IO
INIT_N
DOUT
K4
A26
J3
IO
VDD15
IO
—
0 (TL)
0 (TL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
VREF_0_10
A16/PPC_A30
A15/PPC_A29
A14/PPC_A28
—
L22C_A0
L22T_A0
L1C_D0
L1T_D0
—
J2
IO
J1
IO
K2
K1
K3
L3
1
IO
—
1
VDDIO7
IO
VREF_7_01
D4
L2C_A0
L2T_A0
—
1
IO
U16
L4
—
2
Vss
IO
—
7 (CL)
PL10D
PL14D
RDY/BUSY_N/
RCLK
L3C_A0
M4
L2
L1
7 (CL)
7 (CL)
7 (CL)
2
—
2
IO
VDDIO7
IO
PL10C
VDDIO7
PL10B
PL14C
VDDIO7
PL15D
VREF_7_02
—
L3T_A0
—
A13/PPC_A27
L4C_A0
116
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
M1
M3
M2
U17
N1
7 (CL)
7 (CL)
7 (CL)
—
2
3
IO
IO
PL10A
PL11D
PL11C
Vss
PL15C
PL16D
PL16C
Vss
A12/PPC_A26
L4T_A0
L5C_A0
L5T_A0
—
—
3
IO
—
—
—
3
Vss
IO
7 (CL)
7 (CL)
—
PL11B
PL11A
VDD15
PL13D
PL17D
PL17C
VDD15
PL19D
A11/PPC_A25
VREF_7_03
—
L6C_A0
L6T_A0
—
N2
3
IO
U14
N3
—
4
VDD15
IO
7 (CL)
RD_N/
L7C_A0
MPI_STRB_N
N4
AE1
P4
7 (CL)
—
4
—
4
IO
Vss
IO
PL13C
Vss
PL19C
Vss
VREF_7_04
—
L7T_A0
—
7 (CL)
7 (CL)
7 (CL)
—
PL14D
PL14C
VDDIO7
Vss
PL20D
PL20C
VDDIO7
Vss
PLCK0C
PLCK0T
—
L8C_A0
L8T_A0
—
P3
4
IO
P2
—
—
5
VDDIO7
Vss
IO
AE26
P1
—
—
7 (CL)
7 (CL)
—
PL15D
PL15C
Vss
PL21D
PL21C
Vss
A10/PPC_A24
A9/PPC_A23
—
L9C_A0
L9T_A0
—
R1
5
IO
AF2
R2
—
5
Vss
IO
7 (CL)
7 (CL)
—
PL16D
PL16C
VDD15
PL17D
PL17C
Vss
PL22D
PL22C
VDD15
PL24D
PL24C
Vss
A8/PPC_A22
VREF_7_05
—
L10C_A0
L10T_A0
—
R3
5
IO
AF1
T1
—
6
VDD15
IO
7 (CL)
7 (CL)
—
PLCK1C
PLCK1T
—
L11C_A0
L11T_A0
—
T2
6
IO
AF25
T4
—
6
Vss
IO
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
PL17B
PL17A
PL18D
PL18C
VDDIO7
PL18B
PL19D
PL19C
VDD15
PL20D
PL20C
PL20B
PL20A
PL21D
PL21C
PL21B
PL21A
PL22D
PL22C
Vss
PL25D
PL25C
PL26D
PL26C
VDDIO7
PL26B
PL27D
PL27C
VDD15
PL28D
PL28C
PL29D
PL29C
PL30D
PL30C
PL31D
PL31C
PL32D
PL32C
Vss
VREF_7_06
A7/PPC_A21
A6/PPC_A20
A5/PPC_A19
—
L12C_A0
L12T_A0
L13C_A0
L13T_A0
—
R4
6
IO
U1
6
IO
U2
6
IO
T3
—
7
VDDIO7
IO
V1
—
—
V2
7
IO
WR_N/MPI_RW
VREF_7_07
—
L14C_D0
L14T_D0
—
U3
7
IO
AF26
W1
Y1
—
8
VDD15
IO
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
6 (BL)
6 (BL)
—
A4/PPC_A18
VREF_7_08
A3/PPC_A17
A2/PPC_A16
A1/PPC_A15
A0/PPC_A14
DP0
L15C_A0
L15T_A0
L16C_A0
L16T_A0
L17C_D0
L17T_D0
L18C_D0
L18T_D0
L1C_A0
L1T_A0
—
8
IO
V4
8
IO
U4
8
IO
V3
8
IO
W2
Y2
8
IO
8
IO
W3
AA1
AA2
T16
8
IO
DP1
1
IO
D8
1
IO
VREF_6_01
—
—
Vss
Lattice Semiconductor
117
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
Y3
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
1
1
IO
IO
PL22B
PL22A
PL23D
PL23C
VDDIO6
PL24D
PL24C
Vss
PL33D
PL33C
PL34D
PL34C
VDDIO6
PL35B
PL35A
Vss
D9
L2C_D0
L2T_D0
L3C_D0
L3T_D0
—
W4
D10
Y4
2
IO
—
AA3
AB1
AB2
AC1
T17
AC2
AB3
AD1
U10
AA4
AB4
U11
U12
AC3
AD2
R14
AE2
AD3
U15
AC4
T13
AE3
AC5
AD4
AE4
AF3
AC6
AD5
AF4
AE5
AD6
AF5
AC7
AC8
AD7
AE6
AE7
AD8
AF6
AF7
T14
2
IO
VREF_6_02
—
3
VDDIO6
IO
—
D11
L4C_D0
L4T_D0
—
3
IO
D12
—
3
Vss
IO
—
6 (BL)
6 (BL)
6 (BL)
—
PL25D
PL25C
PL26C
Vss
PL36B
PL36A
PL37A
Vss
VREF_6_03
L5C_D0
L5T_D0
—
3
IO
D13
4
IO
VREF_6_04
—
4
Vss
IO
—
—
6 (BL)
6 (BL)
—
PL27D
PL27C
Vss
PL39D
PL39C
Vss
PLL_CK7C/HPPLL
L6C_A0
L6T_A0
—
4
IO
PLL_CK7T/HPPLL
—
—
—
—
—
—
—
—
—
—
5
Vss
Vss
I
—
—
Vss
Vss
—
—
—
PTEMP
VDDIO6
VDD15
LVDS_R
VDD33
Vss
PTEMP
VDDIO6
VDD15
LVDS_R
VDD33
Vss
PTEMP
—
6 (BL)
—
VDDIO6
VDD15
IO
—
—
—
—
—
LVDS_R
—
—
VDD33
Vss
VDD33
VDD15
IO
—
—
—
—
—
—
VDD33
VDD15
PB2A
PB2C
PB2D
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
PB5B
VDDIO6
PB5C
PB5D
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
VDD15
VDD33
VDD15
PB2A
PB2C
PB2D
PB4A
PB4B
PB4C
PB4D
PB5C
PB5D
PB6B
VDDIO6
PB6C
PB6D
PB7C
PB7D
PB8C
PB8D
PB9C
PB9D
VDD15
—
—
—
—
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
DP2
—
5
IO
PLL_CK6T/PPLL
L7T_D0
L7C_D0
L8T_D0
L8C_D0
L9T_D0
L9C_D0
L10T_D0
L10C_D0
—
5
IO
PLL_CK6C/PPLL
5
IO
VREF_6_05
5
IO
DP3
6
IO
—
—
6
IO
6
IO
VREF_6_06
D14
6
IO
6
IO
—
—
7
VDDIO6
IO
—
—
D15
L11T_A0
L11C_A0
L12T_D0
L12C_D0
L13T_D0
L13C_D0
L14T_A0
L14C_A0
—
7
IO
D16
7
IO
D17
7
IO
D18
7
IO
VREF_6_07
D19
7
IO
8
IO
D20
8
IO
D21
—
VDD15
—
118
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
AE8
AD9
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
5 (BC)
5 (BC)
—
8
8
IO
IO
PB7C
PB7D
PB10C
PB10D
PB11C
PB11D
PB12C
PB12D
PB13C
PB13D
VDDIO6
PB14C
PB14D
PB15C
PB15D
PB16C
PB16D
PB17C
PB17D
VDD15
PB18C
PB18D
Vss
VREF_6_08
L15T_D0
L15C_D0
L16T_A0
L16C_A0
L17T_D0
L17C_D0
L18T_A0
L18C_A0
—
D22
AC9
9
IO
PB8C
D23
AC10
AF8
9
IO
PB8D
D24
9
IO
PB9C
VREF_6_09
AE9
9
IO
PB9D
D25
AD10
AE10
AF9
10
10
—
10
10
11
11
11
11
1
IO
PB10C
PB10D
VDDIO6
PB11C
PB11D
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
VDD15
PB13C
PB13D
Vss
D26
IO
D27
VDDIO6
IO
—
AE11
AD11
AC12
AC11
AF10
AF11
AD12
AE12
P16
VREF_6_10
L19T_A0
L19C_A0
L20T_A0
L20C_A0
L21T_A0
L21C_A0
L1T_A0
L1C_A0
—
IO
D28
IO
D29
IO
D30
IO
VREF_6_11
IO
D31
IO
—
1
IO
—
—
1
VDD15
IO
—
AF12
AF13
R16
5 (BC)
5 (BC)
—
VREF_5_01
L2T_A0
L2C_A0
—
1
IO
—
—
2
Vss
IO
—
AD13
AE13
AF14
AC14
AC13
P17
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
—
PB14C
PB14D
VDDIO5
PB15C
PB15D
VDD15
PB16C
PB16D
PB17A
PB17B
Vss
PB19C
PB19D
VDDIO5
PB20C
PB20D
VDD15
PB21C
PB21D
PB22C
PB22D
Vss
PBCK0T
L3T_A0
L3C_A0
—
2
IO
PBCK0C
—
2
VDDIO5
IO
—
VREF_5_02
L4T_A0
L4C_A0
—
2
IO
—
—
3
VDD15
IO
—
AE14
AD14
AF15
AE15
R17
5 (BC)
5 (BC)
5 (BC)
5 (BC)
—
—
L5T_A0
L5C_A0
L6T_A0
L6C_A0
—
3
IO
VREF_5_03
3
IO
—
3
IO
—
—
3
Vss
IO
—
AD15
AE16
AC15
AC16
AF17
AD16
AE17
T10
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
5 (BC)
—
PB17C
PB17D
PB18A
PB18B
VDDIO5
PB18C
PB18D
Vss
PB23C
PB23D
PB24C
PB24D
VDDIO5
PB25C
PB25D
Vss
PBCK1T
L7T_D0
L7C_D0
L8T_A0
L8C_A0
—
3
IO
PBCK1C
4
IO
—
4
IO
—
—
4
VDDIO5
IO
—
—
L9T_D0
L9C_D0
—
4
IO
VREF_5_04
—
—
5
Vss
Vss
IO
—
T11
—
Vss
Vss
—
—
AF18
AE18
AD17
5 (BC)
5 (BC)
5 (BC)
PB19C
PB19D
VDDIO5
PB26C
PB26D
VDDIO5
—
VREF_5_05
—
L10T_A0
L10C_A0
—
5
IO
—
VDDIO5
Lattice Semiconductor
119
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
AF19
AF20
AC18
AC17
R13
5 (BC)
5 (BC)
5 (BC)
5 (BC)
—
5
5
IO
IO
PB20C
PB20D
PB21A
PB21B
VDD15
PB22A
PB22B
Vss
PB27C
PB27D
PB28C
PB28D
VDD15
PB30C
PB30D
Vss
—
L11T_A0
L11C_A0
L12T_A0
L12C_A0
—
—
6
IO
—
6
IO
VREF_5_06
—
1
VDD15
IO
—
AD18
AE19
P13
4 (BR)
4 (BR)
—
—
L1T_D0
L1C_D0
—
1
IO
—
—
1
Vss
IO
—
AE20
AD19
AF21
AE21
AD20
AC19
AC20
AF22
P14
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
—
PB22C
PB22D
PB23A
PB23B
VDDIO4
PB23C
PB23D
PB24A
Vss
PB31C
PB31D
PB32C
PB32D
VDDIO4
PB33C
PB33D
PB34A
Vss
VREF_4_01
L2T_D0
L2C_D0
L3T_A0
L3C_A0
—
1
IO
—
1
IO
—
1
IO
—
—
2
VDDIO4
IO
—
—
L4T_A0
L4C_A0
—
2
IO
VREF_4_02
2
IO
—
—
2
Vss
IO
—
—
AE22
AD21
AF23
AE23
AF24
R10
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
—
PB24C
PB25A
VDDIO4
PB25C
PB25D
Vss
PB34C
PB35A
VDDIO4
PB35C
PB35D
Vss
—
—
3
IO
—
—
—
3
VDDIO4
IO
—
—
—
L5T_D0
L5C_D0
—
3
IO
VREF_4_03
—
3
Vss
IO
—
AC21
AD22
AD23
AE24
R11
4 (BR)
4 (BR)
4 (BR)
4 (BR)
—
PB26C
PB26D
PB27A
PB27B
Vss
PB36C
PB36D
PB37A
PB37B
Vss
—
L6T_D0
L6C_D0
L7T_D0
L7C_D0
—
3
IO
—
4
IO
—
4
IO
VREF_4_04
—
4
Vss
IO
—
AC22
AC23
P10
4 (BR)
4 (BR)
—
PB27C
PB27D
VDD15
VDD33
Vss
PB37C
PB37D
VDD15
VDD33
Vss
PLL_CK5T/PPLL
L8T_A0
L8C_A0
—
4
IO
PLL_CK5C/PPLL
—
—
—
—
—
—
—
5
VDD15
VDD33
Vss
Vss
VDD15
VDD33
VDDIO4
IO
—
AD24
R12
—
—
—
—
—
—
R15
—
Vss
Vss
—
—
P11
—
VDD15
VDD33
VDDIO4
PR26A
PR26B
PR25A
PR25B
PR25C
PR25D
PR24A
VDD15
VDD33
VDDIO4
PR38A
PR38B
PR37A
PR37B
PR36A
PR36B
PR36C
—
—
AE25
AC24
AD25
AD26
AB23
AA23
AC25
AB24
AB25
—
—
—
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
—
—
PLL_CK4T/PLL2
L9T_A0
L9C_A0
L10T_A0
L10C_A0
L11T_D0
L11C_D0
—
5
IO
PLL_CK4C/PLL2
5
IO
VREF_4_05
5
IO
—
—
—
—
6
IO
6
IO
6
IO
120
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
AA24
AC26
AB26
Y24
W23
AA25
AA26
Y23
W24
P12
Y25
Y26
W25
V24
W26
V23
U23
M12
V25
U24
V26
U26
U25
T24
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
4 (BR)
—
—
6
VDDIO4
IO
VDDIO4
PR24C
PR24D
PR23A
PR23B
PR23C
PR23D
PR22A
PR22B
VDD15
PR22C
PR22D
PR21C
PR21D
VDDIO3
PR20C
PR20D
Vss
VDDIO4
PR35C
PR35D
PR34C
PR34D
PR33C
PR33D
PR32C
PR32D
VDD15
PR31C
PR31D
PR30C
PR30D
VDDIO3
PR29C
PR29D
Vss
—
—
VREF_4_06
L12T_A0
L12C_A0
L13T_D0
L13C_D0
L14T_A0
L14C_A0
L15T_D0
L15C_D0
—
6
IO
—
7
IO
—
7
IO
—
7
IO
—
7
IO
VREF_4_07
7
IO
—
7
IO
—
—
8
VDD15
IO
—
4 (BR)
4 (BR)
4 (BR)
4 (BR)
3 (CR)
3 (CR)
3 (CR)
—
—
L16T_A0
L16C_A0
L17T_D0
L17C_D0
—
8
IO
VREF_4_08
8
IO
—
8
IO
—
—
1
VDDIO3
IO
—
—
L1T_A0
L1C_A0
—
1
IO
—
—
1
Vss
IO
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PR19C
PR19D
PR18A
VDDIO3
PR18C
PR18D
PR17A
PR17B
Vss
PR28C
PR28D
PR27A
VDDIO3
PR26A
PR26B
PR25A
PR25B
Vss
VREF_3_01
L2T_D0
L2C_D0
—
1
IO
—
2
IO
—
—
2
VDDIO3
IO
—
—
—
L3T_D0
L3C_D0
L4T_A0
L4C_A0
—
2
IO
VREF_3_02
R23
T23
2
IO
—
2
IO
—
M15
T25
—
3
Vss
IO
—
3 (CR)
3 (CR)
—
PR17C
PR17D
VDD15
PR16C
PR16D
PR15A
PR15B
VDDIO3
PR15C
PR15D
Vss
PR25C
PR25D
VDD15
PR23C
PR23D
PR22C
PR22D
VDDIO3
PR21C
PR21D
Vss
—
L5T_A0
L5C_A0
—
T26
3
IO
VREF_3_03
N15
R24
R25
R26
P25
P24
P26
N26
M16
N23
P23
N16
N25
N24
M26
—
4
VDD15
IO
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PRCK1T
L6T_A0
L6C_A0
L7T_D0
L7C_D0
—
4
IO
PRCK1C
4
IO
—
4
IO
VREF_3_04
—
5
VDDIO3
IO
—
—
L8T_A0
L8C_A0
—
5
IO
—
—
5
Vss
IO
—
PRCK0T
PRCK0C
—
3 (CR)
3 (CR)
—
PR14A
PR14B
VDD15
PR14C
PR14D
PR13A
PR20C
PR20D
VDD15
PR19C
PR19D
PR18C
L9T_A0
L9C_A0
—
5
IO
—
5
VDD15
IO
3 (CR)
3 (CR)
3 (CR)
VREF_3_05
—
L10T_A0
L10C_A0
L11T_A0
5
IO
5
IO
—
Lattice Semiconductor
121
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
M25
M17
M24
M23
L26
L25
K26
L23
L24
K25
J26
3 (CR)
—
5
—
6
IO
Vss
IO
PR13B
Vss
PR18D
Vss
—
L11C_A0
—
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PR13C
PR13D
PR12A
PR12B
VDDIO3
PR12C
PR12D
PR11A
PR11B
Vss
PR17C
PR17D
PR16C
PR16D
VDDIO3
PR15A
PR15B
PR14A
PR14B
Vss
—
L12T_A0
L12C_A0
L13T_A0
L13C_A0
—
6
IO
VREF_3_06
6
IO
—
6
IO
—
—
7
VDDIO3
IO
—
—
L14T_A0
L14C_A0
L15T_D0
L15C_D0
—
7
IO
—
7
IO
—
7
IO
—
N13
J25
—
7
Vss
IO
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PR11C
PR11D
PR10C
PR10D
Vss
PR14C
PR14D
PR13C
PR13D
Vss
VREF_3_07
L16T_D0
L16C_D0
L17T_A0
L17C_A0
—
K24
H26
G26
N14
K23
J23
7
IO
—
8
IO
—
8
IO
—
—
8
Vss
IO
—
3 (CR)
3 (CR)
—
PR9C
PR9D
VDD15
PR8C
PR8D
PR7A
PR7B
Vss
PR12C
PR12D
VDD15
PR11C
PR11D
PR10C
PR10D
Vss
VREF_3_08
L18T_A0
L18C_A0
—
8
IO
—
M14
J24
—
1
VDD15
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
—
L1T_D0
L1C_D0
L2T_D0
L2C_D0
—
H25
G25
H24
L12
F26
E26
H23
G24
G23
F25
E25
F24
L15
D26
D25
C25
D24
F23
E24
L16
C26
B25
E23
1
IO
VREF_2_01
1
IO
—
1
IO
—
—
1
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PR7C
PR7D
PR6A
PR6B
VDDIO2
PR6C
PR6D
PR5A
Vss
PR9C
PR9D
PR7A
PR7B
VDDIO2
PR6A
PR6B
PR6C
Vss
—
L3T_A0
L3C_A0
L4T_D0
L4C_D0
—
1
IO
—
2
IO
—
2
IO
—
—
2
VDDIO2
IO
—
VREF_2_02
L5T_A0
L5C_A0
—
2
IO
—
2
IO
—
—
3
Vss
IO
—
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PR5C
PR5D
PR4A
PR4B
PR4C
PR4D
Vss
PR5A
PR5B
PR4A
PR4B
PR4C
PR4D
Vss
—
L6T_A0
L6C_A0
L7T_D0
L7C_D0
L8T_D0
L8C_D0
—
3
IO
VREF_2_03
3
IO
—
3
IO
—
3
IO
—
3
IO
—
—
4
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
PR3C
PR3D
VDDIO2
PR3C
PR3D
VDDIO2
PLL_CK3T/PLL1
PLL_CK3C/PLL1
—
L9T_D0
L9C_D0
—
4
IO
—
VDDIO2
122
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
C24
N10
L17
M10
D23
N11
B24
D22
C23
M11
A24
B23
C22
D21
C21
A23
B22
A22
B21
D20
D19
C20
B20
C19
A21
A20
N12
B19
C18
K12
D18
D17
A19
B18
C17
A18
B17
K15
K16
A17
B16
D15
D16
C16
—
—
—
—
—
—
—
—
5
VDD33
VDD15
Vss
Vss
VDD33
VDD15
IO
VDD33
VDD15
Vss
VDD33
VDD15
Vss
—
—
—
—
—
—
—
—
—
Vss
Vss
—
—
—
VDD33
VDD15
PLL_VF
PT27D
PT27C
Vss
VDD33
VDD15
PLL_VF
PT37D
PT37C
Vss
—
—
—
—
—
—
PLL_VF
—
2 (TR)
2 (TR)
—
IO
PLL_CK2C/PPLL
L10C_D0
L10T_D0
—
5
IO
PLL_CK2T/PPLL
—
5
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PT26D
PT26C
VDDIO2
PT26B
PT26A
PT25D
PT25C
PT24D
PT24C
VDDIO2
PT24B
PT24A
PT23D
PT23C
PT22D
PT22C
VDD15
PT21D
PT21C
Vss
PT36D
PT36C
VDDIO2
PT35B
PT35A
PT34D
PT34C
PT33D
PT33C
VDDIO2
PT32D
PT32C
PT31D
PT31C
PT29D
PT29C
VDD15
PT28D
PT28C
Vss
VREF_2_05
L11C_D0
L11T_D0
—
5
IO
—
—
6
VDDIO2
IO
—
—
L12C_A0
L12T_A0
L13C_D0
L13T_D0
L14C_D0
L14T_D0
—
6
IO
—
6
IO
VREF_2_06
6
IO
—
7
IO
—
7
IO
VREF_2_07
—
7
VDDIO2
IO
—
—
L15C_D0
L15T_D0
L16C_D0
L16T_D0
L17C_A0
L17T_A0
—
7
IO
—
8
IO
—
8
IO
VREF_2_08
8
IO
—
8
IO
—
—
1
VDD15
IO
—
1 (TC)
1 (TC)
—
—
L1C_D0
L1T_D0
—
1
IO
—
—
1
Vss
IO
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
PT20D
PT20C
VDDIO1
PT20B
PT20A
PT19D
PT19C
Vss
PT27D
PT27C
VDDIO1
PT27B
PT27A
PT26D
PT26C
Vss
VREF_1_01
L2C_A0
L2T_A0
—
1
IO
—
—
1
VDDIO1
IO
—
—
L3C_D0
L3T_D0
L4C_D0
L4T_D0
—
1
IO
—
2
IO
—
2
IO
VREF_1_02
—
—
2
Vss
Vss
IO
—
—
Vss
Vss
—
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
PT18D
PT18C
VDDIO1
PT18B
PT18A
PT25D
PT25C
VDDIO1
PT24D
PT24C
—
L5C_D0
L5T_D0
—
2
IO
—
—
3
VDDIO1
IO
—
—
L6C_A0
L6T_A0
3
IO
VREF_1_03
Lattice Semiconductor
123
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
A16
A15
K17
C15
C14
L13
B14
A14
D14
D13
C13
L10
B13
A13
L14
A12
B12
C12
D12
L11
B11
A11
D11
C11
A10
C10
B10
A9
1 (TC)
1 (TC)
—
3
3
IO
IO
PT17D
PT17C
Vss
PT23D
PT23C
Vss
—
L7C_A0
L7T_A0
—
—
—
4
Vss
IO
—
1 (TC)
1 (TC)
—
PT16D
PT16C
VDD15
PT15D
PT15C
VDDIO1
PT14D
PT14C
Vss
PT21D
PT21C
VDD15
PT19D
PT19C
VDDIO1
PT18D
PT18C
Vss
—
L8C_A0
L8T_A0
—
4
IO
—
—
4
VDD15
IO
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
—
L9C_A0
L9T_A0
—
4
IO
VREF_1_04
—
5
VDDIO1
IO
—
PTCK1C
PTCK1T
—
L10C_A0
L10T_A0
—
5
IO
—
5
Vss
IO
1 (TC)
1 (TC)
—
PT13D
PT13C
VDD15
PT13B
PT13A
PT12D
PT12C
Vss
PT17D
PT17C
VDD15
PT16D
PT16C
PT15D
PT15C
Vss
PTCK0C
PTCK0T
—
L11C_A0
L11T_A0
—
5
IO
—
5
VDD15
IO
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
VREF_1_05
—
L12C_A0
L12T_A0
L13C_A0
L13T_A0
—
5
IO
6
IO
—
6
IO
—
—
6
Vss
IO
—
1 (TC)
1 (TC)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
PT12B
PT12A
PT11D
PT11C
VDDIO0
PT11A
PT10D
PT10C
PT10B
PT10A
PT14D
PT14C
PT13D
PT13C
VDDIO0
PT13A
PT12D
PT12C
PT12B
PT12A
—
L14C_A0
L14T_A0
L1C_A0
L1T_A0
—
6
IO
VREF_1_06
MPI_RTRY_N
MPI_ACK_N
—
1
IO
1
IO
—
1
VDDIO0
IO
VREF_0_01
M0
—
1
IO
L2C_D0
L2T_D0
L3C_A0
L3T_A0
1
IO
M1
B9
2
IO
MPI_CLK
C9
2
IO
A21/
MPI_BURST_N
D10
D9
A8
B8
K13
A7
A6
C8
B7
C7
B6
D7
D8
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
2
2
2
2
—
3
3
3
3
4
4
4
4
IO
IO
PT9D
PT9C
PT9B
PT9A
VDD15
PT8B
PT8A
PT7D
PT7C
PT7B
PT7A
PT6D
PT6C
PT11D
PT11C
PT11B
PT11A
VDD15
PT9D
PT9C
PT8D
PT8C
PT7D
PT7C
PT6D
PT6C
M2
M3
L4C_A0
L4T_A0
L5C_A0
L5T_A0
—
IO
VREF_0_02
MPI_TEA_N
—
IO
VDD15
IO
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
VREF_0_03
—
L6C_A0
L6T_A0
L7C_D0
L7T_D0
L8C_D0
L8T_D0
L9C_A0
L9T_A0
IO
IO
D0
IO
TMS
IO
A20/MPI_BDIP_N
A19/MPI_TSZ1
A18/MPI_TSZ0
D3
IO
IO
IO
124
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 68. 416-Pin BGAM Pinout
VDDIO
Bank
VREF
Group
Additional
Function
BM416
I/O
OR4E02
OR4E04
Pair
A5
C6
B5
0 (TL)
0 (TL)
0 (TL)
—
—
5
VDDIO0
IO
VDDIO0
PT5D
PT5C
Vss
VDDIO0
PT5D
PT5C
Vss
—
—
D1
L10C_D0
L10T_D0
—
5
IO
D2
B26
A4
—
5
Vss
IO
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PT4D
PT4C
PT3D
PT3C
Vss
PT4D
PT4C
PT3D
PT3C
Vss
TDI
TCK
L11C_D1
L11T_D1
L12C_A0
L12T_A0
—
C5
B3
5
IO
6
IO
—
A3
6
IO
VREF_0_06
—
K10
D5
D6
B4
—
6
Vss
IO
0 (TL)
0 (TL)
—
PT2D
PT2C
PT2D
PT2C
PLL_CK1C/PPLL
PLL_CK1T/PPLL
L13C_A0
L13T_A0
—
6
IO
CFG_IRQ_N/
MPI_IRQ_N
—
O
PCFG_MPI_ PCFG_MPI_IR
IRQ
PCCLK
VDD15
PDONE
VDD33
Vss
Q
B2
K14
C4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IO
PCCLK
VDD15
PDONE
VDD33
Vss
CCLK
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD15
IO
—
DONE
—
C3
—
VDD33
Vss
K11
B15
AF16
T12
T15
U13
P15
N17
M13
—
—
1 (TC)
5 (BC)
—
VDDIO1
VDDIO5
Vss
VDDIO1
VDDIO5
Vss
VDDIO1
VDDIO5
Vss
—
—
—
—
Vss
Vss
Vss
—
—
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
—
—
—
—
—
—
—
Lattice Semiconductor
125
Data Sheet
May, 2006
ORCA Series 4 FPGAs
680-Pin PBGAM Pinout
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Bank Group
Additional
Function
BM680
I/O
OR4E02
OR4E04
OR4E06
Pair
A1
F5
E4
E3
D2
—
—
—
—
—
—
—
—
—
—
Vss
Vss
Vss
Vss
—
—
—
—
—
—
VDD33
VDD33
VDD33
VDD33
—
O
I
PRD_DATA PRD_DATA PRD_DATA
PRESET_N PRESET_N PRESET_N
PRD_CFG_ PRD_CFG_ PRD_CFG_
RD_DATA/TDO
RESET_N
RD_CFG_N
I
N
N
N
G5
D3
D1
F4
A2
F3
G4
E2
H5
E5
E1
F2
J5
—
—
—
7
I
VDDIO0
IO
PPRGRM_N PPRGRM_N PPRGRM_N
PRGRM_N
—
—
—
0 (TL)
0 (TL)
0 (TL)
—
VDDIO0
PL2D
PL2C
Vss
VDDIO0
PL2D
PL2C
Vss
VDDIO0
PL2D
PL2C
Vss
PLL_CK0C/HPPLL
L21C_D2
7
IO
PLL_CK0T/HPPLL L21T_D2
—
7
Vss
IO
—
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PL2B
PL2A
PL3D
PL3C
VDDIO0
PL3B
PL3A
PL4D
PL4C
Vss
PL3D
PL3C
PL4D
PL4C
VDDIO0
PL4B
PL4A
PL5D
PL5C
Vss
PL3D
PL3C
PL4D
PL4C
VDDIO0
PL5D
PL5C
PL6D
PL6C
Vss
—
L22C_D0
L22T_D0
L23C_D2
L23T_D2
—
7
IO
VREF_0_07
7
IO
D5
7
IO
D6
—
8
VDDIO0
IO
—
—
L24C_D0
L24T_D0
L25C_D3
L25T_D3
—
8
IO
VREF_0_08
8
IO
HDC
F1
A18
H4
G3
H3
G2
K5
G1
J4
8
IO
LDC_N
—
8
Vss
IO
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PL4B
PL4A
PL5D
PL5C
PL5B
PL5A
PL6D
PL6C
Vss
PL5B
PL5A
PL6D
PL6C
PL7D
PL7C
PL8D
PL8C
Vss
PL7D
PL7C
PL8D
PL8C
PL9D
PL9C
PL10D
PL10C
Vss
—
L26C_D0
L26T_D0
L27C_D0
L27T_D0
L28C_D3
L28T_D3
L29C_D1
L29T_D1
—
8
IO
—
TESTCFG
D7
9
IO
9
IO
9
IO
VREF_0_09
A17/PPC_A31
CS0_N
CS1
9
IO
9
IO
L5
9
IO
A33
J3
—
10
10
10
10
10
10
1
Vss
IO
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
PL6B
PL6A
PL7D
PL7C
PL7B
PL7A
PL8D
PL8C
VDDIO7
PL8B
PL8A
PL9D
PL9C
PL9D
PL9C
PL10D
PL10C
PL11D
PL11C
PL12D
PL12C
VDDIO7
PL12B
PL12A
PL13D
PL13C
PL11D
PL11C
PL12D
PL12C
PL13D
PL13C
PL14D
PL14C
VDDIO7
PL15D
PL15C
PL16D
PL16C
—
L30C_D0
L30T_D0
L31C_D0
L31T_D0
L32C_D1
L32T_D1
L1C_D1
L1T_D1
—
H2
H1
J2
IO
—
IO
INIT_N
DOUT
IO
J1
IO
VREF_0_10
A16/PPC_A30
A15/PPC_A29
A14/PPC_A28
—
K3
L4
IO
IO
K2
L1
1
IO
—
1
VDDIO7
IO
K1
L2
—
L2C_D0
L2T_D0
L3C_D1
L3T_D1
1
IO
—
L3
1
IO
VREF_7_01
D4
N5
1
IO
126
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Pair
BM680
I/O
OR4E02
OR4E04
OR4E06
Bank Group
Function
AM22
M4
M2
P5
—
—
2
Vss
IO
Vss
Vss
Vss
—
—
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
PL9B
PL13B
PL13A
PL14D
PL14C
VDDIO7
PL15D
PL15C
PL16D
PL16C
Vss
PL17D
PL17C
PL18D
PL18C
VDDIO7
PL19D
PL19C
PL20D
PL20C
Vss
—
L4C_A1
L4T_A1
L5C_D3
L5T_D3
—
2
IO
PL9A
—
RDY/BUSY_N/RCLK
2
IO
PL10D
PL10C
VDDIO7
PL10B
PL10A
PL11D
PL11C
Vss
M1
M3
N1
2
IO
VREF_7_02
—
2
VDDIO7
IO
—
A13/PPC_A27
L6C_A2
L6T_A2
L7C_D0
L7T_D0
—
N4
2
IO
A12/PPC_A26
N2
3
IO
—
P1
3
IO
—
AM32
P2
—
3
Vss
IO
—
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
PL11B
PL11A
PL12D
PL12C
PL12B
PL12A
PL13D
PL13C
Vss
PL17D
PL17C
PL18D
PL18C
PL18B
PL18A
PL19D
PL19C
Vss
PL21D
PL21C
PL22D
PL22C
PL22B
PL22A
PL23D
PL23C
Vss
A11/PPC_A25
L8C_A0
L8T_A0
L9C_D2
L9T_D2
L10C_A1
L10T_A1
L11C_D0
L11T_D0
—
P3
3
IO
VREF_7_03
P4
3
IO
—
R1
3
IO
—
R4
3
IO
—
R2
3
IO
—
RD_N/MPI_STRB_N
U5
4
IO
T4
4
IO
VREF_7_04
AN1
V5
—
4
Vss
IO
—
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
PL13B
PL13A
PL14D
PL14C
VDDIO7
PL14B
PL14A
Vss
PL19B
PL19A
PL20D
PL20C
VDDIO7
PL20B
PL20A
Vss
PL23B
PL23A
PL24D
PL24C
VDDIO7
PL24B
PL24A
Vss
—
L12C_D3
L12T_D3
L13C_A0
L13T_A0
—
T1
4
IO
—
T2
4
IO
PLCK0C
T3
4
IO
PLCK0T
R3
—
4
VDDIO7
IO
—
U4
—
—
L14C_A0
L14T_A0
—
U3
4
IO
AN2
U2
—
5
Vss
IO
—
7 (CL)
7 (CL)
—
PL15D
PL15C
Vss
PL21D
PL21C
Vss
PL25D
PL25C
Vss
A10/PPC_A24
A9/PPC_A23
—
L15C_A0
L15T_A0
—
V2
5
IO
AN33
V3
—
5
Vss
IO
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
—
PL15B
PL15A
PL16D
PL16C
PL16B
PL16A
PL17D
PL17C
Vss
PL21B
PL21A
PL22D
PL22C
PL23D
PL23C
PL24D
PL24C
Vss
PL25B
PL25A
PL26D
PL26C
PL27D
PL27C
PL28D
PL28C
Vss
—
L16C_A0
L16T_A0
L17C_A2
L17T_A2
L18C_D1
L18T_D1
L19C_D2
L19T_D2
—
V4
5
IO
—
W5
W2
W3
Y1
5
IO
A8/PPC_A22
VREF_7_05
—
5
IO
5
IO
5
IO
—
W4
AA1
AN34
Y5
6
IO
PLCK1C
PLCK1T
—
6
IO
—
6
Vss
IO
7 (CL)
7 (CL)
7 (CL)
7 (CL)
PL17B
PL17A
PL18D
PL18C
PL25D
PL25C
PL26D
PL26C
PL29D
PL29C
PL30D
PL30C
VREF_7_06
A7/PPC_A21
A6/PPC_A20
A5/PPC_A19
L20C_A0
L20T_A0
L21C_D3
L21T_D3
Y4
6
IO
AA5
AB1
6
IO
6
IO
Lattice Semiconductor
127
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Function
BM680
I/O
OR4E02
OR4E04
OR4E06
Pair
Bank Group
U1
AB2
AA4
AB4
AB5
AC1
AC2
AC5
W1
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
6 (BL)
6 (BL)
—
—
7
VDDIO7
IO
VDDIO7
PL18B
PL19D
PL19C
PL19B
PL19A
PL20D
PL20C
VDDIO7
PL20B
PL20A
PL21D
PL21C
PL21B
PL21A
PL22D
PL22C
Vss
VDDIO7
PL26B
PL27D
PL27C
PL27B
PL27A
PL28D
PL28C
VDDIO7
PL29D
PL29C
PL30D
PL30C
PL31D
PL31C
PL32D
PL32C
Vss
VDDIO7
PL31D
PL32D
PL32C
PL33D
PL33C
PL34D
PL34C
VDDIO7
PL35D
PL35C
PL36D
PL36C
PL37D
PL37C
PL38D
PL38C
Vss
—
—
—
—
7
IO
WR_N/MPI_RW
L22C_A0
L22T_A0
L23C_D3
L23T_D3
L23C_A2
L23T_A2
—
7
IO
VREF_7_07
7
IO
—
7
IO
—
8
IO
A4/PPC_A18
8
IO
VREF_7_08
—
8
VDDIO7
IO
—
AD2
AD3
AE1
AE2
AD4
AE3
AF1
AF2
AB13
AF3
AF4
AE5
AG1
AK5
AG2
AF5
AG3
AG4
AB14
AH1
AH3
AH4
AG5
AL3
AH2
AJ3
A3/PPC_A17
L23C_A0
L23T_A0
L24C_A0
L24T_A0
L25C_D0
L25T_D0
L1C_A0
L1T_A0
—
8
IO
A2/PPC_A16
8
IO
A1/PPC_A15
8
IO
A0/PPC_A14
8
IO
DP0
8
IO
DP1
1
IO
D8
1
IO
VREF_6_01
—
1
Vss
IO
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
PL22B
PL22A
PL23D
PL23C
VDDIO6
PL23B
PL23A
PL24D
PL24C
Vss
PL33D
PL33C
PL34D
PL34C
VDDIO6
PL34B
PL34A
PL35B
PL35A
Vss
PL39D
PL39C
PL40D
PL40C
VDDIO6
PL41D
PL41C
PL42D
PL42C
Vss
D9
L2C_A0
L2T_A0
L3C_D3
L3T_D3
—
1
IO
D10
2
IO
—
2
IO
VREF_6_02
—
2
VDDIO6
IO
—
—
L4C_D2
L4T_D2
L5C_A0
L5T_A0
—
2
IO
—
3
IO
D11
3
IO
D12
—
3
Vss
IO
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
PL24B
PL24A
PL25D
PL25C
VDDIO6
PL25B
PL25A
PL26D
PL26C
Vss
PL36D
PL36C
PL36B
PL36A
VDDIO6
PL37D
PL38C
PL37B
PL37A
Vss
PL43D
PL43C
PL44D
PL44C
VDDIO6
PL44B
PL45A
PL45D
PL45C
Vss
—
L6C_A1
L6T_A1
L7C_D0
L7T_D0
—
3
IO
—
3
IO
VREF_6_03
3
IO
D13
—
4
VDDIO6
IO
—
—
—
4
IO
—
—
AJ2
4
IO
—
L8C_D2
L8T_D2
—
AH5
AB15
AJ4
4
IO
VREF_6_04
—
4
Vss
IO
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
PL26B
PL26A
PL27D
PL27C
Vss
PL38B
PL38A
PL39D
PL39C
Vss
PL46D
PL46A
PL47D
PL47C
Vss
—
—
—
AJ1
4
IO
—
PLL_CK7C/HPPLL
AK1
AK2
AB20
AJ5
4
IO
L9C_A0
4
IO
PLL_CK7T/HPPLL L9T_A0
—
4
Vss
IO
—
—
—
6 (BL)
PL27B
PL39B
PL47B
L10C_D1
128
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Pair
BM680
I/O
OR4E02
OR4E04
OR4E06
Bank Group
Function
AK3
AB21
AK4
AM1
AL1
6 (BL)
—
4
—
—
—
—
—
—
—
5
IO
Vss
I
PL27A
Vss
PL39A
Vss
PL47A
Vss
—
—
L10T_D1
—
—
PTEMP
VDDIO6
LVDS_R
VDD33
Vss
PTEMP
VDDIO6
LVDS_R
VDD33
Vss
PTEMP
VDDIO6
LVDS_R
VDD33
Vss
PTEMP
—
—
6 (BL)
—
VDDIO6
IO
—
LVDS_R
—
—
—
AL2
—
VDD33
Vss
VDD33
IO
AB22
AK6
AL5
—
—
—
—
VDD33
PB2A
PB2B
VDDIO6
PB2C
PB2D
PB3A
PB3B
PB3C
PB3D
PB4A
PB4B
Vss
VDD33
PB2A
PB2B
VDDIO6
PB2C
PB2D
PB3C
PB3D
PB4A
PB4B
PB4C
PB4D
Vss
VDD33
PB2A
PB2B
VDDIO6
PB2C
PB2D
PB3C
PB3D
PB4C
PB4D
PB5C
PB5D
Vss
—
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
—
DP2
—
L11T_A0
L11C_A0
—
AM5
AM2
AN4
AK7
AL6
5
IO
—
5
VDDIO6
IO
—
PLL_CK6T/PPLL L12T_D2
PLL_CK6C/PPLL L12C_D2
5
IO
5
IO
—
L13T_A0
L13C_A0
L14T_D1
L14C_D1
L15T_D3
L15C_D3
—
AM6
AL7
5
IO
—
5
IO
VREF_6_05
AN5
AK8
AP5
AB32
AN6
AK9
AP6
AL8
5
IO
DP3
6
IO
—
6
IO
—
—
6
Vss
IO
—
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
PB4C
PB4D
PB5A
PB5B
VDDIO6
PB5C
PB5D
PB6A
PB6B
Vss
PB5C
PB5D
PB6A
PB6B
VDDIO6
PB6C
PB6D
PB7C
PB7D
Vss
PB6C
PB6D
PB7C
PB7D
VDDIO6
PB8C
PB8D
PB9C
PB9D
Vss
VREF_6_06
L16T_D2
L16C_D2
L17T_D2
L17C_D2
—
6
IO
D14
6
IO
—
6
IO
—
AM4
AM7
AM8
—
7
VDDIO6
IO
—
D15
D16
D17
D18
—
L18T_A0
L18C_A0
L19T_D3
L19C_D3
—
7
IO
AK10 6 (BL)
7
IO
AP7
AL4
6 (BL)
—
7
IO
—
7
Vss
IO
AK11 6 (BL)
AM9 6 (BL)
AL10 6 (BL)
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
PB8A
PB8B
Vss
PB8C
PB8D
PB9C
PB9D
PB10C
PB10D
PB11A
PB11B
Vss
PB10C
PB10D
PB11C
PB11D
PB12C
PB12D
PB13A
PB13B
Vss
VREF_6_07
D19
D20
D21
VREF_6_08
D22
—
L20T_D1
L20C_D1
L21T_D2
L21C_D2
L22T_D1
L22C_D1
L23T_D0
L23C_D0
—
7
IO
8
IO
AP8
AP9
6 (BL)
6 (BL)
8
IO
8
IO
AM10 6 (BL)
AK12 6 (BL)
AL11 6 (BL)
8
IO
9
IO
9
IO
—
AL31
—
—
9
Vss
IO
—
AN10 6 (BL)
AP10 6 (BL)
AN11 6 (BL)
AM11 6 (BL)
PB8C
PB8D
PB9A
PB9B
VDDIO6
PB11C
PB11D
PB12A
PB12B
VDDIO6
PB13C
PB13D
PB14A
PB14B
VDDIO6
D23
D24
—
L24T_A0
L24C_A0
L25T_A0
L25C_A0
—
9
IO
9
IO
9
IO
—
AN3
6 (BL)
—
VDDIO6
—
Lattice Semiconductor
129
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Function
BM680
I/O
OR4E02
OR4E04
OR4E06
Pair
Bank Group
AK13 6 (BL)
AL12 6 (BL)
AN12 6 (BL)
AK14 6 (BL)
9
9
IO
IO
PB9C
PB9D
PB12C
PB12D
PB13A
PB13B
Vss
PB14C
PB14D
PB15C
PB15D
Vss
VREF_6_09
L26T_D0
L26C_D0
L27T_D2
L27C_D2
—
D25
9
IO
PB10A
PB10B
Vss
—
9
IO
—
AM3
—
—
10
10
10
10
—
10
10
11
11
—
11
11
1
Vss
IO
—
AP12 6 (BL)
AP13 6 (BL)
AL13 6 (BL)
AN13 6 (BL)
PB10C
PB10D
PB11A
PB11B
VDDIO6
PB11C
PB11D
PB12A
PB12B
Vss
PB13C
PB13D
PB14A
PB14B
VDDIO6
PB14C
PB14D
PB15C
PB15D
Vss
PB16C
PB16D
PB17C
PB17D
VDDIO6
PB18C
PB18D
PB19C
PB19D
Vss
D26
L28T_A0
L28C_A0
L29T_A1
L29C_A1
—
IO
D27
IO
—
IO
—
AP3
6 (BL)
VDDIO6
IO
—
AP14 6 (BL)
AK15 6 (BL)
AM14 6 (BL)
AK16 6 (BL)
VREF_6_10
L30T_D3
L30C_D3
L31T_D1
L31C_D1
—
IO
D28
IO
D29
IO
D30
AM13
—
Vss
IO
—
AP15 6 (BL)
AL15 6 (BL)
AN16 5 (BC)
AK17 5 (BC)
AM16 5 (BC)
AP16 5 (BC)
AN17 5 (BC)
AL17 5 (BC)
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
PB14A
PB14B
Vss
PB16C
PB16D
PB17C
PB17D
PB18C
PB18D
PB19A
PB19B
Vss
PB20C
PB20D
PB21C
PB21D
PB22C
PB22D
PB23A
PB23B
Vss
VREF_6_11
L32T_A2
L32C_A2
L1T_D2
L1C_D2
L2T_A1
L2C_A1
L3T_A1
L3C_A1
—
IO
D31
IO
—
1
IO
—
1
IO
VREF_5_01
1
IO
—
2
IO
—
2
IO
—
Y15
—
—
2
Vss
IO
—
AM17 5 (BC)
AM18 5 (BC)
AL18 5 (BC)
AN18 5 (BC)
AM12 5 (BC)
AL19 5 (BC)
AK18 5 (BC)
AM19 5 (BC)
AN19 5 (BC)
AP20 5 (BC)
AN20 5 (BC)
AP21 5 (BC)
AN21 5 (BC)
PB14C
PB14D
PB15A
PB15B
VDDIO5
PB15C
PB15D
PB16A
PB16B
PB16C
PB16D
PB17A
PB17B
Vss
PB19C
PB19D
PB20A
PB20B
VDDIO5
PB20C
PB20D
PB21A
PB21B
PB21C
PB21D
PB22C
PB22D
Vss
PB23C
PB23D
PB24A
PB24B
VDDIO5
PB24C
PB24D
PB25C
PB25D
PB26C
PB26D
PB27C
PB27D
Vss
PBCK0T
L4T_A0
L4C_A0
L5T_A1
L5C_A1
—
2
IO
PBCK0C
2
IO
—
2
IO
—
—
2
VDDIO5
IO
—
VREF_5_02
L6T_D0
L6C_D0
L7T_A0
L7C_A0
L8T_A0
L8C_A0
L9T_A0
L9C_A0
—
2
IO
—
2
IO
—
2
IO
—
3
IO
—
3
IO
VREF_5_03
3
IO
—
3
IO
—
Y20
—
—
3
Vss
IO
—
PBCK1T
PBCK1C
—
AM21 5 (BC)
AL21 5 (BC)
AP22 5 (BC)
AN22 5 (BC)
AM15 5 (BC)
AL22 5 (BC)
PB17C
PB17D
PB18A
PB18B
VDDIO5
PB18C
PB23C
PB23D
PB24C
PB24D
VDDIO5
PB25C
PB28C
PB28D
PB29C
PB29D
VDDIO5
PB30C
L10T_A0
L10C_A0
L11T_A0
L11C_A0
—
3
IO
4
IO
4
IO
—
—
4
VDDIO5
IO
—
—
L12T_A0
130
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Pair
BM680
I/O
OR4E02
OR4E04
OR4E06
Bank Group
Function
AL23 5 (BC)
Y21
4
—
4
IO
Vss
IO
PB18D
Vss
PB25D
Vss
PB30D
Vss
VREF_5_04
L12C_A0
—
—
—
AK22 5 (BC)
AN23 5 (BC)
PB19A
PB19B
Vss
PB26A
PB26B
Vss
PB31C
PB31D
Vss
—
L13T_D2
L13C_D2
—
4
IO
—
Y22
—
—
5
Vss
IO
—
AP23 5 (BC)
AK23 5 (BC)
AN24 5 (BC)
AM24 5 (BC)
AM20 5 (BC)
AL24 5 (BC)
AP25 5 (BC)
AK24 5 (BC)
AP26 5 (BC)
AL25 5 (BC)
AM25 5 (BC)
AP27 4 (BR)
AN27 4 (BR)
PB19C
PB19D
PB20A
PB20B
VDDIO5
PB20C
PB20D
PB21A
PB21B
PB21C
PB21D
PB22A
PB22B
Vss
PB26C
PB26D
PB27A
PB27B
VDDIO5
PB27C
PB27D
PB28C
PB28D
PB29C
PB29D
PB30C
PB30D
Vss
PB32C
PB32D
PB33C
PB33D
VDDIO5
PB34C
PB34D
PB35C
PB35D
PB36C
PB36D
PB37C
PB37D
Vss
—
L14T_A3
L14C_A3
L15T_A0
L15C_A0
—
5
IO
VREF_5_05
5
IO
—
5
IO
—
—
5
VDDIO5
IO
—
—
L16T_D2
L16T_D2
L17T_D3
L17C_D3
L18T_A0
L18C_A0
L1T_A0
L1C_A0
—
5
IO
—
6
IO
—
6
IO
VREF_5_06
6
IO
—
6
IO
—
1
IO
—
1
IO
—
V16
—
—
1
Vss
IO
—
AK25 4 (BR)
AL26 4 (BR)
AM27 4 (BR)
AK26 4 (BR)
AK30 4 (BR)
AP28 4 (BR)
AN28 4 (BR)
AL27 4 (BR)
AL28 4 (BR)
PB22C
PB22D
PB23A
PB23B
VDDIO4
PB23C
PB23D
PB24A
PB24B
Vss
PB31C
PB31D
PB32C
PB32D
VDDIO4
PB33C
PB33D
PB34A
PB34B
Vss
PB38C
PB38D
PB39C
PB39D
VDDIO4
PB40C
PB40D
PB41C
PB41D
Vss
VREF_4_01
L2T_D0
L2C_D0
L3T_D1
L3C_D1
—
1
IO
—
1
IO
—
1
IO
—
—
2
VDDIO4
IO
—
—
L4T_A0
L4C_A0
L5T_A0
L5C_A0
—
2
IO
VREF_4_02
2
IO
—
2
IO
—
V17
—
—
2
Vss
IO
—
AK27 4 (BR)
AM28 4 (BR)
AN29 4 (BR)
AL32 4 (BR)
AK28 4 (BR)
AM29 4 (BR)
AL29 4 (BR)
AP29 4 (BR)
PB24C
PB25A
PB25B
VDDIO4
PB25C
PB25D
PB26A
PB26B
Vss
PB34C
PB35A
PB35B
VDDIO4
PB35C
PB35D
PB36A
PB36B
Vss
PB42C
PB43A
PB43D
VDDIO4
PB44C
PB44D
PB45A
PB45B
Vss
—
—
3
IO
—
—
3
IO
—
—
—
3
VDDIO4
IO
—
—
—
L6T_D1
L6C_D1
L7T_A2
L7C_A2
—
3
IO
VREF_4_03
3
IO
—
3
IO
—
V18
—
—
3
Vss
IO
—
AP30 4 (BR)
AN30 4 (BR)
AK29 4 (BR)
AM30 4 (BR)
PB26C
PB26D
PB27A
PB27B
Vss
PB36C
PB36D
PB37A
PB37B
Vss
PB45C
PB45D
PB46C
PB46D
Vss
—
L8T_A0
L8C_A0
L9T_D1
L9C_D1
—
3
IO
—
4
IO
—
VREF_4_04
—
4
IO
V19
—
—
4
Vss
IO
AL30 4 (BR)
PB27C
PB37C
PB47C
PLL_CK5T/PPLL L10T_D2
Lattice Semiconductor
131
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Function
BM680
I/O
OR4E02
OR4E04
OR4E06
Pair
Bank Group
AP31 4 (BR)
4
—
—
—
—
—
5
IO
VDD33
Vss
Vss
VDD33
VDDIO4
IO
PB27D
VDD33
Vss
PB37D
VDD33
Vss
PB47D
VDD33
Vss
PLL_CK5C/PPLL L10C_D2
AN31
V34
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W16
AK31
Vss
Vss
Vss
VDD33
VDDIO4
PR26A
PR26B
Vss
VDD33
VDDIO4
PR38A
PR38B
Vss
VDD33
VDDIO4
PR46C
PR46D
Vss
AM31 4 (BR)
AJ30 4 (BR)
AK32 4 (BR)
PLL_CK4T/PLL2 L11T_D1
PLL_CK4C/PLL2 L11C_D1
5
IO
W17
—
—
5
Vss
IO
—
—
AL33 4 (BR)
AH30 4 (BR)
AL34 4 (BR)
AJ31 4 (BR)
PR26C
PR26D
PR25A
PR25B
Vss
PR38C
PR38D
PR37A
PR37B
Vss
PR45C
PR45D
PR44C
PR44D
Vss
—
L12T_D2
L12C_D2
L13T_D2
L13C_D2
—
5
IO
—
5
IO
VREF_4_05
5
IO
—
W18
—
—
6
Vss
IO
—
AJ32 4 (BR)
AH31 4 (BR)
AK33 4 (BR)
AG30 4 (BR)
AM34 4 (BR)
AK34 4 (BR)
AJ33 4 (BR)
AJ34 4 (BR)
AG31 4 (BR)
PR25C
PR25D
PR24A
PR24B
VDDIO4
PR24C
PR24D
PR23A
PR23B
Vss
PR36A
PR36B
PR36C
PR36D
VDDIO4
PR35C
PR35D
PR34C
PR34D
Vss
PR43C
PR43D
PR42C
PR42D
VDDIO4
PR41C
PR41D
PR40C
PR40D
Vss
—
L14T_D0
L14C_D0
L15T_D2
L15C_D2
—
6
IO
—
6
IO
—
6
IO
—
—
6
VDDIO4
IO
—
VREF_4_06
L16T_D0
L16C_D0
L17T_D2
L17C_D2
—
6
IO
—
7
IO
—
7
IO
—
W19
—
—
7
Vss
IO
—
AG32 4 (BR)
AH33 4 (BR)
AH34 4 (BR)
AF31 4 (BR)
AG33 4 (BR)
AE31 4 (BR)
AG34 4 (BR)
AF33 4 (BR)
PR23C
PR23D
PR22A
PR22B
PR22C
PR22D
PR21A
PR21B
Vss
PR33C
PR33D
PR32C
PR32D
PR31C
PR31D
PR30A
PR30B
Vss
PR39C
PR39D
PR38C
PR38D
PR37C
PR37D
PR36A
PR36B
Vss
—
L18T_D0
L18C_D0
L19T_D2
L19C_D2
L20T_D1
L20C_D1
L22T_D0
L22C_D0
—
7
IO
VREF_4_07
7
IO
—
7
IO
—
8
IO
—
8
IO
VREF_4_08
8
IO
—
8
IO
—
Y13
—
—
8
Vss
IO
—
AD30 4 (BR)
AF34 4 (BR)
AE32 3 (CR)
AC30 3 (CR)
PR21C
PR21D
PR20A
PR20B
VDDIO3
PR20C
PR20D
PR19A
PR19B
Vss
PR30C
PR30D
PR29A
PR29B
VDDIO3
PR29C
PR29D
PR28A
PR28B
Vss
PR36C
PR36D
PR35C
PR35D
VDDIO3
PR34C
PR34D
PR34A
PR33B
Vss
—
L21T_D3
L21C_D3
L1T_D1
L1C_D1
—
8
IO
—
1
IO
—
1
IO
—
L34
3 (CR)
—
1
VDDIO3
IO
—
AE33 3 (CR)
AC31 3 (CR)
AD31 3 (CR)
AE34 3 (CR)
—
L2T_D1
L2C_D1
—
1
IO
—
1
IO
—
1
IO
—
—
—
R21
—
—
1
Vss
IO
—
AD32 3 (CR)
PR19C
PR28C
PR33C
VREF_3_01
L3T_D1
132
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Pair
BM680
I/O
OR4E02
OR4E04
OR4E06
Bank Group
Function
AB30 3 (CR)
AB31 3 (CR)
AA30 3 (CR)
M32 3 (CR)
AC33 3 (CR)
AB33 3 (CR)
AA32 3 (CR)
1
2
IO
IO
PR19D
PR18A
PR18B
VDDIO3
PR18C
PR18D
PR17A
PR17B
Vss
PR28D
PR27A
PR27B
VDDIO3
PR26A
PR26B
PR25A
PR25B
Vss
PR33D
PR32C
PR32D
VDDIO3
PR31C
PR31D
PR30C
PR30D
Vss
—
L3C_D1
L4T_D0
L4C_D0
—
—
2
IO
—
—
2
VDDIO3
IO
—
—
L5T_A0
L5C_A0
L6T_D1
L6C_D1
—
2
IO
VREF_3_02
2
IO
—
Y30
R22
3 (CR)
—
2
IO
—
—
3
Vss
IO
—
AB34 3 (CR)
W30 3 (CR)
AA33 3 (CR)
W31 3 (CR)
PR17C
PR17D
PR16A
PR16B
PR16C
PR16D
PR15A
PR15B
VDDIO3
PR15C
PR15D
Vss
PR25C
PR25D
PR24C
PR24D
PR23C
PR23D
PR22C
PR22D
VDDIO3
PR21C
PR21D
Vss
PR29C
PR29D
PR28C
PR28D
PR27C
PR27D
PR26C
PR26D
VDDIO3
PR25C
PR25D
Vss
—
L7T_D3
L7C_D3
L8T_D1
L8C_D1
L9T_D0
L9C_D0
L10T_A0
L10C_A0
—
3
IO
VREF_3_03
3
IO
—
3
IO
—
Y34
3 (CR)
4
IO
PRCK1T
W33 3 (CR)
4
IO
PRCK1C
V30
V31
R32
V33
V32
T16
T34
U31
T32
T31
R31
R34
T17
P34
P32
P31
P33
U34
N33
N31
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
4
IO
—
4
IO
VREF_3_04
—
5
VDDIO3
IO
—
—
L11T_A0
L11C_A0
—
5
IO
—
—
5
Vss
IO
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
—
PR14A
PR14B
PR14C
PR14D
PR13A
PR13B
Vss
PR20C
PR20D
PR19C
PR19D
PR18C
PR18D
Vss
PR24C
PR24D
PR23C
PR23D
PR22C
PR22D
Vss
PRCK0T
L13T_D2
L13C_D2
L14T_A0
L14C_A0
L15T_D1
L15C_D1
—
5
IO
PRCK0C
5
IO
VREF_3_05
5
IO
—
5
IO
—
5
IO
—
—
6
Vss
IO
—
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
PR13C
PR13D
PR12A
PR12B
VDDIO3
PR12C
PR12D
PR11A
PR11B
Vss
PR17C
PR17D
PR16C
PR16D
VDDIO3
PR15A
PR15B
PR14A
PR14B
Vss
PR21C
PR21D
PR20C
PR20D
VDDIO3
PR19C
PR19D
PR18C
PR18D
Vss
—
L16T_A1
L16C_A1
L17T_A1
L17C_A1
—
6
IO
VREF_3_06
6
IO
—
6
IO
—
—
7
VDDIO3
IO
—
—
L18T_A1
L18C_A1
L19T_A1
L19C_A1
—
7
IO
—
M31 3 (CR)
M33 3 (CR)
7
IO
—
7
IO
—
T18
—
—
7
Vss
IO
—
M34 3 (CR)
PR11C
PR11D
PR10A
PR10B
VDDIO3
PR10C
PR14C
PR14D
PR13A
PR13B
VDDIO3
PR13C
PR17C
PR17D
PR15A
PR16D
VDDIO3
PR15C
VREF_3_07
L20T_D1
L20C_D1
—
L32
L33
L31
3 (CR)
3 (CR)
3 (CR)
7
IO
—
—
—
—
—
8
IO
8
IO
—
W34 3 (CR)
K34 3 (CR)
—
8
VDDIO3
IO
—
L21T_A0
Lattice Semiconductor
133
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Function
BM680
I/O
OR4E02
OR4E04
OR4E06
Pair
Bank Group
K33
K32
T19
N30
K31
H34
J34
3 (CR)
3 (CR)
—
8
8
IO
IO
PR10D
PR9A
Vss
PR13D
PR12A
Vss
PR15D
PR14A
Vss
—
L21C_A0
—
—
—
8
Vss
IO
—
—
3 (CR)
3 (CR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
PR7A
PR7B
Vss
PR12C
PR12D
PR11A
PR11B
PR11C
PR11D
PR10C
PR10D
Vss
PR14C
PR14D
PR13A
PR13B
PR13C
PR13D
PR12C
PR12D
Vss
VREF_3_08
L22T_D2
L22C_D2
L1T_A0
L1C_A0
L2T_A1
L2C_A1
L3T_D1
L3C_D1
—
8
IO
—
1
IO
—
1
IO
—
J33
1
IO
—
J31
1
IO
VREF_2_01
J32
1
IO
—
G34
N32
H33
H32
H31
G33
A32
F33
G32
K30
G31
P13
E34
J30
1
IO
—
—
1
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PR7C
PR7D
PR6A
PR6B
VDDIO2
PR6C
PR6D
PR5A
PR5B
Vss
PR9C
PR9D
PR7A
PR7B
VDDIO2
PR6A
PR6B
PR6C
PR6D
Vss
PR11C
PR11D
PR10C
PR10D
VDDIO2
PR9C
PR9D
PR8C
PR8D
Vss
—
L4T_A0
L4C_A0
L5T_D1
L5C_D1
—
1
IO
—
2
IO
—
2
IO
—
—
2
VDDIO2
IO
—
VREF_2_02
L6T_D0
L6C_D0
L7T_D2
L7C_D2
—
2
IO
—
2
IO
—
2
IO
—
—
3
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PR5C
PR5D
PR4A
PR4B
VDDIO2
PR4C
PR4D
PR3A
PR3B
Vss
PR5A
PR5B
PR4A
PR4B
VDDIO2
PR4C
PR4D
PR3A
PR3B
Vss
PR7C
PR7D
PR6C
PR6D
VDDIO2
PR5C
PR5D
PR4C
PR4D
Vss
—
L8T_D2
L8C_D2
L9T_A0
L9C_A0
—
3
IO
VREF_2_03
F32
F31
B32
E33
D33
H30
E32
P14
E31
G30
C31
F30
P15
P20
E29
D30
C30
B31
P21
E28
3
IO
—
3
IO
—
—
3
VDDIO2
IO
—
—
L10T_A0
L10C_A0
L11T_D2
L11C_D2
—
3
IO
—
4
IO
—
VREF_2_04
—
4
IO
—
4
Vss
IO
2 (TR)
2 (TR)
2 (TR)
—
PR3C
PR3D
VDDIO2
VDD33
Vss
PR3C
PR3D
VDDIO2
VDD33
Vss
PR3C
PR3D
VDDIO2
VDD33
Vss
PLL_CK3T/PLL1
L12T_A0
4
IO
PLL_CK3C/PLL1 L12C_A0
—
—
—
—
—
—
5
VDDIO2
VDD33
Vss
Vss
VDD33
IO
—
—
—
—
—
—
—
—
—
—
—
Vss
Vss
Vss
—
—
VDD33
PLL_VF
PT27D
PT27C
Vss
VDD33
PLL_VF
PT37D
PT37C
Vss
VDD33
PLL_VF
PT47D
PT47C
Vss
—
—
PLL_VF
2 (TR)
2 (TR)
—
IO
PLL_CK2C/PPLL L13C_D0
PLL_CK2T/PPLL L13T_D0
5
IO
—
5
Vss
IO
—
—
—
2 (TR)
PT27B
PT37B
PT46D
L14C_D2
134
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Pair
BM680
I/O
OR4E02
OR4E04
OR4E06
Bank Group
Function
B30
D29
A31
C33
E27
C29
A30
E26
P22
A29
D27
C28
C27
C34
B28
E25
A28
D26
R13
C26
B27
D25
A27
B26
A26
C25
E24
C22
A25
D24
D23
B25
A11
C24
E23
B24
D22
C32
E22
D21
D4
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
5
5
IO
IO
PT27A
PT26D
PT26C
VDDIO2
PT26B
PT26A
PT25D
PT25C
Vss
PT37A
PT36D
PT36C
VDDIO2
PT35B
PT35A
PT34D
PT34C
Vss
PT46C
PT45D
PT45C
VDDIO2
PT43D
PT43C
PT42D
PT42C
Vss
—
L14T_D2
L15C_D2
L15T_D2
—
VREF_2_05
5
IO
—
—
6
VDDIO2
IO
—
—
L17C_D1
L17T_D1
L18C_D3
L18T_D3
—
6
IO
—
6
IO
VREF_2_06
6
IO
—
—
7
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
—
PT25B
PT25A
PT24D
PT24C
VDDIO2
PT24B
PT24A
PT23D
PT23C
Vss
PT34B
PT34A
PT33D
PT33C
VDDIO2
PT32D
PT32C
PT31D
PT31C
Vss
PT41D
PT41C
PT40D
PT40C
VDDIO2
PT39D
PT39C
PT38D
PT38C
Vss
—
L19C_D2
L19T_D2
L20C_A0
L20T_A0
—
7
IO
—
7
IO
—
7
IO
VREF_2_07
—
7
VDDIO2
IO
—
—
L21C_D2
L21T_D2
L22C_D2
L22T_D2
—
7
IO
—
8
IO
—
8
IO
VREF_2_08
—
8
Vss
IO
—
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
1 (TC)
1 (TC)
—
PT23B
PT23A
PT22D
PT22C
PT22B
PT22A
PT21D
PT21C
Vss
PT30D
PT30A
PT29D
PT29C
PT29B
PT29A
PT28D
PT28C
Vss
PT37D
PT37A
PT36D
PT36C
PT36B
PT36A
PT35D
PT35C
Vss
—
—
8
IO
—
—
8
IO
—
L23C_D2
L23T_D2
L24C_A0
L24T_A0
L1C_D1
L1T_D1
—
8
IO
—
8
IO
—
8
IO
—
1
IO
—
1
IO
—
—
1
Vss
IO
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
PT21B
PT21A
PT20D
PT20C
VDDIO1
PT20B
PT20A
PT19D
PT19C
Vss
PT28B
PT28A
PT27D
PT27C
VDDIO1
PT27B
PT27A
PT26D
PT26C
Vss
PT35B
PT35A
PT34D
PT34C
VDDIO1
PT33D
PT33C
PT32D
PT32C
Vss
—
L2C_D2
L2T_D2
L3C_D1
L3T_D1
—
1
IO
—
1
IO
VREF_1_01
1
IO
—
—
1
VDDIO1
IO
—
—
L4C_D1
L4T_D1
L5C_D1
L5T_D1
—
1
IO
—
2
IO
—
2
IO
VREF_1_02
—
2
Vss
IO
—
—
—
—
—
—
—
1 (TC)
1 (TC)
—
PT19B
PT19A
Vss
PT26B
PT26A
Vss
PT31D
PT31C
Vss
L6C_D0
L6T_D0
—
2
IO
—
2
Vss
IO
B23
B22
A17
1 (TC)
1 (TC)
1 (TC)
PT18D
PT18C
VDDIO1
PT25D
PT25C
VDDIO1
PT30D
PT30C
VDDIO1
L7C_A0
L7T_A0
—
2
IO
—
VDDIO1
Lattice Semiconductor
135
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Function
BM680
I/O
OR4E02
OR4E04
OR4E06
Pair
Bank Group
A23
C21
D20
A22
D31
A21
B21
B20
A20
B19
C19
E19
D18
A19
C18
B18
B17
C17
N3
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
3
3
IO
IO
PT18B
PT18A
PT17D
PT17C
Vss
PT24D
PT24C
PT23D
PT23C
Vss
PT29D
PT29C
PT28D
PT28C
Vss
—
L8C_D1
L8T_D1
L9C_D2
L9T_D2
—
VREF_1_03
3
IO
—
3
IO
—
—
3
Vss
IO
—
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
PT17B
PT17A
PT16D
PT16C
PT16B
PT16A
PT15D
PT15C
VDDIO1
PT15B
PT15A
PT14D
PT14C
Vss
PT22D
PT22C
PT21D
PT21C
PT20D
PT20C
PT19D
PT19C
VDDIO1
PT19B
PT19A
PT18D
PT18C
Vss
PT27D
PT27C
PT26D
PT26C
PT25D
PT25C
PT24D
PT24C
VDDIO1
PT24B
PT24A
PT23D
PT23C
Vss
—
L10C_A0
L10T_A0
L11C_A0
L11T_A0
L12C_A0
L12T_A0
L13C_D0
L13T_D0
—
3
IO
—
4
IO
—
4
IO
—
4
IO
—
4
IO
—
4
IO
—
4
IO
VREF_1_04
—
4
VDDIO1
IO
—
—
L14C_A0
L14T_A0
L15C_D0
L15T_D0
—
4
IO
—
5
IO
PTCK1C
5
IO
PTCK1T
—
5
Vss
IO
—
A16
D17
B16
C16
E18
A15
D15
A14
N13
E17
A13
E16
D14
A3
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
PT14B
PT14A
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
Vss
PT18B
PT18A
PT17D
PT17C
PT16D
PT16C
PT15D
PT15C
Vss
PT23B
PT23A
PT22D
PT22C
PT21D
PT21C
PT20D
PT20C
Vss
—
L16C_D2
L16T_D2
L17C_A0
L17T_A0
L18C_D3
L18T_D3
L19C_D2
L19T_D2
—
5
IO
—
5
IO
PTCK0C
5
IO
PTCK0T
5
IO
VREF_1_05
5
IO
—
6
IO
—
6
IO
—
—
6
Vss
IO
—
1 (TC)
1 (TC)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PT12B
PT12A
PT11D
PT11C
VDDIO0
PT11B
PT11A
PT10D
PT10C
Vss
PT14D
PT14C
PT13D
PT13C
VDDIO0
PT13B
PT13A
PT12D
PT12C
Vss
PT19D
PT19C
PT18D
PT18C
VDDIO0
PT17D
PT17C
PT16D
PT16C
Vss
—
VREF_1_06
MPI_RTRY_N
MPI_ACK_N
—
L20C_D3
L20T_D3
L1C_D1
L1T_D1
—
6
IO
1
IO
1
IO
—
1
VDDIO0
IO
C14
D13
A12
B12
A34
E15
B11
C11
E14
B3
—
L2C_D0
L2T_D0
L3C_A0
L3T_A0
—
1
IO
VREF_0_01
M0
1
IO
1
IO
M1
—
2
Vss
IO
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
PT10B
PT10A
PT9D
PT12B
PT12A
PT11D
PT11C
VDDIO0
PT11B
PT15D
PT15C
PT14D
PT14C
VDDIO0
PT13D
MPI_CLK
L4C_D3
A21/MPI_BURST_N
2
IO
L4T_D3
L5C_D2
L5T_D2
—
2
IO
M2
M3
2
IO
PT9C
—
2
VDDIO0
IO
VDDIO0
PT9B
—
D12
VREF_0_02
L6C_A0
136
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Pair
BM680
I/O
OR4E02
OR4E04
OR4E06
Bank Group
Function
D11
A10
B10
C9
D10
B9
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
2
3
IO
IO
PT9A
PT8D
PT8C
PT8B
PT8A
PT7D
PT7C
Vss
PT11A
PT10D
PT10C
PT9D
PT9C
PT8D
PT8C
Vss
PT13C
PT12D
PT12C
PT11D
PT11C
PT10D
PT10C
Vss
MPI_TEA_N
L6T_A0
L7C_A0
L7T_A0
L8C_D0
L8T_D0
L9C_A0
L9T_A0
—
—
3
IO
—
3
IO
VREF_0_03
3
IO
—
D0
3
IO
A9
3
IO
TMS
—
B1
—
4
Vss
IO
D9
A8
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PT7B
PT7A
PT6D
PT6C
VDDIO0
PT6B
PT6A
PT5D
PT5C
Vss
PT7D
PT7C
PT6D
PT6C
VDDIO0
PT6B
PT6A
PT5D
PT5C
Vss
PT9D
PT9C
PT8D
PT8C
VDDIO0
PT7D
PT7C
PT6D
PT6C
Vss
A20/MPI_BDIP_N L10C_D2
4
IO
A19/MPI_TSZ1
L10T_D2
L11C_D3
L11T_D3
—
B8
4
IO
A18/MPI_TSZ0
E12
C1
C8
D8
E11
A7
4
IO
D3
—
4
VDDIO0
IO
—
VREF_0_04
L12C_A0
L12T_A0
L13C_D3
L13T_D3
—
4
IO
—
5
IO
D1
5
IO
D2
B2
—
5
Vss
IO
—
A6
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PT5B
PT5A
PT4D
PT4C
VDDIO0
PT4B
PT4A
PT3D
PT3C
Vss
PT5B
PT5A
PT4D
PT4C
VDDIO0
PT4B
PT4A
PT3D
PT3C
Vss
PT5D
PT5C
PT4D
PT4C
VDDIO0
PT4B
PT4A
PT3D
PT3C
Vss
—
L14C_D0
L14T_D0
L15C_A0
L15T_A0
—
B7
5
IO
VREF_0_05
C7
D7
C2
E10
A5
5
IO
TDI
5
IO
TCK
—
5
VDDIO0
IO
—
—
L16C_D4
L16T_D4
L17C_D2
L17T_D2
—
5
IO
—
B6
6
IO
—
E9
6
IO
VREF_0_06
B33
A4
—
6
Vss
IO
—
—
—
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
0 (TL)
—
PT3B
PT3A
PT2D
PT2C
VDDIO0
PT2B
PT2A
PT3B
PT3A
PT2D
PT2C
VDDIO0
PT2B
PT2A
PT3B
PT3A
PT2D
PT2C
VDDIO0
PT2B
PT2A
L18C_D0
L18T_D0
B5
6
IO
D6
C6
C4
C5
E8
6
IO
PLL_CK1C/PPLL L19C_A0
PLL_CK1T/PPLL L19T_A0
6
IO
—
6
VDDIO0
IO
—
—
—
—
L20C_D1
L20T_D1
—
6
IO
PCFG_MPI_IR PCFG_MPI_IR PCFG_MPI_IR
CFG_IRQ_N/
MPI_IRQ_N
E7
—
O
Q
Q
Q
E6
B4
—
—
—
—
—
—
—
—
—
10
IO
IO
PCCLK
PDONE
VDD33
Vss
PCCLK
PDONE
VDD33
Vss
PCCLK
PDONE
VDD33
Vss
CCLK
DONE
—
—
—
—
—
—
—
—
—
137
D5
—
VDD33
Vss
B34
A24
—
—
1 (TC)
VDDIO1
VDDIO5
Vss
VDDIO1
VDDIO5
Vss
VDDIO1
VDDIO5
Vss
VDDIO1
VDDIO5
Vss
—
AM23 5 (BC)
—
AP1
K4
—
—
0 (TL)
IO
Unused
PL9A
PL11A
—
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Function
BM680
I/O
OR4E02
OR4E04
OR4E06
Pair
Bank Group
M5
R5
0 (TL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
7 (CL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
6 (BL)
10
3
3
5
6
6
8
8
1
7
7
8
8
11
11
1
1
3
3
3
4
6
6
1
6
6
3
3
3
6
5
5
6
3
3
7
7
7
8
2
2
2
3
3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
PL11A
PL16A
PL17A
PL23A
PL24A
PL25A
PL29A
PL31A
PL32A
PB7A
PL13A
PL20A
PL21A
PL27A
PL28A
PL29A
PL35A
PL37A
PL38A
PB9A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T5
—
Y2
—
AA2
AA3
AC4
AD5
AE4
AN7
AL9
AN8
AN9
—
—
—
—
—
—
PB8A
PB10A
PB11A
PB12A
PB19A
PB20A
PB21A
PB22A
PB27A
PB28A
PB29A
PB30A
PB35A
PB36A
PB37A
PT44D
PT44C
PT29A
PT28A
PT27A
PT19A
PT22A
PT21A
PT20A
PT12A
PT11A
PR40A
PR39A
PR38A
PR37A
PR31A
PR32B
PR30A
PR29B
PR28A
—
PB9A
—
PB10A
PB15A
PB16A
PB17A
PB18A
PB22A
PB23A
PB24A
PB25A
PB28A
PB29A
PB30A
PT35D
PT35C
PT24A
PT23A
PT22A
PT14A
PT17A
PT16A
PT15A
PT10A
PT9A
—
AN14 6 (BL)
AL14 6 (BL)
AN15 5 (BC)
AL16 5 (BC)
AL20 5 (BC)
AK19 5 (BC)
AK20 5 (BC)
AK21 5 (BC)
AN25 5 (BC)
AN26 5 (BC)
AM26 4 (BR)
—
—
—
—
—
—
—
—
—
—
—
D28
B29
E21
E20
D19
B13
D16
B15
B14
C10
E13
2 (TR)
2 (TR)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
0 (TL)
0 (TL)
L16C_D1
L16T_D1
—
—
—
—
—
—
—
—
—
AF30 4 (BR)
AH32 4 (BR)
AE30 4 (BR)
AF32 4 (BR)
AA31 3 (CR)
AD33 3 (CR)
AC34 3 (CR)
PR34A
PR33A
PR32A
PR31A
PR27C
PR27D
PR26C
PR24B
PR24A
—
—
—
—
—
—
—
Y31
3 (CR)
—
AA34 3 (CR)
—
138
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Pair
BM680
I/O
OR4E02
OR4E04
OR4E06
Bank Group
Function
Y33
3 (CR)
4
4
IO
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
VDDIO7
VDDIO7
VDDIO7
VDDIO5
VDDIO5
VDDIO5
VDDIO5
VDDIO4
VDDIO4
VDDIO3
VDDIO3
VDDIO3
VDDIO2
VDDIO2
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDD15
PR23A
PR22A
PR20A
PR20B
PR19A
PR18A
PR17A
PR16A
PR16B
PR15C
PR15D
PR9A
PR27A
PR26A
PR24A
PR24B
PR23A
PR22A
PR21A
PR20A
PR19B
PR17A
PR18B
PR11A
PR10A
PR9A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W32 3 (CR)
IO
U33
U32
T33
U30
R33
T30
R30
P30
N34
M30
L30
F34
D34
AP4
Y3
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
3 (CR)
2 (TR)
2 (TR)
2 (TR)
2 (TR)
6 (BL)
7 (CL)
7 (CL)
7 (CL)
5
IO
L12T_A0
L12C_A0
—
5
IO
5
IO
5
IO
—
5
IO
—
6
IO
—
6
IO
—
7
IO
—
7
IO
—
1
IO
—
1
IO
PR8A
—
2
IO
PR7C
—
3
IO
PR5C
PR6A
—
5
IO
PB3A
PB3A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDDIO7
VDDIO7
VDDIO7
VDDIO5
VDDIO5
VDDIO5
VDDIO5
VDDIO4
VDDIO4
VDDIO3
VDDIO3
VDDIO3
VDDIO2
VDDIO2
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDDIO7
VDDIO7
VDDIO7
VDDIO5
VDDIO5
VDDIO5
VDDIO5
VDDIO4
VDDIO4
VDDIO3
VDDIO3
VDDIO3
VDDIO2
VDDIO2
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDDIO7
VDDIO7
VDDIO7
VDDIO5
VDDIO5
VDDIO5
VDDIO5
VDDIO4
VDDIO4
VDDIO3
VDDIO3
VDDIO3
VDDIO2
VDDIO2
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
—
AC3
AD1
—
—
AP11 5 (BC)
AP17 5 (BC)
AP19 5 (BC)
AP24 5 (BC)
AN32 4 (BR)
AP32 4 (BR)
—
—
—
—
—
—
Y32
3 (CR)
—
AC32 3 (CR)
AD34 3 (CR)
—
—
D32
E30
C12
C15
C20
C23
N16
Y16
Y17
W13
V13
U13
P18
P19
N17
N18
2 (TR)
2 (TR)
1 (TC)
1 (TC)
1 (TC)
1 (TC)
—
—
—
—
—
—
—
—
—
VDD15
—
—
VDD15
—
—
VDD15
—
—
VDD15
—
—
VDD15
—
—
VDD15
—
—
VDD15
—
—
VDD15
—
—
VDD15
—
Lattice Semiconductor
139
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Function
BM680
I/O
OR4E02
OR4E04
OR4E06
Pair
Bank Group
N19
P16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
Vss
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
Vss
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
Vss
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
Vss
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P17
R16
R17
R18
R19
T13
T14
T15
T20
T21
T22
U14
U15
U20
U21
U22
V14
V15
V20
V21
V22
W14
W15
W20
W21
W22
Y18
Y19
AA16
AA17
AA18
AA19
AB16
AB17
AB18
AB19
C3
C13
AP2
AP18
AP33
AP34
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
140
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 69. 680-Pin PBGAM Pinout
VDDIO VREF
Additional
Pair
BM680
I/O
OR4E02
OR4E04
OR4E06
Bank Group
Function
AA13
AA14
AA15
AA20
AA21
AA22
AB3
Y14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
VDDIO4
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
VDDIO4
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
VDDIO4
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
VDDIO4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U16
U17
U18
U19
V1
R14
R15
R20
N14
N15
N20
N21
N22
AM33 4 (BR)
Lattice Semiconductor
141
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Package Thermal Characteristics
Summary
There are three thermal parameters that are in common use: ΘJA, ψJC, and ΘJC. It should be noted that all the
parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials,
the amount of copper in the test board or system board, and system airflow.
Θ
JA
This is the thermal resistance from junction to ambient (theta-JA, R-theta, etc.):
TJ – TA
-------------------
Q
ΘJA =
where TJ is the junction temperature, TA, is the ambient air temperature, and Q is the chip power.
Experimentally, ΘJA is determined when a special thermal test die is assembled into the package of interest, and
the part is mounted on the thermal test board. The diodes on the test chip are separately calibrated in an oven. The
package/board is placed either in a JEDEC natural convection box or in the wind tunnel, the latter for forced con-
vection measurements. A controlled amount of power (Q) is dissipated in the test chip’s heater resistor, the chip’s
temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note
that ΘJA is expressed in units of °C/watt.
ψ
JC
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally
used to infer the junction temperature while the device is operating in the system. It is not considered a true ther-
mal resistance, and it is defined by:
TJ – TC
ψ
-------------------
Q
JC =
where TC is the case temperature at top dead center, TJ is the junction temperature, and Q is the chip power. Dur-
ing the ΘJA measurements described above, besides the other parameters measured, an additional temperature
ψ
reading, TC, is made with a thermocouple attached at top-dead-center of the case. JC is also expressed in units of
°C/W.
142
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Θ
JC
This is the thermal resistance from junction to case. It is most often used when attaching a heat sink to the top of
the package. It is defined by:
TJ – TC
-------------------
ΘJC =
Q
The parameters in this equation have been defined above. However, the measurements are performed with the
case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the
ψ
top of the package. It is this difference in the measurement process that differentiates ΘJC from JC. ΘJC is a true
thermal resistance and is expressed in units of °C/W.
Θ
JB
This is the thermal resistance from junction to board (ΘJL). It is defined by:
TJ – TB
-------------------
Q
ΘJB =
where TB is the temperature of the board adjacent to a lead measured with a thermocouple. The other parameters
on the right-hand side have been defined above. This is considered a true thermal resistance, and the measure-
ment is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads.
Note that ΘJB is expressed in units of °C/W, and that this parameter and the way it is measured are still in JEDEC
committee.
Lattice Semiconductor
143
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Package Thermal Characteristics
Table 70. ORCA Series 4 Plastic Package Thermal Guidelines
Θ
Package
JA (°C/W)
Max Power
0 fpm
200 fpm
500 fpm
T = 70 °C Max
TJ = 125 °C Max
0 fpm (W)
352-Pin PBGA
416-pin PBGAM
680-Pin PBGAM
19.0
18.0
13.4
16.0
16.5
11.5
15.0
13.5
10.5
2.9
3.1
4.1
Note: The 416-pin PBGAM and the 680-pin PBGAM packages include 2 oz. copper plates
Package Coplanarity
The coplanarity limits of packages are as follows:
■ PBGA: 8.0 mils
■ PBGAM: 8.0 mils
Heat Sink Vendors for BGA Packages
In some cases the power required by the customers application is greater than the package can dissipate. Below,
in alphabetical order, is a list of heat sink vendors who advertise heat sinks aimed at the BGA market.
Table 71. Heat Sink Vendors
Vendor
Location
Phone
Aavid Thermalloy
Concord, NH
Harrisburg, PA
Burbank, CA
Buffalo, NY
(603) 224-9988
(800) 468-2023
(818) 842-7277
(800) 388-5428
(310) 783-5400
(603) 635-2800
Chip Coolers (Tyco Electronics)
IERC (CTS Corp.)
R-Theta
Sanyo Denki
Torrance, CA
Pelham, NH
Wakefield Thermal Solutions
144
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Package Parasitics
The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the
package parasitics. Table 72 lists eight parasitics associated with the ORCA packages. These parasitics represent
the contributions of all components of a package, which include the bond wires, all internal package routing, and
the external leads.
Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual induc-
tance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and
inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest
neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be
grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect of
the lead. Resistance values are in mΩ.
The parasitic values in Table 72 are for the circuit model of bond wire and package lead parasitics. If the mutual
capacitance value is not used in the designer’s model, then the value listed as mutual capacitance should be added
to each of the C1 and C2 capacitors.
Table 72. ORCA Series 4 Package Parasitics
Package Type
LSW
LMW
RW
C1
C2
CM
LSL
LML
352-Pin PBGA
416-Pin PBGAM
680-Pin PBGAM
5.00
3.52
3.80
2.00
0.80
1.30
220
235
250
1.50
0.40
0.50
1.50
1.00
1.00
1.50
0.25
0.30
7—12
1.5—5.0
2.8—5
3—6
0.5—1.3
0.5—1.5
CIRCUIT
LSW
LSL
BOARD PAD
C2
RW
PAD N
C1
LMW
LSW
LML
LSL
CM
PAD N + 1
RW
C1
C2
5-3862(C)r2
Figure 60. Package Parasitics
Lattice Semiconductor
145
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Package Outline Diagrams
Terms and Definitions
Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by
the application of the allowance and the tolerance.
Design Size: The design size of a dimension is the actual size of the design, including an allowance for fit and tol-
erance.
Typical (TYP): When specified after a dimension, this indicates the repeated design size if a tolerance is specified
or repeated basic size if a tolerance is not specified.
Reference (REF): The reference dimension is an untoleranced dimension used for informational purposes only. It
is a repeated dimension or one that can be derived from other values in the drawing.
Minimum (MIN) or Maximum (MAX): Indicates the minimum or maximum allowable size of a dimension.
2725(f)
146
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Package Outline Diagrams
352-Pin PBGA
Dimensions are in millimeters.
35.00 ± 0.20
+0.70
30.00
–0.00
A1 BALL
IDENTIFIER ZONE
+0.70
–0.00
30.00
35.00
± 0.20
MOLD
COMPOUND
PWB
1.17 ± 0.05
0.56 ± 0.06
2.33 ± 0.21
SEATING PLANE
0.20
SOLDER BALL
25 SPACES @ 1.27 = 31.75
0.60 ± 0.10
AF
AE
AD
AC
AB
AA
Y
W
0.75 ± 0.15
V
U
T
R
P
N
25 SPACES
@ 1.27 = 31.75
M
L
K
J
H
G
F
E
D
C
B
A
CENTER ARRAY
FOR THERMAL
ENHANCEMENT
(OPTIONAL)
(SEE NOTE BELOW)
1 2 3
4
5 6
7
8 9 10 12 14 16 18 20 22 24 26
11 13 15 17 19 21 23 25
A1 BALL
CORNER
5-4407(F)
Note: Although the 36 thermal enhancement balls are stated as an option, they are standard on the 352 FPGA package.
Lattice Semiconductor
147
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Package Outline Diagrams (continued)
416-Pin PBGAM
Dimensions are in millimeters.
27.00
24.00
PIN A1
CORNER
24.00
27.00
1.17 ± 0.05
0.61 ± 0.08
0.50 ± 0.10
2.28 ± 0.10
SEATING PLANE
0.20
SOLDER BALL
25 SPACES @ 1.00 = 25.00
CORNER
A1 BALL
25 23 21 19 17 15 13 11
26 24 22 20 18 16 14 12 10 9 8
7
6 5 4 3 2 1
A
B
C
D
E
0.63 ± 0.15
F
G
H
J
K
L
M
N
P
R
25 SPACES
@ 1.00 = 25.00
T
U
V
W
Y
AA
CENTER ARRAY
FOR THERMAL
ENHANCEMENT
AB
AC
AD
AE
AF
1139(F)
5-4409(F)
148
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Package Outline Drawings (continued)
680-Pin PBGAM
Dimensions are in millimeters.
35.00
+ 0.70
– 0.00
30.00
A1 BALL
IDENTIFIER ZONE
35.00
+ 0.70
– 0.00
30.00
1.170
0.61 ± 0.08
SEATING PLANE
0.20
SOLDER BALL
33 SPACES @ 1.00 = 33.00
2.51 MAX
0.50 ± 0.10
AP
AM
AK
AH
AF
AD
AB
Y
AN
AL
AJ
AG
AE
AC
AA
W
U
0.64 ± 0.15
33 SPACES
@ 1.00 = 33.00
V
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29 31 33
10 12 14 16 18 20 22 24 26 28 30 32 34
A1 BALL
CORNER
2
4
6
8
5-4406(F)
Lattice Semiconductor
149
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Ordering Information
OR4EXX X XX XXX X
Device Family
Grade
C = Commercial
OR4E02
OR4E04
OR4E06
I = Industrial
Ball Count
Speed Grade
Package Type
BA = Plastic Ball Grid Array (PBGA)
BM = Fine-Pitch Plastic Ball Grid Array (PBGAM)
Table 73. Device Type Options
Device
Voltage
1.5 V internal
3.3 V/2.5 V/1.8 V/1.5 V I/O
OR4Exx
Table 74. Recommended Temperature Range
Symbol Description
Ambient Temperature
Junction Temperature
C
I
Commercial
Industrial
0 ˚C to +70 ˚C
0 ˚C to +85 ˚C
–40 ˚C to +85 ˚C
–40 ˚C to +100 ˚C
150
Lattice Semiconductor
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 75. Commercial Ordering Information
Speed
Grade
Package
Type
Ball
Count
Device Family
Part Number
Grade
OR4E02
OR4E02-3BA352C
OR4E02-3BM416C
OR4E02-3BM680C
OR4E02-2BA352C
OR4E02-2BM416C
OR4E02-2BM680C
OR4E02-1BA352C
OR4E02-1BM416C
OR4E02-1BM680C
OR4E04-3BA352C
OR4E04-3BM416C
OR4E04-3BM680C
OR4E04-2BA352C
OR4E04-2BM416C
OR4E04-2BM680C
OR4E04-1BA352C
OR4E04-1BM416C
OR4E04-1BM680C
OR4E06-2BA352C
OR4E06-2BM680C
OR4E06-1BA352C
OR4E06-1BM680C
3
3
3
2
2
2
1
1
1
3
3
3
2
2
2
1
1
1
2
2
1
1
PBGA
PBGAM
PBGAM
PBGA
352
416
680
352
416
680
352
416
680
352
416
680
352
416
680
352
416
680
352
680
352
680
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
PBGAM
PBGAM
PBGA
PBGAM
PBGAM
PBGA
OR4E04
PBGAM
PBGAM
PBGA
PBGAM
PBGAM
PBGA
PBGAM
PBGAM
PBGA
OR4E06
PBGAM
PBGA
PBGAM
Note: For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed
grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster than the associ-
ated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only.
Lattice Semiconductor
151
Data Sheet
May, 2006
ORCA Series 4 FPGAs
Table 76. Industrial Ordering Information
Speed
Grade
Package
Type
Ball
Count
Device Family
Part Number
OR4E02-2BA352I
Grade
OR4E02
2
2
2
1
1
1
2
2
2
1
1
1
1
1
PBGA
PBGAM
PBGAM
PBGA
352
416
680
352
416
680
352
416
680
352
416
680
352
680
I
I
I
I
I
I
I
I
I
I
I
I
I
I
OR4E02-2BM416I
OR4E02-2BM680I
OR4E02-1BA352I
OR4E02-1BM416I
OR4E02-1BM680I
OR4E04-2BA352I
OR4E04-2BM416I
OR4E04-2BM680I
OR4E04-1BA352I
OR4E04-1BM416I
OR4E04-1BM680I
OR4E06-1BA352I
OR4E06-1BM680I
PBGAM
PBGAM
PBGA
OR4E04
PBGAM
PBGAM
PBGA
PBGAM
PBGAM
PBGA
OR4E06
PBGAM
Note: For all but the slowest commercial speed grade, the speed grades on these devices are dual marked. For example, the commercial speed
grade -2XXXXXC is also marked with the industrial grade -1XXXXXI. The commercial grade is always one speed grade faster than the associ-
ated dual mark industrial grade. The slowest commercial speed grade is marked as commercial grade only.
152
Lattice Semiconductor
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OR4E02-2BMN416C
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OR4E02-2BMN680C
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OR4E021BA352-DB
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