PALCE16V8Q-15JC/4 [LATTICE]
EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic; EE CMOS零功耗的20引脚通用可编程阵列逻辑
| 型号： | PALCE16V8Q-15JC/4 |
| 厂家： | 
LATTICE SEMICONDUCTOR |
| 描述： | EE CMOS Zero-Power 20-Pin Universal Programmable Array Logic |
| 文件： | 总32页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PALCE16V8
COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
IND:-12/15/25
PALCE16V8Z COM’L:-25
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
®
Pin and function compatible w ith all 20-pin PAL devices
Electrically erasable CMOS technology provides reconfigurable logic and full testability
High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for the PAL16R8 series
Outputs programmable as registered or combinatorial in any combination
Peripheral Component Interconnect (PCI) compliant
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on pow er up
Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
Extensive third-party softw are and programmer support
Fully tested for 100% programming and functional yields and high reliability
5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
Publication# 1 6493
Amendment/0
Rev: F
Issue Date: September 2000
BLOCK DIAGRAM
I – I
CLK/I
1
8
0
8
Programmable AND Array
32 x 64
MACRO
MC0
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MACRO
MC1
MC2
MC3
MC4
MC5
MC6
MC7
OE/I
9
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
16493E-1
FUNCTIONAL DESCRIPTION
The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the
PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z
has zero standby power and an unused product term disable feature for reduced power
consumption. It has eight independently configurable macrocells (MC0-MC7). Each macrocell can
be configured as registered output, combinatorial output, combinatorial I/O or dedicated input.
The programming matrix implements a programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complementary outputs to provide user-
programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK)
and output enable (OE), respectively, for all flip-flops.
Unused input pins should be tied directly to VCC or GND. Product terms with all bits
unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true
and complement of any input signal connected assume a logical LOW state.
The programmable functions on the PALCE16V8 are automatically configured from the user’s
design specification. The design specification is processed by development software to verify
the design and create a programming file (JEDEC). This file, once downloaded to a programmer,
configures the device according to the user’s desired function.
The user is given two design options with the PALCE16V8. First, it can be programmed as a
standard PAL device from the PAL16R8 series. The PAL programmer manufacturer will supply
device codes for the standard PAL device architectures to be used with the PALCE16V8.
The programmer will program the PALCE16V8 in the corresponding architecture. This allows
the user to use existing standard PAL device JEDEC files without making any changes to them.
2
PALCE16V8 and PALCE16V8Z Families
Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the
PALCE16V8 device code. This option allows full utilization of the macrocell.
To
Adjacent
Macrocell
1 1
OE
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL0
X
SG1
1 1
0 X
I/O
X
D
Q
Q
1 0
SL1
X
CLK
1 0
1 1
0 X
From
Adjacent
Pin
*SG1
SL0
X
*In macrocells MC and MC , SG1 is replaced by SG0 on the feedback multiplexer.
0
7
16493E-2
Figure 1. PALCE16V8 Macrocell
CONFIGURATION OPTIONS
Each macrocell can be configured as one of the following: registered output, combinatorial
output, combinatorial I/O, or dedicated input. In the registered output configuration, the output
buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled
by a product term or always enabled. In the dedicated input configuration, it is always disabled.
With the exception of MC and MC , a macrocell configured as a dedicated input derives the
0
7
input signal from an adjacent I/O. MC derives its input from pin 11 (OE) and MC from pin 1
0
7
(CLK).
The macrocell configurations are controlled by the configuration control word. It contains 2
global bits (SG0 and SG1) and 16 local bits (SL0 through SL0 and SL1 through SL1 ). SG0
0
7
0
7
determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will
emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0 , in
x
conjunction with SG1, selects the configuration of the macrocell, and SL1 sets the output as
x
either active low or active high for the individual macrocell.
The configuration bits work by acting as control inputs for the multiplexers in the macrocell.
There are four multiplexers: a product term input, an enable select, an output select, and a
feedback select multiplexer. SG1 and SL0 are the control signals for all four multiplexers. In
x
MC and MC , SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being
0
7
the adjacent pin for MC and OE the adjacent pin for MC .
7
0
PALCE16V8 and PALCE16V8Z Families
3
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0 = 0. There is only one registered
x
configuration. All eight product terms are available as inputs to the OR gate. Data polarity is
determined by SL1 The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback
x.
path is from Q on the register. The output buffer is enabled by OE.
Combinatorial Configurations
The PALCE16V8 has three combinatorial output configurations: dedicated output in a non-
registered device, I/O in a non-registered device and I/O in a registered device.
Dedicated Output in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0 = 0. All eight product terms are available
x
to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the
exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK
and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin
1 will use the feedback path of MC , and pin 11 will use the feedback path of MC .
7
0
Combinatorial I/O in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 1, and SL0 = 1. Only seven product terms are
x
available to the OR gate. The eighth product term is used to enable the output buffer. The signal
at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to
be used as an input.
Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as
inputs. Pin 1 will use the feedback path of MC , and pin 11 will use the feedback path of MC .
7
0
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0 = 1. Only seven product terms are available
x
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Dedicated Input Configuration
The control bit settings are SG0 = 1, SG1 = 0 and SL0 = 1. The output buffer is disabled. Except
x
for MC and MC , the feedback signal is an adjacent I/O. For MC and MC , the feedback signals
0
7
0
7
are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2.
Table 1. Macrocell Configuration
Cell
Devices
Cell
Devices
SG0
SG1
SL0
Configuration
Emulated
SG0
SG1
SL0
Configuration
Emulated
X
X
Device Uses Registers
Device Uses No Registers
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
PAL16R8, 16R6,
16R4
Combinatorial
0
0
1
1
0
1
Registered Output
1
0
0
Output
PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
Combinatorial
I/O
PAL16R6, 16R4
1
1
0
1
1
1
Input
Combinatorial
I/O
PAL16L8
4
PALCE16V8 and PALCE16V8Z Families
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal
needs or to reduce product terms. Programmable polarity allows Boolean expressions to be
written in their most compact form (true or inverted), and the output can still be of the desired
polarity. It can also save “DeMorganizing” efforts.
Selection is through a programmable bit SL1 which controls an exclusive-OR gate at the output
x
of the AND/OR logic. The output is active high if SL1 is 1 and active low if SL1 is 0.
x
x
PALCE16V8 and PALCE16V8Z Families
5
OE
OE
D
Q
Q
D
Q
Q
CLK
CLK
a. Registered active low
b. Registered active high
c. Combinatorial I/O active low
d. Combinatorial I/O active high
V
V
CC
CC
Note 1
Note 1
e. Combinatorial output active low
f. Combinatorial output active high
Notes:
1. Feedback is not available on pins 15 and 16 in the
combinatorial output mode.
Adjacent I/O pin
Note 2
2. This configuration is not available on pins 15 and 16.
g. Dedicated input
16493E-2
Figure 2. Macrocell Configurations
6
PALCE16V8 and PALCE16V8Z Families
Pow er-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
PALCE16V8 will depend on whether they are selected as registered or combinatorial. If registered
is selected, the output will be HIGH. If combinatorial is selected, the output will be a function
of the logic.
Register Preload
The register on the PALCE16V8 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
making it unnecessary to cycle through long test vector sequences to reach a desired state. In
addition, transitions from illegal states can be verified by loading illegal states and observing
proper recovery.
Security Bit
A security bit is provided on the PALCE16V8 as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback and verification of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
The bit can only be erased in conjunction with the array during an erase cycle.
Electronic Signature Word
An electronic signature word is provided in the PALCE16V8 device. It consists of 64 bits of
programmable memory that can contain user-defined data. The signature data is always available
to the user independent of the security bit.
Programming and Erasing
The PALCE16V8 can be programmed on standard logic programmers. It also may be erased to
reset a previously configured device back to its unprogrammed state. Erasure is automatically
performed by the programming hardware. No special erase operation is required.
Quality and Testability
The PALCE16V8 offers a very high level of built-in quality. The erasability of the device provides
a direct means of verifying performance of all AC and DC parameters. In addition, this verifies
complete programmability and functionality of the device to provide the highest programming
yields and post-programming functional yields in the industry.
Technology
The high-speed PALCE16V8 is fabricated with Vantis’ advanced electrically-erasable (EE) CMOS
process. The array connections are formed with proven EE cells. Inputs and outputs are
designed to be compatible with TTL devices. This technology provides strong input clamp
diodes, output slew-rate control, and a grounded substrate for clean switching.
PCI Compliance
PALCE16V8 devices in the -5/-7/-10 speed grades are fully compliant with the PCI Local Bus
Specification published by the PCI Special Interest Group. The PALCE16V8’s predictable timing
ensures compliance with the PCI AC specifications independent of the design.
Zero-Standby Pow er Mode
The PALCE16V8Z features a zero-standby power mode. When none of the inputs switch for an
extended period (typically 50 ns), the PALCE16V8Z will go into standby mode, shutting down
PALCE16V8 and PALCE16V8Z Families
7
most of its internal circuitry. The current will go to almost zero (I < 15 µA). The outputs will
CC
maintain the states held before the device went into the standby mode. There is no speed
penalty associated with coming out of standby mode.
When any input switches, the internal circuitry is fully enabled, and power consumption returns
to normal. This feature results in considerable power savings for operation at low to medium
frequencies. This saving is illustrated in the I vs. frequency graph.
CC
Product-Term Disable
On a programmed PALCE16V8Z, any product terms that are not used are disabled. Power is cut
off from the product terms so that they do not draw current. As shown in the I vs. frequency
CC
graph, product-term disabling results in considerable power savings. This saving is greater at the
higher frequencies.
Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zero-Power PLDs.
8
PALCE16V8 and PALCE16V8Z Families
LOGIC DIAGRAM
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
CLK/I
1
2
3
4
0
20
19
1 1
1 0
0 0
0 1
V
CC
1 1
V
CC
0 X
1 0
SL07
0
7
SG1
1 1
0 X
I/O
7
D
Q
Q
1 0
SL17
1 0
1 1
0 X
I
1
SG0
SL07
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL06
8
SG1
1 1
0 X
18 I/O
6
D
Q
1 0
Q
15
SL16
1 0
1 1
0 X
I
2
SG1
SL06
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL05
16
23
SG1
1 1
0 X
17 I/O
5
D
Q
Q
1 0
SL15
1 0
1 1
0 X
I
3
SG1
SL05
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL04
24
31
SG1
1 1
0 X
16
I/O
4
D
Q
Q
1 0
SL14
1 0
1 1
0 X
5
I
4
SG1
SL04
CLK OE
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
16493E-2
PALCE16V8 and PALCE16V8Z Families
9
LOGIC DIAGRAM (CONTINUED)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
CLK OE
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL03
32
39
SG1
1 1
0 X
15
14
13
I/O
3
D
Q
Q
1 0
SL13
1 0
1 1
0 X
6
7
8
I
5
SG1
SL03
SL02
SL01
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL02
40
47
SG1
1 1
0 X
I/O
2
D
Q
Q
1 0
SL12
1 0
1 1
0 X
I
6
SG1
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL01
48
55
SG1
1 1
0 X
I/O
1
D
Q
Q
1 0
SL11
1 0
1 1
0 X
I
7
SG1
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL00
56
63
SG1
1 1
0 X
12 I/O
0
D
Q
Q
1 0
SL10
1 0
1 1
0 X
9
I
8
SL00
SG0
11
OE/I
9
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
GND 10
16493E-6
(concluded)
10
PALCE16V8 and PALCE16V8Z Families
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (T )
A
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage
with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V
Supply Voltage (V
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
)
CC
DC Input Voltage . . . . . . . . . . . -0.5 V to V
+ 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
CC
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . .-0.5 V to V + 0.5 V
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T = 0°C to 75°C) . . . . . . . . . 100 mA
A
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Description
= -3.2 mA, V = V or V , V = Min
Min
Max
Unit
V
V
I
2.4
OH
OH
IN
IH
IL CC
V
Output LOW Voltage
Input HIGH Voltage
I
= 24 mA, V = V or V , V = Min
0.5
V
OL
OL
IN
IH
IL CC
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
V
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
V
Input LOW Voltage
0.8
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V = 5.25 V, V = Max (Note 2)
10
µA
µA
IH
IN
CC
I
V = 0 V, V = Max (Note 2)
–100
IL
IN
CC
V
= 5.25 V, V = Max
CC
OUT
I
Off-State Output Leakage Current HIGH
10
µA
OZH
V = V or V (Note 2)
IN
IH
IL
V
= 0 V, V = Max
CC
OUT
I
Off-State Output Leakage Current LOW
Output Short-Circuit Current
Supply Current for -5
–100
–150
125
µA
mA
mA
OZL
V = V or V (Note 2)
IN
IH
IL
I
V
= 0.5 V, V = Max (Note 3)
–30
SC
OUT
CC
Outputs Open (I = 0 mA), V = 0 V
OUT
IN
I (Static)
CC
V = Max
CC
Outputs Open (I = 0 mA),
OUT
I (Dynamic) Supply Current for -7
115
mA
CC
V = Max, f = 25 MHz
CC
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
V
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
OUT
PALCE16V8H-5/7 (Com’l)
11
CAPACITANCE1
Parameter
Symbol
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
Typ
5
Unit
pF
C
V = 2.0 V
IN
V = 5.0 V, T = 25 °C,
CC A
IN
C
V
= 2.0 V
f = 1 MHz
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES1
-5
-7
Parameter
Symbol
2
2
Parameter Description
Input or Feedback to Combinatorial Output
Min
1
Max
Min
3
Max
Unit
ns
t
5
7.5
PD
t
Setup Time from Input or Feedback to Clock
Hold Time
3
5
ns
S
t
0
0
ns
H
t
Clock to Output
1
4
1
1
5
1
ns
CO
t
Skew Between Registered Outputs (Note 3)
ns
SKEWR
t
LOW
Clock Width
3
3
4
4
ns
WL
t
HIGH
ns
WH
External Feedback
1/(t +t )
142.8
166
166
1
100
125
125
1
MHz
MHz
MHz
ns
S
CO
Maximum Frequency
(Note 4)
f
Internal Feedback (f
)
1/(t +t ) (Note 5)
S CF
MAX
CNT
No Feedback
1/(t +t )
WH WL
t
OE to Output Enable
OE to Output Disable
6
5
6
5
6
6
9
9
PZX
t
1
1
ns
PXZ
t
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
2
3
ns
EA
t
2
3
ns
ER
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for t , t , t , t , t , and t are defined under best case conditions. Future process improvements
PD CO PZX PXZ EA
ER
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
5. t is a calculated value and is not guaranteed. t can be found using the following equation:
CF
CF
t
= 1/f
(internal feedback) – t .
CF
MAX S
12
PALCE16V8H-5/7 (Com’l)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (T )
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
A
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
Supply Voltage (V
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
)
CC
DC Input Voltage . . . . . . . . . . . -0.5 V to V + 0.5 V
CC
Industrial (I) Devices
DC Output or I/O
Temperature (T ) Operating
A
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to V + 0.5 V
CC
in Free Air. . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Supply Voltage (V
)
CC
Latchup Current (T = -40°C to +85°C). . . . . . . 100 mA
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
A
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING
RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Description
= –3.2 mA, V = V or V , V = Min
Min
Max
Unit
V
V
I
2.4
OH
OH
IN
IH
IL CC
V
Output LOW Voltage
Input HIGH Voltage
I
= 24 mA, V = V or V , V = Min
0.5
V
OL
OL
IN
IH
IL CC
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
V
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
V
Input LOW Voltage
0.8
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V = 5.25 V, V = Max (Note 2)
10
µA
µA
IH
IN
CC
I
V = 0 V, V = Max (Note 2)
–100
IL
IN
CC
V
= 5.25 V, V = Max
CC
OUT
I
Off-State Output Leakage Current HIGH
Off-State Output Leakage Current LOW
10
µA
µA
OZH
V = V or V (Note 2)
IN
IH
IL
V
= 0 V, V = Max
CC
OUT
I
–100
OZL
V = V or V (Note 2)
IN
IH
IL
I
Output Short-Circuit Current
Commercial Supply Current
Industrial Supply Current
V
= 0.5 V, V = Max (Note 3)
–30
–150
115
mA
mA
mA
SC
OUT
CC
Outputs Open (I = 0 mA)
OUT
I (Dynamic)
CC
V = Max, f = 15 MHz
CC
130
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
V
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
OUT
PALCE16V8H-10 (Com’l, Ind)
13
CAPACITANCE1
Parameter
Symbol
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
Typ
5
Unit
pF
C
V = 2.0 V
IN
V = 5.0 V, T = 25 °C,
CC A
IN
C
V
= 2.0 V
f = 1 MHz
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES1
-10
Parameter
Symbol
2
Parameter Description
Input or Feedback to Combinatorial Output
Min
3
Max
Unit
ns
t
10
PD
t
Setup Time from Input or Feedback to Clock
Hold Time
7.5
0
ns
S
t
ns
H
t
Clock to Output
3
7.5
ns
CO
t
LOW
Clock Width
6
ns
WL
t
HIGH
6
ns
WH
External Feedback
1/(t +t )
66.7
71.4
83.3
2
MHz
MHz
MHz
ns
S
CO
Maximum Frequency
(Note 3)
f
Internal Feedback (f
)
1/(t +t ) (Note 4)
S CF
MAX
CNT
No Feedback
1/(t +t )
WH WL
t
OE to Output Enable
OE to Output Disable
10
10
10
10
PZX
t
2
ns
PXZ
t
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
3
ns
EA
t
3
ns
ER
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for t , t , t , t , t , and t are defined under best case conditions. Future process improvements
PD CO PZX PXZ EA
ER
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. t is a calculated value and is not guaranteed. t can be found using the following equation:
CF
CF
t
= 1/f
(internal feedback) – t .
CF
MAX S
14
PALCE16V8H-10 (Com’l, Ind)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (T )
A
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage
with Respect to Ground . . . . . . . . . . -0.5 V to +7.0 V
Supply Voltage (V
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
)
CC
DC Input Voltage . . . . . . . . . . . -0.5 V to V
+ 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
CC
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . .-0.5 V to V + 0.5 V
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T = 0°C to 75°C) . . . . . . . . . 100 mA
A
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Description
= -3.2 mA, V = V or V , V = Min
Min
Max
Unit
V
V
I
2.4
OH
OH
IN
IH
IL CC
V
Output LOW Voltage
Input HIGH Voltage
I
= 24 mA, V = V or V , V = Min
0.5
V
OL
OL
IN
IH
IL CC
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
V
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
V
Input LOW Voltage
0.8
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V = 5.25 V, V = Max (Note 2)
10
µA
µA
IH
IN
CC
I
V = 0 V, V = Max (Note 2)
–100
IL
IN
CC
V
= 5.25 V, V = Max
CC
OUT
I
Off-State Output Leakage Current HIGH
10
µA
OZH
V = V or V (Note 2)
IN
IH
IL
V
= 0 V, V = Max
CC
OUT
I
Off-State Output Leakage Current LOW
Output Short-Circuit Current
Supply Current (Dynamic)
–100
–150
55
µA
mA
mA
OZL
V = V or V (Note 2)
IN
IH
IL
I
V
= 0.5 V, V = Max (Note 3)
–30
SC
OUT
CC
Outputs Open (I = 0 mA),
OUT
I
CC
V = Max, f = 15 MHz
CC
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
V
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
OUT
PALCE16V8Q-10 (Com’l)
15
CAPACITANCE1
Parameter
Symbol
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
Typ
5
Unit
pF
C
V = 2.0 V
IN
V = 5.0 V, T = 25 °C,
CC A
IN
C
V
= 2.0 V
f = 1 MHz
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES1
-10
Parameter
Symbol
2
Parameter Description
Input or Feedback to Combinatorial Output
Min
3
Max
Unit
ns
t
10
PD
t
Setup Time from Input or Feedback to Clock
Hold Time
7.5
0
ns
S
t
ns
H
t
Clock to Output
3
7.5
ns
CO
t
LOW
Clock Width
6
ns
WL
t
HIGH
6
ns
WH
External Feedback
1/(t +t )
66.7
71.4
83.3
2
MHz
MHz
MHz
ns
S
CO
Maximum Frequency
(Note 3)
f
Internal Feedback (f
)
1/(t +t ) (Note 4)
S CF
MAX
CNT
No Feedback
1/(t +t )
WH WL
t
OE to Output Enable
OE to Output Disable
10
10
10
10
PZX
t
2
ns
PXZ
t
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
3
ns
EA
t
3
ns
ER
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for t , t , t , t , t , and t are defined under best case conditions. Future process improvements
PD CO PZX PXZ EA
ER
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. t is a calculated value and is not guaranteed. t can be found using the following equation:
CF
CF
t
= 1/f
(internal feedback) – t .
CF
MAX S
16
PALCE16V8Q-10 (Com’l)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (T )
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
A
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
Supply Voltage (V
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
)
CC
DC Input Voltage . . . . . . . . . . . -0.5 V to V + 0.5 V
CC
Industrial (I) Devices
DC Output or I/O
Temperature (T ) Operating
A
Pin Voltage . . . . . . . . . . . . . . . . . -0.5 V to V + 0.5 V
CC
in Free Air. . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Supply Voltage (V
)
CC
Latchup Current (T = -40°C to +85°C). . . . . . . 100 mA
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
A
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING
RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Description
= –3.2 mA, V = V or V , V = Min
Min
Max
Unit
V
V
I
2.4
OH
OH
IN
IH
IL CC
V
Output LOW Voltage
Input HIGH Voltage
I
= 24 mA, V = V or V , V = Min
0.5
V
OL
OL
IN
IH
IL CC
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
V
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
V
Input LOW Voltage
0.8
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V = 5.25 V, V = Max (Note 2)
10
µA
µA
IH
IN
CC
I
V = 0 V, V = Max (Note 2)
–100
IL
IN
CC
V
= 5.25 V, V = Max
CC
OUT
I
Off-State Output Leakage Current HIGH
10
µA
OZH
V = V or V (Note 2)
IN
IH
IL
V
= 0 V, V = Max
CC
OUT
I
Off-State Output Leakage Current LOW
Output Short-Circuit Current
–100
µA
OZL
V = V or V (Note 2)
IN
IH
IL
I
V
= 0.5 V, V = Max (Note 3)
–30
–150
90
mA
SC
OUT
CC
H
Q
H
Q
Commercial Supply Current
Industrial Supply Current
mA
mA
55
Outputs Open (I = 0 mA)
OUT
I (Dynamic)
CC
V = Max, f = 15 MHz
CC
130
65
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of I and I (or I and I ).
IL
OZL
IH
OZH
3. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
V
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
OUT
PALCE16V8H-15/25 (Com’l, Ind), Q-15/25 (Com’l), Q-20/25 (Ind)
17
CAPACITANCE1
Parameter
Symbol
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
Typ
5
Unit
pF
C
V = 2.0 V
IN
V = 5.0 V, T = 25 °C,
CC A
IN
C
V
= 2.0 V
f = 1 MHz
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES1
-15
-20
-25
Parameter
Symbol
Parameter Description
Input or Feedback to Combinatorial Output
Setup Time from Input or Feedback to Clock
Hold Time
Min
Max
Min
Max
Min
Max
Unit
ns
t
15
20
25
PD
t
12
0
13
0
15
0
ns
S
t
ns
H
t
Clock to Output
10
11
12
ns
CO
t
LOW
Clock Width
8
8
10
10
12
12
37
ns
WL
t
HIGH
ns
WH
External Feedback
1/(t +t )
45.5
41.6
MHz
S
CO
Maximum
Internal Feedback
Frequency
1/(t +t )
S CF
(Note 3)
f
50
45.4
50.0
40
MHz
MAX
(f
)
CNT
(Note 2)
No Feedback
1/(t +t )
62.5
41.6
MHz
ns
WH WL
t
OE to Output Enable
15
15
15
15
18
18
18
18
20
20
20
20
PZX
t
OE to Output Disable
ns
PXZ
t
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
ns
EA
t
ns
ER
Notes:
1. See “Switching Test Circuit” for test conditions.
2. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
3. t is a calculated value and is not guaranteed. t can be found using the following equation:
CF
CF
t
= 1/f
(internal feedback) – t .
CF
MAX S
18
PALCE16V8H-15/25 (Com’l, Ind), Q-15/25 (Com’l), Q-20/25 (Ind)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Industrial (I) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (T )
Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C
A
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
Supply Voltage (V
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
)
CC
DC Input Voltage . . . . . . . . . . . -0.5 V to V + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
CC
DC Output or I/O Pin Voltage . . . -0.5 V to V + 0.5 V
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T = -40°C to +85°C). . . . . . . 100 mA
A
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Description
Min
Max
Unit
V
I
= 6 mA
= 20 µA
= 24 mA
= 6 mA
= 20 µA
3.84
OH
V
V = V or V , V = Min
IN IH IL CC
OH
I
V – 0.1 V
V
OH
CC
I
0.5
0.33
0.1
V
OL
V
Output LOW Voltage
V = V or V , V = Min
I
OL
V
OL
IN
IH
IL CC
I
V
OL
Guaranteed Input Logical HIGH
Voltage for all Inputs (Notes 1 and 2)
V
Input HIGH Voltage
Input LOW Voltage
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1 and 2)
V
0.9
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V = 5.25 V, V = Max (Note 3)
10
µA
µA
IH
IN
CC
I
V = 0 V, V = Max (Note 3)
–10
IL
IN
CC
V
= 5.25 V, V = Max
CC
OUT
I
Off-State Output Leakage Current HIGH
Off-State Output Leakage Current LOW
10
µA
µA
OZH
V = V or V (Note 3)
IN
IH
IL
V
= 0 V, V = Max
CC
OUT
I
–10
OZL
V = V or V (Note 3)
IN
IH
IL
I
Output Short-Circuit Current
Supply Current (Static)
V
= 0.5 V, V = Max (Note 4)
–30
–150
30
mA
µA
SC
OUT
CC
f = 0 MHz
Outputs Open (I = 0 mA)
OUT
I
CC
V = Max
Supply Current (Dynamic)
f = 15 MHz
75
mA
CC
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. I/O pin leakage is the worst case of I and I
(or I and I
).
IL
OZL
IH
OZH
4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
V
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
OUT
PALCE16V8Z-12 (Ind)
19
CAPACITANCE1
Parameter
Symbol
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
Typ
5
Unit
pF
C
V = 2.0 V
IN
V = 5.0 V, T = 25 °C,
CC A
IN
C
V
= 2.0 V
f = 1 MHz
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES1
-12
Parameter
Symbol
Parameter Description
Input or Feedback to Combinatorial Output (Note 2)
Min
Max
Unit
ns
t
12
PD
t
Setup Time from Input or Feedback to Clock
Hold Time
8
0
ns
S
t
ns
H
t
Clock to Output
8
ns
CO
t
LOW
Clock Width
5
5
ns
WL
t
HIGH
ns
WH
External Feedback
1/(t +t )
62.5
77
MHz
MHz
MHz
ns
S
CO
Maximum Frequency
(Notes 3 and 4)
f
Internal Feedback (f
)
1/(t +t )
S CF
MAX
CNT
No Feedback
1/(t +t )
100
WH WL
t
OE to Output Enable
OE to Output Disable
8
8
PZX
t
ns
PXZ
t
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
13
13
ns
EA
t
ns
ER
Notes:
1. See “Switching Test Circuit” for test conditions.
2. This parameter is tested in standby mode.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. Output delay minimums for t , t , t , t , t , and t are defined under best case conditions. Future process improvements
PD CO PZX PXZ EA
ER
may alter these values therefore, minimum values are recommended for simulation purposes only.
5. t is a calculated value and is not guaranteed. t can be found using the following equation:
CF
CF
t
= 1/f
(internal feedback) – t .
CF
MAX S
20
PALCE16V8Z-12 (Ind)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Industrial (I) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (T )
Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C
A
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
Supply Voltage (V
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
)
CC
DC Input Voltage . . . . . . . . . . . -0.5 V to V + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
CC
DC Output or I/O Pin Voltage . . . -0.5 V to V + 0.5 V
CC
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (T = -40°C to +85°C). . . . . . . 100 mA
A
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
DC CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Description
Min
Max
Unit
V
I
= 6 mA
= 20 µA
= 24 mA
= 6 mA
= 20 µA
3.84
OH
V
V = V or V , V = Min
IN IH IL CC
OH
I
V – 0.1 V
V
OH
CC
I
0.5
0.33
0.1
V
OL
V
Output LOW Voltage
V = V or V , V = Min
I
OL
V
OL
IN
IH
IL CC
I
V
OL
Guaranteed Input Logical HIGH
Voltage for all Inputs (Notes 1 and 2)
V
Input HIGH Voltage
Input LOW Voltage
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1 and 2)
V
0.9
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V = 5.25 V, V = Max (Note 3)
10
µA
µA
IH
IN
CC
I
V = 0 V, V = Max (Note 3)
–10
IL
IN
CC
V
= 5.25 V, V = Max
CC
OUT
I
Off-State Output Leakage Current HIGH
Off-State Output Leakage Current LOW
10
µA
µA
OZH
V = V or V (Note 3)
IN
IH
IL
V
= 0 V, V = Max
CC
OUT
I
–10
OZL
V = V or V (Note 3)
IN
IH
IL
I
Output Short-Circuit Current
Supply Current (Static)
V
= 0.5 V, V = Max (Note 4)
–30
–150
15
mA
µA
SC
OUT
CC
f = 0 MHz
Outputs Open (I = 0 mA)
OUT
I
CC
V = Max
Supply Current (Dynamic)
f = 25 MHz
75
mA
CC
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. I/O pin leakage is the worst case of I and I
(or I and I
).
IL
OZL
IH
OZH
4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
V
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
OUT
PALCE16V8Z-15 (Ind)
21
CAPACITANCE1
Parameter
Symbol
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
Typ
5
Unit
pF
C
V = 2.0 V
IN
V = 5.0 V, T = 25 °C,
CC A
IN
C
V
= 2.0 V
f = 1 MHz
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES1
-15
Parameter
Symbol
2
Parameter Description
Input or Feedback to Combinatorial Output
Min
Max
Unit
ns
t
15
PD
t
Setup Time from Input or Feedback to Clock
Hold Time
10
0
ns
S
t
ns
H
t
Clock to Output
10
ns
CO
t
LOW
Clock Width
8
8
ns
WL
t
HIGH
ns
WH
External Feedback
Maximum
Frequency (Notes 3 Internal Feedback (f
1/(t +t )
50
MHz
MHz
MHz
ns
S
CO
f
)
1/(t +t )
58.8
62.5
MAX
CNT
S CF
and 4)
No Feedback
1/(t +t )
WH WL
t
OE to Output Enable
OE to Output Disable
15
15
15
15
PZX
t
ns
PXZ
t
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
ns
EA
t
ns
ER
Notes:
1. See “Switching Test Circuit” for test conditions.
2. This parameter is tested in standby mode.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
4. t is a calculated value and is not guaranteed. t can be found using the following equation:
CF
CF
t
= 1/f
(internal feedback) – t .
CF
MAX S
22
PALCE16V8Z-15 (Ind)
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Commercial (C) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Ambient Temperature (T )
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
A
Supply Voltage
with Respect to Ground . . . . . . . . . .-0.5 V to + 7.0 V
Supply Voltage (V
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
)
CC
DC Input Voltage . . . . . . . . . . . -0.5 V to V + 0.5 V
CC
Industrial (I) Devices
DC Output or I/O Pin Voltage . . . -0.5 V to V + 0.5 V
CC
Temperature (T ) Operating
A
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
in Free Air. . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Latchup Current (T = -40°C to +85°C). . . . . . . 100 mA
Supply Voltage (V
)
A
CC
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability. Pro-
gramming conditions may differ.
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING
RANGES
Parameter
Symbol
Parameter Description
Output HIGH Voltage
Test Description
Min
Max
Unit
V
I
= 6 mA
= 20 µA
= 24 mA
= 6 mA
= 20 µA
3.84
OH
V
V = V or V , V = Min
IN IH IL CC
OH
I
V – 0.1 V
V
OH
CC
I
0.5
0.33
0.1
V
OL
V
Output LOW Voltage
V = V or V , V = Min
I
OL
V
OL
IN
IH
IL CC
I
V
OL
Guaranteed Input Logical HIGH
Voltage for all Inputs (Notes 1 and 2)
V
Input HIGH Voltage
Input LOW Voltage
2.0
V
V
IH
Guaranteed Input Logical LOW
Voltage for all Inputs (Notes 1 and 2)
V
0.9
IL
I
Input HIGH Leakage Current
Input LOW Leakage Current
V = 5.25 V, V = Max (Note 3)
10
µA
µA
IH
IN
CC
I
V = 0 V, V = Max (Note 3)
–10
IL
IN
CC
V
= 5.25 V, V = Max
CC
OUT
I
Off-State Output Leakage Current HIGH
Off-State Output Leakage Current LOW
10
µA
µA
OZH
V = V or V (Note 3)
IN
IH
IL
V
= 0 V, V = Max
CC
OUT
I
–10
OZL
V = V or V (Note 3)
IN
IH
IL
I
Output Short-Circuit Current
Supply Current (Static)
V
= 0.5 V, V = Max (Note 4)
–30
–150
15
mA
µA
SC
OUT
CC
f = 0 MHz
Outputs Open (I = 0 mA)
OUT
I
CC
V = Max
Supply Current (Dynamic)
f = 25 MHz
90
mA
CC
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. Represents the worst case of HC and HCT standards, allowing compatibility with either.
3. I/O pin leakage is the worst case of I and I
(or I and I
).
IL
OZL
IH
OZH
4. Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
V
= 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
OUT
PALCE16V8Z-25 (Com’l, Ind)
23
CAPACITANCE1
Parameter
Symbol
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
Typ
5
Unit
pF
C
V = 2.0 V
IN
V = 5.0 V, T = 25 °C,
CC A
IN
C
V
= 2.0 V
f = 1 MHz
8
pF
OUT
OUT
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL
OPERATING RANGES1
-25
Parameter
Symbol
2
Parameter Description
Input or Feedback to Combinatorial Output (Note 3)
Min
Max
Unit
ns
t
25
PD
t
Setup Time from Input or Feedback to Clock
Hold Time
20
0
ns
S
t
ns
H
t
Clock to Output
10
ns
CO
t
LOW
Clock Width
8
8
ns
WL
t
HIGH
ns
WH
External Feedback
Maximum
Frequency (Notes 4 Internal Feedback (f
1/(t +t )
33.3
50
50
MHz
MHz
MHz
ns
S
CO
f
)
1/(t +t )
S CF
MAX
CNT
and 5)
No Feedback
1/(t +t )
WH WL
t
OE to Output Enable
OE to Output Disable
25
25
25
25
PZX
t
ns
PXZ
t
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
ns
EA
t
ns
ER
Notes:
1. See “Switching Test Circuit” for test conditions.
2. This parameter is tested in standby mode.
3. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the t will typically be 2 ns faster.
PD
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
5. t is a calculated value and is not guaranteed. t can be found using the following equation:
CF
CF
t
= 1/f
(internal feedback) – t .
CF
MAX S
24
PALCE16V8Z-25 (Com’l, Ind)
SWITCHING WAVEFORMS
Input or
Feedback
V
T
Input or
Feedback
V
T
t
t
S
H
t
PD
V
T
Clock
Combinatorial
Output
t
CO
V
T
Registered
Output
V
T
16493E-3
16493E-5
b. Registered output
a. Combinatorial output
V
Input
T
t
WH
t
t
EA
ER
V
– 0.5V
+ 0.5V
OH
Clock
V
V
T
T
Output
V
OL
t
WL
16493E-6
16493E-4
d. Input to output disable/enable
c. Clock w idth
V
T
OE
t
t
PZX
PXZ
V
– 0.5V
+ 0.5V
OH
V
Output
T
V
OL
16493E-7
e. OE to output disable/enable
Notes:
1. V = 1.5 V
T
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns to 5 ns typical.
PALCE16V8 and PALCE16V8Z Families
25
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5 V
S
1
R
1
Output
Test Point
R
2
C
L
16493E-8
Commercial
Specification
S
C
R
R
2
Measured Output Value
1
L
1
t , t
Closed
1.5 V
PD CO
Z → H: Open
Z → L: Closed
H → Z: Open
L → Z: Closed
50 pF
5 pF
390 Ω
t
1.5 V
EA
200 Ω
H → Z: V – 0.5 V
OH
t
H-5: 200 Ω
ER
L → Z: V + 0.5 V
OL
26
PALCE16V8 and PALCE16V8Z Families
TYPICAL ICC CHARACTERISTICS
V
= 5 V, T = 25°C
CC
A
150
125
100
75
16V8H-5
16V8H-7
16V8H-10
16V8H-15/25
16V8Z-12/15
50
16V8Q-10/15/25
16V8Z-25
25
0
0
10
20
30
40
50
16493E-9
Frequency (MHz)
I
vs. Frequency
CC
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the
other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half
of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for I . From this midpoint, a designer may scale the I graphs up or down to
CC
CC
estimate the I requirements for a particular design.
CC
PALCE16V8 and PALCE16V8Z Families
27
ENDURANCE CHARACTERISTICS
The PALCE16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the
device can be erased and reprogrammed—a feature which allows 100% testing at the factory.
Symbol
Parameter
Min Pattern Data Retention Time
Min Reprogramming Cycles
Test Conditions
Max Storage Temperature
Value
10
Unit
Years
Years
Cycles
t
DR
Max Operating Temperature
20
N
Normal Programming Conditions
100
ROBUSTNESS FEATURES
PALCE16V8X-X/5 devices have some unique features that make them extremely robust,
especially when operating in high-speed design environments. Pull-up resistors on inputs and
I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits
negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing.
A special noise filter makes the programming circuitry completely insensitive to any positive
overshoot that has a pulse width of less than about 100 ns for the /5 versions. Selected /4 devices
are also being retrofitted with these robustness features.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8
V
VC
CC
C
> 50 kΩ
ESD
Protection
and
Programming
Pins Only
Programming
Voltage
Detection
Positive
Overshoot
Filter
Programming
Circuitry
Clamping
Typical Input
V
V
CC
CC
> 50 kΩ
Provides ESD
Protection and
Clamping
Preload Feedback
Circuitry
Input
16493E-10
Typical Output
28
PALCE16V8 and PALCE16V8Z Families
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8Z
V
CC
ESD
Input
Programming
Programming
Voltage
Detection
Positive
Overshoot
Filter
Protection Transition Pins Only
Programming
Circuitry
and
Clamping
Detection
Typical Input
V
CC
16493E-11
Provides ESD
Protection and
Clamping
Preload Feedback Input
Circuitry
Input Transition
Detection
Typical Output
POWER-UP RESET
The PALCE16V8 has been designed with the capability to reset during system power-up.
Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH
independent of the logic polarity. This feature provides extra flexibility to the designer and is
especially valuable in simplifying state machine initialization. A timing diagram and parameter
table are shown below. Due to the synchronous operation of the power-up reset and the wide
range of ways VCC can rise to its steady state, two conditions are required to ensure a valid
power-up reset. These conditions are:
The VCC rise must be monotonic.
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter Symbol
Parameter Descriptions
Power-Up Reset Time
Min
Max
Unit
t
1000
ns
PR
t
Input or Feedback Setup Time
Clock Width LOW
S
See Switching Characteristics
t
WL
PALCE16V8 and PALCE16V8Z Families
29
V
CC
4 V
Power
t
PR
Registered
Output
t
S
Clock
t
WL
16493E-12
Figure 3. Pow er-Up Reset Waveform
TYPICAL THERMAL CHARACTERISTICS
Measured at 25°C ambient. These parameters are not tested.
Typ
Parameter
Symbol
Parameter Description
Thermal impedance, junction to case
PDID
25
PLCC
22
Unit
θ
θ
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
jc
ja
Thermal impedance, junction to ambient
71
64
200 lfpm air
400 lfpm air
600 lfpm air
800 lfpm air
61
55
55
51
θ
Thermal impedance, junction to ambient with air flow
jma
51
47
47
45
Plastic θ Considerations
jc
The data listed for plastic θ are for reference only and are not recommended for use in calculating junction temperatures. The
jc
heat-flow paths in plastic-encapsulated devices are complex, making the θ measurement relative to a specific location on the pack-
jc
age surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package.
Furthermore, θ tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant tem-
jc
perature. Therefore, the measurements can only be used in a similar environment.
30
PALCE16V8 and PALCE16V8Z Families
CONNECTION DIAGRAMS
Top View
DIP/SOIC
PLCC
CLK/I
1
2
3
4
5
6
7
8
9
10
20
V
CC
0
1
2
3
4
5
6
7
8
I
I
I
I
I
I
I
I
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
12 I/O
7
6
5
4
3
2
1
0
3
2
1
20
19
I/O6
I/O5
I/O4
I/O3
18
17
16
15
4
5
6
7
I3
I4
I5
I6
14
I/O2
I7
8
GND
11 OE/I
9
9
10 11 12 13
16493E-9
Note:
16493E-10
Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK = Clock
GND = Ground
I
= Input
I/O
OE
= Input/Output
= Output Enable
= Supply Voltage
V
CC
PALCE16V8 and PALCE16V8Z Families
31
ORDERING INFORMATION
Commercial and Industrial Products
Lattice/Vantis programmable logic products for commercial and industrial applications are available with several ordering options.
The order number (Valid Combination) is formed by a combination of:
PAL CE 16 V 8 H -5 J C /5
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/4 = First Revision
CE
= CMOS Electrically Erasable
NUMBER OF
ARRAY INPUTS
/5 = Second Revision
(Same Algorithm as /4)
OUTPUT TYPE
V
= Versatile
NUMBER OF OUTPUTS
OPERATING CONDITIONS
POWER
C
I
= Commercial (0°C to +75°C)
= Industrial (-40°C to +85°C)
H
Q
Z
= Half Power (90–125 mA I )
CC
= Quarter Power (55 mA I
= Zero Power (15 µA I Standby)
)
CC
CC
PACKAGE TYPE
SPEED
-5
-7
-10
-12
-15
-20
-25
P
J
= 20-Pin Plastic DIP (PD 020)
= 20-Pin Plastic Leaded Chip
Carrier (PL 020)
= 20-Pin Plastic Gull-Wing
Small Outline Package (SO 020)
= 5 ns t
= 7.5 ns t
= 10 ns t
= 12 ns t
= 15 ns t
= 20 ns t
= 25 ns t
PD
PD
S
PD
PD
PD
PD
PD
Valid Combinations
Valid Combinations
JC
Valid Combinations lists configurations planned to be
supported in volume for this device. Consult the local Lattice/
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
PALCE16V8H-5
PALCE16V8H-7
PALCE16V8H-10
PALCE16V8Q-10
PALCE16V8H-15
PALCE16V8Q-15
PALCE16V8Q-20
PALCE16V8H-25
PALCE16V8Q-25
PALCE16V8Z-12
PALCE16V8Z-15
PALCE16V8Z-25
/5
PC, JC, SC
PC, JC, SC, PI, JI
JC
/4
/5
PC, JC, SC
PC, JC
PI, JI
/4
PC, JC, SC, PI, JI
PC, JC, PI, JI
PI, JI
PC, JC, SC, PI, JI, SI
32
PALCE16V8 and PALCE16V8Z Families
相关型号：
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