LT1425CS [Linear]
Isolated Flyback Switching Regulator; 隔离型反激式开关稳压器
| 型号： | LT1425CS |
| 厂家： | 
Linear |
| 描述： | Isolated Flyback Switching Regulator |
| 文件： | 总20页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1425
Isolated Flyback
Switching Regulator
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FEATURES
DESCRIPTION
The LT®1425 is a monolithic high power switching regu-
lator specifically designed for the isolated flyback topol-
ogy. No “third winding” or optoisolator is required; the
integrated circuit senses the isolated output voltage
directly from the primary side flyback waveform. A high
current, high efficiency switch is included on the die along
with all oscillator, control and protection circuitry.
■
No Transformer “Third Winding” or Optoisolator
Required
■
±5% Accurate Output Voltage Without User Trims
(See Circuit Below)
Resistor Programmable Output Voltage
■
■
Regulation Maintained Well Into Discontinuous
Mode (Light Load)
■
Optional Load Compensation
The LT1425 operates with input supply voltages from 3V
to 20V and draws only 7mA quiescent current. It can
deliver output power up to 6W with no external power
devices. Byutilizingcurrentmodeswitchingtechniques, it
provides excellent AC and DC line regulation.
■
Operating Frequency: 285kHz
■
Easily Synchronized to External Clock
■
Available in 16-Pin Narrow SO Package
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APPLICATIONS
The LT1425 has a number of features not found on other
switching regulator ICs. Its unique control circuitry can
maintain regulation well into discontinuous mode in most
applications. Optional load compensation circuitry allows
for improved load regulation. An externally activated shut-
down mode reduces total supply current to 15µA for
standby operation.
■
Isolated Flyback Switching Regulators
■
Ethernet Isolated 5V to –9V Converters
■
Medical Instruments
Isolated Telecom Supplies
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
5V to Isolated –9VOUT
Load Regulation
500V
9.5
9.4
9.3
9.2
9.1
9.0
8.9
8.8
8.7
8.6
8.5
ISOLATION BARRIER
5V
T1*
–
V
+
C1
100µF
10V
C2
ISOLATED
–9V ±5% AT
20mA TO 200mA
D1
1N5819
12
47µF
+
16V
V
IN
11
3
•
•
V
SW
R1
22.6k
1%
F
LT1425
*DALE LPE 4841-330MB
15
R
FB
SHDN
R2
3.01k
1%
6
SYNC
5
4
R
V
C
REF
C3
1000pF
14
13
R
OCOMP
0
50
100
150
200
R3
15k
R
CCOMP
C4
0.1µF
OUTPUT CURRENT (mA)
SGND PGND
10
1425 TA02
7
1425 TA01
1
LT1425
W W U W
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
ORDER PART
NUMBER
Supply Voltage ........................................................ 20V
Switch Voltage......................................................... 35V
SHDN, SYNC Pin Voltage........................................... 7V
GND
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
SHDN
R
R
FB
OCOMP
R
FB Pin Current....................................................... 2mA
LT1425CS
LT1425IS
V
C
R
V
CCOMP
Operating Junction Temperature Range
R
REF
IN
Commercial .......................................... 0°C to 100°C
Industrial ......................................... –40°C to 100°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
SYNC
SGND
GND
V
SW
PGND
GND
S PACKAGE
16-LEAD PLASTIC SO
TJMAX = 145°C, θJA = 75°C/ W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VIN = 5V, TJ = 25°C, VSW open, VC = 1.4V, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Feedback Amplifier
I
I
Reference Current
Pin Input Current
Measured at R Pin with R = 3.000k
402
396
408
414
420
µA
µA
REF
IN
FB
REF
●
R
500
1000
50
nA
µmho
µA
REF
g
Feedback Amplifier Transconductance
Feedback Amplifier Source or Sink Current
Feedback Amplifier Clamp Voltage
Reference Voltage/Current Line Regulation
Voltage Gain
∆I = ±10µA (Note 2)
C
●
●
400
30
1600
80
m
I
, I
SOURCE SINK
V
1.9
V
CL
5V ≤ V ≤ 18V
●
●
0.01
500
10
0.04
25
%/V
V/V
mV
IN
(Note 3)
V
Sense Error
IN
Output Switch
BV
Output Switch Breakdown Voltage
Output Switch ON Voltage
Switch Current Limit
I = 5mA
●
●
35
50
V
V
C
V(V
)
SW
I
= 1A
SW
0.55
0.85
I
Duty Cycle = 50%, 0°C ≤ T ≤ 100°C
Duty Cycle = 50%, –40°C ≤ T ≤ 100°C
Duty Cycle = 80%
●
●
1.35
1.25
1.60
1.60
1.30
1.9
1.9
A
A
A
LIM
J
J
Current Amplifier
Control Pin Threshold
Duty Cycle = Minimum
0.95
0.85
1.2
2
1.3
1.4
V
V
●
●
Control Voltage to Switch Transconductance
Switching Frequency
A/V
Timing
f
260
240
285
300
320
kHz
kHz
t
t
t
Minimum Switch ON Time
Flyback Enable Delay Time
Minimum Flyback Enable Time
Maximum Switch Duty Cycle
170
210
150
180
90
260
ns
ns
ns
%
ON
ED
EN
●
85
95
2
LT1425
ELECTRICAL CHARACTERISTICS
VIN = 5V, TJ = 25°C, VSW Open, VC = 1.4V, unless otherwise specified.
SYMBOL
Load Compensation
∆V
PARAMETER
CONDITIONS
MIN
TYP
0.45
1.5
MAX
UNITS
/∆I
Ω
RCCOMP SW
SYNC Function
Minimum SYNC Amplitude
Synchronization Range
●
2.2
V
kHz
kΩ
320
450
SYNC Pin Input Resistance
40
Power Supply
V
Minimum Input Voltage
Supply Current
●
●
●
●
2.8
7.0
15
3.1
9.5
40
V
mA
µA
V
IN(MIN)
I
CC
Shutdown Mode Supply Current
Shutdown Mode Threshold
0.4
0.9
1.3
The
●
denotes the specifications which apply over the full operating
Note 2: Feedback amplifier transconductance is R referred.
REF
temperature range.
Note 3: Voltage gain is R referred.
REF
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
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TYPICAL PERFORMANCE CHARACTERISTICS
Switch Saturation Voltage vs
Switch Current
Switch Current Limit vs
Duty Cycle
Minimum Input Voltage vs
Temperature
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0
1.5
1.0
0.5
0
T
A
= 25°C
125°C
25°C
–55°C
50
TEMPERATURE (°C)
75
100 125
0.8
SWITCH CURRENT (A)
1.2
1.4
–50 –25
0
25
0
0.2
0.4 0.6
1.0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
1425 G03
1425 G01
1425 G02
3
LT1425
TYPICAL PERFORMANCE CHARACTERISTICS
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Feedback Amplifier Output
Current vs RREF Pin Voltage
VC Pin Threshold and High Clamp
Voltage vs Temperature
Error Amplifier Transconductance
vs Temperature (RREF Referred)
60
40
1400
1200
1000
800
600
400
200
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
25°C
125°C
–55°C
V
HIGH CLAMP
C
20
0
–20
–40
–60
–80
V
THRESHOLD
C
1.25
1.30
1.35 1.40
–50 –25
0
25
50
75
100 125
50
TEMPERATURE (°C)
100 125
1.05 1.10 1.15 1.20
–50
25
75
–25
0
R
NODE VOLTAGE (V)
TEMPERATURE (°C)
REF
1425 G04
1425 G05
1425 G06
Switching Frequency vs
Temperature
Minimum Synchronization
Voltage vs Temperature
SHDN Pin Input Current vs
Voltage
300
295
290
285
280
275
270
265
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
1
0
T
= 25°C
A
–1
–2
–3
–4
–50 –25
0
25
50
TEMPERATURE (°C)
75
100 125
–50
25
50
TEMPERATURE (°C)
75
100 125
0
1
2
3
4
5
–25
0
SHDN PIN VOLTAGE (V)
1425 G07
1425 G08
1425 G09
Minimum Switch ON Time vs
Temperature
Flyback Enable Delay Time vs
Temperature
Minimum Flyback Enable Time vs
Temperature
250
300
275
250
225
200
175
150
125
275
250
225
200
175
150
125
100
225
200
175
150
125
100
75
–50 –25
0
25
50
TEMPERATURE (°C)
75
100 125
–50 –25
0
25
50
TEMPERATURE (°C)
75
100 125
–50 –25
0
25
50
75
100 125
TEMPERATURE (°C)
1425 G11
1425 G10
1425 G12
4
LT1425
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PIN FUNCTIONS
GND (Pins 1, 8, 9, 16): Ground. These pins connect to the
substrate of the die and are separate from the power
groundandsignalground.Theyshouldconnectdirectlyto
a good quality ground plane.
PGND (Pin 10): Power Ground. This pin is the emitter of
the power switch device and has large currents flowing
throughit.Itshouldbeconnecteddirectlytoagoodquality
ground plane.
RFB (Pin 3): Input Pin for External “Feedback” Resistor
ConnectedtoTransformerPrimary(VSW). Theratioofthis
resistor to the RREF resistor, times the internal bandgap
(VBG) reference, is the primary determinant of the output
voltage (plus the effect of any nonunity transformer turns
ratio).Theaveragecurrentthroughthisresistorduringthe
flyback period should be approximately 400µA. See Appli-
cations Information for more details.
VSW (Pin 11): This is the collector node of the output
switch and has large currents flowing through it. Keep the
traces to the switching components as short as possible
to minimize electromagnetic radiation and voltage spikes.
VIN (Pin12): SupplyVoltage. Bypassinputsupplypinwith
10µF or more. The part goes into undervoltage lockout
when VIN drops below 2.8V. Undervoltage lockout stops
switching and pulls the VC pin low.
VC (Pin 4): Control Voltage. This pin is the output of the
feedback amplifier and the input of the current compara-
tor.Frequencycompensationoftheoverallloopiseffected
by placing a capacitor between this node and ground.
RCCOMP (Pin 13): Pin for the External Filter Capacitor for
Load Compensation Function. A common 0.1µF
ceramic capacitor will suffice for most applications. See
Applications Information for further details.
RREF (Pin 5): Input Pin for External Ground-Referred
“Reference” Resistor. This resistor should be in the range
of3k,butforconvenience,neednotbethisvalueprecisely.
See Applications Information for more details.
ROCOMP (Pin 14): Input Pin for Optional External Load
Compensation Resistor. Use of this pin allows nominal
compensation for nonzero output impedance in the power
transformer secondary circuit, including secondary wind-
ing impedance, output Schottky diode impedance and
output capacitor ESR. In less demanding applications this
resistor is not needed. See Applications Information for
more details.
SYNC (Pin 6): Pin to Synchronize Internal Oscillator to
External Frequency Reference. It is directly logic compat-
ible and can be driven with any signal between 10% and
90% duty cycle. If unused, this pin can be left floating;
however, for best noise immunity the pin should be
grounded.
SHDN (Pin 15): Shutdown. This pin is used to turn off the
regulator and reduce VIN input current to a few tens of
microamperes. The SHDN pin can be left floating when
unused.
SGND (Pin 7): Signal Ground. This pin is a clean ground.
The internal reference and feedback amplifier are referred
to it. Keep the ground path connection to RREF and the VC
compensation capacitor free of large ground currents.
5
LT1425
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BLOCK DIAGRAM
V
IN
R
FB
R
REF
2.6V
SHDN
SYNC
REGULATOR
V
SW
FLYBACK
ERROR
AMPLIFIER
285kHz
OSCILLATOR
LOGIC
COMP
DRIVER
R
CCOMP
LOAD
COMPENSATION
R
OC0MP
SGND
V
C
+
CURRENT
AMPLIFIER
R
SENSE
GND IS OMITTED FOR CLARITY
PGND
–
1425 BD
W
W
FLYBACK ERROR A PLIFIER DIAGRA
D1
V
IN
T1
+
•
+
ISOLATED
C1
V
OUT
V
SW
•
–
V
IN
R
FB
Q4
I
I
FXD
M
D2
R
FB
V
C
Q1
ENABLE
V
C
EXT
Q2 Q3
I
BG
R
REF
I
M
R
REF
1425 EA
6
LT1425
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TI I G DIAGRA
V
SW
VOLTAGE
COLLAPSE
DETECT
V
FLBK
0.80×
FLBK
V
V
IN
GND
SWITCH
STATE
OFF
ON
OFF
ON
MINIMUM t
ON
ENABLE DELAY
DISABLED
MINIMUM ENABLE TIME
FLYBACK AMP
STATE
ENABLED
DISABLED
1425 TD
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OPERATION
The LT1425 derives its information about the isolated
output voltage by examining the primary side flyback
pulsewaveform. Inthismannernooptoisolatornorextra
transformer winding is required. This IC is a quantum
improvement over previous approaches because: target
output voltage is directly resistor-programmable, regu-
lation is maintained well into discontinuous mode and
optional load compensation is available.
TheLT1425isacurrentmodeswitchingregulatorIC that
has been designed specifically for the isolated flyback
topology. The special problem normally encountered in
such circuits is that information relating to the output
voltageontheisolatedsecondarysideofthetransformer
must be communicated to the primary side in order to
maintainregulation. Historically, thishasbeendonewith
optoisolatorsorextratransformerwindings.Optoisolator
circuits waste output power and the extra components
they require increase the cost and physical volume of the
power supply. Optoisolators can also exhibit trouble due
to limited dynamic response (temporal), nonlinearity,
unit-to-unit variation and aging over life. Circuits
employing extra transformer windings also exhibit defi-
ciencies. The extra winding adds to the transformer’s
physical size and cost. Dynamic response is often
mediocre. There is usually no method for maintaining
load regulation versus load.
The Block Diagram shows an overall view of the system.
Many of the blocks are similar to those found in tradi-
tional designs including: internal bias regulator, oscilla-
tor, logic, current amplifier and comparator, driver and
output switch. The novel sections include a special
flyback error amplifier and a load compensation mecha-
nism. Also, due to the special dynamic requirements of
flyback control, the logic system contains additional
functionality not found in conventional designs.
7
LT1425
U
OPERATION
Within the dashed lines in the Block Diagram can be found
the RREF, RFB and ROCOMP resistors. They are external
resistors on the user-programmable LT1425. The capaci-
tor connected to the RCCOMP pin is also external.
V
R
V
FLBK
BG
α
=
or,
R
FB
REF
R
1
FB
V
= V
FLBK
BG
)
)
)
)
α
R
REF
TheLT1425operatesmuchthesameastraditionalcurrent
mode switchers, the major difference being a different
type of error amplifier which derives its feedback informa-
tion from the flyback pulse. Due to space constraints, this
discussion will not reiterate the basics of current mode
switcher/controllers and isolated flyback converters. A
good source of information on these topics is LTC’s
Application Note 19.
α = Ratio of Q1 I to I
C
E
V
= Internal bandgap reference
BG
Combination with the previous VFLBK expression yields an
expression for VOUT, in terms of the internal reference,
programming resistors, transformer turns ratio and diode
forward voltage drop:
R
N
SP
ERROR AMPLIFIER—PSEUDO DC THEORY
FB
V
= V
– V – I
(ESR)
SEC
OUT
BG
F
)
)
)
)
α
R
REF
Please refer to the simplified diagram of the Flyback Error
Amplifier. Operation is as follows: when output switch Q4
turns off, its collector voltage rises above the VIN rail. The
amplitudeofthisflybackpulse,i.e.,thedifferencebetween
it and VIN, is given as:
Additionally, it includes the effect of nonzero secondary
output impedance. See Load Compensation for details.
ThepracticalaspectsofapplyingthisequationforVOUT are
found in the Applications Information section.
So far, this has been a pseudo-DC treatment of flyback
error amplifier operation. But the flyback signal is a pulse,
not a DC level. Provision must be made to enable the
flyback amplifier only when the flyback pulse is present.
Thisisaccomplishedbythedashedlineconnectionstothe
block labeled “ENABLE.” Timing signals are then required
to enable and disable the flyback amplifier.
V
+ V + (I )(ESR)
F
OUT
SEC
SP
V
=
FLBK
N
V = D1 forward voltage
F
SEC
I
= Transformer secondary current
ESR = Total impedance of secondary circuit
N
= Transformer effective secondary-to-primary
turns ratio
SP
ERROR AMPLIFIER—DYNAMIC THEORY
The flyback voltage is then converted to a current by the
action of RFB and Q1. Nearly all of this current flows
through resistor RREF to form a ground-referred voltage.
Thisisthencomparedtotheinternalbandgapreferenceby
thedifferentialtransistorpairQ2/Q3. Thecollectorcurrent
from Q2 is mirrored around and subtracted from fixed
current source IFXD at the VC pin. An external capacitor
integrates this net current to provide the control voltage to
set the current mode trip point.
There are several timing signals that are required for
proper LT1425 operation. Please refer to the Timing
Diagram.
Minimum Output Switch ON Time
The LT1425 effects output voltage regulation via flyback
pulse action. If the output switch is not turned on at all,
there will be no flyback pulse, and output voltage informa-
tion is no longer available. This would cause irregular loop
response and start-up/latchup problems. The solution
chosen is to require the output switch to be on for an
absolute minimum time per each oscillator cycle. This in
turn establishes a minimum load requirement to maintain
The relatively high gain in the overall loop will then cause
the voltage at the RREF resistor to be nearly equal to the
bandgap reference VBG. (VBG is not present in final output
voltage setting equation. See Applications Information
section.) The relationship between VFLBK and VBG may
then be expressed as:
8
LT1425
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OPERATION
regulation. See Applications Information section for fur-
ther details.
Effects of Variable Enable Period
It should now be clear that the flyback amplifier is enabled
only during a portion of the cycle time. This can vary from
thefixed“minimumenabletime”describedtoamaximum
of roughly the OFF switch time minus the enable delay
time. Certain parameters of flyback amp behavior willthen
be directly affected by the variable enable period. These
include effective transconductance and VC node slew rate.
Enable Delay
When the output switch shuts off, the flyback pulse
appears. However, it takes a finite time until the trans-
former primaryside voltage waveformapproximately rep-
resents the output voltage. This is partly due to rise time
ontheVSW node, butmoreimportantlyduetotransformer
leakage inductance. The latter causes a voltage spike on
the primary side not directly related to output voltage.
(Some time is also required for internal settling of the
feedback amplifier circuitry.)
LOAD COMPENSATION THEORY
The LT1425 uses the flyback pulse to obtain information
about the isolated output voltage. A potential error source
is caused by transformer secondary current flow through
the real life nonzero impedances of the output rectifier,
transformer secondary and output capacitor. This has
beenrepresentedpreviouslybytheexpression(ISEC)(ESR).
However,itisgenerallymoreusefultoconvertthisexpres-
sion to an effective output impedance. Because the sec-
ondarycurrentonlyflowsduringtheoffportionoftheduty
cycle, the effective output impedance equals the lumped
secondary impedance times the inverse of the OFF duty
cycle. That is,
Inordertomaintainimmunitytothesephenomena, afixed
delay is introduced between the switch turn-off command
and the enabling of the feedback amplifier. This is termed
“enable delay.” In certain cases where the leakage spike is
not sufficiently settled by the end of the enable delay
period, regulation error may result. See Applications
Information section for further details.
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, that compares the flyback
voltage (RREF referred) to a fixed reference, nominally
80% of VBG. When the flyback waveform drops below this
level, the feedback amplifier is disabled. This action
accommodatesbothcontinuousanddiscontinuousmode
operation.
1
R
= ESR
OUT
)
)
DC OFF
where,
R
= Effective supply output impedance
ESR = Lumped secondary impedance
DC OFF = OFF duty cycle
OUT
Minimum Enable Time
Expressing this in terms of the ON duty cycle, remember-
ing DC OFF = 1 – DC,
The feedback amplifier, once enabled, stays enabled for a
fixed minimum time period termed “minimum enable
time.” This prevents lock-up, especially when the output
voltage is abnormally low, e.g., during start-up. The mini-
mum enable time period ensures that the VC node is able
to “pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. The “minimum enable time” often determines
thelowloadlevelatwhichoutputvoltageregulationislost.
See Applications Information section for details.
1
R
= ESR
OUT
)
)
1 – DC
DC = ON duty cycle
In less critical applications, or if output load current
remains relatively constant, this output impedance error
may be judged acceptable and the external RFB resistor
value adjusted to compensate for nominal expected error.
In more demanding applications, output impedance error
9
LT1425
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OPERATION
may be minimized by the use of the load compensation
function.
external ROCOMP resistor to form a current that is
subtracted from the RFB node. So the effective change in
V
OUT target is:
Toimplementtheloadcompensationfunction,avoltageis
developed that is proportional to average output switch
current.Thisvoltageisthenimpressedacrosstheexternal
ROCOMP resistor and the resulting current is then sub-
tracted from the RFB node. As output loading increases,
averageswitchcurrentincreasestomaintainroughoutput
voltage regulation. This causes an increase in ROCOMP
resistor current subtracted from the RFB node, through
which feedback loop action causes a corresponding
increase in target output voltage.
(R
R
)(G)
SENSE
∆V = K1(∆I
)
R
FB
OUT
OUT
)
)
OCOMP
Expressing the product of RSENSE and G as the data sheet
value of ∆VRCCOMP/∆ISW
,
∆V
R
FB
R
OCOMP
RCCOMP
R
= K1
and,
OUT
)
)
)
)
)
∆I
SW
R
∆V
)
FB
RCCOMP
R
= K1
OCOMP
)
)
Assuming a relatively fixed power supply efficiency, Eff,
Power Out = (Eff)(Power In)
R
∆I
OUT
SW
where,
K1 = Dimensionless variable related to V ,
(VOUT)(IOUT) = (Eff)(VIN)(IIN)
IN
V
and efficiency as above
OUT
Average primary side current may be expressed in terms
of output current as follows:
∆V
RCCOMP
= Data sheet value for R
pin
CCOMP
)
)
∆I
SW
V
action vs switch current
OUT
I =
I
OUT
IN
)
)
(V )(Eff)
R = External “feedback” resistor value
IN
FB
R
= Uncompensated output impedance
OUT
Combining the efficiency and voltage terms in a single
variable,
∆V
∆I
∆V
R
FB
OUT
OUT
RCCOMP
= K1
)
)
)
R
)
∆I
SW
OCOMP
I = K1(I
)
OUT
IN
where,
Nominal output impedance cancellation is obtained by
equating this expression with ROUT. The practical aspects
of applying this equation to determine an appropriate
value forthe ROCOMP resistorare found inthe Applications
Information section.
V
OUT
K1 =
)
)
(V )(Eff)
IN
Switch current is converted to voltage by a sense resistor
and amplified by the current sense amplifier with associ-
ated gain G. This voltage is then impressed across the
10
LT1425
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APPLICATIONS INFORMATION
ROCOMP, the external resistor value required for its nomi-
nal compensation:
SELECTING RFB AND RREF RESISTOR VALUES
The expression for VOUT developed in the Operation
section can be rearranged to yield the following expres-
sion for RFB:
1
R
R
= ESR
OUT
)
)
1 – DC
V
+ V + I (ESR)
α
N
SP
OUT
F
SEC
BG
∆V
R
R = R
RCCOMP
FB
FB
REF
)
)
)
)
= K1
V
OCOMP
)
)
)
)
∆I
R
SW
OUT
The unknown parameter α, which represents the fraction
of RFB current flowing into the RREF node, can be repre-
sented instead by specified data sheet values as follows:
While the value for ROCOMP may therefore be theoretically
determined, it is usually better in practice to employ
empirical methods. This is because several of the required
input variables are difficult to estimate precisely. For
instance, the ESR term above includes that of the trans-
former secondary, but its effective ESR value depends on
high frequency behavior, not simply DC winding resis-
tance. Similarly, K1 appears to be a simple ratio of VIN to
VOUT times (differential) efficiency, but theoretically esti-
mating efficiency is not a simple calculation. The sug-
gested empirical method is as follows:
(I )(α)(3k) = V
REF
BG
V
BG
α =
)
(I )(3k)
REF
Allowing the expression for RFB to be rewritten as:
V
+ V + I (ESR)
F SEC
OUT
R
= R
REF
FB
)
)
I
(3k)N
REF
SP
Build a prototype of the desired supply using the
eventual secondary components. Temporarily ground
the RCCOMP pin to disable the load compensation func-
tion. Operate the supply over the expected range of
output current loading while measuring the output
voltagedeviation.Approximatethisvariationasasingle
value of ROUT (straight line approximation). Calculate a
value for the K1 constant based on VIN, VOUT and the
measured (differential) efficiency. They are then com-
where,
= Desired output voltage
V
OUT
V = Switching diode forward voltage
F
(I )(ESR) = Secondary resistive losses
SEC
I
= Data sheet reference current value
REF
N
= Effective secondary-to-primary turns ratio
SP
bined with the data sheet typical value for (∆VRCCOMP
∆ISW ) to yield a value for ROCOMP
/
Strictlyspeaking,theaboveequationdefinesRFB notasan
absolute value, but as a ratio of RREF. So the next question
is, “What is the proper value for RREF?” The answer is that
RREF should be approximately 3k. This is because the
.
Verifythisresultbyconnectingaresistorofroughlythis
value from the ROCOMP pin to ground. (Disconnect the
ground short to RCCOMP and connect the requisite
0.1µF filter capacitor to ground.) Measure the output
impedancewiththenewcompensationinplace. Modify
the original ROCOMP value if necessary to increase or
decrease the effective compensation.
LT1425 is trimmed and specified using this value of RREF
.
If the impedance of RREF varies considerably from 3k,
additional errors will result. However, a variation in RREF
ofseveralpercentorsoisperfectlyacceptable. Thisyields
a bit of freedom in selecting standard 1% resistor values
to yield nominal RFB/RREF ratios.
Once the proper load compensation resistor has been
chosen, it may be necessary to adjust the value of the
RFB resistor. This is because the load compensation
system exhibits some nonlinearity. In particular, the
circuit can shift the reference current by a noticeable
SELECTING ROCOMP RESISTOR VALUE
The Operation section previously derived the following
expressionsforROUT, i.e., effectiveoutputimpedanceand
11
LT1425
U
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APPLICATIONS INFORMATION
amountwhenoutputswitchcurrentiszero.Pleaserefer
toFigure1whichshowsnominalreferencecurrentshift
at zero load for a range of ROCOMP values. Example: for
a load compensation resistor of 12k, the graph indi-
cates a 1.0% shift in reference current. The RFB resistor
value should be adjusted down by about 1.0% to
restore the original target output voltage.
integers, e.g., 1:1, 2:1, 3:2, etc. can be employed which
yield more freedom in setting total turns and mutual
inductance. Turns ratio can then be chosen on the basis of
desired duty cycle. However, remember that the input
supply voltage plus the secondary-to-primary referred
versionoftheflybackpulse(includingleakagespike)must
not exceed the allowed output switch breakdown rating.
2
1
0
Leakage Inductance
Transformer leakage inductance (on either the primary or
secondary) causes a spike after output switch turn-off.
This is increasingly prominent at higher load currents
where more stored energy must be dissipated. In many
cases a “snubber” circuit will be required to avoid over-
voltage breakdown at the output switch node. LTC’s
Application Note 19 is a good reference on snubber
design.
1
10
R
100
(kΩ)
1000
In situations where the flyback pulse extends beyond the
enable delay time, the output voltage regulation will be
affected to some degree. It is important to realize that the
feedback system has a deliberately limited input range,
roughly ±50mV referred to the RREF node, and this works
to the user’s advantage in rejecting large, i.e., higher
voltage leakage spikes. In other words, once a leakage
spike is several volts in amplitude, a further increase in
amplitude has little effect on the feedback system. So the
user is generally advised to arrange the snubber circuit to
clamp at as high a voltage as comfortably possible,
observing switch breakdown, such that leakage spike
duration is as short as possible.
OCOMP
1425 F01
Figure 1
In less critical applications, or when output current
remains relatively constant, the load compensation func-
tion may be deemed unnecessary. In such cases, a
reduced component solution may be obtained as follows:
Leave the ROCOMP node open (ROCOMP = ∞), and replace
the filter capacitor normally on the RCCOMP node with a
short to ground.
TRANSFORMER DESIGN CONSIDERATIONS
As a rough guide, total leakage inductances of several
percent (of mutual inductance) or less may require a
snubber, but exhibit little to no regulation error due to
leakage spike behavior. Inductances from several percent
up to perhaps ten percent cause increasing regulation
error.
Transformer specification and design is perhaps the most
critical part of applying the LT1425 successfully. In addi-
tion to the usual list of caveats dealing with high frequency
isolated power supply transformer design, the following
information should prove useful.
Severe leakage inductances in the double digit percentage
range should be avoided if at all possible as there is a
potential for abrupt loss of control at high load current.
This curious condition potentially occurs when the leak-
age spike becomes such a large portion of the flyback
waveform that the processing circuitry is fooled into
thinking that the leakage spike itself is the real flyback
Turns Ratio
Note that due to the use of an RFB/RREF resistor ratio to set
output voltage, the user has relative freedom in selecting
transformer turns ratio to suit a given application. In other
words, “screwball” turns ratios like “1.736:1.0” can scru-
pulously be avoided! In contrast, simpler ratios of small
12
LT1425
U
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APPLICATIONS INFORMATION
signal! It then reverts to a potentially stable state whereby
the top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This will typically reduce the output volt-
age abruptly to a fraction, perhaps between one-third to
two-thirds of its correct value. If load current is reduced
sufficiently, the system will snap back to normal opera-
tion. When using transformers with considerable leakage
inductance, it is important to exercise this worst-case
check for potential bistability:
degrades load regulation (at least before load compensa-
tion is employed).
Bifilar Winding
A bifilar or similar winding technique is a good way to
minimize troublesome leakage inductances. However,
remember that this will increase primary-to-secondary
capacitance and limit the primary-to-secondary break-
down voltage, so bifilar winding is not always practical.
Finally, the LTC Applications group is available to assist
in the choice and/or design of the transformer. Happy
Winding!
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short circuit the output.
OUTPUT VOLTAGE ERROR SOURCES
3. Observe that normal operation is restored.
Conventional nonisolated switching power supply ICs
typically have only two substantial sources of output
voltage error—the internal or external resistor divider
network that connects to VOUT and the internal IC refer-
ence.TheLT1425,whichsensestheoutputvoltageinboth
a dynamic and an isolated manner, exhibits additional
potential error sources to contend with. Some of these
errors are proportional to output voltage, others are fixed
in an absolute millivolt sense. Here is a list of possible
error sources and their effective contribution:
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This will usually be
evident by simultaneously monitoring the VSW waveform
on an oscilloscope to observe leakage spike behavior
firsthand. A final note, the susceptibility of the system to
bistable behavior is somewhat a function of the load I/V
characteristics. A load with resistive, i.e., I = V/R behavior
is the most susceptible to bistability. Loads which exhibit
“CMOSsy”, i.e., I = V2/R behavior are less susceptible.
Secondary Leakage Inductance
Internal Voltage Reference
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the second-
ary in particular exhibits an additional phenomenon. It
forms an inductive divider on the transformer secondary,
that reduces the size of the primary-referred flyback pulse
used for feedback. This will increase the output voltage
target by a similar percentage. Note that unlike leakage
spike behavior, this phenomenon is load independent. To
the extent that the secondary leakage inductance is a
constantpercentageofmutualinductance(overmanufac-
turingvariations), thiscanbeaccommodatedbyadjusting
the RFB/RREF resistor ratio.
The internal bandgap voltage reference is, of course,
imperfect. Its error, both at 25°C and over temperature is
already included in the specifications for Reference
Current.
User Programming Resistors
Output voltage is controlled by the ratio of RFB to RREF
.
Both are user supplied external resistors. To the extent
that the resistor ratio differs from the ideal value, the
output voltage will be proportionally affected.
Schottky Diode Drop
Winding Resistance Effects
The LT1425 senses the output voltage from the trans-
formerprimarysideduringtheflybackportionofthecycle.
This sensed voltage therefore includes the forward drop,
VF, of the rectifier (usually a Schottky diode). The nominal
Resistance in either the primary or secondary will act to
reduce overall efficiency (POUT/PIN). Resistance in the
secondary increases effective output impedance which
13
LT1425
U
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APPLICATIONS INFORMATION
VF of this diode should therefore be included in RFB
calculations. Lot-to-lot and ambient temperature varia-
tions will show up as output voltage shift/drift.
“collapse,” thereby supporting operation well into discon-
tinuous mode. Nevertheless, there still remain constraints
to ultimate low load operation. They relate tothe minimum
switchONtimeandtheminimumenabletime. Discontinu-
ous mode operation will be assumed in the following
theoretical derivations.
Secondary Leakage Inductance
Leakage inductance on the transformer secondary
reduces the effective primary-to-secondary turns ratio
(NP/NS) from its ideal value. This will increase the output
voltage target by a similar percentage. To the extent that
secondary leakage inductance is constant from part-to-
part, this can be accommodated by adjusting the RFB to
RREF resistor ratio.
As outlined in the Operation section, the LT1425 utilizes a
minimum output switch ON time, tON. This value can be
combined with expected VIN and switching frequency to
yield an expression for minimum delivered power.
1
f
2
Min Power =
(V • t )
IN ON
)
)
)
)
2 L
PRI
Output Impedance Error
= (V )(I
)
OUT OUT
An additional error source is caused by transformer sec-
ondary current flow through the real life nonzero imped-
ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the RFB value adjusted for nominal expected error. In
more demanding applications, output impedance error
may be minimized by the use of the load compensation
function (see Load Compensation).
This expression then yields a minimum output current
constraint:
f
1
2
I
=
(V • t )
IN ON
OUT(MIN)
)
)
)
)
(L )(V
)
2
PRI OUT
where,
f = Switching frequency (nominally 285kHz)
= Transformer primary side inductance
L
PRI
V = Input voltage
IN
V
= Output voltage
OUT
t
= Output switch minimum ON time
ON
VIN Sense Error
An additional constraint has to do with the minimum
enable time. The LT1425 derives its output voltage infor-
mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, tED, plus the
minimum enable time, tEN. Minimum power delivered to
the load is then:
The LT1425 determines the size of the flyback pulse by
comparing the VSW signal to VIN, through RFB. This
comparisonisnotperfect, inthesensethatanoffsetexists
between the sensing mechanism and the actual VIN. This
isexpressedinthedatasheetasVIN senseerror. Thiserror
isfixedinabsolutemillivolttermsrelativetoVOUT (withthe
exception that it is reflected to VOUT by any nonunity
secondary-to-primary turns ratio).
1
f
2
[V
• (t + t )]
EN ED
MINIMUM LOAD CONSIDERATIONS
Min Power =
OUT
)
)
)
)
2 L
SEC
The LT1425 generally provides better low load perfor-
mance than previous generation switcher/controllers
utilizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
= (V )(I
)
OUT OUT
which yields a minimum output constraint:
14
LT1425
U
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APPLICATIONS INFORMATION
f(V
L
)
minimum switch ON time, irrespective of current trip
point. If the duty cycle exhibited by this minimum ON time
is greater than the ratio of secondary winding voltage
(referred-to-primary) divided by input voltage, then peak
current will not be controlled at the nominal value, and will
cycle-by-cycle ratchet up to some higher level. Expressed
mathematically, the requirement to maintain short-circuit
control is:
1
OUT
SEC
2
I
=
(t + t )
ED EN
OUT(MIN)
)
)
)
)
2
where,
f = Switching frequency (nominally 285kHz)
L
V
t
t
= Transformer secondary side inductance
= Output voltage
= Enable delay time
SEC
OUT
ED
EN
= Minimum enable time
V + (I )(R )
SEC
F
SC
(t )(f) <
Note that generally, depending on the particulars of input
and output voltages and transformer inductance, one of
the above constraints will prove more restrictive. In other
words, the minimum load current in a particular applica-
tion will be either “output switch minimum ON time”
constrained,or “minimumflybackpulsetime”constrained.
(A final note—LPRI and LSEC refer to transformer induc-
tance as seen from the primary or secondary side respec-
tively. This general treatment allows these expressions to
be used when the transformer turns ratio is nonunity.)
ON
)
)
(V )(N )
IN
SP
where,
t
= Output switch minimum ON time
f = Switching frequency
= Short-circuit output current
V = Output diode forward voltage at I
= Resistance of transformer secondary
V = Input voltage
ON
I
SC
F
SC
R
SEC
IN
N
= Secondary-to-primary turns ratio
SP
(N /N
)
MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
SEC PRI
The LT1425 is a current mode controller. It uses the VC
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the VC
node, nominally 1.9V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit, which is
somewhat duty cycle dependent due to internal slope
compensation action.
Trouble will typically only be encountered in applications
with a relatively high product of input voltage times
secondary-to-primary turns ratio. Additionally, several
realworldeffectssuchastransformerleakageinductance,
AC winding losses and output switch voltage drop com-
bine to make this simple theoretical calculation a conser-
vative estimate. In cases where short-circuit protection is
mandatory and this theoretical calculation indicates cause
for concern, the prototype should be observed directly as
follows: short the output while observing the VSW signal
with an oscilloscope. The measured output switch ON
time can then be compared against the specifications for
minimum tON.
Short-circuit conditions are handled by the same mecha-
nism. The output switch turns on, peak current is quickly
reached and the switch is turned off. Because the output
switchisonlyonforasmallfractionoftheavailableperiod,
internal power dissipation is controlled. (The LT1425
contains an internal overtemperature shutdown circuit,
that disables switch action, just in case.)
THERMAL CONSIDERATIONS
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. The narrow 16-pin package is rated
at 75°C/W.
While the majority of users will not experience a problem,
thereishowever, apossibilityoflossofcurrentlimitunder
certain conditions. Remember that the LT1425 exhibits a
15
LT1425
U
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APPLICATIONS INFORMATION
Average supply current (including driver current) is:
nextcycle.ThisactionnaturallyholdstheVC voltagestable
duringthecurrentcomparatorsenseaction(currentmode
switching).
I
35
SW
I = 7mA + DC
IN
)
)
where,
PCB LAYOUT CONSIDERATIONS
I
= Switch current
DC = On switch duty cycle
SW
For maximum efficiency, switch rise and fall times are
made as short as practical. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the IC is essential, especially the
power paths (primary and secondary). B field (magnetic)
radiation is minimized bykeepingoutput diode, switch pin
and output bypass capacitor leads as short as possible. E
field radiation is kept low by minimizing the length and
area of all traces connected to the switch pin. A ground
plane should always be used under the switcher circuitry
to prevent interplane coupling.
Switch power dissipation is given by:
PSW = (ISW)2(RSW)(DC)
R
SW = Output switch ON resistance
Total power dissipation of the die is the sum of supply
current times supply voltage plus switch power:
PD(TOTAL) = (IIN • VIN) + PSW
The high speed switching current paths are shown sche-
matically in Figure 2. Minimum lead length in these paths
are essential to ensure clean switching and minimal EMI.
The path containing the input capacitor, transformer pri-
mary, output switch, the path containing the transformer
secondary, output diode and output capacitor are the only
ones containing nanosecond rise and fall times. Keep
these paths as short as possible.
FREQUENCY COMPENSATION
Loop frequency compensation is performed by connect-
ing a capacitor from the output of the error amplifier (VC
pin) to ground. An additional series resistor, often
required in traditional current mode switcher controllers
is usually not required, and can even prove detrimental.
The phase margin improvement traditionally offered by
this extra resistor will usually be already accomplished by
the nonzero secondary circuit impedance, which adds a
“zero” to the loop response.
V
OUT
•
HIGH
FREQUENCY
CIRCULATING
PATH
ISOLATED
LOAD
HIGH
FREQUENCY
CIRCULATING
PATH
V
•
In further contrast to traditional current mode switchers,
VC pinrippleisgenerallynotanissuewiththeLT1425. The
dynamic nature of the clamped feedback amplifier forms
an effective track/hold type response, whereby the VC
voltage changes during the flyback pulse, but is then
“held” during the subsequent “switch ON” portion of the
IN
F
1425 F02
Figure 2
16
LT1425
U
TYPICAL APPLICATIONS
maximum input voltage, so a bootstrap winding is used.
D1, D2, Q2 and Q3 and associated components for the
necessary start-up circuitry with hysteresis. When C1
charges to 15V, switching begins and the bootstrap wind-
ing begins to supply power before C1 has a chance to
discharge to 11V. Feedback voltage is fed directly through
a resistor divider to the RREF pin. The load compensation
circuitry is bypassed, resulting in ±5% load regulation.
The following are several application examples of the
LT1425. The first shows an isolated LAN supply which
provides –9V with ±1% load regulation for output cur-
rents of 0mA to 250mA. An alternate transformer, the
Coiltronics part, provides a complete PCMCIA Type II
height solution. The LT1425 offers excellent load regula-
tion and fast dynamic response not found in similar
isolated flyback schemes.
Finally, the “12V to 5V Isolated Converter” is similar to the
previous example in that a cascoded MOSFET is used to
prevent voltage breakdown of the output switch. But
because the nominal 12V input is well within the range of
the VIN pin, no bootstrap winding is required and normal
load compensation function is provided. Diode D1, tran-
sistor Q1 and associated components provide an under-
voltage lockout function via the SHDN pin. The off-the-
shelf transformer provides up to 5W of isolated regulated
power.
The next example shows a ±15V supply with 1.5kV of
isolation. The sum of line/load/cross regulation is better
than ±3%. Full load efficiency is between 72% (VIN = 5V)
and 80% (VIN = 15V). The isolation is ultimately limited
only by bobbin selection and transformer construction.
The “–48V to 5V Isolated Telecom Supply” uses an
external cascoded 200V MOSFET to extend the LT1425’s
35V maximum switch voltage limit. The input voltage
range (–36V to –72V) also exceeds the LT1425’s 20V
–9V Isolated LAN Supply
C6
R2
5V
C1
LT1425
R
10µF
25V
0.1µF
D1
MBRS130LT3
7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C2
10µF
25V
R1
OUT
GND
NC
GND
22.1k
1%
COM
SHDN
T1
C5
2
1
3
R
C3
C4
FB
OCOMP
1.8k
10µF
10µF
V
C
R
CCOMP
D2
25V
25V
R3
R
V
IN
REF
4
6
3.01k
1%
–9V
SYNC
SGND
GND
V
SW
100k
47pF
PGND
C1, C2, C3, C4 = MARCON THCS50E1E106Z CERAMIC
CAPACITOR, SIZE 1812. (847) 696-2000
0.1µF
1000pF
GND
INPUT
COM
1424/25 TA03
Transformer T1
LPRI
RATIO
ISOLATION
(L × W × H)
10.7 × 11.5 × 6.3mm 250mA
14 × 14 × 2.2mm 200mA
I
EFFICIENCY
D1
D2
R1, R2
C5, C6
R3
OUT
DALE
LPE-4841-A307
36µH
27µH
1:1:1
1:1
500VAC
500VAC
76%
70%
NOT USED
1N5248
NOT USED
47Ω
75Ω
330pF
220pF
13.3k
5.9k
COILTRONICS
CTX02-13483
MBR0540TL1
17
LT1425
U
TYPICAL APPLICATIONS
±15V Isolated Power Supply
330pF
130Ω
MBRS1100T3
T1*
5V TO
15V
15V
60mA
1
8
+
35V
15µF
1µF
3k
+
35V
22µF
75Ω
LT1425
1N759
OUT
COM
2
3
1
16
GND
7
6
GND
18.4k
0.1%
MBRS1100T3
2
3
4
5
6
7
8
15
NC
R
SHDN
0.1µF
MBR0540LT1
14
13
12
11
10
9
R
R
OCOMP
CCOMP
FB
220pF
+
15µF
35V
V
C
3k
4
5
R
V
IN
REF
1000pF
–15V
60mA
SYNC
SGND
GND
V
SW
1425 TA04
7.32k
1%
PGND
3.01k
1%
GND
*PHILIPS EFD-15-3F3 CORE
GAP FOR PRIMARY
L = 40µH
0.1µF
INPUT
COM
PIN 3 TO 4, 7 TURNS BIFILAR 34AWG
3 LAYERS 2 MIL
POLYESTER FILM
PIN 7 TO 8, 28 TURNS 40AWG
PIN 5 TO 6, 28 TURNS 40AWG
PIN 1 TO 2, 7 TURNS BIFILAR 34AWG
0.12 INCH MARGIN TAPE
–48V to 5V Isolated Telecom Supply
470pF
18Ω
MBR745
T1*
8
1
2
INPUT
COM
5V
2A
BAV21
5
R1
24k
50Ω
1W
T1
510Ω
+
+
LT1425
BAV21
1
3.3µF
R2
18Ω
150µF
6.3V
150µF
6.3V
16
15
14
13
12
11
10
9
3
4
GND
NC
GND
2
3
4
5
6
7
8
6
150pF
SHDN
0.1µF
30.1k
1%
C1
+
7
OUT
COM
R
R
R
OCOMP
CCOMP
FB
27µF
35V
V
C
10Ω
Q1
IRF620
R
V
IN
REF
D1
7.5V
1N755
SYNC
SGND
GND
V
SW
3.16k
1%
MUR120
PGND
GND
1000pF
–36V TO
–72V
2.4k
Q2
2N3906
Q3
2N3904
D2
7.5V
1N755
5k
*PHILIPS EFD-15-3F3 CORE
GAP FOR PRIMARY
L = 100µH
100k
10k
0.1µF
1425 TA06
PIN 3 TO 4, 15 TURNS BIFILAR 31AWG
PIN 7 TO 8, 6 TURNS QUADFILAR 29AWG
PIN 5 TO 6, 15 TURNS BIFILAR 33AWG
PIN 1 TO 2, 15 TURNS BIFILAR 31AWG
2 LAYERS 2 MIL
POLYESTER FILM
1 LAYER 2 MIL
POLYESTER FILM
18
LT1425
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
16
15
14
13
12
11
10
9
0.150 – 0.157**
0.228 – 0.244
(3.810 – 3.988)
(5.791 – 6.197)
5
7
8
1
2
3
4
6
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
S16 0695
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT1425
U
TYPICAL APPLICATION
12V to 5V Isolated Converter
330pF
100Ω
MBRS340T3
8 9
4
3
7
5V
1A
12V
+
1
5
22µF
35V
2.4k
D1
1N755
7.5V
LT1425
+
+
220µF
10V
220µF
10V
200Ω
1
2
3
4
5
6
7
8
16
GND
GND
NC
25.5k
1%
0.1µF
15
SHDN
14
2
6
10 11 12
OUT
COM
R
R
R
OCOMP
FB
13
V
C
CCOMP
10Ω
12
MMFT1N10E
R
V
IN
REF
11
10
9
1000pF
COILTRONICS
VP1-0190
SYNC
SGND
GND
V
SW
MUR120
9.3k
PGND
TURNS RATIO 1 : 1 : 1 : 1 : 1 : 1
12µH PER WINDING
407-241-7876
3.01k
1%
GND
0.1µF
1%
INPUT
COM
1425 TA05
1.8k
Q1
2N3906
1000pF
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Off-Line Switching Regulator
Built-In Isolated Regulation Without Optoisolator
Up to 200kbps Data Rate, UL Listed
Isolated Flyback Mode for Higher Currents
Uses Ultrasmall Magnetics
LTC®1145/46
LT1170/71/72
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LT1424
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5A/3A/1.25A Flyback Regulators
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Application Specific Isolated Regulator
8-Pin Fixed Voltage Version of LT1425
1425fa LT/TP 1198 2K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1997
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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