LT3412AEUF#TR [Linear]
IC 3 A SWITCHING REGULATOR, 4 kHz SWITCHING FREQ-MAX, PQCC16, 4 X 4 MM, PLASTIC, QFN-16, Switching Regulator or Controller;
| 型号： | LT3412AEUF#TR |
| 厂家： | 
Linear |
| 描述： | IC 3 A SWITCHING REGULATOR, 4 kHz SWITCHING FREQ-MAX, PQCC16, 4 X 4 MM, PLASTIC, QFN-16, Switching Regulator or Controller 开关 |
| 文件： | 总20页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3412A
3A, 4MHz, Monolithic
Synchronous Step-Down Regulator
U
DESCRIPTIO
FEATURES
The LTC®3412A is a high efficiency monolithic synchro-
nous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.25V to 5.5V and provides a
regulated output voltage from 0.8V to 5V while delivering
up to 3A of output current. The internal synchronous
power switch with 77mΩ on-resistance increases effi-
ciency and eliminates the need for an external Schottky
diode. Switchingfrequencyissetbyanexternalresistoror
can be synchronized to an external clock. 100% duty cycle
provides low dropout operation extending battery life in
portable systems. OPTI-LOOP® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
■
High Efficiency: Up to 95%
3A Output Current
■
■
Low Quiescent Current: 64μA
■
Low RDS(ON) Internal Switch: 77mΩ
■
2.25V to 5.5V Input Voltage Range
■
Programmable Frequency: 300KHz to 4MHz
2% Output Voltage Accuracy
0.8V Reference Allows Low Output Voltage
Selectable Forced Continuous/Burst Mode®operation
with Adjustable Burst Clamp
■
■
■
■
■
■
■
■
Synchronizable Switching Frequency
Low Dropout Operation: 100% Duty Cycle
Power Good Output Voltage Monitor
Overtemperature Protected
Available in 16-Lead Exposed Pad TSSOP and QFN
Packages
The LTC3412A can be configured for either Burst Mode
operationorforcedcontinuousoperation.Forcedcontinu-
ous operation reduces noise and RF interference while
Burst Mode operation provides high efficiency by reduc-
ing gate charge losses at light loads. In Burst Mode
operation, external control of the burst clamp level allows
the output voltage ripple to be adjusted according to the
application requirements.
U
APPLICATIO S
■
Point-of-Load Regulation
Notebook Computers
Portable Instruments
Distributed Power Systems
■
■
■
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466,
6611131, 6724174.
U
TYPICAL APPLICATIO
22μF
Efficiency and Power Loss
V
IN
3.3V
100
95
90
85
80
75
70
65
60
55
50
100000
10000
1000
100
PV SV
IN
EFFICIENCY
IN
RT
2.2M
PGOOD
LTC3412A
0.47μH
294k
V
OUT
SW
2.5V AT 3A
C
OUT
RUN/SS
PGND
100μF
×2
12.1k
1000pF
I
SGND
V
FB
TH
SYNC/MODE
POWER LOSS
820pF
10
69.8k
392k
115k
3412A F01a
1
0.01
0.1
1
10
LOAD CURRENT (A)
Figure 1. 2.5V/3A Step-Down Regulator
3412afb
1
LTC3412A
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Input Supply Voltage ...................................–0.3V to 6V
ITH, RUN/SS, VFB, PGOOD,
SYNC/MODE Voltages .................................. –0.3 to VIN
SW Voltages ................................. –0.3V to (VIN + 0.3V)
Operating Ambient Temperature Range
(Note 2) .............................................. –40°C to 85°C
Junction Temperature (Note 5)............................. 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
U
U
PI CO FIGURATIO
TOP VIEW
TOP VIEW
1
PV
IN
16
15
14
13
12
11
10
9
SV
IN
2
SW
PGOOD
16 15 14 13
3
SW
I
TH
RUN/SS
SGND
1
2
3
4
12 PGOOD
4
5
6
7
8
PGND
PGND
SW
V
FB
17
11 SV
IN
IN
17
R
T
PV
IN
PV
10
9
SYNC/MODE
RUN/SS
SW
SW
SW
5
6
7
8
PV
IN
SGND
FE PACKAGE
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W, θJC = 1°C/W
16-LEAD PLASTIC TSSOP
EXPOSED PAD IS SGND (PIN 17) MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE CONNECTED TO PCB
U
W
U
ORDER I FOR ATIO
LEAD FREE FINISH
LT3412AEFE#PBF
LT3412AIFE#PBF
LT3412AEUF#PBF
LEAD BASED FINISH
LT3412AEFE
TAPE AND REEL
LT3412AEFE#TRPBF
LT3412AIFE#TRPBF
LT3412AEUF#TRPBF
TAPE AND REEL
LT3412AEFE#TR
LT3412AIFE#TR
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
3412AEFE
3412AIFE
3412A
PART MARKING
3412AEFE
3412AIFE
3412A
16-Lead Plastic TSSOP
16-Lead Plastic TSSOP
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
16-Lead (4mm x 4mm) Plastic QFN
PACKAGE DESCRIPTION
16-Lead Plastic TSSOP
LT3412AIFE
LT3412AEUF
16-Lead Plastic TSSOP
16-Lead (4mm x 4mm) Plastic QFN
LT3412AEUF#TR
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3412afb
2
LTC3412A
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
SV
PARAMETER
CONDITIONS
MIN
2.25
TYP
MAX
5.5
UNITS
V
Signal Input Voltage Range
Regulated Feedback Voltage
Voltage Feedback Leakage Current
Reference Voltage Line Regulation
Output Voltage Load Regulation
IN
V
I
(Note 3)
●
●
0.784
0.800
0.1
0.816
0.2
V
FB
μA
%/V
FB
ΔV
FB
V
= 2.7V to 5.5V (Note 3)
IN
0.04
0.2
V
Measured in Servo Loop, V = 0.36V
Measured in Servo Loop, V = 0.84V
●
●
0.02
–0.02
0.2
–0.2
%
%
LOADREG
ITH
ITH
ΔV
PGOOD
Power Good Range
7.5
9
%
R
PGOOD
Power Good Pull-Down Resistance
120
200
Ω
I
Input DC Bias Current
Active Current
Sleep
(Note 4)
Q
V
V
V
= 0.78V, V = 1V
250
64
0.02
330
80
1
μA
μA
μA
FB
FB
RUN
ITH
= 1V, V = 0V
ITH
Shutdown
= 0V, V
= 0V
MODE
f
f
Switching Frequency
R
= 294kΩ
0.88
0.3
1
1.1
4
MHz
MHz
OSC
OSC
Switching Frequency Range
(Note 6)
SYNC Capture Range
(Note 6)
0.3
4
MHz
mΩ
mΩ
A
SYNC
R
R
R
R
of P-Channel FET
of N-Channel FET
I
I
= 1A (Note 7)
77
65
6
110
90
PFET
NFET
DS(ON)
DS(ON)
SW
SW
= –1A (Note 7)
I
Peak Current Limit
4.5
LIMIT
V
I
Undervoltage Lockout Threshold
SW Leakage Current
RUN Threshold
1.75
2
2.25
1
V
UVLO
V
= 0V, V = 5.5V
0.1
0.65
μA
V
LSW
RUN
IN
V
0.5
0.8
1
RUN
RUN
I
RUN/SS Leakage Current
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LTC3412A is tested in a feedback loop that adjusts V to
FB
achieve a specified error amplifier output voltage (I ).
TH
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 2: The LTC3412AE is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3412I is guaranteed to meet
specified performance over the full –40°C to 85°C operating temperature
range.
Note 5: T is calculated from the ambient temperature T and power
J
A
dissipation as follows: LTC3412AFE: T = T + P (38°C/W)
J
A
D
LTC3412AEUF: T = T + P (34°C/W)
J
A
D
Note 6: 4MHz operation is guaranteed by design and not production tested.
Note 7: Switch on resistance is guaranteed by design and test condition in
the UF package and by final test correlation in the FE package.
3412afb
3
LTC3412A
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current, Burst
Mode Operation
Efficiency vs Load Current,
Forced Continuous Operation
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
V
= 3.3V
V
= 3.3V
IN
IN
Burst Mode
OPERATION
V
= 5V
V
= 5V
IN
IN
FORCED
CONTINUOUS
V
V
= 3.3V
IN
OUT
V
= 2.5V
V
OUT
= 2.5V
= 2.5V
OUT
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
0.01
0.1
1
10
0.01
0.1
1
10
0.01
0.1
1 10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
3412A GO1
3412A GO2
3412A GO3
Load Regulation
Efficiency vs Input Voltage
Efficiency vs Frequency
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
94
92
90
88
86
84
82
80
96
95
94
93
92
91
90
89
88
87
FIGURE 4 CIRCUIT
= 3.3V
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
= 3.3V
V
IN
V
IN
1μH
0.22μH
0.47μH
1A
0.1A
3A
3.0
3.5
INPUT VOLTAGE (V)
4.5
5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
2.5
4.0
0
0.5
1.5 2.0 2.5 3.0
FREQUENCY (MHz)
4.0
1.0
3.5
LOAD CURRENT (A)
3412A GO6
3412A GO4
3412A GO5
Load Step Transient Burst Mode
Operation
Burst Mode Operation
Output Voltage Ripple
BURST
MODE
20mV/DIV
V
OUT
20mV/DIV
V
OUT
100mV/DIV
PULSE
SKIPPING
20mV/DIV
INDUCTOR
CURRENT
1A/DIV
FORCED
CONTINUOUS
20mV/DIV
INDUCTOR
CURRENT
2A/DIV
FIGURE 4 CIRCUIT
V
V
= 3.3V
V
V
= 3.3V
5μs/DIV
5μs/DIV
40μs/DIV
IN
OUT
IN
OUT
= 2.5V
= 2.5V
FIGURE 4 CIRCUIT
F = 1MHz
3412A GO7
3412A GO8
3412A GO9
LOAD STEP = 50mA TO 2A
FIGURE 4 CIRCUIT
3412afb
4
LTC3412A
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Load Step Transient Forced
Continuous
Start-Up Transient
VREF vs Temperature
0.7975
0.7970
0.7965
0.7960
0.7955
0.7950
0.7945
0.7940
0.7935
0.7930
V
= 3.3V
IN
V
OUT
2V/DIV
V
OUT
100mV/DIV
RUN/SS
2V/DIV
INDUCTOR
CURRENT
2A/DIV
INDUCTOR
CURRENT
2A/DIV
115
–45 –25
15 35 55
TEMPERATURE (°C)
95
V
V
= 3.3V
OUT
F = 1MHz
40μs/DIV
V
V
= 3.3V
1ms/DIV
–5
75
IN
IN
=2.5V
=2.5V
OUT
LOAD STEP = 2A
3412A G10
3412A G11
3412A G12
LOAD STEP = 0A TO 3A
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT
Switch Leakage Current vs
Input Voltage
Switch On-Resistance vs
Temperature
Switch On-Resistance vs
Input Voltage
50
100
95
90
85
80
75
70
65
60
55
50
120
100
80
60
40
20
0
V
= 3.3V
IN
45
40
35
30
25
20
15
10
5
PFET
NFET
PFET
NFET
PFET
NFET
4.5 5.0
INPUT VOLTAGE (V)
0
2.5
3.0
4.0
5.5
3.5
–40
40
TEMPERATURE (°C)
80 100
120
– 20
0
20
60
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
3412A G15
3412A G14
3412A G13
Frequency vs ROSC
Frequency vs Input Voltage
Frequency vs Temperature
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
1060
1050
1040
1030
1020
1010
1000
990
1020
1015
1010
1005
1000
995
V
= 3.3V
OSC
V
IN
= 3.3V
R
OSC
= 294k
IN
R
= 294k
990
985
980
975
0
970
2.5
3.0
3.5
4.0
4.5
5.0
5.5
40 140 240 340 440 540 640 740 840 940
(kΩ)
–40
40
TEMPERATURE (°C)
80 100
120
–20
0
20
60
INPUT VOLTAGE (V)
R
OSC
3412A G17
3412A G16
3412A G18
3412afb
5
LTC3412A
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current vs
Temperature
Minimum Peak Inductor Current
vs Burst Clamp Voltage
Quiescent Current vs
Input Voltage
350
300
250
200
150
100
50
350
300
250
200
150
100
50
4000
3500
3000
2500
2000
1500
1000
500
V
IN
= 3.3V
ACTIVE
ACTIVE
SLEEP
80
SLEEP
0
0
0
0.6
–20
0
20 40 60
100 120
0.1
0.2
0.3
0.4
0.5
0.7
–40
2.5
3.5
4.0
4.5
5.0
5.5
3.0
V
(V)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
BURST
3412A G21
3412A G20
3412A G19
Peak Current vs Input Voltage
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
4.75
2.25
2.75
3.25
3.75
4.25
INPUT VOLTAGE (V)
3412A G22
3412afb
6
LTC3412A
U
U
U
PI FU CTIO S
(FE Package/UHF Package)
RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input.
Forcing this pin below 0.5V shuts down the LTC3412A. In
shutdown all functions are disabled drawing < 1μA of
supplycurrent.Acapacitortogroundfromthispinsetsthe
ramp time to full output current.
SVIN (Pin 1/Pin 11): Signal Input Supply. Decouple this
pin to SGND with a capacitor.
PGOOD (Pin 2/Pin 12): Power Good Output. Open-drain
logic output that is pulled to ground when the output
voltage is not within 7.5% of regulation point.
SGND (Pin 8/Pin 2): Signal Ground. All small-signal
components,compensationcomponentsandtheexposed
pad on the bottom side of the IC should connect to this
ground, which in turn connects to PGND at one point.
ITH (Pin 3/Pin 13): Error Amplifier Compensation Point.
The current comparator threshold increases with this
control voltage. Nominal voltage range for this pin is from
0.2V to 1.4V with 0.4V corresponding to the zero-sense
voltage (zero current).
PVIN(Pins9,16/Pins3,10):PowerInputSupply.Decouple
this pin to PGND with a capacitor.
V
FB (Pin 4/Pin 14): Feedback Pin. Receives the feedback
SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node
ConnectiontotheInductor.Thispinconnectstothedrains
of the internal main and synchronous power MOSFET
switches.
voltage from a resistive divider connected across the
output.
RT (Pin 5/Pin 15): Oscillator Resistor Input. Connecting a
resistor to ground from this pin sets the switching fre-
quency.
PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect
this pin close to the (–) terminal of CIN and COUT
.
SYNC/MODE (Pin 6/Pin 16): Mode Select and External
ClockSynchronizationInput. Toselectforcedcontinuous,
tietoSVIN.Connectingthispintoavoltagebetween0Vand
1V selects Burst Mode operation with the burst clamp set
to the pin voltage.
Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be
soldered to PCB for electrical connection and rated ther-
mal performance.
3412afb
7
LTC3412A
U
U
W
FUNCTIONAL BLOCK DIAGRA
PV
IN
SV
SGND
8
I
TH
3
IN
1
9
16
SLOPE
COMPENSATION
RECOVERY
PMOS CURRENT
COMPARATOR
VOLTAGE
REFERENCE
0.8V
BCLAMP
+
–
+
–
–
+
P-CH
4
V
FB
ERROR
AMPLIFIER
BURST
COMPARATOR
+
–
SYNC/MODE
+
–
0.74V
10
SLOPE
11
14
15
COMPENSATION
OSCILLATOR
SW
+
–
RUN/SS
PGOOD
7
2
RUN
0.86V
N-CH
LOGIC
+
–
NMOS
CURRENT
COMPARATOR
–
+
REVERSE
CURRENT
COMPARATOR
12
13
PGND
5
6
3412 FBD
R
SYNC/MODE
T
U
OPERATIO
Main Control Loop
the ITH pin by comparing the feedback signal from a
resistor divider on the VFB pin with an internal 0.8V
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the ITH voltage until the average
inductor current matches the new load current. When the
top power MOSFET shuts off, the synchronous power
switch (N-channel MOSFET) turns on until either the
bottomcurrentlimitisreachedorthebeginningofthenext
clock cycle. The bottom current limit is set at –1.3A for
forcedcontinuousmodeand0AforBurstModeoperation.
The LTC3412A is a monolithic, constant-frequency, cur-
rent-mode step-down DC/DC converter. During normal
operation, the internal top power switch (P-channel
MOSFET)isturnedonatthebeginningofeachclockcycle.
Current in the inductor increases until the current com-
parator trips and turns off the top power MOSFET. The
peak inductor current at which the current comparator
shuts off the top power switch is controlled by the voltage
on the ITH pin. The error amplifier adjusts the voltage on
3412afb
8
LTC3412A
U
OPERATIO
The operating frequency is externally set by an external
resistor connected between the RT pin and ground. The
practical switching frequency can range from 300kHz to
4MHz.
switched back on. This process repeats at a rate that is
dependent on the load demand.
Pulse Skipping operation is implemented by connecting
the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
peak inductor current will be determined by the voltage on
theITH pinuntiltheITH voltagedropsbelow400mV. Atthis
point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by 7.5%. In an overvoltage condition, the top
powerMOSFETisturnedoffandthebottompowerMOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to SVIN will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation, but may be desirable
in some applications where it is necessary to keep switch-
ing harmonics out of a signal band. The output voltage
ripple is minimized in this mode.
Frequency Synchronization
The internal oscillator of the LTC3412A can be synchro-
nized to an external clock connected to the SYNC/MODE
pin. Thefrequencyoftheexternalclockcanbeintherange
of 300kHz to 4MHz. For this application, the oscillator
timing resistor should be chosen to correspond to a
frequency that is 25% lower than the synchronization
frequency. During synchronization, the burst clamp is set
to 0V, and each switching cycle begins at the falling edge
of the clock signal.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage in the range
of 0V to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermit-
tently at light loads. This increases efficiency by minimiz-
ing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the ITH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the ITH pin drops. As the ITH voltage falls
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top power MOSFET is
held off and the ITH pin is disconnected from the output of
the error amplifier. The majority of the internal circuitry is
also turned off to reduce the quiescent current to 64μA
while the load current is solely supplied by the output
capacitor. When the output voltage drops, the ITH pin is
reconnectedtotheoutputoftheerroramplifierandthetop
power MOSFET along with all the internal circuitry is
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle eventually reaching 100% duty cycle. The output
voltage will then be determined by the input voltage minus
the voltage drop across the internal P-channel MOSFET
and the inductor.
Low Supply Operation
The LTC3412A is designed to operate down to an input
supply voltage of 2.25V. One important consideration
at low input supply voltages is that the RDS(ON) of the
P-channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3412A is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
3412afb
9
LTC3412A
W U U
U
APPLICATIO S I FOR ATIO
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3412A imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns; therefore, the minimum duty cycle is
equal to 100 • 110ns • f(Hz).
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3412A, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN or VOUT and
decreases with higher inductance.
⎛
⎞
VOUT
fL
⎛
VOUT
V ⎠
IN
⎞
⎟
ΔIL =
1–
⎜
⎝
⎜
⎝
⎟
⎠
Short-Circuit Protection
Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors, and
the output voltage ripple. Highest efficiency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
A reasonable starting point for selecting the ripple current
is ΔIL = 0.4(IMAX). The largest ripple current occurs at the
highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
Whentheoutputisshortedtoground,theinductorcurrent
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 4.4A, the top
powerMOSFETwillbeheldoffandswitchingcycleswillbe
skipped until the inductor current is reduced.
The basic LTC3412A application circuit is shown
in Figure 1. External component selection is determined
by the maximum load current and begins with the selec-
tion of the operating frequency and inductor value fol-
⎛
⎞ ⎛
⎟ ⎜
⎞
VOUT
fΔI
VOUT
L =
1–
lowed by CIN and COUT
.
⎜
⎟
V
⎝
L(MAX) ⎠ ⎝
⎠
IN(MAX)
Operating Frequency
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
the burst clamp. Lower inductor values result in higher
ripple current which causes this to occur at lower load
currents. This causes a dip in efficiency in the upper range
of low current operation. In Burst Mode operation, lower
inductance values will cause the burst frequency to in-
crease.
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3412A is determined
by an external resistor that is connected between pin RT
andground.Thevalueoftheresistorsetstherampcurrent
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance re-
quires more turns of wire and therefore copper losses will
3.08 •1011
ROSC
=
Ω – 10kΩ
( )
f
increase.
3412afb
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LTC3412A
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APPLICATIO S I FOR ATIO
U
Ferritedesignshaveverylowcorelossesandarepreferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy mate-
rials are small and don’t radiate much energy, but gener-
ally cost more than powdered iron core inductors with
similar characteristics. The choice of which style inductor
to use mainly depends on the price verus size require-
ments and any radiated field/EMI requirements. New
designs for surface mount inductors are available from
Coiltronics, Coilcraft, Toko, and Sumida.
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple, ΔVOUT, is determined by:
⎛
⎞
1
ΔVOUT ≤ ΔIL ESR +
⎜
⎟
⎠
8fCOUT
⎝
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors
placedinparallelmaybeneededtomeettheESRandRMS
currenthandlingrequirements.Drytantalum,specialpoly-
mer, aluminum electrolytic, and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capaci-
tors have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoi-
dal wave current at the source of the top MOSFET. To
preventlargevoltagetransientsfromoccurring,alowESR
input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
Using Ceramic Input and Output Capacitors
VOUT
V
IN
V
IN
VOUT
IRMS = IOUT(MAX)
– 1
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
thepowerissuppliedbyawalladapterthroughlongwires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design. For low input voltage applications, sufficient
bulk input capacitance is needed to minimize transient
effects during output load changes.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients as well as the amount of
bulk capacitance that is necessary to ensure that the
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LTC3412A
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APPLICATIO S I FOR ATIO
Output Voltage Programming
IBURST is determined by the desired amount of output
voltage ripple. As the value of IBURST increases, the sleep
period between pulses and the output voltage ripple in-
crease. The burst clamp voltage, VBURST, can be set by a
resistordividerfromtheVFB pintotheSGNDpinasshown
in Figure 1.
The output voltage is set by an external resistive divider
according to the following equation:
R2
R1
⎛
⎝
⎞
⎟
⎠
VOUT = 0.8V 1+
⎜
Pulse skipping, which is a compromise between low
output voltage ripple and efficiency, can be implemented
byconnectingpinSYNC/MODEtoground.ThissetsIBURST
to0A. Inthiscondition, thepeakinductorcurrentislimited
by the minimum on-time of the current comparator. The
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
The resistive divider allows pin VFB to sense a fraction of
the output voltage as shown in Figure 2.
V
OUT
R2
V
FB
LTC3412A
SGND
R1
3412A F02
Frequency Synchronization
Figure 2. Setting the Output Voltage
TheLTC3412A’sinternaloscillatorcanbesynchronizedto
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
externalfrequencysource.Thesynchronizationfrequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set
by the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external
frequency should be set 25% higher than the frequency
set by the external resistor to ensure that adequate slope
compensation is present.
Burst Clamp Programming
IfthevoltageontheSYNC/MODEpinislessthanVIN by1V,
Burst Mode operation is enabled. During Burst Mode
Operation, the voltage on the SYNC/MODE pin determines
the burst clamp level, which sets the minimum peak
inductor current, IBURST. To select the burst clamp level,
use the graph of Minimum Peak Inductor Current vs Burst
Clamp Voltage in the Typical Performance Characteristics
section.
VBURST is the voltage on the SYNC/MODE pin. IBURST can
only be programmed in the range of 0A to 6A. For values
of VBURST greater than 1V, IBURST is set at 6A. For values
of VBURST less than 0.4V, IBURST is set at 0A. As the output
load current drops, the peak inductor currents decrease to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than IBURST, the burst clamp will force the peak inductor
current to remain equal to IBURST regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the ITH pin will decrease. When the ITH voltage drops
to 150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3412A as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412A in a low
quiescent current shutdown state (IQ < 1μA).
The LTC3412A contains an internal soft-start clamp that
gradually raises the clamp on ITH after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on ITH after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on ITH can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
⎛
⎜
V
⎞
⎟
IN
tSS = RSS CSS ln
(SECONDS)
⎝ V – 1.8V⎠
IN
3412afb
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LTC3412A
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APPLICATIO S I FOR ATIO
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
U
curves. To obtain I2R losses, simply add RSW to RL and
multiply the result by the square of the average output
current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Efficiency = 100% – (L1 + L2 + L3 + ...)
Thermal Considerations
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
In most applications, the LTC3412A does not dissipate
much heat due to its high efficiency.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: VIN quiescent current and I2R losses.
However, in applications where the LTC3412A is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
150°C, both power switches will be turned off and the SW
node will become high impedance.
The VIN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
To avoid the LTC3412A from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
1. The VIN quiescent current is due to two components:
theDCbiascurrentasgivenintheelectricalcharacteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current out
of VIN that is typically larger than the DC bias current. In
continuous mode, IGATECHG = f(QT + QB) where QT and QB
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to VIN; thus, their effects will be more pro-
nounced at higher supply voltages.
tr = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature. For the 16-lead exposed TSSOP
package, the θJA is 38°C/W. For the 16-lead QFN package
the θJA is 34°C/W.
The junction temperature, TJ, is given by:
TJ = TA + tr
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In con-
tinuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
where TA is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (RDS(ON)).
To maximize the thermal performance of the LTC3412A,
the exposed pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current.
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
3412afb
13
LTC3412A
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APPLICATIO S I FOR ATIO
When a load step occurs, VOUT immediately shifts by an
Decoupling the PVIN and SVIN pins with two 22μF capaci-
tors is adequate for most applications.
amount equal to ΔI
, where ESR is the effective
LOAD(ESR)
series resistance of COUT. ΔILOAD also begins to charge or
dischargeCOUT generatingafeedbackerrorsignalusedby
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The ITH pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2, and R3. The
voltage on pin MODE will be set to 0.50V by the resistor
divider consisting of R2 and R3. According to the graph of
Minimum Peak Inductor Current vs Burst Clamp Voltage
intheTypicalPerformanceCharacteristicssection,aburst
clamp voltage of 0.5V will set the minimum inductor
current, IBURST, to approximately 1.1A.
Design Example
If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
As a design example, consider using the LTC3412A in an
application with the following specifications:
R2 + R3 = 185k
VIN = 3.3V, VOUT = 2.5V, IOUT(MAX) = 3A,
IOUT(MIN) = 100mA, f = 1MHz.
R2 0.8V
R3 0.50V
1+
=
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
The two equations shown above result in the following
values for R2 and R3: R2 = 69.8k , R3 = 115k. The value
of R1 can now be determined by solving the following
equation.
First, calculate the timing resistor:
3.08•1011
ROSC
=
– 10k = 298k
R1
2.5V
1•106
1+
=
185k 0.8V
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum VIN:
R1= 392k
A value of 392k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
⎛
⎞
⎛
⎞
2.5V
2.5V
3.3V
L =
1–
= 0.51μH
⎜
⎟
⎜
⎟
(1MHz)(1.2A)
⎝
⎠
⎝
⎠
PC Board Layout Checklist
Using a 0.47μH inductor results in a maximum ripple
current of:
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3412A. Check the following in your layout:
⎛
⎝
⎞
2.5V
2.5V
3.3V
⎛
⎜
⎝
⎞
⎟
⎠
ΔIL =
1–
= 1.29A
⎜
⎟
⎠
(1MHz)(0.47μH)
1. Agroundplaneisrecommended. Ifagroundplanelayer
is not used, the signal and power grounds should be
segregated with all small signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3412A.
COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100μF ceramic capacitors will be used.
CIN should be sized for a maximum current rating of:
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin. This capacitor
provides the AC current into the internal power MOSFETs.
⎛
⎞
2.5V 3.3V
IRMS = (3A)
– 1 = 1.29ARMS
⎜
⎟
3.3V 2.5V
⎝
⎠
3412afb
14
LTC3412A
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APPLICATIO S I FOR ATIO
U
3. Keep the switching node, SW, away from all sensitive
small signal nodes.
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and SGND.
4. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. You can connect the copper areas to
any DC net (PVIN, SVIN, VOUT, PGND, SGND, or any other
DC rail in your system).
Bottom
Top
Figure 3. LTC3412A Layout Diagram
V
IN
3.3V
C
FF
22pF X5R
R1 392k
C
IN3
**
100μF
C
IN1
22μF
1
16
SV
IN
PV
IN
R
PG
100k
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
C
ITH
330pF X7R
ITH
17.4k
I
TH
C
C
LTC3412A
EFE
47pF
L1*
0.47μH
PGND
PGND
SW
V
2.5V
3A
4
5
OUT
V
FB
R2
69.8k
R3
115k
R
T
R
OSC
294k
SYNC/MODE
6
7
R
SS
2.2M
C
**
OUT
100μF
RUN
SW
C
×2
SS
1000pF X7R
8
SGND
PV
IN
C
IN2
22μF
GND
X5R 6.3V
3412 F04
*VISHAY IHLP-2525CZ-01
**TDK 4532X5R0J107M
Figure 4. 3.3V to 2.5V, 3A Regulator at 1MHz, Burst Mode Operation
3412afb
15
LTC3412A
U
TYPICAL APPLICATIO S
1.2V, 3A, 1.5MHz 1mm Height Regulator Using All Ceramic Capacitors
V
IN
3.3V
C1 22pF X5R
R1 95.3k
C
IN1
10μF
11
10
SV
IN
PV
IN
X5R 6.3V
R
PG
100k
12
13
9
8
7
6
5
4
3
PGOOD
1000pF X7R
PGOOD
SW
SW
R
ITH
C
ITH
6.34k
I
TH
C
C
LTC3412A
EUF
22pF
L1*
PGND
PGND
SW
0.47μH
V
1.2V
3A
14
15
OUT
V
FB
R2
187k
R
T
R
196k
OSC
16
1
C
**
OUT
R
SS
SYNC/MODE
RUN
22μF
2.2M
X3
SW
C
SS
1000pF X7R
2
SGND
PV
IN
C
IN2
10μF
X5R 6.3V
GND
3412 TA01
*COOPER SD10-R47
**TAIYO YUDEN AMK212BJ226MD-B
1.8V, 3A Step-Down Regulator at 1MHz, Burst Mode Operation
V
IN
2.5V
C1 47pF X5R
C
**
IN3
100μF
R1 232k
C
IN1
1
16
22μF
SV
IN
PV
IN
X5R 6.3V
R
PG
100k
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
C
ITH
820pF X7R ITH
15k
I
TH
C2
LTC3412A
EFE
47pF
L1
0.47μH*
PGND
PGND
SW
V
4
5
OUT
1.8V
3A
V
FB
R2
R3
115k
69.8k
R
T
R
294k
OSC
C
**
OUT
6
7
R
100μF
SS
SYNC/MODE
RUN
2.2M
×3
SW
C
SS
1000pF X7R
8
SGND
PV
IN
C
IN2
22μF
X5R 6.3V
GND
3412 TA02
*VISHAY IHLP-2525CZ-01
**TDK C4532X5R0J107M
3412afb
16
LTC3412A
U
TYPICAL APPLICATIO S
3.3V, 3A Step-Down Regulator at 2MHz, Forced Continuous Mode Operation
V
IN
5V
C
**
IN3
C1 22pF X5R
R1 634k
100μF
C
IN1
22μF
1
16
SV
PV
IN
X5R 6.3V
IN
R
PG
100k
2
3
4
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
ITH
C
ITH
820pF X7R
7.5k
I
TH
C
C
LTC3412A
EFE
47pF
L1*
0.47μH
PGND
PGND
SW
V
3.3V
3A
OUT
V
FB
R2
200k
5
R
T
R
137k
OSC
6
7
C
**
OUT
SYNC/MODE
RUN
100μF
×2
SW
C
R
SS
SS
1000pF X7R
2.2M
8
SGND
PV
IN
C
IN2
22μF
X5R 6.3V
GND
3412 TA03
*VISHAY IHLP-2525CZ-01
**TDK C4532X5R0J107M
2.5V, 3A Step-Down Regulator Synchronized to 1.8MHz
V
IN
3.3V
C1 22pF X5R
R1 392k
C
IN1
22μF
1
16
SV
IN
PV
IN
X5R 6.3V
R
PG
100k
2
3
15
14
13
12
11
10
9
PGOOD
PGOOD
SW
SW
R
ITH
C
ITH
220pF X7R
6.49k
I
TH
LTC3412A
EFE
C
C
22pF
L1*
PGND
PGND
SW
0.47μH
V
1.5V
3A
4
5
OUT
V
FB
R2 162k
182k
R
T
R
OSC
+
6
7
C
**
1.8MHz
EXT CLOCK
OUT
R
SS
SYNC/MODE
RUN
150μF
2.2M
SW
C
SS
1000pF X7R
8
SGND
PV
IN
C
IN2
22μF
X5R 6.3V
GND
3412 TA04
*COOPER SD20-R47
**SANYO POSCAP 4TPE150MAZB
3412afb
17
LTC3412A
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
9
6.60 0.10
4.50 0.10
2.74
(.108)
6.40
(.252)
BSC
SEE NOTE 4
2.74
(.108)
0.45 0.05
1.05 0.10
0.65 BSC
5
7
8
1
2
3
4
6
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE16 (BA) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
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18
LTC3412A
U
PACKAGE DESCRIPTIO
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 0.05
4.35 0.05
2.90 0.05
2.15 0.05
(4 SIDES)
PACKAGE OUTLINE
0.30 0.05
0.65 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER
0.75 0.05
R = 0.115
TYP
4.00 0.10
(4 SIDES)
15
16
0.55 0.20
PIN 1
TOP MARK
(NOTE 6)
1
2
2.15 0.10
(4-SIDES)
(UF16) QFN 10-04
0.200 REF
0.30 0.05
0.65 BSC
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3412afb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LTC3412A
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ThinSOT is a trademark of Linear Technology Corporation.
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LT 0807 REV B • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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