LT3782AIUFD#TRPBF [Linear]
LT3782A - 2-Phase Step-Up DC/DC Controller; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C;型号: | LT3782AIUFD#TRPBF |
厂家: | Linear |
描述: | LT3782A - 2-Phase Step-Up DC/DC Controller; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C 控制器 |
文件: | 总36页 (文件大小:477K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC1871
Wide Input Range, No R
™
SENSE
Current Mode Boost,
Flyback and SEPIC Controller
DESCRIPTION
The LTC®1871 is a wide input range, current mode, boost,
flybackorSEPICcontrollerthatdrivesanN-channelpower
MOSFET and requires very few external components. In-
tendedforlowtomediumpowerapplications,iteliminates
theneedforacurrentsenseresistorbyutilizingthepower
MOSFET’s on-resistance, thereby maximizing efficiency.
FEATURES
n
High Efficiency (No Sense Resistor Required)
n
Wide Input Voltage Range: 2.5V to 36V
n
Current Mode Control Provides Excellent
Transient Response
n
High Maximum Duty Cycle (92% Typ)
n
2% RUN Pin Threshold with 100mV Hysteresis
n
1% Internal Voltage Reference
The IC’s operating frequency can be set with an external
resistor over a 50kHz to 1MHz range, and can be syn-
chronized to an external clock using the MODE/SYNC
pin. Burst Mode operation at light loads, a low minimum
operating supply voltage of 2.5V and a low shutdown
quiescentcurrentof10μAmaketheLTC1871ideallysuited
for battery-operated systems.
n
Micropower Shutdown: I = 10μA
Q
n
Programmable Operating Frequency
(50kHz to 1MHz) with One External Resistor
Synchronizable to an External Clock Up to 1.3 × f
n
n
n
n
n
OSC
User-Controlled Pulse Skip or Burst Mode® Operation
Internal 5.2V Low Dropout Voltage Regulator
Output Overvoltage Protection
For applications requiring constant frequency opera-
tion, Burst Mode operation can be defeated using the
MODE/SYNC pin. Higher output voltage boost, SEPIC
and flyback applications are possible with the LTC1871
by connecting the SENSE pin to a resistor in the source
of the power MOSFET.
Capable of Operating with a Sense Resistor for
High Output Voltage Applications
Small 10-Lead MSOP Package
n
APPLICATIONS
n
Telecom Power Supplies
Portable Electronic Equipment
The LTC1871 is available in the 10-lead MSOP package.
L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.
n
No R
is a trademark of Linear Technology Corporation. All other trademarks are the
SENSE
property of their respective owners.
TYPICAL APPLICATION
V
IN
3.3V
Efficiency of Figure 1
L1
100
90
80
70
60
50
40
30
1μH
D1
RUN
SENSE
Burst Mode
OPERATION
V
OUT
5V
I
V
IN
TH
7A
C
R
OUT1
C
+
(10A PEAK)
LTC1871
INTV
150μF
6.3V
×4
22k
PULSE-SKIP
MODE
FB
CC
C
6.8nF
C1
R1
12.1k
1%
C
OUT2
FREQ
GATE
GND
M1
22μF
6.3V
X5R
×2
C
IN
C
4.7μF
X5R
VCC
+
R2
37.4k
1%
R
T
80.6k
1%
MODE/SYNC
22μF
6.3V
×2
C
C2
47pF
GND
1871 F01a
C
C
C
:
TAIYO YUDEN JMK325BJ226MM
: PANASONIC EEFUEOJ151R
: TAIYO YUDEN JMK325BJ226MM
D1: MBRB2515L
IN
0.001
0.01
0.1
1
10
L1: SUMIDA CEP125-H 1R0MH
M1: FAIRCHILD FDS7760A
OUT1
OUT2
OUTPUT CURRENT (A)
1871 F01b
Figure 1. High Efficiency 3.3V Input, 5V Output Boost Converter (Bootstrapped)
1871fe
1
LTC1871
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V Voltage ............................................... –0.3V to 36V
IN
RUN
TH
FB
FREQ
MODE/
SYNC
1
2
3
4
5
10 SENSE
INTV Voltage............................................ –0.3V to 7V
I
9
8
7
6
V
IN
CC
INTV
CC
INTV Output Current.......................................... 50mA
CC
GATE
GND
GATE Voltage ............................ –0.3V to V
TH
+ 0.3V
INTVCC
MS PACKAGE
10-LEAD PLASTIC MSOP
= 125°C, θ = 120°C/W
I , FB Voltages ....................................... –0.3V to 2.7V
RUN, MODE/SYNC Voltages ....................... –0.3V to 7V
FREQ Voltage ............................................ –0.3V to 1.5V
SENSE Pin Voltage.................................... –0.3V to 36V
Operating Temperature Range (Note 2)
T
JMAX
JA
LTC1871E............................................. –40°C to 85°C
LTC1871I............................................ –40°C to 125°C
LTC1871H .......................................... –40°C to 150°C
Junction Temperature (Note 3)
LTC1871E/LTC1871I......................................... 125°C
LTC1871H ......................................................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
ORDER INFORMATION
LEAD FREE FINISH
LTC1871EMS#PBF
LTC1871IMS#PBF
LTC1871HMS#PBF
LEAD BASED FINISH
LTC1871EMS
TAPE AND REEL
PART MARKING
LTSX
PACKAGE DESCRIPTION
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
PACKAGE DESCRIPTION
10-Lead Plastic MSOP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
TEMPERATURE RANGE
–40°C to 85°C
LTC1871EMS#TRPBF
LTC1871IMS#TRPBF
LTC1871HMS#TRPBF
TAPE AND REEL
LTBFC
–40°C to 125°C
LTCXS
–40°C to 150°C
PART MARKING
LTSX
TEMPERATURE RANGE
–40°C to 85°C
LTC1871EMS#TR
LTC1871IMS#TR
LTC1871IMS
LTBFC
–40°C to 125°C
LTC1871HMS
LTC1871HMS#TR
LTCXS
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1871fe
2
LTC1871
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VINTVCC = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Main Control Loop
V
Minimum Input Voltage
2.5
2.5
V
V
IN(MIN)
I-Grade or H-Grade (Note 2)
(Note 4)
●
I
Input Voltage Supply Current
Continuous Mode
Q
V
V
= 5V, V = 1.4V, V = 0.75V
550
550
1000
1000
μA
μA
MODE/SYNC
FB
ITH
= 5V, V = 1.4V, V = 0.75V,
●
●
●
MODE/SYNC
FB
ITH
I-Grade or H-Grade (Note 2)
Burst Mode Operation, No Load
Shutdown Mode
V
= 0V, V = 0.2V (Note 5)
250
250
500
500
μA
μA
MODE/SYNC
ITH
V
= 0V, V = 0.2V (Note 5),
MODE/SYNC
ITH
I-Grade or H-Grade (Note 2)
V
RUN
V
RUN
= 0V
10
10
20
20
μA
μA
V
= 0V, I-Grade or H-Grade (Note 2)
+
–
V
V
Rising RUN Input Threshold Voltage
Falling RUN Input Threshold Voltage
1.348
1.248
RUN
RUN
1.223
1.198
1.273
1.298
V
V
●
●
H-Grade (Note 2)
1.179
50
1.315
150
175
300
60
V
mV
mV
mV
nA
V
RUN Pin Input Threshold Hysteresis
100
100
RUN(HYST)
I-Grade (Note 2)
H-Grade (Note 2)
●
●
35
35
I
RUN Input Current
Feedback Voltage
1
RUN
V
V
= 0.2V (Note 5)
1.218
1.212
1.230
1.242
1.248
V
V
FB
ITH
●
●
V
V
= 0.2V (Note 5), I-Grade or H-Grade (Note 2)
= 0.2V (Note 5)
1.205
1.255
60
V
nA
ITH
ITH
I
FB Pin Input Current
Line Regulation
18
FB
ΔV
ΔV
2.5V ≤ V ≤ 30V
0.002
0.002
–0.1
–0.1
0.02
0.02
%/V
%/V
%
FB
IN
2.5V ≤ V ≤ 30V, I-Grade or H-Grade (Note 2)
●
●
●
IN
IN
ΔV
ΔV
Load Regulation
V
= 0V, V = 0.5V to 0.9V (Note 5)
–1
–1
FB
MODE/SYNC
ITH
V
= 0V, V = 0.5V to 0.9V (Note 5)
%
ITH
MODE/SYNC
ITH
I-Grade or H-Grade (Note 2)
ΔV
ΔFB Pin, Overvoltage Lockout
V
– V in Percent
FB(NOM)
2.5
6
10
%
μmho
V
FB(OV)
FB(OV)
g
m
Error Amplifier Transconductance
I
TH
Pin Load = 5μA (Note 5)
650
0.3
150
V
V
Burst Mode Operation I Pin Voltage
Falling I Voltage (Note 5)
TH
ITH(BURST)
SENSE(MAX)
TH
Maximum Current Sense Input Threshold Duty Cycle < 20%
Duty Cycle < 20%, I-Grade or H-Grade (Note 2)
120
100
180
200
50
mV
mV
μA
●
I
I
SENSE Pin Current (GATE High)
SENSE Pin Current (GATE Low)
V
= 0V
35
SENSE(ON)
SENSE(OFF)
SENSE
SENSE
V
= 30V
0.1
5
μA
Oscillator
f
Oscillator Frequency
R
R
R
= 80k
250
250
240
50
300
300
300
350
350
kHz
kHz
kHz
kHz
kHz
OSC
FREQ
FREQ
FREQ
= 80k, I-Grade (Note 2)
= 80k, H-Grade (Note 2)
●
●
360
Oscillator Frequency Range
1000
1000
I-Grade or H-Grade (Note 2)
●
50
1871fe
3
LTC1871
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = VINTVCC = 5V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless
otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
87
TYP
92
MAX UNITS
D
MAX
Maximum Duty Cycle
97
97
%
%
I-Grade or H-Grade (Note 2)
●
●
87
92
f
f
Recommended Maximum Synchronized
Frequency Ratio
f
f
= 300kHz (Note 6)
1.25
1.25
25
1.30
1.30
SYNC/ OSC
OSC
OSC
= 300kHz (Note 6), I-Grade or H-Grade (Note 2)
t
t
MODE/SYNC Minimum Input Pulse Width
MODE/SYNC Maximum Input Pulse Width
Low Level MODE/SYNC Input Voltage
V
SYNC
V
SYNC
= 0V to 5V
= 0V to 5V
ns
ns
V
SYNC(MIN)
0.8/f
SYNC(MAX)
OSC
V
0.3
0.3
IL(MODE)
IH(MODE)
I-Grade or H-Grade (Note 2)
I-Grade or H-Grade (Note 2)
●
●
V
V
High Level MODE/SYNC Input Voltage
1.2
1.2
V
V
R
MODE/SYNC Input Pull-Down Resistance
Nominal FREQ Pin Voltage
50
kΩ
V
MODE/SYNC
V
0.62
FREQ
Low Dropout Regulator
V
INTV Regulator Output Voltage
V
V
V
= 7.5V
5.0
5.0
5.2
5.2
5.2
8
5.4
5.4
V
V
INTVCC
CC
IN
IN
IN
= 7.5V, I-Grade (Note 2)
= 7.5V, H-Grade (Note 2)
●
●
4.95
5.45
25
V
ΔV
Δ
INTV Regulator Line Regulation
7.5V ≤ V ≤ 15V
mV
INTVCC
CC
IN
V
IN1
ΔV
INTV Regulator Line Regulation
15V ≤ V ≤ 30V
70
200
mV
INTVCC
CC
IN
Δ
V
IN2
V
V
INTV Load Regulation
0 ≤ I
≤ 20mA, V = 7.5V
–2
–0.2
280
10
%
mV
μA
LDO(LOAD)
DROPOUT
INTVCC
CC
INTVCC
IN
INTV Regulator Dropout Voltage
V = 5V, INTV Load = 20mA
IN CC
CC
I
Bootstrap Mode INTV Supply
RUN = 0V, SENSE = 5V
I-Grade (Note 2)
20
30
50
CC
Current in Shutdown
●
●
μA
H-Grade (Note 2)
μA
GATE Driver
t
r
t
f
GATE Driver Output Rise Time
GATE Driver Output Fall Time
C = 3300pF (Note 7)
17
8
100
100
ns
ns
L
C = 3300pF (Note 7)
L
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The dynamic input supply current is higher due to power MOSFET
gate charging (Q • f ). See Applications Information.
G
OSC
Note 5: The LTC1871 is tested in a feedback loop which servos V to
FB
the reference voltage with the I pin forced to the midpoint of its voltage
TH
Note 2: The LTC1871E is guaranteed to meet performance specifications
from 0°C to 85°C operating temperature. Specifications over the –40°C to
85°C operating temperature range are assured by design, characterization
and correlation with statistical process controls. The LTC1871I is
guaranteed over the full –40°C to 125°C operating temperature range
and the LTC1871H is guaranteed over the full –40°C to 150°C operating
temperature range.
range (0.3V ≤ V ≤ 1.2V, midpoint = 0.75V).
ITH
Note 6: In a synchronized application, the internal slope compensation
gain is increased by 25%. Synchronizing to a significantly higher ratio will
reduce the effective amount of slope compensation, which could result in
subharmonic oscillation for duty cycles greater than 50%.
Note 7: Rise and fall times are measured at 10% and 90% levels.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
T = T + (P • 110°C/W)
J
A
D
1871fe
4
LTC1871
TYPICAL PERFORMANCE CHARACTERISTICS
FB Voltage vs Temp
FB Voltage Line Regulation
FB Pin Current vs Temperature
60
50
40
30
20
10
0
1.231
1.230
1.229
1.25
1.24
1.23
1.22
1.21
–50
0
25 50 75 100 125 150
TEMPERATURE (°C)
–25
50 75
TEMPERATURE (°C)
0
5
10
15
V
20
(V)
25
30
35
–50 –25
0
25
100 125 150
IN
1871 G03
1871 G02
1871 G01
Shutdown Mode IQ vs VIN
Shutdown Mode IQ vs Temperature
Burst Mode IQ vs VIN
20
15
10
5
600
500
400
300
200
100
0
30
20
10
V
= 5V
IN
0
0
30
0
10
20
(V)
40
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
10
20
(V)
30
40
V
V
IN
IN
1871 G04
1871 G05
1871 G06
Gate Drive Rise and
Fall Time vs CL
Burst Mode IQ vs Temperature
Dynamic IQ vs Frequency
500
400
300
200
100
0
18
16
14
12
10
8
60
50
40
30
20
10
0
C
= 3300pF
L
I
= 550μA + Qg • f
Q(TOT)
RISE TIME
6
FALL TIME
4
2
0
–50
50
100 125
0
4000 6000 8000 10000 12000
(pF)
–25
0
25
75
150
2000
0
200
400
FREQUENCY (kHz)
1000 1200
600
800
TEMPERATURE (°C)
C
L
1871 G07
1871 G09
1871 G08
1871fe
5
LTC1871
TYPICAL PERFORMANCE CHARACTERISTICS
RUN Thresholds vs VIN
RUN Thresholds vs Temperature
RT vs Frequency
1.5
1.4
1.3
1.40
1.35
1.30
1.25
1.20
1000
100
10
1.2
30
0
10
20
(V)
40
50 75
TEMPERATURE (°C)
–50 –25
0
25
100 125 150
100 200
400
600 700 800
1000
900
0
300
500
V
IN
FREQUENCY (kHz)
1871 G12
1871 G10
1871 G11
SENSE Pin Current
vs Temperature
Maximum Sense Threshold
vs Temperature
Frequency vs Temperature
35
30
25
325
320
315
310
305
300
295
290
285
280
275
160
155
150
145
GATE HIGH
V
= 0V
SENSE
140
–50
50
100 125
150
–25
0
25
75
–50
50
100 125
150
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
–25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
1871 G15
1871 G13
1871 G14
INTVCC Dropout Voltage
vs Current, Temperature
INTVCC Load Regulation
INTVCC Line Regulation
500
450
400
350
300
250
200
150
100
50
5.4
5.3
5.2
V
= 7.5V
IN
150°C
5.2
125°C
75°C
25°C
5.1
5.0
0°C
–50°C
5.1
0
25 30
10
20
40
0
5
10 15 20
(V)
35 40
0
5
15
0
10 20 30
50 60 70 80
V
INTV LOAD (mA)
CC
INTV LOAD (mA)
IN
CC
1871 G17
1871 G18
1871 G16
1871fe
6
LTC1871
PIN FUNCTIONS
RUN (Pin 1): The RUN pin provides the user with an
accurate means for sensing the input voltage and pro-
gramming the start-up threshold for the converter. The
falling RUN pin threshold is nominally 1.248V and the
comparatorhas100mVofhysteresisfornoiseimmunity.
When the RUN pin is below this input threshold, the IC
operating frequency to an external clock. If the MODE/
SYNC pin is connected to ground, Burst Mode operation
isenabled.IftheMODE/SYNCpinisconnectedtoINTV ,
CC
or if an external logic-level synchronization signal is ap-
plied to this input, Burst Mode operation is disabled and
the IC operates in a continuous mode.
is shut down and the V supply current is kept to a low
value (typ 10μA). The Absolute Maximum Rating for the
voltage on this pin is 7V.
IN
GND (Pin 6): Ground Pin.
GATE (Pin 7): Gate Driver Output.
I
NTV (Pin 8): The Internal 5.20V Regulator Output.
CC
I
(Pin 2): Error Amplifier Compensation Pin. The
TH
The gate driver and control circuits are powered from
this voltage. Decouple this pin locally to the IC ground
with a minimum of 4.7μF low ESR tantalum or ceramic
capacitor.
current comparator input threshold increases with this
control voltage. Nominal voltage range for this pin is 0V
to 1.40V.
FB(Pin3):Receivesthefeedbackvoltagefromtheexternal
resistor divider across the output. Nominal voltage for
this pin in regulation is 1.230V.
V (Pin 9): Main Supply Pin. Must be closely decoupled
to ground.
IN
SENSE (Pin 10): The Current Sense Input for the Control
FREQ (Pin 4): A resistor from the FREQ pin to ground
programstheoperatingfrequencyofthechip.Thenominal
voltage at the FREQ pin is 0.6V.
Loop. Connect this pin to the drain of the power MOSFET
for V sensing and highest efficiency. Alternatively, the
DS
SENSE pin may be connected to a resistor in the source
of the power MOSFET. Internal leading edge blanking is
provided for both sensing methods.
MODE/SYNC (Pin 5): This input controls the operating
mode of the converter and allows for synchronizing the
1871fe
7
LTC1871
BLOCK DIAGRAM
RUN
1
+
–
BIAS AND
START-UP
CONTROL
SLOPE
COMPENSATION
C2
1.248V
V
IN
FREQ
V-TO-I
OV
OSC
4
9
0.6V
I
OSC
MODE/SYNC
5
INTV
CC
GATE
7
PWM LATCH
50k
LOGIC
85mV
S
Q
R
–
+
+
1.230V
GND
BURST
COMPARATOR
CURRENT
COMPARATOR
SENSE
10
+
–
0.30V
+
–
FB
C1
EA
–
+
3
g
m
1.230V
I
TH
2
V-TO-I
SLOPE
R
LOOP
INTV
8
I
CC
LOOP
5.2V
1.230V
TO
LDO
UV
1.230V
–
+
GND
START-UP
CONTROL
BIAS
V
6
1871 BD
REF
2.00V
V
IN
OPERATION
Main Control Loop
is turned on when the oscillator sets the PWM latch and
is turned off when the current comparator C1 resets the
latch. The divided-down output voltage is compared to an
internal 1.230V reference by the error amplifier EA, which
The LTC1871 is a constant frequency, current mode con-
troller for DC/DC boost, SEPIC and flyback converter ap-
plications.TheLTC1871isdistinguishedfromconventional
current mode controllers because the current control loop
canbeclosedbysensingthevoltagedropacrossthepower
MOSFETswitchinsteadofacrossadiscretesenseresistor,
as shown in Figure 2. This sensing technique improves
efficiency, increases power density, and reduces the cost
of the overall solution.
outputs an error signal at the I pin. The voltage on the
TH
I
TH
pin sets the current comparator C1 input threshold.
When the load current increases, a fall in the FB voltage
relative to the reference voltage causes the I pin to rise,
TH
which causes the current comparator C1 to trip at a higher
peak inductor current value. The average inductor current
will therefore rise until it equals the load current, thereby
maintaining output regulation.
For circuit operation, please refer to the Block Diagram of
theICandFigure1.Innormaloperation,thepowerMOSFET
1871fe
8
LTC1871
OPERATION
D
reset pulse to the main RS latch. Because this RS latch is
reset-dominant, the power MOSFET is actively held off for
the duration of an output overvoltage condition.
L
V
V
C
IN
OUT
OUT
V
IN
+
SENSE
V
SW
The LTC1871 can be used either by sensing the voltage
drop across the power MOSFET or by connecting the
SENSE pin to a conventional shunt resistor in the source
of the power MOSFET, as shown in Figure 2. Sensing the
voltage across the power MOSFET maximizes converter
efficiency and minimizes the component count, but limits
theoutputvoltagetothemaximumratingforthispin(36V).
By connecting the SENSE pin to a resistor in the source
of the power MOSFET, the user is able to program output
voltages significantly greater than 36V.
GATE
GND
GND
2a. SENSE Pin Connection for
Maximum Efficiency (V
< 36V)
SW
D
L
V
V
IN
OUT
V
SW
V
IN
GATE
+
SENSE
GND
C
OUT
Programming the Operating Mode
R
S
1871 F02
GND
For applications where maximizing the efficiency at very
light loads (e.g., <100μA) is a high priority, the current
in the output divider could be decreased to a few micro-
amps and Burst Mode operation should be applied (i.e.,
the MODE/SYNC pin should be connected to ground).
In applications where fixed frequency operation is more
critical than low current efficiency, or where the lowest
outputrippleisdesired,pulse-skipmodeoperationshould
be used and the MODE/SYNC pin should be connected
2b. SENSE Pin Connection for Precise
Control of Peak Current or for V > 36V
SW
Figure 2. Using the SENSE Pin On the LTC1871
The nominal operating frequency of the LTC1871 is pro-
grammed using a resistor from the FREQ pin to ground
and can be controlled over a 50kHz to 1000kHz range. In
addition, the internal oscillator can be synchronized to
an external clock applied to the MODE/SYNC pin and can
be locked to a frequency between 100% and 130% of its
nominal value. When the MODE/SYNC pin is left open, it
is pulled low by an internal 50k resistor and Burst Mode
operation is enabled. If this pin is taken above 2V or an
externalclockisapplied, BurstModeoperationisdisabled
and the IC operates in continuous mode. With no load (or
an extremely light load), the controller will skip pulses in
order to maintain regulation and prevent excessive output
ripple.
to the INTV pin. This allows discontinuous conduction
CC
mode (DCM) operation down to near the limit defined
by the chip’s minimum on-time (about 175ns). Below
this output current level, the converter will begin to skip
cycles in order to maintain output regulation. Figures 3
and 4 show the light load switching waveforms for Burst
Mode and pulse-skip mode operation for the converter
in Figure 1.
Burst Mode Operation
Burst Mode operation is selected by leaving the MODE/
SYNC pin unconnected or by connecting it to ground. In
TheRUNpincontrolswhethertheICisenabledorisinalow
current shutdown state. A micropower 1.248V reference
and comparator C2 allow the user to program the supply
voltage at which the IC turns on and off (comparator C2
has 100mV of hysteresis for noise immunity). With the
RUN pin below 1.248V, the chip is off and the input supply
current is typically only 10μA.
normaloperation,therangeontheI pincorrespondingto
TH
no load to full load is 0.30V to 1.2V. In Burst Mode opera-
tion, if the error amplifier EA drives the I voltage below
TH
0.525V, the buffered I input to the current comparator
TH
C1 will be clamped at 0.525V (which corresponds to 25%
of maximum load current). The inductor current peak is
then held at approximately 30mV divided by the power
An overvoltage comparator OV senses when the FB pin
exceeds the reference voltage by 6.5% and provides a
1871fe
9
LTC1871
OPERATION
MOSFET R
. If the I pin drops below 0.30V, the
When an external clock signal drives the MODE/SYNC
pin at a rate faster than the chip’s internal oscillator, the
oscillatorwillsynchronizetoit.Inthissynchronizedmode,
Burst Mode operation is disabled. The constant frequency
associated with synchronized operation provides a more
controlled noise spectrum from the converter, at the ex-
pense of overall system efficiency of light loads.
DS(ON)
TH
BurstModecomparatorB1willturnoffthepowerMOSFET
and scale back the quiescent current of the IC to 250μA
(sleep mode). In this condition, the load current will be
supplied by the output capacitor until the I voltage rises
TH
above the 50mV hysteresis of the burst comparator. At
light loads, short bursts of switching (where the average
inductor current is 20% of its maximum value) followed
by long periods of sleep will be observed, thereby greatly
improving converter efficiency. Oscilloscope waveforms
illustrating Burst Mode operation are shown in Figure 3.
When the oscillator’s internal logic circuitry detects a
synchronizing signal on the MODE/SYNC pin, the in-
ternal oscillator ramp is terminated early and the slope
compensation is increased by approximately 30%. As
a result, in applications requiring synchronization, it is
recommended that the nominal operating frequency of
the IC be programmed to be about 75% of the external
clock frequency. Attempting to synchronize to too high an
Pulse-Skip Mode Operation
With the MODE/SYNC pin tied to a DC voltage above 2V,
Burst Mode operation is disabled. The internal, 0.525V
buffered I burst clamp is removed, allowing the I
TH
TH
external frequency (above 1.3f ) can result in inadequate
O
pin to directly control the current comparator from no
slopecompensationandpossiblesubharmonicoscillation
load to full load. With no load, the I pin is driven below
TH
(or jitter).
0.30V, the power MOSFET is turned off and sleep mode
is invoked. Oscilloscope waveforms illustrating this mode
of operation are shown in Figure 4.
The external clock signal must exceed 2V for at least 25ns,
and should have a maximum duty cycle of 80%, as shown
in Figure 5. The MOSFET turn on will synchronize to the
rising edge of the external clock signal.
V
V
= 3.3V
MODE/SYNC = 0V
(Burst Mode OPERATION)
IN
= 5V
OUT
OUT
I
= 500mA
V
OUT
50mV/DIV
2V TO 7V
MODE/
SYNC
I
L
5A/DIV
t
= 25ns
MIN
0.8T
T
T = 1/f
O
1871 F03
10μs/DIV
Figure 3. LTC1871 Burst Mode Operation
(MODE/SYNC = 0V) at Low Output Current
GATE
D = 40%
V
V
= 3.3V
MODE/SYNC = INTV
CC
(PULSE-SKIP MODE)
IN
= 5V
OUT
OUT
I
L
I
= 500mA
V
OUT
50mV/DIV
1871 F05
Figure 5. MODE/SYNC Clock Input and Switching
Waveforms for Synchronized Operation
I
L
5A/DIV
1871 F04
2μs/DIV
Figure 4. LTC1871 Low Output Current Operation with
Burst Mode Operation Disabled (MODE/SYNC = INTVCC
)
1871fe
10
LTC1871
APPLICATIONS INFORMATION
Programming the Operating Frequency
INTV Regulator Bypassing and Operation
CC
An internal, P-channel low dropout voltage regulator pro-
duces the 5.2V supply which powers the gate driver and
logic circuitry within the LTC1871, as shown in Figure 7.
The choice of operating frequency and inductor value is
a tradeoff between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET and diode switching losses. However, lower
frequency operation requires more inductance for a given
amount of load current.
The INTV regulator can supply up to 50mA and must be
CC
bypassed to ground immediately adjacent to the IC pins
with a minimum of 4.7μF tantalum or ceramic capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate driver.
The LTC1871 uses a constant frequency architecture that
can be programmed over a 50kHz to 1000kHz range with
a single external resistor from the FREQ pin to ground, as
shown in Figure 1. The nominal voltage on the FREQ pin is
0.6V, and the current that flows into the FREQ pin is used
to charge and discharge an internal oscillator capacitor. A
For input voltages that don’t exceed 7V (the absolute
maximum rating for this pin), the internal low dropout
regulator in the LTC1871 is redundant and the INTV pin
CC
can be shorted directly to the V pin. With the INTV
IN
CC
pin shorted to V , however, the divider that programs the
graph for selecting the value of R for a given operating
IN
T
regulated INTV voltage will draw 10μA of current from
frequency is shown in Figure 6.
CC
theinputsupply, eveninshutdownmode. Forapplications
1000
that require the lowest shutdown mode input supply cur-
rent, do not connect the INTV pin to V . Regardless of
CC
IN
whethertheINTV pinisshortedtoV ornot,itisalways
CC
IN
necessary to have the driver circuitry bypassed with a
100
4.7μF tantalum or low ESR ceramic capacitor to ground
immediately adjacent to the INTV and GND pins.
CC
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
As a result, high input voltage applications in which a
large power MOSFET is being driven at high frequencies
can cause the LTC1871 to exceed its maximum junction
10
100 200
400
600 700 800
1000
900
0
300
500
FREQUENCY (kHz)
1871 F06
Figure 6. Timing Resistor (RT) Value
INPUT
SUPPLY
2.5V TO 30V
V
IN
–
1.230V
P-CH
5.2V
+
C
IN
R2
R1
INTV
CC
+
C
VCC
4.7μF
GATE
GND
LOGIC
DRIVER
M1
GND
PLACE AS CLOSE AS
POSSIBLE TO DEVICE PINS
1871 F07
Figure 7. Bypassing the LDO Regulator and Gate Driver Supply
1871fe
11
LTC1871
APPLICATIONS INFORMATION
temperature rating. The junction temperature can be
estimated using the following equations:
The external resistor divider is connected to the output
as shown in Figure 1, allowing remote voltage sensing.
The resistors R1 and R2 are typically chosen so that the
error caused by the current flowing into the FB pin dur-
ing normal operation is less than 1% (this translates to a
maximum value of R1 of about 250k).
I
≈ I + f • Q
Q G
Q(TOT)
P = V • (I + f • Q )
IC
IN
Q
G
T = T + P • R
J
A
IC
TH(JA)
The total quiescent current I
consists of the static
Q(TOT)
Programming Turn-On and Turn-Off Thresholds with
the RUN Pin
supply current (I ) and the current required to charge and
Q
dischargethegateofthepowerMOSFET.The10-pinMSOP
package has a thermal resistance of R
TheLTC1871containsanindependent,micropowervoltage
reference and comparator detection circuit that remains
active even when the device is shut down, as shown in
Figure 8. This allows users to accurately program an input
voltage at which the converter will turn on and off. The
falling threshold voltage on the RUN pin is equal to the
internal reference voltage of 1.248V. The comparator has
100mV of hysteresis to increase noise immunity.
= 120°C/W.
TH(JA)
As an example, consider a power supply with V = 5V and
IN
V = 12V at I = 1A. The switching frequency is 500kHz,
O
O
andthemaximumambienttemperatureis70°C.Thepower
MOSFET chosen is the IRF7805, which has a maximum
R
of 11mΩ (at room temperature) and a maximum
DS(ON)
total gate charge of 37nC (the temperature coefficient of
the gate charge is low).
The turn-on and turn-off input voltage thresholds are
programmed using a resistor divider according to the
following formulas:
I
= 600μA + 37nC • 500kHz = 19.1mA
Q(TOT)
P = 5V • 19.1mA = 95mW
IC
R2
R1
ꢀ
ꢁ
ꢃ
ꢄ
T = 70°C + 120°C/W • 95mW = 81.4°C
J
V
=1.248V • 1+
ꢂ
ꢅ
IN(OFF)
Thisdemonstrateshowsignificantthegatechargecurrent
can be when compared to the static quiescent current in
the IC.
R2
R1
ꢀ
ꢁ
ꢃ
ꢄ
V
=1.348V • 1+
ꢂ
ꢅ
IN(ON)
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked when
The resistor R1 is typically chosen to be less than 1M.
For applications where the RUN pin is only to be used as
alogicinput,theusershouldbeawareofthe7VAbsolute
Maximum Rating for this pin! The RUN pin can be con-
nectedtotheinputvoltagethroughanexternal1Mresistor,
as shown in Figure 8c, for “always on” operation.
operating in a continuous mode at high V . A tradeoff
IN
between the operating frequency and the size of the power
MOSFETmayneedtobemadeinordertomaintainareliable
IC junction temperature. Prior to lowering the operating
frequency, however, be sure to check with power MOSFET
manufacturers for their latest-and-greatest low Q , low
G
Application Circuits
R
DS(ON)
devices. Power MOSFET manufacturing tech-
A basic LTC1871 application circuit is shown in Figure 1.
External component selection is driven by the character-
istics of the load and the input supply. The first topology
to be analyzed will be the boost converter, followed by
SEPIC (single ended primary inductance converter).
nologies are continually improving, with newer and better
performance devices being introduced almost yearly.
Output Voltage Programming
The output voltage is set by a resistor divider according
to the following formula:
R2
R1
ꢀ
ꢁ
ꢃ
ꢄ
V =1.230V • 1+
ꢂ
ꢅ
O
1871fe
12
LTC1871
APPLICATIONS INFORMATION
V
IN
+
R2
RUN
COMPARATOR
RUN
+
–
BIAS AND
START-UP
CONTROL
6V
INPUT
SUPPLY
OPTIONAL
FILTER
CAPACITOR
R1
1.248V
μPOWER
REFERENCE
GND
–
1871 F8a
Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin
V
IN
+
R2
1M
RUN
RUN
COMPARATOR
+
–
RUN
COMPARATOR
6V
INPUT
SUPPLY
RUN
+
–
6V
1.248V
EXTERNAL
LOGIC CONTROL
1.248V
GND
–
1871 F08b
1871 F08c
Figure 8b. On/Off Control Using External Logic
Figure 8c. External Pull-Up Resistor On
RUN Pin for “Always On” Operation
Boost Converter: Duty Cycle Considerations
Boost Converter: The Peak and Average Input Currents
Foraboostconverteroperatinginacontinuousconduction
mode (CCM), the duty cycle of the main switch is:
The control circuit in the LTC1871 is measuring the input
current (either by using the R
of the power MOSFET
DS(ON)
or by using a sense resistor in the MOSFET source), so
the output current needs to be reflected back to the input
in order to dimension the power MOSFET properly. Based
on the fact that, ideally, the output power is equal to the
input power, the maximum average input current is:
ꢀ
IN ꢃ
VO + VD – V
D=
ꢂ
ꢅ
VO + VD
ꢁ
ꢄ
where V is the forward voltage of the boost diode. For
D
converters where the input voltage is close to the output
voltage,thedutycycleislowandforconvertersthatdevelop
a high output voltage from a low voltage input supply,
the duty cycle is high. The maximum output voltage for a
boost converter operating in CCM is:
IO(MAX)
I
=
IN(MAX)
1–DMAX
Thepeak input current is:
V
IN(MIN)
IO(MAX)
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
VO(MAX)
=
– VD
I
= 1+
•
ꢃ
ꢆ
IN(PEAK)
1–D
MAX
2
1–DMAX
The maximum duty cycle capability of the LTC1871 is
typically 92%. This allows the user to obtain high output
voltages from low input supply voltages.
The maximum duty cycle, D
, should be calculated at
MAX
minimum V .
IN
1871fe
13
LTC1871
APPLICATIONS INFORMATION
χ
Boost Converter: Ripple Current ΔI and the ‘ ’ Factor
applications requiring a step-up converter that is short-
circuit protected, please refer to the applications section
covering SEPIC converters.
L
χ
The constant ‘ ’ in the equation above represents the
percentage peak-to-peak ripple current in the inductor,
relative to its maximum value. For example, if 30% ripple
The minimum required saturation current of the inductor
can be expressed as a function of the duty cycle and the
load current, as follows:
χ
current is chosen, then = 0.30, and the peak current is
15% greater than the average.
IO(MAX)
For a current mode boost regulator operating in CCM,
slope compensation must be added for duty cycles above
50% in order to avoid subharmonic oscillation. For the
LTC1871, this ramp compensation is internal. Having an
internally fixed ramp compensation waveform, however,
does place some constraints on the value of the inductor
and the operating frequency. If too large an inductor is
ꢁ
ꢂ
ꢃ
ꢅ
ꢆ
IL(SAT) ꢀ 1+
•
ꢄ
ꢇ
2
1–DMAX
The saturation current rating for the inductor should be
checked at the minimum input voltage (which results
in the highest inductor current) and maximum output
current.
used, theresultingcurrentramp(ΔI )willbesmallrelative
L
Boost Converter: Operating in Discontinuous Mode
to the internal ramp compensation (at duty cycles above
50%), and the converter operation will approach voltage
mode(rampcompensationreducesthegainofthecurrent
loop). If too small an inductor is used, but the converter
is still operating in CCM (near critical conduction mode),
the internal ramp compensation may be inadequate to
prevent subharmonic oscillation. To ensure good current
mode gain and avoid subharmonic oscillation, it is recom-
mended that the ripple current in the inductor fall in the
range of 20% to 40% of the maximum average current.
Discontinuous mode operation occurs when the load cur-
rent is low enough to allow the inductor current to run out
during the off-time of the switch, as shown in Figure 9.
Oncetheinductorcurrentisnearzero,theswitchanddiode
capacitancesresonatewiththeinductancetoformdamped
ringing at 1MHz to 10MHz. If the off-time is long enough,
the drain voltage will settle to the input voltage.
Depending on the input voltage and the residual energy
in the inductor, this ringing can cause the drain of the
power MOSFET to go below ground where it is clamped
by the body diode. This ringing is not harmful to the IC
and it has not been shown to contribute significantly to
EMI. Any attempt to damp it with a snubber will degrade
the efficiency.
For example, if the maximum average input current is
χ
1A, choose a ΔI between 0.2A and 0.4A, and a value ‘ ’
L
between 0.2 and 0.4.
Boost Converter: Inductor Selection
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
the inductor value can be determined using the following
equation:
V
V
= 3.3V I
= 5V
= 200mA
IN
OUT
OUT
MOSFET DRAIN
VOLTAGE
V
IN(MIN)
2V/DIV
L =
•DMAX
ꢀIL • f
where:
INDUCTOR
CURRENT
2A/DIV
IO(MAX)
ꢀIL = ꢁ •
1–DMAX
1871 F09
2μs/DIV
Remember that boost converters are not short-circuit
protected. Under a shorted output condition, the inductor
current is limited only by the input supply capability. For
Figure 9. Discontinuous Mode Waveforms
1871fe
14
LTC1871
APPLICATIONS INFORMATION
Boost Converter: Inductor Core Selection
Pay close attention to the BV
specifications for the
DSS
MOSFETsrelativetothemaximumactualswitchvoltagein
theapplication.Manylogic-leveldevicesarelimitedto30V
or less, and the switch node can ring during the turn-off of
the MOSFET due to layout parasitics. Check the switching
waveforms of the MOSFET directly across the drain and
source terminals using the actual PC board layout (not
just on a lab breadboard!) for excessive ringing.
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ® cores. Actual core loss is independent of core
size for a fixed inductor value, but is very dependent on
the inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore, copper losses
will increase. Generally, there is a tradeoff between core
losses and copper losses that needs to be balanced.
During the switch on-time, the control circuit limits the
maximumvoltagedropacrossthepowerMOSFETtoabout
150mV (at low duty cycle). The peak inductor current
is therefore limited to 150mV/R
. The relationship
DS(ON)
between the maximum load current, duty cycle and the
of the power MOSFET is:
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper losses and preventing saturation.
Ferrite core material saturates “hard,” meaning that the
inductancecollapsesrapidlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequently, output voltage ripple. Do
not allow the core to saturate!
R
DS(ON)
1–DMAX
RDS(ON) ꢀ VSENSE(MAX) •
ꢁ
ꢂ
ꢃ
ꢅ
ꢇ
1+
•IO(MAX) •ꢈT
ꢄ
ꢆ
2
The VSENSE(MAX) term is typically 150mV at low duty
cycle, and is reduced to about 100mV at a duty cycle of
92% due to slope compensation, as shown in Figure 10.
The ρT term accounts for the temperature coefficient of
the RDS(ON) of the MOSFET, which is typically 0.4%/°C.
Figure 11 illustrates the variation of normalized RDS(ON)
over temperature for a typical power MOSFET.
Molypermalloy (from Magnetics, Inc.) is a very good,
low cost core material for toroids, but is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mμ.
Boost Converter: Power MOSFET Selection
200
150
100
50
The power MOSFET serves two purposes in the LTC1871:
itrepresentsthemainswitchingelementinthepowerpath,
and its R
represents the current sensing element
DS(ON)
for the control loop. Important parameters for the power
MOSFET include the drain-to-source breakdown voltage
(BV ),thethresholdvoltage(V
),theon-resistance
GS(TH)
DSS
DS(ON)
(R
)versusgate-to-sourcevoltage,thegate-to-source
and gate-to-drain charges (Q and Q , respectively),
the maximum drain current (I
thermal resistances (R
GS
D(MAX)
and R
GD
) and the MOSFET’s
0
0
0.2
0.4
0.5
0.8
1.0
).
TH(JA)
TH(JC)
DUTY CYCLE
The gate drive voltage is set by the 5.2V INTV low drop
1871 F10
CC
regulator. Consequently, logic-level threshold MOSFETs
should be used in most LTC1871 applications. If low input
voltage operation is expected (e.g., supplying power from
alithium-ionbatteryora3.3Vlogicsupply),thensublogic-
level threshold MOSFETs should be used.
Figure 10. Maximum SENSE Threshold Voltage vs Duty Cycle
1871fe
15
LTC1871
APPLICATIONS INFORMATION
2.0
ThepowerdissipatedbytheMOSFETinaboostconverteris:
IO(MAX)
ꢀ
ꢃ2
ꢅ
1.5
1.0
0.5
0
PFET
=
• RDS(ON) •DMAX •ꢆT
ꢂ
1–D
ꢁ
MAX ꢄ
IO(MAX)
1.85
+k • VO
•
•CRSS • f
1–D
MAX
2
The first term in the equation above represents the I R
losses in the device, and the second term, the switching
losses.Theconstant,k=1.7,isanempiricalfactorinversely
related to the gate drive current and has the dimension
of 1/current.
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
1871 F11
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
Figure 11. Normalized RDS(ON) vs Temperature
Another method of choosing which power MOSFET to
use is to check what the maximum output current is for a
T = T + P • R
J
A
FET
TH(JA)
givenR
, sinceMOSFETon-resistancesareavailable
DS(ON)
in discrete values.
The R
to be used in this equation normally includes
TH(JA)
1–DMAX
the R
for the device plus the thermal resistance from
TH(JC)
I
O(MAX) = VSENSE(MAX)
•
the case to the ambient temperature (R
). This value
TH(CA)
ꢀ
ꢁ
ꢂ
ꢄ
1+
•RDS(ON) •ꢇT
ꢃ
ꢆ
of T can then be compared to the original, assumed value
ꢅ
J
2
used in the iterative calculation process.
It is worth noting that the 1 – D
relationship between
MAX
I
and R
can cause boost converters with a
O(MAX)
DS(ON)
Boost Converter: Output Diode Selection
wide input range to experience a dramatic range of maxi-
mum input and output current. This should be taken into
consideration in applications where it is important to limit
the maximum current drawn from the input supply.
To maximize efficiency, a fast switching diode with low
forwarddropandlowreverseleakageisdesired.Theoutput
diode in a boost converter conducts current during the
switch off-time. The peak reverse voltage that the diode
must withstand is equal to the regulator output voltage.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to the
peak inductor current.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the
power MOSFET, the power dissipated by the device must
be known. This power dissipation is a function of the
duty cycle, the load current and the junction temperature
itself (due to the positive temperature coefficient of its
RDS(ON)).Asaresult,someiterativecalculationisnormally
required to determine a reasonably accurate value. Since
the controller is using the MOSFET as both a switching
and a sensing element, care should be taken to ensure
that the converter is capable of delivering the required
load current over all operating conditions (line voltage
and temperature), and for the worst-case specifications
IO(MAX)
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
I
D(PEAK) =IL(PEAK) = 1+
•
ꢃ
ꢆ
2
1–DMAX
The power dissipated by the diode is:
P = I • V
D
O(MAX)
D
and the diode junction temperature is:
T = T + P • R
J
A
D
TH(JA)
The R
to be used in this equation normally includes
TH(JA)
the R
for the device plus the thermal resistance from
TH(JC)
for V
and the R
of the MOSFET listed in
SENSE(MAX)
DS(ON)
the board to the ambient temperature in the enclosure.
the manufacturer’s data sheet.
1871fe
16
LTC1871
APPLICATIONS INFORMATION
Remember to keep the diode lead lengths short and to
observe proper switch-node layout (see Board Layout
Checklist) to avoid excessive ringing and increased dis-
sipation.
necting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic capacitor can be used
to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board (see Board
Layout section for more information on component place-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
mustbeconsideredwhenchoosingthecorrectcomponent
for a given output ripple voltage. The effects of these three
parameters (ESR, ESL and bulk C) on the output voltage
ripple waveform are illustrated in Figure 12e for a typical
boost converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
theoutputvoltage), andhowthisrippleshouldbedivided
between the ESR step and the charging/discharging ΔV.
For the purpose of simplicity we will choose 2% for the
maximumoutputripple,tobedividedequallybetweenthe
ESR step and the charging/discharging ΔV. This percent-
age ripple will change, depending on the requirements
of the application, and the equations provided below can
easily be modified.
Theoutputcapacitorinaboostregulatorexperienceshigh
RMS ripple currents, as shown in Figure 12. The RMS
output capacitor ripple current is:
VO – V
V
IN(MIN)
IRMS(COUT) ꢀIO(MAX) •
IN(MIN)
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
Manufacturers such as Nichicon, United Chemicon and
Sanyoshouldbeconsideredforhighperformancethrough-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest product of
ESR and size of any aluminum electrolytic, at a somewhat
higher price.
0.01• VO
ESRCOUT ꢀ
IIN(PEAK)
where:
IO(MAX)
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
IIN(PEAK)= 1+
•
ꢃ
ꢆ
2
1–DMAX
In surface mount applications, multiple capacitors may
have to be placed in parallel in order to meet the ESR or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount packages. In the case of
tantalum, it is critical that the capacitors have been surge
tested for use in switching power supplies. An excellent
choice is AVX TPS series of surface mount tantalum. Also,
ceramic capacitors are now available with extremely low
ESR, ESL and high ripple current ratings.
For the bulk C component, which also contributes 1% to
the total ripple:
IO(MAX)
COUT ꢀ
0.01• VO • f
Formanydesignsitispossibletochooseasinglecapacitor
type that satisfies both the ESR and bulk C requirements
forthedesign.Incertaindemandingapplications,however,
the ripple voltage can be improved significantly by con-
1871fe
17
LTC1871
APPLICATIONS INFORMATION
L
D
V
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure
to specify surge-tested capacitors!
OUT
V
SW
C
R
L
IN
OUT
12a. Circuit Diagram
Burst Mode Operation and Considerations
I
IN
I
L
The choice of MOSFET R
and inductor value also
DS(ON)
determines the load current at which the LTC1871 enters
Burst Mode operation. When bursting, the controller
clamps the peak inductor current to approximately:
12b. Inductor and Input Currents
30mV
RDS(ON)
IBURST(PEAK)
=
I
SW
t
ON
which represents about 20% of the maximum 150mV
SENSE pin voltage. The corresponding average current
dependsupontheamountofripplecurrent.Lowerinductor
12c. Switch Current
I
values (higher ΔI ) will reduce the load current at which
D
L
t
OFF
I
O
Burst Mode operations begins, since it is the peak current
that is being clamped.
12d. Diode and Output Currents
The output voltage ripple can increase during Burst Mode
ΔV
COUT
operation if ΔI is substantially less than I
. This can
L
BURST
occur if the input voltage is very low or if a very large
inductor is chosen. At high duty cycles, a skipped cycle
causes the inductor current to quickly decay to zero.
V
OUT
(AC)
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
ΔV
ESR
However, because ΔI is small, it takes multiple cycles
L
for the current to ramp back up to I
. Dur-
BURST(PEAK)
12e. Output Voltage Ripple Waveform
Figure 12. Switching Waveforms for a Boost Converter
Boost Converter: Input Capacitor Selection
ing this inductor charging interval, the output capacitor
must supply the load current and a significant droop in
the output voltage can occur. Generally, it is a good idea
to choose a value of inductor ΔI between 25% and 40%
L
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input and the input current waveform
is continuous (see Figure 12b). The input voltage source
impedance determines the size of the input capacitor,
which is typically in the range of 10μF to 100μF. A low ESR
capacitor is recommended, although it is not as critical as
for the output capacitor.
of I
. The alternative is to either increase the value
of the output capacitor or disable Burst Mode operation
IN(MAX)
using the MODE/SYNC pin.
Burst Mode operation can be defeated by connecting the
MODE/SYNC pin to a high logic-level voltage (either with
a control input or by connecting this pin to INTV ). In
CC
this mode, the burst clamp is removed, and the chip can
operateatconstantfrequencyfromcontinuousconduction
mode (CCM) at full load, down into deep discontinuous
conduction mode (DCM) at light load. Prior to skipping
pulsesatverylightload(i.e.,<5%offullload),thecontrol-
The RMS input capacitor ripple current for a boost con-
verter is:
V
IN(MIN)
I
RMS(CIN) = 0.3•
•DMAX
L • f
ler will operate with a minimum switch on-time in DCM.
1871fe
18
LTC1871
APPLICATIONS INFORMATION
Table 1. Recommended Component Manufacturers
VENDOR
COMPONENTS
TELEPHONE
(207) 282-5111
(952) 894-9590
(847) 639-6400
(407) 241-7876
(805) 446-4800
(408) 822-2126
(516) 847-3000
(310) 322-3331
(361) 992-7900
(408) 986-0424
(800) 245-3984
(617) 926-0404
(770) 436-1300
(847) 843-7500
(602) 244-6600
(714) 373-7334
(619) 661-6835
(847) 956-0667
(408) 573-4150
(562) 596-1212
(972) 243-4321
(408) 432-8020
(847) 699-3430
(847) 696-2000
(605) 665-9301
(800) 554-5565
(207) 324-4140
(631) 543-7100
WEB ADDRESS
AVX
Capacitors
Inductors, Transformers
Inductors
avxcorp.com
BH Electronics
Coilcraft
bhelectronics.com
coilcraft.com
Coiltronics
Diodes, Inc
Fairchild
Inductors
coiltronics.com
diodes.com
Diodes
MOSFETs
fairchildsemi.com
generalsemiconductor.com
irf.com
General Semiconductor
International Rectifier
IRC
Diodes
MOSFETs, Diodes
Sense Resistors
Tantalum Capacitors
Toroid Cores
Diodes
irctt.com
Kemet
kemet.com
Magnetics Inc
Microsemi
Murata-Erie
Nichicon
mag-inc.com
microsemi.com
murata.co.jp
Inductors, Capacitors
Capacitors
nichicon.com
onsemi.com
On Semiconductor
Panasonic
Sanyo
Diodes
Capacitors
panasonic.com
sanyo.co.jp
Capacitors
Sumida
Inductors
sumida.com
Taiyo Yuden
TDK
Capacitors
t-yuden.com
Capacitors, Inductors
Heat Sinks
component.tdk.com
aavidthermalloy.com
nec-tokinamerica.com
tokoam.com
Thermalloy
Tokin
Capacitors
Toko
Inductors
United Chemicon
Vishay/Dale
Vishay/Siliconix
Vishay/Sprague
Zetex
Capacitors
chemi-com.com
vishay.com
Resistors
MOSFETs
vishay.com
Capacitors
vishay.com
Small-Signal Discretes
zetex.com
Pulse skipping prevents a loss of control of the output at
very light loads and reduces output voltage ripple.
and which change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for the majority
of the losses in LTC1871 application circuits:
Efficiency Considerations: How Much Does V
DS
Sensing Help?
1. The supply current into V . The V current is the sum
IN
IN
The efficiency of a switching regulator is equal to the out-
put power divided by the input power (×100%). Percent
efficiency can be expressed as:
of the DC supply current I (given in the Electrical Char-
Q
acteristics)andtheMOSFETdriverandcontrolcurrents.
The DC supply current into the V pin is typically about
IN
550μA and represents a small power loss (much less
% Efficiency = 100% – (L1 + L2 + L3 + …),
than 1%) that increases with V . The driver current
IN
where L1, L2, etc. are the individual loss components as a
percentage of the input power. It is often useful to analyze
individuallossestodeterminewhatislimitingtheefficiency
resultsfromswitchingthegatecapacitanceofthepower
MOSFET; this current is typically much larger than the
DC current. Each time the MOSFET is switched on and
1871fe
19
LTC1871
APPLICATIONS INFORMATION
then off, a packet of gate charge Q is transferred from
3. The losses in the inductor are simply the DC input cur-
rent squared times the winding resistance. Expressing
this loss as a function of the output current yields:
G
INTV to ground. The resulting dQ/dt is a current that
CC
must be supplied to the INTV capacitor through the
CC
ꢀ
ꢃ2
ꢅ
V pin by an external supply. If the IC is operating in
IN
IO(MAX)
CCM:
PR(WINDING)
=
•RW
ꢂ
1–D
ꢁ
MAX ꢄ
I
≈ I = f • Q
Q G
Q(TOT)
4. Losses in the boost diode. The power dissipation in the
boost diode is:
P = V • (I + f • Q )
IC
IN
Q
G
2. Power MOSFET switching and conduction losses. The
technique of using the voltage drop across the power
MOSFETtoclosethecurrentfeedbackloopwaschosen
because of the increased efficiency that results from
not having a sense resistor. The losses in the power
MOSFET are equal to:
P
= I
• V
O(MAX) D
DIODE
The boost diode can be a major source of power loss
in a boost converter. For the 3.3V input, 5V output at
7A example given above, a Schottky diode with a 0.4V
forwardvoltagewoulddissipate2.8W,whichrepresents
7%oftheinputpower.Diodelossescanbecomesignifi-
cant at low output voltages where the forward voltage
is a significant percentage of the output voltage.
ꢀ
ꢂ
ꢃ2
ꢅ
IO(MAX)
PFET
=
• RDS(ON) •DMAX •ꢆT
1–D
ꢁ
MAX ꢄ
IO(MAX)
5. Other losses, including C and C ESR dissipation and
1.85
IN
O
+k • VO
•
•CRSS • f
inductor core losses, generally account for less than
1–D
MAX
2% of the total additional loss.
2
The I R power savings that result from not having a
discrete sense resistor can be calculated almost by
inspection.
Checking Transient Response
The regulator loop response can be verified by looking at
theloadtransientresponse.Switchingregulatorsgenerally
take several cycles to respond to an instantaneous step
ꢀ
ꢃ2
ꢅ
IO(MAX)
PR(SENSE)
=
•RSENSE •DMAX
ꢂ
1–D
ꢁ
MAX ꢄ
in resistive load current. When the load step occurs, V
O
immediately shifts by an amount equal to (ΔI
)(ESR),
To understand the magnitude of the improvement with
LOAD
and then C begins to charge or discharge (depending on
this V sensing technique, consider the 3.3V input,
O
DS
the direction of the load step) as shown in Figure 13. The
5V output power supply shown in Figure 1. The maxi-
mum load current is 7A (10A peak) and the duty cycle
is 39%. Assuming a ripple current of 40%, the peak
inductor current is 13.8A and the average is 11.5A.
With a maximum sense voltage of about 140mV, the
sense resistor value would be 10mΩ, and the power
dissipated in this resistor would be 514mW at maxi-
mum output current. Assuming an efficiency of 90%,
this sense resistor power dissipation represents 1.3%
of the overall input power. In other words, for this ap-
regulator feedback loop acts on the resulting error amp
output signal to return V to its steady-state value. During
O
this recovery time, V can be monitored for overshoot or
O
ringing that would indicate a stability problem.
V
V
= 3.3V
OUT
MODE/SYNC = INTV
IN
= 5V
CC
(PULSE-SKIP MODE)
I
OUT
2V/DIV
plication, the use of V sensing would increase the
DS
V
(AC)
OUT
100mV/DIV
efficiency by approximately 1.3%.
For more details regarding the various terms in these
equations, please refer to the section Boost Converter:
Power MOSFET Selection.
1871 F13
100μs/DIV
Figure 13. Load Transient Response for a 3.3V Input,
5V Output Boost Converter Application, 0.7A to 7A Step
1871fe
20
LTC1871
APPLICATIONS INFORMATION
A second, more severe transient can occur when con-
necting loads with large (>1μF) supply bypass capacitors.
The discharged bypass capacitors are effectively put in
can be used. Because the duty cycle is 39%, the maxi-
mum SENSE pin threshold voltage is reduced from its
low duty cycle typical value of 150mV to approximately
140mV. Assuming a MOSFET junction temperature of
parallel with C , causing a nearly instantaneous drop in
O
V . No regulator can deliver enough current to prevent
125°C, the room temperature MOSFET R
should
O
DS(ON)
this problem if the load switch resistance is low and it is
driven quickly. The only solution is to limit the rise time
of the switch drive in order to limit the inrush current
di/dt to the load.
be less than:
1–DMAX
RDS(ON) ꢀ VSENSE(MAX) •
ꢁ
ꢂ
ꢃ
ꢅ
ꢇ
1+
•IO(MAX) •ꢈT
ꢄ
ꢆ
2
1– 0.39
Boost Converter Design Example
= 0.140V •
= 6.8mꢉ
0.4
2
ꢂ
ꢃ
ꢅ
ꢆ
1+
•7A •1.5
Thedesignexamplegivenherewillbeforthecircuitshown
in Figure 1. The input voltage is 3.3V, and the output is 5V
at a maximum load current of 7A (10A peak).
ꢄ
ꢇ
The MOSFET used was the Fairchild FDS7760A, which
has a maximum R of 8mΩ at 4.5V V , a BV
DSS
DS(ON)
GS
1. The duty cycle is:
of greater than 30V, and a gate charge of 37nC at 5V
ꢀ
IN ꢃ
VO + VD – V
5+ 0.4– 3.3
5+ 0.4
V .
GS
D=
=
= 38.9%
ꢂ
ꢅ
VO + VD
ꢁ
ꢄ
6. The diode for this design must handle a maximum
DC output current of 10A and be rated for a minimum
2. Pulse-skip operation is chosen so the MODE/SYNC pin
reverse voltage of V , or 5V. A 25A, 15V diode from
OUT
is shorted to INTV .
CC
On Semiconductor (MBRB2515L) was chosen for its
3. The operating frequency is chosen to be 300kHz to
reduce the size of the inductor. From Figure 5, the
resistor from the FREQ pin to ground is 80k.
high power dissipation capability.
7. The output capacitor usually consists of a high valued
bulk C connected in parallel with a lower valued, low
ESRceramic.Basedonamaximumoutputripplevoltage
of 1%, or 50mV, the bulk C needs to be greater than:
4. An inductor ripple current of 40% of the maximum load
current is chosen, so the peak input current (which is
also the minimum saturation current) is:
IO(MAX)
IOUT(MAX)
COUT ꢀ
=
ꢀ
7
ꢁ
ꢂ
ꢄ
ꢅ
0.01• VOUT • f
7A
I
= 1+
•
=1.2•
= 13.8A
ꢃ
ꢆ
IN(PEAK)
2
1–DMAX
1– 0.39
= 466μF
0.01•5V •300kHz
The inductor ripple current is:
IO(MAX)
7
ꢀIL = ꢁ •
= 0.4•
= 4.6A
The RMS ripple current rating for this capacitor needs
to exceed:
1–DMAX
1– 0.39
And so the inductor value is:
VO – V
V
IN(MIN)
I
RMS(COUT) ꢀIO(MAX)
•
=
V
3.3V
4.6A •300kHz
IN(MIN)
IN(MIN)
L =
•DMAX
=
•0.39= 0.93μH
ꢀIL • f
5V – 3.3V
3.3V
7A •
= 5A
The component chosen is a 1μH inductor made by
Sumida (part number CEP125-H 1ROMH) which has
a saturation current of greater than 20A.
To satisfy this high RMS current demand, four
150μF Panasonic capacitors (EEFUEOJ151R) are
required. In parallel with these bulk capacitors, two
22μF, low ESR (X5R) Taiyo Yuden ceramic capacitors
1871fe
5. With the input voltage to the IC bootstrapped to the
output of the power supply (5V), a logic-level MOSFET
21
LTC1871
APPLICATIONS INFORMATION
(JMK325BJ226MM)areaddedforHFnoisereduction.
Check the output ripple with a single oscilloscope
probe connected directly across the output capacitor
terminals, where the HF switching currents flow.
should be kept as tight as possible to reduce inductive
ringing. Excess inductance can cause increased stress
on the power MOSFET and increase HF noise on the
output. If low ESR ceramic capacitors are used on the
output to reduce output noise, place these capacitors
close to the boost diode in order to keep the series
inductance to a minimum.
8. The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and
the amount of input ripple the converter will safely tol-
erate. For this particular design and lab setup a 100μF
Sanyo Poscap (6TPC 100M), in parallel with two 22μF
Taiyo Yuden ceramic capacitors (JMK325BJ226MM)
is required (the input and return lead lengths are kept
to a few inches, but the peak input current is close to
20A!). As with the output node, check the input ripple
with a single oscilloscope probe connected across the
input capacitor terminals.
5. Check the stress on the power MOSFET by measuring
its drain-to-source voltage directly across the device
terminals(referencethegroundofasinglescopeprobe
directly to the source pad on the PC board). Beware
of inductive ringing which can exceed the maximum
specified voltage rating of the MOSFET. If this ringing
cannot be avoided and exceeds the maximum rating
of the device, either choose a higher voltage device
or specify an avalanche-rated power MOSFET. Not all
MOSFETs are created equal (some are more equal than
others).
PC Board Layout Checklist
1. Inordertominimizeswitchingnoiseandimproveoutput
load regulation, the GND pin of the LTC1871 should be
connected directly to 1) the negative terminal of the
INTVCC decoupling capacitor, 2) the negative terminal
of the output decoupling capacitors, 3) the source of
the power MOSFET or the bottom terminal of the sense
resistor, 4) the negative terminal of the input capacitor
and 5) at least one via to the ground plane immediately
adjacent to Pin 6. The ground trace on the top layer of
the PC board should be as wide and short as possible
to minimize series resistance and inductance.
6. Place the small-signal components away from high
frequency switching nodes. In the layout shown in
Figure 14, all of the small-signal components have
been placed on one side of the IC and all of the power
components have been placed on the other. This also
allows the use of a pseudo-Kelvin connection for the
signal ground, where high di/dt gate driver currents
flow out of the IC ground pin in one direction (to the
bottom plate of the INTV decoupling capacitor) and
CC
small-signal currents flow in the other direction.
2. Beware of ground loops in multiple layer PC boards.
Try to maintain one central ground node on the board
and use the input capacitor to avoid excess input ripple
for high output current power supplies. If the ground
plane is to be used for high DC currents, choose a path
away from the small-signal components.
7. If a sense resistor is used in the source of the power
MOSFET, minimize the capacitance between the SENSE
pin trace and any high frequency switching nodes. The
LTC1871containsaninternalleadingedgeblankingtime
of approximately 180ns, which should be adequate for
most applications.
3. Place the C
capacitor immediately adjacent to the
8. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC1871 in order
to keep the high impedance FB node short.
VCC
INTV and GND pins on the IC package. This capaci-
CC
tor carries high di/dt MOSFET gate drive currents. A
low ESR and ESL 4.7μF ceramic capacitor works well
here.
4. The high di/dt loop from the bottom terminal of the
output capacitor, through the power MOSFET, through
the boost diode and back through the output capacitors
9. Forapplicationswithmultipleswitchingpowerconvert-
ers connected to the same input supply, make sure
1871fe
22
LTC1871
APPLICATIONS INFORMATION
V
IN
L1
JUMPER
R3
R4
R
R
C
C
C
J1
C
IN
PIN 1
LTC1871
R2
R1
T
C
VCC
SWITCH NODE IS ALSO
THE HEAT SPREADER
FOR L1, M1, D1
M1
PSEUDO-KELVIN
SIGNAL GROUND
CONNECTION
C
C
OUT
OUT
D1
VIAS TO GROUND
PLANE
V
OUT
TRUE REMOTE
OUTPUT SENSING
1871 F14
BULK C
LOW ESR CERAMIC
Figure 14. LTC1871 Boost Converter Suggested Layout
V
IN
R3
R4
L1
J1
1
2
10
9
C
SWITCH
NODE
C
RUN
SENSE
R
C
I
V
IN
TH
LTC1871
R1
D1
3
4
5
8
7
6
FB
INTV
CC
R2
FREQ
GATE
GND
M1
R
T
+
MODE/
SYNC
C
C
VCC
IN
GND
C
PSEUDO-KELVIN
GROUND CONNECTION
OUT
+
V
OUT
1871 F15
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 15. LTC1871 Boost Converter Layout Diagram
1871fe
23
LTC1871
APPLICATIONS INFORMATION
that the input filter capacitor for the LTC1871 is not
shared with other converters. AC input current from
anotherconvertercouldcausesubstantialinputvoltage
ripple, and this could interfere with the operation of the
LTC1871. A few inches of PC trace or wire (L ≈ 100nH)
and size. All of the SEPIC applications information that
follows assumes L1 = L2 = L.
SEPIC Converter: Duty Cycle Considerations
ForaSEPICconverteroperatinginacontinuousconduction
mode (CCM), the duty cycle of the main switch is:
between the C of the LTC1871 and the actual source
IN
V
should be sufficient to prevent current sharing
IN
ꢀ
ꢃ
ꢅ
VO + VD
V + V + V
problems.
D=
ꢂ
ꢁ
D ꢄ
IN
O
SEPIC Converter Applications
where V is the forward voltage of the diode. For convert-
ers where the input voltage is close to the output voltage
the duty cycle is near 50%.
D
The LTC1871 is also well suited to SEPIC (single-ended
primaryinductanceconverter)converterapplications. The
SEPIC converter shown in Figure 16 uses two inductors.
The advantage of the SEPIC converter is the input voltage
may be higher or lower than the output voltage, and the
output is short-circuit protected.
The maximum output voltage for a SEPIC converter is:
DMAX
1–DMAX
1
VO(MAX) = V + V
– V
D 1–DMAX
(
)
IN
D
C1
D1
L1
V
OUT
•
+
The maximum duty cycle of the LTC1871 is typically
92%.
+
+
R
L
V
IN
SW
L2
C
OUT
•
SEPIC Converter: The Peak and Average Input
Currents
16a. SEPIC Topology
V
IN
The control circuit in the LTC1871 is measuring the input
V
OUT
•
+
+
current (either using the R
of the power MOSFET
DS(ON)
+
R
L
V
IN
or by means of a sense resistor in the MOSFET source),
so the output current needs to be reflected back to the
input in order to dimension the power MOSFET properly.
Based on the fact that, ideally, the output power is equal
to the input power, the maximum input current for a SEPIC
converter is:
•
16b. Current Flow During Switch On-Time
V
IN
D1
V
OUT
•
+
+
+
R
L
V
IN
DMAX
1–DMAX
IIN(MAX) =IO(MAX) •
•
16c. Current Flow During Switch Off-Time
Figures 16. SEPIC Topology and Current Flow
Thepeak input current is:
DMAX
1–DMAX
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
I
= 1+
•I
•
ꢃ
ꢆ
IN(PEAK)
O(MAX)
The first inductor, L1, together with the main switch,
resembles a boost converter. The second inductor, L2,
together with the output diode D1, resembles a flyback or
buck-boost converter. The two inductors L1 and L2 can be
independentbutcanalsobewoundonthesamecoresince
identical voltages are applied to L1 and L2 throughout the
switching cycle. By making L1 = L2 and winding them on
the same core the input ripple is reduced along with cost
2
The maximum duty cycle, D
, should be calculated at
MAX
minimum V .
IN
Theconstant‘χ’representsthefractionofripplecurrentin
the inductor relative to its maximum value. For example, if
30% ripple current is chosen, then χ = 0.30 and the peak
current is 15% greater than the average.
1871fe
24
LTC1871
APPLICATIONS INFORMATION
It is worth noting here that SEPIC converters that operate
at high duty cycles (i.e., that develop a high output volt-
age from a low input voltage) can have very high input
currents, relative to the output current. Be sure to check
that the maximum load current will not overload the input
supply.
example, aCoiltronixCTX10-4isa10μHinductorwithtwo
windings.Withthewindingsinparallel,10μHinductanceis
obtained with a current rating of 4A (the number of turns
hasn’t changed, but the wire diameter has doubled). Split-
ting the two windings creates two 10μH inductors with a
currentratingof2Aeach. Therefore, substituting2Lyields
the following equation for coupled inductors:
SEPIC Converter: Inductor Selection
V
IN(MIN)
L1=L2=
•DMAX
For most SEPIC applications the equal inductor values
will fall in the range of 10μH to 100μH. Higher values will
reduce the input ripple voltage and reduce the core loss.
Lower inductor values are chosen to reduce physical size
and improve transient response.
2• ꢀIL • f
Specify the maximum inductor current to safely handle
I
specified in the equation above. The saturation
L(PK)
current rating for the inductor should be checked at the
minimum input voltage (which results in the highest
inductor current) and maximum output current.
Like the boost converter, the input current of the SEPIC
converter is calculated at full load current and minimum
inputvoltage.Thepeakinductorcurrentcanbesignificantly
higher than the output current, especially with smaller in-
ductors and lighter loads. The following formulas assume
CCM operation and calculate the maximum peak inductor
SEPIC Converter: Power MOSFET Selection
The power MOSFET serves two purposes in the LTC1871:
itrepresentsthemainswitchingelementinthepowerpath,
and its R
represents the current sensing element
currents at minimum V :
DS(ON)
IN
for the control loop. Important parameters for the power
MOSFET include the drain-to-source breakdown voltage
VO + VD
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
IL1(PEAK) = 1+
•I
•
ꢃ
ꢆ
O(MAX)
2
V
(BV ),thethresholdvoltage(V
),theon-resistance
IN(MIN)
DSS
GS(TH)
(R
)versusgate-to-sourcevoltage,thegate-to-source
DS(ON)
V
IN(MIN) + VD
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
and gate-to-drain charges (Q and Q , respectively),
IL2(PEAK) = 1+
•I
ꢆ
•
GS
GD
ꢃ
O(MAX)
2
V
IN(MIN)
the maximum drain current (I
) and the MOSFET’s
D(MAX)
thermal resistances (R
and R
).
TH(JA)
TH(JC)
The ripple current in the inductor is typically 20% to 40%
(i.e., a range of ‘χ’ from 0.20 to 0.40) of the maximum
The gate drive voltage is set by the 5.2V INTV low
CC
dropout regulator. Consequently, logic-level threshold
MOSFETs should be used in most LTC1871 applications.
If low input voltage operation is expected (e.g., supplying
power from a lithium-ion battery), then sublogic-level
threshold MOSFETs should be used.
averageinputcurrentoccurringatV
andI
and
IN(MIN)
O(MAX)
ΔI = ΔI . Expressing this ripple current as a function of
L1
L2
the output current results in the following equations for
calculating the inductor value:
V
IN(MIN)
L =
•DMAX
The maximum voltage that the MOSFET switch must
sustain during the off-time in a SEPIC converter is equal
ꢀIL • f
where:
to the sum of the input and output voltages (V + V ).
O
IN
DMAX
1–DMAX
As a result, careful attention must be paid to the BV
DSS
ꢀIL = ꢁ •IO(MAX)
•
specifications for the MOSFETs relative to the maximum
actual switch voltage in the application. Many logic-level
devices are limited to 30V or less. Check the switching
waveforms directly across the drain and source terminals
By making L1 = L2 and winding them on the same core,
the value of inductance in the equation above is replace
by 2L due to mutual inductance. Doing this maintains the
sameripplecurrentandenergystorageintheinductors.For
of the power MOSFET to ensure the V remains below
DS
the maximum rating for the device.
1871fe
25
LTC1871
APPLICATIONS INFORMATION
During the MOSFET’s on-time, the control circuit limits
the maximum voltage drop across the power MOSFET to
about150mV(atlowdutycycle).Thepeakinductorcurrent
ThepowerdissipatedbytheMOSFETinaSEPICconverter
is:
ꢀ
ꢃ2
ꢅ
DMAX
P
FET = IO(MAX)
•
•RDS(ON) •DMAX •ꢆT
is therefore limited to 150mV/R . The relationship
DS(ON)
ꢂ
1–D
ꢁ
MAX ꢄ
between the maximum load current, duty cycle and the
of the power MOSFET is:
+ k • VIN(MIN) + VO 1.85 •IO(MAX)
•
•CRSS • f
DMAX
1–DMAX
R
DS(ON)
(
)
VSENSE(MAX)
1
1
RDS(ON) ꢀ
•
•
2
The first term in the equation above represents the I R
losses in the device and the second term, the switching
losses.Theconstant k=1.7isanempiricalfactorinversely
related to the gate drive current and has the dimension
of 1/current.
ꢁ
IO(MAX)
ꢂ
ꢃ
ꢅ
ꢇ
ꢂ
ꢅ
VO + VD
1+
•ꢈ
T
ꢄ
+1
ꢄ
ꢇ
ꢆ
2
V
ꢃ
ꢆ
IN(MIN)
The V
term is typically 150mV at low duty cycle
SENSE(MAX)
and is reduced to about 100mV at a duty cycle of 92% due
toslopecompensation,asshowninFigure8.Theconstant
‘χ’ in the denominator represents the ripple current in the
inductors relative to their maximum current. For example,
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
if 30% ripple current is chosen, then χ = 0.30. The ρ term
T
T = T + P •R
J
A
FET TH(JA)
accounts for the temperature coefficient of the R
of
DS(ON)
The R
the R
to be used in this equation normally includes
theMOSFET,whichistypically0.4%/°C.Figure9illustrates
TH(JA)
for the device plus the thermal resistance from
the variation of normalized R
a typical power MOSFET.
over temperature for
TH(JC)
DS(ON)
the board to the ambient temperature in the enclosure.
This value of T can then be used to check the original
J
Another method of choosing which power MOSFET to
use is to check what the maximum output current is for a
assumption for the junction temperature in the iterative
calculation process.
given R
since MOSFET on-resistances are available
DS(ON)
in discrete values.
VSENSE(MAX)
SEPIC Converter: Output Diode Selection
1
1
IO(MAX) ꢀ
•
•
To maximize efficiency, a fast-switching diode with low
forwarddropandlowreverseleakageisdesired.Theoutput
diode in a SEPIC converter conducts current during the
switch off-time. The peak reverse voltage that the diode
ꢁ
RDS(ON)
ꢂ
ꢃ
ꢅ
ꢆ
ꢂ
ꢅ
VO + VD
1+
•ꢈ
T
ꢄ
ꢇ
+1
ꢄ
ꢇ
2
V
ꢃ
ꢆ
IN(MIN)
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
must withstand is equal to V
+ V . The average
IN(MAX)
O
forward current in normal operation is equal to the output
current, and the peak current is equal to:
In order to calculate the junction temperature of the
power MOSFET, the power dissipated by the device must
be known. This power dissipation is a function of the
duty cycle, the load current and the junction temperature
itself. As a result, some iterative calculation is normally
required to determine a reasonably accurate value. Since
the controller is using the MOSFET as both a switching
and a sensing element, care should be taken to ensure
that the converter is capable of delivering the required
load current over all operating conditions (load, line and
temperature) and for the worst-case specifications for
ꢁ
ꢄ
VO + V
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
ID(PEAK) = 1+
•I
•
D +1
ꢃ
ꢆ
ꢃ
ꢆ
O(MAX)
2
V
ꢂ
ꢅ
IN(MIN)
The power dissipated by the diode is:
P = I • V
D
O(MAX)
D
and the diode junction temperature is:
T = T + P • R
J
A
D
TH(JA)
The R
to be used in this equation normally includes
TH(JA)
the R
for the device plus the thermal resistance from
TH(JC)
V
and the R
of the MOSFET listed in the
SENSE(MAX)
manufacturer’s data sheet.
DS(ON)
the board to the ambient temperature in the enclosure.
1871fe
26
LTC1871
APPLICATIONS INFORMATION
SEPIC Converter: Output Capacitor Selection
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ΔV.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESRstepandthecharging/dischargingΔV.Thispercentage
ripple will change, depending on the requirements of the
application, and the equations provided below can easily
be modified.
Because of the improved performance of today’s electro-
lytic, tantalum and ceramic capacitors, engineers need
to consider the contributions of ESR (equivalent series
resistance), ESL (equivalent series inductance) and the
bulk capacitance when choosing the correct component
for a given output ripple voltage. The effects of these three
parameters (ESR, ESL, and bulk C) on the output voltage
ripple waveform are illustrated in Figure 17 for a typical
coupled-inductor SEPIC converter.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
I
IN
I
L1
SW
ON
SW
OFF
0.01• VO
ESRCOUT ꢀ
17a. Input Inductor Current
ID(PEAK)
I
O
I
where:
L2
ꢁ
ꢄ
VO + V
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
ID(PEAK) = 1+
•I
•
D +1
ꢃ
ꢆ
ꢃ
ꢆ
O(MAX)
17b. Output Inductor Current
2
V
ꢂ
ꢅ
IN(MIN)
I
I
IN
O
For the bulk C component, which also contributes 1% to
the total ripple:
I
C1
IO(MAX)
COUT ꢀ
17c. DC Coupling Capacitor Current
0.01• VO • f
Formanydesignsitispossibletochooseasinglecapacitor
type that satisfies both the ESR and bulk C requirements
forthedesign.Incertaindemandingapplications,however,
the ripple voltage can be improved significantly by con-
necting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic or tantalum capacitor
can be used to supply the required bulk C.
I
D1
I
O
17d. Diode Current
V
OUT
(AC)
ΔV
COUT
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board (see Board
Layout section for more information on component place-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
ΔV
ESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
17e. Output Ripple Voltage
Figure 17. SEPIC Converter Switching Waveforms
designed PC board.
1871fe
27
LTC1871
APPLICATIONS INFORMATION
The output capacitor in a SEPIC regulator experiences
high RMS ripple currents, as shown in Figure 17. The
RMS output capacitor ripple current is:
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure
to specify surge-tested capacitors!
VO
IRMS(COUT) =IO(MAX) •
V
IN(MIN)
SEPIC Converter: Selecting the DC Coupling Capacitor
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
ThecouplingcapacitorC1inFigure16seesnearlyarectan-
gular current waveform as shown in Figure 17. During the
switch off-time the current through C1 is I (V /V ) while
O
O
IN
approximately –I flows during the on-time. This current
O
waveform creates a triangular ripple voltage on C1:
IO(MAX)
VO
C1• f V + VO + VD
Manufacturers such as Nichicon, United Chemicon and
Sanyoshouldbeconsideredforhighperformancethrough-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest product of
ESR and size of any aluminum electrolytic, at a somewhat
higher price.
ꢀVC1(PꢁP)
=
•
IN
The maximum voltage on C1 is then:
ꢀVC1(PꢁP)
V
C1(MAX) = V +
IN
2
In surface mount applications, multiple capacitors may
have to be placed in parallel in order to meet the ESR or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount packages. In the case of
tantalum, it is critical that the capacitors have been surge
tested for use in switching power supplies. An excellent
choice is AVX TPS series of surface mount tantalum. Also,
ceramic capacitors are now available with extremely low
ESR, ESL and high ripple current ratings.
which is typically close to V
through C1 is:
. The ripple current
IN(MAX)
VO + VD
IRMS(C1) =IO(MAX) •
V
IN(MIN)
The value chosen for the DC coupling capacitor normally
starts with the minimum value that will satisfy 1) the RMS
current requirement and 2) the peak voltage requirement
(typically close to V ). Low ESR ceramic and tantalum
IN
capacitors work well here.
SEPIC Converter: Input Capacitor Selection
SEPIC Converter Design Example
The input capacitor of a SEPIC converter is less critical
than the output capacitor due to the fact that an inductor
is in series with the input and the input current waveform
istriangularinshape. Theinputvoltagesourceimpedance
determines the size of the input capacitor which is typi-
cally in the range of 10μF to 100μF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
Thedesignexamplegivenherewillbeforthecircuitshown
in Figure 18. The input voltage is 5V to 15V and the output
is 12V at a maximum load current of 1.5A (2A peak).
1. The duty cycle range is:
ꢀ
ꢃ
ꢅ
VO + VD
V + V + V
D=
= 45.5% to 71.4%
ꢂ
ꢁ
D ꢄ
IN
O
The RMS input capacitor ripple current for a SEPIC con-
2. The operating mode chosen is pulse skipping, so the
verter is:
MODE/SYNC pin is shorted to INTV .
1
CC
IRMS(CIN)
=
• ꢀIL
12
1871fe
28
LTC1871
APPLICATIONS INFORMATION
3. The operating frequency is chosen to be 300kHz to
reduce the size of the inductors; the resistor from the
FREQ pin to ground is 80k.
6. The diode for this design must handle a maximum
DC output current of 2A and be rated for a minimum
reverse voltage of V + V , or 27V. A 3A, 40V diode
IN
OUT
from International Rectifier (30BQ040) is chosen for its
small size, relatively low forward drop and acceptable
reverse leakage at high temp.
4. Aninductorripplecurrentof40%ischosen,sothepeak
input current (which is also the minimum saturation
current) is:
7. The output capacitor usually consists of a high valued
bulkCconnectedinparallelwithalowervalued,lowESR
ceramic. Based on a maximum output ripple voltage of
1%, or 120mV, the bulk C needs to be greater than:
VO + VD
ꢀ
ꢁ
ꢂ
ꢄ
ꢅ
IL1(PEAK) = 1+
•I
•
ꢃ
ꢆ
O(MAX)
2
V
IN(MIN)
0.4
2
12+ 0.5
ꢁ
ꢄ
ꢅ
= 1+
•1.5•
= 4.5A
ꢃ
ꢆ
IOUT(MAX)
ꢂ
5
COUT ꢀ
=
0.01• VOUT • f
1.5A
The inductor ripple current is:
DMAX
1–DMAX
= 41μF
ꢀIL = ꢁ •IO(MAX)
•
0.01•12V •300kHz
0.714
1– 0.714
The RMS ripple current rating for this capacitor needs
to exceed:
= 0.4•1.5•
=1.5A
VO
I
RMS(COUT) ꢀIO(MAX)
•
=
And so the inductor value is:
V
IN(MIN)
V
5
IN(MIN)
L =
•DMAX
=
•0.714= 4μH
12V
5V
2• ꢀIL • f
2•1.5•300k
1.5A •
= 2.3A
T
he component chosen is a BH Electronics BH510-
1007, which has a saturation current of 8A.
To satisfy this high RMS current demand, two 47μF
Kemetcapacitors(T495X476K020AS)arerequired.Asa
result, the output ripple voltage is a low 50mV to 60mV.
Inparallelwiththesetantalums,two10μF,lowESR(X5R)
TaiyoYudenceramiccapacitors(TMK432BJ106MM)are
added for HF noise reduction. Check the output ripple
with a single oscilloscope probe connected directly
across the output capacitor terminals, where the HF
switching currents flow.
5. With an minimum input voltage of 5V, only logic-level
power MOSFETs should be considered. Because the
maximum duty cycle is 71.4%, the maximum SENSE
pin threshold voltage is reduced from its low duty
cycle typical value of 150mV to approximately 120mV.
Assuming a MOSFET junction temperature of 125°C,
the room temperature MOSFET R
than:
should be less
DS(ON)
VSENSE(MAX)
8. The choice of an input capacitor for a SEPIC converter
dependsontheimpedanceofthesourcesupplyandthe
amount of input ripple the converter will safely toler-
ate. For this particular design and lab setup, a single
47μF Kemet tantalum capacitor (T495X476K020AS) is
adequate.Aswiththeoutputnode,checktheinputripple
with a single oscilloscope probe connected across the
input capacitor terminals. If any HF switching noise is
observed it is a good idea to decouple the input with
1
1
RDS(ON) ꢀ
•
•
ꢁ
IO(MAX)
ꢂ
ꢃ
ꢅ
ꢆ
ꢂ
ꢅ
VO + VD
1+
•ꢈ
T
ꢄ
ꢇ
+1
ꢄ
ꢇ
2
V
ꢃ
ꢆ
IN(MIN)
0.12
•
1
•
1
12.5
5
=
=12.7mꢉ
1.5 1.2•1.5 ꢂ
ꢅ
ꢆ
+1
ꢇ
ꢄ
ꢃ
For a SEPIC converter, the switch BV
rating must be
DSS
greater than V
+ V , or 27V. This comes close to
IN(MAX)
O
a low ESR, X5R ceramic capacitor as close to the V
and GND pins as possible.
IN
anIRF7811W,whichisratedto30V,andhasamaximum
room temperature R of 12mΩ at V = 4.5V.
DS(ON)
GS
1871fe
29
LTC1871
APPLICATIONS INFORMATION
9. The DC coupling capacitor in a SEPIC converter is cho-
sen based on its RMS current requirement and must be
Forthisdesignasingle10μF,lowESR(X5R)TaiyoYuden
ceramic capacitor (TMK432BJ106MM) is adequate.
rated for a minimum voltage of V plus the AC ripple
IN
voltage. Start with the minimum value which satisfies
the RMS current requirement and then check the ripple
voltage to ensure that it doesn’t exceed the DC rating.
VO + VD
IRMS(CI) ꢀIO(MAX) •
V
IN(MIN)
12V + 0.5V
=1.5A •
= 2.4A
5V
V
IN
4.5V to 15V
•
R3
1M
C
DC
L1*
10μF
25V
1
10
9
X5R
RUN
SENSE
D1
V
OUT
2
12V
I
V
IN
TH
1.5A
C
OUT1
(2A PEAK)
R
+
LTC1871
INTV
C
47μF
20V
×2
33k
3
4
5
8
7
6
C
OUT2
FB
CC
C
10μF
25V
X5R
×2
R1
12.1k
1%
C1
FREQ
GATE
GND
M1
6.8nF
L2*
+
C
4.7μF
X5R
R2
105k
1%
R
T
80.6k
1%
VCC
MODE/SYNC
C
IN
47μF
•
C
C2
47pF
GND
1871 F018a
C
C
, C
:
KEMET T495X476K020AS
L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS)
M1: INTERNATIONAL RECTIFIER IRF7811W
IN OUT1
, C
: TAIYO YUDEN TMK432BJ106MM
DC OUT2
D1:
INTERNATIONAL RECTIFIER 30BQ040
Figure 18a. 4.5V to 15V Input, 12V/2A Output SEPIC Converter
100
95
V
= 12V
IN
90
85
80
75
70
65
60
55
50
45
V
= 4.5V
IN
V
= 15V
IN
V
= 12V
O
MODE = INTV
CC
0.001
0.01
0.1
1 10
OUTPUT CURRENT (A)
1871 F18b
Figure 18b. SEPIC Efficiency vs Output Current
1871fe
30
LTC1871
APPLICATIONS INFORMATION
V
V
= 4.5V
OUT
V
V
= 15V
IN
IN
OUT
= 12V
= 12V
V
(AC)
V
(AC)
OUT
200mV/DIV
OUT
200mV/DIV
I
I
OUT
0.5A/DIV
OUT
0.5A/DIV
1871 F19
50μs/DIV
50μs/DIV
Figure 19. LTC1871 SEPIC Converter Load Step Response
TYPICAL APPLICATIONS
2.5V to 3.3V Input, 5V/2A Output Boost Converter
V
IN
2.5V to 3.3V
L1
1.8μH
D1
1
2
10
9
RUN
SENSE
V
5V
2A
OUT
I
TH
V
IN
C
OUT1
R
C
+
LTC1871
INTV
150μF
6.3V
×2
22k
3
4
5
8
7
6
C
OUT2
FB
CC
C
6.8nF
10μF
6.3V
X5R
×2
R1
12.1k
1%
C1
FREQ
GATE
GND
M1
C
4.7μF
X5R
R2
37.4k
1%
R
80.6k
1%
+
VCC
C
IN
47μF
6.3V
MODE/SYNC
T
C
C2
47pF
GND
1871 TA01a
C
C
C
C
:
SANYO POSCAP 6TPA47M
: SANYO POSCAP 6TPB150M
: TAIYO YUDEN JMK316BJ106ML
TAIYO YUDEN LMK316BJ475ML
D1: INTERNATIONAL RECTIFIER 30BQ015
L1: TOKO DS104C2 B952AS-1R8N
M1: SILICONIX/VISHAY Si9426
IN
OUT1
OUT2
VCC
:
Output Efficiency at 2.5V and 3.3V Input
100
95
90
85
80
75
70
65
60
55
50
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
1871 TA01b
1871fe
31
LTC1871
TYPICAL APPLICATIONS
18V to 27V Input, 28V Output, 400W 2-Phase, Low Ripple, Synchronized RF Base Station Power Supply (Boost)
V
IN
18V to 27V
R1
93.1k
1%
L1
5.6μH
L2
R2
8.45k
1%
5.6μH
C
+
IN1
330μF
50V
1
2
10
9
RUN
SENSE
D1
I
TH
V
IN
C
C1
47pF
LTC1871
INTV
C
OUT1
3
4
5
8
7
6
2.2μF
35V
X5R
×3
C
+
FB
OUT2
CC
330μF
50V
FREQ
GATE
GND
M1
C
IN2
R
150k
5%
C
4.7μF
X5R
MODE/SYNC
T1
VCC1
2.2μF
35V
C
R
S1
FB1
47pF
0.007Ω
1W
X5R
GND
C
*
OUT5
330μF
50V
×4
+
EXT CLOCK
C
*
OUT6
L3
5.6μH
L4
INPUT (200kHz)
2.2μF
35V
5.6μH
X5R
1
2
10
9
RUN
SENSE
D2
V
OUT
28V
14A
I
TH
V
IN
C
C2
L5*
0.3μH
LTC1871
INTV
47pF
C
OUT3
R
C
3
4
5
8
7
6
2.2μF
35V
X5R
×3
C
+
*L5, C
OUT6
AND
FB
22k
OUT4
OUT5
ARE AN
CC
330μF
50V
C
C
FB2
47pF
FREQ
GATE
GND
M2
OPTIONAL SECONDARY
FILTER TO REDUCE
C
IN3
R4
261k
1%
R3
12.1k
1%
R
150k
5%
MODE/SYNC
C
4.7μF
X5R
T2
VCC2
2.2μF
35V
C
6.8nF
R
S2
0.007Ω
1W
OUTPUT RIPPLE FROM
<500mV TO <100mV
C3
P-P P-P
X5R
1871 TA04
C
C
C
C
C
:
SANYO 50MV330AX
TAIYO YUDEN GMK325BJ225MN
SANYO 50MV330AX
TAIYO YUDEN GMK325BJ225MN
TAIYO YUDEN LMK316BJ475ML
L1 TO L4: SUMIDA CEP125-5R6MC-HD
L5: SUMIDA CEP125-0R3NC-ND
D1, D2: ON SEMICONDUCTOR MBR2045CT
M1, M2: INTERNATIONAL RECTIFIER IRLZ44NS
IN1
:
IN2, 3
OUT2, 4, 5
OUT1, 3, 6
:
:
:
VCC1, 2
5V to 12V Input, 12V/0.2A Output SEPIC Converter with Undervoltage Lockout
V
IN
5V to 12V
•
R1
127k
1%
C
DC1
R2
54.9k
1%
L1*
4.7μF
16V
1
2
10
9
X5R
RUN
SENSE
D1
V
OUT1
12V
I
V
IN
TH
0.4A
R
C
22k
LTC1871
INTV
C
OUT1
3
4
5
8
7
6
4.7μF
16V
X5R
×3
FB
CC
C
R4
127Ω
1%
C1
L2*
FREQ
GATE
GND
M1
6.8nF
C
C
C
IN1
IN2
VCC
MODE/SYNC
+
R3
1.10k
1%
R
T
60.4k
1%
1μF
16V
X5R
47μF
16V
•
4.7μF
10V
C
C2
R
S
100pF
0.02Ω
AVX
X5R
GND
V
C
OUT2
C
DC2
4.7μF
16V
X5R
×3
NOTE:
D1, D2: MBS120T3
L1 TO L3: COILTRONICS VP1-0076 (*COUPLED INDUCTORS)
M1: SILICONIX/VISHAY Si4840
4.7μF
+
–
D2
1. V UVLO = 4.47V
IN
16V
X5R
V
UVLO = 4.14V
IN
L3*
OUT2
•
–12V
0.4A
1871 TA03
1871fe
32
LTC1871
TYPICAL APPLICATIONS
4.5V to 28V Input, 5V/2A Output SEPIC Converter with Undervoltage Lockout and Soft-Start
V
IN
4.5V to 28V
R1
115k
1%
•
C
DC
2.2μF
25V
X5R
×3
R2
54.9k
1%
L1*
C1
4.7nF
1
2
10
9
RUN
SENSE
D1
V
OUT
5V
I
V
IN
TH
2A
(3A TO 4A PEAK)
R
+
LTC1871
INTV
C
C
OUT1
12k
3
4
5
8
7
6
330μF
6.3V
FB
CC
C
OUT2
R4
49.9k
1%
C
C1
22μF
6.3V
X5R
FREQ
GATE
GND
M1
L2*
8.2nF
C
C
IN1
VCC
+
C
22μF
35V
IN2
R3
154k
1%
R
T
162k
1%
MODE/SYNC
4.7μF
10V
2.2μF
35V
•
C
47pF
C2
X5R
X5R
GND
1871 TA02a
R5
100Ω
C2
1μF
NOTES:
1. V UVLO = 4.17V
+
–
Q1
X5R
IN
R6
750Ω
V
UVLO = 3.86V
IN
2. SOFT-START dV /dt = 5V/6ms
OUT
C
C
C
C
C
, C : TAIYO YUDEN GMK325BJ225MN
D1:
INTERNATIONAL RECTIFIER 30BQ040
IN1 DC
IN2
:
AVX TPSE226M035R0300
SANYO 6TPB330M
TAIYO YUDEN JMK325BJ226MN
LMK316BJ475ML
L1, L2: BH ELECTRONICS BH510-1007 (*COUPLED INDUCTORS)
:
:
M1:
Q1:
SILICONIX/VISHAY Si4840
PHILIPS BC847BF
OUT1
OUT2
:
VCC
Soft-Start
Load Step Response at VIN = 4.5V
V
OUT
100mV/DIV
(AC)
V
OUT
1V/DIV
2.2A
I
OUT
1A/DIV
(DC)
0.5A
1871 TA02b
1871 TA02c
1ms/DIV
250μs/DIV
Load Step Response at VIN = 28V
V
OUT
100mV/DIV
(AC)
2.2A
I
OUT
1A/DIV
(DC)
0.5A
1871 TA02d
250μs/DIV
1871fe
33
LTC1871
TYPICAL APPLICATIONS
5V to 15V Input, –5V/5A Output Positive-to-Negative Converter with Undervoltage Lockout and Level-Shifted Feedback
V
IN
5V to 15V
V
–5V
5A
OUT
•
•
R1
154k
1%
R2
68.1k
1%
L1*
L2*
C1
1nF
1
2
10
9
RUN
SENSE
C
OUT
I
V
IN
TH
100μF
6.3V
X5R
×2
C
22μF
25V
X7R
M1
DC
LTC1871
INTV
3
4
5
8
7
6
R
C
FB
CC
10k
FREQ
GATE
GND
C
C2
MODE/SYNC
330pF
D1
C
C
IN
VCC
R
80.6k
1%
T
4.7μF
10V
47μF
16V
C
10nF
C1
X5R
X5R
GND
R4
10k
1%
C2
10nF
R5
40.2k
1%
R3
10k
1%
6
–
4
1
LT1783
2
+
3
1871 TA05
C
:
TDK C5750X5R1C476M
TDK C5750X7R1E226M
: TDK C5750X5R0J107M
: TAIYO YUDEN LMK316BJ475ML
D1:
ON SEMICONDUCTOR MBRB2035CT
IN
C
C
C
:
L1, L2: COILTRONICS VP5-0053 (*3 WINDINGS IN PARALLEL
FOR THE PRIMARY, 3 IN PARALLEL FOR SECONDARY)
DC
OUT
VCC
M1:
INTERNATIONAL RECTIFIER IRF7822
1871fe
34
LTC1871
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
0.50
0.305 ± 0.038
(.0120 ± .0015)
TYP
(.0197)
10 9
8
7 6
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
1
2
3
4 5
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.50
(.0197)
BSC
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
1871fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC1871
TYPICAL APPLICATION
High Power SLIC Supply with Undervoltage Lockout
(Also See the LTC3704 Data Sheet)
GND
•
4
C3
D2
10BQ060
10μF
25V
X5R
V
IN
R1
49.9k
1%
R2
150k
1%
7V TO 12V
V
OUT1
–24V
C
200mA
C
R
1nF
IN
•
5
+
C4
D3
10BQ060
220μF
16V
C
3.3μF
100V
OUT
10μF
25V
X5R
T1*
1, 2, 3
TPS
C
•
C2
100pF
RUN
SENSE
I
V
IN
TH
•
6
D4
C5
LTC1871
C2
10BQ060
10μF
25V
X5R
R
C
FB
INTV
CC
4.7μF
50V
82k
FREQ
GATE
GND
IRL2910
V
OUT2
X5R
–72V
C
C1
+
C1
4.7μF
X5R
MODE/SYNC
f = 200kHz
R
200mA
1nF
R
R
F2
196k
1%
T
F1
10k
1%
R
120k
S
0.012Ω
6
–
4
*COILTRONICS VP5-0155
(PRIMARY = 3 WINDINGS IN PARALLEL)
10k
1
LT1783
2
+
3
C8
0.1μF
1871 TA06
RELATED PARTS
PART NUMBER
LT®1619
DESCRIPTION
COMMENTS
300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology
SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design;
Up to 36V
Current Mode PWM Controller
Current Mode DC/DC Controller
LTC1624
V
IN
LTC1700
No R
Synchronous Step-Up Controller
Up to 95% Efficiency, Operation as Low as 0.9V Input
No R , 7V Gate Drive, Current Mode Control
SENSE
LTC1871-7
LTC1872
Wide Input Range Controller
SENSE
SOT-23 Boost Controller
Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode
LT1930
1.2MHz, SOT-23 Boost Converter
Inverting 1.2MHz, SOT-23 Converter
1A/2A 3MHz Synchronous Boost Converters
Positive-to-Negative DC/DC Controller
2-Phase Step-Up DC/DC Controller
Up to 34V Output, 2.6V ≤ V ≤ 16V, Miniature Design
IN
LT1931
Positive-to-Negative DC/DC Conversion, Miniature Design
LTC3401/LTC3402
LTC3704
Up to 97% Efficiency, Very Small Solution, 0.5V ≤ V ≤ 5V
IN
No R , Current Mode Control, 50kHz to 1MHz
SENSE
LT3782
6V ≤ V ≤ 40V; 4A Gate Drive, 150kHz to 500kHz
IN
1871fe
LT 0108 REV E • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
© LINEAR TECHNOLOGY CORPORATION 2001
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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