LTC1275BCN [Linear]
12-Bit, 300ksps Sampling A/D Converters with Reference; 12位，高达300ksps的采样A / D转换器，内置参考
| 型号： | LTC1275BCN |
| 厂家： | 
Linear |
| 描述： | 12-Bit, 300ksps Sampling A/D Converters with Reference |
| 文件： | 总24页 (文件大小：449K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1273
LTC1275/LTC1276
12-Bit, 300ksps Sampling
A/D Converters with Reference
U
DESCRIPTIO
EATURE
S
F
■
■
■
■
■
■
■
■
■
■
■
Single Supply 5V or ±5V Operation
TheLTC1273/LTC1275/LTC1276are300ksps, sampling
12-bit A/D converters that draw only 75mW from single
5V or ±5V supplies. These easy-to-use devices come
complete with 600ns sample-and-holds, precision refer-
ences and internally trimmed clocks. Unipolar and bipo-
larconversionmodesprovideflexibilityforvariousappli-
cations. They are built with LTBiCMOSTM switched ca-
pacitor technology.
300ksps Sample Rate
75mW (Typ) Power Dissipation
On-Chip 25ppm/°C Reference
Internal Synchronized Clock; No Clock Required
High Impedance Analog Input
70dB S/(N + D) and 77dB THD at Nyquist
±1/2LSB INL and ±3/4LSB DNL Max (A Grade)
ESD Protected On All Pins
These devices have 25ppm/°C (max) internal references.
The LTC1273 converts 0V to 5V unipolar inputs from a
single 5V supply. The LTC1275/LTC1276 convert ±2.5V
and ±5V respectively from ±5V supplies. Maximum DC
specifications include ±1/2LSB INL, ±3/4LSB DNL and
25ppm/°C full scale drift over temperature. Outstanding
AC performance includes 70dB S/(N + D) and 77dB THD
at the Nyquist input frequency of 150kHz.
24-Pin Narrow DIP and SOL Packages
Variety of Input Ranges:
0V to 5V (LTC1273)
±2.5V (LTC1275)
±5V (LTC1276)
O U
PPLICATI
S
A
The internal clock is trimmed for 2.7µs maximum conver-
sion time. The clock automatically synchronizes to each
sample command eliminating problems with asynchro-
nous clock noise found in competitive devices. A high
speed parallel interface eases connections to FIFOs, DSPs
and microprocessors.
■
■
■
■
■
High Speed Data Acquisition
Digital Signal Processing
Multiplexed Data Acquisition Systems
Audio and Telecom Processing
Spectrum Analysis
LTBiCMOSTM is a trademark of Linear Technology Corporation
U
O
TYPICAL APPLICATI
Effective Bits and Signal to (Noise + Distortion)
vs Input Frequency
Single 5V Supply, 300ksps, 12-Bit Sampling A/D Converter
LTC1273
5V
12
11
10
9
74
68
62
56
50
1
2
24
23
22
21
20
19
18
17
16
15
14
13
ANALOG INPUT
(0V TO 5V)
A
V
V
DD
IN
2.42V
REF
OUTPUT
+
NC
BUSY
CS
0.1µF
V
REF
10µF
NYQUIST
FREQUENCY
+
3
0.1µF
AGND
D11
D10
D9
10µF
4
µP CONTROL
LINES
8
5
RD
7
6
HBEN
NC
6
7
D8
5
8
D7
NC
4
9
D6
D0/8
D1/9
D2/10
D3/11
3
10
11
12
8- OR 12-BIT
PARALLEL BUS
D5
2
D4
1
f
= 300kHz
SAMPLE
DGND
0
10k
100k
1M 2M
INPUT FREQUENCY (Hz)
LTC1273/75/76 • TA02
LTC1273/75/76 • TA01
1
LTC1273
LTC1275/LTC1276
W W W
U
(Notes 1 and 2)
ABSOLUTE AXI U RATI GS
Digital Output Voltage (Note 3)
Supply Voltage (VDD).............................................. 12V
Negative Supply Voltage (VSS)
LTC1275/LTC1276.................................. –6V to GND
Total Supply Voltage (VDD to VSS)
LTC1275/LTC1276............................................... 12V
Analog Input Voltage (Note 3)
LTC1273 .................................... –0.3V to VDD + 0.3V
LTC1275/LTC1276.............. VSS – 0.3V to VDD + 0.3V
Power Dissipation............................................. 500mW
Operating Temperature Range
LTC1273AC, LTC1273BC, LTC1275AC
LTC1275BC, LTC1276AC, LTC1276BC .... 0°C to 70°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
LTC1273 .................................... –0.3V to VDD + 0.3V
LTC1275/LTC1276.............. VSS – 0.3V to VDD + 0.3V
Digital Input Voltage (Note 4)
LTC1273 ................................................ –0.3V to 12V
LTC1275/LTC1276......................... VSS – 0.3V to 12V
W
U
/O
PACKAGE RDER I FOR ATIO
TOP VIEW
TOP VIEW
ORDER
PART NUMBER
ORDER
A
A
1
2
3
4
5
6
7
8
9
V
V
1
2
V
24
23
22
21
20
19
18
17
16
15
14
24
23
22
21
20
19
18
17
16
15
14
13
PART NUMBER
IN
IN
DD
DD
V
V
NC
REF
REF
SS
AGND
D11
D10
D9
AGND
D11
D10
D9
BUSY
CS
3
BUSY
CS
LTC1273ACN
LTC1273BCN
LTC1273ACS
LTC1273BCS
LTC1275ACN
LTC1275BCN
LTC1275ACS
LTC1275BCS
LTC1276ACN
LTC1276BCN
LTC1276ACS
LTC1276BCS
4
5
RD
RD
6
HBEN
NC
HBEN
NC
D8
D8
7
D7
D7
NC
8
NC
D6
D6
D0/8
D1/9
D2/10
9
D0/8
D1/9
D2/10
D3/11
(For MIL Grade:
Contact Factory)
D5
D5 10
D4 11
10
11
12
D4
DGND
DGND
12
13 D3/11
N PACKAGE
S PACKAGE
N PACKAGE
24-LEAD PLASTIC DIP 24-LEAD PLASTIC SOL
S PACKAGE
24-LEAD PLASTIC DIP 24-LEAD PLASTIC SOL
(For MIL Grade:
Contact Factory)
TJMAX = 110°C, θJA = 100°C/W (N)
TJMAX = 110°C, θJA = 130°C/W (S)
TJMAX = 110°C, θJA = 100°C/W (N)
TJMAX = 110°C, θJA = 130°C/W (S)
U
With Internal Reference (Notes 5 and 6)
CO VERTER
CHARACTERISTICS
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Linearity Error
●
12
12
Bits
(Note 7)
Commercial
Military
±1/2
±1/2
±3/4
±1
±1
±1
LSB
LSB
LSB
●
●
Differential Linearity Error
Offset Error
Commercial
Military
●
●
±3/4
±1
±1
±1
LSB
LSB
(Note 8)
±3
±4
±4
±6
LSB
LSB
●
●
Full Scale Error
±10
±25
±15
±45
LSB
Full Scale Tempco
I
= 0
±5
±10
ppm/°C
OUT(REFERENCE)
2
LTC1273
LTC1275/LTC1276
W
U
(Note 5)
DY
A IC
ACCURACY
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
SYMBOL PARAMETER
S/(N + D) Signal-to-Noise Plus Distortion Ratio
CONDITIONS
MIN
TYP
MAX
UNITS
dB
50kHz/150kHz Input Signal
50kHz/150kHz Input Signal
72/70
THD
Total Harmonic Distortion
Up to 5th Harmonic
–83/–74
dB
Peak Harmonic or Spurious Noise
Intermodulation Distortion
Full Power Bandwidth
50kHz/150kHz Input Signal
–85/–76
–80
dB
dB
IMD
f
= 29.37kHz, f = 32.446kHz
IN2
IN1
4.5
MHz
kHz
200
U
Full Linear BanU dwidth (S/(N + D) ≥ 68dB)
(Note 5)
A ALOG I PUT
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
SYMBOL PARAMETER
CONDITIONS
4.95V ≤ V ≤ 5.25V (LTC1273)
MIN
TYP
MAX
UNITS
V
IN
Analog Input Range (Note 9)
●
●
●
0 to 5
±2.5
±5
V
V
V
DD
4.75V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –2.45V (LTC1275)
DD
SS
4.95V ≤ V ≤ 5.25V, –5.25V ≤ V ≤ –4.95V (LTC1276)
DD
SS
I
Analog Input Leakage Current
Analog Input Capacitance
CS = High
●
±1
µA
IN
C
Between Conversions (Sample Mode)
During Conversions (Hold Mode)
50
5
pF
pF
IN
t
Sample-and-Hold
Acquisition Time
Commercial
Military
●
●
600
1000
ns
ns
ACQ
U U
U
I TER AL REFERE CE CHARACTERISTICS (Note 5)
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
PARAMETER
CONDITIONS
MIN
TYP
2.420
±5
MAX
2.440
±25
MIN
TYP
2.420
±10
MAX
2.440
±45
UNITS
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
I
I
= 0
= 0
2.400
2.400
REF
REF
REF
OUT
OUT
●
ppm/°C
4.95V ≤ V ≤ 5.25V
–5.25V ≤ V ≤ –4.95V
0.01
0.01
0.01
0.01
LSB/V
LSB/V
DD
SS
V
Load Regulation
0V ≤
|
I
|
≤ 1mA
2
2
LSB/mA
REF
OUT
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS (Note 5)
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
V
= 5.25V
= 4.95V
= 0V to V
●
●
●
2.4
V
V
IH
IL
DD
DD
IN
0.8
I
±10
µA
pF
IN
DD
C
V
Digital Input Capacitance
High Level Output Voltage
5
IN
V
DD
= 4.95V
OH
I = –10µA
I = –200µA
O
4.7
V
V
O
●
4.0
3
LTC1273
LTC1275/LTC1276
U
U
(Note 5)
DIGITAL I PUTS A D DIGITAL OUTPUTS
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Low Level Output Voltage
V
= 4.95V
DD
OL
I = 160µA
0.05
0.10
V
V
O
I = 1.6mA
O
●
●
●
0.4
±10
15
I
High Z Output Leakage D11-D0/8
High Z Output Capacitance D11-D0/8
Output Source Current
V
= 0V to V , CS High
µA
pF
OZ
OUT
DD
C
OZ
CS High (Note 9 )
I
I
V
V
= 0V
–10
10
mA
mA
SOURCE
SINK
OUT
OUT
Output Sink Current
= V
DD
W U
POWER REQUIRE E TS (Note 5)
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
Positive Supply Voltage
LTC1273/LTC1276 (Notes 10, 11)
LTC1275 (Note 10)
4.95
4.75
5.25
5.25
V
V
V
SS
Negative Supply Voltage
LTC1275 (Note 10)
LTC1276 (Notes 10, 11)
–2.45
–4.95
–5.25
–5.25
V
V
I
I
Positive Supply Current
Negative Supply Current
Power Dissipation
●
●
15
0.065
75
25
mA
mA
DD
SS
LTC1275/LTC1276
0.200
P
mW
D W U
See Timing Characteristics Figures (Note 5)
TI I G CHARACTERISTICS
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
Maximum Sampling Frequency
(Note 10)
Commercial
Military
SAMPLE(MAX)
CONV
●
●
300
250
kHz
kHz
t
Conversion Time
Commercial
Military
●
●
2.7
3.0
µs
µs
t
t
CS to RD Setup Time
RD to BUSY Delay
●
0
ns
1
2
C = 50pF
Commercial
Military
80
40
50
190
230
270
ns
ns
ns
L
●
●
t
Data Access Time After RD↓
C = 20pF
90
110
120
ns
ns
ns
3
L
Commercial
Military
●
●
C = 100pF
125
150
170
ns
ns
ns
L
Commercial
Military
●
●
t
t
t
RD Pulse Width
●
●
t
ns
ns
4
5
6
3
CS to RD Hold Time
Data Setup Time After BUSY↑
0
40
70
90
100
ns
ns
ns
Commercial
Military
●
●
4
LTC1273
LTC1275/LTC1276
W U
See Timing Characteristics Figures (Note 5)
CONDITIONS
TI I G CHARACTERISTICS
LTC1273A/LTC1275A/LTC1276A
LTC1273B/LTC1275B/LTC1276B
SYMBOL PARAMETER
MIN
TYP
MAX
UNITS
t
Bus Relinquish Time
20
20
20
30
75
85
90
ns
ns
ns
7
Commercial
Military
●
●
●
●
●
t
t
t
t
HBEN to RD Setup Time
HBEN to RD Hold Time
0
0
ns
ns
ns
8
9
Delay Between RD Operations
Delay Between Conversions
40
10
11
(Note 10)
Commercial
Military
500
600
1000
ns
ns
ns
●
●
t
Aperture Delay of Sample-and-Hold
25
ns
12
The
● indicates specifications which apply over the full operating
Note 6: Linearity, offset and full scale specifications apply for unipolar and
temperature range; all other limits and typicals T = 25°C.
bipolar modes.
A
Note 1: Absolute maximum ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below V (ground for
Note 8: Bipolar offset (LTC1275/LTC1276) is the different voltage
measured from –0.5LSB when the LTC1275/LTC1276 output code flickers
between 0000 0000 0000 and 1111 1111 1111.
SS
LTC1273) or above V , they will be clamped by internal diodes. This
DD
product can handle input currents greater than 60mA below V (ground
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
SS
for LTC1273) or above V without latch-up.
DD
Note 4: When these pin voltages are taken below V (ground for
LTC1273) they will be clamped by internal diodes. This product can handle
SS
Note11: A must not exceed V or fall below V by more than 50mV for
IN
DD
SS
specified accuracy. Therefore the minimum supply voltage for the
LTC1273 is +4.95V. The minimum supplies for the LTC1275 are +4.75V
and –2.45V and the minimum supplies for the LTC1276 are ±4.95V.
input currents greater than 60mA below V (ground for LTC1273)
SS
without latch-up. These pins are not clamped to V
.
DD
Note 5: V = 5V (V = –5V for LTC1275/LTC1276), 300kHz at 70°C and
DD
SS
250kHz at 125°C, t = t = 5ns unless otherwise specified.
r
f
W U
TI I G CHARACTERISTICS (Note 5)
ROM Mode, Parallel Read Timing Diagram
Slow Memory Mode, Parallel Read Timing Diagram
CS
CS
t
1
t
t
1
t
5
t
1
t
5
t
1
5
t
4
t
4
RD
BUSY
DATA
RD
BUSY
DATA
t
10
t
11
t
t
t
t
2
11
2
2
t
t
t
CONV
CONV
CONV
t
7
t
7
t
t
t
t
t
t
3
3
6
3
7
OLD DATA
DB11 TO DB0
NEW DATA
DB11 TO DB0
OLD DATA
DB11 TO DB0
NEW DATA
DB11 TO DB0
t
t
12
12
12
HOLD
HOLD
TRACK
TRACK
LTC1273/75/76 • TA03
LTC1273/75/76 • TA04
5
LTC1273
LTC1275/LTC1276
W U
TI I G CHARACTERISTICS (Note 5)
Slow Memory Mode, Two Byte Read Timing Diagram
HBEN
CS
t
8
t
9
t
t
9
8
t
1
t
t
t
1
t
5
5
t
4
RD
t
10
t
10
t
11
t
2
t
CONV
BUSY
DATA
t
3
t
7
t
3
t
6
7
OLD DATA
DB7 TO DB0
NEW DATA
DB7 TO DB0
NEW DATA
DB11 TO DB8
t
12
t
12
HOLD
TRACK
LTC1273/75/76 • TA05
ROM Mode, Two Byte Read Timing Diagram
HBEN
t
t
8
t
t
9
t
9
9
8
t
8
CS
RD
t
t
t
t
t
t
t
5
1
5
1
5
1
t
t
t
4
4
4
t
10
t
11
t
t
2
2
t
CONV
BUSY
DATA
t
t
t
t
t
7
3
7
3
7
3
OLD DATA
DB7 TO DB0
NEW DATA
DB11 TO DB8
NEW DATA
DB7 TO DB0
t
t
12
12
HOLD
LTC1273/75/76 • TA06
TRACK
6
LTC1273
LTC1275/LTC1276
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity
Differential Nonlinearity
Supply Current vs Temperature
25
1.0
0.5
0
1.0
0.5
0
20
15
10
5
–0.5
–0.5
–1.0
–1.0
0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
LTC1273/75/76 • TPC01
LTC1273/75/76 • TPC02
LTC1273/75/76 • TPC03
ENOBs and S/(N + D)
vs Input Frequency
Signal-to-Noise Ratio (Without
Harmonics) vs Input Frequency
Distortion vs Input Frequency
12
11
10
9
74
68
62
56
50
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
f
= 300kHz
SAMPLE
THD
2nd HARMONIC
3rd HARMONIC
8
–40
–50
–60
–70
–80
–90
–100
7
6
5
4
3
2
1
f
= 300kHz
f
= 300kHz
10k
SAMPLE
SAMPLE
0
1k
10k
100k
1M
10M
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
1k
100k
1M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
LTC1273/75/76 • TPC04
LTC1273/75/76 • TPC05
LTC1273/75/76 • TPC06
Power Supply Feedthrough
vs Ripple Frequency (LTC1275/76)
Power Supply Feedthrough
vs Ripple Frequency (LTC1273)
0
–20
0
–20
f
= 300kHz
f
= 300kHz
SAMPLE
SAMPLE
V
(V
= 1mV)
DD RIPPLE
DGND (V
= 0.1V)
RIPPLE
–40
–40
V
(V
= 10mV)
SS RIPPLE
V
DD
= 1mV)
(V
(V
RIPPLE
–60
–60
–80
–80
DGND
RIPPLE
–100
–120
–100
–120
= 0.1V)
1k
10k
100k
1M
1k
10k
100k
1M
RIPPLE FREQUENCY (Hz)
RIPPLE FREQUENCY (Hz)
LTC1273/75/76 • TPC07
LTC1273/75/76 • TPC08
7
LTC1273
LTC1275/LTC1276
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Acquisition Time
vs Source Impedance
S/(N + D) vs Input Frequency and
Amplitude
Intermodulation Distortion Plot
80
70
60
50
40
30
20
10
0
0
–20
4500
4000
3500
3000
2500
2000
1500
1000
500
f
= 300kHz
SAMPLE
f
f
f
= 300kHz
SAMPLE
IN1
IN2
= 29.37kHz
V
= 0dB
IN
= 32.446kHz
V
= –20dB
IN
–40
–60
–80
V
= –60dB
100k
IN
–100
–120
0
120 140
160
0
20 40 60 80 100
FREQUENCY (kHz)
1k
10k
1M
10M
10
100
1k
10k
INPUT FREQUENCY (Hz)
R
(Ω)
SOURCE
LTC1273/75/76 • TPC11
LTC1273/75/76 • TPC10
LTC1273/75/76 • F05
Spurious Free Dynamic Range
vs Input Frequency
Reference Voltage
vs Load Current
2.435
2.430
0
–10
–20
–30
f
= 300kHz
SAMPLE
2.425
2.420
–40
–50
–60
–70
2.415
2.410
2.405
–80
–90
–100
–5 –4
–3
–2
–1
0
1
2
10k
100k
1M
10M
LOAD CURRENT (mA)
INPUT FREQUENCY (Hz)
LTC1273/75/76 • TPC13
LTC1273/75/76 • TPC12
U U
U
PI FU CTIO S
AIN (Pin 1): Analog Input. 0V to 5V (LTC1273), ±2.5V
(LTC1275) or ±5V (LTC1276).
HBEN (Pin 19): High Byte Enable Input. This pin is used to
multiplex the internal 12-bit conversion result into the
lower bit outputs (D7-D0/8). See Table 1. HBEN also
disables conversion start when HIGH.
VREF (Pin 2): +2.42V Reference Output. Bypass to AGND
(10µF tantalum in parallel with 0.1µF ceramic).
RD (Pin 20): READ Input. This active low signal starts a
conversion when CS and HBEN are low. RD also enables
the output drivers when CS is low.
AGND (Pin 3): Analog Ground.
D11-D4 (Pins 4 to 11): Three-State Data Outputs.
DGND (Pin 12): Digital Ground.
CS (Pin 21): The CHIP SELECT Input must be low for the
ADC to recognize RD and HBEN inputs.
D3/11-D0/8 (Pins 13 to 16): Three-State Data Outputs.
NC (Pins 17 and 18): No Connection.
BUSY (Pin 22): The BUSY Output shows the converter
status. It is low when a conversion is in progress.
8
LTC1273
LTC1275/LTC1276
U
O
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PI
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S
VSS (Pin23):NegativeSupply.–5VforLTC1275/LTC1276.
Bypass to AGND with 0.1µF ceramic.
VDD (Pin 24): Positive Supply, 5V. Bypass to AGND (10µF
tantalum in parallel with 0.1µF ceramic).
NC (Pin 23): No Connection for LTC1273.
Table 1. Data Bus Output, CS and RD = LOW
Pin 4
D11
Pin 5
D10
Pin 6
D9
Pin 7
D8
Pin 8
D7
Pin 9
D6
Pin 10
D5
Pin 11
D4
Pin 13
D3/11
DB3
Pin 14
D2/10
DB2
Pin 15
D1/9
DB1
Pin 16
D0/8
DB0
MNEMONIC*
HBEN = LOW
HBEN = HIGH
DB11
DB11
DB10
DB10
DB9
DB9
DB8
DB8
DB7
LOW
DB6
LOW
DB5
LOW
DB4
LOW
DB11
DB10
DB9
DB8
*D11...D0/8 are the ADC data output pins.
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
U U
FU TIO AL BLOCK DIAGRA
W
SAMPLE
V
V
SS
(NC ON LTC1273)
DD
C
SAMPLE
COMPARATOR
SAMPLE
HOLD
–
A
IN
+
D11
12
12
SUCCESSIVE
APPROXIMATION
REGISTER
•
•
•
OUTPUT
LATCHES
12-BIT
CAPACITIVE
DAC
V
REF(OUT)
D0/8
BUSY
2.42V
REFERENCE
CS
RD
INTERNAL
CLOCK
CONTROL
LOGIC
HBEN
AGND DGND
LTC1273/75/76 • FBD
TEST CIRCUITS
Load Circuits for Output Float Delay
Load Circuits for Access Time
5V
3k
5V
3k
DBN
DBN
DBN
DBN
3k
C
C
3k
10pF
10pF
L
L
DGND
A) HIGH-Z TO V (t )
DGND
B) HIGH-Z TO V (t )
DGND
A) V TO HIGH-Z
DGND
B) V TO HIGH-Z
OH
3
OL
3
OH
OL
AND V TO V (t )
AND V TO V (t )
OH OL 6
1273/75/76 • TA08
OL
OH
6
1273/75/76 • TA07
9
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capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the AIN input charge. The SAR contents (a 12-bit
data word) which represent the AIN are loaded into the
12-bit output latches.
CONVERSION DETAILS
The LTC1273/LTC1275/LTC1276 use a successive ap-
proximation algorithm and an internal sample-and-hold
circuit to convert an analog signal to a 12-bit parallel or
2-byte output. The ADCs are complete with a precision
reference and an internal clock. The control logic provides
easyinterfacetomicroprocessorsandDSPs.(Pleaserefer
to the Digital Interface section for the data format.)
DYNAMIC PERFORMANCE
The LTC1273/LTC1275/LTC1276 have an exceptionally
high speed sampling capability. FFT (Fast Fourier Trans-
form) test techniques are used to characterize the ADC’s
frequency response, distortion and noise at the rated
throughput. By applying a low distortion sine wave and
analyzing the digital output using an FFT algorithm, the
ADC’s spectral content can be examined for frequencies
outsidethefundamental.Figure2showsatypicalLTC1275
FFT plot.
Conversion start is controlled by the CS, RD and HBEN
inputs. At the start of conversion the successive approxi-
mation register (SAR) is reset and the three-state data
outputs are enabled. Once a conversion cycle has begun
it cannot be restarted.
During conversion, the internal 12-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, the AIN input connects to the sample-and-hold
capacitor during the acquire phase, and the comparator
offset is nulled by the feedback switch. In this acquire
phase, a minimum delay of 600ns will provide enough
time for the sample-and-hold capacitor to acquire the
analog signal. During the convert phase, the comparator
feedback switch opens, putting the comparator into the
compare mode. The input switch switches CSAMPLE to
ground, injecting the analog input charge onto the sum-
ming junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
Signal-to-Noise Ratio
TheSignal-to-NoiseplusDistortionRatio[S/(N+D)]isthe
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 2 shows a typical spectral content with
a 300kHz sampling rate and a 29kHz input. The dynamic
performance is excellent for input frequencies up to the
Nyquist limit of 150kHz.
0
SAMPLE
–20
–40
SI
C
SAMPLE
SAMPLE
HOLD
A
–
+
IN
–60
C
V
DAC
COMPARATOR
–80
DAC
DAC
S
A
R
–100
–120
120 140
160
0
20
40 60 80 100
FREQUENCY (kHz)
12-BIT
LATCH
LTC1273/75/76 • F02
LTC1273/75/76 • F01
Figure 1. AIN Input
Figure 2. LTC1275 Nonaveraged, 1024 Point FFT Plot
10
LTC1273
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Effective Number of Bits
quency is shown in Figure 4. The LTC1273/LTC1275/
LTC1276 have good distortion performance up to Nyquist
and beyond.
TheEffectiveNumberofBits(ENOBs)isameasurementof
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
0
f
= 300kHz
SAMPLE
–10
–20
–30
N = [S/(N + D) – 1.76]/6.02
THD
2nd HARMONIC
3rd HARMONIC
where N is the Effective Number of Bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 300kHz the LTC1273/LTC1275/LTC1276 maintain
very good ENOBs up to the Nyquist input frequency of
150kHz. Refer to Figure 3.
–40
–50
–60
–70
–80
–90
–100
12
11
10
9
74
68
62
56
50
1k
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
LTC1273/75/76 • F04
8
7
Figure 4. Distortion vs Input Frequency
6
5
4
Intermodulation Distortion
3
2
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
1
f
= 300kHz
SAMPLE
0
10k
100k
INPUT FREQUENCY (Hz)
1M 2M
LTC1273/75/76 • F03
Figure 3. Effective Bits and Signal to (Noise + Distortion)
vs Input Frequency
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at sum and difference
frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
Forexample, the2ndorderIMDtermsinclude(fa+fb)and
(fa – fb) while the 3rd order IMD terms include (2fa + fb),
(2fa – fb), (fa + 2fb), and (fa – 2fb). If the two input sine
wavesareequalinmagnitude,thevalue(indecibels)ofthe
2ndorderIMDproductscanbeexpressedbythefollowing
formula:
Total Harmonic Distortion
Total Harmonic Distortion (THD) is the ratio of the RMS
sumofallharmonicsoftheinputsignaltothefundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:
2
2
2
2
√V2 + V3 + V4 ... + VN
THD = 20log
V1
Amplitude at (fa ± fb)
IMD (fa ± fb) = 20log
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the
second through Nth harmonics. THD versus input fre-
Amplitude at fa
11
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the analog input must settle after the small current spike
before the next conversion starts. Any op amp that settles
in 600ns to small current transients will allow maximum
speedoperation.Ifsloweropampsareused,moresettling
time can be provided by increasing the time between
conversions.SuitabledevicescapableofdrivingtheADCs’
Figure 5 shows the IMD performance at a 30kHz input.
0
f
f
f
= 300kHz
SAMPLE
IN1
IN2
= 29.37kHz
–20
–40
= 32.446kHz
A
IN input include the LT1190/LT1191, LT1007, LT1220,
–60
LT1223 and LT1224 op amps.
–80
The analog input tolerates source resistance very well.
Here again, the only requirement is that the analog input
must settle before the next conversion starts. For larger
source resistance, full DC accuracy can be obtained if
more time is allowed between conversions. For more
information, see the Acquisition Time vs Source Resis-
tance curve in the Typical Performance Characteristics
section. For optimum frequency domain performance
[e.g., S/(N + D)], keep the source resistance below 100Ω.
–100
–120
120 140
160
0
20 40 60 80 100
FREQUENCY (kHz)
LTC1273/75/76 • F05
Figure 5. Intermodulation Distortion Plot
Peak Harmonic or Spurious Noise
Internal Reference
The peak harmonic or spurious noise is the largest spec-
tral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full scale input signal.
The LTC1273/LTC1275/LTC1276 have an on-chip, tem-
perature compensated, curvature corrected, bandgap ref-
erence which is factory trimmed to 2.42V. It is internally
connected to the DAC and is available at pin 2 to provide
up to 1mA current to an external load.
Full Power and Full Linear Bandwidth
The full power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is re-
duced by 3dB for a full scale input signal.
For minimum code transition noise the reference output
should be decoupled with a capacitor to filter wideband
noise from the reference (10µF tantalum in parallel with a
0.1µF ceramic).
The full linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 68dB (11 effective bits). The
LTC1273/LTC1275/LTC1276 have been designed to opti-
mize input bandwidth, allowing ADCs to undersample
inputsignalswithfrequenciesabovetheconverters’Nyquist
Frequency. The noise floor stays very low at high frequen-
cies; S/(N + D) becomes dominated by distortion at
frequencies far beyond Nyquist.
I
n the LTC1275, the VREF pin can be driven above its
normal value with a DAC or other means to provide input
spanadjustmentortoimprovethereferencetemperature
drift. Figure 6 shows an LT1006 op amp driving the
INPUT RANGE
±1.033V
REF(OUT)
LTC1275
A
+
IN
Driving the Analog Input
V
≥ 2.45V
3Ω
REF(OUT)
LT1006
V
REF
The analog inputs of the LTC1273/LTC1275/LTC1276 are
easytodrive.Theydrawonlyonesmallcurrentspikewhile
charging the sample-and-hold capacitor at the end of
conversion. During conversion the analog input draws no
current. The only requirement is that the amplifier driving
–
AGND
LTC1273/75/76 • F06
10µF
Figure 6. Driving the VREF with the LT1006 Op Amp
12
LTC1273
LTC1275/LTC1276
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reference pin. The VREF pin must be driven to at least
2.45V to prevent conflict with the internal reference. The
reference should be driven to no more than 4.8V to keep
the input span within the ±5V supplies. In the LTC1273/
LT1276, the input spans are 0V to 5V and ±5V respec-
tively with the internal reference. Driving the reference is
not recommended on the LTC1273/LTC1276 since the
inputspanswillexceedthesuppliesandcodeswillbelost
at full scale.
FS
5V
=
111...111
111...110
111...101
111...100
1LSB =
4096 4096
UNIPOLAR
ZERO
000...011
000...010
000...001
000...000
Figure 7 shows a typical reference, the LT1019A-2.5
connected to the LTC1275. This will provide an improved
drift(equaltothemaximum5ppm/°CoftheLT1019A-2.5)
and a ±2.582V full scale.
0V
FS – 1LSB
1
LSB
INPUT VOLTAGE (V)
LTC1273/75/76 • F08
Figure 8. LTC1273 Unipolar Transfer Characteristic
INPUT RANGE
±2.58V
5V
011...111
LTC1275
BIPOLAR
ZERO
011...110
A
IN
V
IN
V
V
OUT
REF
000...101
000...000
111...111
LT1019A-2.5
3Ω
10µF
AGND
LTC1273/75/76 • F07
GND
111...110
100...001
100...000
FS = 5V (LTC1275)
FS = 10V (LTC1276)
1LSB = FS/4096
Figure 7. Supplying a 2.5V Reference Voltage
to the LTC1275 with the LT1019A-2.5
–1 0V
–FS/2
1
FS/2 – 1LSB
LSB
LSB
UNIPOLAR/BIPOLAR OPERATION AND ADJUSTMENT
INPUT VOLTAGE (V)
LTC1273/75/76 • F09
Figure 8 shows the ideal input/output characteristics for
theLTC1273. Thecodetransitionsoccurmidwaybetween
successive integer LSB values (i.e., 1/2LSB, 1 1/2LSBs,
2 1/2LSBs, ... FS – 1 1/2LSBs). The output code is natural
binary with 1LSB = FS/4096 = 5V/4096 = 1.22mV. Figure
9 shows the input/output transfer characteristics for the
LTC1275/LTC1276in2’scomplementformat. Asstatedin
the figure, 1LSB for LTC1275/LTC1276 are 1.22mV and
2.44mV respectively.
Figure 9. LTC1275/LTC1276 Bipolar Transfer Characteristic
R1
50Ω
V
1
+
–
A1
A
IN
R4
R2
10k
100Ω
LTC1273
LTC1275
LTC1276
R3
10k
FULL SCALE
ADJUST
Unipolar Offset and Full Scale Adjustment (LTC1273)
AGND
LTC1273/75/76 • F10a
In applications where absolute accuracy is important,
offset and full scale errors can be adjusted to zero. Figure
10a shows the extra components required for full scale
error adjustment. If both offset and full scale adjustments
are needed, the circuit in Figure 10b can be used. Offset
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
Figure 10a. Full Scale Adjust Circuit
13
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A
R1
R1
10k
ANALOG
INPUT
0V TO 5V
10k
ANALOG
INPUT
±2.5V (LTC1275)
±5V (LTC1276)
+
–
+
–
R2
10k
R2
10k
A
A
IN
IN
10k
R4
100k
R4
100k
5V
R9
20Ω
R5
4.3k
R5
LTC1275
LTC1276
LTC1273
4.3k
FULL SCALE
FULL SCALE
ADJUST
5V
5V
ADJUST
R3
R3
R7
100k
R7
100k
R8
100k
R8
100k
LTC1273/75/76 • F10b
LTC1273/75/76 • F10c
10k
20k
OFFSET
ADJUST
OFFSET
ADJUST
R6
400Ω
R6
200Ω
–5V
Figure 10b. LTC1273 Offset and Full Scale Adjust Circuit
Figure 10c. LTC1275/LTC1276 Offset and
Full Scale Adjust Circuit
shouldbeadjustedbeforefullscale. Toadjustoffset, apply
0.61mV(i.e.,1/2LSB)attheinputandadjusttheoffsettrim
untiltheLTC1273outputcodeflickersbetween00000000
0000 and 0000 0000 0001. To adjust full scale, apply an
analog input of 4.99817V (i.e., FS – 1 1/2LSBs or last code
transition) at the input and adjust the full scale trim until
the LTC1273 output code flickers between 1111 1111
1110 and 1111 1111 1111. It should be noted that if
negative ADC offsets need to be adjusted or if an output
swing to ground is required, the op amp in Figure 10b
requires a negative power supply.
input and R5 is adjusted until the output code flickers
between 0111 1111 1110 and 0111 1111 1111.
BOARD LAYOUT AND BYPASSING
The LTC1273/LTC1275/LTC1276 are easy to use. To ob-
tain the best performance from the devices a printed
circuit board is required. Layout for the printed circuit
boardshouldensurethatdigitalandanalogsignallinesare
separated as much as possible. In particular, care should
be taken not to run any digital track alongside an analog
signal track. The analog input should be screened by
AGND.
Bipolar Offset and Full Scale Adjustment
(LTC1275/LTC1276)
Bipolar offset and full scale errors are adjusted in a similar
fashion to the unipolar case. Figure 10a shows the extra
componentsrequiredforfullscaleerroradjustment. Ifboth
offset and full scale adjustments are needed, the circuit in
Figure 10c can be used. Again, bipolar offset must be
adjusted before full scale error. Bipolar offset adjustment is
achieved by trimming the offset adjustment of Figure 10c
whiletheinputvoltageis1/2LSBbelowground.Thisisdone
by applying an input voltage of –0.61mV or –1.22mV
(–0.5LSB for LTC1275 or LTC1276) to the input in Figure
10c and adjusting R8 until the ADC output code flickers
between 0000 0000 0000 and 1111 1111 1111. For full
scaleadjustment,aninputvoltageof2.49817Vor4.99636V
(FS – 1 1/2LSBs for LTC1275 or LTC1276) is applied to the
High quality tantalum and ceramic bypass capacitors
shouldbeusedattheVDD andVREF pinsasshowninFigure
11. For the LTC1275/LTC1276 a 0.1µF ceramic provides
adequate bypassing for the VSS pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Noise: Input signal leads to AIN and signal return leads
from AGND (Pin 3) should be kept as short as possible to
minimize input noise coupling. In applications where this
is not possible, a shielded cable between source and ADC
is recommended. Also, since any potential difference in
groundsbetweenthesignalsourceandADCappearsasan
14
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1
DIGITAL
SYSTEM
A
LTC1273
IN
AGND
3
V
V
DGND
12
+
–
REF
DD
24
ANALOG
INPUT
CIRCUITRY
2
GROUND CONNECTION
TO DIGITAL CIRCUITRY
10µF
0.1µF
10µF
0.1µF
ANALOG GROUND PLANE
LTC1273/75/76 • F11
Figure 11. Power Supply Grounding Practice
error voltage in series with the input signal, attention
should be paid to reducing the ground circuit impedances
as much as possible.
Internal Clock
TheseADCshaveaninternalclockthateliminatestheneed
for synchronization between an external clock and the CS
and RD signals found in other ADCs. The internal clock is
factory trimmed to achieve a typical conversion time of
2.45µs, and a maximum conversion time over the full
operating temperature range of 2.7µs. No external adjust-
ments are required and, with the guaranteed maximum
acquisition time of 600ns, throughput performance of
300ksps is assured.
Asinglepointanaloggroundplaneseparatefromthelogic
system ground should be established at Pin 3 (AGND) or
as close as possible to the ADC, as shown in Figure 11. Pin
12 (DGND) and all other analog grounds should be con-
nected to this single analog ground point. No other digital
grounds should be connected to this analog ground point.
Low impedance analog and digital power supply common
returnsareessentialtolownoiseoperationoftheADCand
the width for these traces should be as wide as possible.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: HBEN, CS and RD. Figure 12 shows
the logic structure associated with these inputs. The three
signals are internally gated so that a logic “0” is required
In applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in conversion
results. These errors are due to feedthrough from the
microprocessor to the ADC. The problem can be elimi-
nated by forcing the microprocessor into a WAIT state
during conversion or by using three-state buffers to iso-
late the ADC data bus.
LTC1273/75/76
BUSY
D
Q
CONVERSION
START (RISING
EDGE TRIGGER)
19
HBEN
CS 21
20
FLIP
FLOP
RD
DIGITAL INTERFACE
CLEAR
The ADCs are designed to interface with microprocessors
as a memory mapped device. The CS and RD control
inputs are common to all peripheral memory interfacing.
The HBEN input serves as a data byte select for 8-bit
processors and is normally either connected to the micro-
processor address bus or grounded.
ACTIVE HIGH
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
D11....D0/8 = DB11....DB0
ENABLE THREE-STATE OUTPUTS
D11....D8 = DB11....DB8
D7....D4 = LOW
D3/11....D0/8 = DB11....DB8
LTC1273/75/76 • F12
* D11....D0/8 ARE THE ADC DATA OUTPUT PINS
DB11....DB0 ARE THE 12-BIT CONVERSION RESULTS
Figure 12. Internal Logic for Control Inputs CS, RD and HBEN
15
LTC1273
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on all three inputs to initiate a conversion. Once initiated it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output, and this
is low while conversion is in progress.
8MSBs) where it can be read in two read cycles. The
4MSBs always appear on D11...D8 whenever the three-
state output drivers are turned on.
Slow Memory Mode, Parallel Read (HBEN = LOW)
Therearetwomodesofoperationasoutlinedbythetiming
diagrams of Figures 13 to 16. Slow Memory Mode is
designed for microprocessors which can be driven into a
WAITstate.AREADoperationbringsCSandRDlowwhich
initiates a conversion and data is read when conversion is
complete. The second is the ROM Mode which does not
require microprocessor WAIT states. A READ operation
brings CS and RD low which initiates a conversion and
reads the previous conversion result.
Figure 13 and Table 2 show the timing diagram and data
bus status for Slow Memory Mode, Parallel Read. CS and
RD going low trigger a conversion and the ADC acknowl-
edgesbytakingBUSYlow. Datafromthepreviousconver-
sion appears on the three-state data outputs. BUSY re-
turns high at the end of conversion when the output
latches have been updated and the conversion result is
placed on data outputs D11...D0/8.
Slow Memory Mode, Two Byte Read
Data Format
Foratwobyteread,only8dataoutputsD7...D0/8areused.
Conversion start procedure and data output status for the
first read operation are identical to Slow Memory Mode,
Parallel Read. See Figure 14 timing diagram and Table 3
data bus status. At the end of the conversion, the low data
byte (D7...D0/8) is read from the ADC. A second READ
operation,withtheHBENhigh,placesthehighbyteondata
outputs D3/11...D0/8 and disables conversion start. Note
Theoutputformatcanbeeitheracompleteparallelloadfor
16-bit microprocessors or a two byte load for 8-bit micro-
processors. Data is always right justified (i.e., LSB is the
most right-hand bit in a 16-bit word). For a two byte read,
only data outputs D7...D0/8 are used. Byte selection is
governed by the HBEN input which controls an internal
digital multiplexer. This multiplexes the 12-bits of conver-
sion data onto the lower D7...D0/8 outputs (4MSBs or
CS
t
t
5
t
1
1
RD
t
10
t
t
11
2
t
CONV
BUSY
DATA
t
t
t
7
6
3
OLD DATA
DB11-DB0
NEW DATA
DB11-DB0
t
12
HOLD
TRACK
LTC1273/75/76 • F13
Figure 13. Slow Memory Mode, Parallel Read Timing Diagram
Table 2. Slow Memory Mode, Parallel Read Data Bus Status
Data Outputs
D11
D10
D9
D8
D7
D6
D5
D4
D3/11
D2/10
D1/9
D0/8
Read
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
16
LTC1273
LTC1275/LTC1276
O U
W
U
PPLICATI
A
S I FOR ATIO
HBEN
t
t
t
t
9
8
9
8
CS
RD
t
t
5
t
1
t
5
1
t
4
t
10
t
10
t
t
11
2
t
CONV
BUSY
DATA
t
t
t
7
t
t
7
3
6
3
OLD DATA
DB7-DB0
NEW DATA
DB7-DB0
NEW DATA
DB11-DB8
t
t
12
12
HOLD
TRACK
LTC1273/75/76 • F14
Figure 14. Slow Memory Mode, Two Byte Read Timing Diagram
Table 3. Slow Memory Mode, Two Byte Read Data Bus Status
Data Outputs
First Read
D7
D6
D5
D4
D3/11
DB3
D2/10
DB2
D1/9
D0/8
DB7
Low
DB6
Low
DB5
Low
DB4
Low
DB1
DB9
DB0
DB8
Second Read
DB11
DB10
that the 4MSBs appear on data output D11...D8 during
both READ operations.
normal way with a READ operation and the data output
status is the same as the ROM mode, Parallel Read (see
Figure 16 timing diagram and Table 5 data bus status).
TwomoreREADoperationsarerequiredtoaccessthenew
conversion result. A delay equal at the ADCs’ conversion
time must be allowed between conversion start and the
third data READ operation. The second READ operation
with HBEN high disables conversion start and places the
high byte (4MSBs) on data outputs D3/11...D0/8. A third
read operation accesses the low data byte (DB7...DB0)
and starts another conversion. The 4MSBs appear on data
outputs D11...D8 during all three read operations.
ROM Mode, Parallel Read (HBEN = LOW)
The ROM Mode avoids placing a microprocessor into a
WAIT state. A conversion is started with a READ opera-
tion, and the 12 bits of data from the previous conversion
are available on data outputs D11...D0/8 (see Figure 15
and Table 4). This data may be disregarded if not re-
quired. A second READ operation reads the new data
(DB11...DB0) and starts another conversion. A delay at
leastaslongastheADC’sconversiontimeplusthe600ns
minimum delay between conversions must be allowed
between READ operations.
MICROPROCESSOR INTERFACING
The LTC1273/LTC1275/LTC1276 allow easy interfac-
ing to digital signal processors as well as modern high
speed, 8-bit or 16-bit microprocessors. Here are sev-
eral examples.
ROM Mode, Two Byte Read
As previously mentioned for a two byte read, only data
outputs D7...D0/8 are used. Conversion is started in the
17
LTC1273
LTC1275/LTC1276
O U
W
U
PPLICATI
A
S I FOR ATIO
CS
t
1
t
t
t
5
5
1
t
t
4
4
RD
t
11
t
2
t
t
CONV
2
t
CONV
BUSY
DATA
t
t
t
t
7
3
7
3
OLD DATA
DB11-DB0
NEW DATA
DB11-DB0
t
t
12
12
HOLD
TRACK
LTC1273/75/76 • F15
Figure 15. ROM Mode, Parallel Read Timing Diagram (HBEN = LOW)
Table 4. ROM Mode, Parallel Read Data Bus Status
Data Outputs
D11
DB11
DB11
D10
DB10
DB10
D9
D8
D7
D6
D5
D4
D3/11
DB3
D2/10
DB2
D1/9
DB1
DB1
D0/8
DB0
DB0
First Read (Old Data)
Second Read
DB9
DB9
DB8
DB8
DB7
DB7
DB6
DB6
DB5
DB5
DB4
DB4
DB3
DB2
HBEN
t
t
t
t
t
t
9
8
9
8
9
8
CS
RD
t
t
t
t
t
t
t
5
1
5
1
5
1
4
t
t
t
4
4
t
10
t
11
t
2
2
t
CONV
BUSY
DATA
t
t
t
t
t
t
7
3
7
3
7
3
OLD DATA
DB7-DB0
NEW DATA
DB11-DB8
NEW DATA
DB7-DB0
t
t
12
12
HOLD
LTC1272 • TA16
TRACK
Figure 16. ROM Mode Two Byte Read Timing Diagram
Table 5. ROM Mode, Two Byte Read Data Bus Status
Data Outputs
D7
D6
D5
D4
D3/11
DB3
D2/10
DB2
D1/9
DB1
DB9
DB1
D0/8
DB0
DB8
DB0
First Read (Old Data)
Second Read (New Data)
Third Read (New Data)
DB7
Low
DB7
DB6
Low
DB6
DB5
Low
DB5
DB4
Low
DB4
DB11
DB3
DB10
DB2
18
LTC1273
LTC1275/LTC1276
O U
W
U
PPLICATI
TMS320C25
S I FOR ATIO
A
A23
A1
ADDRESS BUS
ADDRESS
Figure 17 shows an interface between the LTC1273 and
the TMS320C25.
AS
EN
DECODE
LTC1273/75/76
MC68000
The W/R signal of the DSP initiates a conversion and
conversion results are read from the LTC1273 using the
following instruction:
CS
BUSY
DTACK
R/W
RD
D11
D0
D11
IN
D, PA
DATA BUS
D0/8
HBEN
where D is Data Memory Address and PA is the PORT
ADDRESS.
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76 • F18
A16
Figure 18. MC68000 Interface
ADDRESS BUS
A1
ADDRESS
DECODE
IS
TMS320C25
EN
8085A/Z80 Microprocessor
LTC1273/75/76
Figure 19 shows an LTC1273 interface for the Z80/8085A.
The LTC1273 is operating in the Slow Memory Mode and
a two byte read is required. Not shown in the figure is the
8-bit latch required to demultiplex the 8085A common
address/data bus. A0 is used to assert HBEN so that an
even address (HBEN = LOW) to the LTC1273 will start a
conversion and read the low data byte. An odd address
(HBEN = HIGH) will read the high data byte. This is
accomplished with the single 16-bit LOAD instruction
below.
CS
BUSY
READY
R/W
RD
D16
D0
D11
DATA BUS
D0/8
HBEN
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76 • F17
Figure 17. TMS320C25 Interface
MC68000 Microprocessor
For the 8085A
For the Z80
LHLD (B000)
LDHL, (B000)
Figure 18 shows a typical interface for the MC68000. The
LTC1273 is operating in the Slow Memory Mode. Assum-
ing the LTC1273 is located at address C000, then the
following single 16-bit MOVE instruction both starts a
conversion and reads the conversion result:
A15
A0
ADDRESS BUS
A0
ADDRESS
DECODE
Move.W $C000,D0
MREQ
EN
HBEN
Z80
8085A
At the beginning of the instruction cycle when the ADC
address is selected, BUSY and CS assert DTACK so that
the MC68000 is forced into a WAIT state. At the end of
conversion, BUSY returns high and the conversion result
is placed in the D0 register of the microprocessor.
CS
WAIT
BUSY
LTC1273/75/76
RD
RD
D7
D0
D7
DATA BUS
D0/8
ADDITIONAL PINS OMITTED FOR CLARITY
LTC1273/75/76 • F19
Figure 19. 8085A and Z80 Interface
19
LTC1273
LTC1275/LTC1276
O U
W
U
PPLICATI
A
S I FOR ATIO
This is a two byte read instruction which loads the ADC
data (address B000) into the HL register pair. During the
first read operation, BUSY forces the microprocessor to
WAIT for the LTC1273 conversion. No WAIT states are
inserted during the second read operation when the mi-
croprocessor is reading the high data byte.
current so it can be accurately driven by the unbuffered
MUX. The CD4520 counter increments the MUX channel
after each sample is taken. Figure 22 shows the acquisi-
tion time of LTC1275 vs the source resistance. For a
500Ω maximum “on” resistance of the CD4051, the
acquisition time of the ADC is not greatly affected. For
larger source resistances, modest increases in acquisi-
tion time must be allowed.
TMS32010 Microcomputer
Figure 20 shows an LTC1273/TMS32010 interface. The
LTC1273 is operating in the ROM Mode.
5V
NO
CD4051
BUFFER
The LTC1273 is mapped at a port address. The following
I/O instruction starts a conversion and reads the previous
conversion result into data memory.
V
DD
D11
REQUIRED
•
•
•
A
IN
µP
OR
DSP
D0
LTC1275
CS
RD
8 INPUT
CHANNELS
±2.8V
IN A,PA
(PA = PORT ADDRESS)
BUSY
When conversion is complete, a second I/O instruction
reads the up-to-date data into memory and starts another
conversion. A delay at least as long as the ADC conversion
time must be allowed between I/O instructions.
INPUT
VARIES
LTC1273/75/76 • F21
V
SS
5V
V
A
B C
EE
ENABLE
CD4520
COUNTER
RESET
Q2
Q1
Q0
PA2
–5V
PORT ADDRESS BUS
PA0
ADDRESS
DECODE
DEN
TMS32010
EN
LTC1273/75/76
CS
Figure 21. MUXing the LTC1275 with CD4051
RD
4
D11
D0
D11
DATA BUS
D0/8
HBEN
R
SOURCE
3
2
1
0
LINEAR CIRCUITRY OMITTED FOR CLARITY
A
LTC1275
IN
LTC1273/75/76 • F20
V
IN
Figure 20. TMS32010 Interface
500Ω
MUXing with CD4051
The high input impedance of the LTC1273/LTC1275/
LTC1276providesaneasy, cheap, fast, andaccurateway
to multiplex many channels of data through one con-
verter. Figure 21 shows a low cost CD4051 connected to
the LTC1275. The LTC1275’s input draws no DC input
10
100
1k
10k
SOURCE RESISTANCE (Ω)
LTC1273/75/76 • F22
Figure 22. Acqusition Time of LTC1275 vs Source Resistance
20
LTC1273
LTC1275/LTC1276
O U
W
U
PPLICATI
A
S I FOR ATIO
Demodulating a Signal by Undersampling
AtimedomainviewofthedemodulationisshowninFigure
25. The top trace shows the 455kHz waveform modulated
by a –6dB, 5kHz signal. The bottom trace shows the
demodulated signal produced by the LTC1275 recon-
structed through a 12-bit DAC. The resultant frequency is
5kHz with a sample rate of 227.5kHz. There are roughly 45
points per cycle.
with LTC1275
Figure 23 shows a 455kHz amplitude modulated input
undersampled by the LTC1275. With a 227.5kHz sample
rate,theconverterprovidesa100dBnoisefloorand68dB
distortion when digitizing the 455kHz AM input.
Figure 24 shows an FFT of the AM signal digitized at
212.5kHz.
5V
455kHz
AM SIGNAL
227.5kHz
SAMPLE RATE
1V/DIV
RD
RD
455kHz
AMPLITUDE
MODULATED
INPUT
A
LTC1275
IN
D11
D0
DATA OUTPUT
DEMODULATED
5kHz OUTPUT
1V/DIV
–5V
LTC1273/75/76 • F23
Figure 23. A 455kHz Amplitude Modulated Input
Undersampled by the LTC1275
LTC1273/75/76 • F27
50µs/DIV
Figure 25. 455kHz AM Signal Demodulated to 10.5 ENOBs
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
100ps Resolution ∆Time Measurement with LTC1273
Figure 26 shows a circuit that precisely measures the
difference in time between two events. It has a 400ns full
scale and 100ps resolution. The start signal releases the
ramp generator made up of the PNP current source and
the 250pF capacitor. The circuit ramps until the stop
signal shuts off the current source. The final value of the
ramp represents the time between the start and stop
events.TheLTC1273digitizesthisfinalvalueandoutputs
the digital data.
0
20
40
60
80
100
120
FREQUENCY (kHz)
LTC1273/75/76 • F24
Figure 24. 455kHz Input Voltage Modulated by a 5kHz Signal
21
LTC1273
LTC1275/LTC1276
O U
W
U
PPLICATI
A
S I FOR ATIO
7V
5V
10µF
2N2369
2N2369
65Ω
65Ω
400k
10µF
1N457
REF
V
DD
OUT
20k
2N5771
620Ω
LM134
12-BIT
DATA OUTPUT
A
IN
LTC1273
250pF
POLYSTYRENE
45.3Ω
CS
V
GND RD BUSY
SS
74HC03
1N457
45.3Ω
74HC74
5V
D
Q
Q
START↑
CLK
1N4148
1k
CLR
10k
100pF
DATA LATCH
SIGNAL
5V
D
Q
Q
5V
1k
1N4148
100k
STOP↑
CLK
0.001µF
CLR
1k
5V
10k
10pF
LTC1273/75/76 • F26
Figure 26. ∆Time Measurement with the LTC1273
22
LTC1273
LTC1275/LTC1276
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTIO
N Package
24-Lead Plastic DIP
1.265
(32.131)
24
23
22
21
20
19
18
17
16
15
10
14
11
13
12
0.260 ± 0.010
(6.604 ± 0.254)
3
4
5
6
7
8
9
1
2
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.015
(0.381)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.025
0.125
(3.175)
MIN
0.050 – 0.085
(1.27 – 2.159)
0.325
0.018 ± 0.003
(0.457 ± 0.076)
–0.015
+0.635
8.255
0.100 ± 0.010
(2.540 ± 0.254)
(
)
–0.381
S Package
24-Lead Plastic SOL
0.598 – 0.614
(15.190 – 15.600)
(NOTE 2)
24 23 22 21 20 19 18
16 15 14 13
17
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
2
3
5
7
8
9
10
1
4
6
11 12
0.291 – 0.299
(7.391 – 7.595)
(NOTE 2)
0.037 – 0.045
(0.940 – 1.143)
0.093 – 0.104
(2.362 – 2.642)
0.005
0.010 – 0.029
× 45°
(0.127)
(0.254 – 0.737)
RAD MIN
0° – 8° TYP
0.050
(1.270)
TYP
0.004 – 0.012
(0.102 – 0.305)
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.014 – 0.019
0.016 – 0.050
(0.356 – 0.482)
(0.406 – 1.270)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS.
2. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC1273
LTC1275/LTC1276
U.S. Area Sales Offices
SOUTHEAST REGION
Linear Technology Corporation
17060 Dallas Parkway
Suite 208
Dallas, TX 75248
Phone: (214) 733-3071
FAX: (214) 380-5138
SOUTHWEST REGION
Linear Technology Corporation
22141 Ventura Blvd.
NORTHEAST REGION
Linear Technology Corporation
One Oxford Valley
2300 E. Lincoln Hwy.,Suite 306
Langhorne, PA 19047
Suite 206
Woodland Hills, CA 91364
Phone: (818) 703-0835
FAX: (818) 703-0517
Phone: (215) 757-8578
FAX: (215) 757-5631
CENTRAL REGION
Linear Technology Corporation
Chesapeake Square
NORTHWEST REGION
Linear Technology Corporation
782 Sycamore Dr.
Linear Technology Corporation
266 Lowell St., Suite B-8
Wilmington, MA 01887
Phone: (508) 658-3881
FAX: (508) 658-2701
229 Mitchell Court, Suite A-25
Addison, IL 60101
Phone: (708) 620-6910
FAX: (708) 620-6977
Milpitas, CA 95035
Phone: (408) 428-2050
FAX: (408) 432-6331
International Sales Offices
FRANCE
KOREA
TAIWAN
Linear Technology S.A.R.L.
Immeuble "Le Quartz"
58 Chemin de la Justice
92290 Chatenay Malabry
France
Linear Technology Korea Branch
Namsong Building, #505
Itaewon-Dong 260-199
Yongsan-Ku, Seoul
Korea
Linear Technology Corporation
Rm. 801, No. 46, Sec. 2
Chung Shan N. Rd.
Taipei, Taiwan, R.O.C.
Phone: 886-2-521-7575
FAX: 886-2-562-2285
Phone: 33-1-41079555
FAX: 33-1-46314613
Phone: 82-2-792-1617
FAX: 82-2-792-1619
UNITED KINGDOM
GERMANY
SINGAPORE
Linear Technology (UK) Ltd.
The Coliseum, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
Phone: 44-276-677676
FAX: 44-276-64851
Linear Techonolgy GMBH
Untere Hauptstr. 9
D-85386 Eching
Germany
Phone: 49-89-3197410
FAX: 49-89-3194821
Linear Technology Pte. Ltd.
101 Boon Keng Road
#02-15 Kallang Ind. Estates
Singapore 1233
Phone: 65-293-5322
FAX: 65-292-0398
JAPAN
Linear Technology KK
5F YZ Bldg.
Iidabashi, Chiyoda-Ku
Tokyo, 102 Japan
Phone: 81-3-3237-7891
FAX: 81-3-3237-8010
World Headquarters
Linear Technology Corporation
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
Phone: (408) 432-1900
FAX: (408) 434-0507
06/24/93
LT/GP 0893 10K REV 0
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
24
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1993
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