LTC1391CS [Linear]
8-Channel Analog Multiplexer with Cascadable Serial Interface; 8通道模拟多路复用器级联的串行接口
| 型号： | LTC1391CS |
| 厂家： | 
Linear |
| 描述： | 8-Channel Analog Multiplexer with Cascadable Serial Interface |
| 文件： | 总9页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1391
8-Channel
Analog Multiplexer with
Cascadable Serial Interface
U
FEATURES
DESCRIPTION
TheLTC ®1391isahighperformanceCMOS8-to-1analog
multiplexer. It features a serial digital interface that allows
several LTC1391s to be daisy-chained together, increas-
ing the number of MUX channels available using a single
digital port.
■
Low RON: 45Ω
■
Single 2.7V to ±5V Supply Operation
■
Analog Inputs May Extend to Supply Rails
Low Charge Injection
Serial Digital Interface
Low Leakage: ±5nA Max
Guaranteed Break-Before-Make
TTL/CMOS Compatible for All Digital Inputs
■
■
■
The LTC1391 features a typical RON of 45Ω, a typical
switch leakage of 50pA and guaranteed break-before-
make operation. Charge injection is ±10pC maximum. All
digital inputs are TTL and CMOS compatible when oper-
ated from single or dual supplies. The inputs can with-
stand 100mA fault current.
■
■
■
Cascadable to Allow Additional Channels
Can Be Used as a Demultiplexer
■
U
APPLICATIONS
The LTC1391 is available in 16-pin PDIP, SSOP and
narrow SO packages. For applications requiring 2-way
serial data transmission, see the LTC1390 data sheet.
■
Data Acquisition Systems
Communication Systems
Signal Multiplexing/Demultiplexing
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
U
TYPICAL APPLICATION
On-Resistance vs
Analog Input Voltage
3V, 8-Channel 12-Bit ADC
3V
300
OPTIONAL A/D
INPUT FILTER
1µF
0.1µF
1
2
3
4
8
7
6
5
T
= 25°C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
+
V
V
S0
S1
S2
S3
S4
S5
S6
S7
V
REF
CC
250
200
150
100
50
+
–
+IN
–IN
GND
CLK
V
V
= 2.7V
= 0V
D
–
LTC1285
V
D
OUT
D
ANALOG
INPUTS
CS/SHDN
OUT
LTC1391
D
IN
CS
CLK
+
–
V
= 5V
= –5V
GND
V
0
DATA IN
CLK
–5 –4 –3 –2 –1
0
1
2
3
4
5
SERIAL INTERFACE
TO MUX AND ADC
ANALOG INPUT VOLTAGE (V)
CS
1391 TA02
DATA OUT
1391 TA01
1
LTC1391
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
ORDER PART
NUMBER
Total Supply Voltage (V+ to V–) .............................. 15V
Input Voltage
+
S0
S1
S2
S3
S4
S5
S6
S7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
D
V
D
D
Analog Inputs ................... (V– – 0.3V) to (V+ + 0.3V)
Digital Inputs .........................................–0.3V to 15V
Digital Outputs ..........................–0.3V to (V+ + 0.3V)
Power Dissipation.............................................. 500mW
Operating Temperature Range
–
LTC1391CGN
LTC1391CN
LTC1391CS
LTC1391IGN
LTC1391IN
LTC1391IS
OUT
IN
CS
CLK
GND
LTC1391C ............................................... 0°C to 70°C
LTC1391I........................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
GN PACKAGE
N PACKAGE
GN PART MARKING
16-LEAD PLASTIC SSOP 16-LEAD PDIP
S PACKAGE
16-LEAD PLASTIC SO
1391
1391I
TJMAX = 125°C, θJA = 110°C/ W (GN)
T
T
JMAX = 125°C, θJA = 70°C/ W (N)
JMAX = 125°C, θJA = 100°C/ W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
V+ = 5V, V– = –5V, GND = 0V, TA = operating temperature range, unless otherwise specified.
SYMBOL PARAMETER
Switch
CONDITIONS
MIN
TYP
MAX
UNITS
V
R
Analog Signal Range
On-Resistance
(Note 2)
V = ±3.5V
S
●
–5
5
75
V
Ω
ANALOG
T
MIN
ON
I = 1mA
D
25°C
45
75
Ω
T
120
Ω
MAX
∆R vs V
20
0.5
%
%/°C
ON
S
∆R vs Temperature
ON
I
I
I
Off Input Leakage
Off Output Leakage
On Channel Leakage
V = 4V, V = –4V, V = –4V, V = 4V
Channel Off
±0.05
±5
±20
±5
±20
±5
±20
nA
nA
nA
nA
nA
nA
S(OFF)
D(OFF)
D(ON)
S
D
S
D
●
●
●
V = 4V, V = –4V, V = –4V, V = 4V
±0.05
±0.05
S
D
S
D
Channel Off
V = V = ±4V
S
D
Channel On
Digital
+
V
INH
V
INL
High Level Input Voltage
Low Level Input Voltage
Input Current
V = 5.25V
●
●
●
2.4
2.4
V
V
µA
V
V
V
+
V = 4.75V
0.8
±5
I
, I
INL INH
V
= 5V, 0V
IN
+
V
OH
High Level Output Voltage
V = 4.75V, I = –10µA
4.74
4.50
0.5
O
I = –360µA
●
●
O
+
V
OL
Low Level Output Voltage
V = 4.75V, I = 1.6mA
0.8
O
Dynamic
f
t
t
t
Clock Frequency
(Note 2)
5
400
200
MHz
ns
ns
ns
dB
pC
CLK
ON
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Off Isolation
V = 2.5V, R = 1k, C = 35pF
260
100
155
70
S
L
L
V = 2.5V, R = 1k, C = 35pF
S
OFF
L
L
35
OPEN
OIRR
Q
V = 2V , R = 1k, f = 100kHz
S
P–P
L
Charge Injection
R = 0, C = 1000pF, V = 1V (Note 2)
S
±2
±10
INJ
L
S
2
LTC1391
ELECTRICAL CHARACTERISTICS
V+ = 5V, V– = –5V, GND = 0V, TA = operating temperature range, unless otherwise specified.
SYMBOL PARAMETER
Dynamic
CONDITIONS
MIN
TYP
MAX
UNITS
C
S(OFF)
C
D(0FF)
Input Off Capacitance
Output Off Capacitance
5
10
pF
pF
Supply
+
I
I
Positive Supply Current
Negative Supply Current
All Logic Inputs Tied Together, V = 0V or 5V
●
●
15
–15
40
–40
µA
µA
IN
–
All Logic Inputs Tied Together, V = 0V or 5V
IN
V+ = 2.7V, V– = GND = 0V, TA = operating temperature range, unless otherwise specified.
SYMBOL PARAMETER
Switch
CONDITIONS
MIN
TYP
MAX
UNITS
V
R
Analog Signal Range
On-Resistance
(Note 2)
V = 1.2V
S
●
0
2.7
300
300
350
V
Ω
ANALOG
T
MIN
ON
I = 1mA
O
25°C
250
Ω
T
Ω
MAX
∆R vs V
20
0.5
%
%/°C
ON
S
∆R vs Temperature
ON
I
I
I
Off Input Leakage
Off Output Leakage
On Channel Leakage
V = 2.5V, V = 0.5V; V = 0.5V, V = 2.5V (Note 3)
Channel Off
±0.05
±5
±20
±5
±20
±5
±20
nA
nA
nA
nA
nA
nA
S(OFF)
D(OFF)
D(ON)
S
D
S
D
●
●
●
V = 2.5V, V = 0.5V; V = 0.5V, V = 2.5V (Note 3)
±0.05
±0.05
S
D
S
D
Channel Off
V = V = 0.5V, 2.5V (Note 3)
S
D
Channel On
Digital
+
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V = 3.0V
●
●
●
2.0
2.0
V
V
µA
V
V
V
V
INH
INL
+
V = 2.4V
0.8
±5
I
, I
INL INH
V
= 2.7V, 0V
IN
+
V
High Level Output Voltage
V = 2.7V, I = –20µA
2.68
2.30
0.01
0.20
OH
O
I = –400µA
●
●
O
+
V
Low Level Output Voltage
V = 2.7V, I = 20µA
OL
O
I = 400µA
O
0.8
Dynamic
f
t
t
t
Clock Frequency
(Note 2)
V = 1.5V, R = 1k, C = 35pF (Note 4)
5
800
400
MHz
ns
ns
CLK
ON
Enable Turn-On Time
Enable Turn-Off Time
Break-Before-Make Interval
Off Isolation
Charge Injection
Input Off Capacitance
Output Off Capacitance
490
190
290
70
±1
5
S
L
L
V = 1.5V, R = 1k, C = 35pF (Note 4)
OFF
S
L
L
(Note 4)
125
ns
OPEN
QIRR
Q
C
C
V = 2V , R = 1k, f = 100kHz
dB
pC
pF
S
P–P
L
R = 0, C = 1000pF, V = 1V (Note 2)
±5
INJ
S
L
S
S(OFF)
10
pF
D(OFF)
Supply
+
I
Positive Supply Current
All Logic Inputs Tied Together, V = 0V or 2.7V
●
0.2
2
µA
IN
The
●
denotes specifications which apply over the full operating
Note 2: Guaranteed by Design.
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 3: Leakage current with a single 2.7V supply is guaranteed by
correlation with the ±5V leakage current specifications.
of a device may be impaired.
Note 4: Timing specifications with a single 2.7V supply are guaranteed by
correlation with the ±5V timing specifications.
3
LTC1391
U W
TYPICAL PERFORMANCE CHARACTERISTICS
Driver Output Low Voltage
vs Output Current
Driver Output Low Voltage
vs Temperature
On-Resistance vs Temperature
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
300
250
200
150
100
50
T
= 25°C
+
A
V
= 2.7V
–
+
–
V
= 0V
V
V
O
= 5V
+
V
= 2.7V
V
= 1.2V
= –5V
S
–
V
= 0V
I
= 1.8mA
+
–
+
–
V
O
= 2.7V
V
= 5V
= –5V
= 0V
+
–
V
= 0V
V
V
V
= 5V
= –5V
I
= 400µA
V
S
0
20
40
60
–40 –20
0
80
–40 –20
0
20
40
60
80
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
1391 G01
1391 G03
1391 G02
Driver Output High Voltage
vs Temperature
Driver Output High Voltage
vs Output Current
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
+
V
V
O
= 5V
+
–
V
V
= 2.7V
= 0V
–
= –5V
I
= 1.6mA
+
V
= 5V
–
V
= –5V
+
V
= 2.7V
–
V
= 0V
I
= 400µA
O
T
=25°C
A
4.5
2.0
2.5
3.0
3.5
4.0
5.0
–40 –20
0
20
40
60
80
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
1391 G04
1391 G05
U
U
U
PIN FUNCTIONS
S0, S1, S2, S3, S4, S5, S6, S7 (Pins 1, 2, 3, 4, 5, 6, 7,
8): Analog Multiplexer Inputs.
DOUT into three-state and enables the selected channel for
analog signal transmission.
GND (Pin 9): Digital Ground. Connect to system ground.
DIN (Pin 12): Digital Input (TTL/CMOS Compatible). Input
for the channel selection bits.
CLK(Pin10): SystemClock(TTL/CMOSCompatible). The
DOUT (Pin 13): Digital Output (TTL/CMOS Compatible).
Output from the internal shift register.
clock synchronizes the channel selection bits and the
serial data transfer from DIN to DOUT
.
CS (Pin 11): Channel Select Input (TTL/CMOS Compat-
ible). A logic high on this input enables the LTC1391 to
read in the channel selection bits and allows digital data
transfer from DIN to DOUT. A logic low on this input puts
V– (Pin 14): Negative Supply.
D (Pin 15): Analog Multiplexer Output.
V+ (Pin 16): Positive Supply.
4
LTC1391
U
W U U
APPLICATIONS INFORMATION
Multiplexer Operation
selection of next channel. If the “EN” bit is logic low, as
illustrated in the second data sequence, it disables all
channels and there will be no analog signal transmission.
Table 1 shows the various bit combinations for channel
selection.
Figure 1 shows the block diagram of the components
within the LTC1391 required for MUX operation. The
LTC1391usesDIN toselecttheactivechannelandthechip
select input, CS, to switch on the selected channel as
shown in Figure 2.
Table 1. Logic Table for Channel Selection
ACTIVE CHANNEL
EN
B2
X
0
B1
X
0
BO
X
0
When CS is high, the input data on the DIN pin is latched
into the 4-bit shift register on the rising clock edge. The
input data consists of the “EN” bit and a string of three bits
for channel selection. If “EN” bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. After the clocking in of the last channel selection
bit B0, the CS pin must be pulled low before the next rising
clock edge to ensure correct operation. Once CS is pulled
low, the previously selected channel is switched off to
ensure a break-before-make interval. After a delay of tON,
the selected channel is switched on allowing signal trans-
mission. The selected channel remains on until the next
falling edge of CS. After a delay of tOFF, the LTC1391
terminates the analog signal transmission and allows the
All Off
S0
0
1
S1
1
0
0
1
S2
1
0
1
0
S3
1
0
1
1
S4
1
1
0
0
S5
1
1
0
1
S6
1
1
1
0
S7
1
1
1
1
Digital Data Transfer Operation
The block diagram of Figure 3 shows the components
within theLTC1391 required forserialdatatransfer. When
CS is held high, data is fed into the 4-bit shift register and
then shifted to DOUT. Data appears at DOUT after the fourth
rising edge of the clock as shown in Figure 4. The last four
CLK
CONTROL
LOGIC
4-BIT SHIFT
REGISTER
D
IN
CS
CLK
CONTROL
LOGIC
4-BIT SHIFT
REGISTER
D
D
OUT
IN
ANALOG
OUTPUT (D)
MUX
BLOCK
ANALOG INPUTS
(S0 TO S7)
CS
1391 F03
1391 • F01
Figure 3. Simplified Block Diagram of the
Digital Data Transfer Operation
Figure 1. Simplified Block Diagram of the MUX Operation
CLK
CS
EN
HIGH
EN LO
D
B2
B1
B0
B2
B1
B0
IN
ANY ANALOG
INPUT
D
t
t
OFF
ON
1391 • F02
Figure 2. Multiplexer Operation
5
LTC1391
U
W U U
APPLICATIONS INFORMATION
To ensure that only one channel is switched on at any one
time, two sets of channel selection bits are needed for
DATAasshowninFigure6. Thefirstdatasequenceisused
to switch off one MUX and the second data sequence is
used to select one channel from the other MUX or
vice versa. In other words, if bit “ENA” is high and bit
“ENB” is low, one channel of MUX A is switched on and all
channels of MUX B are switched off. If bit “ENA” is low and
bit “ENB” is high, all channels at MUX A are switched off
and one channel of MUX B is switched on. Care should be
taken to ensure that only one LTC1391 is enabled at any
one time to prevent two channels from being enabled
simultaneously.
bits clocked into the LTC1391 shift register before CS is
taken low select the MUX channel that is turned on. This
allows a series of devices, with the DOUT of one device
connected to the DIN of the next device, to be programmed
with a single data stream.
CLK
1
2
3
4
D
D3
D4
D5
D1
D2
IN
D
OUT
D3
D4
D5
D1
D2
1391 • F04
Figure 4. Digital Data Transfer Operation
CLK
1
2
3
4
5
6
7
8
Multiplexer Expansion
CS
Several LTC1391s can be daisy-chained to expand the
number of multiplexer inputs. No additional interface
ports are required for the expansion. Figure 5 shows two
LTC1391s connected at their analog outputs to form a
16-to-1multiplexerattheinputtoanLTC1400A/Dconverter.
D
ENA
A2
A1
A0
ENB
B2
B1
B0
IN
1391 • F06
Figure 6. Data Sequence for MUX Expansion
–5V
5V
5V
0.1µF
+
0.1µF
0.1µF
10µF
10µF
OPTIONAL A/D
INPUT FILTER
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
V
A
V
V
SS
–5V
0.1µF
S0
S1
S2
S3
S4
S5
S6
S7
V
CC
+
D
–
CONV
LTC1400
IN
V
CLK
REF
+
0.1µF
DATA
OUT
10µF
D
ANALOG
INPUTS
OUT
GND
D
OUT
LTC1391
A
D
IN
CS
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
S1
S2
S3
S4
S5
S6
S7
V
D
–
V
D
OUT
ANALOG
INPUTS
LTC1391
B
DATA IN
CS
D
IN
CS
CLK
GND
CLK
1391 • F05
Figure 5. Daisy-Chaining Two LTC1391s for Expansion
6
LTC1391
U
TYPICAL APPLICATIONS
Daisy-Chaining Five LTC1391s
5V
0.1µF BYPASS CAPACITORS FROM
+
V
TO GND FOR EACH LTC1391
0.1µF
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
V
V
CC
S0
S1
S2
S3
S4
S5
S6
S7
V
REF
D
–
+IN
–IN
GND
CLK
LTC1286
DATA
OUT
V
D
OUT
CS
LTC1391
A
D
ANALOG
INPUTS
OUT
D
IN
CS
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
S1
S2
S3
S4
S5
S6
S7
V
D
–
V
LTC1391
B
D
ANALOG
INPUTS
OUT
D
IN
CS
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
S1
S2
S3
S4
S5
S6
S7
V
D
–
V
LTC1391
C
D
ANALOG
INPUTS
OUT
D
IN
CS
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
S1
S2
S3
S4
S5
S6
S7
V
D
–
V
LTC1391
D
D
ANALOG
INPUTS
OUT
D
IN
CS
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
S0
S1
S2
S3
S4
S5
S6
S7
V
D
–
V
LTC1391
E
D
ANALOG
INPUTS
OUT
DATA IN
CS
D
IN
CS
CLK
GND
CLK
1391 TA04
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
7
LTC1391
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 – 0.196*
(4.801 – 4.978)
0.009
(0.229)
REF
0.015 ± 0.004
(0.38 ± 0.10)
16 15 14 13 12 11 10 9
× 45°
0.053 – 0.068
(1.351 – 1.727)
0.004 – 0.0098
(0.102 – 0.249)
0.007 – 0.0098
(0.178 – 0.249)
0° – 8° TYP
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
0.016 – 0.050
(0.406 – 1.270)
0.0250
(0.635)
BSC
0.008 – 0.012
(0.203 – 0.305)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
GN16 (SSOP) 1098
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
5
6
7
8
N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.770*
(19.558)
MAX
0.300 – 0.325
(7.620 – 8.255)
0.130 ± 0.005
(3.302 ± 0.127)
0.045 – 0.065
(1.143 – 1.651)
14
12
10
9
15
13
11
16
0.015
(0.381)
MIN
0.255 ± 0.015*
(6.477 ± 0.381)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.025
2
1
3
4
6
8
5
7
0.325
0.005
(0.127)
MIN
0.100 ± 0.010
(2.540 ± 0.254)
–0.015
0.125
(3.175)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
+0.635
8.255
N16 0695
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020
(0.254 – 0.508)
16
15
14
13
12
11
10
9
× 45°
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0° – 8° TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
0.016 – 0.050
0.406 – 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
1
2
3
4
5
6
7
8
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
S16 0695
8
LTC1391
U
TYPICAL APPLICATION
Interfacing LTC1391 with LTC1257 for Demultiplex Operation
16
+
1
2
3
4
5
6
7
8
+
5V ≤ V ≤ 12V
S0
S1
S2
S3
S4
S5
S6
S7
V
15
D
–
0.1µF
14
13
12
11
10
9
47k
V
D
ANALOG
OUT
LTC1391
OUTPUTS
D
IN
OPTIONAL D/A
OUTPUT FILTER
CS
8
7
6
5
1
2
3
4
CLK
CLK
V
CC
GND
0.1µF
D
V
OUT
IN
LTC1257
LOAD
V
REF
DATA
CLK
CS
D
GND
OUT
TTL COMPATIBLE
+
1391 TA03
AT V = 5V
RELATED PARTS
PART NUMBER
LTC1285
DESCRIPTION
3V 12-Bit ADC
5V 12-Bit ADC
COMMENTS
Micropower, Auto Shutdown, SO-8 Package, SPI, QSPI + MICROWIRETM Compatible
Micropower, Auto Shutdown, SO-8 Package, SPI, QSPI + MICROWIRE Compatible
LTC1286
LTC1390
Serial-Controlled 8-to-1 Analog Multiplexer
5V 12-Bit DAC
Low R , Bidirectional Serial Interface, Low Power, 16-Pin SO
ON
LTC1451
Complete V
DAC, SO-8 Package, Daisy-Chainable, Low Power
OUT
LTC1452
5V and 3V 12-Bit DAC
3V 12-Bit DAC
Multiplying V
DAC, SO-8 Package, Rail-to-Rail Output, Low Power
OUT
LTC1453
Complete V
DAC, SO-8 Package, Daisy-Chainable, Low Power
OUT
MICROWIRE is a trademark of National Semiconductor.
1391f, sn1391 LT/GP 0896 7K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
9
●
●
(408) 432-1900 FAX: (408) 434-0507 TELEX: 499-3977
LINEAR TECHNOLOGY CORPORATION 1995
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