LTC1407AIMSE_技术文档

LTC1407/LTC1407A

Serial 12-Bit/14-Bit, 3Msps

Simultaneous Sampling

ADCs with Shutdown

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FEATURES

DESCRIPTIO

The LTC^®1407/LTC1407A are 12-bit/14-bit, 3Msps ADCs

with two 1.5Msps simultaneously sampled differential

inputs. The devices draw only 4.7mA from a single 3V

supply and come in a tiny 10-lead MS package. A Sleep

shutdown feature lowers power consumption to 10µW.

The combination of speed, low power and tiny package

makes the LTC1407/LTC1407A suitable for high speed,

portable applications.

■

3Msps Sampling ADC with Two Simultaneous

Differential Inputs

■

1.5Msps Throughput per Channel

■

Low Power Dissipation: 14mW (Typ)

3V Single Supply Operation

2.5V Internal Bandgap Reference with External

Overdrive

3-Wire Serial Interface

Sleep (10µW) Shutdown Mode

Nap (3mW) Shutdown Mode

80dB Common Mode Rejection at 100kHz

0V to 2.5V Unipolar Input Range

Tiny 10-Lead MS Package

■

The LTC1407/LTC1407A contain two separate differential

inputs that are sampled simultaneously on the rising edge

of the CONV signal. These two sampled inputs are then

converted at a rate of 1.5Msps per channel.

■

The 80dB common mode rejection allows users to elimi-

nategroundloopsandcommonmodenoisebymeasuring

signals differentially from the source.

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APPLICATIO S

■

Telecommunications

The devices convert 0V to 2.5V unipolar inputs differen-

tially. The absolute voltage swing for CH0⁺, CH0^–, CH1⁺

and CH1^–extends from ground to the supply voltage.

■

Data Acquisition Systems

■

Uninterrupted Power Supplies

Multiphase Motor Control

I & Q Demodulation

Industrial Control

■

The serial interface sends out the two conversion results in

32 clocks for compatibility with standard serial interfaces.

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

W

BLOCK DIAGRA

10µF 3V

THD, 2nd and 3rd

vs Input Frequency

7

V

DD

LTC1407A

–44

+

–

CH0

1

2

+

–

–50

S & H

THD

–56

–62

2nd

THREE-

STATE

SERIAL

OUTPUT

PORT

3Msps

14-BIT ADC

MUX

8

SDO

–68

–74

3rd

+

–

CH1

4

5

3

+

–80

–86

S & H

–

10

9

CONV

SCK

–92

TIMING

LOGIC

V

REF

–98

10µF

–104

GND

2.5V

REFERENCE

0.1

1

10

100

6

FREQUENCY (MHz)

EXPOSED PAD

11

1407 G02

1407A BD

1407f

1

LTC1407/LTC1407A

W W U W

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ABSOLUTE AXI U RATI GS

(Notes 1, 2)

PACKAGE/ORDER I FOR ATIO

Supply Voltage (V_DD)................................................. 4V

Analog Input Voltage

ORDER PART

NUMBER

TOP VIEW

(Note 3) ................................... – 0.3V to (V_DD+ 0.3V)

Digital Input Voltage .................... – 0.3V to (V_DD+ 0.3V)

Digital Output Voltage.................. – 0.3V to (V_DD+ 0.3V)

Power Dissipation.............................................. 100mW

Operation Temperature Range

LTC1407C/LTC1407AC............................ 0°C to 70°C

LTC1407I/LTC1407AI ......................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

+

–

LTC1407CMSE

CH0

V

1

2

3

4

5

10 CONV

9

8

7

6

SCK

SDO

DD

GND

LTC1407IMSE

11

REF

+

–

CH1

V

LTC1407ACMSE

LTC1407AIMSE

MSE PACKAGE

10-LEAD PLASTIC MSOP

MSE PART MARKING

T_JMAX= 125°C, θ_JA= 150°C/ W

EXPOSED PAD IS GND (PIN 11)

MUST BE SOLDERED TO PCB

LTBDQ

LTBDR

LTAFE

LTAFF

Consult LTC Marketing for parts specified with wider operating temperature ranges.

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CO VERTER CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. With internal reference, V_DD= 3V.

LTC1407

MIN TYP MAX

LTC1407A

MIN TYP MAX

PARAMETER

CONDITIONS

UNITS

Bits

Resolution (No Missing Codes)

Integral Linearity Error

Offset Error

●

12

14

(Notes 5, 17)

(Notes 4, 17)

(Note 17)

–2 ±0.25

–10 ±1

–5 ±0.5

2

10

5

–4 ±0.5

4

LSB

–20

–10

±2

±1

20

10

Offset Match from CH0 to CH1

Gain Error

(Notes 4, 17)

(Note 17)

●

–30

–5

±5

±1

30

5

–60 ±10 60

Gain Match from CH0 to CH1

Gain Tempco

–10

±2

10

Internal Reference (Note 4)

External Reference

±15

±1

±15

±1

ppm/°C

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A ALOG I PUT

The ● denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. With internal reference, V_DD= 3V.

SYMBOL PARAMETER CONDITIONS

MIN

TYP

MAX

UNITS

V

Analog Differential Input Range (Notes 3, 9)

2.7V ≤ V ≤ 3.3V

0 to 2.5

V

IN

DD

Analog Common Mode + Differential

Input Range (Note 10)

0 to V

CM

DD

I

Analog Input Leakage Current

●

1

µA

pF

ns

ps

IN

C

Analog Input Capacitance

13

IN

t

Sample-and-Hold Acquisition Time

Sample-and-Hold Aperture Delay Time

Sample-and-Hold Aperture Delay Time Jitter

Sample-and-Hold Aperture Skew from CH0 to CH1

Analog Input Common Mode Rejection Ratio

(Note 6)

39

ACQ

AP

1

0.3

JITTER

SK

200

CMRR

f

= 1MHz, V = 0V to 3V

= 100MHz, V = 0V to 3V

–60

–15

dB

IN

1407f

2

LTC1407/LTC1407A

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DY A IC ACCURACY

The ● denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. With internal reference, V_DD= 3V.

LTC1407

MIN TYP MAX

LTC1407A

MIN TYP MAX

SYMBOL

PARAMETER

CONDITIONS

UNITS

SINAD

Signal-to-Noise Plus

Distortion Ratio

100kHz Input Signal

750kHz Input Signal

100kHz Input Signal, External V = 3.3V, V ≥ 3.3V

70.5

68 70.5

72.0

73.5

70 73.5

76.3

dB

●

REF

DD

750kHz Input Signal, External V = 3.3V, V ≥ 3.3V

72.0

76.3

REF

DD

THD

SFDR

IMD

Total Harmonic

Distortion

100kHz First 5 Harmonics

750kHz First 5 Harmonics

–87

–83 –77

–90

–86 –80

dB

Spurious Free

Dynamic Range

100kHz Input Signal

750kHz Input Signal

–87

–83

–90

–86

dB

+

Intermodulation

Distortion

1.25V to 2.5V 1.40MHz into CH0 , 0V to 1.25V,

–82

dB

–

+

–

1.56MHz into CH0 . Also Applicable to CH1 and CH1

Code-to-Code

V

REF

= 2.5V (Note 17)

0.25

1

LSB

RMS

Transition Noise

Full Power Bandwidth

V

= 2.5V , SDO = 11585LSB (–3dBFS) (Note 15)

50

5

50

5

MHz

IN

P-P

Full Linear Bandwidth S/(N + D) ≥ 68dB

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T_A= 25°C. V_DD= 3V.

I TER AL REFERE CE CHARACTERISTICS

PARAMETER

CONDITIONS

= 0

MIN

TYP

2.5

15

MAX

UNITS

V

Output Voltage

Output Tempco

Line Regulation

Output Resistance

Settling Time

I

OUT

REF

ppm/°C

µV/V

Ω

V

= 2.7V to 3.6V, V = 2.5V

600

0.2

2

DD

REF

Load Current = 0.5mA

ms

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The ● denotes the specifications which apply over the

DIGITAL I PUTS A D DIGITAL OUTPUTS

full operating temperature range, otherwise specifications are at T_A= 25°C. V_DD= 3V.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

V

= 3.3V

= 2.7V

●

2.4

V

IH

IL

DD

IN

0.6

I

= 0V to V

±10

µA

pF

V

IN

DD

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

5

IN

V

= 3V, I = –200µA

OUT

●

2.5

2.9

OH

OL

DD

V

= 2.7V, I

= 160µA

= 1.6mA

0.05

0.10

V

DD

OUT

●

0.4

I

Hi-Z Output Leakage D

V

= 0V to V

DD

±10

µA

pF

OZ

OUT

C

Hi-Z Output Capacitance D

1

OZ

OUT

I

Output Short-Circuit Source Current

Output Short-Circuit Sink Current

V

= 0V, V = 3V

20

15

mA

SOURCE

SINK

OUT

DD

= V = 3V

DD

1407f

3

LTC1407/LTC1407A

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POWER REQUIRE E TS

The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. With internal reference, V_DD= 3V.

SYMBOL

PARAMETER

Supply Voltage

Supply Current

CONDITIONS

MIN

TYP

MAX

UNITS

V

2.7

3.6

V

DD

I

Active Mode, f

Nap Mode

Sleep Mode (LTC1407)

Sleep Mode (LTC1407A)

= 1.5Msps

SAMPLE

●

4.7

1.1

2.0

7.0

1.5

15

mA

µA

DD

10

µA

Active Mode with SCK in Fixed State (Hi or Lo)

12

mW

^PDW U ^{Power Dissipation}

The ● denotes the specifications which apply over the full operating temperature

TI I G CHARACTERISTICS

range, otherwise specifications are at T_A= 25°C. V_DD= 3V.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

f

Maximum Sampling Frequency per Channel

(Conversion Rate)

●

1.5

MHz

SAMPLE(MAX)

t

Minimum Sampling Period (Conversion + Acquisiton Period)

Clock Period

●

667

ns

THROUGHPUT

(Note 16)

(Note 6)

19.6

32

2

10000

ns

SCK

Conversion Time

34

SCLK cycles

CONV

Minimum Positive or Negative SCLK Pulse Width

CONV to SCK Setup Time

(Note 6)

ns

ms

1

(Notes 6, 10)

(Note 6)

3

2

SCK Before CONV

0

3

Minimum Positive or Negative CONV Pulse Width

SCK to Sample Mode

(Note 6)

4

(Note 6)

4

5

CONV to Hold Mode

(Notes 6, 11)

1.2

45

8

6

32nd SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13)

7

Minimum Delay from SCKto Valid Bits 0 Through 11

SCK to Hi-Z at SDO

(Notes 6, 12)

(Notes 6, 14)

8

6

9

Previous SDO Bit Remains Valid After SCK

2

10

12

V

Settling Time After Sleep-to-Wake Transition

2

REF

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground GND.

Note 10: If less than 3ns is allowed, the output data will appear one clock

cycle later. It is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

Note 11: Not the same as aperture delay. Aperture delay (1ns) is the

difference between the 2.2ns delay through the sample-and-hold and the

1.2ns CONV to Hold mode delay.

Note 12: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.

Note 3: When these pins are taken below GND or above V , they will be

clamped by internal diodes. This product can handle input currents greater

DD

than 100mA below GND or greater than V without latchup.

DD

+

Note 4: Offset and range specifications apply for a single-ended CH0 or

+

–

CH1 input with CH0 or CH1 grounded and using the internal 2.5V

reference.

Note 13: The time period for acquiring the input signal is started by the

32nd rising clock and it is ended by the rising edge of CONV.

Note 14: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10µF capacitive load.

Note 5: Integral linearity is tested with an external 2.55V reference and is

defined as the deviation of a code from the straight line passing through

the actual endpoints of a transfer curve. The deviation is measured from

the center of quantization band.

Note 15: The full power bandwidth is the frequency where the output code

Note 6: Guaranteed by design, not subject to test.

Note 7: Recommended operating conditions.

swing drops by 3dB with a 2.5V input sine wave.

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read with an arbitrarily long clock period.

Note 17: The LTC1407A is measured and specified with 14-bit Resolution

(1LSB = 152µV) and the LTC1407 is measured and specified with 12-bit

Resolution (1LSB = 610µV).

P-P

Note 8: The analog input range is defined for the voltage difference

+

–

+

–

between CH0 and CH0 or CH1 and CH1 .

+

–

+

–

Note 9: The absolute voltage at CH0 , CH0 , CH1 and CH1 must be

within this range.

1407f

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LTC1407/LTC1407A

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TYPICAL PERFOR A CE CHARACTERISTICS

V

_DD= 3V, T_A= 25°C (LTC1407A)

ENOBs and SINAD

vs Input Sinewave Frequency

THD, 2nd and 3rd

vs Input Frequency

SFDR vs Input Frequency

–44

–50

–56

–62

12.0

11.5

11.0

10.5

10.0

9.5

74

71

68

65

62

59

56

53

50

104

98

92

86

80

74

68

62

56

50

44

THD

2nd

–68

–74

3rd

–80

–86

9.0

–92

8.5

–98

8.0

0.1

–104

1

10

100

0.1

1

10

100

0.1

1

10

100

FREQUENCY (MHz)

1407 G01

1407 G02

1407 G19

98kHz Sine Wave 4096 Point

FFT Plot

748kHz Sine Wave 4096 Point

FFT Plot

SNR vs Input Frequency

74

71

68

65

62

59

56

53

50

0

–10

0

–10

–20

1.5Msps

–20

–30

–40

–50

–60

–70

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–90

–100

–110

–120

0.1

1

10

100

0

100 200 300 400 500 600 700

0

100 200 300 400 500 600 700

FREQUENCY (MHz)

FREQUENCY (kHz)

1407 G03

1407 G04

1407 G05

1403kHz Input Summed with

1563kHz Input IMD 4096 Point

FFT Plot

Differential Linearity for CH0 with

Internal 2.5V Reference

Integral Linearity End Point Fit for

CH0 with Internal 2.5V Reference

0

1.0

0.8

2.0

1.6

1.5Msps

–10

–20

0.6

1.2

–30

0.4

0.8

–40

0.2

0.4

–50

–60

0

–70

–0.2

–0.4

–0.6

–0.8

–1.0

–0.4

–0.8

–1.2

–1.6

–2.0

–80

–90

–100

–110

–120

0

100 200 300 400 500 600 700

FREQUENCY (kHz)

0

8192

OUTPUT CODE

12288

0

8192

12288

4096

16384

4096

16384

OUTPUT CODE

1407 G06

1407 G15

1407 G16

1407f

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LTC1407/LTC1407A

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V_DD= 3V, T_A= 25°C (LTC1407A)

TYPICAL PERFOR A CE CHARACTERISTICS

Differential Linearity for CH1 with

Internal 2.5V Reference

Integral Linearity End Point Fit for

CH1 with Internal 2.5V Reference

1.0

0.8

2.0

1.6

0.6

1.2

0.8

0.4

0.2

0.4

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.4

–0.8

–1.2

–1.6

–2.0

0

8192

12288

0

8192

12288

4096

16384

4096

16384

OUTPUT CODE

1407 G17

1407 G18

V_DD= 3V, T_A= 25°C (LTC1407/LTC1407A)

Full-Scale Signal Frequency

Response

CMRR vs Frequency

Crosstalk vs Frequency

0

12

–20

–30

–40

–50

–60

–70

–80

–90

6

0

–20

–40

–6

–12

–18

–60

–80

CH0

CH1

CH1 TO CH0

CH0 TO CH1

–24

–30

–36

–100

–120

1M

10M

100M

1G

100

1k

10k 100k

1M

10M 100M

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

1407 G08

1407 G07

1407 G09

Simultaneous Input Steps at CH0

and CH1 from 25Ω

PSSR vs Frequency

–25

–30

–35

–40

–45

–50

–55

–60

–65

–70

3.0

2.6

2.2

1.8

1.4

CH0

CH1

1.0

0.6

0.2

–0.2

–0.6

1

10

100

1k

10k 100k

1M

0

5

10

15

30

20

25

TIME (ns)

FREQUENCY (Hz)

1407 G11

1407 G10

1407f

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LTC1407/LTC1407A

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V_DD= 3V, T_A= 25°C (LTC1407/LTC1407A)

TYPICAL PERFOR A CE CHARACTERISTICS

Reference Voltage

vs Load Current

Reference Voltage vs V_DD

2.4902

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

2.4900

2.4898

2.4896

2.4894

2.4892

2.4890

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

LOAD CURRENT (mA)

2.6

2.8

3.0

3.2

(V)

3.4

3.6

V

DD

1407 G13

1407 G12

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PI FU CTIO S

CH0⁺(Pin1):NoninvertingChannel0. CH0⁺operatesfully

differentially with respect to CH0^–with a 0V to 2.5V

differential swing and a 0 to V_DDabsolute input range.

CH0^–(Pin 2): Inverting Channel 0. CH0^–operates fully

differentially with respect to CH0⁺with a –2.5V to 0V

differential swing and a 0 to V_DDabsolute input range.

V_DD(Pin 7): 3V Positive Supply. This single power pin

supplies3Vtotheentirechip. BypasstoGNDpinandsolid

analog ground plane with a 10µF ceramic capacitor (or

10µF tantalum) in parallel with 0.1µF ceramic. Keep in

mindthatinternalanalogcurrentsanddigitaloutputsignal

currents flow through this pin. Care should be taken to

place the 0.1µF bypass capacitor as close to Pins 6 and 7

as possible.

V_REF(Pin 3): 2.5V Internal Reference. Bypass to GND and

a solid analog ground plane with a 10µF ceramic capacitor

(or 10µF tantalum in parallel with 0.1µF ceramic). Can be

overdriven by an external reference voltage ≥2.55V and

≤V_DD.

SDO (Pin 8): Three-state Serial Data Output. Each pair of

output data words represent the two analog input chan-

nels at the start of the previous conversion.

SCK (Pin 9): External Clock Input. Advances the conver-

sion process and sequences the output data on the rising

edge. One or more pulses wake from sleep.

CH1⁺(Pin4):NoninvertingChannel1. CH1⁺operatesfully

differentially with respect to CH1^–with a 0V to 2.5V

differential swing and a 0 to V_DDabsolute input range.

CONV (Pin 10): Convert Start. Holds the two analog input

signals and starts the conversion on the rising edge. Two

pulses with SCK in fixed high or fixed low state starts Nap

mode. Four or more pulses with SCK in fixed high or fixed

low state starts Sleep mode.

CH1^–(Pin 5): Inverting Channel 1. CH1^–operates fully

differentially with respect to CH1⁺with a –2.5V to 0V

differential swing and a 0 to V_DDabsolute input range.

GND (Pins 6, 11): Ground and Exposed Pad. This single

ground pin and the Exposed Pad must be tied directly to

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

flow through these connections.

1407f

7

LTC1407/LTC1407A

W

BLOCK DIAGRA

10µF 3V

7

V

DD

LTC1407A

+

CH0

1

2

+

–

S & H

–

CH0

THREE-

STATE

SERIAL

OUTPUT

PORT

3Msps

14-BIT ADC

MUX

8

SDO

+

–

CH1

4

5

3

+

S & H

–

10

9

CONV

SCK

TIMING

LOGIC

V

REF

10µF

GND

2.5V

REFERENCE

6

EXPOSED PAD

11

1407A BD

1407f

8

LTC1407/LTC1407A

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W

TI I G DIAGRA S

1407f

9

LTC1407/LTC1407A

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W

TI I G DIAGRA S

Nap Mode and Sleep Mode Waveforms

SCK

t

1

t

1

CONV

NAP

SLEEP

t

12

V

1407 TD02

REF

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS

SCK to SDO Delay

SCK

V

IH

V

IH

t

10

8

t

9

V

90%

10%

OH

SDO

OL

1407 TD03

1407f

10

LTC1407/LTC1407A

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APPLICATIO S I FOR ATIO

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DRIVING THE ANALOG INPUT

increasing the time between conversions. The best choice

for an op amp to drive the LTC1407/LTC1407A depends

on the application. Generally, applications fall into two

categories: AC applications where dynamic specifications

are most critical and time domain applications where DC

accuracy and settling time are most critical. The following

list is a summary of the op amps that are suitable for

driving the LTC1407/LTC1407A. (More detailed informa-

tion is available in the Linear Technology Databooks and

on the LinearView^TMCD-ROM.)

The differential analog inputs of the LTC1407/LTC1407A

are easy to drive. The inputs may be driven differentially or

as a single-ended input (i.e., the CH0^–input is grounded).

All four analog inputs of both differential analog input

pairs, CH0⁺with CH0^–and CH1⁺with CH1^–, are sampled

at the same instant. Any unwanted signal that is common

to both inputs of each input pair will be reduced by the

common mode rejection of the sample-and-hold circuit.

The inputs draw only one small current spike while charg-

ing the sample-and-hold capacitors at the end of conver-

sion. During conversion, the analog inputs draw only a

small leakage current. If the source impedance of the

driving circuit is low, then the LTC1407/LTC1407A inputs

can be driven directly. As source impedance increases, so

will acquisition time. For minimum acquisition time with

high source impedance, a buffer amplifier must be used.

The main requirement is that the amplifier driving the

analog input(s) must settle after the small current spike

before the next conversion starts (settling time must be

39ns for full throughput rate). Also keep in mind, while

choosing an input amplifier, the amount of noise and

harmonic distortion added by the amplifier.

LTC1566-1: Low Noise 2.3MHz Continuous Time Low-

pass Filter.

LT^®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.

2.7V to ±15V supplies. Very high A_VOL, 500µV offset and

520ns settling to 0.5LSB for a 4V swing. THD and noise

are –93dB to 40kHz and below 1LSB to 320kHz (A_V= 1,

2V_P-Pinto1kΩ,V_S=5V),makingthepartexcellentforAC

applications (to 1/3 Nyquist) where rail-to-rail perfor-

mance is desired. Quad version is available as LT1631.

LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.

2.7V to ±15V supplies. Very high A_VOL, 1.5mV offset and

400ns settling to 0.5LSB for a 4V swing. It is suitable for

applications with a single 5V supply. THD and noise are

–93dB to 40kHz and below 1LSB to 800kHz (A_V= 1,

2V_P-Pinto1kΩ,V_S=5V),makingthepartexcellentforAC

applications where rail-to-rail performance is desired.

Quad version is available as LT1633.

CHOOSING AN INPUT AMPLIFIER

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a low

output impedance (< 100Ω) at the closed-loop bandwidth

frequency. For example, if an amplifier is used in a gain of

1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz must be less than 100Ω. The

second requirement is that the closed-loop bandwidth

must be greater than 40MHz to ensure adequate small-

signal settling for full throughput rate. If slower op amps

are used, more time for settling can be provided by

LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/ampli-

fier, 8.5nV/√Hz.

LT1806/LT1807: 325MHz GBWP, –80dBc distortion at

5MHz, unity gain stable, rail-to-rail in and out,

10mA/amplifier, 3.5nV/√Hz.

LT1810: 180MHz GBWP, –90dBc distortion at 5MHz,

unity gain stable, rail-to-rail in and out, 15mA/amplifier,

16nV/√Hz.

LinearView is a trademark of Linear Technology Corporation.

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APPLICATIO S I FOR ATIO

LT1818/LT1819: 400MHz, 2500V/µs, 9mA, Single/Dual

inputs to minimize noise. A simple 1-pole RC filter is suf-

ficientformanyapplications. Forexample, Figure1shows

a 47pF capacitor from CHO⁺to ground and a 51Ω source

resistor to limit the net input bandwidth to 30MHz. The

47pF capacitor also acts as a charge reservoir for the input

sample-and-hold and isolates the ADC input from sam-

pling-glitchsensitivecircuitry.Highqualitycapacitorsand

resistors should be used since these components can add

distortion. NPO and silvermica type dielectric capacitors

have excellent linearity. Carbon surface mount resistors

can generate distortion from self heating and from dam-

age that may occur during soldering. Metal film surface

mount resistors are much less susceptible to both prob-

lems. When high amplitude unwanted signals are close in

frequency to the desired signal frequency a multiple pole

filter is required.

Voltage Mode Operational Amplifier.

LT6200: 165MHz GBWP, –85dBc distortion at 1MHz,

unity gain stable, rail-to-rail in and out, 15mA/amplifier,

0.95nV/√Hz.

LT6203: 100MHz GBWP, –80dBc distortion at 1MHz,

unity gain stable, rail-to-rail in and out, 3mA/amplifier,

1.9nV/√Hz.

LT6600: Amplifier/Filter Differential In/Out with 10MHz

Cutoff.

INPUT FILTERING AND SOURCE IMPEDANCE

The noise and the distortion of the input amplifier and

other circuitry must be considered since they will add to

the LTC1407/LTC1407A noise and distortion. The small-

signalbandwidthofthesample-and-holdcircuitis50MHz.

Any noise or distortion products that are present at the

analog inputs will be summed over this entire bandwidth.

Noisy input circuitry should be filtered prior to the analog

High external source resistance, combined with 13pF of

inputcapacitance,willreducetherated50MHzinputband-

width and increase acquisition time beyond 39ns.

51Ω*

1

+

ANALOG

INPUT

CH0

47pF*

2

–

CH0

LTC1407/

LTC1407A

3

V

REF

10µF

11

GND

51Ω*

ANALOG

INPUT

4

+

CH1

47pF*

5

–

1407 F01

*TIGHT TOLERANCE REQUIRED TO AVOID

APERTURE SKEW DEGRADATION

Figure 1. RC Input Filter

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INPUT RANGE

overdrivenwithanexternalreferenceasshowninFigure 2.

The voltage of the external reference must be higher than

the2.5Voftheopen-drainP-channeloutputoftheinternal

reference. The recommended range for an external refer-

ence is 2.55V to V_DD. An external reference at 2.55V will

see a DC quiescent load of 0.75mA and as much as 3mA

during conversion.

The analog inputs of the LTC1407/LTC1407A may be

driven fully differentially with a single supply. Either input

may swing up to 3V, provided the differential swing is no

greater than 2.5V. In the valid input range, the noninvert-

ing input of each channel should always be more positive

than the inverting input of each channel. The 0V to 2.5V

range is also ideally suited for single-ended input use with

single supply applications. The common mode range of

the inputs extend from ground to the supply voltage V_DD.

If the difference between the CH0⁺and CH0^–inputs or the

CH1⁺and CH1^–inputs exceeds 2.5V, the output code will

stay fixed at all ones, and if this difference goes below 0V,

the ouput code will stay fixed at all zeros.

INPUT SPAN VERSUS REFERENCE VOLTAGE

The differential input range has a unipolar voltage span

that equals the difference between the voltage at the

reference buffer output V_REF(Pin 3) and the voltage at the

Exposed Pad ground. The differential input range of ADC

is 0V to 2.5V when using the internal reference. The

internal ADC is referenced to these two nodes. This

relationship also holds true with an external reference.

INTERNAL REFERENCE

The LTC1407/LTC1407A have an on-chip, temperature

compensated, bandgap reference that is factory trimmed

near 2.5V to obtain a precise 2.5V input span. The refer-

enceamplifieroutputV_REF,(Pin3)mustbebypassedwith

acapacitortoground.Thereferenceamplifierisstablewith

capacitors of 1µF or greater. For the best noise perfor-

mance, a 10µF ceramic or a 10µF tantalum in parallel with

a 0.1µF ceramic is recommended. The V_REFpin can be

DIFFERENTIAL INPUTS

The ADC will always convert the unipolar difference of

CH0⁺minus CH0^–or the unipolar difference of CH1⁺

minus CH1^–, independent of the common mode voltage at

either set of inputs. The common mode rejection holds up

at high frequencies (see Figure 3.) The only requirement is

that both inputs not go below ground or exceed V_DD.

0

–20

–40

3

3V REF

V

REF

LTC1407/

LTC1407A

GND

10µF

11

–60

1407 F02

CH0

CH1

–80

Figure 2

–100

–120

100

1k

10k 100k

1M

10M 100M

FREQUENCY (Hz)

1407 G08

Figure 3. CMRR vs Frequency

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APPLICATIO S I FOR ATIO

Integral nonlinearity errors (INL) and differential nonlin-

earityerrors(DNL)arelargelyindependentofthecommon

mode voltage. However, the offset error will vary. CMRR

is typically better than 60dB.

Highqualitytantalumandceramicbypasscapacitorsshould

be used at the V_DDand V_REFpins as shown in the Block

Diagram on the first page of this data sheet. For optimum

performance, a 10µF surface mount tantalum capacitor

witha0.1µFceramicisrecommendedfortheV_DDandV_REF

pins. Alternatively, 10µF ceramic chip capacitors such as

X5R or X7R may be used. The capacitors must be located

as close to the pins as possible. The traces connecting the

pins and the bypass capacitors must be kept short and

should be made as wide as possible. The V_DDbypass ca-

pacitorreturnstoGND(Pin6)andtheV_REFbypasscapaci-

torreturnstotheExposedPadground(Pin11).Careshould

be taken to place the 0.1µF V_DDbypass capacitor as close

to Pins 6 and 7 as possible.

Figure 4 shows the ideal input/output characteristics for

the LTC1407/LTC1407A. The code transitions occur mid-

way between successive integer LSB values (i.e., 0.5LSB,

1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural

binarywith1LSB=2.5V/16384=153µVfortheLTC1407A

and 1LSB = 2.5V/4096 = 610µV for the LTC1407. The

LTC1407A has 1LSB RMS of Gaussian white noise.

Board Layout and Bypassing

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC1407/LTC1407A, a printed cir-

cuit board with ground plane is required. Layout for the

printed circuit board should ensure that digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital track

alongside an analog signal track. If optimum phase match

between the inputs is desired, the length of the four input

wires of the two input channels should be kept matched.

But each pair of input wires to the two input channels

should be kept separated by a ground trace to avoid high

frequency crosstalk between channels.

Figure5showstherecommendedsystemgroundconnec-

tions. All analog circuitry grounds should be terminated at

the LTC1407/LTC1407A Exposed Pad. The ground return

from the LTC1407/LTC1407A Pin 6 to the power supply

should be low impedance for noise-free operation. The

Exposed Pad of the 10-lead MSE package is also tied to

Pin 6 and the LTC1407/LTC1407A GND. The Exposed Pad

should be soldered on the PC board to reduce ground

connection inductance. Digital circuitry grounds must be

connected to the digital supply common.

111...111

111...110

111...101

000...010

000...001

000...000

0

FS – 1LSB

INPUT VOLTAGE (V)

1407 F04

Figure 4. LTC1407/LTC1407A Transfer Characteristic

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1407 F05

Figure 5. Recommended Layout

conversion within a clock cycle. Four rising edges at

CONV, without any intervening rising edges at SCK, put

the LTC1407/LTC1407A in Sleep mode and the power

drain drops from 14mW to 10µW. One or more rising

edges at SCK wake up the LTC1407/LTC1407A for opera-

tion. The internal reference (V_REF) takes 2ms to slew and

settle with a 10µF load. Using sleep mode more frequently

compromises the settled accuracy of the internal refer-

ence. Note that for slower conversion rates, the Nap and

Sleep modes can be used for substantial reductions in

power consumption.

POWER-DOWN MODES

Upon power-up, the LTC1407/LTC1407A are initialized to

the active state and is ready for conversion. The Nap and

Sleep mode waveforms show the power down modes for

the LTC1407/LTC1407A. The SCK and CONV inputs con-

trol the power down modes (see Timing Diagrams). Two

rising edges at CONV, without any intervening rising

edges at SCK, put the LTC1407/LTC1407A in Nap mode

and the power drain drops from 14mW to 6mW. The

internal reference remains powered in Nap mode. One or

morerisingedgesatSCKwakeuptheLTC1407/LTC1407A

for service very quickly and CONV can start an accurate

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APPLICATIO S I FOR ATIO

DIGITAL INTERFACE

directly from the DSP crystal. Another problem with high

speed processor clocks is that they often use a low cost,

low speed crystal (i.e., 10MHz) to generate a fast, but

jittery, phase-locked-loop system clock (i.e., 40MHz). The

jitter in these PLL-generated high speed clocks can be

several nanoseconds. Note that if you choose to use the

frame sync signal generated by the DSP port, this signal

will have the same jitter of the DSP’s master clock.

The LTC1407/LTC1407A have a 3-wire SPI (Serial Proto-

col Interface) interface. The SCK and CONV inputs and

SDO output implement this interface. The SCK and CONV

inputs accept swings from 3V logic and are TTL compat-

ible, if the logic swing does not exceed V_DD. A detailed

description of the three serial port signals follows:

Conversion Start Input (CONV)

Serial Clock Input (SCK)

The rising edge of CONV starts a conversion, but subse-

quent rising edges at CONV are ignored by the LTC1407/

LTC1407A until the following 32 SCK rising edges have

occurred.ThedutycycleofCONVcanbearbitrarilychosen

to be used as a frame sync signal for the processor serial

port. A simple approach to generate CONV is to create a

pulsethatisoneSCKwidetodrivetheLTC1407/LTC1407A

and then buffer this signal to drive the frame sync input of

the processor serial port. It is good practice to drive the

LTC1407/LTC1407ACONVinputfirsttoavoiddigitalnoise

interference during the sample-to-hold transition trig-

gered by CONV at the start of conversion. It is also good

practice to keep the width of the low portion of the CONV

signal greater than 15ns to avoid introducing glitches in

the front end of the ADC just before the sample-and-hold

goes into Hold mode at the rising edge of CONV.

The rising edge of SCK advances the conversion process

and also udpates each bit in the SDO data stream. After

CONV rises, the third rising edge of SCK sends out two

sets of 12/14 data bits, with the MSB sent first. A simple

approach is to generate SCK to drive the LTC1407/

LTC1407A first and then buffer this signal with the appro-

priate number of inverters to drive the serial clock input of

the processor serial port. Use the falling edge of the clock

to latch data from the Serial Data Output (SDO) into your

processor serial port. The 14-bit Serial Data will be re-

ceived right justified, in two 16-bit words with 32 or more

clocks per frame sync. It is good practice to drive the

LTC1407/LTC1407A SCK input first to avoid digital noise

interference during the internal bit comparison decision

by the internal high speed comparator. Unlike the CONV

input, the SCK input is not sensitive to jitter because the

input signal is already sampled and held constant.

Minimizing Jitter on the CONV Input

Inhighspeedapplicationswherehighamplitudesinewaves

above 100kHz are sampled, the CONV signal must have as

little jitter as possible (10ps or less). The square wave

output of a common crystal clock module usually meets

this requirement easily. The challenge is to generate a

CONV signal from this crystal clock without jitter corrup-

tion from other digital circuits in the system. A clock

divider and any gates in the signal path from the crystal

clock to the CONV input should not share the same

integratedcircuitwithotherpartsofthesystem. Asshown

intheinterfacecircuitexamples,the SCKandCONVinputs

should be driven first, with digital buffers used to drive the

serial port interface. Also note that the master clock in the

DSP may already be corrupted with jitter, even if it comes

Serial Data Output (SDO)

Upon power-up, the SDO output is automatically reset to

the high impedance state. The SDO output remains in high

impedance until a new conversion is started. SDO sends

out two sets of 12/14 bits in the output data stream after

the third rising edge of SCK after the start of conversion

withtherisingedgeofCONV.Thetwo12-/14-bitwordsare

separated by two clock cycles in high impedance mode.

Please note the delay specification from SCK to a valid

SDO. SDO is always guaranteed to be valid by the next

rising edge of SCK. The 32-bit output data stream is

compatible with the 16-bit or 32-bit serial port of most

processors.

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HARDWARE INTERFACE TO TMS320C54x

and the serial clock at the BCLKR pin to accept an external

positive edge clock. Buffers near the LTC1407/LTC1407A

may be added to drive long tracks to the DSP to prevent

corruption of the signal to LTC1407/LTC1407A. This con-

figuration is adequate to traverse a typical system board,

but source resistors at the buffer outputs and termination

resistors at the DSP, may be needed to match the charac-

teristic impedance of very long transmission lines. If you

need to terminate the SDO transmission line, buffer it first

withoneortwo74ACxxgates. TheTTLthresholdinputsof

the DSP port respond properly to the 3V swing used with

the LTC1407/LTC1407A.

The LTC1407/LTC1407A are serial output ADCs whose

interface has been designed for high speed buffered serial

ports in fast digital signal processors (DSPs). Figure 6

shows an example of this interface using a TMS320C54X.

The buffered serial port in the TMS320C54x has direct

accesstoa2kBsegmentofmemory. TheADC’sserialdata

can be collected in two alternating 1kB segments, in real

time, at the full 3Msps conversion rate of the LTC1407/

LTC1407A.TheDSPassemblycodesetsframesyncmode

at the BFSR pin to accept an external positive going pulse

3V

5V

7

V

CC

DD

10

9

CONV

LTC1407/

LTC1407A

SCK

BFSR

TMS320C54x

BCLKR

B13 B12

8

6

SDO

GND

BDR

CONV

CLK

3-WIRE SERIAL

INTERFACELINK

1407 F06

0V TO 3V LOGIC SWING

Figure 6. DSP Serial Interface to TMS320C54x

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; 08-21-03 ******************************************************************

; Files: 1407ASIAB.ASM -> 1407A Sine wave collection with Serial Port interface

;

both channels collected in sequence in the same 2k record

bvectors.asm

s2k14ini.asm

buffered mode.

2k buffer size.

; unipolar mode

; Works 16 or 64 clock frames.

; negative edge BCLKR

; negative BFSR pulse

; -0 data shifted

; 1' cable from counter to CONV at DUT

; 2' cable from counter to CLK at DUT

; ***************************************************************************

.width

160

.length 110

.title “sineb0 BSP in auto buffer mode”

.mmregs

.setsect “.text”,

0x500,0

;Set address of executable

.setsect “vectors”, 0x180,0

.setsect “buffer”, 0x800,0

.setsect “result”, 0x1800,0

.text

;Set address of incoming 1407A data

;Set address of BSP buffer for clearing

;Set address of result for clearing

;.text marks start of code

start:

;this label seems necessary

;Make sure /PWRDWN is low at J1-9

;to turn off AC01 adc

tim=#0fh

prd=#0fh

tcr = #10h

tspc = #0h

pmst = #01a0h

sp = #0700h

dp = #0

; stop timer

; stop TDM serial port to AC01

; set up iptr. Processor Mode STatus register

; init stack pointer.

; data page

ar2 = #1800h

ar3 = #0800h

ar4 = #0h

; pointer to computed receive buffer.

; pointer to Buffered Serial Port receive buffer

; reset record counter

call sineinit

; Double clutch the initialization to insure a proper

sinepeek:

call sineinit

; reset. The external frame sync must occur 2.5 clocks

; or more after the port comes out of reset.

wait

;

goto

wait

————————Buffered Receive Interrupt Routine -————————-

breceive:

ifr = #10h

TC = bitf(@BSPCE,#4000h) ; check which half (bspce(bit14)) of buffer

if (NTC) goto bufull ; if this still the first half get next half

; clear interrupt flags

bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))

return_enable

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APPLICATIO S I FOR ATIO

;

———————mask and shift input data ——————————————

bufull:

b = *ar3+ << -0

b = #07FFFh & b

; load acc b with BSP buffer and shift right -0

; mask out the TRISTATE bits with #03FFFh

;

*ar2+ = data(#0bh)

; store B to out buffer and advance AR2 pointer

TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h

if (TC) goto start

goto bufull

; restart if out buffer is at 1fffh

;

—————————dummy bsend return————————————

return_enable ;this is also a dummy return to define bsend

;in vector table file BVECTORS.ASM

bsend

;

——————————— end ISR ——————————————

.copy “c:\dskplus\1407A\s2k14ini.asm”

;initialize buffered serial port

.space 16*32

;clear a chunk at the end to mark the end

;======================================================================

;

VECTORS

;======================================================================

.sect “vectors” ;The vectors start here

.copy “c:\dskplus\1407A\bvectors.asm” ;get BSP vectors

.sect “buffer”

.space 16*0x800

.sect “result”

.space 16*0x800

;Set address of BSP buffer for clearing

;Set address of result for clearing

.end

; ***************************************************************************

; File: BVECTORS.ASM -> Vector Table for the ‘C54x DSKplus 10.Jul.96

;

BSP vectors and Debugger vectors

TDM vectors just return

; ***************************************************************************

; The vectors in this table can be configured for processing external and

; internal software interrupts. The DSKplus debugger uses four interrupt

; vectors. These are RESET, TRAP2, INT2, and HPIINT.

;

*

DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER

*

; All other vector locations are free to use. When programming always be sure

; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and

; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the

; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.

;

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APPLICATIO S I FOR ATIO

.title “Vector Table”

.mmregs

reset

nmi

goto #80h

nop

;00; RESET * DO NOT MODIFY IF USING DEBUGGER *

;04; non-maskable external interrupt

return_enable

nop

trap2

int0

goto #88h

nop

.space 52*16

return_enable

;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *

;0C-3F: vectors for software interrupts 18-30

;40; external interrupt int0

nop

int1

return_enable

nop

return_enable

nop

return_enable

nop

goto breceive

nop

;44; external interrupt int1

;48; external interrupt int2

;4C; internal timer interrupt

;50; BSP receive interrupt

;54; BSP transmit interrupt

;58; TDM receive interrupt

int2

tint

brint

bxint

trint

goto bsend

nop

return_enable

nop

txint

int3

return_enable

nop

;5C; TDM transmit interrupt

;60; external interrupt int3

return_enable

nop

hpiint

dgoto #0e4h

;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *

nop

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.space 24*16

;68-7F; reserved area

**********************************************************************

*

* File: BSPI1407A.ASM BSP initialization code for the ‘C54x DSKplus

*

for use with 1407A in standard mode

BSPC and SPC seem interchangeable in the ‘C542

BSPCE and SPCE seem interchangeable in the ‘C542

**********************************************************************

.title “Buffered Serial Port Initialization Routine”

ON

.set 1

OFF

YES

.set !ON

.set 1

NO

.set !YES

.set 2

.set 1

.set 3

.set 0

BIT_8

BIT_10

BIT_12

BIT_16

GO

.set 0x80

**********************************************************************

* This is an example of how to initialize the Buffered Serial Port (BSP).

* The BSP is initialized to require an external CLK and FSX for

* operation. The data format is 16-bits, burst mode, with autobuffering

* enabled. Set the variables listed below to configure the BSP for

* your application.

*

*****************************************************************************************************

*LTC1407A timing with 40MHz crystal.

*

*10MHz, divided from 40MHz, forced to CLKIN by 1407A board.

*

*Horizontal scale is 6.25ns/chr or 25ns period at BCLKR

*

*BFSR Pin J1-20 ~~\____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\____/

~~~~~~~~~~~*

*BCLKR Pin J1-14 _/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/

~\_/~\_/~*

*BDR

B12*

Pin J1-26 _—_—_—<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>—_—<B13-

*CLKIN Pin J5-09 ~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/~~~~~~~\_______/

~~~~~~~\_______/~~~~~*

*C542 read

0

B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00

0

B13 B12*

*

* negative edge BCLKR

* negative BFSR pulse

* no data shifted

* 1' cable from counter to CONV at DUT

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* 2' cable from counter to CLK at DUT

*No right shift is needed to right justify the input data in the main program

*

*the two msbs should also be masked

*

****************************************************************************************************

*

Loopback

Format

IntSync

IntCLK

BurstMode

CLKDIV

PCM_Mode

FS_polarity

CLK_polarity

Frame_ignore

XMTautobuf

RCVautobuf

XMThalt

.set

NO

BIT_16

NO

YES

3

NO

YES

NO

!YES

NO

0x600

0x800

0x200

0x040

;(digital looback mode?)

;(Data format? 16,12,10,8)

;(internal Frame syncs generated?) TXM bit

;(internal clks generated?) MCM bit

;(if BurstMode=NO, then Continuous) FSM bit

;(3=default value, 1/4 CLOCKOUT)

;(Turn on PCM mode?)

;(change polarity)YES=~~~\_/~~~, NO=___/~\___

;(change polarity)for BCLKR YES=_/~, NO=~\_

;(inverted !YES -ignores frame)

;(transmit autobuffering)

DLB bit

FO bit

;(receive autobuffering)

;(transmit buff halt if XMT buff is full)

;(receive buff halt if RCV buff is full)

;(address of transmit buffer)

;(address of receive buffer)

;(length of transmit buffer)

RCVhalt

XMTbufAddr

RCVbufAddr

XMTbufSize

RCVbufSize

*

;(length of receive buffer)

* See notes in the ‘C54x CPU and Peripherals Reference Guide on setting up

* valid buffer start and length values.

*

**********************************************************************

.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync

<<5)) ,SPCval

.eval ((CLKDIV)|(FS_polarity <<5)|(CLK_polarity<<6)|((Format &

1)<<7)|(Frame_ignore<<8)|(PCM_Mode<<9)), SPCEval

.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<15)),

SPCEval

bspi1407A:

bspc = #SPCval

; places buffered serial port in reset

; programs BSPCE and ABU

; initializes transmit buffer start address

; initializes transmit buffer size

; initializes receive buffer start address

; initializes receive buffer size

bspce = #SPCEval

axr = #XMTbufAddr

bkx = #XMTbufSize

arr = #RCVbufAddr

bkr = #RCVbufSize

bspc = #(SPCval | GO)

return

; bring buffered serial port out of reset

; for transmit and receive because GO=0xC0

1407f

22

LTC1407/LTC1407A

U

PACKAGE DESCRIPTIO

MSE Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1663)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.794 ± 0.102

(.110 ± .004)

0.889 ± 0.127

(.035 ± .005)

2.06 ± 0.102

(.081 ± .004)

1

1.83 ± 0.102

(.072 ± .004)

5.23

(.206)

MIN

2.083 ± 0.102 3.20 – 3.45

(.082 ± .004) (.126 – .136)

10

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ± .0015)

TYP

DETAIL “A”

0.254

RECOMMENDED SOLDER PAD LAYOUT

(.010)

0° – 6° TYP

GAUGE PLANE

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.497 ± 0.076

(.0196 ± .003)

REF

0.53 ± 0.152

(.021 ± .006)

0.86

(.034)

REF

1.10

(.043)

MAX

10 9

8

7 6

DETAIL “A”

0.18

(.007)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

TYP

0.127 ± 0.076

(.005 ± .003)

0.50

(.0197)

BSC

MSOP (MSE) 0603

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

1

2

3

4 5

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

1407f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

23

LTC1407/LTC1407A

RELATED PARTS

PART NUMBER

ADCs

DESCRIPTION

COMMENTS

LTC1608

16-Bit, 500ksps Parallel ADC

16-Bit, 250ksps Serial ADC

12-/14-Bit, 2.8Msps Serial ADC

14-Bit, 2.5Msps Parallel ADC

12-Bit, 10Msps Parallel ADC

12-Bit, 5Msps Parallel ADC

12-Bit, 3Msps Parallel ADC

12-Bit, 2.2Msps Serial ADC

16-Bit, 250ksps 1-/2-Channel Serial ADCs

±5V Supply, ±2.5V Span, 90dB SINAD

5V Configurable Bipolar/Unipolar Inputs

3V, 15mW, MSOP Package

LTC1609

LTC1403/LTC1403A

LTC1411

5V, Selectable Spans, 80dB SINAD

5V, Selectable Spans, 72dB SINAD

5V, Selectable Spans, 115mW

LTC1420

LTC1405

LTC1412

±5V Supply, ±2.5V Span, 72dB SINAD

5V or ±5V Supply, 4.096V or ±2.5V Span

5V or 3V (L-Version), Micropower, MSOP Package

LTC1402

LTC1864/LTC1865

LTC1864L/LTC1865L

DACs

LTC1666/LTC1667

LTC1668

12-/14-/16-Bit, 50Msps DAC

87dB SFDR, 20ns Settling Time

LTC1592

16-Bit, Serial SoftSpan^TM

I

DAC

±1LSB INL/DNL, Software Selectable Spans

OUT

References

LT1790-2.5

LT1461-2.5

LT1460-2.5

Micropower Series Reference in SOT-23

Precision Voltage Reference

0.05% Initial Accuracy, 10ppm Drift

0.04% Initial Accuracy, 3ppm Drift

0.10% Initial Accuracy, 10ppm Drift

Micropower Series Voltage Reference

SoftSpan is a trademark of Linear Technology Corporation.

1407f

LT/TP 1103 1K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

LINEAR TECHNOLOGY CORPORATION 2003

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1407AIMSE
厂家：	Linear
描述：	Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling Simultaneous Sampling 串行12位/ 14位， 3MSPS同步采样同步采样
文件：	总24页 (文件大小：444K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1407AIMSE [Linear]

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LTC1407CMSE-1

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LTC1407IMSE#PBF