LTC1448CS8#TRPBF [Linear]
LTC1448 - Dual 12-Bit Rail-to-Rail Micropower DAC; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LTC1448CS8#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1448 - Dual 12-Bit Rail-to-Rail Micropower DAC; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1448
Dual 12-Bit Rail-to-Rail
Micropower DAC
U
DESCRIPTION
FEATURES
■
SO-8 Package
The LTC®1448 is a dual rail-to-rail voltage output, 12-bit
digital-to-analog converter (DAC). It includes rail-to-rail
output buffer amplifiers and an easy-to-use 3-wire serial
interface.Itisavailablein8-pinSOandPDIPpackagesand
provides the smallest footprint of any dual 12-bit DAC.
■
12-Bit Resolution
■
Buffered True Rail-to-Rail Voltage Output
■
External Reference Input Can Be Tied to VCC
■
Output Swings from 0V to VREF
3V and 5V Supply Operation
■
The LTC1448 has an external reference input pin (REF)
and its outputs swing from 0V to REF. The REF input can
betiedtoVCC providingrail-to-railoperationfromsupplies
of2.7Vto5.5V.(Fordeviceswithinternalreferenceseethe
LTC1446 data sheet.) The LTC1448 dissipates 2.5mW
from a 5V supply.
■
Schmitt Trigger on Clock Input Allows Direct
Optocoupler Interface
■
Power-On Reset Clears DACs to 0V
■
3-Wire Serial Interface
■
Maximum DNL Error: 0.5LSB
■
Low Cost
The low power supply current and the small SO-8 package
maketheLTC1448idealforbattery-poweredapplications.
U
APPLICATIONS
■
Digital Calibration
■
Industrial Process Control
■
Automatic Test Equipment
Cellular Telephones
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
U
TYPICAL APPLICATION
Functional Block Diagram: 12-Bit Rail-to-Rail Dual DAC
Differential Nonlinearity
vs Input Code
2.7V TO 5.5V
0.5
0.4
0.3
0.2
7
4
REF
V
CC
2
D
IN
+
–
0.1
V
OUT B
8
0
12-BIT
DAC B
–0.1
µP
1
3
CLK
–0.2
24-BIT
SHIFT
REG
RAIL-TO-RAIL
–0.3
VOLTAGE
CS/LD
OUTPUTS
–0.4
–0.5
AND
DAC
LATCH
+
–
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
V
OUT A
5
12-BIT
DAC A
1448 TA02
POWER-ON
RESET
GND
6
1448 TA01
1
LTC1448
W W U W
W
U
/O
ABSOLUTE MAXIMUM RATINGS
PACKAGE RDER I FOR ATIO
VCC to GND .............................................. –0.5V to 7.5V
Logic Inputs to GND ................................ –0.5V to 7.5V
VOUT A, VOUT B, REF to GND ........... –0.5V to VCC + 0.5V
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC1448C ............................................ 0°C to 70°C
LTC1448I......................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
TOP VIEW
NUMBER
CLK
1
2
3
4
V
V
8
7
6
5
OUT B
LTC1448CN8
LTC1448IN8
LTC1448CS8
LTC1448IS8
D
IN
CC
CS/LD
REF
GND
V
OUT A
N8 PACKAGE
S8 PACKAGE
8-LEAD PDIP 8-LEAD PLASTIC SO
S8 PART MARKING
TJMAX = 125°C, θJA = 100°C/W (N8)
TJMAX = 125°C, θJA = 150°C/W (S8)
1448
1448I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 2.7V to 5.5V, VOUT A and VOUT B unloaded, REF ≤ VCC, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER
DAC
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
●
●
●
12
12
Bits
Monotonicity
Bits
LSB
DNL
INL
Differential Nonlinearity
V
≤ V – 0.1V (Note 1)
±0.2
±0.5
REF
CC
Integral Nonlinearity
V
V
≤ V – 0.1V (Note 1), T = 25°C
±5.0
±5.5
LSB
LSB
REF
REF
CC
A
≤ V – 0.1V (Note 1)
●
●
CC
V
V
V
V
Offset Error
Measured at Code 20, T = 25°C
Measured at Code 20
±10
±15
mV
mV
OS
OS
FS
A
TC
Offset Error Temperature
Coefficient
±15
µV/°C
Full-Scale Voltage
V
V
= 4.096V, T = 25°C
4.070
4.060
4.095
4.095
4.120
4.130
V
V
REF
REF
A
= 4.096V
●
TC
FS
Full-Scale Voltage
10
ppm/°C
Temperature Coefficient
Power Supply
V
Positive Supply Voltage
Supply Current
For Specified Performance
(Note 4)
●
●
2.7
5.5
V
CC
I
450
700
µA
CC
Op Amp DC Performance
Short-Circuit Current Low
V
V
Shorted to GND
●
●
●
●
55
65
30
0.2
120
120
120
1.5
mA
mA
OUT
OUT
Short-Circuit Current High
Output Impedance to GND
Output Line Regulation
Shorted to V
CC
Input Code = 0
Input Code = 4095. V = 4.5V to 5.5V, V
Ω
= 4.096V
REF
LSB/V
CC
2
LTC1448
ELECTRICAL CHARACTERISTICS
VCC = 2.7V to 5.5V, VOUT A and VOUT B unloaded, REF ≤ VCC, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER
AC Performance
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Output Slew Rate
●
0.5
1.0
14
V/µs
µs
Voltage Output Settling Time (Notes 2, 3) to ±0.5LSB
Digital Feedthrough
0.3
nV•s
Reference Input
R
REF Input Resistance
REF Input Range
●
●
7.5
0
12.5
18
kΩ
IN
REF
(Notes 5, 6)
V
V
CC
Digital I/O
V
Digital Input High Voltage
Digital Input Low Voltage
V
V
= 5V
= 3V
●
●
2.4
2.0
V
V
IH
CC
CC
V
V
V
= 5V
= 3V
●
●
0.8
0.6
V
V
IL
CC
CC
I
Digital Input Leakage
V
= GND to V
CC
●
●
±10
10
µA
pF
LEAK
IN
C
Digital Input Capacitance
(Note 6)
IN
Switching (V = 4.5V to 5.5V)
CC
t
t
t
t
t
t
t
t
D
D
Valid to CLK Setup
Valid to CLK Hold
●
●
●
●
●
●
●
●
40
0
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
IN
IN
CLK High Time
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
40
40
50
40
20
20
CLK Low Time
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
CLK Low to CS/LD Low
Switching (V = 2.7V to 5.5V)
CC
t
t
t
t
t
t
t
t
D
D
Valid to CLK Setup
Valid to CLK Hold
●
●
●
●
●
●
●
●
60
0
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
IN
IN
CLK High Time
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
60
60
80
60
30
30
CLK Low Time
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
CLK Low to CS/LD Low
Note 4: Digital inputs at 0V or V
.
The
● denotes specifications which apply over the full operating
CC
temperature range.
Note 5: V
can only swing from (GND +
V
) to (V
–
V ) when
OS
OUT
OS
CC
output is unloaded.
Note 1: Nonlinearity is defined from code 20 to code 4095 (full scale).
See Applications Information.
Note 6. Guaranteed by design, not subject to test.
Note 2: Load is 5k in parallel with 100pF.
Note 3: DAC switched between all 1s and the code corresponding to V
OS
for the part.
3
LTC1448
TYPICAL PERFORMANCE CHARACTERISTICS
U W
Minimum Supply Headroom for
Full Output Swing vs Load Current
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
0.5
0.4
5
4
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
∆V
< 1LSB
OUT
CODE: ALL 1’s
= 4.095V
V
0.3
OUT
3
0.2
2
0.1
1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
–2
–3
–4
–5
0
5
10
15
0
512 1024 1536 2048 2560 3072 3584 4095
CODE
512 1024 1536
2048
CODE
2560 4095
3072 3584
0
LOAD CURRENT (mA)
1448 G03
1448 TA02
1448 G01
Minimum Output Voltage vs
Output Sink Current
Supply Current vs
Logic Input Voltage
800
700
600
500
400
300
200
100
0
CODE: ALL 0’s
2.0
1.6
1.2
0.8
0.4
0
125°C
25°C
–55°C
0
5
10
15
0
1
2
3
4
5
OUTPUT SINK CURRENT (mA)
LOGIC INPUT VOLTAGE (V)
1448 G04
1448 G06
U
U
U
PIN FUNCTIONS
CLK (Pin 1): Serial Interface Clock. Internal Schmitt trig-
ger on this input allows direct optocoupler interface.
updating the DAC output and the CLK is disabled
internally.
DIN (Pin 2): Serial Interface Data. Data on the DIN pin is
latchedintotheshiftregisterontherisingedgeoftheserial
clock.
REF (Pin 4): Reference Input for Both DACs. This pin can
be tied to VCC. The output will swing from 0V to REF. The
typical input resistance is 12.5k.
CS/LD (Pin 3): Serial Interface Enable and Load Control.
When CS/LD is low the CLK signal is enabled, so the data
can be clocked in. When CS/LD is pulled high, data is
loaded from the shift register into the DAC register,
VOUT A, VOUT B (Pins 5, 8): Buffered DAC Outputs.
GND (Pin 6): Ground.
VCC (Pin 7): Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V.
Requires a bypass capacitor to ground.
4
LTC1448
W
BLOCK DIAGRA
12-BIT
DAC B
LD
+
–
DAC B
REGISTER
V
V
8
7
1
2
CLK
OUT B
24-BIT
SHIFT
REGISTER
D
IN
CC
LD
GND
V
6
5
CS/LD
REF
3
4
DAC A
REGISTER
12-BIT
DAC A
+
–
OUT A
POWER-ON
RESET
1448 BD
W U
W
TI I G DIAGRA S
OPERATING SEQUENCE
DAC A INPUT
DAC B INPUT
MSB
LSB MSB
D1 D0 D11 D10 D9 D8
LSB
D1 D0
D
D11 D10 D9 D8
D7 D6 D5
D4
D3
D2
D7 D6 D5
D4
D3
21
D2
IN
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
23
24
CS/LD
(ENABLE CLOCK)
(UPDATE DAC OUTPUT)
1448 TD01
t
1
t
4
t
3
t
2
t
6
t
7
CLK
t
8
B0-B
PREVIOUS WORD
B11-A
MSB
B0-A
LSB
B11-B
MSB
B0-B
LSB
D
IN
t
5
CS/LD
1448 TD02
5
LTC1448
U U
DEFI ITIO S
Differential Nonlinearity (DNL): The differerence
between the measured change and the ideal 1LSB change
for any two adjacent codes. The DNL error between any
two codes is calculated as follows:
than zero. The INL error at a given input code is calculated
as follows:
INL = [VOUT – VOS – (VFS – VOS)(code/4095)]/LSB
where VOUT is the output voltage of the DAC measured at
the given input code.
DNL = (∆VOUT – LSB)/LSB
where ∆VOUT is the measured voltage difference between
two adjacent codes.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
Digital Feedthrough: The glitch that appears at the analog
outputcausedbyACcouplingfromthedigitalinputswhen
they change state. The area of the glitch is specified in
(nV)(sec).
LSB = VREF/4096
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve(EndpointINL).Becausetheoutputcannotgobelow
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
U
OPERATIO
Serial Interface
while pulling to within 300mV of the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalentoutputresistanceof30Ωwhendrivingaloadto
the rails. The output can drive 1000pF without going into
oscillation.
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one 24-
bit word where the first 12 bits are for DAC A and the
second12areforDACB.Foreach12-bitsegmenttheMSB
isloadedfirst.Datafromtheshiftregisterisloadedintothe
DAC register when CS/LD is pulled high. The clock is
disabledinternallywhenCS/LDishigh. Note:CLKmustbe
low before CS/LD is pulled low to avoid an extra internal
clock pulse.
The output swings from 0V to the voltage at the REF pin,
i.e., there is a gain of 1 from the REF to VOUT. Please note
if REF is tied to VCC the output can only swing to
(VCC – VOS). See Applications Information.
Voltage Output
The LTC1448’s rail-to-rail buffered outputs can source or
sink 5mA over the entire operating temperature range
6
LTC1448
U
W U U
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations
(FSE) is positive, the output for the highest codes limits at
VCC as shown in Figure 1c. No full-scale limiting can occur
if VREF is less than VCC – FSE.
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
POSITIVE
FSE
V
= V
CC
REF
OUTPUT
VOLTAGE
INPUT CODE
(c)
V
= V
CC
REF
OUTPUT
VOLTAGE
0
2048
4095
INPUT CODE
(a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1448 F01
Figure 1. Effects of Rail-to-Rail Operation on a DAC Transfer Curve: (a) Overall Transfer Function, (b) Effect of Negative
Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
7
LTC1448
U
TYPICAL APPLICATIONS
the REF+ pin on the LTC1296. The LTC1296 has a Shut-
down pin that goes low in shutdown mode. This will turn
off the PNP transistor supplying power to the LTC1448.
The resistor and capacitor on the LTC1448 outputs act as
a lowpass filter for noise.
This circuit shows how to use one LTC1448 to make an
autoranging ADC. The microprocessor sets the reference
span and the Common pin for the analog input by loading
the appropriate digital code into the LTC1448. VOUT A
controls the Common pin for the analog inputs to the
LTC1296andVOUTB controlsthereferencespanbysetting
An Autoranging 8-Channel ADC with Shutdown
22µF
5V
V
CC
CH0
CS
D
OUT
8 ANALOG
INPUT CHANNELS
CLK
LTC1296
µP
D
CH7
IN
COM
+
REF
–
SSO REF
74HC04
50k
50k
5V
0.1µF
100Ω
V
OUT B
CLK
0.1µF
V
CC
D
IN
LTC1448
GND
CS/LD
REF
100Ω
1448 TA04
V
OUT A
0.1µF
8
LTC1448
U
TYPICAL APPLICATIONS
Digitally Programmable Current Source
5V
V
+ 6V TO 100V
S
FOR R ≤ 50Ω
L
0.1µF
D
• 5
IN
R
L
I
=
≈ 0mA TO 10mA
V
CC
REF
OUT
CLK
4096 • R
A
µP
V
+
–
LTC1448
GND
D
OUT A
IN
Q1
2N3440
LT1077
CS/LD
R
A
510Ω
5%
V
OUT
B PIN NOT SHOWN FOR CLARITY
1448 TA05
9
LTC1448
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
0.125
0.020
(0.508)
MIN
(3.175)
MIN
+0.035
0.325
–0.015
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
(
)
N8 1197
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
10
LTC1448
U
Dimensions in inches (millimeters) unless otherwise noted.
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.053 – 0.069
3
4
2
0.010 – 0.020
(0.254 – 0.508)
× 45°
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.050
(1.270)
TYP
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC1448
TYPICAL APPLICATION
U
12-Bit, 3V to 5V Supply, Dual Voltage Output DAC
2.7V TO 5.5V
0.1µF
V
REF
D
CC
IN
CLK
CS/LD
OUTPUT A
µP
V
V
OUT A
0V TO REF
LTC1448
GND
OUTPUT B
0V TO REF
OUT B
1448 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1257
Single 12-Bit V
Reference Can Be Overdriven Up to 12V, i.e., FS
DAC, Full Scale: 2.048V, V : 4.75V to 15.75V,
5V to 15V Single Supply, Complete V
SO-8 Package
DAC in
OUT
OUT
CC
= 12V
MAX
LTC1446/LTC1446L Dual 12-Bit V
DACs in SO-8 Package with Internal Reference
LTC1446: V = 4.5V to 5.5V, V
= 0V to 4.095V
= 0V to 2.5V
OUT
OUT
CC
OUT
LTC1446L: V = 2.7V to 5.5V, V
CC
LTC1450/LTC1450L Single 12-Bit V
DACs with Parallel Interface
LTC1450: V = 4.5V to 5.5V, V
= 0V to 4.095V
= 0V to 2.5V
OUT
OUT
CC
OUT
LTC1450L: V = 2.7V to 5.5V, V
CC
LTC1451
LTC1452
LTC1453
Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, V : 4.5V to 5.5V,
Internal 2.048V Reference Brought Out to Pin
5V Low Power, Complete V
DAC in SO-8 Package
CC
OUT
Single Rail-to-Rail 12-Bit V
Multiplying DAC, V : 2.7V to 5.5V
Low Power, Multiplying V
DAC with Rail-to-Rail
OUT
CC
OUT
Buffer Amplifier in SO-8 Package
Single Rail-to-Rail 12-Bit V
DAC, Full Scale: 2.5V, V : 2.7V to 5.5V
3V, Low Power, Complete V DAC in SO-8 Package
OUT
CC
OUT
LTC1454/LTC1454L Dual 12-Bit V
DACs in SO-16 Package with Added Functionality
LTC1454: V = 4.5V to 5.5V, V
= 0V to 4.095V
= 0V to 2.5V
OUT
OUT
CC
OUT
LTC1454L: V = 2.7V to 5.5V, V
CC
LTC1456
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,
Full Scale: 4.095V, V : 4.5V to 5.5V
Low Power, Complete V
Package with Clear Pin
DAC in SO-8
OUT
CC
LTC1458/LTC1458L Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: V = 4.5V to 5.5V, V
= 0V to 4.095V
= 0V to 2.5V
OUT
CC
OUT
LTC1458L: V = 2.7V to 5.5V, V
CC
LTC1659
Single Rail-to-Rail 12-Bit V
DAC in MSOP-8 Package,
Low Power Multiplying V
Package. Output Swings from GND to REF.
REF Input Can Be Tied to V
DAC in MSOP-8
OUT
OUT
V
CC
: 2.7V to 5.5V
CC
1448f LT/TP 0398 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1997
Linear Technology Corporation
●
1630McCarthyBlvd.,Milpitas, CA95035-7417 (408)432-1900
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