LTC1705EGN_技术文档

LTC1705

Dual 550kHz Synchronous

Switching Regulator Controller with

5-Bit VID and 150mA LDO

U

FEATURES

DESCRIPTIO

The LTC^®1705 is a complete power supply controller for

Intel Mobile Pentium processors. It includes two switch-

ing regulator controllers, each designed to drive a pair of

N-channel MOSFETs in a voltage mode feedback, syn-

chronous buck configuration, to provide the core and I/O

supplies. The core controller includes a 5-bit DAC that

conforms to the Intel Mobile VID specification. The IC also

includes alowdropoutlinearregulator(LDO)thatdelivers

up to 150mA of output current to provide the CLK supply.

The LTC1705 uses a constant-frequency 550kHz PWM

architecture, minimizing external component size and

cost, as well as optimizing load transient performance. It

providesbetterthan1.25%DCaccuracyatitscoreoutput,

and 2% at I/0 and CLK outputs. The high performance

feedback loops allow the circuit to keep total output

regulation within ±5% under all transient conditions. An

open-drain PGOOD flag indicates that all three outputs are

within ±10% of their regulated values. A shutdown circuit

disables all three outputs if the RUN/SS pin is pulled to

ground. In this mode, the LTC1705 supply current drops

to below 100µA.

■

Three Regulated Outputs: Core, I/O and CLK in One

Package

Integrated Intel Mobile 5-Bit VID DAC

No External Current Sense Resistors

All N-Channel External MOSFET Architecture

550kHz Switching Frequency Minimizes External

Component Size and Cost

Integrated 150mA LDO Linear Regulator

Excellent DC Accuracy: 1.25% for Core, 2% for I/O

and CLK Supplies

PGOOD Flag Monitors All Three Outputs

High Efficiency Over Wide Load Current Range

Low Shutdown Current: < 100µA

■

Switchers Run Out-of-Phase to Minimize C_IN

Small 28-Pin Narrow SSOP Package

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APPLICATIO S

■

Complete Power Supply Controller for Intel

Mobile Pentium^®Processors

■

Intel Mobile Pentium Core, I/O, Clock Supplies

Multiple Logic Supply Generator

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

Pentium is a registered trademark of Intel Corporation.

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TYPICAL APPLICATIO

Intel Mobile Pentium VRM Supply

V

IN

5V

C

IN

+

R

10µF

10Ω

PGOOD

5k

1µF

330µF

10V

×3

D

CPIO

D

CPC

MBR

0520LT1

2

22

19

0520LT1

QTCA

QTCB

PV

TGC

BOOSTC

PGOOD

V

CC

TGIO

5

3

26

27

QTIO

BOOSTIO

L

C

IO

3µH

C

CPIO

CPC

1µF

0.68µH

6

4

25

28

1µF

SWC

SWIO

QBCB

QBCA

C

OUTIO

V

OUTC

180µF

4V

1µF

OUTC

V

1.5V

3A

+

OUTIO

1µF

100µF

0.9V TO 2V

15A

QBIO

BGC

BGIO

10V

×2

R

, 16k

IMAXI0

R

, 27k

IMAXC

8

LTC1705

1

×6

I

MAXIO

MAXC

13

R22, 11k

SENSEC

FBC

21

RB2

10k

1%

R12

8.87k

1%

COMPIO

FBIO

11

C22

100pF

C12

C11

C21

R31

1.8k

20

24

2200pF

C31

1800pF

330pF

10

9

COMPC

RUN/SS

V

INCLK

3.3V

R21, 11k

10k

V

INCLK

+

C

VINCLK

SS

7

0.1µF

10µF

SHUTDOWN

PGND

GND

C

: KEMET T510X337K010AS

10V

IN

12

V

OUTCLK

2.5V

150mA

23

: PANASONIC EEFUE0G181R

OUTC

OUTIO

V

OUTCLK

14–18

: AVX TPS0107M010R0065

C

+

VOUTCLK

L : SUMIDA CEP125-4712-T007

C

1µF

5-BIT VID

VID4:0

10µF

L

: SUMIDA CDRH6D28-3R0

IO

10V

QTCA, QTCB, QBCA, QBCB: FAIRCHILD FDS6670A

QTIO, QBIO: 1/2 FAIRCHILD NDS8926

1705 TA01

1

LTC1705

W W

U W

U

W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

ORDER PART

Supply Voltage

1

2

BGIO

28

27

26

25

24

23

22

21

20

19

18

17

16

15

I

NUMBER

MAXIO

V_CC, PV_CC, V_INCLK.................................................. 6V

BOOSTC, BOOSTIO ............................................. 12V

BOOSTC – SWC, BOOSTIO – SWIO....................... 6V

Input Voltage

BOOSTIO

TGIO

PV

CC

LTC1705EGN

3

BOOSTC

BGC

4

SWIO

5

V

TGC

INCLK

SWC, SWIO ................................................–1V to 6V

SENSEC, FBC, FBIO, VIDn ....... –0.3V to (V_CC+ 0.3V)

PGOOD, RUN/SS,

6

V

SWC

OUTCLK

7

PGOOD

COMPIO

FBIO

PGND

8

I

MAXC

9

RUN/SS

COMPC

FBC

I_MAXC, I_MAXIO.................................. –0.3V to (V_CC+ 0.3V)

Peak Output Current <10µs

TGC, BGC .............................................................. 5A

TGIO, BGIO....................................................... 1.25A

Operating Temperature Range (Note 2) .. –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

10

11

12

13

14

V

CC

VID4

VID3

VID2

VID1

GND

SENSEC

VID0

GN PACKAGE

28-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 80°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T_A= 25°C.

V_CC= PV_CC= BOOST = 5V, V_INCLK= 3.3V unless otherwise specified. (Note 3)

SYMBOL PARAMETER

Supply Voltage

CONDITIONS

MIN

3.15

3

TYP

5

MAX

5.5

UNITS

V

CC

V

CC

●

V

PV

CC

BV

CC

PV Supply Voltage

(Note 4)

5

5.5

CC

BOOST Pin Voltage

V

– V (Note 4)

5

5.5

BOOST

SW

V

Supply Voltage

INCLK

3.3

5.5

INCLK

VCC

I

V

CC

Supply Current

Test Circuit 1

RUN/SS = 0V

●

4.5

40

8

100

mA

µA

PV Supply Current

V

= V = 0V, No Load at Drivers (Note 5)

FBIO

●

2

1

6

50

mA

µA

PVCC

CC

SENSEC

RUN/SS = 0V (Note 6)

I

+ I

BOOSTIO

V

= V = 0V, No Load at Drivers (Note 5)

●

2

1

6

50

mA

µA

BOOST

VINCLK

BOOSTC

SENSEC

FBIO

RUN/SS = 0V (Note 6)

V

INCLK

Supply Current

I

= 0mA

●

1

4

1.5

30

mA

µA

VOUTCLK

RUN/SS = 0V

V

RUN/SS Shutdown Threshold

RUN/SS Source Current

V

↑ (Rising Edge)

●

0.2

0.5

–3

V

SHDN

RUN/SS

I

RUN/SS = 0V

µA

SS

Core, I/O Supply Control Loops

V

Output Voltage Accuracy

Core Feedback Voltage

Programmed from 0.9V to 2V

(Note 10)

–1.25

0.784

–0.2

1.25

%

V

SENSEC

FBC

0.800

±0.01

–0.1

I/O Feedback Voltage

●

0.816

V

FBIO

dV

Feedback Voltage Line Regulation

Output Voltage Load Regulation

I/O Feedback Input Current

V

CC

= 3.3V to 5.5V

±0.1

%/V

%

FB

(Note 7)

OUT

I

±1

µA

FBIO

2

LTC1705

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T_A= 25°C.

V_CC= PV_CC= BOOST = 5V, V_INCLK= 3.3V unless otherwise specified. (Note 3)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

85

MAX

UNITS

dB

A

FB

Feedback Amplifier DC Gain

●

74

GBW

Feedback Amplifier Gain Bandwidth Product

Feedback Amplifier Output Sink/Source Current

f = 100kHz (Note 7)

20

MHz

mA

I

±3

±10

COMP

V

Negative Power Good Threshold

Positive Power Good Threshold

Relative to Nominal Output Voltage

●

–15

6

–10

10

–6

15

%

PGOOD

A

Current Limit Amplifier DC Gain

●

40

60

dB

ILIM

I

Source Current

V

IMAXC

= V = 0V

IMAXIO

–12

–10

–8

µA

IMAX

MAX

Core, I/O Supply Switching Characteristics

f

Oscillator Frequency

Test Circuit 1

(Note 7)

●

460

550

180

90

650

kHz

DEG

%

OSC

Φ

Core and I/O Oscillator Phase Difference

Maximum Duty Cycle

OSC

DC

●

87

10

93

MAX

t

Driver Nonoverlap

Test Circuit 1, 50% to 50%

Test Circuit 1, 10% to 90%

25

120

100

ns

NOV

t , t

Driver Rise/Fall Time

15

ns

r

f

Clock Supply Output

V

CLK Output Voltage

I

= 0mA

VOUTCLK

●

2.45

–0.1

2.50

±0.02

–0.05

–240

0.3

2.55

V

%/V

%

OUTCLK

dV

Output Voltage Line Regulation

Output Voltage Load Regulation

CLK Output Short-Circuit Current

CLK Output Dropout Voltage

V

= 3.0V to 5.5V

±0.1

OUTCLK

INCLK

I

= 0mA to 150mA

= 0V

VOUTCLK

ILM

–150

0.5

mA

V

CLK

V

= 150mA, d

= –1% (Note 8)

DROPOUT

PGOOD

VOUTCLK

Negative V

Power Good Threshold

Relative to V

●

–15

6

–10

10

–6

15

%

OUTCLK

Positive V

VID Inputs

R1

Resistance Across SENSEC and FBC

VID Input Pull-Up Resistance

VID Input Threshold

10

30

kΩ

V

R

(Note 9)

VID

V

●

0.4

10

1.6

PGOOD

I

V

Sink Current

Power Good

Power Bad

●

10

µA

mA

PGOOD

V

OLPG

PGOOD Output Low Voltage

I

= 1mA

PGOOD

●

0.03

0.1

V

T

V

Falling Edge Delay

Rising Edge Delay

●

2

10

4

20

8

40

µs

PGOOD

PBAD

Pulse

VID Code Change

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: The LTC1705 is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

gates. This current varies with supply voltage and the choice of external

MOSFETs.

Note 6: Supply current in shutdown is dominated by external MOSFET

leakage and may be significantly higher than the quiescent current drawn

by the LTC1705, especially at elevated temperature.

Note 7: Guaranteed by design, not subject to test.

Note 3: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to ground unless otherwise

specified.

Note 8: Dropout voltage is the minimum input-to-output voltage

differential required to maintain regulation at the specified output current.

In dropout, the output voltage will be equal to V

– V

.

INCLK

DROPOUT

Note 4: PV and BV (V

– V ) must be greater than V of

Note 9: Each internal pull-up resistor attached to the VID inputs has a

CC

CC BOOST

SW

GS(ON)

the external MOSFETs to ensure proper operation.

Note 5: Supply current in normal operation is dominated by the current

series diode connected to V to allow input voltages higher than the V

supply without damage or clamping. (See Block Diagram.)

CC

needed to charge and discharge the capacitance of the external MOSFET

Note 10: The core feedback voltage accuracy is guaranteed by the V

output voltage accuracy test.

SENSE

3

LTC1705

U W

TYPICAL PERFOR A CE CHARACTERISTICS

V_SENSECvs Temperature

V_SENSECLine Regulation

1.315

1.310

1.305

1.300

1.295

1.290

1.285

1.30

0.10

0.08

0.06

0.04

0.02

0

V

= 5V

OUT

T

= 25°C

A

CC

1.04

0.78

= 1.3V

0.52

0.26

0

–0.26

–0.52

–0.78

–1.04

–1.30

–0.02

–0.04

–0.06

–0.08

–0.10

–50 –25

0

25

50

75 100 125

3

3.5

4

4.5

(V)

5

5.5

6

TEMPERATURE (°C)

V

CC

1705 G01

1705 G02

V_SENSECLoad Regulation

Core Supply Efficiency

100

90

80

70

60

50

0.8

0

0.05

0

T

= 25°C

OUT

A

V

= 2V

OUT

V

= 1.6V

= 0.9V

–0.8

–1.6

–2.4

–3.2

–0.05

–0.10

–0.15

–0.20

V

= 5V, T = 25°C, I/O DISABLED

A

IN

QTC = QBC = 2× FDS6670A

0

3

6

I

9

12

15

0

3

6

I

9

(A)

12

15

(A)

LOAD

1705 G04

1705 G03

V_FBIOvs Temperature

V_FBIOLine Regulation

0.810

0.806

0.802

0.798

0.794

0.790

0.80

0.64

0.10

0.08

0.06

0.04

0.02

0

V

= 5V

T

= 25°C

A

CC

0.48

0.32

0.16

0

–0.16

–0.32

–0.48

–0.64

–0.80

–0.02

–0.04

–0.06

–0.08

–0.10

–50 –25

0

25

50

75 100 125

3

3.5

4

4.5

(V)

5

5.5

6

TEMPERATURE (°C)

V

CC

1705 G05

1705 G06

4

LTC1705

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Current Limit Threshold vs

Temperature

V_OUTC0A To 10A Load Step

I/O Supply Efficiency

100

90

80

70

60

50

24

22

20

18

16

14

12

10

V

= 5V, V

= 1.5V, T = 25°C,

V

= 5V, V

IMAXC

= 1.6V, ∆V

= –1%,

IN

OUT

A

OUT

IN

0A TO 10A

LOAD

CORE DISABLED, QTIO = QBIO = NDS8926

R

= 24.9k, QTC = QBC = 2× FDS6670A

5A/DIV

V_OUT= 1.6V

AC 50mV/

DIV

5ms/DIV

1705 G08

0

0.5

1

I

1.5

(A)

2

2.5

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

LOAD

1705 G07

1705 G09

V_OUTCvs Load Current

V_OUTCLKvs Temperature

V_OUTCLKLine Regulation

2.0

2.55

2.54

2.53

2.52

2.51

2.50

2.49

2.48

2.47

2.46

2.45

2.5

2.0

0.10

V

= 3.3V

T

= 25°C

INCLK

A

0.08

0.06

0.04

0.02

0

1.5

1.0

0.5

0

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.02

–0.04

–0.06

–0.08

–0.10

T

= 25°C, V = 5V,

IN

OUT

A

V

= 1.6V,

QBC = 2× FDS6670A,

R

C

= 24.9k,

= 0.01µF

IMAXC

RUNSS

0

4

8

12

16

20

–50 –25

0

25

50

75 100 125

3

3.5

4

4.5

5

5.5

6

LOAD CURRENT (A)

TEMPERATURE (°C)

V

(V)

INCLK

1705 G10

1705 G11

1705 G12

V_OUTCLKDropout Voltage vs

Temperature

V_OUTCLKShort-Circuit Current vs

Temperature

V_OUTCLKLoad Regulation

500

450

400

350

300

250

200

150

100

–150

–190

–230

–270

–310

–350

0.5

0

0.02

I

= –150mA

V

= 3.3V

T

= 25°C

OUTCLK

INCLK

A

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.02

–0.04

–0.06

–0.08

–0.10

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–150 –125 –100 –75

–50

–25

0

TEMPERATURE (°C)

I

(mA)

OUTCLK

1705 G14

1705 G15

1705 G13

5

LTC1705

U W

TYPICAL PERFOR A CE CHARACTERISTICS

V_OUTCLKShort-Circuit Current vs

V_INCLK

V_OUTCLK10mA To 150mA Load

Step

f_OSCvs Temperature

–150

–190

–230

–270

–310

–350

650

630

610

590

570

550

530

510

490

470

450

T

= 25°C

V

= 5V

CC

A

V_OUTCLK

AC 5mV/DIV

10mA TO

150mA LOAD

100mA/DIV

2ms/DIV

1705 G18.tif

3

3.5

4

4.5

5

5.5

6

–50 –25

0

25

50

75 100 125

V

INCLK

(V)

TEMPERATURE (°C)

1705 G16

1705 G19

f_OSCvs V_CC

I_IMAXvs Temperature

I_IMAXvs V_CC

–8.0

650

610

570

530

490

450

–8.0

–8.5

T

A

= 25°C

T

= 25°C

V

CC

= 5V

A

–8.5

–9.0

–9.5

–10.0

–10.5

–11.0

–11.5

–12.0

–10.0

–10.5

–11.0

–11.5

–12.0

3

3.5

4

4.5

(V)

5

5.5

6

3

3.5

4

4.5

(V)

5

5.5

6

–50 –25

0

25

50

75 100 125

V

TEMPERATURE (°C)

CC

1705 G22

1705 G20

1705 G21

VID Input Threshold vs

Temperature

VID Input Threshold vs V_CC

Supply Current vs Temperature

1.6

1.4

1.2

1.0

0.8

0.6

0.4

6.0

4.5

3.0

1.5

0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

V

= 5V

V

= PV = BV = 5V, V

= 3.3V,

INCLK

T

= 25°C

CC

A

TGC, BGC, TGIO, BGIO FLOAT

I

VCC

I

, I

PVCC BOOST

VINCLK

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

3

3.5

4

4.5

(V)

5

5.5

6

TEMPERATURE (°C)

V

CC

1705 G23

1705 G25

1705 G24

6

LTC1705

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Drivers Rise and Fall Time vs

Load

I_PVCC, I_BOOSTvs Driver Load

V_SHDNvs Temperature

0.80

0.68

0.56

0.44

0.32

0.20

12

10

8

36

30

24

18

12

6

60

50

40

30

20

10

0

V

= 5V

CC

I/O DRIVERS

SUPPLY CURRENT

WITH CORE DISABLED

T

= 25°C, PVCC = BOOST = 5V

A

MEASURED AT RUN/SS

CORE

I/O DRIVERS

DRIVERS

CORE

6

SUPPLY

DRIVERS

CURRENT

WITH I/O

DISABLED

4

2

T

= 25°C, PVCC = BOOST = 5V

A

0

–50 –25

0

25

50

75 100 125

0

2000

4000

6000

8000

10000

0

2000

4000

6000

8000

10000

TEMPERATURE (°C)

TG, BG LOAD (pF)

1705 G28

1705 G26

1705 G27

U

PI FU CTIO S

I_MAXIO(Pin1):I/OSupplyCurrentLimitSet.TheI_MAXIOpin

sets the current limit comparator threshold for the I/O

controller. If the voltage drop across the bottom MOSFET,

QBIO, exceeds the magnitude of the voltage at I_MAXIO, the

I/O controller enters current limit. The I_MAXIOpin has an

internal 10µA current source pull-up, allowing the current

threshold to be set with a single external resistor to PGND.

Kelvinconnectthiscurrentsettingresistortothesourceof

QBIO. Refer to the Current Limit Programming section for

BGC (Pin 4): Core Supply Bottom Gate Drive. The BGC pin

drives the gate of the bottom N-channel synchronous

switch MOSFET, QBC. BGC is designed to typically drive

up to 10,000pF of gate capacitance. If RUN/SS goes low,

BGC goes low, turning off QBC.

TGC (Pin 5): Core Supply Top Gate Drive. The TGC pin

drives the gate of the top N-channel MOSFET, QTC. The

TGCdriverdrawspowerfromtheBOOSTCpinandreturns

it to the SWC pin, providing true floating drive to QTC. TGC

is designed to typically drive up to 10,000pF of gate

capacitance. If RUN/SS goes low, TGC goes low, turning

off QTC.

more information on choosing the value of R_IMAX

.

PV_CC(Pin 2): Driver Power Supply Input. PV_CCprovides

power to the BGC and BGIO output drivers. PV_CCmust be

connected to a voltage high enough to fully turn on the

external MOSFETs QBC and QBIO. PV_CCshould generally

be connected directly to V_IN, the main system 5V supply.

PV_CCrequires at least a 10µF bypass capacitor directly to

PGND.

SWC (Pin 6): Core Supply Switching Node. Connect SWC

totheswitchingnodeofthecoreconverter.TheTGCdriver

groundreturnstoSWC,providingfloatinggatedrivetothe

top N-channel MOSFET switch, QTC. The voltage at SWC

iscomparedtoI_MAXCbythecurrentlimitcomparatorwhile

the bottom MOSFET, QBC, is on.

BOOSTC (Pin 3): Core Controller Top Gate Driver Supply.

TheBOOSTCpinsuppliespowertothefloatingTGCdriver.

Bypass BOOSTC to SWC with a 1µF capacitor. An external

schottky diode from V_INto BOOSTC creates a complete

floating charge-pumped supply at BOOSTC. No other

external supplies are required.

PGND (Pin 7): Power Ground. The BGC and BGIO drivers

return to this pin. Connect PGND to a high-current ground

nodeincloseproximitytothesourcesofexternalMOSFETs

QBC and QBIO, and the V_INand V_OUTbypass capacitors.

I_MAXC(Pin 8): Core Supply Current Limit Set. See I_MAXIO

.

7

LTC1705

U

PI FU CTIO S

RUN/SS (Pin 9): SoftStart. Pulling RUN/SS to GND exter-

nallyshutsdowntheLTC1705andturnsoffalltheexternal

MOSFET switches. The quiescent supply current drops

below 100µA. A capacitor from RUN/SS to GND controls

the turn on time and rate of rise of the core and I/O output

voltages at power up. An internal 3µA current source pull-

up at RUN/SS sets the turn-on time at approximately

300ms/µF.

FBIO (Pin 20): I/O Controller Feedback Input. Connect

FBIOthrougharesistordividernetworktoV_OUTIOtosetthe

output voltage. Also, connect the loop compensation

network for the I/O controller to FBIO.

COMPIO(Pin21):I/OControllerLoopCompensation. See

COMPC.

PGOOD (Pin 22): Power Good. PGOOD is an open-drain

logic output. PGOOD pulls low if any of the three supply

outputs are out of regulation (see Electrical Characteris-

tics table for Core, I/O and CLK thresholds). An external

pull-up resistor is required at PGOOD to allow it to swing

positive.

COMPC (Pin 10): Core Controller Loop Compensation.

The COMPC pin is connected directly to the output of the

Core controller’s error amplifier and the input of the PWM

comparator. Use an RC network between the COMPC pin

and the FBC pin to compensate the feedback loop for

optimum transient response.

V_OUTCLK(Pin 23): Clock Supply Output. V_OUTCLKis the

output node of the internal linear clock supply regulator.

V_OUTCLKprovidesupto150mAatthe2.5Voutputtopower

the CPU CLK supply. Bypass V_OUTCLKwith at least a 2.2µF

capacitor to GND (refer to the V_CLKLinear Regulator

section). If RUN/SS goes low, the V_OUTCLKregulator shuts

down.

FBC(Pin11):CoreControllerFeedbackInput.Connectthe

loop compensation network for the core controller to FBC.

FBC internally connects to the VID resistor network to set

the Core output voltage.

GND (Pin 12): Signal Ground. All internal low power

circuitry returns to the GND pin. Connect to a low imped-

ance ground, separated from the PGND node. All feed-

back, compensation and softstart connections should

return to GND. GND and PGND should connect only at a

single point, near the PGND pin and the negative plate of

the V_INbypass capacitor.

V_INCLK(Pin 24): Clock Supply Input. V_INCLKis the input

terminal to the internal linear CLK supply regulator. Con-

nectV_INCLKtoa3.3Vsupplytomaximizeefficiency.V_INCLK

canbeconnectedtothe5Vsupply, buttheefficiencyofthe

V_OUTCLKregulator is reduced. Bypass V_INCLKwith a 10µF

capacitor to GND.

SENSEC (Pin 13): Core Controller Output Sense. Connect

SWIO (Pin 25): I/O Controller Switching Node. See SWC.

to V_OUTC

.

TGIO (Pin 26): I/O Controller Top Gate Drive. See TGC.

TGIO is designed to typically drive up to 2,000pF of gate

capacitance.

VID0 to VID4 (Pins 14 to 18): VID Programming Inputs.

These are logic inputs that set the output voltage at the

Coresupplytoapreprogrammedvalue(seeTable1).VID4

istheMSB, VID0istheLSB. ThecodesselectedbytheVID

inputs correspond to the Intel Mobile VID specification.

Any VID code transition forces PGOOD to go low for 20µs.

Each VID pin includes an on-chip 30k pull-up resistor in

series with a diode (see Block Diagram).

BOOSTIO (Pin 27): I/O Controller Top Gate Driver Power.

See BOOSTC.

BGIO(Pin28):I/OControllerBottomGateDrive. SeeBGC.

BGIO is designed to typically drive up to 2,000pF of gate

capacitance.

V_CC(Pin 19): Power Supply Input. All internal circuits

except the output drivers are powered from this pin.

Connect V_CCto a low-noise 5V supply and bypass the pin

to GND with at least a 10µF capacitor in close proximity to

the LTC1705.

8

LTC1705

W

BLOCK DIAGRA

P W R B A D I O

P W R B A D C L K

P W R B A D C O R E

9

LTC1705

TEST CIRCUIT

Test Circuit 1

5V

+

I

BOOSTIO

BOOSTC

VCC

PVCC

VINCLK

100µF

0.1µF

V

CC

PV

V

INCLK

CC

BOOSTC

TGC

BOOSTIO

TGIO

f

OSCIO

OSCC

BGC

BGIO

LTC1705

I

2000pF

1000pF

MAXC

MAXIO

2k

COMPC

FBC

COMPIO

FBIO

V

FBC

V

FBIO

SENSEC

VIDO:4

RUN/SS

PGOOD

V

OUTCLK

RUN/SS

+

10µF

SWC

PGND

GND

SWIO

1705 TC

W U W

VID PROGRA I G CODES

Table 1. VID Inputs and Corresponding Core Output Voltages

CODE

VID4

Float

VID3

Gnd

Float

VID2

VID1

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

VID0

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

V

OUTC

CODE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

VID4

Gnd

VID3

Gnd

Float

VID2

Gnd

Float

Gnd

Float

VID1

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

VID0

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

Gnd

Float

V

OUTC

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

Gnd

Float

Gnd

Float

1.275V

1.250V

1.225V

1.200V

1.175V

1.150V

1.125V

1.100V

1.075V

1.050V

1.025V

1.000V

0.975V

0.950V

0.925V

0.900V

2.00V

1.95V

1.90V

1.85V

1.80V

1.75V

1.70V

1.65V

1.60V

1.55V

1.50V

1.45V

1.40V

1.35V

1.30V

1.25V

*

*01111 and 11111 are defined by Intel to signify “no CPU.” The LTC1705

generates the output voltages shown if these codes are selected.

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The LTC1705 includes two, step-down (buck), voltage

mode feedback switching regulator controllers and a low

dropoutlinearregulator.Thethreeoutputsaredesignedto

power the core, I/O and CLK supplies of an Intel Mobile

Pentium system. Each switching regulator controller em-

ploys a synchronous switching architecture with two

external N-channel MOSFETs per channel. The chip oper-

ates from a low voltage input supply (6V maximum) and

provides high power, high efficiency, precisely regulated

output voltages. Several features make the LTC1705 par-

ticularly suited for microprocessor supply regulation.

Output regulation at the core supply is extremely tight,

with initial accuracy and DC line and load regulation better

than 1.25%. Total regulation including transient response

is inside of 3.5% with a properly designed circuit. The

550kHz switching frequency and the high speed internal

feedback amplifiers allow the use of physically small, low

valueexternalcomponentswithoutcompromisingperfor-

mance.Anonboard5-bitDACsetsthecoreoutputvoltage,

consistentwiththeIntelMobileVIDspecification(Table 1).

efficiency while maintaining reasonable duty cycle. In

contrast,aregulatorconvertinginasinglestepfromahigh

input voltage to a 1.xV output must operate at a very

narrow duty cycle, mandating trade-offs in external com-

ponent values while compromising efficiency and tran-

sient response. The efficiency loss can exceed that of a

2-stepsolution. Furthercomplicatingthecalculationisthe

fact that many systems draw a significant fraction of their

total power off the intermediate 5V supply, bypassing the

low voltage supply. 2-step solutions using the LTC1705

usually match or exceed the total system efficiency of

single-step solutions and provide the additional benefits

of improved transient response, reduced PCB area and

simplified power trace routing.

2-step regulation can also buy advantages in thermal

management. Power dissipation in the LTC1705 portion

of a 2-step circuit is lower than it would be in a typical

1-stepconverter,evenincaseswherethe1-stepconverter

has higher total efficiency than the 2-step system. In a

typical microprocessor core supply regulator, for ex-

ample, the regulator is usually located directly next to the

CPU. In a 1-step design, all of the power dissipated by the

core regulator is located next to the already hot CPU,

aggravating thermal management. In a 2-step LTC1705

design, a significant percentage of the power lost in the

core regulation system happens in the 5V supply, which is

usually located away from the CPU. The power lost to heat

in the LTC1705 section of the system is relatively low,

minimizing the added heat near the CPU.

The 800mV internal reference allows regulated output

voltages as low as 800mV without external level shifting

amplifiers. The linear regulator controls an internal P-

channel MOSFET that can provide more than 150mA of

current at an output voltage of 2.5V. A power good

(PGOOD) flag goes high when all the three outputs are in

regulation.

2-Step Conversion

“2-step” architectures use a primary regulator to convert

the input power source (batteries or AC line voltage) to an

intermediate supply voltage, often 5V. This intermediate

voltage is then converted to the low voltage, high current

supplies required by the system using a secondary regula-

tor, such as the LTC1705. 2-step conversion eliminates the

need for a single converter to convert a high input voltage

to a very low output voltage, often an awkward design

challenge. It also fits naturally into systems that continue to

usethe5Vsupplytopowerportionsoftheircircuitryorhave

excess 5V capacity available as newer circuit designs shift

the current load to lower voltage supplies.

Fast Transient Response

The LTC1705 core and I/O supplies use fast 20MHz GBW

opampsaserroramplifiers.Thisallowsthecompensation

network to be designed with several poles and zeros in a

more flexible configuration than with typical gm feedback

amplifiers. The high bandwidth of the amplifier, coupled

with the high 550kHz switching frequency and the low

values of the external inductor and output capacitor, allow

very high loop cross-over frequencies. Additionally, a

typical LTC1705 circuit uses an inductor value on the

order of 1µH, allowing very fast di/dt slew rates. The result

is superior transient response compared with conven-

tional solutions.

Each regulator in a typical 2-step system maintains a

relativelylowstep-downratio(5:1orless),runningathigh

11

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High Efficiency

compensates the linear regulator feedback loop. The CLK

output is short-circuit protected and the built-in thermal

shutdown circuit turns off all three regulator outputs

should the LTC1705 junction temperature exceed 155°C.

The LTC1705 core and I/O supplies use a synchronous

step-down (buck) architecture, with two external N-chan-

nel MOSFETs per output. A floating topside driver and a

simple external charge pump provide full gate drive to

each upper MOSFET. The voltage mode feedback loops

andMOSFETV_DScurrentlimitsensingcircuitsremovethe

need for external current sense resistors, eliminating

externalcomponentsandthecorrespondingpowerlosses

in the high current paths. Properly designed circuits using

low gate charge MOSFETs are capable of efficiencies

exceeding 90% over a wide range of output voltages and

load currents.

SWITCHING ARCHITECTURE DETAILS

The LTC1705 dual switching regulator controller includes

two independent regulator channels. The two switching

regulator controllers and their corresponding external

components act independently of each other with the

exception of the common input bypass capacitor. The

RUN/SS and PGOOD pins also affect both channels. In the

following discussions, when a pin is referred to without

mentioningwhichsideisinvolved, thatdiscussionapplies

equally to both sides.

VID Programming

The LTC1705 includes an onboard feedback network that

programs the core output voltage in accordance with the

Intel Mobile VID specification (Table 1). This network

includes a 10k resistor connected between SENSEC and

FBC and a variable value resistor connected between FBC

and GND, with the value set by the digital code present at

the VID4:0 pins. Connect SENSEC to V_OUTCto allow the

network to monitor the output voltage. No additional

feedback components are required to set the output volt-

age of the core controller, although loop compensation

components are still required. Each VIDn pin includes an

internal 30k pull-up resistor, allowing it to float high if left

unconnected.Thepull-upresistorsconnecttoV_CCthrough

diodes (see Block Diagram), allowing the VIDn pins to be

pulled above V_CCwithout damage.

Switching Architecture

Each half of the LTC1705 is designed to operate as a

synchronous buck converter (Figure 1). Each channel

includes two high power MOSFET gate drivers to control

external N-channel MOSFETs QT and QB. The core drivers

have 0.5Ω output impedances and can carry well over an

amp of continuous current with peak currents up to 5A to

slew large MOSFET gates quickly. The I/O drivers have 2Ω

output impedances. The external MOSFETs are connected

with the drain of QT attached to the input supply and the

source of QT at the switching node SW. QB is the synchro-

nous rectifier with its drain at SW and its source at PGND.

SW is connected to one end of the inductor, with the other

end connected to V_OUT. The output capacitor is connected

from V_OUTto PGND.

Note that codes 01111 and 11111, defined by Intel to

indicate “no CPU present, ” do generate output voltages at

V_OUTC(1.25V and 0.9V, respectively). Also, note that the

I/O and CLK outputs on the LTC1705 are not connected to

the VID circuitry and work independently from the core

controller.

When a switching cycle begins, QB is turned off and QT is

turned on. SW rises almost immediately to V_INand the

inductor current begins to increase. When the PWM pulse

finishes, QTturnsoffandonenonoverlapintervallater, QB

turnson. NowSWdropstoPGNDandtheinductorcurrent

decreases. The cycle repeats with the next tick of the

master clock. The percentage of time spent in each mode

is controlled by the duty cycle of the PWM signal, which in

turn is controlled by the feedback amplifier. The master

clock runs at a 550kHz rate and turns QT on once every

1.8µs. In a typical application with a 5V input and a 1.5V

Linear Regulator and Thermal Shutdown

TheLTC1705CLKoutputisaneasytousemonolithicLDO.

The V_INCLKpin powers the regulator and an internal

P-channel MOS transistor provides the output current at

the 2.5V output. An external 10µF capacitor frequency

12

LTC1705

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APPLICATIO S I FOR ATIO

output, the duty cycle will be set at 1.5/5 • 100% or 30%

by the feedback loop. This will give roughly a 540ns on-

time for QT and a 1.26µs on-time for QB.

combination with a simple external charge pump (Figure

2), this allows the LTC1705 to completely enhance the

gate of QT without requiring an additional, higher supply

voltage.

This constant frequency operation brings with it a couple

of benefits. Inductor and capacitor values can be chosen

with a precise operating frequency in mind and the feed-

back loop components can be similarly tightly specified.

Noise generated by the circuit will always be in a known

frequency band with the 550kHz frequency designed to

leavethe455kHzIFbandfreeofinterference.Subharmonic

oscillation and slope compensation, common headaches

with constant frequency current mode switchers, are

absent in voltage mode designs like the LTC1705.

The two channels of the LTC1705 run from a common

clock, with the phasing chosen to be 180° from the core

side to the I/O side. This has the effect of doubling the

frequency of the switching pulses seen by the input

bypass capacitor, lowering the RMS current seen by the

capacitor and reducing the value required.

Feedback Amplifier

Each side of the LTC1705 senses the output voltage at

V_OUTwith an internal feedback op amp (see Block Dia-

gram). This is a real op amp with a low impedance output,

85dB open-loop gain and 20MHz gain bandwidth product.

The positive input is connected internally to an 800mV

reference, while the negative input is connected to the FB

pin. The output is connected to COMP, which is in turn

connected to the soft-start circuitry and from there to the

PWM generator.

During the time that QT is on, its source (the SW pin) is at

V_IN. V_INis also the power supply for the LTC1705. How-

ever, QT requires V_IN+V_GS(ON)at its gate to achieve mini-

mum R_ON. This presents a problem for the LTC1705—it

needs to generate a gate drive signal at TG higher than its

highest supply voltage. To accomplish this, the TG driver

runs from floating supplies, with its negative supply

attached to SW and its power supply at BOOST. This

allows it to slew up and down with the source of QT. In

Unlike many regulators that use a resistor divider con-

nected to a high impedance feedback input, the LTC1705

is designed to use an inverting summing amplifier topol-

ogy with the FB pin configured as a virtual ground. This

allows flexibility in choosing pole and zero locations not

available with simple gm configurations. In particular, it

allows the use of “Type 3” compensation, which provides

a phase boost at the LC pole frequency and significantly

improves loop phase margin (see Figure 3). Note that the

core side of the LTC1705 includes R1 and R_Binternally as

part of the VID DAC circuitry.

V

IN

+

C

IN

QT

TG

L

SW

V

C

LTC1705

OUT

QB

BG

PGND

1705 F01

Figure 1. Synchronous Buck Architecture

V

IN

+

D

LTC1705 PV

CP

CC

C

C3

R3

IN

BOOST

TG

+

0.8V

C

CP

COMP

FB

QT

R1

SW

FB

L

V

–

OUT

V

C

OUT

LTC1705

BG

R

B

QB

C2

PGND

C1

R2

1705 F02

1705 F03

Figure 3. "Type 3" Feedback Loop (I/O Channel)

Figure 2. Floating TG Driver Supply

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MIN/MAX Comparators

PGOOD Flag

Two additional feedback loops keep an eye on the main

feedback amplifier and step in if the feedback node moves

±5% from its nominal 800mV value. The MAX comparator

(see Block Diagram) activates if FB rises more than 5%

above 800mV. It immediately turns the top MOSFET (QT)

off and the bottom MOSFET (QB) on and keeps them that

way until FB falls back within 5% of its nominal value. This

pulls the output down as fast as possible, preventing

damage to the (often expensive) load. If FB rises because

the output is shorted to a higher supply, QB will stay on

until the short goes away, the higher supply current limits

or QB dies trying to save the load. This behavior provides

maximum protection against overvoltage fault at the out-

put, while allowing the circuit to resume normal operation

when the fault is removed.

The LTC1705 incorporates a power good pin (PGOOD).

PGOOD is an open-drain output and requires an external

pull-up resistor. If all three regulators are typically within

±10%oftheirnominalvalue,transistorMPGshutsoff(see

Block Diagram) and PGOOD is pulled high by the external

pull-up resistor. If any of the three outputs is more than

10% outside the nominal value for more than 4µs, PGOOD

pulls low, indicating that an output is out of regulation. For

PGOODtopullhigh, allthreeoutputsmustbeinregulation

for more than 20µs. PGOOD remains active during soft

start and current limit. On power up, PGOOD pulls low. As

soon as the RUN/SS pin rises above the shutdown thresh-

old, the three pair of power good comparators take over

and control the transistor MPG directly. The 4µs and 20µs

delay ensure that short output transient glitches, that are

successfully “caught” by the power good comparators,

don’t cause momentary glitches at the PGOOD pin.

The MIN comparator (see Block Diagram) trips if FB is

more than 5% below 800mV and immediately forces the

switch duty cycle to 90% to bring the output voltage back

into range. It releases when FB is within the 5% window.

MINisdisabledwhenthesoft-startorcurrentlimitcircuits

are active—the only two times that the output should

legitimately be below its regulated value.

For the core channel, if there is a VID code change, the

internal DAC responds by switching its output voltage

immediately.However,theswitchingpowersupplyoutput

slew rate is limited by the output filter. If the VID code step

change is small, the power good comparator might not

register any transition. To acknowledge the code transi-

tioncommand, theLTC1705forcesPGOODtopulllowfor

20µs once there is a VID code change. After this short

interval, the power good comparators decide the PGOOD

status.

Notice that the FB pin is the virtual ground node of the

feedback amplifier. A typical compensation network does

not include local DC feedback around the amplifier, so that

the DC level at FB will be an accurate replica of the output

voltage,divideddownbyR1andR_B(Figure3).However,the

compensation capacitors will tend to attenuate AC signals

atFB, especiallywithlowbandwidthType1feedbackloops.

ThiscancreateasituationwheretheMIN,MAXandPGOOD

comparators do not respond immediately to shifts in the

output voltage, if they monitor the output at FB. With VID

code switching on the fly, this problem is aggravated.

Shutdown/Soft-Start

The RUN/SS pin performs two functions: if pulled to

ground, it shuts down the LTC1705 and it acts as a

conventional soft-start pin, enforcing a maximum duty

cycle limit proportional to the voltage at RUN/SS. An

internal 3µA current source pull-up is connected to the

RUN/SS pin, allowing a soft-start ramp to be generated

withasingleexternalcapacitortoground. The3µAcurrent

source is active even if the LTC1705 is shut down, ensur-

ing the device will start when any external pull-down at

RUN/SS is released. In shutdown, the LTC1705 enters

micropower sleep mode and quiescent current drops

typically below 50µA.

To overcome this, a second resistor divider is used (see

Block Diagram) to provide the MIN, MAX and PGOOD

comparators with an accurate replica of the output voltage.

This ensures that the comparators react rapidly to code

changes. For the I/O channel, the output voltage is indepen-

dent of VID codes and therefore the change in V_OUTis

minimized. Maximizing I/O feedback loop bandwidth will

minimize these delays and allow MIN and MAX to operate

properly. See the Feedback Loop/Compensation section.

14

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The RUN/SS pin shuts down the LTC1705 if it falls below

0.5V (Figure 4). Between 0.5V and about 1V, the LTC1705

wakes up and the duty cycle is kept to a miminum. As the

potential at RUN/SS increases, the duty cycle increases

linearly between 1V and 2V, reaching its final value of 90%

when RUN/SS is above 2V. Somewhere before this point,

the feedback amplifier will assume control of the loop and

the output will come into regulation. When RUN/SS rises

to 1V below V_CC, the MIN feedback comparator is enabled

and the LTC1705 is in full operation.

includes a trimmed 10µA pull-up, enabling the user to set

thevoltageatI_MAXwithasingleresistor, R_IMAX, toground.

TheLTC1705comparesthetwoinputsandbeginslimiting

the output current when the magnitude of the negative

voltage at the SW pin is greater than the voltage at I_MAX

.

When the load current increases abruptly, the voltage

feedbackloopforcesthedutycycletoincreaserapidlyand

the on-time of QB will be small momentarily. The R_DS(ON)

of QB must be low enough to ensure that the SW node is

pulled low within the QB on-time for proper current

sensing.

The current limit detector is connected to an internal gm

amplifier that pulls a current from the RUN/SS pin propor-

tional to the difference in voltage magnitudes between the

SW and I_MAXpins. The maximum value of this current is

250µA (typically). It begins to discharge the soft-start

capacitor at RUN/SS, reducing the duty cycle and control-

ling the output voltage until the current drops below the

limit. The soft-start capacitor needs to move a fair amount

before it has any effect on the duty cycle, adding a delay

until the current limit takes effect (Figure 4). This allows

the LTC1705 to experience brief overload conditions with-

out affecting the output voltage regulation. The delay also

acts as a pole in the current limit loop to enhance loop

stability.Whilethesoft-startcapacitorisbeingdischarged,

the top MOSFET must withstand the high power dissipa-

tion due to the high current especially if the regulator is

powered by a high current supply. Larger overloads cause

thesoft-startcapacitortopulldownquickly,protectingthe

output components from damage. The current limit gm

amplifier includes a clamp to prevent it from pulling RUN/

SS below 0.5V and shutting off the LTC1705.

V

OUT

0V

NORMAL

CURRENT

LIMIT

START UP

OPERATION

5V

4V

COMP CONTROLS

DUTY CYCLE

MIN

COMPARATOR

ENABLE

2V

1V

RUN/SS CONTROLS

DUTY CYCLE

MINIMUM DUTY CYCLE

0.5V

0V

POWER-DOWN MODE

LTC1705 ENABLE

1705 F04

Figure 4. Soft-Start Operation in Start Up and Current Limit

Current Limit

TheLTC1705includesanonboardcurrentlimitcircuitthat

limitsthemaximumoutputcurrenttoauser-programmed

level. It works by sensing the voltage drop across QB

during the time that QB is on and comparing that voltage

to a user-programmed voltage at I_MAX. Since QB looks like

a low value resistor during its on-time, the voltage drop

across it is proportional to the current flowing in it. In a

buckconverter,theaveragecurrentintheinductorisequal

to the output current. This current also flows through QB

during its on-time. Thus, by watching the voltage across

QB, the LTC1705 can monitor the output current.

Power MOSFET R_DS(ON)varies from MOSFET to MOSFET,

limitingtheaccuracyobtainablefromtheLTC1705current

limit loop. Additionally, ringing on the SW node due to

parasitics can add to the apparent current, causing the

loop to engage early. The LTC1705 current limit is de-

signed primarily as a disaster prevention, “no blow up”

circuit and is not useful as a precision current regulator. It

should typically be set around 50% above the maximum

expected normal output current to prevent component

tolerancesfromencroachingonthenormalcurrentrange.

See the Current Limit Programming section for advice on

Any time QB is on and the current flowing to the output is

reasonably large, the SW node at the drain of QB will be

somewhat negative with respect to PGND. The LTC1705

senses this voltage, inverts it and compares the sensed

voltagewithapositivevoltageattheI_MAXpin. TheI_MAXpin

choosing a valve for R_IMAX

.

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EXTERNAL COMPONENT SELECTION

Gate Charge

Gate charge is amount of charge (essentially, the number

of electrons) that the LTC1705 needs to put into the gate

of an external MOSFET to turn it on. The easiest way to

visualize gate charge is to think of it as a capacitance from

the gate pin of the MOSFET to SW (for QT) or to PGND (for

QB). This capacitance is composed of MOSFET channel

charge, actual parasitic drain-source capacitance and

Miller-multiplied gate-drain capacitance, but can be ap-

proximated as a single capacitance from gate to source.

Regardless of where the charge is going, the fact remains

that it all has to come out of PV_CCto turn the MOSFET gate

on and when the MOSFET is turned back off, that charge

all ends up at ground. In the meanwhile, it travels through

the LTC1705’s gate drivers, heating them up. More power

lost!

Power MOSFETs

GettingpeakefficiencyoutoftheLTC1705dependsstrongly

on the external MOSFETs used. The LTC1705 requires at

least two external MOSFETs per side—more if one or

more of the MOSFETs are paralleled to lower on-resis-

tance. To work efficiently, these MOSFETs must exhibit

low R_DS(ON)at 5V V_GSto minimize resistive power loss

while they are conducting current. They must also have

low gate charge to minimize transition losses during

switching. On the other hand, voltage breakdown require-

ments in a typical LTC1705 circuit are pretty tame: the 6V

maximuminputvoltagelimitstheV_DSandV_GStheMOSFETs

can see to safe levels for most devices.

Low R_DS(ON)

Inthiscase,thepowerislostinlittlebite-sizedchunks,one

chunk per switch per cycle, with the size of the chunk set

bythegatechargeoftheMOSFET. EverytimetheMOSFET

switches, another chunk is lost. Clearly, the faster the

clock runs, the more important gate charge becomes as a

lossterm.Old-fashionedswitchersthatranat20kHzcould

pretty much ignore gate charge as a loss term; in the

550kHz LTC1705, gate charge loss can be a significant

efficiency penalty. Gate charge loss can be the dominant

loss term at medium load currents, especially with large

MOSFETs. Gate charge loss is also the primary cause of

power dissipation in the LTC1705 itself.

R_DS(ON)calculationsareprettystraightforward. R_DS(ON)is

the resistance from the drain to the source of the

MOSFETwhen the gate is fully on. Many MOSFETs have

R_DS(ON)specified at 4.5V gate drive—this is the right

number to use in LTC1705 circuits running from a 5V

supply. As current flows through this resistance while the

MOSFET is on, it generates I²R watts of heat, where I is the

current flowing (usually equal to the output current) and R

is the MOSFET R_DS(ON). This heat is only generated when

theMOSFETison.Whenitisoff,thecurrentiszeroandthe

power lost is also zero (and the other MOSFET is busy

losing power).

TG Charge Pump

This lost power does two things: it subtracts from the

power available at the output, costing efficiency, and it

makes the MOSFET hotter—both bad things. The effect is

worst at maximum load when the current in the MOSFETs

and thus the power lost are at a maximum. Lowering

R_DS(ON)improves heavy load efficiency at the expense of

additional gate charge (usually) and more cost (usually).

Proper choice of MOSFET R_DS(ON)becomes a trade-off

between tolerable efficiency loss, power dissipation and

cost. Note that while the lost power has a significant effect

on system efficiency, it only adds up to a watt or two in a

typical LTC1705 circuit, allowing the use of small, surface

mount MOSFETs without heat sinks.

There’sanothernuanceofMOSFETdrivethattheLTC1705

needs to get around. The LTC1705 is designed to use

N-channel MOSFETs for both QT and QB, primarily be-

cause N-channel MOSFETs generally cost less and have

lower R_DS(ON)than similar P-channel MOSFETs. Turning

QB on is simple since the source of QB is attached to

PGND; the LTC1705 just switches the BG pin between

PGND and PV_CC. Driving QT is another matter. The source

of QT is connected to SW which rises to PV_CCwhen QT is

on. To keep QT on, the LTC1705 must get TG one MOSFET

V_GS(ON)above PV_CC. It does this by utilizing a floating

driver with the negative lead of the driver attached to SW

(the source of QT) and the PV_CClead of the driver coming

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out separately at BOOST. An external 1µF capacitor (CCP) LTC1705 I/O channel typically operates at a much smaller

connected between SW and BOOST (Figure 2) supplies output current, hence the input bypass capacitor in an

power to BOOST when SW is high and recharges itself LTC1705 circuit should be chosen primarily to meet the

through DCP when SW is low. This simple charge pump core output requirement.

keeps the TG driver alive even as it swings well above

Consider our 15A example. The input bypass capacitor

PV_CC. The value of the bootstrap capacitor CCP needs to

gets exercised in three ways: its ESR must be low enough

be at least 100 times that of the total “effective” gate

to keep the initial drop as QT turns on within a reasonable

capacitance of the topside MOSFET(s). For very large

value (100mV or so); its RMS current capability must be

external MOSFETs (or multiple MOSFETs in parallel), CCP

adequate to withstand the 7A_RMSripple current at the

may need to be increased beyond the 1µF value.

input and the capacitance must be large enough to main-

tain the input voltage until the input supply can make up

Input Supply

the difference. Generally, a capacitor that meets the first

The BiCMOS process that allows the LTC1705 to include

large MOSFET drivers on-chip also limits the maximum

input voltage to 6V. This limits the practical maximum

input supply to a loosely regulated 5V rail. The LTC1705

operates properly with input supplies down to about 3.3V,

so a typical 3.3V supply can also be used if the external

MOSFETs are appropriately chosen (see the Power

MOSFETs section).

two parameters will have far more capacitance than is

required to keep capacitance-based droop under control.

In our example, we need 0.006Ω ESR to keep the input

drop under 100mV with a 15A current step and 7A_RMS

ripple current capacity to avoid overheating the capacitor.

These requirements can be met with multiple low ESR

tantalum or electrolytic capacitors in parallel or with a

large monolithic ceramic capacitor.

At the same time, the input supply needs to supply several

amps of current without excessive voltage drop. The input

supply must have regulation adequate to prevent sudden

load changes from causing the LTC1705 input voltage to

dip. In typical applications where the LTC1705 is generat-

ing a secondary low voltage logic supply, all of these input

conditions are met by the main system logic supply when

fortified with an input bypass capacitor.

Tantalum capacitors are a popular choice as input capaci-

tors for LTC1705 applications, but they deserve a special

caution here. Generic tantalum capacitors have a destruc-

tive failure mechanism if they are subjected to large RMS

currents (like those seen at the input of a LTC1705). At

some random time after they are turned on, they can blow

up for no apparent reason. The capacitor manufacturers

are aware of this and sell special “surge tested” tantalum

capacitors specifically designed for use with switching

regulators. When choosing a tantalum input capacitor,

make sure that it is rated to carry the RMS current that the

LTC1705 will draw. If the data sheet doesn’t give an RMS

currentrating,chancesarethecapacitorisn’tsurgetested.

Don’t use it!

Input Bypass Capacitor

A typical LTC1705 circuit running from a 5V logic supply

might provide 1.6V at 15A at its core output. 5V to 1.6V

implies a duty cycle of 32%, which means QTC is on 32%

of each switching cycle. During QTC’s on-time, the current

drawn from the input equals the load current and during the

rest of the cycle, the current drawn from the input is near

zero. This 0A to 15A, 32% duty cycle pulse train adds up to

7A_RMSat the input. At 550kHz, switching cycles last about

1.8µs—most system logic supplies have no hope of regu-

lating output current with that kind of speed. A local input

bypass capacitor is required to make up the difference and

prevent the input supply from dropping drastically when

QTC kicks on. This capacitor is usually chosen for RMS

ripple current capability and ESR as well as value. The

Output Bypass Capacitor

The output bypass capacitor has quite different require-

ments from the input capacitor. The ripple current at the

output of a buck regulator like the LTC1705 is much lower

than at the input, due to the fact that the inductor current

is constantly flowing at the output. The primary concern at

the output is capacitor ESR. Fast load current transitions

at the output appear as voltage across the ESR of the

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output bypass capacitor until the feedback loop in the

LTC1705 can change the inductor current to match the

newloadcurrentvalue. ThisESRstepattheoutputisoften

the single largest budget item in the load regulation

calculation. As an example, our hypothetical 1.6V, 15A

switcher with a 0.006Ω ESR output capacitor would

experiencea90mVstepattheoutputwitha0Ato15Aload

step—a 5.6% output change!

andthefeedbackamplifierwithitscompensationnetwork.

All of these components affect loop behavior and must be

accounted for in the loop compensation. The modulator

consistsoftheinternalPWMgenerator,theoutputMOSFET

drivers and the external MOSFETs themselves. From a

feedback loop point of view, it looks like a linear voltage

transferfunctionfromCOMPtoSWandhasagainroughly

equal to the input voltage. It has fairly benign AC behavior

at typical loop compensation frequencies with significant

phase shift appearing at half the switching frequency.

Usually the solution is to parallel several capacitors at the

output. Forexample, tokeepthetransientresponseinside

of 3.5% with the previous design, we’d need an output

ESR better than 0.004Ω. This can be met with six 0.025Ω,

180µF special polymer capacitors in parallel.

Theexternalinductor/outputcapacitorcombinationmakes

a more significant contribution to loop behavior. These

componentscauseasecondorderLCrolloffattheoutput,

with the attendant 180° phase shift. This rolloff is what

filters the PWM waveform, resulting in the desired DC

output voltage, but the phase shift complicates the loop

compensation if the gain is still higher than unity at the

pole frequency. Eventually (usually well above the LC pole

frequency), the reactance of the output capacitor will

approach its ESR and the rolloff due to the capacitor will

stop, leaving 6dB/octave and 90° of phase shift (Figure 5).

Inductor

The inductor in a typical LTC1705 circuit is chosen prima-

rily for value and saturation current. The inductor value

sets the ripple current, which is commonly chosen be-

tween 20% to 40% of the anticipated full load current.

Ripple current is set by:

t_ON(QB)(V_OUT

)

I_RIPPLE

=

L

In our 1.6V, 15A example, we’d set the ripple to 20% of

15A or 3A and the inductor value would be:

GAIN

A

V

–12dB/OCT

0

FREQ

–90

t_ON(QB)(V_OUT

)

(1.2µs)(1.6V)

PHASE

L =

=

= 0.67µH

–180

–270

–360

I_RIPPLE

3A

–6dB/OCT

1.6V

5V

with t_ON(QB)= 1−

/550kHz = 1.2µs

1705 F05

Figure 5. Transfer Function of Buck Modulator

The inductor must not saturate at the expected peak

current. In this case, if the current limit was set to 22.5A,

the inductor should be rated to withstand 22.5A + (0.5 •

I_RIPPLE) or 24A without saturating.

So far, the AC response of the loop is pretty well out of the

user’scontrol.Themodulatorisafundamentalpieceofthe

LTC1705 design and the external L and C are usually

chosen based on the regulation and load current require-

ments without considering the AC loop response. The

feedback amplifier, on the other hand, gives us a handle

with which to adjust the AC response. The goal is to have

180° phase shift at DC (so the loop regulates) and some-

thing less than 360° phase shift at the point that the loop

FEEDBACK LOOP/COMPENSATION

Feedback Loop Types

In a typical LTC1705 circuit, the feedback loop consists of

the modulator, the external inductor, the output capacitor

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gain falls to 0dB. The simplest strategy is to set up the

feedback amplifier as an inverting integrator, with the 0dB

frequency lower than the LC pole (Figure 6). This “Type 1”

configuration is stable but transient response is less than

exceptional if the LC pole is at a low frequency.

“Type 3” loops (Figure 8) use two poles and two zeros to

obtain a 180° phase boost in the middle of the frequency

band. A properly designed Type 3 circuit can maintain

acceptable loop stability even when low output capacitor

ESR causes the LC section to approach 180° phase shift

well above the initial LC roll-off. As with a Type 2 circuit,

the loop should cross through 0dB in the middle of the

phase bump to maximize phase margin. Many LTC1705

circuitsusinglowESRtantalumorOS-CONoutputcapaci-

torsneedType3compensationtoobtainacceptablephase

margin with a high bandwidth feedback loop.

Figure 7 shows an improved “Type 2” circuit that uses an

additional pole-zero pair to temporarily remove 90° of

phase shift. This allows the loop to remain stable with 90°

more phase shift in the LC section, provided the loop

reaches 0dB gain near the center of the phase “bump.”

Type 2 loops work well in systems where the ESR zero in

the LC roll-off happens close to the LC pole, limiting the

total phase shift due to the LC. The additional phase

compensation in the feedback amplifier allows the 0dB

point to be at or above the LC pole frequency, improving

loop bandwidth substantially over a simple Type 1 loop. It

has limited ability to compensate for LC combinations

where low capacitor ESR keeps the phase shift near 180°

for an extended frequency range. LTC1705 circuits using

conventional switching grade electrolytic output capaci-

tors can often get acceptable phase margin with Type 2

compensation.

IN

C2

C1

C3

R3

R2

R1

–6dB/OCT

GAIN

FB

–

+6dB/OCT

–6dB/OCT

R

B

OUT

0

FREQ

–90

V

REF

+

–180

–270

–360

PHASE

1705 F08

Figure 8. Type 3 Schematic and Transfer Function

C1

IN

GAIN

Feedback Component Selection

R1

FB

Selecting the R and C values for a typical Type 2 or Type 3

loop is a nontrivial task. The applications shown in this

data sheet show typical values, optimized for the power

components shown. They should give acceptable perfor-

mance with similar power components, but can be way off

if even one major power component is changed signifi-

cantly. Applications that require optimized transient re-

sponse will need to recalculate the compensation values

specifically for the circuit in question. The underlying

mathematics are complex, but the component values can

be calculated in a straightforward manner if we know the

gain and phase of the modulator at the crossover fre-

quency.

–

–6dB/OCT

R

OUT

0

FREQ

–90

B

V

+

REF

–180

–270

–360

PHASE

1705 F06

Figure 6. Type 1 Schematic and Transfer Function

C2

C1

IN

R2

–6dB/OCT

R1

GAIN

FB

–6dB/OCT

–

R

OUT

0

FREQ

–90

B

Modulator gain and phase can be measured directly from

a breadboard or can be simulated if the appropriate

parasitic values are known. Measurement will give more

accurateresults,butsimulationcanoftengetcloseenough

to give a working system. To measure the modulator gain

and phase directly, wire up a breadboard with an LTC1705

V

+

REF

–180

–270

–360

PHASE

1705 F07

Figure 7. Type 2 Schematic and Transfer Function

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and the actual MOSFETs, inductor and input and output

capacitors that the final design will use. This breadboard

should use appropriate construction techniques for high

speed analog circuitry: bypass capacitors located close to

the LTC1705, no long wires connecting components,

appropriately sized ground returns, etc. Wire the feedback

amplifier as a simple Type 1 loop, with a 10k resistor from

*1705 modulator gain/phase

*2000 Linear Technology

*this file written to run with PSpice 8.0

*may require modifications for other

SPICE simulators

*MOSFETs

rfet mod sw 0.02

;MOSFET rdson

V

_OUTto FB and a 0.1µF feedback capacitor from COMP to

*inductor

FB. Choose the bias resistor (R_B) as required to set the

desired output voltage. Disconnect R_Bfrom ground and

connect it to a signal generator or to the source output of

a network analyzer (Figure 9) to inject a test signal into the

loop. Measure the gain and phase from the COMP pin to

the output node at the positive terminal of the output

capacitor. Make sure the analyzer’s input is AC coupled so

that the DC voltages present at both the COMP and V_OUT

nodes don’t corrupt the measurements or damage the

analyzer.

lext sw out1 1u

rl out1 out 0.005

;inductor value

;inductor series R

*output cap

cout out out2 1000u ;capacitor value

resr out2 0 0.01

;capacitor ESR

*1705 internals

emod mod 0 comp 0 5 ;3.3 for 3.3V supply

vstim comp 0 0 ac 1 ;ac stimulus

.ac dec 100 1k 1meg

5V

.probe

.end

10Ω

+

10µF

MBR0530T

With the gain/phase plot in hand, a loop crossover fre-

quency can be chosen. Usually the curves look something

like Figure 5. Choose the crossover frequency in the rising

or flat parts of the phase curve, beyond the external LC

poles. Frequencies between 10kHz and 50kHz usually

work well. Note the gain (GAIN, in dB) and phase (PHASE,

in degrees) at this point. The desired feedback amplifier

gain will be -GAIN to make the loop gain at 0dB at this

frequency.Nowcalculatetheneededphaseboost,assum-

ing 60° as a target phase margin:

V

PV

CC

V

TO

COMP

QT

QB

COMP

FB

TG

ANALYZER

BOOST

0.1µF

1µF

L

SW

LTC1705

V

TO

OUT

R

B

10k

ANALYZER

+

BG

C

OUT

AC SOURCE

FROM

ANALYZER

RUN/SS

NC

GND

PGND

1705 F09

Figure 9. Modulator Gain/Phase Measurement Set Up

BOOST = –(PHASE + 30°)

If breadboard measurement is not practical, a SPICE

simulation can be used to generate approximate gain/

phase curves. Plug the expected capacitor, inductor and

MOSFET values into the following SPICE deck and gener-

ate an AC plot of V(V_OUT)/V(COMP) in dB and phase of

V_OUTin degrees. Refer to your SPICE manual for details of

how to generate this plot.

If the required BOOST is less than 60°, a Type 2 loop can

be used successfully, saving two external components.

BOOST values greater than 60° usually require Type 3

loops for satisfactory performance.

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Finally, choose a convenient resistor value for R1 (10k is

usuallyagoodvalue). Nowcalculatetheremainingvalues:

CURRENT LIMIT PROGRAMMING

Programming current limit on the LTC1705 is straight-

forward. The I_MAXpin sets the current limit by setting the

maximum allowable voltage drop across QB (the bottom

MOSFET) before the current limit circuit engages. The

voltage across QB is set by its on-resistance and the

current flowing in the inductor, which is the same as the

output current. The LTC1705 current limit circuit inverts

the negative voltage across QB before comparing it with

the voltage at I_MAX, allowing the current limit to be set with

a positive voltage.

(K is a constant used in the calculations)

f = chosen crossover frequency

G = 10^(GAIN/20)(this converts GAIN in dB to G in

absolute gain)

TYPE 2 Loop:

BOOST

K = Tan

+ 45°

To set the current limit, calculate the expected voltage

drop across QB at the maximum desired current:

2

1

C2 =

V_PROG= (I_LIMIT) (R_DS(ON)

)

2πfGKR1

C1= C2 K²−1

I_LIMITshould be chosen to be quite a bit higher than the

expected operating current, to allow for MOSFET R_DS(ON)

changes with temperature. Setting I_LIMITto 150% of the

maximumnormaloperatingcurrentisusuallysafeandwill

adequately protect the power components if they are

chosen properly. Note that the ringing on the switch node

can cause error for the current limit threshold. This factor

will change depending on the layout and the components

used. V_PROGis then programmed at the I_MAXpin using the

internal 10µA pull-up and an external resistor:

(

)

K

R2 =

R_B=

2πfC1

_REF(R1)

V_OUT− V_REF

V

TYPE 3 Loop:

R_IMAX= V_PROG/10µA

BOOST

K = Tan²

+ 45°

The resulting value of R_IMAXshould be checked in an

actual circuit to ensure that the current circuit kicks in as

expected. MOSFET R_DS(ON)specs are like horsepower

ratings in automobiles and should be taken with a grain of

salt. Circuits that use very low values for R_IMAX(<10k)

shouldbecheckedcarefully, sincesmallchangesinR_IMAX

can cause large I_LIMITchanges when the switch node

ringing makes up a large percentage of the total V_PROG

value. If V_PROGis set too low, the LTC1705 may fail to start

up.

4

1

C2 =

2πfGR1

C1= C2 K −1

(

)

K

R2 =

R3 =

C3 =

2πfC1

R1

K − 1

1

2πf KR3

V_REF(R1)

V_OUT− V_REF

R_B=

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Accuracy Trade-Offs

OPTIMIZING PERFORMANCE

2-Step Conversion

The V_DSsensing scheme used in the LTC1705 is not

particularly accurate, primarily due to uncertainty in the

R_DS(ON)from MOSFET to MOSFET. A second error term

arises from the ringing present at the SW pin, which

causes the V_DSto look larger than (I_LOAD)(R_DS(ON)) at the

beginning of QB’s on-time. These inaccuracies do not

prevent the LTC1705 current limit circuit from protecting

itself and the load from damaging overcurrent conditions,

but they do prevent the user from setting the current limit

to a tight tolerance if more than one copy of the circuit is

being built. The 50% factor in the current setting equation

above reflects the margin necessary to ensure that the

circuitwillstayoutofcurrentlimitatthemaximumnormal

load, even with a hot MOSFET that is running quite a bit

higher than its R_DS(ON)spec.

The LTC1705 is ideally suited for use in 2-step conversion

systems. 2-step systems use a primary regulator to con-

vert the input power source (batteries or AC line voltage)

to an intermediate supply voltage, often 5V. The LTC1705

then converts the intermediate voltage to the lower volt-

age, high current supplies required by the system. Com-

pared to a 1-step converter that converts a high input

voltage directly to a very low output voltage, the 2-step

converter exhibits superior transient response, smaller

component size and equivalent efficiency. Thermal man-

agement and layout complexity are also improved with a

2-step approach.

A typical notebook computer supply might use a 4-cell Li-

Ion battery pack as an input supply with a 15V nominal

terminal voltage. The logic circuits require 5V/3A and

3.3V/5A to power system board logic and 2.5V/0.15A,

1.5V/2A and 1.3V/15A to power the CPU. A typical 2-step

conversion system would use a step-down switcher (per-

haps an LTC1628 or two LTC1625s) to convert 15V to 5V

and another to convert 15V to 3.3V (Figure 10). The 3.3V

input supply can power the 1.3V output at the LTC1705

core channel and the 2.5V LDO. The 5V input supply can

power the 1.5V I/O channel. The corresponding 1-step

system would use four similar step-down switchers plus

an LDO, each switcher using 15V as the input supply and

generating one of the four output voltages.

V_CLKLINEAR REGULATOR

The LTC1705 monolithic LDO linear regulator is easy to

use. Input and output supply bypass capacitors are the

only two external components required for this LDO. The

V_INCLKpinpowersuptheregulatorandaninternalP-channel

MOS transistor sources at least 150mA of current at a

fixed output voltage of 2.5V. This device is short-circuit

protected and includes thermal shutdown to turn off all

three regulator outputs should the junction temperature

exceed about 155°C.

The circuit design in the LTC1705 requires the use of an

output capacitor as part of the frequency compensation. A

minimum output capacitor of 2.2µF and ESR larger than

100mΩ is recommended to prevent oscillations. Larger

values of output capacitance decrease the peak deviations

and provide improved transient response for large load

current changes. Many different types of capacitors are

available and have widely varying characteristics. These

capacitors differ in capacitor tolerance (sometimes rang-

ing up to ±100%), equivalent series resistance, equivalent

series inductance and capacitance temperature coeffi-

cient. In a typical operating condition, a 10µF solid tanta-

lum at the V_OUTCLKpin ensures stability. The AVX

TPSD106M035R0300 or equivalent works well in this

application.

Clearly, the 5V and 3.3V sections of the two schemes are

equivalent. The 2-step system draws additional power

from the 5V and 3.3V outputs, but the regulation tech-

niques and trade-offs at these outputs are similar. The

difference lies in the way the 1.5V and 1.3V supplies are

generated. For example, the 2-step system converts 3.3V

to 1.3V with a 39% duty cycle. During the QT on-time, the

voltage across the inductor is 2V and during the QB on-

time, the voltage is 1.3V, giving roughly symmetrical

transientresponsetopositiveandnegativeloadsteps.The

2Vmaximumvoltageacrosstheinductorallowstheuseof

a small 0.47µH inductor while keeping ripple current to 3A

(20% of the 15A maximum load). By contrast, the 1-step

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converter is converting 15V to 1.3V, requiring just a 9%

dutycycle. Inductorvoltagesarenow13.7VwhenQTison

and1.3VwhenQBison, givingvastlydifferentdi/dtvalues

andcorrespondinglyskewedtransientresponsewithposi-

tive and negative current steps. The narrow 9% duty cycle

usually requires a lower switching frequency, which in

turn requires a higher value inductor and larger output

capacitor. Parasitic losses due to the large voltage swing

at the source of QT cost efficiency, eliminating any advan-

tage the 1-step conversion might have had.

regulator is right there next to the hot CPU, aggravating

thermal management. In a 2-step LTC1705 design, a

significant percentage of the power lost in the core regu-

lation system happens in the 5V or 3.3V supply, which is

usually away from the CPU. The power lost to heat in the

LTC1705 section of the system is relatively low, minimiz-

ing the heat near the CPU.

Additionally,witha1-stepconverter,thehighinputbattery

voltage requires the MOSFET to operate at high voltage

levels. This imposes stringent requirements on the

MOSFETs selection. Most of the MOSFETs that meet the

high voltage and high current requirements are expensive

and bulky. This makes for an awkward power supply

design, especially in portable applications. The high input

voltage also necessitates higher gate drive, which aggra-

vate switching losses.

Note that power dissipation in the LTC1705 portion of a

2-step circuit is lower than it would be in a typical 1-step

converter, even in cases where the 1-step converter has

higher total efficiency than the 2-step system. In a typical

microprocessor core supply regulator, for example, the

regulator is usually located right next to the CPU. In a

1-step design, all of the power dissipated by the core

LTC1628*

5V/3A LOGIC SUPPLY

3.3V/5A LOGIC SUPPLY

I/O

1.5V/2A CPU I/O SUPPLY

CORE

LDO

1.3V/15A CPU CORE SUPPLY

2.5V/0.15A CPU CLOCK SUPPLY

LTC1705

CPU SUPPLY CONTROLLER

*OR TWO LTC1625s

2-STEP CONVERSION OFFERS

• BETTER TRANSIENT RESPONSE

• SMALLER COMPONENT SIZE

• BETTER THERMAL MANAGEMENT

• LOWER VOLTAGE REQUIREMENT FOR MOSFETS

• SMALLER SWITCHING LOSS

• EQUIVALENT EFFICIENCY

1705 F10

Figure 10. 2-Step Conversion Block Diagram

23

LTC1705

U

W U U

APPLICATIO S I FOR ATIO

2-Step Efficiency Calculation

If the 5V and 3.3V supplies are each 94% efficient, the

power lost in each supply is:

Calculating the efficiency of a 2-step converter system

involves some subtleties. Simply multiplying the effi-

ciency of the primary 5V or 3.3V supply by the efficiency

of the 1.5V or 1.3V supply under estimates the actual

efficiency, since a significant fraction of the total power is

drawn from the 3.3V and 5V rails in a typical system. The

correct way to calculate system efficiency is to calculate

thepowerlostineachstageoftheconverteranddividethe

total output power from all outputs by the sum of the

output power plus the power lost:

1.3V: 21.67W – 19.5W

1.5V: 3.3W – 3W

= 2.17W

= 0.3W

2.5V: 0.5W – 0.375W

= 0.125W

3.3V: 16.5W + 3.3V(6.6A + 0.152A) = 38.78W Load

(38.78W/94%) – 38.78W

5V: 15W + 5V(0.66A)

(18.3W/94%) – 18.3W

Total Loss

Total System Efficiency =

= 2.48W Lost

= 18.3W Load

= 1.17W Lost

= 6.25W

Efficiency =

TotalOutputPower

TotalOutputPower + TotalOutput Lost

54.375W/(54.375W + 6.25W) = 89.7%

100%

(

)

Maximizing High Load Current Efficiency

In our example 2-step system, the total output power is:

Total Output Power =

Efficiency at high load currents is primarily controlled by

the resistance of the components in the power path (QT,

QB, L_EXT) and power lost in the gate drive circuits due to

MOSFET gate charge. Maximizing efficiency in this region

of operation is as simple as minimizing these terms.

15W + 16.5W + 0.375W + 3W + 19.5W = 54.375W

(corresponding to 5V, 3.3V, 2.5V, 1.5V and

1.3V output voltages)

The behavior of the load over time affects the efficiency

strategy. Parasitic resistances in the MOSFETs and the

inductor set the maximum output current the circuit can

supply without burning up. A typical efficiency curve

shows that peak efficiency occurs near 30% of this maxi-

mum current. If the load current will vary around the

efficiency peak and will spend relatively little time at the

maximumload, choosingcomponentssothattheaverage

load is at the efficiency peak is a good idea. This puts the

maximum load well beyond the efficiency peak, but usu-

ally gives the greatest system efficiency over time, which

translates to the longest run time in a battery-powered

system. If the load is expected to be relatively constant at

the maximum level, the components should be chosen so

that this load lands at the peak efficiency point, well below

the maximum possible output of the converter.

Assuming the LTC1705 provides 90% efficiency at the

core and I/O channels, and 75% efficiency at the LDO, the

additional loads on the 5V and 3.3V supplies are:

1.3V: 19.5W/90% =21.67W

1.5V: 3W/90% =3.3W

6.6A from 3.3V

0.66A from 5V

0.152A from 3.3V

2.5V: 0.375W/75% =0.5W

24

LTC1705

U

W U U

APPLICATIO S I FOR ATIO

REGULATION OVER COMPONENT TOLERANCE/

TEMPERATURE

achieving optimum load regulation from the LTC1705. A

properly laid out LTC1705 circuit should move not more

than one to two millivolts at the output from zero to full

load.

DC Regulation Accuracy

The LTC1705 initial DC output accuracy depends mainly

on internal reference accuracy, op amp offset and internal

or external resistor accuracy. Two LTC1705 specs come

into play: V_SENSECvoltage and feedback voltage line regu-

lation. The V_SENSECvoltage spec is within ±1.25% for all

VID codes over the full temperature range, which encom-

passes reference accuracy, error amplifier offset and the

input resistor divider mismatch. The feedback voltage line

regulation spec adds an additional 0.1%/V term that

accounts for change in reference output with change in

input supply voltage. With a 5V supply, the errors contrib-

uted by the LTC1705 itself add up to less than 1.5% DC

error at the output.

Transient Response

Transient response is the other half of the regulation

equation. The LTC1705 can keep the DC output voltage

constant to within 1% when averaged over hundreds of

cycles. Over just a few cycles, however, the external

components conspire to limit the speed that the output

can move. Consider our typical 5V to 1.5V circuit, sub-

jected to a 1A to 5A load transient. Initially, the loop is in

regulation and the DC current in the output capacitor is

zero. Suddenly, an extra 4A start flowing out of the output

capacitor while the inductor is still supplying only 1A. This

sudden change will generate a (4A)(R_ESR)voltage step at

the output; with a typical 0.015Ω output capacitor ESR,

this is a 60mV or 4% (for a 1.5V output voltage) step at the

output!

AttheI/Oside, theoutputvoltagesettingresistors(R1and

R_Bin Figure 3) are the other major contributor to DC error.

At a typical 1.xV output voltage, the resistors are of

roughly the same value, which tends to halve their error

terms, improving accuracy. Still, using 1% resistors for

R1 and R_Bwill add 1% to the total output error budget.

Using0.1%resistorsinjustthosetwopositionscannearly

halve the DC output error for very little additional cost.

Very quickly, the feedback loop will realize that something

has changed and will move at the bandwidth allowed by

the external compensation network towards a new duty

cycle. If the bandwidth is set to 50kHz, the COMP pin will

get to 60% of the way to 90% duty cycle in 3µs. Now the

inductor is seeing 3.5V across itself for a large portion of

the cycle and its current will increase from 1A at a rate set

by di/dt = V/L. If the inductor value is 0.5µH, the peak di/dt

will be 3.5V/0.5µH or 7A/µs. Sometime in the next few

micro-seconds after the switch cycle begins, the inductor

current will have risen to the 5A level of the load current

andtheoutputvoltagewillstopdropping. Atthispoint, the

inductor current will rise somewhat above the level of the

outputcurrenttoreplenishthechargelostfromtheoutput

capacitor during the load transient. During the next couple

of cycles, the MIN comparator may trip on and off,

preventing the output from falling below its -5% threshold

until the time constant of the compensation loop runs out

and the main feedback amplifier regains control. With a

properly compensated loop, the entire recovery time will

be inside of 10µs.

Load Regulation

Load regulation is affected by feedback amplifier gain and

external ground drops in the feedback path. A full-range

load step might require a 10% duty cycle change to keep

the output constant, requiring the COMP pin to move

about 100mV. With amplifier gain at 85dB, this adds up to

only a 10µV shift at FB, negligible compared to the refer-

ence accuracy terms.

External ground drops aren’t so negligible. The LTC1705

can sense the positive end of the output voltage by

attaching the feedback resistor directly at the load, but it

cannot do the same with the ground lead. Just 0.001Ω of

resistanceinthegroundleadat15Aloadwillcausea15mV

error in the output voltage—as much as all the other DC

errors put together. Proper layout becomes essential to

25

LTC1705

U

TYPICAL APPLICATIO S

Most loads care only about the maximum deviation from

ideal, whichoccurssomewhereinthefirsttwocyclesafter

the load step hits. During this time, the output capacitor

does all the work until the inductor and control loop regain

control. The initial drop (or rise if the load steps down) is

entirelycontrolledbytheESRofthecapacitorandamounts

to most of the total voltage drop. To minimize this drop,

reduce the ESR as much as possible by choosing low ESR

capacitors and/or paralleling multiple capacitors at the

output. The capacitance value accounts for the rest of the

voltage drop until the inductor current rises. With most

output capacitors, several devices paralleled to get the

ESR down will have so much capacitance that this drop

term is negligible. Ceramic capacitors are an exception; a

small ceramic capacitor can have suitably low ESR with

relatively small values of capacitance, making this second

drop term significant.

doesn’t cause a bigger spike than the transient signal

beingmeasured.Conveniently,thetypicalprobetipground

clipisspacedjustrighttospantheleadsofatypicaloutput

capacitor.

Now that we know how to measure the signal, we need to

have something to measure. The ideal situation is to use

the actual load for the test and switch it on and off while

watching the output. If this isn’t convenient, a current step

generator is needed. This generator needs to be able to

turn on and off in nanoseconds to simulate a typical

switching logic load, so stray inductance and long clip

leads between the LTC1705 and the transient generator

must be minimized.

Figure 11 shows an example of a simple transient genera-

tor. Be sure to use a noninductive resistor as the load

element—many power resistors use an inductive spiral

pattern and are not suitable for use here. A simple solution

is to take ten 1/4W film resistors and wire them in parallel

togetthedesiredvalue.Thisgivesanoninductiveresistive

load which can dissipate 2.5W continuously or 50W if

pulsed with a 5% duty cycle, enough for most LTC1705

circuits. SoldertheMOSFETandtheresistor(s)ascloseto

the output of the LTC1705 circuit as possible and set up

thesignalgeneratortopulseata100Hzratewitha5%duty

cycle.ThispulsestheLTC1705with500µstransients10ms

apart, adequate for viewing the entire transient recovery

time for both positive and negative transitions while keep-

ing the load resistor cool.

Optimizing Loop Compensation

Loop compensation has a fundamental impact on tran-

sient recovery time, the time it takes the LTC1705 to

recoveraftertheoutputvoltagehasdroppedduetooutput

capacitor ESR. Optimizing loop compensation entails

maintaining the highest possible loop bandwidth while

ensuringloopstability.Thefeedbackcomponentselection

section describes in detail the techniques used to design

an optimized Type 3 feedback loop, appropriate for most

LTC1705 systems.

Measurement Techniques

Measuring transient response presents a challenge in two

respects: obtaining an accurate measurement and gener-

ating a suitable transient to use to test the circuit. Output

measurements should be taken with a scope probe di-

rectly across the output capacitor. Proper high frequency

probing techniques should be used. In particular, don’t

use the 6" ground lead that comes with the probe! Use an

adapter that fits on the tip of the probe and has a short

ground clip to ensure that inductance in the ground path

LTC1705

V

OUT

R

LOAD

IRFZ44 OR

EQUIVALENT

PULSE

GENERATOR

50Ω

0V TO 10V

100Hz, 5%

DUTY CYCLE

1705 F11

LOCATE CLOSE TO THE OUTPUT

Figure 11. Transient Load Generator

26

LTC1705

U

PACKAGE DESCRIPTIO

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

0.386 – 0.393*

(9.804 – 9.982)

0.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

0.229 – 0.244

(5.817 – 6.198)

0.150 – 0.157**

(3.810 – 3.988)

1

2

3

4

5

6

7

8

9

10 11 12 13 14

0.004 – 0.009

0.015 ± 0.004

(0.38 ± 0.10)

0.053 – 0.069

× 45°

(1.351 – 1.748)

(0.102 – 0.249)

0.0075 – 0.0098

(0.191 – 0.249)

0° – 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.008 – 0.012

(0.203 – 0.305)

0.0250

(0.635)

BSC

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

GN28 (SSOP) 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

27

LTC1705

U

TYPICAL APPLICATIO

Complete 2-Step Notebook Power Supply

V

IN

7V TO 20V

+

STDBY5V

C

0.1µF

IN

+

0.1µF

D2

22µF

50V

1µF

4.7µF

10Ω

50V

CMDSH-3

0.1µF

50V

D1

CMDSH-3

21

INTV

24

Q1

Q2

V

IN

CC

27

25

16

18

TG1

BOOST1

TG2

BOOST2

Q5

L1

2.9µH

L2

4.6µH

0.1µF

0.22µF

4mΩ

10mΩ

26

17

SW1

SW2

D5

MBRD

835L

D4

MBRS

130T3

10µF

23

2

19

14

13

Q4

Q3

BG1

BG2

6.3V

10Ω

1000pF

10Ω

1000pF

+

150µF

6.3V

×2

SENSE1

LTC1628

SENSE2

180µF

4V

V

3.3V

5A

OUT1

5V

4A

OUT2

3

22

4

–

SENSE2

105k

1%

10Ω

20

12

63.4k

1%

100pF

EXTV

PGND

100pF

CC

OSENSE1

RUN/SS1

V

OSENSE2

1

8

15

11

20k

1%

20k

1%

RUN/SS2

47pF

5V

47pF

I

TH2

TH1

3.3V

ENABLE

180pF

330pF

33k

9

33k

180pF

330pF

ENABLE

0.1µF

SGND

5

7

28

10

6

FREQSET

FCB

FLTCPL

3.3V

OUT

STDBY3.3V

0.1µF

STDBYMD

STBYMD

L5, 0.33µH

D03316P-331HC

0.01µF

+

150µF

6.3V

×2

1µF

10µF

10Ω

1µF

D7

MBR

5k

D6

MBR0520LT1

2

22

19

0520LT1

QT1A

QT1B

PV

CC

PGOOD

V

CC

TGIO

5

3

26

27

TGC

QT2

BOOSTC

BOOSTIO

L3

L4

1µF

0.68µH

1µF

3µH

6

4

25

28

SWC

SWIO

QB1A

QB1B

D5

V

+

100µF

4V

V

1.5V

3A

OUTC

+

180µF

4V

×6

OUTIO

MBRD

835L

0.9V TO 2V

1µF

QB2

BGC

BGIO

1µF

15A

×2

16k

27k

8

LTC1705

1

I

MAXIO

MAXC

13

11k

SENSEC

FBC

21

COMPIO

FBIO

10k

1%

11

8.87k

1%

100pF

2200pF

1.8k

20

24

1800pF

330pF

1800pF

10

9

COMPC

RUN/SS

11k

V

INCLK

+

10µF

10V

0.1µF

7

Q1, Q2, Q3: IRF7805

Q4, Q5: IRF7807

L1: ETQP6F2R9L

L2: ETQP6F4R6H

QT1A, QT1B, QB1A, QB1B: FAIRCHILD FDS6670A

QT2, QB2: NDS8926

COREENABLE

PGND

GND

12

V

OUTCLK

2.5V

150mA

23

V

OUTCLK

+

VID0 VID1 VID2 VID3 VID4

14 15 16 17 18

VID0 VID1 VID2 VID3 VID4

10µF

10V

1µF

L3: SUMIDA CEP125-4712-T007

L4: SUMIDA CDRH6D28-3R0

1705 TA02

RELATED PARTS

PART NUMBER

LTC1628/LTC1628-PG Dual High Efficiency 2-Phase Synchronous Step-Down Controller Constant Frequency, Standby 5V and 3.3V LDOs,

3.5V ≤ V ≤ 36V

DESCRIPTION

COMMENTS

IN

LTC1703

LTC1708

LTC1736

Dual 550kHz Synchronous 2-Phase Switching Regulator

Controller with VID

Mobile VID Control with 25MHz GBW Voltage Mode, V ≤ 7V

IN

Dual, 2-Phase Synchronous Step-Down Controller with 5-Bit VID Mobile CPU VID, Dual Output 3.5V ≤ V ≤ 36V,

IN

Minimum C and C

IN

OUT

Synchronous Step-Down Controller with 5-Bit VID Control

Output Fault Protection, Power Good Output, 3.5V to 36V Input

1705fa LT/TP 0801 1.5K REV A • PRINTED IN USA

28 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

LINEAR TECHNOLOGY CORPORATION 2001

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1705EGN
厂家：	Linear
描述：	Dual 550kHz Synchronous Switching Regulator Controller with 5-Bit VID and 150mA LDO 双路550kHz的同步开关稳压控制器5位VID到150mA LDO 开关控制器
文件：	总28页 (文件大小：311K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1705EGN [Linear]

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