LTC2140-12_技术文档

Electrical Specifications Subject to Change

LTC2142-12/

LTC2141-12/LTC2140-12

12-Bit, 65Msps/

40Msps/25Msps Low Power

Dual ADCs

FEATURES

DESCRIPTION

TheLTC^®2142-12/LTC2141-12/LTC2140-12are2-channel

simultaneous sampling 12-bit A/D converters designed

for digitizing high frequency, wide dynamic range signals.

They are perfect for demanding communications applica-

tions with AC performance that includes 70.8dB SNR and

89dB spurious free dynamic range (SFDR). Ultralow jitter

n

2-Channel Simultaneously Sampling ADC

n

70.8dB SNR

n

89dB SFDR

n

Low Power: 92mW/65mW/48mW Total

46mW/33mW/24mW per Channel

n

Single 1.8V Supply

n

of0.08ps

allowsundersamplingofIFfrequencieswith

CMOS, DDR CMOS, or DDR LVDS Outputs

RMS

n

excellent noise performance.

Selectable Input Ranges: 1V to 2V

P-P

n

800MHz Full Power Bandwidth S/H

Optional Data Output Randomizer

Optional Clock Duty Cycle Stabilizer

Shutdown and Nap Modes

Serial SPI Port for Configuration

64-Pin (9mm × 9mm) QFN Package

DC specs include 0.3LSB INL (typ), 0.1LSB DNL (typ)

and no missing codes over temperature. The transition

noise is 0.3LSB

.

RMS

The digital outputs can be either full rate CMOS, double

data rate CMOS, or double data rate LVDS. A separate

output power supply allows the CMOS output swing to

range from 1.2V to 1.8V.

APPLICATIONS

+

–

The ENC and ENC inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL, or

CMOS inputs. An optional clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

n

Communications

n

Cellular Base Stations

n

Software Defined Radios

n

Portable Medical Imaging

n

Multi-Channel Data Acquisition

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

Nondestructive Testing

TYPICAL APPLICATION

1.8V

OV

2-Tone FFT, f_IN= 70MHz and 69MHz

V

DD

0

–10

–20

CH 1

ANALOG

INPUT

12-BIT

D1_11

–30

•

S/H

ADC CORE

•

–40

–50

–60

–70

CMOS

OR

D1_0

LVDS

D2_11

OUTPUTS

•

OUTPUT

DRIVERS

CH 2

ANALOG

INPUT

–80

–90

12-BIT

ADC CORE

D2_0

–100

–110

–120

65MHz

CLOCK

CONTROL

0

20

10

FREQUENCY (MHz)

30

21821012 TA01b

21421012 TA01a

GND

OGND

21421012p

1

LTC2142-12/

LTC2141-12/LTC2140-12

ABSOLUTE MAXIMUM RATINGS ^{(Notes 1, 2)}

Supply Voltages (V , OV )....................... –0.3V to 2V

Digital Output Voltage................ –0.3V to (OV + 0.3V)

DD

+

–

Analog Input Voltage (A , A

,

Operating Temperature Range

IN

PAR/SER, SENSE) (Note 3).......... –0.3V to (V + 0.2V)

LTC2142C, LTC2141C, LTC2140C............. 0°C to 70°C

LTC2142I, LTC2141I, LTC2140I ............–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

DD

+

–

Digital Input Voltage (ENC , ENC , CS,

SDI, SCK) (Note 4).................................... –0.3V to 3.9V

SDO (Note 4)............................................. –0.3V to 3.9V

PIN CONFIGURATIONS

FULL RATE CMOS OUTPUT MODE

TOP VIEW

DOUBLE DATA RATE CMOS OUTPUT MODE

TOP VIEW

V

1

2

48 D1_0_1

47 DNC

46 DNC

45 DNC

44 DNC

43 DNC

DD

V

1

2

48 D1_1

47 D1_0

46 DNC

45 DNC

44 DNC

43 DNC

DD

V

CM1

V

CM1

GND 3

+

A

4

5

IN1

A

4

5

IN1

–

IN1

GND 6

REFH 7

REFL 8

REFH 9

REFL 10

GND 6

REFH 7

REFL 8

REFH 9

REFL 10

42 OV

DD

42 OV

DD

41 OGND

40 CLKOUT

39 CLKOUT

38 D2_10_11

37 DNC

36 D2_8_9

35 DNC

65

GND

41 OGND

40 CLKOUT

39 CLKOUT

38 D2_11

37 D2_10

36 D2_9

35 D2_8

34 D2_7

33 D2_6

65

GND

+

–

+

–

PAR/SER 11

+

A

12

13

IN2

GND 14

A

12

13

IN2

GND 14

–

V

15

16

34 D2_6_7

33 DNC

CM2

V

15

16

CM2

V

DD

V

DD

UP PACKAGE

64-LEAD (9mm s 9mm) PLASTIC QFN

UP PACKAGE

64-LEAD (9mm × 9mm) PLASTIC QFN

T

= 150°C, θ = 29°C/W

JA

T

= 150°C, θ = 29°C/W

JA

JMAX

EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB

DOUBLE DATA RATE LVDS OUTPUT MODE

21421012p

2

LTC2142-12/

LTC2141-12/LTC2140-12

PIN CONFIGURATIONS

DOUBLE DATA RATE LVDS OUTPUT MODE

TOP VIEW

+

V

1

2

48 D1_0_1

DD

–

V

47 D1_0_1

CM1

GND 3

46 DNC

45 DNC

44 DNC

43 DNC

+

A

4

5

IN1

–

IN1

GND 6

REFH 7

REFL 8

REFH 9

REFL 10

42 OV

DD

41 OGND

40 CLKOUT

39 CLKOUT

65

GND

+

–

+

–

PAR/SER 11

38 D2_10_11

37 D2_10_11

+

A

12

13

IN2

–

+

36 D2_8_9

IN2

–

GND 14

35 D2_8_9

34 D2_6_7

+

V

15

16

CM2

–

33 D2_6_7

DD

UP PACKAGE

64-LEAD (9mm s 9mm) PLASTIC QFN

T

= 150°C, θ = 29°C/W

JA

JMAX

EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC2142CUP-12#PBF

LTC2142IUP-12#PBF

LTC2141CUP-12#PBF

LTC2141IUP-12#PBF

LTC2140CUP-12#PBF

LTC2140IUP-12#PBF

TAPE AND REEL

PART MARKING*

LTC2142UP-12

LTC2141UP-12

LTC2140UP-12

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC2142CUP-12#TRPBF

LTC2142IUP-12#TRPBF

LTC2141CUP-12#TRPBF

LTC2141IUP-12#TRPBF

LTC2140CUP-12#TRPBF

LTC2140IUP-12#TRPBF

64-Lead (9mm × 9mm) Plastic QFN

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

21421012p

3

LTC2142-12/

LTC2141-12/LTC2140-12

CONVERTER CHARACTERISTICS _{The l denotes the specifications which apply over the full operating}

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

LTC2142-12

TYP

LTC2141-12

TYP

LTC2140-12

TYP MAX

PARAMETER

CONDITIONS

MIN

12

MAX

MIN

12

MAX

MIN

12

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

Differential Analog Input (Note 6)

Differential Analog Input

(Note 7)

TBD

–1

0.3

0.1

1.5

TBD

1

TBD

–1

0.3

0.1

1.5

TBD

1

TBD

–1

0.3 TBD

LSB

mV

0.1

1.5

1

9

–9

9

–9

9

–9

Gain Error

Internal Reference

External Reference

1.5

–0.6

1.5

–0.6

1.5

–0.6

%FS

l

–2.1

0.9

–2.1

0.9

–2.1

0.9

Offset Drift

10

μV/°C

Full-Scale Drift

Internal Reference

External Reference

30

10

30

10

30

10

ppm/°C

Gain Matching

Offset Matching

Transition Noise

0.3

1.5

0.3

1.5

0.3

1.5

0.3

%FS

mV

LSB

RMS

ANALOG INPUT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

1.7V < V < 1.9V

MIN

TYP

MAX

UNITS

+

–

l

V

Analog Input Range (A – A

)

1 to 2

V

P-P

IN

DD

+

–

Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)

0.7

V

CM

1.25

V

IN(CM)

SENSE

INCM

IN

External Voltage Reference Applied to SENSE External Reference Mode

0.625

1.250

1.300

V

I

Analog Input Common Mode Current

Per Pin, 65Msps

Per Pin, 40Msps

Per Pin, 25Msps

81

50

31

μA

+

–

l

I

t

Analog Input Leakage Current (No Encode)

PAR/SER Input Leakage Current

0 < A , A < V

–1

–3

–6

1

3

6

μA

ns

IN1

IN

DD

0 < PAR/SER < V

IN2

DD

SENSE Input Leakage Current

0.625 < SENSE < 1.3V

IN3

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Jitter

0

AP

Single-Ended Encode

Differential Encode

0.08

0.10

ps

JITTER

RMS

CMRR

BW-3B

Analog Input Common Mode Rejection Ratio

Full-Power Bandwidth

80

dB

Figure 6 Test Circuit

800

MHz

21421012p

4

LTC2142-12/

LTC2141-12/LTC2140-12

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. A_IN= –1dBFS. (Note 5)

LTC2142-12

TYP

LTC2141-12

TYP

LTC2140-12

TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

SNR

Signal-to-Noise Ratio

5MHz Input

70.8

70.7

70.5

70.4

70.2

71

dBFS

l

30MHz Input

70MHz Input

140MHz Input

TBD

70.9

70.7

SFDR

Spurious Free Dynamic Range 5MHz Input

2nd or 3rd Harmonic

89

88

84

89

88

84

89

88

84

dBFS

30MHz Input

70MHz Input

140MHz Input

TBD

Spurious Free Dynamic Range 5MHz Input

4th Harmonic or Higher

95

dBFS

30MHz Input

70MHz Input

140MHz Input

S/(N+D) Signal-to-Noise Plus

Distortion Ratio

5MHz Input

70.7

70.6

70.2

70.4

70.3

69.9

70.9

70.8

70.4

dBFS

30MHz Input

70MHz Input

140MHz Input

Crosstalk

10MHz Input

–110

dBc

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

PARAMETER

CONDITIONS

= 0

MIN

TYP

0.5 • V

25

MAX

UNITS

V

CM

V

CM

V

CM

V

REF

V

REF

V

REF

V

REF

Output Voltage

I

0.5 • V – 25mV

0.5 • V + 25mV

OUT

DD

Output Temperature Drift

Output Resistance

Output Voltage

ppm/°C

Ω

–600μA < I

< 1mA

4

OUT

I

= 0

1.225

1.250

25

1.275

V

OUT

Output Temperature Drift

Output Resistance

Line Regulation

ppm/°C

Ω

–400μA < I

7

OUT

1.7V < V < 1.9V

0.6

mV/V

DD

21421012p

5

LTC2142-12/

LTC2141-12/LTC2140-12

DIGITAL INPUTS AND OUTPUTS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

ENCODE INPUTS (ENC , ENC )

–

Differential Encode Mode (ENC Not Tied to GND)

l

V

Differential Input Voltage

(Note 8)

0.2

V

ID

Common Mode Input Voltage

Internally Set

Externally Set (Note 8)

1.2

V

ICM

l

1.1

0.2

1.6

3.6

+

–

V

IN

Input Voltage Range

Input Resistance

ENC , ENC to GND

(See Figure 10)

(Note 8)

V

kΩ

pF

R

10

IN

C

Input Capacitance

3.5

–

Single-Ended Encode Mode (ENC Tied to GND)

l

V

High Level Input Voltage

Low Level Input Voltage

Input Voltage Range

Input Resistance

V

= 1.8V

1.2

0

V

IH

IL

IN

DD

0.6

3.6

DD

+

ENC to GND

(See Figure 11)

(Note 8)

V

R

30

kΩ

pF

IN

C

Input Capacitance

3.5

DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)

l

V

High Level Input Voltage

Low Level Input Voltage

Input Current

V

= 1.8V

1.3

V

IH

IL

DD

IN

l

= 1.8V

0.6

10

I

= 0V to 3.6V

–10

μA

pF

IN

C

Input Capacitance

(Note 8)

3

200

3

IN

SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)

R

Logic Low Output Resistance to GND

Logic High Output Leakage Current

Output Capacitance

V

DD

= 1.8V, SDO = 0V

Ω

μA

pF

OL

l

I

OH

SDO = 0V to 3.6V

(Note 8)

–10

10

C

OUT

DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)

OV = 1.8V

DD

l

V

High Level Output Voltage

Low Level Output Voltage

I = –500μA

1.750

1.790

0.010

V

OH

OL

O

I = 500μA

O

0.050

OV = 1.5V

DD

V

OH

V

OL

High Level Output Voltage

Low Level Output Voltage

I = –500μA

1.488

0.010

V

O

I = 500μA

O

OV = 1.2V

DD

V

OH

V

OL

High Level Output Voltage

Low Level Output Voltage

I = –500μA

1.185

0.010

V

O

I = 500μA

O

DIGITAL DATA OUTPUTS (LVDS MODE)

l

V

Differential Output Voltage

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

350

175

454

mV

OD

V

OS

Common Mode Output Voltage

On-Chip Termination Resistance

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

1.375

V

R

Termination Enabled, OV = 1.8V

100

Ω

TERM

DD

21421012p

6

LTC2142-12/

LTC2141-12/LTC2140-12

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 9)

LTC2142-12

TYP

LTC2141-12

TYP

LTC2140-12

TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

CMOS Output Modes: Full Data Rate and Double Data Rate

l

V

Analog Supply Voltage (Note 10)

Output Supply Voltage (Note 10)

Analog Supply Current DC Input

1.7

1.1

1.8

1.9

1.7

1.1

1.8

1.9

1.7

1.1

1.8

1.9

V

DD

OV

DD

I

50.9

51.3

TBD

35.9

36.2

TBD

26.9 TBD

27

mA

VDD

Sine Wave Input

I

Digital Supply Current Sine Wave Input, OV = 1.2V

3.8

2.4

1.5

mA

OVDD

DD

l

P

Power Dissipation

DC Input

Sine Wave Input, OV = 1.2V

91.6

96.9

TBD

64.6

68

TBD

48.4 TBD

50.4

mW

DISS

DD

LVDS Output Mode

Analog Supply Voltage (Note 10)

l

V

DD

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

V

OV

DD

Output Supply Voltage (Note 10)

I

Analog Supply Current Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

52.6

53.8

37.4

38.7

28.3

mA

VDD

l

TBD

29.5 TBD

I

Digital Supply Current Sine Input, 1.75mA Mode

30

57.4

29.6

57.1

29.3

56.8 TBD

mA

OVDD

(0V = 1.8V)

Sine Input, 3.5mA Mode

DD

P

Power Dissipation

Sine Input, 1.75mA Mode

Sine Input, 3.5mA Mode

149

200

121

172

104

155

mW

DISS

TBD

All Output Modes

P

Sleep Mode Power

Nap Mode Power

1

mW

SLEEP

NAP

10

20

10

20

10

20

Power Increase with Differential Encode Mode Enabled

(No Increase for Nap or Sleep Modes)

DIFFCLK

TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

LTC2142-12

TYP

LTC2141-12

TYP

LTC2140-12

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

TYP MAX UNITS

l

f

t

Sampling Frequency

(Note 10)

1

65

1

40

1

25

MHz

S

L

l

ENC Low Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

2

7.69

500 11.88 12.5

500 12.5

500

19

2

20

500

ns

2

l

t

ENC High Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

2

7.69

500 11.88 12.5

500

19

2

20

500

ns

H

500

2

12.5

Sample-and-Hold

Acquisition Delay Time

0

ns

AP

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)

l

t

ENC to Data Delay

ENC to CLKOUT Delay

DATA to CLKOUT Skew

Pipeline Latency

C = 5pF (Note 8)

1.1

1

1.7

1.4

0.3

3.1

2.6

0.6

ns

D

L

C = 5pF (Note 8)

L

C

t – t (Note 8)

0

SKEW

D

C

Full Data Rate Mode

Double Data Rate Mode

6

6.5

Cycles

21421012p

7

LTC2142-12/

LTC2141-12/LTC2140-12

TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Data Outputs (LVDS Mode)

l

t

ENC to Data Delay

ENC to CLKOUT Delay

DATA to CLKOUT Skew

Pipeline Latency

C = 5pF (Note 8)

1.1

1

1.8

1.5

0.3

6.5

3.2

2.7

0.6

ns

D

L

C = 5pF (Note 8)

L

C

t – t (Note 8)

0

ns

SKEW

D

C

Cycles

SPI Port Timing (Note 8)

l

t

SCK Period

Write Mode

40

ns

SCK

Readback Mode, C

= 20pF, R

= 2k

250

SDO

PULLUP

l

t

CS to SCK Setup Time

SCK to CS Setup Time

SDI Setup Time

5

ns

S

H

DS

DH

DO

SDI Hold Time

SCK Falling to SDO Valid

Readback Mode, C

125

SDO

PULLUP

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND with GND and OGND

shorted (unless otherwise noted).

Note 6: Integral nonlinearity is defined as the deviation of a code from a

best fit straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 7: Offset error is the offset voltage measured from –0.5 LSB when

the output code flickers between 0000 0000 0000 and 1111 1111 1111 in

2’s complement output mode.

Note 3: When these pin voltages are taken below GND or above V , they

Note 8: Guaranteed by design, not subject to test.

DD

will be clamped by internal diodes. This product can handle input currents

Note 9: V = 1.8V, f

= 65MHz (LTC2142), 40MHz (LTC2141), or

DD

SAMPLE

+

of greater than 100mA below GND or above V without latchup.

DD

25MHz (LTC2140), CMOS outputs, ENC = single-ended 1.8V square

–

Note 4: When these pin voltages are taken below GND they will be

wave, ENC = 0V, input range = 2V with differential drive, 5pF load on

P-P

clamped by internal diodes. When these pin voltages are taken above V

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

each digital output unless otherwise noted. The supply current and power

dissipation specifications are totals for the entire IC, not per channel.

Note 10: Recommended operating conditions.

DD

Note 5: V = OV = 1.8V, f = 65MHz (LTC2142), 40MHz

(LTC2141), or 25MHz (LTC2140), LVDS outputs, differential ENC /ENC =

DD

SAMPLE

+

–

2V sine wave, input range = 2V with differential drive, unless

P-P

otherwise noted.

21421012p

8

LTC2142-12/

LTC2141-12/LTC2140-12

TIMING DIAGRAMS

Full Rate CMOS Output Mode Timing

All Outputs Are Single-Ended and Have CMOS Levels

t

AP

CH 1

ANALOG

INPUT

A + 4

B + 4

A + 2

B + 2

A

B

A + 3

B + 3

t

AP

A + 1

B + 1

CH 2

ANALOG

INPUT

t

H

t

L

–

ENC

+

ENC

t

D

A – 6

A – 5

B – 5

A – 4

B – 4

A – 3

B – 3

A – 2

B – 2

D1_0 - D1_11, OF1

D2_0 - D2_11, OF2

B – 6

C

+

CLKOUT

–

CLKOUT

21421012 TD01

Double Data Rate CMOS Output Mode Timing

All Outputs Are Single-Ended and Have CMOS Levels

t

AP

CH 1

ANALOG

INPUT

A + 4

A + 2

B + 2

A

B

A + 3

B + 3

t

AP

A + 1

B + 1

CH 2

ANALOG

INPUT

B + 4

t

H

t

L

–

ENC

+

ENC

t

D

t

D

BIT 0

A-6

BIT 1

A-6

BIT 0

A-5

BIT 1

A-5

BIT 0

A-4

BIT 1

A-4

BIT 0

A-3

BIT 1

A-3

BIT 0

A-2

D1_0_1

•

BIT 10

A-6

BIT 11 BIT 10

BIT 11

A-5

BIT 10

A-4

BIT 11

A-4

BIT 10

A-3

BIT 11

A-3

BIT 10

A-2

D1_10_11

A-6

A-5

BIT 0

B-6

BIT 1

B-6

BIT 0

B-5

BIT 1

B-5

BIT 0

B-4

BIT 1

B-4

BIT 0

B-3

BIT 1

B-3

BIT 0

B-2

D2_0_1

•

BIT 10

B-6

BIT 11 BIT 10

BIT 11

B-5

BIT 10

B-4

BIT 11

B-4

BIT 10

B-3

BIT 11

B-3

BIT 10

B-2

D2_10_11

B-6

B-5

OF

B-6

OF

A-6

OF

B-5

OF

A-5

OF

B-4

OF

A-4

OF

B-3

OF

A-3

OF

B-2

OF2_1

t

C

t

C

+

CLKOUT

–

CLKOUT

21421012 TD02

21421012p

9

LTC2142-12/

LTC2141-12/LTC2140-12

TIMING DIAGRAMS

Double Data Rate LVDS Output Mode Timing

All Outputs Are Differential and Have LVDS Levels

t

AP

CH 1

ANALOG

INPUT

A + 4

B + 4

A + 2

B + 2

A

B

A + 3

B + 3

t

A + 1

B + 1

CH 2

ANALOG

INPUT

t

H

t

L

–

ENC

+

ENC

t

D

t

D

+

D1_0_1

BIT 0

A-6

BIT 1

A-6

BIT 0

A-5

BIT 1

A-5

BIT 0

A-4

BIT 1

BIT 0

A-3

BIT 1

BIT 0

A-2

A-4

A-3

–

D1_0_1

•

+

D1_10_11

BIT 10

A-6

BIT 11 BIT 10

A-6

BIT 11

A-5

BIT 10

A-4

BIT 11

A-4

BIT 10

A-3

BIT 11

A-3

BIT 10

A-2

A-5

–

D1_10_11

+

D2_0_1

BIT 0

B-6

BIT 1

B-6

BIT 0

B-5

BIT 1

B-5

BIT 0

B-4

BIT 1

B-4

BIT 0

B-3

BIT 1

B-3

BIT 0

B-2

–

D2_0_1

•

+

D2_10_11

BIT 10

B-6

BIT 11 BIT 10

B-6

BIT 11

B-5

BIT 10

B-4

BIT 11

B-4

BIT 10

B-3

BIT 11

B-3

BIT 10

B-2

B-5

–

D2_10_11

+

OF2_1

OF

B-6

OF

A-6

OF

B-5

OF

A-5

OF

B-4

OF

A-4

OF

B-3

OF

A-3

OF

B-2

–

OF2_1

t

C

t

C

+

CLKOUT

–

CLKOUT

21421012 TD03

SPI Port Timing (Readback Mode)

t

DS

t

DH

t

H

S

SCK

CS

SCK

t

DO

SDI

A6

A5

A4

A3

A2

A1

A0

XX

D6

XX

D5

XX

D4

XX

D3

XX

D2

XX

D1

XX

R/W

SDO

D7

D0

HIGH IMPEDANCE

SPI Port Timing (Write Mode)

CS

SCK

SDI

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

SDO

21421012 TD04

HIGH IMPEDANCE

21421012p

10

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2142-12: Integral

Non-Linearity (INL)

LTC2142-12: Differential

Non-Linearity (DNL)

LTC2142-12: 64k Point FFT, f_IN

5MHz, –1dBFS, 65Msps

=

1.0

0.8

1.0

0.8

0

–10

–20

–30

–40

–50

–60

–70

0.6

0.4

0.2

0.0

0

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

–80

–90

–100

–110

–120

–0.4

–0.6

–0.8

–1.0

0

20

10

FREQUENCY (MHz)

30

0

2048

3072

4096

0

2048

3072

4096

1024

OUTPUT CODE

21421012 G01

21421012 G02

21421012 G03

LTC2142-12: 64k Point FFT,

f_IN= 30MHz, –1dBFS, 65Msps

LTC2142-12: 64k Point FFT,

f_IN= 70MHz, –1dBFS, 65Msps

LTC2142-12: 64k Point FFT,

f_IN= 140MHz, –1dBFS, 65Msps

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–80

–90

–80

–90

–100

–110

–120

–100

–110

–120

–100

–110

–120

0

20

10

FREQUENCY (MHz)

30

0

20

10

FREQUENCY (MHz)

30

0

20

10

FREQUENCY (MHz)

30

21421012 G05

21421012 G06

21421012 G04

LTC2142-12: 64k Point 2-Tone

FF

T

,

f

_IN

= 69MHz

,

70MHz

,

–7dBFS, 65Msps

LTC2142-12: SNR vs Input

LTC2142-12: Shorted Input

Histogram

Frequency, –1dBFS, 65Msps,

2V Range

0

–10

–20

–30

–40

–50

–60

–70

72

71

70

69

68

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

SINGLE-ENDED

ENCODE

DIFFERENTIAL

ENCODE

–80

–90

–100

–110

–120

0

20

10

FREQUENCY (MHz)

30

2043

2044

2045

2046

2047

0

50

100

150

200

250

300

INPUT FREQUENCY (MHz)

OUTPUT CODE

21421012 G07

21421012 G09

21421012 G08

21421012p

11

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2142-12: 2nd, 3rd Harmonic

vs Input Frequency, –1dBFS,

65Msps, 2V Range

LTC2142-12: 2nd, 3rd Harmonic

vs Input Frequency, –1dBFS,

65Msps, 1V Range

LTC2142-12: SFDR vs Input Level,

f_IN= 70MHz, 65Msps, 2V Range

100

95

90

85

80

75

70

65

100

95

90

85

80

75

70

65

110

100

90

80

70

60

50

40

30

20

10

0

dBFS

3RD

2ND

dBc

2ND

0

50

100

150

200

250

300

0

50

100

150

200

250

300

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

21421012 G12

0

INPUT FREQUENCY (MHz)

21421012 G10

21421012 G11

LTC2142-12: I_VDD

LTC2142-12: IO_VDD

vs Sample Rate, 5MHz, –1dBFS,

Sine Wave on Each Channel

vs Sample Rate, 5MHz, –1dBFS

LTC2142-12: SNR

vs SENSE, f_IN= 5MHz, –1dBFS

Sine Wave Input on Each Channel

55

50

45

40

35

70

60

50

40

30

20

10

0

72

71

70

69

68

67

66

3.5mA LVDS

LVDS OUTPUTS

1.75mA LVDS

CMOS OUTPUTS

1.8V CMOS

0

10

20

30

40

50

60

0

10

20

30

40

50

60

0.6 0.7 0.8 0.9

1

1.1 1.2 1.3

SAMPLE RATE (Msps)

SENSE PIN (V)

21421012 G13

21421012 G14

21421012 G15

LTC2141-12: Integral

Non-Linearity (INL)

LTC2141-12: Differential

Non-Linearity (DNL)

LTC2141-12: 64k Point FFT,

f_IN= 5MHz, –1dBFS, 40Msps

1.0

0.8

1.0

0.8

0.6

0

–10

–20

–30

–40

–50

–60

–70

0.6

0.4

0.2

0

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–80

–90

–100

–110

–120

0

2048

3072

4096

0

2048

3072

4096

1024

0

5

10

15

20

OUTPUT CODE

FREQUENCY (MHz)

21421012 G16

21421012 G17

21421012 G18

21421012p

12

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2141-12: 64k Point FFT,

f_IN= 140MHz, –1dBFS, 40Msps

LTC2141-12: 64k Point FFT,

_IN= 30MHz, –1dBFS, 40Msps

LTC2141-12: 64k Point FFT,

f_IN= 70MHz, –1dBFS, 40Msps

f

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–80

–90

–80

–90

–100

–110

–120

–100

–110

–120

–100

–110

–120

0

5

10

15

20

0

5

10

15

20

0

5

10

15

20

FREQUENCY (MHz)

21421012 G19

21421012 G20

21421012 G21

LTC2141-12: 64k Point 2-Tone

FFT, f_IN= 69MHz, 70MHz,

–7dBFS, 40Msps

LTC2141-12: SNR

vs Input Frequency, –1dBFS,

40Msps, 2V Range

LTC2141-12: Shorted Input

Histogram

0

–10

–20

–30

–40

–50

–60

–70

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

72

71

70

69

68

SINGLE-ENDED

ENCODE

DIFFERENTIAL

ENCODE

–80

–90

–100

–110

–120

2043

2044

2045

OUTPUT CODE

2046

2047

0

5

10

15

20

0

50

100

INPUT FREQUENCY (MHz)

21421012 G24

150

200

250

300

FREQUENCY (MHz)

21421012 G22

21421012 G23

LTC2141-12: 2nd, 3rd Harmonic

vs Input Frequency, –1dBFS,

40Msps, 2V Range

LTC2141-12: 2nd, 3rd Harmonic

vs Input Frequency, –1dBFS,

40Msps, 1V Range

LTC2141-12: SFDR vs Input Level,

f_IN= 70MHz, 40Msps, 2V Range

100

95

90

85

80

75

70

65

100

95

90

85

80

75

70

65

110

100

90

80

70

60

50

40

30

20

10

0

dBFS

dBc

3RD

2ND

0

50

100

150

200

250

300

0

50

100

150

200

250

300

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

21421012 G27

0

INPUT FREQUENCY (MHz)

21421012 G25

21421012 G26

21421012p

13

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2141-12: I_VDDvs Sample

Rate, 5MHz, –1dBFS Sine Wave

Input on Each Channel

LTC2141-12: IO_VDDvs Sample

Rate, 5MHz, –1dBFS, Sine Wave

Input on Each Channel

LTC2141-12: SNR vs SENSE,

f_IN= 5MHz, –1dBFS

40

35

30

25

70

60

50

40

30

20

10

0

72

71

70

69

68

67

66

3.5mA LVDS

1.75mA LVDS

1.8V CMOS

LVDS OUTPUTS

CMOS OUTPUTS

0.6 0.7 0.8 0.9

1

1.1 1.2 1.3

0

10

20

30

40

0

10

20

30

40

SENSE PIN (V)

SAMPLE RATE (Msps)

21421012 G30

21421012 G28

21421012 G29

LTC2140-12: Integral

Non-Linearity (INL)

LTC2140-12: Differential

Non-Linearity (DNL)

LTC2140-12: 64k Point FFT,

f_IN= 5MHz, –1dBFS, 25Msps

1.0

0.8

0.6

1.0

0.8

0

–10

–20

–30

–40

–50

–60

–70

0.6

0.4

0.2

0

0.4

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–80

–90

–100

–110

–120

0

2048

3072

4096

0

2048

3072

4096

1024

0

5

10

OUTPUT CODE

FREQUENCY (MHz)

21421012 G32

21421012 G31

21421012 G33

LTC2140-12: 64k Point FFT,

f_IN= 30MHz, –1dBFS, 25Msps

LTC2140-12: 64k Point FFT,

f_IN= 70MHz, –1dBFS, 25Msps

L

T

C2140-12: 64k Point FF

T

,

f_IN= 140MHz, –1dBFS, 25Msps

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–80

–90

–80

–90

–100

–110

–120

–100

–110

–120

–100

–110

–120

0

5

10

0

5

10

0

5

10

FREQUENCY (MHz)

21421012 G34

21421012 G35

21421012 G36

21421012p

14

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2140-12: 64k Point 2-Tone FFT,

LTC2140-12: SNR vs Input

f_IN= 69MHz, 70MHz,

–7dBFS, 25Msps

LTC2140-12: Shorted Input

Histogram

Frequency, –1dBFS, 25Msps,

2V Range

0

–10

–20

–30

–40

–50

–60

–70

72

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

SINGLE-ENDED

ENCODE

71

70

69

68

DIFFERENTIAL

ENCODE

–80

–90

–100

–110

–120

0

5

10

2050

2051

2052

2053

2054

0

50

100

150

200

250

300

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

OUTPUT CODE

21421012 G37

21421012 G39

21421012 G38

LTC2140-12: 2nd, 3rd Harmonic

vs Input Frequency, –1dBFS,

25Msps, 2V Range

LTC2140-12: 2nd, 3rd Harmonic

vs Input Frequency, –1dBFS,

25Msps, 1V Range

LTC2140-12: SFDR vs Input Level,

f_IN= 70MHz, 25Msps, 2V Range

100

95

90

85

80

75

70

65

100

95

90

85

80

75

70

65

110

100

90

80

70

60

50

40

30

20

10

0

dBFS

dBc

3RD

2ND

0

50

100

150

200

250

300

0

50

100

150

200

250

300

–80 –70 –60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

21421012 G42

0

INPUT FREQUENCY (MHz)

21421012 G40

21421012 G41

LTC2140-12: I_VDDvs Sample

Rate, 5MHz, –1dBFS Sine Wave

Input on Each Channel

LTC2140-12: IO_VDDvs Sample

Rate, 5MHz, –1dBFS, Sine Wave

on Each Input

LTC2140-12: SNR vs SENSE,

f_IN= 5MHz, –1dBFS

30

28

26

24

22

20

60

50

40

30

20

10

0

72

71

70

69

68

67

66

3.5mA LVDS

LVDS OUTPUTS

1.75mA LVDS

CMOS OUTPUTS

1.8V CMOS

0.6 0.7 0.8 0.9

1

1.1 1.2 1.3

0

5

10

15

20

25

0

5

10

15

20

25

SENSE PIN (V)

SAMPLE RATE (Msps)

21421012 G45

21421012 G43

21421012 G44

21421012p

15

LTC2142-12/

LTC2141-12/LTC2140-12

PIN FUNCTIONS

PINS THAT ARE THE SAME FOR ALL DIGITAL

OUTPUT MODES

–

ENC (Pin 19): Encode Complement Input. Conversion

starts on the falling edge. Tie to GND for single-ended

encode mode.

V

(Pins 1, 16, 17, 64): Analog Power Supply, 1.7V to

DD

1.9V. Bypass to ground with 0.1μF ceramic capacitors.

Adjacent pins can share a bypass capacitor.

CS (Pin 20): In Serial Programming Mode, (PAR/SER =

0V), CS Is the Serial Interface Chip Select Input. When

CS is low, SCK is enabled for shifting data on SDI into

the mode control registers. In the parallel programming

V

(Pin2):CommonModeBiasOutput,NominallyEqual

CM1

to V /2. V

should be used to bias the common mode

DD

CM1

mode (PAR/SER = V ), CS controls the clock duty cycle

DD

of the analog inputs to channel 1. Bypass to ground with

a 0.1μF ceramic capacitor.

stabilizer (see Table 2). CS can be driven with 1.8V to

3.3V logic.

GND (Pins 3, 6, 14): ADC Power Ground.

SCK (Pin 21): In Serial Programming Mode, (PAR/SER =

+

A

(Pin 4): Channel 1 Positive Differential Analog

0V), SCK Is the Serial Interface Clock Input. In the parallel

IN1

Input.

programming mode (PAR/SER = V ), SCK controls the

DD

digital output mode (see Table 2). SCK can be driven with

1.8V to 3.3V logic.

–

A

(Pin 5): Channel 1 Negative Differential Analog

IN1

Input.

SDI (Pin 22): In Serial Programming Mode, (PAR/SER =

0V), SDI Is the Serial Interface Data Input. Data on SDI is

clocked into the mode control registers on the rising edge

of SCK. In the parallel programming mode (PAR/SER =

REFH (Pins 7, 9): ADC High Reference. See the Applica-

tions Information section for recommended bypassing

circuits for REFH and REFL.

REFL (Pins 8, 10): ADC Low Reference. See the Applica-

tions Information section for recommended bypassing

circuits for REFH and REFL.

V ), SDI can be used together with SDO to power down

DD

the part (see Table 2). SDI can be driven with 1.8V to

3.3V logic.

PAR/SER(Pin11):ProgrammingModeSelectionPin.Con-

necttogroundtoenabletheserialprogrammingmode.CS,

SCK, SDI, SDO become a serial interface that control the

OGND (Pin 41): Output Driver Ground. Must be shorted

to the ground plane by a very low inductance path. Use

multiple vias close to the pin.

A/Doperatingmodes.ConnecttoV toenabletheparallel

DD

OV (Pin 42): Output Driver Supply. Bypass to ground

DD

programming mode where CS, SCK, SDI, SDO become

parallel logic inputs that control a reduced set of the A/D

operating modes. PAR/SER should be connected directly

with a 0.1μF ceramic capacitor.

SDO (Pin 61): In Serial Programming Mode, (PAR/SER

= 0V), SDO Is the Optional Serial Interface Data Output.

Data on SDO is read back from the mode control regis-

ters and can be latched on the falling edge of SCK. SDO

is an open-drain NMOS output that requires an external

2k pull-up resistor to 1.8V – 3.3V. If read back from the

mode control registers is not needed, the pull-up resistor

is not necessary and SDO can be left unconnected. In the

to ground or V and not be driven by a logic signal.

DD

+

A

(Pin 12): Channel 2 Positive Differential Analog

(Pin 13): Channel 2 Negative Differential Analog

(Pin 15): Common Mode Bias Output, Nominally

IN2

Input.

–

A

IN2

Input.

V

CM2

parallel programming mode (PAR/SER = V ), SDO can

DD

Equal to V /2. V

should be used to bias the common

CM2

DD

be used together with SDI to power down the part (see

Table 2). When used as an input, SDO can be driven with

1.8V to 3.3V logic through a 1k series resistor.

mode of the analog inputs to channel 2. Bypass to ground

with a 0.1μF ceramic capacitor.

+

ENC (Pin 18): Encode Input. Conversion starts on the

V

(Pin 62): Reference Voltage Output. Bypass to

REF

rising edge.

ground with a 2.2μF ceramic capacitor. The output voltage

is nominally 1.25V.

21421012p

16

LTC2142-12/

LTC2141-12/LTC2140-12

PIN FUNCTIONS

DNC (Pins 23, 24, 25, 26, 27, 29, 31, 33, 35, 37, 43,

44, 45, 46, 47, 49, 51, 53, 55, 57, 59): Do not connect

these pins.

SENSE(Pin63):ReferenceProgrammingPin.Connecting

SENSEtoV selectstheinternalreferenceanda 1Vinput

DD

range. Connecting SENSE to ground selects the internal

reference and a 0.5V input range. An external reference

between 0.625V and 1.3V applied to SENSE selects an

–

+

CLKOUT (Pin 39): Inverted Version of CLKOUT .

+

CLKOUT (Pin 40): Data Output Clock. The digital outputs

input range of 0.8 • V

.

SENSE

normally transition at the same time as the falling and

Ground (Exposed Pad Pin 65): The exposed pad must be

soldered to the PCB ground.

+

rising edges of CLKOUT . The phase of CLKOUT can also

be delayed relative to the digital outputs by programming

the mode control registers.

FULL RATE CMOS OUTPUT MODE

D1_0_1 to D1_10_11 (Pins 48, 50, 52, 54, 56, 58):

Channel 1 Double Data Rate Digital Outputs. Two data

bits are multiplexed onto each output pin. The even data

All Pins Below Have CMOS Output Levels

(OGND to OV )

DD

+

bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT is

D2_0 to D2_11 (Pins 27, 28, 29, 30, 31, 32, 33, 34,

35, 36, 37, 38): Channel 2 Digital Outputs. D2_11 is the

MSB.

low. The odd data bits (D1, D3, D5, D7, D9, D11) appear

+

when CLKOUT is high.

OF2_1 (Pin 60): Over/Underflow Digital Output. OF2_1 is

high when an overflow or underflow has occurred. The

over/underflow for both channels are multiplexed onto

DNC(Pins23, 24, 25, 26, 43, 44, 45, 46):Donotconnect

these pins.

+

–

+

this pin. Channel 2 appears when CLKOUT is low, and

CLKOUT (Pin 39): Inverted Version of CLKOUT .

+

Channel 1 appears when CLKOUT is high.

+

CLKOUT (Pin 40): Data Output Clock. The digital outputs

normally transition at the same time as the falling edge

DOUBLE DATA RATE LVDS OUTPUT MODE

+

of CLKOUT . The phase of CLKOUT can also be delayed

relative to the digital outputs by programming the mode

control registers.

All Pins Below Have LVDS Output Levels. The Output

Current Level Is Programmable. There Is an Optional

Internal 100Ω Termination Resistor Between the Pins

of Each LVDS Output Pair.

D1_0 to D1_11 (Pins 47, 48, 49, 50, 51, 52, 53, 54,

55, 56, 57, 58): Channel 1 Digital Outputs. D1_11 Is the

MSB.

–

+

–

+

D2_0_1 /D2_0_1 toD2_10_11 /D2_10_11 (Pins 27/28,

29/30, 31/32, 33/34, 35/36, 37/38): Channel 2 Double

Data Rate Digital Outputs. Two data bits are multiplexed

onto each differential output pair. The even data bits (D0,

OF2(Pin59):Channel2Over/UnderflowDigitalOutput.OF2

is high when an overflow or underflow has occurred.

+

OF1(Pin60):Channel1Over/UnderflowDigitalOutput.OF1

is high when an overflow or underflow has occurred.

D2, D4, D6, D8, D10) appear when CLKOUT is low. The

odd data bits (D1, D3, D5, D7, D9, D11) appear when

+

CLKOUT is high.

–

+

DOUBLE DATA RATE CMOS OUTPUT MODE

All Pins Below Have CMOS Output Levels

CLKOUT /CLKOUT (Pins 39/40): Data Output Clock.

The digital outputs normally transition at the same time

+

as the falling and rising edges of CLKOUT . The phase of

(OGND to OV )

+

DD

CLKOUT canalsobedelayedrelativetothedigitaloutputs

by programming the mode control registers.

D2_0_1 to D2_10_11 (Pins 28, 30, 32, 34, 36, 38):

Channel 2 Double Data Rate Digital Outputs. Two data

bits are multiplexed onto each output pin. The even data

DNC(Pins23, 24, 25, 26, 43, 44, 45, 46):Donotconnect

these pins.

+

bits (D0, D2, D4, D6, D8, D10) appear when CLKOUT is

low. The odd data bits (D1, D3, D5, D7, D9, D11) appear

+

when CLKOUT is high.

21421012p

17

LTC2142-12/

LTC2141-12/LTC2140-12

PIN FUNCTIONS

–

+

–

+

–

+

D1_0_1 /D1_0_1 toD1_10_11 /D1_10_11 (Pins47/48,

49/50, 51/52, 53/54, 55/56, 57/58): Channel 2 Double

Data Rate Digital Outputs. Two data bits are multiplexed

onto each differential output pair. The even data bits (D0,

OF2_1 /OF2_1 (Pins 59/60): Over/Underflow Digital

Output. OF2_1 is high when an overflow or underflow

has occurred. The over/underflow for both channels

are multiplexed onto this pin. Channel 2 appears when

CLKOUT is low, and Channel 1 appears when CLKOUT

is high.

+

D2, D4, D6, D8, D10) appear when CLKOUT is low. The

odd data bits (D1, D3, D5, D7, D9, D11) appear when

+

CLKOUT is high.

FUNCTIONAL BLOCK DIAGRAM

OV

DD

CH 1

ANALOG

INPUT

OF1

12-BIT

ADC CORE

S/H

OF2

CORRECTION

LOGIC

D1_11

•

CH 2

ANALOG

INPUT

D1_0

12-BIT

ADC CORE

S/H

OUTPUT

DRIVERS

+

CLKOUT

D2_11

–

V

REF

1.25V

REFERENCE

•

2.2μF

D2_0

RANGE

SELECT

OGND

REFH

REFL INTERNAL CLOCK SIGNALS

REF

BUF

V

DD

SENSE

DIFF

REF

AMP

CLOCK/DUTY

CYCLE

CONTROL

MODE

CONTROL

REGISTERS

V

CM1

V

DD

/2

0.1μF

V

CM2

0.1μF

+

–

GND

REFH

REFL

ENC

PAR/SER CS SCK SDI SDO

2.2μF

21421012 F01

0.1μF

Figure 1. Functional Block Diagram

21421012p

18

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

CONVERTER OPERATION

Thetwochannelsaresimultaneouslysampledbyashared

encode circuit (Figure 2).

The LTC2142-12/LTC2141-12/LTC2140-12 are low

power, 2-channel, 12-bit, 65Msps/40Msps/25Msps A/D

converters that are powered by a single 1.8V supply. The

analog inputs should be driven differentially. The encode

input can be driven differentially, or single ended for lower

power consumption. The digital outputs can be CMOS,

double data rate CMOS (to halve the number of output

lines), or double data rate LVDS (to reduce digital noise

in the system.) Many additional features can be chosen

by programming the mode control registers through a

serial SPI port.

Single-Ended Input

For applications less sensitive to harmonic distortion, the

+

A

IN

input can be driven single-ended with a 1V signal

P-P

–

centered around V . The A input should be connected

CM

IN

to V . With a single-ended input the harmonic distortion

CM

and INL will degrade, but the noise and DNL will remain

unchanged.

INPUT DRIVE CIRCUITS

Input Filtering

ANALOG INPUT

If possible, there should be an RC lowpass filter right at

the analog inputs. This lowpass filter isolates the drive

circuitry from the A/D sample-and-hold switching, and

alsolimitswidebandnoisefromthedrivecircuitry.Figure 3

shows an example of an input RC filter. The RC component

values should be chosen based on the application’s input

frequency.

The analog inputs are differential CMOS sample-and-hold

circuits (Figure 2). The inputs should be driven differen-

tially around a common mode voltage set by the V

or

CM1

V

CM2

output pins, which are nominally V /2. For the 2V

DD

input range, the inputs should swing from V – 0.5V

CM

to V + 0.5V. There should be 180° phase difference

CM

between the inputs.

Transformer Coupled Circuits

LTC2142-12

V

DD

C

Figure 3 shows the analog input being driven by an RF

transformer with a center-tapped secondary. The center

SAMPLE

5pF

R

ON

10Ω

10ꢀ

15Ω

+

–

A

IN

tap is biased with V , setting the A/D input at its opti-

C

PARASITIC

CM

1.8pF

V

DD

mal DC level. At higher input frequencies, a transmission

line balun transformer (Figure 4 to Figure 6) has better

balance, resulting in lower A/D distortion.

SAMPLE

5pF

R

15Ω

ON

A

C

1.8pF

PARASITIC

V

50Ω

DD

V

CM

0.1μF

T1

1:1

+

25Ω

1.2V

A

IN

ANALOG

INPUT

LTC2142-12

10k

0.1μF

25Ω

+

–

ENC

12pF

–

25Ω

A

IN

10k

T1: MA/COM MABAES0060

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

21421012 F03

1.2V

21421012 F02

Figure 3. Analog Input Circuit Using a Transformer.

Recommended for Input Frequencies from 5MHz to 70MHz

Figure 2. Equivalent Input Circuit. Only One of the Two

Analog Channels Is Shown

21421012p

19

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

Amplifier Circuits

Reference

TheLTC2142-12/LTC2141-12/LTC2140-12hasaninternal

1.25V voltage reference. For a 2V input range using the

Figure 7 shows the analog input being driven by a high

speeddifferentialamplifier.TheoutputoftheamplifierisAC-

coupledtotheA/Dsotheamplifier’soutputcommonmode

voltage can be optimally set to minimize distortion.

internal reference, connect SENSE to V . For a 1V input

DD

range using the internal reference, connect SENSE to

ground. For a 2V input range with an external reference,

apply a 1.25V reference voltage to SENSE (Figure 9).

At very high frequencies, an RF gain block will often have

lower distortion than a differential amplifier. If the gain

block is single-ended, then a transformer circuit (Figure 4

to Figure 6) should convert the signal to differential before

driving the A/D.

The input range can be adjusted by applying a voltage to

SENSE that is between 0.625V and 1.30V. The input range

will then be 1.6 • V

.

SENSE

The V , REFH and REFL pins should be bypassed, as

REF

50Ω

V

CM

shown in Figure 8. A low inductance 2.2μF interdigitated

capacitor is recommended for the bypass between REFH

and REFL. This type of capacitor is available at a low cost

from multiple suppliers.

0.1μF

+

12Ω

A

ANALOG

INPUT

IN

T2

LTC2142-12

T1

0.1μF

25Ω

8.2pF

50Ω

V

CM

–

12Ω

A

IN

0.1μF

21421012 F04

0.1μF

4.7nH

0.1μF

+

A

ANALOG

INPUT

IN

T1: MA/COM MABA-007159-000000

T2: COILCRAFT WBC1-1TL

LTC2142-12

T1

25Ω

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

–

4.7nH

Figure 4. Recommended Front-End Circuit for Input

Frequencies from 5MHz to 150MHz

T1: MA/COM ETC1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

21421012 F06

50Ω

V

CM

Figure 6. Recommended Front-End Circuit for Input

Frequencies Above 250MHz

0.1μF

+

A

ANALOG

INPUT

IN

T2

LTC2142-12

T1

0.1μF

25Ω

V

CM

1.8pF

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

0.1μF

–

200Ω 200Ω

25Ω

A

IN

0.1μF

+

A

IN

21421012 F05

LTC2142-12

ANALOG

INPUT

12pF

+

T1: MA/COM MABA-007159-000000

T2: COILCRAFT WBC1-1TL

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

–

25Ω

A

IN

12pF

Figure 5. Recommended Front-End Circuit for Input

Frequencies from 150MHz to 250MHz

21421012 F07

Figure 7. Front-End Circuit Using a High Speed

Differential Amplifier

21421012p

20

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

REFL pins are connected by short jumpers in an internal

layer. To minimize the inductance of these jumpers they

can be placed in a small hole in the GND plane on the

second board layer.

LTC2142-12

5Ω

V

REF

1.25V BANDGAP

REFERENCE

1.25V

2.2μF

0.625V

RANGE

DETECT

AND

CONTROL

TIE TO V FOR 2V RANGE;

DD

SENSE

TIE TO GND FOR 1V RANGE;

3"/(&ꢀꢁꢀꢂꢃꢄꢀtꢀ7

FOR

SENSE

BUFFER

0.625V < V

< 1.300V

SENSE

INTERNAL ADC

HIGH REFERENCE

Figure 8c. Recommended Layout for the REFH/REFL

Bypass Circuit in Figure 8a

REFH

REFL

C2

0.1μF

–

+

–

+

0.8x

DIFF AMP

C1

REFH

REFL

–

+

–

C3

0.1μF

INTERNAL ADC

LOW REFERENCE

C1: 2.2μF LOW INDUCTANCE

INTERDIGITATED CAPACITOR

TDK CLLE1AX7S0G225M

MURATA LLA219C70G225M

AVX W2L14Z225M

21421012 F08a

Figure 8d. Recommended Layout for the REFH/REFL

Bypass Circuit in Figure 8b

OR EQUIVALENT

Figure 8a. Reference Circuit

V

REF

2.2μF

Alternatively C1 can be replaced by a standard 2.2μF

capacitor between REFH and REFL (see Figure 8b). The

capacitors should be as close to the pins as possible (not

on the back side of the circuit board).

LTC2142-12

1.25V

EXTERNAL

REFERENCE

SENSE

1μF

21421012 F09

Figure 9. Using an External 1.25V Reference

Figure 8c and Figure 8d show the recommended circuit

board layout for the REFH/REFL bypass capacitors. Note

that in Figure 8c, every pin of the interdigitated capacitor

(C1)isconnectedsincethepinsarenotinternallyconnected

in some vendors’ capacitors. In Figure 8d the REFH and

Encode Inputs

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals – do not route them next to

digital traces on the circuit board. There are two modes

of operation for the encode inputs: the differential encode

mode (Figure 10), and the single-ended encode mode

(Figure 11).

LTC2142-12

REFH

REFL

C3

0.1μF

C1

2.2μF

REFH

The differential encode mode is recommended for si-

nusoidal, PECL, or LVDS encode inputs (Figure 12 and

Figure 13). The encode inputs are internally biased to 1.2V

through 10k equivalent resistance. The encode inputs can

C2

REFL

0.1μF

21421012 F08b

CAPACITORS ARE 0402 PACKAGE SIZE

be taken above V (up to 3.6V), and the common mode

Figure 8b. Alternative REFH/REFL Bypass Circuit

DD

rangeisfrom1.1Vto1.6V. Inthedifferentialencodemode,

21421012p

21

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

–

ENC should stay at least 200mV above ground to avoid

LTC2142-12

V

DD

falsely triggering the single ended encode mode. For good

jitter performance ENC and ENC should have fast rise

and fall times.

+

–

DIFFERENTIAL

COMPARATOR

V

DD

Thesingle-endedencodemodeshouldbeusedwithCMOS

15k

30k

–

+

–

ENC

encode inputs. To select this mode, ENC is connected

+

to ground and ENC is driven with a square wave encode

+

input. ENC can be taken above V (up to 3.6V) so 1.8V

DD

+

to3.3VCMOSlogiclevelscanbeused.TheENC threshold

+

is 0.9V. For good jitter performance, ENC should have

21421012 F10

fast rise and fall times.

Figure 10. Equivalent Encode Input Circuit

for Differential Encode Mode

If the encode signal is turned off or drops below approxi-

mately 500kHz, the A/D enters nap mode.

LTC2142-12

+

Clock Duty Cycle Stabilizer

1.8V TO 3.3V

0V

ENC

For good performance the encode signal should have a

50% ( 5%) duty cycle. If the optional clock duty cycle

stabilizer circuit is enabled, the encode duty cycle can

vary from 30% to 70% and the duty cycle stabilizer will

maintain a constant 50% internal duty cycle. If the encode

signal changes frequency, the duty cycle stabilizer circuit

requires one hundred clock cycles to lock onto the input

clock. The duty cycle stabilizer is enabled by mode control

register A2 (serial programming mode), or by CS (parallel

programming mode).

–

30k

ENC

CMOS LOGIC

BUFFER

21421012 F11

Figure 11. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

0.1μF

+

ENC

T1

50ꢀ

100ꢀ

LTC2142-12

Forapplicationswherethesamplerateneedstobechanged

quickly, the clock duty cycle stabilizer can be disabled. If

thedutycyclestabilizerisdisabled,careshouldbetakento

makethesamplingclockhavea50%( 5%)dutycycle.The

duty cycle stabilizer should not be used below 5Msps.

–

ENC

0.1μF

21421012 F12

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

DIGITAL OUTPUTS

Figure 12. Sinusoidal Encode Drive

Digital Output Modes

0.1μF

+

ENC

The LTC2142-12/LTC2141-12/LTC2140-12 can operate in

three digital output modes: full rate CMOS, double data

rateCMOS(tohalvethenumberofoutputlines), ordouble

data rate LVDS (to reduce digital noise in the system.) The

output mode is set by mode control register A3 (serial

programming mode), or by SCK (parallel programming

mode).NotethatdoubledatarateCMOScannotbeselected

in the parallel programming mode.

PECL OR

LTC2142-12

LVDS

CLOCK

0.1μF

–

ENC

21421012 F13

Figure 13. PECL or LVDS Encode Drive

21421012p

22

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

+

–

Full Rate CMOS Mode

dataoutputclock(CLKOUT /CLKOUT )eachhaveanLVDS

output pair. Note that the overflow for both ADC channels

In full rate CMOS mode the data outputs (D1_0 to D1_11

and D2_0 to D2_11), overflow (OF2, OF1), and the data

+

–

is multiplexed onto the OF2_1 /OF2_1 output pair.

+

–

output clocks (CLKOUT , CLKOUT ) have CMOS output

By default the outputs are standard LVDS levels: 3.5mA

output current and a 1.25V output common mode volt-

age. An external 100ꢀ differential termination resistor

is required for each LVDS output pair. The termination

resistors should be located as close as possible to the

LVDS receiver.

levels. TheoutputsarepoweredbyOV andOGNDwhich

DD

are isolated from the A/D core power and ground. OV

DD

can range from 1.1V to 1.9V, allowing 1.2V through 1.8V

CMOS logic outputs.

For good performance, the digital outputs should drive

minimal capacitive loads. If the load capacitance is larger

than 10pF a digital buffer should be used.

The outputs are powered by OV and OGND which are

DD

isolated from the A/D core power and ground. In LVDS

mode, OV must be 1.8V.

DD

Double Data Rate CMOS Mode

Programmable LVDS Output Current

In double data rate CMOS mode, two data bits are

multiplexed and output on each data pin. This reduces

the number of digital lines by thirteen, simplifying

board routing and reducing the number of input pins

needed to receive the data. The data outputs (D1_0_1,

D1_2_3, D1_4_5, D1_6_7, D1_8_9, D1_10_11, D2_0_1,

D2_2_3,D2_4_5,D2_6_7,D2_8_9,D2_10_11),overflow

In LVDS mode, the default output driver current is 3.5mA.

Thiscurrentcanbeadjustedbyseriallyprogrammingmode

control register A3. Available current levels are 1.75mA,

2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.

Optional LVDS Driver Internal Termination

+

–

(OF2_1),andthedataoutputclocks(CLKOUT ,CLKOUT )

have CMOS output levels. The outputs are powered by

In most cases, using just an external 100ꢀ termination

resistor will give excellent LVDS signal integrity. In addi-

tion, an optional internal 100ꢀ termination resistor can

beenabledbyseriallyprogrammingmodecontrolregister

A3. The internal termination helps absorb any reflections

caused by imperfect termination at the receiver. When the

internal termination is enabled, the output driver current

is doubled to maintain the same output voltage swing.

OV and OGND which are isolated from the A/D core

DD

power and ground. OV can range from 1.1V to 1.9V,

DD

allowing 1.2V through 1.8V CMOS logic outputs. Note

that the overflow for both ADC channels is multiplexed

onto the OF2_1 pin.

For good performance, the digital outputs should drive

minimal capacitive loads. If the load capacitance is larger

than 10pF a digital buffer should be used.

Overflow Bit

Theoverflowoutputbitoutputsalogichighwhentheanalog

input is either overranged or underranged. The overflow

bit has the same pipeline latency as the data bits. In full

rate CMOS mode each ADC channel has its own overflow

pin (OF1 for channel 1, OF2 for channel 2). In DDR CMOS

or DDR LVDS mode the overflow for both ADC channels

is multiplexed onto the OF2_1 output.

Double Data Rate LVDS Mode

In double data rate LVDS mode, two data bits are

multiplexed and output on each differential output

pair. There are six LVDS output pairs per ADC channel

+

–

+

–

(D1_0_1 /D1_0_1 through D1_10_11 /D1_10_11 and

D2_0_1 /D2_0_1 through D2_10_11 /D2_10_11 ) for

–

thedigitaloutputdata. Overflow(OF2_1 /OF2_1 )andthe

21421012p

23

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

Phase Shifting the Output Clock

DATA FORMAT

In full rate CMOS mode the data output bits normally

Table 1 shows the relationship between the analog input

voltage, the digital data output bits and the overflow bit.

By default the output data format is offset binary. The 2’s

complement format can be selected by serially program-

ming mode control register A4.

+

change at the same time as the falling edge of CLKOUT ,

+

so the rising edge of CLKOUT can be used to latch the

output data. In double data rate CMOS and LVDS modes

the data output bits normally change at the same time as

+

thefallingandrisingedgesofCLKOUT .Toallowadequate

Table 1. Output Codes vs Input Voltage

+

set-up and hold time when latching the data, the CLKOUT

+

–

A

– A

D11-D0

IN

signal may need to be phase shifted relative to the data

outputbits. MostFPGAshavethisfeature;thisisgenerally

the best place to adjust the timing.

(2V Range)

>+1.000000V

+0.999512V

+0.999024V

+0.000488V

0.000000V

OF (OFFSET BINARY)

(2’s COMPLEMENT)

1

0

1

1111 1111 1111

1111 1111 1110

1000 0000 0001

1000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

1000 0000 0001

1000 0000 0000

The LTC2142-12/LTC2141-12/LTC2140-12 can also

+

–

phase shift the CLKOUT /CLKOUT signals by serially

programming mode control register A2. The output

clock can be shifted by 0°, 45°, 90°, or 135°. To use the

phase shifting feature the clock duty cycle stabilizer must

be turned on. Another control register bit can invert the

–0.000488V

–0.000976V

–0.999512V

–1.000000V

≤–1.000000V

+

–

polarity of CLKOUT and CLKOUT , independently of the

phaseshift.Thecombinationofthesetwofeaturesenables

phase shifts of 45° up to 315° (Figure 14).

+

ENC

D0-D11, OF

MODE CONTROL BITS

PHASE

SHIFT

CLKINV

CLKPHASE1 CLKPHASE0

0°

0

1

0

1

0

1

0

1

0

1

0

1

0

1

45°

90°

135°

180°

225°

270°

+

CLKOUT

315°

21421012 F14

Figure 14. Phase Shifting CLKOUT

21421012p

24

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

Digital Output Randomizer

CLKOUT

OF

Interference from the A/D digital outputs is sometimes

unavoidable.Digitalinterferencemaybefromcapacitiveor

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off chip, these unwanted

tones can be randomized which reduces the unwanted

tone amplitude.

OF

D11

D11/D0

D10/D0

D10

D2

•

D2/D0

D1/D0

The digital output is randomized by applying an exclusive-

OR logic operation between the LSB and all other data

output bits. To decode, the reverse operation is applied

– an exclusive-OR operation is applied between the LSB

and all other bits. The LSB, OF and CLKOUT outputs are

not affected. The output randomizer is enabled by serially

programming mode control register A4.

RANDOMIZER

ON

D1

D0

21421012 F15

Figure 15. Functional Equivalent of Digital Output Randomizer

Alternate Bit Polarity

Anotherfeaturethatreducesdigitalfeedbackonthecircuit

board is the alternate bit polarity mode. When this mode

is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11)

are inverted before the output buffers. The even bits (D0,

D2, D4, D6, D8, D10), OF and CLKOUT are not affected.

Thiscanreducedigitalcurrentsinthecircuitboardground

plane and reduce digital noise, particularly for very small

analog input signals.

PC BOARD

FPGA

CLKOUT

OF

D11/D0

D11

D10

When there is a very small signal at the input of the A/D

thatiscenteredaroundmid-scale,thedigitaloutputstoggle

between mostly 1’s and mostly 0’s. This simultaneous

switchingofmostofthebitswillcauselargecurrentsinthe

ground plane. By inverting every other bit, the alternate bit

polarity mode makes half of the bits transition high while

half of the bits transition low. This cancels current flow in

the ground plane, reducing the digital noise.

D10/D0

LTC2142-12

t

D2/D0

D1/D0

D2

D1

D0

The digital output is decoded at the receiver by inverting

the odd bits (D1, D3, D5, D7, D9, D11). The alternate

bit polarity mode is independent of the digital output

randomizer – either, both or neither function can be on at

the same time. The alternate bit polarity mode is enabled

by serially programming mode control register A4.

21421012 F16

Figure 16. Unrandomizing a Randomized Digital

Output Signal

21421012p

25

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

Digital Output Test Patterns

slight temperature shift caused by the change in supply

current as the A/D leaves nap mode. Either channel 2 or

bothchannelscanbeplacedinnapmode;itisnotpossible

to have channel 1 in nap mode and channel 2 operating

normally.

To allow in-circuit testing of the digital interface to the

A/D, there are several test modes that force the A/D data

outputs (OF, D11-D0) to known values:

All 1s: All outputs are 1

All 0s: All outputs are 0

Sleep mode and nap mode are enabled by mode control

register A1 (serial programming mode), or by SDI and

SDO (parallel programming mode).

Alternating: Outputs change from all 1s to all 0s on

alternating samples.

DEVICE PROGRAMMING MODES

Checkerboard: Outputs change from 1010101010101

to 0101010101010 on alternating samples.

The operating modes of the LTC2142-12/LTC2141-12/

LTC2140-12 can be programmed by either a parallel

interface or a simple serial interface. The serial interface

has more flexibility and can program all available modes.

Theparallelinterfaceismorelimitedandcanonlyprogram

some of the more commonly used modes.

The digital output test patterns are enabled by serially

programming mode control register A4. When enabled,

the test patterns override all other formatting modes: 2’s

complement, randomizer, alternate bit polarity.

Output Disable

Parallel Programming Mode

The digital outputs may be disabled by serially program-

mingmodecontrolregisterA3.Alldigitaloutputsincluding

OFandCLKOUTaredisabled.Thehighimpedancedisabled

state is intended for in-circuit testing or long periods of

inactivity – it is too slow to multiplex a data bus between

multiple converters at full speed. When the outputs are

disabled both channels should be put into either sleep or

nap mode.

To use the parallel programming mode, PAR/SER should

be tied to V . The CS, SCK, SDI and SDO pins are binary

DD

logic inputs that set certain operating modes. These pins

can be tied to V or ground, or driven by 1.8V, 2.5V, or

DD

3.3V CMOS logic. When used as an input, SDO should

be driven through a 1k series resistor. Table 2 shows the

modes set by CS, SCK, SDI and SDO.

Table 2. Parallel Programming Mode Control Bits (PAR/SER = V_DD

)

Sleep and Nap Modes

DESCRIPTION

CS

Clock Duty Cycle Stabilizer Control Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

Digital Output Mode Control Bit

0 = Full Rate CMOS Output Mode

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire device is powered down,

resulting in 1mW power consumption. The amount of

time required to recover from sleep mode depends on the

SCK

size of the bypass capacitors on V , REFH, and REFL.

REF

1 = Double Data Rate LVDS Output Mode

For the suggested values in Fig. 8, the A/D will stabilize

after 2ms.

(3.5mA LVDS Current, Internal Termination Off)

SDI/SDO Power Down Control Bit

InnapmodetheA/Dcoreispowereddownwhiletheinternal

reference circuits stay active, allowing faster wakeup than

from sleep mode. Recovering from nap mode requires at

least 100 clock cycles. If the application demands very

accurate DC settling then an additional 50μs should be

allowed so the on-chip references can settle from the

00 = Normal Operation

01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode

10 = Channel 1 and Channel 2 in Nap Mode

11 = Sleep Mode (Entire Device Powered Down)

21421012p

26

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

Serial Programming Mode

GROUNDING AND BYPASSING

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become

a serial interface that program the A/D mode control

registers. Data is written to a register with a 16-bit serial

word. Data can also be read back from a register to verify

its contents.

The LTC2142-12/LTC2141-12/LTC2140-12 requires a

printed circuit board with a clean unbroken ground plane.

A multilayer board with an internal ground plane in the

first layer beneath the ADC is recommended. Layout for

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. In

particular, care should be taken not to run any digital track

alongside an analog signal track or underneath the ADC.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the first 16 rising edges of

SCK. Any SCK rising edges after the first 16 are ignored.

The data transfer ends when CS is taken high again.

High quality ceramic bypass capacitors should be used at

the V , OV , V , V , REFH and REFL pins. Bypass

DD

DD CM REF

capacitorsmustbelocatedasclosetothepinsaspossible.

Size0402ceramiccapacitorsarerecommended.Thetraces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

The first bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The final eight bits are the register data (D7:D0).

If the R/W bit is low, the serial data (D7:D0) will be writ-

ten to the register set by the address bits (A6:A0). If the

R/W bit is high, data in the register set by the address bits

(A6:A0) will be read back on the SDO pin (see the timing

diagrams). During a read back command the register is

not updated and data on SDI is ignored.

Of particular importance is the capacitor between REFH

and REFL. This capacitor should be on the same side of

the circuit board as the A/D, and as close to the device

as possible.

The analog inputs, encode signals, and digital outputs

should not be routed next to each other. Ground fill and

grounded vias should be used as barriers to isolate these

signals from each other.

The SDO pin is an open drain output that pulls to ground

with a 200ꢀ impedance. If register data is read back

through SDO, an external 2k pull-up resistor is required.

If serial data is only written and read back is not needed,

then SDO can be left floating and no pull-up resistor is

needed.

HEAT TRANSFER

MostoftheheatgeneratedbytheLTC2142-12/LTC2141-12/

LTC2140-12istransferredfromthediethroughthebottom-

sideexposedpadandpackageleadsontotheprintedcircuit

board. For good electrical and thermal performance, the

exposed pad must be soldered to a large grounded pad

on the PC board. This pad should be connected to the

internal ground planes by an array of vias.

Table 3 shows a map of the mode control registers.

Software Reset

If serial programming is used, the mode control registers

shouldbeprogrammedassoonaspossibleafterthepower

supplies turn on and are stable. The first serial command

must be a software reset which will reset all register data

bits to logic 0. To perform a software reset, bit D7 in the

reset register is written with a logic 1. After the reset is

complete, bit D7 is automatically set back to zero.

21421012p

27

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

Table 3. Serial Programming Mode Register Map (PAR/SER = GND)

REGISTER A0: RESET REGISTER (ADDRESS 00h)

D7

D6

X

D5

X

D4

X

D3

X

D2

X

D1

X

D0

X

RESET

Bit 7

RESET

0 = Not Used

Software Reset Bit

1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. This Bit Is

Automatically Set Back to Zero After the Reset Is Complete

Bits 6-0

Unused, Don’t Care Bits.

REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)

D7

X

D6

X

D5

X

D4

X

D3

X

D2

X

D1

D0

PWROFF1

PWROFF0

Bits 7-2

Bits 1-0

Unused, Don’t Care Bits.

PWROFF1:PWROFF0

Power Down Control Bits

00 = Normal Operation

01 = Channel 1 in Normal Operation, Channel 2 in Nap Mode

10 = Channel 1 and Channel 2 in Nap Mode

11 = Sleep Mode

REGISTER A2: TIMING REGISTER (ADDRESS 02h)

D7

X

D6

X

D5

X

D4

X

D3

D2

D1

D0

CLKINV

CLKPHASE1

CLKPHASE0

DCS

Bits 7-4

Unused, Don’t Care Bits.

Bit 3

CLKINV

Output Clock Invert Bit

0 = Normal CLKOUT Polarity (As Shown in the Timing Diagrams)

1 = Inverted CLKOUT Polarity

Bits 2-1

CLKPHASE1:CLKPHASE0

Output Clock Phase Delay Bits

00 = No CLKOUT Delay (As Shown in the Timing Diagrams)

+

–

01 = CLKOUT /CLKOUT Delayed by 45° (Clock Period • 1/8)

+

–

10 = CLKOUT /CLKOUT Delayed by 90° (Clock Period • 1/4)

+

–

11 = CLKOUT /CLKOUT Delayed by 135° (Clock Period • 3/8)

Note: If the CLKOUT Phase Delay Feature Is Used, the Clock Duty Cycle Stabilizer Must Also Be Turned On

DCS Clock Duty Cycle Stabilizer Bit

Bit 0

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

21421012p

28

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)

D7

X

D6

D5

D4

D3

D2

D1

D0

ILVDS2

ILVDS1

ILVDS0

TERMON

OUTOFF

OUTMODE1

OUTMODE0

Bit 7

Unused, Don’t Care Bit.

Bits 6-4

ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 3

Bit 2

TERMON

LVDS Internal Termination Bit

0 = Internal Termination Off

1 = Internal Termination On. LVDS Output Driver Current is 2 the Current Set by ILVDS2:ILVDS0

OUTOFF

0 = Digital Outputs Are Enabled

Output Disable Bit

1 = Digital Outputs Are Disabled and Have High Output Impedance

Note: If the Digital Outputs Are Disabled the Part Should Also Be Put in Sleep or Nap Mode (Both Channels).

Bits 1-0

OUTMODE1:OUTMODE0

Digital Output Mode Control Bits

00 = Full Rate CMOS Output Mode

01 = Double Data Rate LVDS Output Mode

10 = Double Data Rate CMOS Output Mode

11 = Not Used

REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)

D7

X

D6

X

D5

D4

D3

D2

D1

D0

OUTTEST2

OUTTEST1

OUTTEST0

ABP

RAND

TWOSCOMP

Bit 7-6

Unused, Don’t Care Bits.

Bits 5-3

OUTTEST2:OUTTEST0

Digital Output Test Pattern Bits

000 = Digital Output Test Patterns Off

001 = All Digital Outputs = 0

011 = All Digital Outputs = 1

101 = Checkerboard Output Pattern. OF, D11-D0 Alternate Between 1 0101 0101 0101 and 0 1010 1010 1010

111 = Alternating Output Pattern. OF, D11-D0 Alternate Between 0 0000 0000 0000 and 1 1111 1111 1111

Note: Other Bit Combinations Are Not Used

Bit 2

Bit 1

Bit 0

ABP

Alternate Bit Polarity Mode Control Bit

0 = Alternate Bit Polarity Mode Off

1 = Alternate Bit Polarity Mode On. Forces the Output Format to Be Offset Binary

RAND

Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

TWOSCOMP

Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

21421012p

29

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL APPLICATIONS

Silkscreen Top

Top Side

21421012p

30

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL APPLICATIONS

Inner Layer 2 GND

Inner Layer 3

21421012p

31

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL APPLICATIONS

Inner Layer 4

Inner Layer 5 Power

21421012p

32

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL APPLICATIONS

Bottom Side

21421012p

33

LTC2142-12/

LTC2141-12/LTC2140-12

TYPICAL APPLICATIONS

SDO

C23

2.2μF

SENSE

C17

1μF

V

DD

C19

0.1μF

C20

0.1μF

DIGITAL

OUTPUTS

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

+

–

V

D1_0_1

DD

CM1

3

GND

DNC

4

+

A

IN1

5

–

6

GND

C15

7

0.1μF

REFH

REFL

REFH

REFL

OV

DD

OV

DD

–

+

–

C37

0.1μF

8

OGND

LTC2142-12

9

+

CLKOUT

CN1

10

11

12

13

14

15

16

–

CLKOUT

–

+

–

+

PAR/SER

D2_10_11

C21

0.1μF

+

–

A

D2_10_11

IN2

–

+

A

D2_8_9

IN2

–

GND

D2_8_9

DIGITAL

OUTPUTS

+

V

D2_6_7

CM2

DD

–

D2_6_7

PAR/SER

65

PAD

+

A

IN2

–

IN2

V

DD

C67

0.1μF

C18

0.1μF

C78

0.1μF

C79

0.1μF

R51

100Ω

ENCODE

CLOCK

SPI BUS

21821012 TA02

LTC2142 Schematic

21421012p

34

LTC2142-12/

LTC2141-12/LTC2140-12

PACKAGE DESCRIPTION

UP Package

64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705 Rev C)

0.70 ±0.05

7.15 ±0.05

7.50 REF

8.10 ±0.05 9.50 ±0.05

(4 SIDES)

7.15 ±0.05

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 ± 0.05

R = 0.10

TYP

R = 0.115

TYP

9 .00 ± 0.10

(4 SIDES)

63 64

0.40 ± 0.10

PIN 1 TOP MARK

(SEE NOTE 5)

1

2

PIN 1

CHAMFER

C = 0.35

7.15 ± 0.10

7.50 REF

(4-SIDES)

7.15 ± 0.10

(UP64) QFN 0406 REV C

0.200 REF

0.25 ± 0.05

0.50 BSC

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

21421012p

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

35

LINEAR TECHNOLOGY CONFIDENTIAL

LTC2141-12/LTC2140-12

LTC2142-12/

TYPICAL APPLICATIONS

2-Tone FFT, f_IN= 70MHz and 69MHz

1.8V

OV

V

DD

0

–10

–20

–30

–40

–50

–60

–70

CH 1

ANALOG

INPUT

12-BIT

D1_11

S/H

•

ADC CORE

CMOS

OR

D1_0

LVDS

D2_11

OUTPUTS

•

OUTPUT

DRIVERS

CH 2

ANALOG

INPUT

–80

–90

12-BIT

ADC CORE

D2_0

–100

–110

–120

125MHz

CLOCK

0

20

10

FREQUENCY (MHz)

30

CLOCK

CONTROL

21821012 TA01b

21454312 TA01a

GND

OGND

RELATED PARTS

PART NUMBER

ADCs

DESCRIPTION

COMMENTS

LTC2259-14/LTC2260-14/ 14-Bit, 80Msps/105Msps/125Msps

89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS

Outputs, 6mm × 6mm QFN-40

LTC2261-14

1.8V ADCs, Ultralow Power

LTC2262-14

14-Bit, 150Msps 1.8V ADC, Ultralow

Power

149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,

6mm × 6mm QFN-40

LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps

LTC2268-14 1.8V Dual ADCs, Ultralow Power

216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs,

6mm × 6mm QFN-40

LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps

216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs,

6mm × 6mm QFN-40

LTC2268-12

1.8V Dual ADCs, Ultralow Power

LTC2182/LTC2181/

LTC2180

16-Bit 65Msps/40Msps/25Msps

1.8V Dual ADCs, Ultralow Power

182mW/112mW/70mW, 76.8dB SNR, 90dB SFDR, DDR WDS/DDR CMOS/

CMOS Outputs, 9mm × 9mm QFN-64

LTC2142-14/LTC2141-14/ 14-Bit 65Msps/40Msps/25Msps

104mW/68mW/48mW, 73dB SNR, 90dB SFDR, DDR LVDS/DDR CMOS/

CMOS Outputs, 9mm × 9mm QFN-64

LTC2140-14

1.8V Dual ADCs, Ultralow Power

RF Mixers/Demodulators

LTC5517

40MHz to 900MHz Direct Conversion

Quadrature Demodulator

High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LTC5557

LTC5575

400MHz to 3.8GHz High Linearity

Downconverting Mixer

23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply

Operation, Integrated Transformer

800MHz to 2.7GHz Direct Conversion

Quadrature Demodulator

High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF

and LO Transformer

Amplifiers/Filters

LTC6412

800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure,

Variable Gain Amplifier

4mm × 4mm QFN-24

LTC6605-7/LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz

Dual Matched 2nd Order Lowpass Filters with Differential Drivers,

Pin-Programmable Gain, 6mm × 3mm DFN-22

LTC6605-14

Filters with ADC Drivers

Signal Chain Receivers

LTM9002

14-Bit Dual Channel IF/Baseband

Receiver Subsystem

Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers

21421012p

LT 0311 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

36

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2140-12
厂家：	Linear
描述：	12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs 12位，支持65Msps / 40Msps的/ 25Msps时的低功耗双通道ADC
文件：	总36页 (文件大小：1015K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2140-12 [Linear]

相关型号：

LTC2140-12_15

LTC2140-14

LTC2140-14_15

LTC2140CUP-14#PBF

LTC2140IUP-14#PBF

LTC2141-12_15

LTC2141-14

LTC2141-14_15

LTC2141CUP-14#PBF

LTC2141IUP-14#PBF

LTC2142-12_15

LTC2142-14