LTC2253IUH#TR [Linear]
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| 型号： | LTC2253IUH#TR |
| 厂家： | 
Linear |
| 描述： | 暂无描述 |
| 文件： | 总24页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2253/LTC2252
12-Bit, 125/105Msps
Low Power 3V ADCs
U
FEATURES
DESCRIPTIO
The LTC®2253/LTC2252 are 12-bit 125Msps/105Msps,
low power 3V A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2253/
LTC2252 are perfect for demanding imaging and commu-
nications applications with AC performance that includes
70.1dB SNR and 85dB SFDR for signals at the Nyquist
frequency.
■
Sample Rate: 125Msps/105Msps
■
Single 3V Supply (2.85V to 3.4V)
■
Low Power: 395mW/320mW
■
70.2dB SNR
88dB SFDR
No Missing Codes
■
■
■
Flexible Input: 1VP-P to 2VP-P Range
■
640MHz Full Power Bandwidth S/H
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
■
Clock Duty Cycle Stabilizer
and no missing codes over temperature. The transition
■
Shutdown and Nap Modes
noise is a low 0.32LSBRMS
.
■
Pin Compatible Family
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V
logic.
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
Asingle-endedCLKinputcontrolsconverteroperation.An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
32-Pin (5mm × 5mm) QFN Package
U
APPLICATIO S
■
Wireless and Wired Broadband Communication
■
Imaging Systems
■
Ultrasound
Spectral Analysis
Portable Instrumentation
■
■
U
TYPICAL APPLICATIO
LTC2253: SNR vs Input Frequency,
–1dB, 2V Range, 125Msps
REFH
73
FLEXIBLE
REFERENCE
REFL
72
OV
DD
71
D11
+
12-BIT
PIPELINED
ADC CORE
70
69
68
67
66
•
•
•
CORRECTION
LOGIC
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
–
D0
OGND
CLOCK/DUTY
CYCLE
CONTROL
65
0
50
100 150 200 250 300 350
22532 TA01
22532 G09
INPUT FREQUENCY (MHz)
CLK
22532fa
1
LTC2253/LTC2252
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
OV = V (Notes 1, 2)
DD
SuDpDply Voltage (VDD)................................................. 4V
Digital Output Ground Voltage (OGND) .......–0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage................–0.3V to (OVDD + 0.3V)
Power Dissipation............................................ 1500mW
Operating Temperature Range
TOP VIEW
ORDER PART
NUMBER
32 31 30 29 28 27 26 25
LTC2253CUH
LTC2253IUH
LTC2252CUH
LTC2252IUH
+
–
A
A
1
2
3
4
5
6
7
8
24 D8
23 D7
IN
IN
REFH
REFH
REFL
REFL
D6
OV
22
21
DD
33
20 OGND
D5
LTC2253C, LTC2252C ............................. 0°C to 70°C
LTC2253I, LTC2252I ...........................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
19
V
18 D4
17 D3
DD
GND
QFN PART*
MARKING
9
10 11 12 13 14 15 16
UH PACKAGE
2253
2252
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS GND
MUST BE SOLDERED TO PCB
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
U
CO VERTER CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
LTC2253
TYP
LTC2252
TYP
PARAMETER
CONDITIONS
MIN
12
MAX
MIN
12
MAX
UNITS
Bits
Resolution (No Missing Codes)
Integral Linearity Error
●
●
Differential Analog Input
(Note 5)
–1.5
±0.3
1.5
–1.5
±0.3
1.5
LSB
Differential Linearity Error
Offset Error
Differential Analog Input
(Note 6)
●
●
●
–0.7 ±0.15
0.7
12
–0.7 ±0.15
0.7
12
LSB
mV
–12
±2
–12
±2
Gain Error
External Reference
–2.5
±0.5
±10
2.5
–2.5
±0.5
±10
2.5
%FS
µV/°C
Offset Drift
Full-Scale Drift
Internal Reference
External Reference
±30
±5
±30
±5
ppm/°C
ppm/°C
Transition Noise
SENSE = 1V
0.32
0.32
LSB
RMS
22532fa
2
LTC2253/LTC2252
U
U
A ALOG I PUT
The
●
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
±0.5V to ±1V
1.5
MAX
UNITS
V
+
–
V
V
Analog Input Range (A – A
)
2.85V < V < 3.4V (Note 7)
●
●
●
●
●
IN
IN
IN
DD
Analog Input Common Mode
Differential Input (Note 7)
1
1.9
1
V
IN,CM
+
–
I
I
I
t
t
Analog Input Leakage Current
SENSE Input Leakage
MODE Pin Leakage
0V < A , A < V
DD
–1
–3
–3
µA
µA
µA
ns
IN
IN
IN
0V < SENSE < 1V
3
SENSE
MODE
AP
3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
0
0.2
80
ps
RMS
JITTER
CMRR
dB
Figure 8 Test Circuit
640
MHz
U W
DY A IC ACCURACY
The
IN
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T = 25°C. A = –1dBFS. (Note 4)
A
LTC2253
TYP
LTC2252
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
SNR
Signal-to-Noise Ratio
5MHz Input
70.2
70.1
70
70.2
70.2
70.1
69.8
88
30MHz Input
70MHz Input
140MHz Input
5MHz Input
●
●
●
●
68
68.5
69.6
88
Spurious Free Dynamic Range
2nd or 3rd Harmonic
SFDR
SFDR
S/(N+D)
IMD
30MHz Input
70MHz Input
140MHz Input
5MHz Input
85
88
72
77
67
82
71
78
84
78
79
Spurious Free Dynamic Range
4th Harmonic or Higher
90
90
30MHz Input
70MHz Input
140MHz Input
5MHz Input
90
90
90
90
90
90
Signal-to-Noise Plus
Distortion Ratio
69.8
69.7
69.6
68.5
85
70.1
70.1
70
30MHz Input
70MHz Input
140MHz Input
67.5
68.7
85
Intermodulation Distortion
f
f
= 28.2MHz,
= 26.8MHz
IN1
IN2
22532fa
3
LTC2253/LTC2252
U U
U
(Note 4)
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
CONDITIONS
= 0
MIN
TYP
MAX
UNITS
V
V
V
V
V
Output Voltage
Output Tempco
Line Regulation
Output Resistance
I
1.475 1.500 1.525
CM
CM
CM
CM
OUT
±25
3
ppm/°C
mV/V
Ω
2.85V < V < 3.4V
DD
–1mA < I
< 1mA
4
OUT
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
2
TYP
MAX
UNITS
LOGIC INPUTS (CLK, OE, SHDN)
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 3V
●
●
●
V
V
IH
IL
DD
DD
IN
= 3V
0.8
10
I
= 0V to V
–10
µA
pF
IN
DD
C
Input Capacitance
(Note 7)
3
IN
LOGIC OUTPUTS
OV = 3V
DD
C
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
OE = High (Note 7)
3
pF
mA
mA
OZ
I
I
V
V
= 0V
= 3V
50
50
SOURCE
SINK
OUT
OUT
V
High Level Output Voltage
I = –10µA
O
2.995
2.99
V
V
OH
O
I = –200µA
●
●
2.7
V
Low Level Output Voltage
I = 10µA
0.005
0.09
V
V
OL
O
I = 1.6mA
0.4
O
OV = 2.5V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
2.49
0.09
V
V
OH
OL
O
I = 1.6mA
O
OV = 1.8V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –200µA
1.79
0.09
V
V
OH
OL
O
I = 1.6mA
O
22532fa
4
LTC2253/LTC2252
W U
POWER REQUIRE E TS
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 8)
A
LTC2253
TYP
LTC2252
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
V
Analog Supply
Voltage
(Note 9)
●
2.85
3
3.4
2.85
3
3.4
V
DD
OV
Output Supply Voltage
Supply Current
(Note 9)
●
●
●
0.5
3
3.6
156
468
0.5
3
3.6
126
378
V
mA
DD
I
132
395
2
107
320
2
VDD
P
P
Power Dissipation
Shutdown Power
mW
mW
DISS
SHDN = H,
SHDN
OE = H, No CLK
P
Nap Mode Power
SHDN = H,
OE = L, No CLK
15
15
mW
NAP
W U
TI I G CHARACTERISTICS The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T = 25°C. (Note 4)
A
LTC2253
TYP
LTC2252
TYP
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
f
t
Sampling Frequency
CLK Low Time
(Note 9)
●
1
125
1
105
MHz
s
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●
●
3.8
3
4
4
500
500
4.5
3
4.76
4.76
500
500
ns
ns
L
t
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●
●
3.8
3
4
4
500
500
4.5
3
4.76
4.76
500
500
ns
ns
H
t
t
Sample-and-Hold
Aperture Delay
0
0
ns
AP
D
CLK to DATA Delay
C = 5pF (Note 7)
●
●
1.4
2.7
4.3
5.4
10
1.4
2.7
4.3
5.4
10
ns
ns
L
Data Access Time
C = 5pF (Note 7)
L
After OE↓
BUS Relinquish Time
(Note 7)
●
3.3
5
8.5
3.3
5
8.5
ns
Pipeline
Latency
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
Note 2: All voltage values are with respect to ground with GND and OGND
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
wired together (unless otherwise noted).
Note 7: Guaranteed by design, not subject to test.
Note 3: When these pin voltages are taken below GND or above V , they
will be clamped by internal diodes. This product can handle input currents
DD
Note 8: V = 3V, f
= 125MHz (LTC2253) or 105MHz (LTC2252),
SAMPLE
DD
input range = 1V with differential drive.
P-P
of greater than 100mA below GND or above V without latchup.
DD
Note 9: Recommend operating conditions.
Note 4: V = 3V, f
= 125MHz (LTC2253) or 105MHz (LTC2252),
SAMPLE
DD
input range = 2V with differential drive, clock duty cycle stabilizer on,
P-P
unless otherwise noted.
22532fa
5
LTC2253/LTC2252
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2253: 8192 Point FFT,
f = 5MHz, –1dB, 2V Range,
IN
125Msps
LTC2253: Typical INL, 2V Range,
125Msps
LTC2253: Typical DNL, 2V Range,
125Msps
1.0
0.8
1.0
0.8
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
60
0
10
20
30
40
50
CODE
22532 G01
CODE
FREQUENCY (MHz)
22532 G03
22532 G02
LTC2253: 8192 Point FFT,
= 70MHz, –1dB, 2V Range,
LTC2253: 8192 Point FFT,
f = 140MHz, –1dB, 2V Range,
IN
125Msps
LTC2253: 8192 Point FFT,
= 30MHz, –1dB, 2V Range,
f
f
IN
IN
125Msps
125Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
60
0
10
20
30
40
50
60
60
0
10
20
30
40
50
0
10
20
30
40
50
FREQUENCY (MHz)
22532 G05
FREQUENCY (MHz)
22532 G06
FREQUENCY (MHz)
22532 G04
LTC2253: 8192 Point 2-Tone FFT,
= 28.2MHz and 26.8MHz, –1dB,
LTC2253: Grounded Input
Histogram, 125Msps
f
LTC2253: SNR vs Input Frequency,
–1dB, 2V Range, 125Msps
IN
2V Range, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
70000
60000
73
58717
72
71
50000
40000
30000
20000
10000
0
70
69
68
67
66
4249
2562
0
0
65
60
0
10
20
30
40
50
2045
2046
2047
50
100
200 250 300 350
2044
2048
0
150
FREQUENCY (MHz)
22532 G07
CODE
22532 G08
INPUT FREQUENCY (MHz)
22532 G09
22532fa
6
LTC2253/LTC2252
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2253: SFDR vs Input Frequency,
–1dB, 2V Range, 125Msps
LTC2253: SNR vs Input Level,
IN
LTC2253: SNR and SFDR vs Sample
f
= 70MHz, 2V Range, 125Msps
Rate, 2V Range, f = 5MHz, –1dB
IN
95
90
85
80
90
80
70
60
80
70
60
50
SFDR
dBFS
SNR
dBc
40
30
75
70
65
20
10
0
50
200
INPUT FREQUENCY (MHz)
300 350
0
50
100 150
250
0
20 40 60 80 100 120 140 160
SAMPLE RATE (Msps)
–50
–40
–20
–60
–10
0
–30
INPUT LEVEL (dBFS)
22532 G10
22532 G11
22532 G13
LTC2253: SFDR vs Input Level,
IN
LTC2253: I
vs Sample Rate,
VDD
f
= 70MHz, 2V Range, 125Msps
5MHz Sine Wave Input, –1dB
145
140
135
130
125
120
115
110
105
100
95
110
100
90
80
70
60
50
40
30
20
10
0
dBFS
2V RANGE
1V RANGE
dBc
0
20
40
60
80 100 120 140
–60
–50
–40
–30
–20
–10
0
INPUT LEVEL (dBFS)
SAMPLE RATE (Msps)
22532 G15
22532 G14
LTC2253: I
vs Sample Rate,
OVDD
5MHz Sine Wave Input, –1dB,
OV = 1.8V
LTC2253: SNR vs SENSE,
= 5MHz, –1dB
f
DD
IN
8
7
6
5
4
3
2
1
0
72
71
70
69
68
67
66
65
64
0
20
40
60
80 100 120 140
0.5
0.6
0.8 0.9 1.0 1.1
0.7
SENSE PIN (V)
0.4
SAMPLE RATE (Msps)
22532 G16
22532 G32
22532fa
7
LTC2253/LTC2252
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2252: 8192 Point FFT,
f = 5MHz, –1dB, 2V Range,
IN
105Msps
LTC2252: Typical INL, 2V Range,
105Msps
LTC2252: Typical DNL, 2V Range,
105Msps
1.0
0.8
1.0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
30
20
FREQUENCY (MHz)
40
0
10
50
22532 G17
CODE
CODE
22532 G18
22532 G19
LTC2252: 8192 Point FFT,
= 30MHz, –1dB, 2V Range,
LTC2252: 8192 Point FFT,
= 70MHz, –1dB, 2V Range,
LTC2252: 8192 Point FFT,
f = 140MHz, –1dB, 2V Range,
IN
105Msps
f
f
IN
IN
105Msps
105Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
30
20
FREQUENCY (MHz)
40
30
20
FREQUENCY (MHz)
40
30
20
FREQUENCY (MHz)
40
0
10
50
0
10
50
0
10
50
22532 G21
22532 G22
22532 G20
LTC2252: 8192 Point 2-Tone FFT,
= 28.2MHz and 26.8MHz, –1dB,
LTC2252: Grounded Input
Histogram, 105Msps
LTC2252: SNR vs Input Frequency,
–1dB, 2V Range, 105Msps
f
IN
2V Range, 105Msps
60000
50000
40000
30000
20000
10000
0
73
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
56911
72
71
70
69
68
67
66
6704
1913
0
0
65
2045
2046
2047
2044
2048
50
100
200 250 300 350
0
150
30
FREQUENCY (MHz)
40
0
10
20
50
CODE
22532 G24
22532 G25
INPUT FREQUENCY (MHz)
22532 G23
22532fa
8
LTC2253/LTC2252
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2252: SFDR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTC2252: SNR and SFDR vs
Sample Rate, 2V Range,
IN
LTC2252: SNR vs Input Level,
IN
f
= 70MHz, 2V Range, 105Msps
f
= 5MHz, –1dB
95
90
85
80
80
70
60
50
90
80
70
60
SFDR
dBFS
SNR
dBc
40
30
75
70
65
20
10
0
50
–50
–40
–20
0
20
40
60
80 100 120 140
–60
–10
0
200
INPUT FREQUENCY (MHz)
300 350
–30
0
50
100 150
250
SAMPLE RATE (Msps)
INPUT LEVEL (dBFS)
22532 G27
22532 G28
22532 G26
LTC2252: SFDR vs Input Level,
= 70MHz, 2V Range, 105Msps
LTC2252: I
vs Sample Rate,
VDD
f
IN
5MHz Sine Wave Input, –1dB
110
100
90
80
70
60
50
40
30
20
10
0
120
115
110
105
100
95
dBFS
2V RANGE
1V RANGE
dBc
90
85
80
75
0
–60
–50
–40
–30
–20
–10
0
20
40
60
80
100
120
INPUT LEVEL (dBFS)
SAMPLE RATE (Msps)
22532 G29
22532 G30
LTC2252: I
vs Sample Rate,
OVDD
LTC2252: SNR vs SENSE,
= 5MHz, –1dB
5MHz Sine Wave Input, –1dB,
f
OV = 1.8V
IN
DD
72
7
6
5
4
3
2
1
0
71
70
69
68
67
66
65
64
0.5
0.6
0.8 0.9 1.0 1.1
0.4
0.7
80
SAMPLE RATE (Msps)
120
0
20
40
60
100
22532 G33
SENSE PIN (V)
22532 G31
22532fa
9
LTC2253/LTC2252
U
U
U
PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input.
NC (Pins 12, 13): Do Not Connect These Pins.
AIN- (Pin 2): Negative Differential Analog Input.
D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
27): Digital Outputs. D11 is the MSB.
REFH(Pins3,4):ADCHighReference.Shorttogetherand
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypasstogroundwith0.1µFceramicchipcapacitor.OVDD
can be set to 0.5V to 3.6V.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
andturnstheclockdutycyclestabilizeron.2/3VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
V
DD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SENSE(Pin30):ReferenceProgrammingPin.Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connect-
ing SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package must be
soldered to ground.
22532fa
10
LTC2253/LTC2252
U
U
W
FUNCTIONAL BLOCK DIAGRA
+
A
IN
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
–
A
IN
V
CM
1.5V
REFERENCE
SHIFT REGISTER
AND CORRECTION
2.2µF
RANGE
SELECT
REFH
REFL
INTERNAL CLOCK SIGNALS
OV
OF
DD
REF
BUF
SENSE
D11
D0
CLOCK/DUTY
DIFF
REF
AMP
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
CYCLE
CONTROL
22532 F01
REFH
REFL
0.1µF
2.2µF
OGND
SHDN
CLK
M0DE
OE
1µF
1µF
Figure 1. Functional Block Diagram
W U
W
TI I G DIAGRA
Timing Diagram
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
N + 5
t
H
N + 1
t
L
CLK
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
N
D0-D11, OF
22532 TD01
22532fa
11
LTC2253/LTC2252
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APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Signal-to-Noise Ratio
Input Bandwidth
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Total Harmonic Distortion
Aperture Delay Time
Total harmonic distortion is the ratio of the RMS sum of all
harmonicsoftheinputsignaltothefundamentalitself.The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
ThetimefromwhenCLKreachesmid-supplytotheinstant
that the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
Thevariationintheaperturedelaytimefromconversionto
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the
secondthroughnthharmonics. TheTHDcalculatedinthis
data sheet uses all the harmonics up to the fifth.
SNRJITTER = –20log (2π • fIN • tJITTER
)
CONVERTER OPERATION
Intermodulation Distortion
As shown in Figure 1, the LTC2253/LTC2252 is a CMOS
pipelined multistep converter. The converter has six
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive applica-
tions, the analog inputs can be driven single-ended with
slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2253/LTC2252 has two phases of
operation, determined by the state of the CLK input pin.
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer func-
tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
22532fa
12
LTC2253/LTC2252
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APPLICATIO S I FOR ATIO
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
outputbytheresidueamplifier.Successivestagesoperate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
voltageisheldonthesamplingcapacitors.Duringthehold
phase when CLK is high, the sampling capacitors are
disconnectedfromtheinputandtheheldvoltageispassed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportionaltothechangeinvoltagebetweensampleswill
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
WhenCLKislow, theanaloginputissampleddifferentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
+
DNLwillremainunchanged.Forasingle-endedinput,AIN
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM
.
Common Mode Bias
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
thattheresultscanbeproperlycombinedinthecorrection
logic before being sent to the output buffer.
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin (Pin
31) may be used to provide the common mode bias level.
V
CM can be tied directly to the center tap of a transformer
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
LTC2253/LTC2252
V
DD
C
C
SAMPLE
3.5pF
Figure 2 shows an equivalent circuit for the LTC2253/
LTC2252 CMOS differential sample-and-hold. The analog
15Ω
15Ω
A
A
+
–
IN
IN
C
PARASITIC
1pF
inputsareconnectedtothesamplingcapacitors(CSAMPLE
)
V
DD
SAMPLE
3.5pF
through NMOS transistors. The capacitors shown at-
tached to each input (CPARASITIC) are the summation of all
other capacitance associated with each input.
C
PARASITIC
1pF
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
V
DD
CLK
22532 F02
Figure 2. Equivalent Input Circuit
22532fa
13
LTC2253/LTC2252
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APPLICATIO S I FOR ATIO
tosettheDCinputlevelorasareferenceleveltoanopamp
differentialdrivercircuit. TheVCM pinmustbebypassedto
ground close to the ADC with a 2.2µF or greater capacitor.
frequencyinputresponse;however,thelimitedgainband-
width of most op amps will limit the SFDR at high input
frequencies.
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2253/LTC2252 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 3.5pF
sampling capacitor to the input pin and start the sampling
period. ThesamplingperiodendswhenCLKrises, holding
the sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE);however, thisisnotalwayspossibleandthe
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
The25Ωresistorsand12pFcapacitorontheanaloginputs
serve two purposes: isolating the drive circuitry from the
V
CM
2.2µF
0.1µF T1
+
25Ω
A
IN
1:1
ANALOG
INPUT
LTC2253/
LTC2252
0.1µF
25Ω
25Ω
12pF
–
A
IN
25Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22532 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
V
CM
2.2µF
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
+
25Ω
25Ω
A
IN
LTC2253/
LTC2252
ANALOG
INPUT
+
+
Input Drive Circuits
CM
12pF
Figure 3 shows the LTC2253/LTC2252 being driven by an
RF transformer with a center tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Terminating on
the transformer secondary is desirable, as this provides a
common mode path for charging glitches caused by the
sample and hold. Figure 3 shows a 1:1 turns ratio trans-
former. Other turns ratios can be used if the source
impedance seen by the ADC does not exceed 100Ω for
each ADC input. A disadvantage of using a transformer is
the loss of low frequency response. Most small RF
transformers have poor performance at frequencies
below 1MHz.
–
–
–
A
IN
22532 F04
Figure 4. Differential Drive with an Amplifier
V
CM
2.2µF
1k
1k
25Ω
0.1µF
+
A
IN
ANALOG
INPUT
LTC2253/
LTC2252
12pF
–
25Ω
A
IN
22532 F05
0.1µF
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. Theadvantageofthismethodisthatitprovideslow
Figure 5. Single-Ended Drive
22532fa
14
LTC2253/LTC2252
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APPLICATIO S I FOR ATIO
U
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to gener-
ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun trans-
former gives better high frequency response than a flux
coupled center tapped transformer. The coupling capaci-
tors allow the analog inputs to be DC biased at 1.5V. In
Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
V
CM
Reference Operation
2.2µF
Figure 9 shows the LTC2253/LTC2252 reference circuitry
consisting of a 1.5V bandgap reference, a difference
amplifier and switching and control circuit. The internal
voltage reference can be configured for two pin selectable
input ranges of 2V (±1V differential) or 1V (±0.5V differ-
ential). Tying the SENSE pin to VDD selects the 2V range;
tying the SENSE pin to VCM selects the 1V range.
0.1µF
0.1µF
+
8.2nH
0.1µF
A
IN
ANALOG
INPUT
LTC2253/
LTC2252
25Ω
25Ω
T1
8.2nH
–
A
IN
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
22532 F08
V
CM
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
2.2µF
0.1µF
0.1µF
+
–
12Ω
A
8pF
A
IN
IN
ANALOG
INPUT
LTC2253/
LTC2252
LTC2253/LTC2252
0.1µF
25Ω
25Ω
T1
4Ω
V
CM
1.5V BANDGAP
REFERENCE
1.5V
12Ω
2.2µF
1V
0.5V
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22532 F06
RANGE
DETECT
AND
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
CONTROL
TIE TO V FOR 2V RANGE;
DD
CM
SENSE
REFH
TIE TO V FOR 1V RANGE;
RANGE = 2 • V
FOR
< 1V
SENSE
SENSE
BUFFER
0.5V < V
INTERNAL ADC
HIGH REFERENCE
V
CM
1µF
2.2µF
0.1µF
0.1µF
+
–
A
A
IN
IN
ANALOG
INPUT
LTC2253/
LTC2252
2.2µF
1µF
0.1µF
0.1µF
25Ω
25Ω
DIFF AMP
T1
REFL
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
INTERNAL ADC
LOW REFERENCE
22532 F07
22532 F09
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
Figure 9. Equivalent Reference Circuit
22532fa
15
LTC2253/LTC2252
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APPLICATIO S I FOR ATIO
The difference amplifier generates the high and low refer-
ence for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9.
In applications where jitter is critical, such as when digitiz-
ing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
inFigure10.Anexternalreferencecanbeusedbyapplying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
levelasclosetotheconverteraspossible. IftheSENSEpin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
CLEAN
SUPPLY
4.7µF
FERRITE
BEAD
0.1µF
1k
0.1µF
SINUSOIDAL
CLOCK INPUT
LTC2253/
LTC2252
CLK
NC7SVU04
1k
50Ω
1.5V
V
CM
22532 F11
2.2µF
12k
LTC2253/
LTC2252
Figure 11. Sinusoidal Single-Ended CLK Drive
0.75V
12k
SENSE
1µF
CLEAN
SUPPLY
4.7µF
22532 F10
FERRITE
BEAD
Figure 10. 1.5V Range ADC
0.1µF
CLK
LTC2253/
LTC2252
Input Range
100Ω
The input range can be set based on the application. The
2Vinputrangewillprovidethebestsignal-to-noiseperfor-
mance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 4.2dB.
22532 F12
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
levelsignal. Asinusoidalclockcanalsobeusedalongwith
a low jitter squaring circuit before the CLK pin (Figure 11).
ETC1-1T
CLK
LTC2253/
LTC2252
5pF-30pF
DIFFERENTIAL
CLOCK
The noise performance of the LTC2253/LTC2252 can
depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
resultinadditionalaperturejitterthatwillbeRMSsummed
with the inherent ADC aperture jitter.
INPUT
22532 F13
0.1µF
FERRITE
BEAD
V
CM
Figure 13. LVDS or PECL CLK Drive Using a Transformer
22532fa
16
LTC2253/LTC2252
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APPLICATIO S I FOR ATIO
U
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM,wherethenominalpowerlevelmustbeatleast6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
internal falling edge is generated by a phase-locked loop.
The input clock duty cycle can vary from 40% to 60% and
theclockdutycyclestabilizerwillmaintainaconstant50%
internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the
input clock.
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (±5%) duty cycle.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
areconsidered. Thecentertapmaybebypassedtoground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capaci-
tor at the input may result in peaking, and depending on
transmission line length may require a 10Ω to 20Ω ohm
series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
Table 1. Output Codes vs Input Voltage
+
–
A
IN
– A
D11 – D0
D11 – D0
IN
(2V Range)
OF
(Offset Binary)
(2’s Complement)
>+1.000000V
+0.999512V
+0.999024V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
Maximum and Minimum Conversion Rates
–0.999512V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
The maximum conversion rate for the LTC2253/LTC2252
is 125Msps (LTC2253) and 105Msps (LTC2252). The
lower limit of the LTC2253/LTC2252 sample rate is deter-
mined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operat-
ing frequency for the LTC2253/LTC2252 is 1Msps.
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND,
isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series
with the output makes the output appear as 50Ω to
external circuitry and may eliminate the need for external
damping resistors.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures
high performance even if the input clock has a non 50%
duty cycle. Using the clock duty cycle stabilizer is
recommended for most applications. To use the clock
dutycyclestabilizer, theMODEpinshouldbeconnectedto
1/3VDD or 2/3VDD using external resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2253/LTC2252 should drive a
minimal capacitive load to avoid possible interaction be-
tween the digital outputs and sensitive input circuitry. For
22532fa
This circuit uses the rising edge of the CLK pin to sample
theanaloginput. ThefallingedgeofCLKisignoredandthe
17
LTC2253/LTC2252
U
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APPLICATIO S I FOR ATIO
to the same power supply as for the logic being driven. For
exampleiftheconverterisdrivingaDSPpoweredbya1.8V
supply,thenOVDD shouldbetiedtothatsame1.8Vsupply.
LTC2253/LTC2252
OV
DD
0.5V
TO 3.6V
V
DD
V
DD
0.1µF
OVDD can be powered with any voltage from 500mV up to
3.6V.OGNDcanbepoweredwithanyvoltagefromGNDup
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
OV
DD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
Output Enable
Theoutputsmaybedisabledwiththeoutputenablepin,OE.
OE high disables all data outputs including OF. The data
access and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
22510 F14
Figure 14. Digital Ouput Buffer
full speed operation the capacitive load should be kept
under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normaloperation. ConnectingSHDNtoVDD andOEtoVDD
results in sleep mode, which powers down all circuitry
includingthereferenceandtypicallydissipates1mW.When
exiting sleep mode it will take milliseconds for the output
datatobecomevalidbecausethereferencecapacitorshave
torechargeandstabilize. ConnectingSHDNtoVDD andOE
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on,sothatrecoveryfromnapmodeisfasterthanthatfrom
sleepmode,typicallytaking100clockcycles.Inbothsleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Data Format
Using the MODE pin, the LTC2253/LTC2252 parallel
digital output can be selected for offset binary or 2’s
complement format. Connecting MODE to GND or 1/3VDD
selects offset binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format. An
external resistor divider can be used to set the 1/3VDD or
2/3VDD logic values. Table 2 shows the logic states for the
MODE pin.
Table 2. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stablizer
0
Offset Binary
Off
On
On
Off
1/3V
2/3V
Offset Binary
DD
DD
Grounding and Bypassing
2’s Complement
2’s Complement
V
DD
TheLTC2253/LTC2252requireaprintedcircuitboardwith
a clean, unbroken ground plane. A multilayer board with
an internal ground plane is recommended. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
High quality ceramic bypass capacitors should be used at
theVDD, OVDD, VCM, REFH, andREFLpins. Bypasscapaci-
tors must be located as close to the pins as possible. Of
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18
LTC2253/LTC2252
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APPLICATIO S I FOR ATIO
particularimportanceisthe0.1µFcapacitorbetweenREFH
and REFL. This capacitor should be placed as close to the
device as possible (1.5mm or less). A size 0402 ceramic
capacitor is recommended. The large 2.2µF capacitor
between REFH and REFL can be somewhat further away.
The traces connecting the pins and bypass capacitors
must be kept short and should be made as wide as
possible.
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
thefilterandtheADC. Ifyouaresensitivetoclose-inphase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
todrivedigitaldevicessuchasanFPGA, youshouldlocate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the re-
timing flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
The LTC2253/LTC2252 differential inputs should run par-
allel and close to each other. The input traces should be as
short as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2253/LTC2252 is
transferred from the die through the bottom-side exposed
pad and package leads onto the printed circuit board. For
good electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to a
ground plane of sufficient area.
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated
in the waveguides that exist between the layers of multi-
layer PCBs. The differential pairs must be close together,
and distanced from other signals. The differential pair
should be guarded on both sides with copper distanced at
least 3x the distance between the traces, and grounded
with vias no more than 1/4 inch apart.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix or
Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
mayoccurevenoverafractionofaninchisadvisable. You
must not allow the clock to overshoot the supplies or
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19
LTC2253/LTC2252
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22532fa
20
LTC2253/LTC2252
U
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APPLICATIO S I FOR ATIO
Silkscreen Top
Topside
Inner Layer 2 GND
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21
LTC2253/LTC2252
U
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APPLICATIO S I FOR ATIO
Inner Layer 3 Power
Topside
Silkscreen Bottom
22532fa
22
LTC2253/LTC2252
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
R = 0.115
0.75 ± 0.05
OR 0.35 × 45° CHAMFER
5.00 ± 0.10
(4 SIDES)
TYP
31 32
0.00 – 0.05
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ± 0.10
(4-SIDES)
(UH32) QFN 1004
0.200 REF
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
22532fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC2253/LTC2252
RELATED PARTS
PART NUMBER
LTC1747
LTC1748
LTC1749
LTC1750
LT1993
DESCRIPTION
COMMENTS
12-Bit, 80Msps ADC
72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
Up to 500MHz IF Undersampling, 87dB SFDR
Up to 500MHz IF Undersampling, 90dB SFDR
600MHz BW, 75dBc Distortion at 70MHz
14-Bit, 80Msps ADC
12-Bit, 80Msps Wideband ADC
14-Bit, 80Msps Wideband ADC
High Speed Differential Op Amp
12-Bit, 170Msps ADC
LTC2220
LTC2220-1
LTC2221
LTC2222
LTC2223
LTC2224
LTC2225
LTC2228
LTC2229
LTC2248
LTC2249
LTC2250
LTC2251
LTC2254
LTC2255
LTC2292
LTC2293
LTC2294
LTC2297
LTC2298
LTC2299
LT5512
890mW, 67.5dB SNR, 9mm x 9mm QFN Package
910mW, 67.5dB SNR, 9mm x 9mm QFN Package
660mW, 67.5dB SNR, 9mm x 9mm QFN Package
475mW, 67.9dB SNR, 7mm x 7mm QFN Package
366mW, 68dB SNR, 7mm x 7mm QFN Package
660mW, 67.5dB SNR, 7mm x 7mm QFN Package
60mW, 71.4dB SNR, 5mm x 5mm QFN Package
210mW, 71dB SNR, 5mm x 5mm QFN Package
230mW, 71.6dB SNR, 5mm x 5mm QFN Package
210mW, 74dB SNR, 5mm x 5mm QFN Package
230mW, 73dB SNR, 5mm x 5mm QFN Package
320mW, 61.6dB SNR, 5mm x 5mm QFN Package
395mW, 61.6dB SNR, 5mm x 5mm QFN Package
320mW, 72.5dB SNR, 5mm x 5mm QFN Package
395mW, 72.4dB SNR, 5mm x 5mm QFN Package
240mW, 71dB SNR, 9mm x 9mm QFN Package
410mW, 71dB SNR, 9mm x 9mm QFN Package
445mW, 70.6dB SNR, 9mm x 9mm QFN Package
240mW, 74dB SNR, 9mm x 9mm QFN Package
410mW, 74dB SNR, 9mm x 9mm QFN Package
445mW, 73dB SNR, 9mm x 9mm QFN Package
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
12-Bit, 185Msps ADC
12-Bit, 135Msps ADC
12-Bit, 105Msps ADC
12-Bit, 80Msps ADC
12-Bit, 135Msps ADC
12-Bit, 10Msps ADC
12-Bit, 65Msps ADC
12-Bit, 80Msps ADC
14-Bit, 65Msps ADC
14-Bit, 80Msps ADC
10-Bit, 105Msps ADC
10-Bit, 125Msps ADC
14-Bit, 105Msps ADC
14-Bit, 125Msps ADC
Dual 12-Bit, 40Msps ADC
Dual 12-Bit, 65Msps ADC
Dual 12-Bit, 80Msps ADC
Dual 14-Bit, 40Msps ADC
Dual 14-Bit, 65Msps ADC
Dual 14-Bit, 80Msps ADC
DC-3GHz High Signal Level Downconverting Mixer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
450MHz 1dB BW, 47dB OIP3, Digital Gain Control
10.5dB to 33dB in 1.5dB/Step
LT5522
600MHz to 2.7GHz High Linearity Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
22532fa
LT 0306 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
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