LTC2295CUP_技术文档

LTC2295

Dual 14-Bit, 10Msps

Low Power 3V ADC

U

FEATURES

DESCRIPTIO

■

Integrated Dual 14-Bit ADCs

The LTC^®2295 is a 14-bit 10Msps, low power dual 3V

A/Dconverterdesignedfordigitizinghighfrequency, wide

dynamic range signals. The LTC2295 is perfect for

demanding imaging and communications applications

with AC performance that includes 74.4dB SNR and 90dB

SFDR for signals well beyond the Nyquist frequency.

■

Sample Rate: 10Msps

■

Single 3V Supply (2.7V to 3.4V)

■

Low Power: 120mW

■

74.4dB SNR

90dB SFDR

■

110dB Channel Isolation

DC specs include ±1.2LSB INL (typ), ±0.5LSB DNL (typ)

■

Multiplexed or Separate Data Bus

and no missing codes over temperature. The transition

■

Flexible Input: 1V_P-Pto 2V_P-PRange

noise is a low 1LSB_RMS

.

■

575MHz Full Power Bandwidth S/H

■

Clock Duty Cycle Stabilizer

A single 3V supply allows low power operation. A separate

output supply allows the outputs to drive 0.5V to 3.6V

logic. An optional multiplexer allows both channels to

share a digital output bus.

■

Shutdown and Nap Modes

■

Pin Compatible Family

105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)

80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)

65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)

40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)

25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)

10Msps: LTC2290 (12-Bit), LTC2295 (14-Bit)

Asingle-endedCLKinputcontrolsconverteroperation.An

optional clock duty cycle stabilizer allows high perfor-

mance at full speed for a wide range of clock duty cycles.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

■

64-Pin (9mm × 9mm) QFN Package

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APPLICATIO S

■

Wireless and Wired Broadband Communication

■

Imaging Systems

■

Spectral Analysis

Portable Instrumentation

■

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TYPICAL APPLICATIO

Typical INL, 2V Range

OV

DD

2.0

1.5

+

14-BIT

PIPELINED

ADC CORE

INPUT

S/H

ANALOG

INPUT A

D13A

OUTPUT

DRIVERS

•

–

D0A

1.0

OGND

0.5

0

CLOCK/DUTY CYCLE

CONTROL

CLK A

CLK B

–0.5

–1.0

–1.5

–2.0

MUX

CLOCK/DUTY CYCLE

CONTROL

OV

DD

0

4096

8192

CODE

12288

16384

D13B

+

OUTPUT

DRIVERS

•

14-BIT

PIPELINED

ADC CORE

ANALOG

INPUT B

INPUT

S/H

2295 G02

D0B

–

OGND

2295 TA01

2295fa

1

LTC2295

W W

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U

W

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

OV = V (Notes 1, 2)

DD

Su^Dp^Dply Voltage (V_DD)................................................. 4V

Digital Output Ground Voltage (OGND) .......–0.3V to 1V

Analog Input Voltage (Note 3) ..... –0.3V to (V_DD+ 0.3V)

Digital Input Voltage .................... –0.3V to (V_DD+ 0.3V)

Digital Output Voltage................–0.3V to (OV_DD+ 0.3V)

Power Dissipation............................................ 1500mW

Operating Temperature Range

TOP VIEW

+

A

1

2

48 DA7

47 DA6

46 DA5

45 DA4

44 DA3

43 DA2

42 DA1

41 DA0

40 OFB

39 DB13

38 DB12

37 DB11

36 DB10

35 DB9

34 DB8

33 DB7

INA

–

A

INA

REFHA 3

REFHA 4

REFLA 5

REFLA 6

V

7

DD

CLKA 8

CLKB 9

65

LTC2295C ............................................... 0°C to 70°C

LTC2295I.............................................–40°C to 85°C

Storage Temperature Range ..................–65°C to 125°C

V

10

DD

REFLB 11

REFLB 12

REFHB 13

REFHB 14

–

A

15

16

INB

+

UP PACKAGE

64-LEAD (9mm × 9mm) PLASTIC QFN

T

= 125°C, θ = 20°C/W

JA

JMAX

EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB

ORDER PART

NUMBER

QFN PART*

MARKING

LTC2295CUP

LTC2295IUP

LTC2295UP

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

*The temperature grade is identified by a label on the shipping container.

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CO VERTER CHARACTERISTICS ^The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. (Note 4)

A

PARAMETER

CONDITIONS

MIN

14

TYP

MAX

UNITS

Bits

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

●

Differential Analog Input (Note 5)

Differential Analog Input

(Note 6)

–5

±1.2

±0.5

±2

±0.5

±10

±30

±5

±0.3

±2

1

5

1

LSB

–1

LSB

–12

–2.5

12

2.5

mV

Gain Error

External Reference

%FS

Offset Drift

µV/°C

ppm/°C

%FS

Full-Scale Drift

Internal Reference

External Reference

Gain Matching

Offset Matching

Transition Noise

mV

SENSE = 1V

LSB

RMS

2295fa

2

LTC2295

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A ALOG I PUT

The

●

denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T = 25°C. (Note 4)

A

SYMBOL

PARAMETER

Analog Input Range (A –A

CONDITIONS

MIN

TYP

±0.5 to ±1

1.5

MAX

UNITS

V

+

–

V

)

2.7V < V < 3.4V (Note 7)

●

IN

DD

+

–

Analog Input Common Mode (A +A )/2

Differential Input (Note 7)

Single Ended Input (Note 7)

1

1.9

2

V

IN,CM

IN

0.5

–1

–3

1.5

V

+

–

I

t

Analog Input Leakage Current

0V < A , A < V

DD

1

µA

ns

IN

SENSEA, SENSEB Input Leakage

MODE Input Leakage Current

0V < SENSEA, SENSEB < 1V

0V < MODE < V

3

SENSE

MODE

AP

3

DD

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Time Jitter

Analog Input Common Mode Rejection Ratio

Full Power Bandwidth

0

0.2

80

ps

RMS

JITTER

CMRR

dB

Figure 8 Test Circuit

575

MHz

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DY A IC ACCURACY

The

IN

●

denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T = 25°C. A = –1dBFS. (Note 4)

A

SYMBOL

PARAMETER

CONDITIONS

5MHz Input

70MHz Input

5MHz Input

70MHz Input

5MHz Input

70MHz Input

5MHz Input

70MHz Input

MIN

TYP

74.4

73.2

90

MAX

UNITS

dB

SNR

Signal-to-Noise Ratio

●

71.6

dB

SFDR

Spurious Free Dynamic Range

2nd or 3rd Harmonic

75

80

71

dB

85

dB

SFDR

Spurious Free Dynamic Range

4th Harmonic or Higher

90

dB

90

dB

S/(N+D)

Signal-to-Noise Plus Distortion Ratio

74.4

73.1

90

dB

I

Intermodulation Distortion

Crosstalk

f

= 4.3MHz, 4.6MHz

= 5MHz

dB

MD

IN

–110

dB

2295fa

3

LTC2295

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U

(Note 4)

I TER AL REFERE CE CHARACTERISTICS

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Output Voltage

Output Tempco

Line Regulation

Output Resistance

I

= 0

1.475 1.500 1.525

CM

OUT

±25

3

ppm/°C

mV/V

Ω

2.7V < V < 3.3V

DD

–1mA < I

< 1mA

4

OUT

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DIGITAL I PUTS A D DIGITAL OUTPUTS

The

●

denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T = 25°C. (Note 4)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

2

TYP

MAX

UNITS

LOGIC INPUTS (CLK, OE, SHDN, MUX)

V

High Level Input Voltage

Low Level Input Voltage

Input Current

V

= 3V

●

V

IH

IL

DD

IN

= 3V

0.8

10

I

= 0V to V

–10

µA

pF

IN

DD

C

Input Capacitance

(Note 7)

3

IN

LOGIC OUTPUTS

OV = 3V

DD

C

Hi-Z Output Capacitance

Output Source Current

Output Sink Current

OE = High (Note 7)

3

pF

mA

OZ

I

V

= 0V

= 3V

50

SOURCE

SINK

OUT

V

High Level Output Voltage

I = –10µA

O

2.995

2.99

V

OH

O

I = –200µA

●

2.7

V

Low Level Output Voltage

I = 10µA

0.005

0.09

V

OL

O

I = 1.6mA

0.4

O

OV = 2.5V

DD

V

High Level Output Voltage

Low Level Output Voltage

I = –200µA

2.49

0.09

V

OH

OL

O

I = 1.6mA

O

OV = 1.8V

DD

V

High Level Output Voltage

Low Level Output Voltage

I = –200µA

1.79

0.09

V

OH

OL

O

I = 1.6mA

O

2295fa

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LTC2295

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POWER REQUIRE E TS

The

●

denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T = 25°C. (Note 8)

A

SYMBOL

PARAMETER

CONDITIONS

(Note 9)

MIN

2.7

TYP

3

MAX

3.4

UNITS

V

Analog Supply Voltage

Output Supply Voltage

Supply Current

●

DD

OV

(Note 9)

0.5

3

3.6

V

DD

IV

Both ADCs at f

40

120

2

46

mA

mW

DD

S(MAX)

P

Power Dissipation

138

DISS

SHDN

NAP

Shutdown Power (Each Channel)

Nap Mode Power (Each Channel)

SHDN = H, OE = H, No CLK

SHDN = H, OE = L, No CLK

15

W U

TI I G CHARACTERISTICS ^The

●

denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T = 25°C. (Note 4)

A

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

t

Sampling Frequency

CLK Low Time

(Note 9)

●

1

10

MHz

s

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On (Note 7)

●

40

5

50

500

ns

L

t

CLK High Time

Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On (Note 7)

●

40

5

50

500

ns

H

t

Sample-and-Hold Aperture Delay

CLK to DATA Delay

0

ns

AP

D

C = 5pF (Note 7)

●

1.4

2.7

4.3

3.3

5

5.4

10

L

MUX to DATA Delay

C = 5pF (Note 7)

L

ns

MD

Data Access Time After OE↓

BUS Relinquish Time

C = 5pF (Note 7)

L

ns

(Note 7)

8.5

ns

Pipeline Latency

Cycles

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground with GND and OGND

wired together (unless otherwise noted).

Note 5: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 6: Offset error is the offset voltage measured from –0.5 LSB when

the output code flickers between 00 0000 0000 0000 and

11 1111 1111 1111.

Note 3: When these pin voltages are taken below GND or above V , they

will be clamped by internal diodes. This product can handle input currents

Note 7: Guaranteed by design, not subject to test.

DD

Note 8: V = 3V, f

= 10MHz, input range = 1V with differential

DD

SAMPLE

P-P

of greater than 100mA below GND or above V without latchup.

DD

drive. The supply current and power dissipation are the sum total for both

channels with both channels active.

Note 9: Recommended operating conditions.

Note 4: V = 3V, f

= 10MHz, input range = 2V with differential

DD

SAMPLE

P-P

drive, unless otherwise noted.

2295fa

5

LTC2295

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TYPICAL PERFOR A CE CHARACTERISTICS

Crosstalk vs Input Frequency

Typical INL, 2V Range

Typical DNL, 2V Range

2.0

1.5

1.0

0.8

–100

–105

0.6

1.0

0.4

–110

–115

0.5

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

–120

–125

–130

0

4096

8192

12288

16384

0

4096

8192

12288

16384

0

20

40

60

80

100

INPUT FREQUENCY (MHz)

CODE

2295 G02

2295 G03

2295 G01

8192 Point 2-Tone FFT, f = 4.3MHz

8192 Point FFT, f = 5.1MHz,

8192 Point FFT, f = 70.1MHz,

IN

and 4.6MHz, –1dB, 2V Range

–1dB, 2V Range

0

–10

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

–100

–110

–120

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

FREQUENCY (MHz)

2295 G05

2295 G04

2295 G06

SNR vs Input Frequency,

–1dB, 2V Range

SFDR vs Input Frequency, –1dB,

2V Range

Grounded Input Histogram

25000

20000

15000

10000

5000

0

75

74

73

72

71

70

69

68

67

66

65

100

95

22016

18803

90

85

80

75

70

13373

6919

3227

853

43

278

65

8179 8180 8181 8182 8183 8184 8185 8186

40

INPUT FREQUENCY (MHz)

60

70

0

10

20

30

50

0

20

30

40

50

60

70

10

CODE

INPUT FREQUENCY (MHz)

2295 G07

2295 G09

2295 G08

2295fa

6

LTC2295

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TYPICAL PERFOR A CE CHARACTERISTICS

SNR and SFDR vs Sample Rate,

SNR vs Input Level, f = 5MHz,

SFDR vs Input Level,

f = 5MHz, 2V Range

IN

2V Range, f = 5MHz, –1dB

2V Range

IN

120

110

100

90

80

70

60

50

40

30

20

10

0

80

70

60

100

90

dBFS

SFDR

dBc

50

40

30

20

10

80

dBc

100dBc SFDR

REFERENCE LINE

SNR

70

0

60

–60 –50

–30 –20 –10

0

–70

–40

0

2

4

6

8

10

12

14

–80

–40

–20

0

–60

SAMPLE RATE (Msps)

INPUT LEVEL (dBFS)

2295 G11

2295 G10

2295 G12

I

vs Sample Rate, 5MHz Sine

I

vs Sample Rate, 5MHz Sine

VDD

OVDD

Wave Input, –1dB

Wave Input, –1dB, O

= 1.8V

VDD

50

40

30

20

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2V RANGE

1V RANGE

0

2

4

6

8

10

12

14

0

4

6

8

10

12

14

2

SAMPLE RATE (Msps)

2295 G13

2295 G14

2295fa

7

LTC2295

U

PI FU CTIO S

+

A_INA(Pin 1): Channel A Positive Differential Analog

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEB selects an input

range of ±V_SENSEB. ±1V is the largest valid input range.

Input.

–

A_INA(Pin 2): Channel A Negative Differential Analog

Input.

V

_CMB(Pin 20): Channel B 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2µF ceramic chip

capacitor. Do not connect to V_CMA

REFHA (Pins 3, 4): Channel A High Reference. Short

together and bypass to Pins 5, 6 with a 0.1µF ceramic chip

capacitor as close to the pin as possible. Also bypass to

Pins 5, 6 with an additional 2.2µF ceramic chip capacitor

and to ground with a 1µF ceramic chip capacitor.

.

MUX (Pin 21): Digital Output Multiplexer Control. If MUX

isHigh,ChannelAcomesoutonDA0-DA13,OFA;Channel B

comes out on DB0-DB13, OFB. If MUX is Low, the output

busses are swapped and Channel A comes out on DB0-

DB13, OFB; Channel B comes out on DA0-DA13, OFA. To

multiplex both channels onto a single output bus, connect

MUX, CLKA and CLKB together.

REFLA (Pins 5, 6): Channel A Low Reference. Short

together and bypass to Pins 3, 4 with a 0.1µF ceramic chip

capacitor as close to the pin as possible. Also bypass to

Pins 3, 4 with an additional 2.2µF ceramic chip capacitor

and to ground with a 1µF ceramic chip capacitor.

SHDNB (Pin 22): Channel B Shutdown Mode Selection

Pin. Connecting SHDNB to GND and OEB to GND results

in normal operation with the outputs enabled. Connecting

SHDNB to GND and OEB to V_DDresults in normal opera-

tion with the outputs at high impedance. Connecting

SHDNB to V_DDand OEB to GND results in nap mode with

the outputs at high impedance. Connecting SHDNB to V_DD

and OEB to V_DDresults in sleep mode with the outputs at

high impedance.

V_DD(Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to

GND with 0.1µF ceramic chip capacitors.

CLKA (Pin 8): Channel A Clock Input. The input sample

starts on the positive edge.

CLKB (Pin 9): Channel B Clock Input. The input sample

starts on the positive edge.

REFLB (Pins 11, 12): Channel B Low Reference. Short

together and bypass to Pins 13, 14 with a 0.1µF ceramic

chipcapacitorasclosetothepinaspossible.Alsobypass

to Pins 13, 14 with an additional 2.2µF ceramic chip ca-

pacitor and to ground with a 1µF ceramic chip capacitor.

OEB (Pin 23): Channel B Output Enable Pin. Refer to

SHDNB pin function.

DB0 – DB13 (Pins 24 to 30, 33 to 39): Channel B Digital

Outputs. DB13 is the MSB.

REFHB (Pins 13, 14): Channel B High Reference. Short

together and bypass to Pins 11, 12 with a 0.1µF ceramic

chipcapacitorasclosetothepinaspossible.Alsobypass

to Pins 11, 12 with an additional 2.2µF ceramic chip ca-

pacitor and to ground with a 1µF ceramic chip capacitor.

OGND (Pins 31, 50): Output Driver Ground.

OV_DD(Pins 32, 49): Positive Supply for the Output Driv-

ers. Bypass to ground with 0.1µF ceramic chip capacitor.

OFB (Pin 40): Channel B Overflow/Underflow Output.

High when an overflow or underflow has occurred.

–

A_INB(Pin 15): Channel B Negative Differential Analog

Input.

DA0 – DA13 (Pins 41 to 48, 51 to 56): Channel A Digital

Outputs. DA13 is the MSB.

+

A_INB(Pin 16): Channel B Positive Differential Analog

Input.

OFA (Pin 57): Channel A Overflow/Underflow Output.

High when an overflow or underflow has occurred.

GND (Pins 17, 64): ADC Power Ground.

OEA (Pin 58): Channel A Output Enable Pin. Refer to

SHDNA pin function.

SENSEB(Pin19):ChannelBReferenceProgrammingPin.

ConnectingSENSEBtoV_CMBselectstheinternalreference

and a ±0.5V input range. V_DDselects the internal reference

2295fa

8

LTC2295

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PI FU CTIO S

SHDNA (Pin 59): Channel A Shutdown Mode Selection

Pin. Connecting SHDNA to GND and OEA to GND results

in normal operation with the outputs enabled. Connecting

SHDNA to GND and OEA to V_DDresults in normal opera-

tion with the outputs at high impedance. Connecting

SHDNA to V_DDand OEA to GND results in nap mode with

the outputs at high impedance. Connecting SHDNA to V_DD

and OEA to V_DDresults in sleep mode with the outputs at

high impedance.

lizer on. V_DDselects 2’s complement output format and

turns the clock duty cycle stabilizer off.

V

_CMA(Pin 61): Channel A 1.5V Output and Input Common

Mode Bias. Bypass to ground with 2.2µF ceramic chip

capacitor. Do not connect to V_CMB

.

SENSEA(Pin62):ChannelAReferenceProgrammingPin.

ConnectingSENSEAtoV_CMAselectstheinternalreference

and a ±0.5V input range. V_DDselects the internal reference

and a ±1V input range. An external reference greater than

0.5V and less than 1V applied to SENSEA selects an input

range of ±V_SENSEA. ±1V is the largest valid input range.

MODE (Pin 60): Output Format and Clock Duty Cycle

Stabilizer Selection Pin. Note that MODE controls both

channels. Connecting MODE to GND selects offset binary

output format and turns the clock duty cycle stabilizer off.

1/3 V_DDselects offset binary output format and turns the

clock duty cycle stabilizer on. 2/3 V_DDselects 2’s comple-

ment output format and turns the clock duty cycle stabi-

GND (Exposed Pad) (Pin 65): ADC Power Ground. The

Exposed Pad on the bottom of the package needs to be

soldered to ground.

U

W

FUNCTIONAL BLOCK DIAGRA

+

A

IN

INPUT

S/H

FIRST PIPELINED

ADC STAGE

SECOND PIPELINED

ADC STAGE

THIRD PIPELINED

ADC STAGE

FOURTH PIPELINED

ADC STAGE

FIFTH PIPELINED

ADC STAGE

SIXTH PIPELINED

ADC STAGE

–

A

IN

V

CM

1.5V

REFERENCE

SHIFT REGISTER

AND CORRECTION

2.2µF

RANGE

SELECT

REFH

REFL

INTERNAL CLOCK SIGNALS

OV

DD

REF

BUF

SENSE

OF

D13

D0

CLOCK/DUTY

CYCLE

CONTROL

DIFF

REF

AMP

CONTROL

LOGIC

OUTPUT

DRIVERS

•

2295 F01

REFH

REFL

0.1µF

2.2µF

OGND

SHDN

CLK

MODE

OE

1µF

Figure 1. Functional Block Diagram (Only One Channel is Shown)

2295fa

9

LTC2295

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W

TI I G DIAGRA S

Dual Digital Output Bus Timing

(Only One Channel is Shown)

t

AP

N + 4

N + 2

ANALOG

INPUT

N

N + 1

N + 3

N + 5

t

H

L

CLK

t

D

N – 5

N – 4

N – 3

N – 2

N – 1

N

D0-D13, OF

2295 TD01

Multiplexed Digital Output Bus Timing

t

APA

A + 4

A + 2

ANALOG

INPUT A

A

A + 1

B + 1

A + 3

B + 3

t

APB

B + 4

B + 2

ANALOG

INPUT B

B

t

H

L

CLKA = CLKB = MUX

A – 5

B – 5

A – 5

A – 4

B – 4

A – 3

B – 3

A – 2

B – 2

A – 1

D0A-D13A, OFA

D0B-D13B, OFB

t

MD

D

B – 5

A – 4

A – 3

A – 2

B – 1

2295 TD02

2295fa

10

LTC2295

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DYNAMIC PERFORMANCE

2fb + fa, 2fa – fb and 2fb – fa. The intermodulation

distortion is defined as the ratio of the RMS value of either

input tone to the RMS value of the largest 3rd order

intermodulation product.

Signal-to-Noise Plus Distortion Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the ADC output. The output is band limited

to frequencies above DC to below half the sampling

frequency.

Spurious Free Dynamic Range (SFDR)

Spurious free dynamic range is the peak harmonic or

spurious noise that is the largest spectral component

excluding the input signal and DC. This value is expressed

in decibels relative to the RMS value of a full scale input

signal.

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC.

Input Bandwidth

The input bandwidth is that input frequency at which the

amplitude of the reconstructed fundamental is reduced by

3dB for a full scale input signal.

Total Harmonic Distortion

Aperture Delay Time

Total harmonic distortion is the ratio of the RMS sum of all

harmonicsoftheinputsignaltothefundamentalitself.The

out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency. THD is

expressed as:

The time from when CLK reaches midsupply to the instant

that the input signal is held by the sample and hold circuit.

Aperture Delay Jitter

THD = 20Log ( )

√(V2²+ V3²+ V4²+ . . . Vn²)/V1

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through Vn are the amplitudes of the

secondthroughnthharmonics. TheTHDcalculatedinthis

data sheet uses all the harmonics up to the fifth.

Thevariationintheaperturedelaytimefromconversionto

conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

SNR_JITTER= –20log (2π • f_IN• t_JITTER

)

Crosstalk

Intermodulation Distortion

Crosstalk is the coupling from one channel (being driven

by a full-scale signal) onto the other channel (being driven

by a –1dBFS signal).

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused by

the presence of another sinusoidal input at a different

frequency.

CONVERTER OPERATION

As shown in Figure 1, the LTC2295 is a dual CMOS

pipelined multistep converter. The converter has six

pipelined ADC stages; a sampled analog input will result in

a digitized value five cycles later (see the Timing Diagram

section). For optimal AC performance the analog inputs

should be driven differentially. For cost sensitive

If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer func-

tion can create distortion products at the sum and differ-

ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,

etc. The 3rd order intermodulation products are 2fa + fb,

2295fa

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applications, theanaloginputscanbedrivensingle-ended

with slightly worse harmonic distortion. The CLK input is

single-ended. The LTC2295 has two phases of operation,

determined by the state of the CLK input pin.

third, fourth and fifth stages, resulting in a fifth stage

residue that is sent to the sixth stage ADC for final

evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally synchronized such

thattheresultscanbeproperlycombinedinthecorrection

logic before being sent to the output buffer.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue amplifier.

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is amplified and

outputbytheresidueamplifier.Successivestagesoperate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and vice versa.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample/Hold Operation

Figure 2 shows an equivalent circuit for the LTC2295

CMOSdifferentialsample-and-hold.Theanaloginputsare

connected to the sampling capacitors (C_SAMPLE) through

NMOStransistors. Thecapacitorsshownattachedtoeach

input (C_PARASITIC) are the summation of all other capaci-

tance associated with each input.

WhenCLKislow, theanaloginputissampleddifferentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that CLK transitions from low to high, the sampled input is

held. While CLK is high, the held input voltage is buffered

by the S/H amplifier which drives the first pipelined ADC

stage. The first stage acquires the output of the S/H during

this high phase of CLK. When CLK goes back low, the first

stage produces its residue which is acquired by the

second stage. At the same time, the input S/H goes back

to acquiring the analog input. When CLK goes back high,

the second stage produces its residue which is acquired

by the third stage. An identical process is repeated for the

During the sample phase when CLK is low, the transistors

connect the analog inputs to the sampling capacitors and

they charge to and track the differential input voltage.

When CLK transitions from low to high, the sampled input

voltageisheldonthesamplingcapacitors.Duringthehold

phase when CLK is high, the sampling capacitors are

disconnectedfromtheinputandtheheldvoltageispassed

to the ADC core for processing. As CLK transitions from

LTC2295

V

DD

C

SAMPLE

4pF

15Ω

+

–

A

IN

C

PARASITIC

1pF

SAMPLE

4pF

C

PARASITIC

1pF

V

DD

CLK

2295 F02

Figure 2. Equivalent Input Circuit

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the sampling capacitor. Ideally the input circuitry should

be fast enough to fully charge the sampling capacitor

during the sampling period 1/(2F_ENCODE); however, this is

not always possible and the incomplete settling may

degradetheSFDR. Thesamplingglitchhasbeendesigned

to be as linear as possible to minimize the effects of

incomplete settling.

high to low, the inputs are reconnected to the sampling

capacitors to acquire a new sample. Since the sampling

capacitors still hold the previous sample, a charging glitch

proportionaltothechangeinvoltagebetweensampleswill

be seen at this time. If the change between the last sample

and the new sample is small, the charging glitch seen at

the input will be small. If the input change is large, such as

the change seen with input frequencies near Nyquist, then

a larger charging glitch will be seen.

For the best performance, it is recommended to have a

source impedance of 100Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

Single-Ended Input

For cost sensitive applications, the analog inputs can be

driven single-ended. With a single-ended input the har-

monic distortion and INL will degrade, but the SNR and

Input Drive Circuits

+

DNLwillremainunchanged.Forasingle-endedinput,A_IN

Figure 3 shows the LTC2295 being driven by an RF

transformer with a center tapped secondary. The second-

ary center tap is DC biased with V_CM, setting the ADC input

signal at its optimum DC level. Terminating on the trans-

former secondary is desirable, as this provides a common

modepathforchargingglitchescausedbythesampleand

hold. Figure 3 shows a 1:1 turns ratio transformer. Other

turns ratios can be used if the source impedance seen by

the ADC does not exceed 100Ω for each ADC input. A

disadvantage of using a transformer is the loss of low

frequency response. Most small RF transformers have

poor performance at frequencies below 1MHz.

should be driven with the input signal and A_IN^–should be

connected to V_CMor a quiet reference voltage between

0.5V and 1.5V.

Common Mode Bias

For optimal performance the analog inputs should be

driven differentially. Each input should swing ±0.5V for

the 2V range or ±0.25V for the 1V range, around a

common mode voltage of 1.5V. The V_CMoutput pin may

be used to provide the common mode bias level. V_CMcan

be tied directly to the center tap of a transformer to set the

DC input level or as a reference level to an op amp

differentialdrivercircuit. TheV_CMpinmustbebypassedto

ground close to the ADC with a 2.2µF or greater capacitor.

V

CM

2.2µF

0.1µF T1

+

–

25Ω

A

IN

Input Drive Impedance

1:1

ANALOG

INPUT

LTC2295

0.1µF

25Ω

As with all high performance, high speed ADCs, the

dynamic performance of the LTC2295 can be influenced

by the input drive circuitry, particularly the second and

third harmonics. Source impedance and reactance can

influence SFDR. At the falling edge of CLK, the sample-

and-holdcircuitwillconnectthe4pFsamplingcapacitorto

the input pin and start the sampling period. The sampling

period ends when CLK rises, holding the sampled input on

12pF

A

IN

25Ω

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

2295 F03

Figure 3. Single-Ended to Differential Conversion

Using a Transformer

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Figure 4 demonstrates the use of a differential amplifier to

convert a single ended input signal into a differential input

signal. Theadvantageofthismethodisthatitprovideslow

frequencyinputresponse;however,thelimitedgainband-

width of most op amps will limit the SFDR at high input

frequencies.

Reference Operation

Figure6showstheLTC2295referencecircuitryconsisting

of a 1.5V bandgap reference, a difference amplifier and

switching and control circuit. The internal voltage refer-

ence can be configured for two pin selectable input ranges

of2V(±1Vdifferential)or1V(±0.5Vdifferential).Tyingthe

SENSE pin to V_DDselects the 2V range; tying the SENSE

pin to V_CMselects the 1V range.

V

CM

2.2µF

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

The 1.5V bandgap reference serves two functions: its

output provides a DC bias point for setting the common

mode voltage of any external input circuitry; additionally,

the reference is used with a difference amplifier to gener-

ate the differential reference levels needed by the internal

ADC circuitry. An external bypass capacitor is required for

the 1.5V reference output, V_CM. This provides a high

frequency low impedance path to ground for internal and

external circuitry.

+

25Ω

A

IN

LTC2295

ANALOG

INPUT

+

CM

12pF

–

A

IN

2295 F04

Figure 4. Differential Drive with an Amplifier

Figure 5 shows a single-ended input circuit. The imped-

ance seen by the analog inputs should be matched. This

circuit is not recommended if low distortion is required.

LTC2295

4Ω

V

CM

1.5V BANDGAP

REFERENCE

1.5V

2.2µF

1V

0.5V

V

CM

RANGE

DETECT

AND

2.2µF

1k

25Ω

0.1µF

+

–

A

IN

CONTROL

ANALOG

INPUT

LTC2295

TIE TO V FOR 2V RANGE;

DD

SENSE

REFH

TIE TO V FOR 1V RANGE;

CM

RANGE = 2 • V

FOR

< 1V

SENSE

0.5V < V

SENSE

BUFFER

12pF

INTERNAL ADC

HIGH REFERENCE

25Ω

1µF

A

2295 F05

0.1µF

2.2µF

1µF

0.1µF

DIFF AMP

Figure 5. Single-Ended Drive

REFL

The25Ωresistorsand12pFcapacitorontheanaloginputs

serve two purposes: isolating the drive circuitry from the

sample-and-hold charging glitches and limiting the

wideband noise at the converter input.

INTERNAL ADC

LOW REFERENCE

2295 F06

Figure 6. Equivalent Reference Circuit

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The difference amplifier generates the high and low refer-

ence for the ADC. High speed switching circuits are

connected to these outputs and they must be externally

bypassed. Each output has two pins. The multiple output

pins are needed to reduce package inductance. Bypass

capacitors must be connected as shown in Figure 6. Each

ADC channel has an independent reference with its own

bypass capacitors. The two channels can be used with the

same or different input ranges.

Driving the Clock Input

The CLK inputs can be driven directly with a CMOS or TTL

levelsignal.Adifferentialclockcanalsobeusedalongwith

a low jitter CMOS converter before the CLK pin (Figure 8).

CLEAN

SUPPLY

4.7µF

FERRITE

BEAD

0.1µF

Other voltage ranges between the pin selectable ranges

can be programmed with two external resistors as shown

in Figure 7. An external reference can be used by applying

its output directly or through a resistor divider to SENSE.

It is not recommended to drive the SENSE pin with a logic

device. The SENSE pin should be tied to the appropriate

levelasclosetotheconverteraspossible. IftheSENSEpin

is driven externally, it should be bypassed to ground as

close to the device as possible with a 1µF ceramic capacitor.

Forthebestchannelmatching, connectanexternalreference

to SENSEA and SENSEB.

CLK

LTC2295

100Ω

2295 F08

IF LVDS USE FIN1002 OR FIN1018.

FOR PECL, USE AZ1000ELT21 OR SIMILAR

Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter

The noise performance of the LTC2295 can depend on the

clock signal quality as much as on the analog input. Any

noise present on the clock signal will result in additional

aperture jitter that will be RMS summed with the inherent

ADC aperture jitter.

1.5V

V

CM

2.2µF

12k

LTC2295

It is recommended that CLKA and CLKB are shorted

together and driven by the same clock source. If a small

time delay is desired between when the two channels

sample the analog inputs, CLKA and CLKB can be driven

by two different signals. If this delay exceeds 1ns, the

performance of the part may degrade. CLKA and CLKB

should not be driven by asynchronous signals.

0.75V

12k

SENSE

1µF

2295 F7

Figure 7. 1.5V Range ADC

Input Range

The input range can be set based on the application. The

2Vinputrangewillprovidethebestsignal-to-noiseperfor-

mance while maintaining excellent SFDR. The 1V input

range will have better SFDR performance, but the SNR will

degrade by 5.8dB.

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Table 1. Output Codes vs Input Voltage

Maximum and Minimum Conversion Rates

+

–

A

– A

D13 – D0

(OFFSET BINARY)

D13 – D0

(2’s COMPLEMENT)

IN

ThemaximumconversionratefortheLTC2295is10Msps.

For the ADC to operate properly, the CLK signal should

have a 50% (±10%) duty cycle. Each half cycle must have

at least 40ns for the ADC internal circuitry to have enough

settling time for proper operation.

(2V RANGE)

OF

>+1.000000V

+0.999878V

+0.999756V

1

0

11 1111 1111 1111

11 1111 1111 1110

01 1111 1111 1111

01 1111 1111 1110

+0.000122V

0.000000V

–0.000122V

–0.000244V

0

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1111

11 1111 1111 1110

An optional clock duty cycle stabilizer circuit can be used

if the input clock has a non 50% duty cycle. This circuit

uses the rising edge of the CLK pin to sample the analog

input. The falling edge of CLK is ignored and the internal

falling edge is generated by a phase-locked loop. The

input clock duty cycle can vary and the clock duty cycle

stabilizerwillmaintainaconstant50%internaldutycycle.

If the clock is turned off for a long period of time, the duty

cycle stabilizer circuit will require a hundred clock cycles

for the PLL to lock onto the input clock. To use the clock

duty cycle stabilizer, the MODE pin should be connected

to 1/3V_DDor 2/3V_DDusing external resistors. The MODE

pin controls both Channel A and Channel B—the duty

cycle stabilizer is either on or off for both channels.

–0.999878V

–1.000000V

<–1.000000V

0

1

00 0000 0000 0001

00 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0000

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OV_DDand OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50Ω to external

circuitry and may eliminate the need for external damping

resistors.

The lower limit of the LTC2295 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architectureofthisADCreliesonstoringanalogsignalson

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating fre-

quency for the LTC2295 is 1Msps.

LTC2295

OV

DD

0.5V

TO 3.6V

V

DD

V

DD

0.1µF

OV

DD

DATA

FROM

LATCH

PREDRIVER

LOGIC

43Ω

TYPICAL

DATA

OUTPUT

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits, and the overflow bit.

OE

OGND

2295 F9

Figure 9. Digital Output Buffer

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Aswithallhighspeed/highresolutionconverters, thedigi-

tal output loading can affect the performance. The digital

outputs of the LTC2295 should drive a minimal capacitive

load to avoid possible interaction between the digital out-

puts and sensitive input circuitry. The output should be

buffered with a device such as an ALVCH16373 CMOS

latch. For full speed operation the capacitive load should

be kept under 10pF.

to the same power supply as for the logic being driven. For

example,iftheconverterisdrivingaDSPpoweredbya1.8V

supply,thenOV_DDshouldbetiedtothatsame1.8Vsupply.

OV_DDcan be powered with any voltage from 500mV up to

3.6V.OGNDcanbepoweredwithanyvoltagefromGNDup

to 1V and must be less than OV_DD. The logic outputs will

swing between OGND and OV_DD.

Lower OV_DDvoltages will also help reduce interference

from the digital outputs.

Output Enable

Theoutputsmaybedisabledwiththeoutputenablepin,OE.

OE high disables all data outputs including OF. Channels

A and B have independent output enable pins (OEA, OEB).

Data Format

Using the MODE pin, the LTC2295 parallel digital output

can be selected for offset binary or 2’s complement

format. Note that MODE controls both Channel A and

Channel B. Connecting MODE to GND or 1/3V_DDselects

offset binary output format. Connecting MODE to

2/3V_DDor V_DDselects 2’s complement output format. An

external resistor divider can be used to set the 1/3V_DDor

2/3V_DDlogic values. Table 2 shows the logic states for the

MODE pin.

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes

to conserve power. Connecting SHDN to GND results in

normaloperation. ConnectingSHDNtoV_DDandOEtoV_DD

results in sleep mode, which powers down all circuitry

includingthereferenceandtypicallydissipates1mW.When

exiting sleep mode it will take milliseconds for the output

datatobecomevalidbecausethereferencecapacitorshave

torechargeandstabilize. ConnectingSHDNtoV_DDandOE

to GND results in nap mode, which typically dissipates

30mW. In nap mode, the on-chip reference circuit is kept

on,sothatrecoveryfromnapmodeisfasterthanthatfrom

sleepmode,typicallytaking100clockcycles.Inbothsleep

and nap modes, all digital outputs are disabled and enter

the Hi-Z state.

Table 2. MODE Pin Function

CLOCK DUTY

MODE PIN

OUTPUT FORMAT

CYCLE STABILIZER

0

Offset Binary

Off

On

Off

1/3V

2/3V

Offset Binary

DD

2’s Complement

V

DD

Channels A and B have independent SHDN pins (SHDNA,

SHDNB). Channel A is controlled by SHDNA and OEA, and

ChannelBiscontrolledbySHDNBandOEB.Thenap,sleep

andoutputenablemodesofthetwochannelsarecompletely

independent, so it is possible to have one channel operat-

ing while the other channel is in nap or sleep mode.

Overflow Bit

When OF outputs a logic high the converter is either

overranged or underranged.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OV_DD, should be tied

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High quality ceramic bypass capacitors should be used

at the V_DD, OV_DD, V_CM, REFH, and REFL pins. Bypass

capacitorsmustbelocatedasclosetothepinsaspossible.

Of particular importance is the 0.1µF capacitor between

REFH and REFL. This capacitor should be placed as close

to the device as possible (1.5mm or less). A size 0402

ceramic capacitor is recommended. The large 2.2µF

capacitor between REFH and REFL can be somewhat

further away. The traces connecting the pins and bypass

capacitorsmustbekeptshortandshouldbemadeaswide

as possible.

Digital Output Multiplexer

ThedigitaloutputsoftheLTC2295canbemultiplexedonto

a single data bus. The MUX pin is a digital input that swaps

the two data busses. If MUX is High, Channel A comes out

on DA0-DA13, OFA; Channel B comes out on DB0-DB13,

OFB. If MUX is Low, the output busses are swapped and

ChannelAcomesoutonDB0-DB13,OFB;ChannelBcomes

out on DA0-DA13, OFA. To multiplex both channels onto

asingleoutputbus,connectMUX,CLKAandCLKBtogether

(see the Timing Diagram for the multiplexed mode). The

multiplexed data is available on either data bus—the un-

used data bus can be disabled with its OE pin.

The LTC2295 differential inputs should run parallel and

close to each other. The input traces should be as short as

possible to minimize capacitance and to minimize noise

pickup.

Grounding and Bypassing

The LTC2295 requires a printed circuit board with a clean,

unbroken ground plane. A multilayer board with an inter-

nal ground plane is recommended. Layout for the printed

circuit board should ensure that digital and analog signal

linesareseparatedasmuchaspossible. Inparticular, care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC.

Heat Transfer

Most of the heat generated by the LTC2295 is transferred

from the die through the bottom-side exposed pad and

package leads onto the printed circuit board. For good

electrical and thermal performance, the exposed pad

should be soldered to a large grounded pad on the PC

board. It is critical that all ground pins are connected to a

ground plane of sufficient area.

2295fa

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D D

O V

O G N D

D A 8

D A 9

D A 1 0

D A 1 1

D A 1 2

D A 1 3

3 2

4 9

5 0

5 1

5 2

5 3

5 4

5 5

5 6

5 7

5 8

5 9

6 0

6 1

6 2

6 3

6 4

O G N D

3 1

D B 6

3 0

D B 5

2 9

D B 4

2 8

D B 3

2 7

D B 2

2 6

D B 1

2 5

O F A

O E A

S H D N A

D B 0

2 4

O E B

2 3

S H D N B

2 2

M O D E

V C M A

S E N S E A

V

G N D

M U X

2 1

V C M B

2 0

S E N S E B

1 9

D D

V

D D

1 8

G N D

1 7

2295fa

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Silkscreen Top

Top Side

2295fa

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Inner Layer 2 GND

Inner Layer 3 Power

2295fa

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Bottom Side

2295fa

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LTC2295

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PACKAGE DESCRIPTIO

UP Package

64-Lead Plastic QFN (9mm × 9mm)

(Reference LTC DWG # 05-08-1705)

0.70 ±0.05

7.15 ±0.05

8.10 ±0.05 9.50 ±0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.75 ± 0.05

R = 0.115

TYP

9 .00 ± 0.10

(4 SIDES)

63 64

0.40 ± 0.10

PIN 1 TOP MARK

(SEE NOTE 5)

1

2

PIN 1

CHAMFER

7.15 ± 0.10

(4-SIDES)

(UP64) QFN 1003

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5

2. ALL DIMENSIONS ARE IN MILLIMETERS

BOTTOM VIEW—EXPOSED PAD

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

4. EXPOSED PAD SHALL BE SOLDER PLATED

5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

6. DRAWING NOT TO SCALE

2295fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

23

LTC2295

RELATED PARTS

PART NUMBER

LTC2220

LTC2221

LTC2222

LTC2223

LTC2224

LTC2225

LTC2226

LTC2227

LTC2228

LTC2230

LTC2231

LTC2232

LTC2233

LTC2245

LTC2246

LTC2247

LTC2248

LTC2249

LTC2290

LTC2291

LTC2292

LTC2293

LTC2296

LTC2297

LTC2298

DESCRIPTION

COMMENTS

12-Bit, 170Msps ADC

12-Bit, 135Msps ADC

12-Bit, 105Msps ADC

12-Bit, 80Msps ADC

12-Bit, 135Msps ADC

12-Bit, 10Msps ADC

12-Bit, 25Msps ADC

12-Bit, 40Msps ADC

12-Bit, 65Msps ADC

10-Bit, 170Msps ADC

10-Bit, 135Msps ADC

10-Bit, 105Msps ADC

10-Bit, 80Msps ADC

14-Bit, 10Msps ADC

14-Bit, 25Msps ADC

14-Bit, 40Msps ADC

14-Bit, 65Msps ADC

14-Bit, 80Msps ADC

12-Bit, Dual, 10Msps ADC

12-Bit, Dual, 25Msps ADC

12-Bit, Dual, 40Msps ADC

12-Bit, Dual, 65Msps ADC

14-Bit, Dual, 25Msps ADC

14-Bit, Dual, 40Msps ADC

14-Bit, Dual, 65Msps ADC

890mW, 67.5dB SNR, 9mm × 9mm QFN Package

630mW, 67.5dB SNR, 9mm × 9mm QFN Package

475mW, 67.9dB SNR, 7mm × 7mm QFN Package

366mW, 68dB SNR, 7mm × 7mm QFN Package

630mW, 67.5dB SNR, 7mm × 7mm QFN Package

60mW, 71.4dB SNR, 5mm × 5mm QFN Package

75mW, 71.4dB SNR, 5mm × 5mm QFN Package

120mW, 71.4dB SNR, 5mm × 5mm QFN Package

205mW, 71.3dB SNR, 5mm × 5mm QFN Package

890mW, 67.5dB SNR, 9mm × 9mm QFN Package

630mW, 67.5dB SNR, 9mm × 9mm QFN Package

475mW, 61.3dB SNR, 7mm × 7mm QFN Package

366mW, 61.3dB SNR, 7mm × 7mm QFN Package

60mW, 74.4dB SNR, 5mm × 5mm QFN Package

75mW, 74.5dB SNR, 5mm × 5mm QFN Package

120mW, 74.4dB SNR, 5mm × 5mm QFN Package

205mW, 74.3dB SNR, 5mm × 5mm QFN Package

222mW, 73dB SNR, 5mm × 5mm QFN Package

120mW, 71.3dB SNR, 9mm × 9mm QFN Package

150mW, 74.5dB SNR, 9mm × 9mm QFN Package

235mW, 74.4dB SNR, 9mm × 9mm QFN Package

400mW, 74.3dB SNR, 9mm × 9mm QFN Package

150mW, 74.5dB SNR, 9mm × 9mm QFN Package

235mW, 74.4dB SNR, 9mm × 9mm QFN Package

400mW, 74.3dB SNR, 9mm × 9mm QFN Package

2295fa

RD/LT 0106 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2295CUP
厂家：	Linear
描述：	Dual 14-Bit, 10Msps Low Power 3V ADC 双通道14位， 10MSPS低功耗ADC 3V 转换器模数转换器
文件：	总24页 (文件大小：668K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2295CUP [Linear]

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