LTC2615IGNTRPBF_技术文档

LTC2605/LTC2615/LTC2625

Octal 16-/14-/12-Bit

Rail-to Rail DACs in 16-Lead SSOP

FEATURES

DESCRIPTION

The LTC^®2605/LTC2615/LTC2625 are octal 16-, 14- and

12-bit, 2.7V to 5.5V rail-to-rail voltage-output DACs

in 16-lead narrow SSOP packages. They have built-in

high performance output buffers and are guaranteed

monotonic.

n

Smallest Pin-Compatible Octal DACs:

LTC2605: 16 Bits

LTC2615: 14 Bits

LTC2625: 12 Bits

n

Guaranteed Monotonic Over Temperature

2

n

400kHz I C Interface

These parts establish new board-density benchmarks

for 16-/14-bit DACs and advance performance standards

for output drive, crosstalk and load regulation in single

supply, voltage-output multiples.

n

Wide 2.7V to 5.5V Supply Range

n

Low Power Operation: 250μA per DAC at 3V

n

Individual Channel Power-Down to 1μA (Max)

n

Ultralow Crosstalk Between DACs (<10μV)

2

n

Thepartsusethe2-wireI Ccompatibleserialinterface.The

High Rail-to-Rail Output Drive ( 15mA, Min)

n

LTC2605/LTC2615/LTC2625 operate in both the standard

mode (maximum clock rate of 100kHz) and the fast mode

(maximum clock rate of 400kHz).

Double-Buffered Digital Inputs

27 Selectable Addresses

n

LTC2605/LTC2615/LTC2625: Power-On Reset to

Zero-Scale

The LTC2605/LTC2615/LTC2625 incorporate a power-on

resetcircuit.Duringpower-up,thevoltageoutputsriseless

than10mVabovezero-scale;andafterpower-up,theystay

at zero-scale until a valid write and update take place. The

power-on reset circuit resets the LTC2605-1/\LTC2615-1/

LTC2625-1 to mid-scale. The voltage output stays at mid-

scale until a valid write and update takes place.

n

LTC2605-1/LTC2615-1/LTC2625-1: Power-On Reset

to Mid-Scale

Tiny 16-Lead Narrow SSOP Package

n

APPLICATIONS

n

Mobile Communications

n

Process Control and Industrial Automation

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

Instrumentation

Automatic Test Equipment

n

TYPICAL APPLICATION

GND

1

16

15

V

CC

DAC A

DAC H

V

2

Differential Nonlinearity (LTC2605)

OUT A

OUT H

1.0

V

= 5V

REF

CC

0.8

0.6

= 4.096V

DAC B

DAC C

DAC G

DAC F

V

OUT G

V

OUT F

3

4

14

13

OUT B

OUT C

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

DAC D

DAC E

V

5

12

OUT D

OUT E

REF

CA0

CA1

6

7

11

10

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

0

16384

32768

CODE

49152

65535

CA2

2605 G02

9

SDA

SCL

8

2605/15/25 BD

2605fa

1

LTC2605/LTC2615/LTC2625

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Any Pin to GND............................................ –0.3V to 6V

Any Pin to V ............................................. –6V to 0.3V

GND

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

CC

Maximum Junction Temperature .......................... 125°C

Operating Temperature Range

V

OUT A

OUT B

OUT C

OUT H

OUT G

OUT F

OUT E

LTC2605C/LTC2615C/LTC2625C ............. 0°C to 70°C

LTC2605C-1/LTC2615C-1/LTC2625C-1.... 0°C to 70°C

LTC2605I/LTC2615I/LTC2625I.............–40°C to 85°C

LTC2605I-1/LTC2615I-1/LTC2625I-1....–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)...................300°C

OUT D

REF

CA0

CA1

SDA

CA2

SCL

GN PACKAGE

16-LEAD PLASTIC SSOP

T

JMAX

= 125°C, θ = 160°C/W

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC2605CGN#PBF

LTC2605CGN-1#PBF

LTC2605IGN#PBF

LTC2605IGN-1#PBF

LTC2615CGN#PBF

LTC2615CGN-1#PBF

LTC2615IGN#PBF

LTC2615IGN-1#PBF

LTC2625CGN#PBF

LTC2625CGN-1#PBF

LTC2625IGN#PBF

LTC2625IGN-1#PBF

TAPE AND REEL

PART MARKING

2605

PACKAGE DESCRIPTION

16-Lead Plastic SSOP

TEMPERATURE RANGE

LTC2605CGN#TRPBF

LTC2605CGN-1#TRPBF

LTC2605IGN#TRPBF

LTC2605IGN-1#TRPBF

LTC2615CGN#TRPBF

LTC2615CGN-1#TRPBF

LTC2615IGN#TRPBF

LTC2615IGN-1#TRPBF

LTC2625CGN#TRPBF

LTC2625CGN-1#TRPBF

LTC2625IGN#TRPBF

LTC2625IGN-1#TRPBF

0°C to 70°C

26051

2605I

0°C to 70°C

–40°C to 85°C

0°C to 70°C

2605I1

2615

26151

2615I

0°C to 70°C

–40°C to 85°C

0°C to 70°C

2615I1

2625

26251

2625I

0°C to 70°C

–40°C to 85°C

2625I1

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

2605fa

2

LTC2605/LTC2615/LTC2625

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), V_OUTunloaded,

unless otherwise noted.

LTC2625/LTC2625-1 LTC2615/LTC2615-1 LTC2605/LTC2605-1

SYMBOL

DC Performance

Resolution

Monotonicity

PARAMETER

CONDITIONS

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNITS

l

12

14

16

Bits

LSB

(Note 2)

DNL

INL

Differential Nonlinearity (Note 2)

0.5

4

1

Integral Nonlinearity

Load Regulation

(Note 2)

1

4

16

18

64

V

= V = 5V, Mid-Scale

CC

OUT

REF

I

l

= 0mA to 15mA Sourcing

= 0mA to 15mA Sinking

0.02 0.125

0.03 0.125

0.07 0.5

0.10 0.5

0.3

0.4

2

LSB/mA

V

= V = 2.7V, Mid-Scale

OUT

REF

I

CC

l

= 0mA to 7.5mA Sourcing

= 0mA to 7.5mA Sinking

0.04 0.25

0.07 0.25

0.15

0.20

1

0.6

0.8

4

LSB/mA

l

ZSE

Zero-Scale Error

Offset Error

Code = 0

(Note 4)

1.7

1

9

1.7

1

9

1.7

1

9

mV

V

OS

9

V

Temperature

5

μV/°C

OS

Coefﬁcient

l

GE

Gain Error

0.1

8

0.7

0.1

8

0.7

0.1

8

0.7

%FSR

Gain Temperature

Coefﬁcient

ppm/°C

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_A= 25°C.

REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), V_OUTunloaded, unless otherwise noted. (Note 9)

SYMBOL PARAMETER

PSR Power Supply Rejection

CONDITIONS

MIN

TYP

MAX

UNITS

V

10%

–80

dB

CC

l

R

DC Output Impedance

V

REF

V

REF

= V = 5V, Mid-Scale; –15mA ≤ I ≤ 15mA

OUT

0.02

0.03

0.15

Ω

OUT

CC

= V = 2.7V, Mid-Scale; –7.5mA ≤ I

≤ 7.5mA

CC

OUT

DC Crosstalk (Note 10)

Due to Full-Scale Output Change (Note 11)

Due to Load Current Change

Due to Powering Down (per Channel)

10

3.5

7

μV

μV/mA

μV

I

SC

Short-Circuit Output Current

V

= 5.5V, V = 5.5V

CC REF

l

Code: Zero-Scale; Forcing Output to V

15

34

60

mA

CC

Code: Full-Scale; Forcing Output to GND

V

= 2.7V, V = 2.7V

CC

REF

l

Code: Zero-Scale; Forcing Output to V

7.5

20

27

50

mA

CC

Code: Full-Scale; Forcing Output to GND

Reference Input

Input Voltage Range

l

0

V

kΩ

pF

CC

Resistance

Normal Mode

11

16

90

20

Capacitance

l

I

Reference Current, Power-Down Mode DAC Powered Down

0.001

1

μA

REF

Power Supply

l

V

Positive Supply Voltage

Supply Current

For Speciﬁed Performance

2.7

5.5

V

CC

l

I

V

= 5V (Note 3)

= 3V (Note 3)

2.50

2.00

0.38

0.16

4.0

3.2

1.0

mA

μA

CC

DAC Powered Down (Note 3), V = 5V

CC

DAC Powered Down (Note 3), V = 3V

μA

2605fa

3

LTC2605/LTC2615/LTC2625

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), V_OUTunloaded,

unless otherwise noted. (Note 9)

SYMBOL PARAMETER

Digital I/O (Note 9)

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Low Level Input Voltage (SDA and SCL)

High Level Input Voltage (SDA and SCL)

Low Level Input Voltage (CA0 to CA2)

High Level Input Voltage (CA0 to CA2)

0.3V

V

IL

CC

0.7V

IH

CC

See Test Circuit 1

See Test Circuit 2

0.15V

V

IL(CA)

IH(CA)

CC

0.85V

V

CC

R

Resistance from CAn (n = 0,1,2) to V

10

kΩ

INH

INL

INF

OL

CC

to Set CAn = V

CC

l

Resistance from CAn (n = 0,1,2) to GND See Test Circuit 2

to Set CAn = GND

kΩ

Resistance from CAn (n = 0,1,2) to V

or GND to Set CAn = FLOAT

See Test Circuit 2

2

0

MΩ

CC

l

V

Low Level Output Voltage

Output Fall Time

Sink Current = 3mA

0.4

V

t

I

V = V

to V = V

, C = 10pF to 400pF

20 + 0.1CB

250

ns

OF

O

IH(MIN)

O

IL(MAX)

B

(Note 7)

l

Pulse Width of Spikes Surpassed by

Input Filter

0

50

ns

SP

IN

l

Input Leakage

0.1V ≤ V ≤ 0.9V

1

μA

pF

CC

IN

CC

C

I/O Pin Capacitance

(Note 12)

10

IN

Capacitance Load for Each Bus Line

400

10

B

External Capacitive Load on Address

Pins CA0, CA1 and CA2

CAn

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at T_A= 25°C.

REF = 4.096V (V_CC= 5V), REF = 2.048V (V_CC= 2.7V), V_OUTunloaded, unless otherwise noted.

LTC2625/LTC2625-1 LTC2615/LTC2615-1 LTC2605/LTC2605-1

MIN TYP MAX MIN TYP MAX MIN TYP MAX

SYMBOL PARAMETER

AC Performance

CONDITIONS

UNITS

t

S

Settling Time (Note 5)

0.024% ( 1LSB at 12 Bits)

0.006% ( 1LSB at 14 Bits)

0.0015% ( 1LSB at 16 Bits)

7

9

7

9

10

μs

Settling Time for 1LSB Step

(Note 6)

0.024% ( 1LSB at 12 Bits)

0.006% ( 1LSB at 14 Bits)

0.0015% ( 1LSB at 16 Bits)

2.7

4.8

2.7

4.8

5.2

μs

Voltage Output Slew Rate

Capacitive Load Driving

Glitch Inpulse

0.80

1000

12

0.80

1000

12

0.80

1000

12

V/μs

pF

At Mid-Scale Transition

nV•s

kHz

Multiplying Bandwidth

180

e

Output Voltage Noise Density At f = 1kHz

At f = 10kHz

120

100

120

100

120

100

nV/√Hz

n

Output Voltage Noise

0.1Hz to 10Hz

15

μV

P-P

2605fa

4

LTC2605/LTC2615/LTC2625

TIMING CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. See Figure 1. (Notes 8, 9)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

CC

= 2.7V to 5.5V

l

f

t

SCL Clock Frequency

0

400

kHz

μs

ns

μs

SCL

Hold Time (Repeated) Start Condition

Low Period of the SCL Clock Pin

High Period of the SCL Clock Pin

Set-Up Time for a Repeated Start Program

Data Hold Time

0.6

HD(STA)

LOW

1.3

0.6

HIGH

SU(STA)

HD(DAT)

SU(DAT)

r

0.6

0

0.9

Data Set-Up Time

100

Rise Time of Both SDA and SCL Signals

Fall Time of Both SDA and SCL Signals

Set-Up Time for Stop Condition

Bus Free Time Between a Stop and Start Condition

(Note 7)

20 + 0.1CB

0.6

300

f

SU(STO)

BUF

1.3

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: V = 5V, V = 4.096V. DAC is stepped 1/4-scale to 3/4-scale and

CC REF

3/4-scale to 1/4-scale. Load is 2kΩ in parallel with 200pF to GND.

Note 6: V = 5V, V = 4.096V. DAC is stepped 1LSB between half-scale

CC

REF

and half-scale – 1. Load is 2kΩ in parallel with 200pF to GND.

Note 2: Linearity and monotonicity are deﬁned from code k to code

L

Note 7: C = capacitance of one bus line in pF.

B

N

2 – 1, where N is the resolution and k is given by k = 0.016(2 /V ),

L

REF

Note 8: All values refer to V

and V

levels.

IL(MAX)

IH(MIN)

rounded to the nearest whole code. For V = 4.096V and N = 16,

REF

Note 9: These speciﬁcations apply to LTC2605/LTC2605-1,

LTC2615/LTC2615-1 and LTC2625/LTC2625-1.

k = 256 and linearity is deﬁned from code 256 to code 65,535.

L

Note 3: SDA, SCL at 0V or V , CA0, CA1 and CA2 ﬂoating.

CC

Note 10: DC Crosstalk is measured with V = 5V and V = 4096V, with

CC

REF

Note 4: Inferred from measurement at code 256 (LTC2605/LTC2605-1),

code 64 (LTC2615/LTC2615-1) or code 16 (LTC2625/LTC2625-1) and at

full-scale.

the measured DAC at mid-scale, unless otherwise noted.

Note 11: R = 2kΩ to GND or V

.

CC

L

Note 12: Guaranteed by design and not production tested.

ELECTRICAL CHARACTERISTICS

Test Circuit 1

Test Circuit 2

V

DD

100Ω

CAn

V

/V

IH(CA ) IL(CA )

n

R

/R /R

INH INL INF

2605 TC01

2605 TC02

GND

2605fa

5

LTC2605/LTC2615/LTC2625

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2605

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

INL vs Temperature

1.0

0.8

32

24

32

24

V

= 5V

REF

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

16

0.4

INL (POS)

INL (NEG)

8

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–16

–24

–32

–16

–24

–32

0

16384

32768

CODE

49152

65535

0

16384

32768

CODE

49152

65535

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

2605 G02

2605 G01

2605 G03

DNL vs Temperature

INL vs V_REF

DNL vs V_REF

1.0

0.8

32

24

1.5

1.0

V

= 5V

REF

V

= 5.5V

V

CC

= 5.5V

CC

= 4.096V

0.6

16

0.4

0.5

INL (POS)

INL (NEG)

DNL (POS)

DNL (NEG)

8

DNL (POS)

DNL (NEG)

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–8

–0.5

–1.0

–1.5

–16

–24

–32

–50 –30 –10 10

30

50

70

90

0

1

2

3

4

5

0

1

2

3

4

5

TEMPERATURE (°C)

V

REF

(V)

V

REF

(V)

2605 G04

2605 G05

2605 G06

Settling to 1LSB

Settling of Full-Scale Step

V

OUT

V

OUT

100μV/DIV

12.3μs

9.7μs

9TH CLOCK

OF 3RD DATA

BYTE

9TH CLOCK OF

3RD DATA BYTE

SCL

2V/DIV

SCR

2V/DIV

2605 G08

2605 G07

5μs/DIV

2μs/DIV

= 4.096V

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

AVERAGE OF 2048 EVENTS

SETTLING TO 1LSB

V

= 5V, V

REF

CC

V

CC

= 5V, V

= 4.096V

REF

CODE 512 TO 65535 STEP

AVERAGE OF 2048 EVENTS

R

L

2605fa

6

LTC2605/LTC2615/LTC2625

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2615

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to 1LSB

8

6

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

4

0.4

V

OUT

2

0.2

100μV/DIV

0

9TH CLOCK

OF 3RD DATA

BYTE

–0.2

–0.4

–0.6

–0.8

–1.0

SCL

2V/DIV

–2

–4

–6

–8

8.9μs

2605 G11

2μs/DIV

= 4.096V

V

= 5V, V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

R

= 2k, C = 200pF

L

0

4096

8192

CODE

12288

16383

0

4096

8192

CODE

12288

16383

AVERAGE OF 2048 EVENTS

2605 G09

2605 G10

LTC2625

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Settling to 1LSB

2.0

1.5

1.0

0.8

V

= 5V

REF

V

= 5V

REF

CC

= 4.096V

0.6

1.0

6.8μs

0.4

V

OUT

0.5

0.2

1mV/DIV

0

9TH CLOCK

OF 3RD DATA

BYTE

–0.2

–0.4

–0.6

–0.8

–1.0

SCL

2V/DIV

–0.5

–1.0

–1.5

–2.0

2605 G14

2μs/DIV

= 4.096V

V

= 5V, V

REF

CC

1/4-SCALE TO 3/4-SCALE STEP

= 2k, C = 200pF

R

0

1024

2048

CODE

3072

4095

0

1024

2048

CODE

3072

4095

L

AVERAGE OF 2048 EVENTS

2605 G12

2605 G13

LTC2605/LTC2615/LTC2625

Current Limiting

Load Regulation

Offset Error vs Temperature

1.0

0.8

0.10

3

2

CODE = MID-SCALE

0.08

V

= V = 5V

CC

REF

0.6

0.06

0.04

= V = 3V

CC

0.4

1

0.2

0.02

0

V

REF

= V = 5V

CC

–0.2

–0.4

–0.6

–0.8

–1.0

–0.02

–0.04

–0.06

–0.08

–0.10

V

= V = 3V

CC

REF

–1

–2

–3

V

REF

= V = 3V

V

REF

= V = 5V

CC

–35 –25 –15 –5

I

5

15

25

35

–40 –30 –20 –10

I

0

10 20 30 40

–50 –30 –10 10

30

50

70

90

(mA)

TEMPERATURE (°C)

OUT

2606 G16

2605 G15

2605 G17

2605fa

7

LTC2605/LTC2615/LTC2625

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2605/LTC2615/LTC2625

Zero-Scale Error vs Temperature

Gain Error vs Temperature

Offset Error vs V_CC

3

2.5

2.0

1.5

1.0

0.5

0

0.4

0.3

3

2

0.2

1

0.1

0

–0.1

–0.2

–0.3

–0.4

–1

–2

–3

–50 –30 –10 10

30

50

70

90

–50 –30 –10 10

30

50

70

90

2.5

3

3.5

4

4.5

5

5.5

TEMPERATURE (°C)

V

CC

(V)

2605 G18

2605 G19

2605 G20

Gain Error vs V_CC

I_CCShutdown vs V_CC

Large-Signal Response

0.4

0.3

450

400

350

300

250

200

150

100

50

0.2

0.1

V

OUT

0.5V/DIV

0

–0.1

–0.2

–0.3

–0.4

V

= V = 5V

CC

REF

1/4-SCALE TO 3/4-SCALE

2.5μs/DIV

2605 G23

0

2.5

3

3.5

4

4.5

5

5.5

2.5

3

3.5

4

4.5

5

5.5

V

CC

(V)

V

CC

(V)

2605 G22

2605 G21

Headroom at Rails

vs Output Current

Mid-Scale Glitch Impulse

Power-On Reset Glitch

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

5V SOURCING

TRANSITION FROM

MS-1 TO MS

V

OUT

V

CC

10mV/DIV

3V SOURCING

1V/DIV

TRANSITION FROM

MS TO MS-1

9TH CLOCK

OF 3RD DATA

BYTE

4mV PEAK

SCL

2V/DIV

V

OUT

10mV/DIV

5V SINKING

2605 G24

2605 G25

3V SINKING

2.5μs/DIV

250μs/DIV

0

1

2

3

4

5

6

7

8

9

10

I

(mA)

OUT

2605 G26

2605fa

8

LTC2605/LTC2615/LTC2625

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2605/LTC2615/LTC2625

Power-On Reset to Mid-Scale

Supply Current vs Logic Voltage

Multiplying Bandwidth

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

2.0

0

–3

V = 5V

CC

SWEEP SCL

AND SDA 0V

TO V AND

CC

V

REF

= V

CC

–6

–9

V

CC

TO 0V

–12

–15

–18

–21

–24

–27

–30

–33

–36

1V/DIV

V

CC

V

= 5V

CC

(DC) = 2V

REF

V

OUT

(AC) = 0.2V

P-P

CODE = FULL-SCALE

2605 G27

0

1

2

3

4

5

1k

10k

100k

1M

500μs/DIV

2605 G28

FREQUENCY (Hz)

LOGIC VOLTAGE (V)

2605 G29

Output Voltage Noise,

0.1Hz to 10Hz

Short-Circuit Output Current

vs V_OUT(Sinking)

Short-Circuit Output Current

vs V_OUT(Sourcing)

0mA

–10mA

–20mA

–30mA

–40mA

–50mA

40mA

30mA

20mA

10mA

0mA

V

OUT

10μV/DIV

0

1

2

3

4

5

6

7

8

9

10

SECONDS

2605 G30

2605 G31

0

1

2

3

4

5

0

1

2

3

4

5

V

= 5.5V

= 5.6V

1V/DIV

2605 G32

V

= 5.5V

= 5.6V

1V/DIV

CC

REF

CC

REF

CODE = FULL-SCALE

SWEPT V TO 0V

CODE = 0

SWEPT 0V TO V

V

OUT

CC

OUT

CC

2605fa

9

LTC2605/LTC2615/LTC2625

PIN FUNCTIONS

GND (Pin 1): Analog Ground.

SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This

is a high impedance pin while data is shifted in. It is an

open-drainN-channeloutputduringacknowledgment.This

V

to V

(Pins 2-5 and 12-15): DAC Analog Volt-

OUT H

OUT A

age Output. The output range is 0V to V

.

REF

REF (Pin 6): Reference Voltage Input. 0V ≤ V ≤ V .

pin requires a pull-up resistor or current source to V .

REF

CC

CA2 (Pin 7): Chip Address Bit 2. Tie this pin to V , GND

CA1 (Pin 10): Chip Address Bit 1. Tie this pin to V , GND

CC

2

or leave it ﬂoating to select an I C slave address for the

part (Table 2).

SCL (Pin 8): Serial Clock Input Pin. Data is shifted into

the SDA pin at the rising edges of the clock. This high

impedance pin requires a pull-up resistor or current

CA0 (Pin 11): Chip Address Bit 0. Tie this pin to V , GND

CC

2

or leave it ﬂoating to select an I C slave address for the

part (Table 2).

source to V .

CC

V

CC

(Pin 16): Supply Voltage Input. 2.7V ≤ V ≤ 5.5V.

CC

BLOCK DIAGRAM

GND

1

16

15

V

CC

DAC A

DAC H

V

2

OUT A

OUT H

DAC B

DAC C

DAC G

DAC F

V

OUT G

V

OUT F

3

4

14

13

OUT B

OUT C

DAC D

DAC E

V

5

12

OUT D

REF

OUT E

CA0

CA1

6

7

11

10

32-BIT SHIFT REGISTER

2-WIRE INTERFACE

CA2

9

SDA

SCL

8

2605 BD01

TIMING DIAGRAM

SDA

t

f

SU(DAT)

t

f

t

r

t

r

t

BUF

LOW

HD(STA)

SP

SCL

t

SU(STO)

HD(STA)

SU(STA)

t

S

P

S

HD(DAT)

HIGH

2605 F01

ALL VOLTAGE LEVELS REFER TO V

AND V LEVELS

IL(MAX)

IH(MIN)

Figure 1

2605fa

10

LTC2605/LTC2615/LTC2625

OPERATION

Power-On Reset

where k is the decimal equivalent of the binary DAC input

code, N is the resolution and V

(Pin 6).

is the voltage at REF

REF

The LTC2605/LTC2615/LTC2625 clear the outputs to

zero-scale when power is ﬁrst applied, making system

initialization consistent and repeatable. The LTC2605-1/

LTC2615-1/LTC2625-1setthevoltageoutputstomid-scale

when power is ﬁrst applied.

Serial Digital Interface

The LTC2605/LTC2615/LTC2625 communicate with a

host using the standard 2-wire digital interface. The Tim-

ing Diagram (Figure 1) shows the timing relationship of

the signals on the bus. The two bus lines, SDA and SCL,

must be high when the bus is not in use. External pull-up

resistors or current sources are required on these lines.

The value of these pull-up resistors is dependent on the

Forsomeapplications,downstreamcircuitsareactivedur-

ingDACpower-up,andmaybesensitivetononzerooutputs

from the DAC during this time. The LTC2605/LTC2615/

LTC2625 contain circuitry to reduce the power-on glitch:

the analog outputs typically rise less than 10mV above

zero-scale during power on if the power supply is ramped

to 5V in 1ms or more. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See Power-On Reset Glitch in the Typical Performance

Characteristics section.

2

power supply and can be obtained from the I C speciﬁca-

2

tions. For an I C bus operating in the fast mode, an active

pull-up will be necessary if the bus capacitance is greater

than 200pF. The V power should not be removed from

CC

2

the LTC2605/LTC2615/LTC2625 when the I C bus is active

2

to avoid loading the I C bus lines through the internal ESD

Power Supply Sequencing

protection diodes.

The voltage at REF (Pin 6) should be kept within the range

The LTC2605/LTC2615/LTC2625 are receive-only (slave)

devices. The master can write to the LTC2605/LTC2615/

LTC2625.TheLTC2605/LTC2615/LTC2625donotrespond

to a read from the master.

–0.3V ≤ V ≤ V + 0.3V (see Absolute Maximum Rat-

REF

CC

ings). Particular care should be taken to observe these

limitsduringpowersupplyturn-onandturn-offsequences,

when the voltage at V (Pin 16) is in transition.

CC

The START (S) and STOP (P) Conditions

Transfer Function

When the bus is not in use, both SCL and SDA must be

high. A bus master signals the beginning of a communica-

tion to a slave device by transmitting a START condition. A

START condition is generated by transitioning SDA from

high to low while SCL is high.

The digital-to-analog transfer function is:

k

⎛

⎞

V_{OUT(IDEAL) ⎜}

=

V

_N⎟ REF

⎝

⎠

2

Table 1

COMMAND*

ADDRESS (n)*

C3 C2 C1 C0

A3 A2 A1 A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Write to Input Register n

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

All DACs

Update (Power Up) DAC Register n

Write to Input Register n, Update (Power Up) All n

Write to and Update (Power Up) n

Power Down n

No Operation

*Address and command codes not shown are reserved and should not

be used.

2605fa

11

LTC2605/LTC2615/LTC2625

Table 2. Slave Address Map

OPERATION

CA2

GND

CA1

CA0 SA6 SA5 SA4 SA3 SA2 SA1 SA0

GND

When the master has ﬁnished communicating with the

slave, it issues a STOP condition. A STOP condition is

generated by transitioning SDA from low to high while

SCL is high. The bus is then free for communication with

GND

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GND FLOAT

GND

V

CC

GND FLOAT GND

GND FLOAT FLOAT

GND FLOAT VCC

2

another I C device.

Acknowledge

GND

V

GND

CC

The Acknowledge signal is used for handshaking between

the master and the slave. An Acknowledge (active LOW)

generated by the slave lets the master know that the lat-

est byte of information was received. The Acknowledge

related clock pulse is generated by the master. The master

releases the SDA line (HIGH) during the Acknowledge

clock pulse. The slave-receiver must pull down the SDA

during the Acknowledge clock pulse so that it remains a

stable LOW during the HIGH period of this clock pulse.

The LTC2605/LTC2615/LTC2625 respond to a write by a

masterinthismanner. TheLTC2605/LTC2615/LTC2625do

not acknowledge a read (it retains SDA HIGH during the

period of the Acknowledge clock pulse).

FLOAT

V

CC

FLOAT GND

FLOAT GND FLOAT

FLOAT GND

GND

V

CC

FLOAT FLOAT GND

FLOAT FLOAT FLOAT

FLOAT FLOAT

V

CC

FLOAT

V

GND

CC

FLOAT

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

GND

GND FLOAT

GND

V

CC

Chip Address

FLOAT GND

FLOAT FLOAT

The state of CA0, CA1 and CA2 decides the slave address

of the part. The pins CA0, CA1 and CA2 can be each set to

any one of three states: V , GND or FLOAT. This results

in 27 selectable addresses for the part. The addresses

corresponding to the states of CA0, CA1 and CA2 and the

global address are shown in Table 2.

FLOAT

V

CC

V

GND

CC

FLOAT

V

CC

GLOBAL ADDRESS

In addition to the address selected by the address pins,

the parts also respond to a global address. This address

allows a common write to all LTC2605, LTC2615 and

LTC2625 parts to be accomplished with one 3-byte write

low at the 9th clock if the 7-bit slave address matches the

address of the parts (set by CA0, CA1 and CA2) or the

global address. The master then transmits three bytes of

data.TheLTC2605/LTC2615/LTC2625acknowledgeseach

byte of data by pulling the SDA line low at the 9th clock of

eachdatabytetransmission.Afterreceivingthreecomplete

bytesofdata,theLTC2605/LTC2615/LTC2625executesthe

command speciﬁed in the 24-bit input word.

2

transaction on the I C bus. The global address is a 7-bit

hard-wired address and is not selectable by CA0, CA1 and

CA2.Themaximumcapacitiveloadallowedontheaddress

pins (CA0, CA1 and CA2) is 10pF.

Write Word Protocol

If more than three data bytes are transmitted after a valid

7-bitslaveaddress,theLTC2605/LTC2615/LTC2625donot

acknowledge the extra bytes of data (SDA is high during

the 9th clock).

The master initiates communication with the LTC2605/

LTC2615/LTC2625withaSTARTconditionanda7-bitslave

address followed by the Write bit (W) = 0. The LTC2605/

LTC2615/LTC2625 acknowledges by pulling the SDA pin

2605fa

12

LTC2605/LTC2615/LTC2625

OPERATION

WRITE WORD PROTOCOL FOR LTC2605/LTC2615/LTC2625

S

W

A

1ST DATA BYTE

A

2ND DATA BYTE

INPUT WORD

A

P

SLAVE ADDRESS

3RD DATA BYTE

INPUT WORD (LTC2605)

A3 A2

1ST DATA BYTE

INPUT WORD (LTC2615)

A3 A2

1ST DATA BYTE

INPUT WORD (LTC2625)

A3 A2

1ST DATA BYTE

A0

D12

D6

D4

D2

D0

X

C3

C1

A1

D15 D14 D13

D11 D10 D9 D8

D5 D4 D3 D2 D1

3RD DATA BYTE

D7

D5

D3

C2

C0

2ND DATA BYTE

D10

C3

C1

D13 D12 D11

D9 D8 D7 D6

D3 D2 D1 D0

3RD DATA BYTE

X

C2

C0

2ND DATA BYTE

D8

X

2605 F02

C3

C1

D11 D10 D9

D7 D6 D5 D4

D1 D0

X

C2

C0

2ND DATA BYTE

3RD DATA BYTE

Figure 2

The format of the three data bytes is shown in Figure 2.

The ﬁrst byte of the input word consists of the 4-bit com-

mand and 4-bit DAC address. The next two bytes consist

of the 16-bit data word. The 16-bit data word consists of

the 16-, 14- or 12-bit input code, MSB to LSB, followed by

0, 2 or 4 don’t care bits (LTC2605, LTC2615 and LTC2625

a high impedance state, and the output pins are passively

pulled to ground through individual 90k resistors. When

all eight DACs are powered down, the bias generation

circuit is also disabled. Input and DAC registers are not

disturbed during power down.

Any channel or combination of channels can be put into

2

respectively). A typical I C write transaction is shown in

power-down mode by using command 0100 in combi-

b

Figure 3.

nation with the appropriate DAC address, (n). The 16-bit

data word is ignored. The supply and reference currents

are reduced by approximately 1/8 for each DAC powered

down; the effective resistance at REF (Pin 6) rises accord-

ingly, becoming a high impedance input (typically >1GΩ)

when all eight DACs are powered down.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The ﬁrst four commands in the table

consist of write and update operations. A write operation

loads the 16-bit data word from the 32-bit shift register

into the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

Normal operation can be resumed by executing any com-

mand which includes a DAC update, as shown in Table 1.

The selected DAC is powered up as its voltage output is

updated.

There is an initial delay as the DAC powers up before it

begins its usual settling behavior. If less than eight DACs

are in a powered-down state prior to the updated com-

mand, the power-up delay is 5μs. If, on the other hand,

all eight DACs are powered down, then the bias genera-

tion circuit is also disabled and must be restarted. In this

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than eight outputs are needed. When in power down, the

buffer ampliﬁers and reference inputs are disabled and

drawessentiallyzerocurrent.TheDACoutputsareputinto

case, the power-up delay is greater: 12μs for V = 5V,

CC

30μs for V = 3V.

CC

2605fa

13

LTC2605/LTC2615/LTC2625

OPERATION

2605fa

14

LTC2605/LTC2615/LTC2625

OPERATION

Voltage Outputs

Digital and analog ground planes should be joined at only

one point, establishing a system star ground as close to

the device’s ground pin as possible. Ideally, the analog

ground plane should be located on the component side of

the board, and should be allowed to run under the part to

shielditfromnoise.Analoggroundshouldbeacontinuous

and uninterrupted plane, except for necessary lead pads

and vias, with signal traces on another layer.

Each of the eight rail-to-rail ampliﬁers contained in these

parts has guaranteed load regulation when sourcing or

sinking up to 15mA at 5V (7.5mA at 3V).

Load regulation is a measure of the ampliﬁer’s ability to

maintain the rated voltage accuracy over a wide range of

load conditions. The measured change in output voltage

permilliampereofforcedloadcurrentchangeisexpressed

in LSB/mA.

The GND pin of the part should be connected to analog

ground. Resistance from the GND pin to system star

ground should be as low as possible. Resistance here will

add directly to the effective DC output impedance of the

device (typically 0.020Ω), and will degrade DC crosstalk.

Note that the LTC2605/LTC2615/LTC2625 are no more

susceptible to these effects than other parts of their type;

on the contrary, they allow layout-based performance

improvements to shine rather than limiting attainable

performance with excessive internal resistance.

DC output impedance is equivalent to load regulation and

may be derived from it by simply calculating a change in

units from LSB/mA to Ohms. The ampliﬁer’s DC output

impedance is 0.020Ω when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 30Ω typical channel resistance of the output devices;

e.g., when sinking 1mA, the minimum output voltage =

30Ω • 1mA = 30mV. See the graph Headroom at Rails vs

Output Current in the Typical Performance Characteristics

section.

Rail-to-Rail Output Considerations

Inanyrail-to-railvoltageoutputdevice,theoutputislimited

to voltages within the supply range.

The ampliﬁers are stable driving capacitive loads of up

to 1000pF.

Since the analog outputs of the device cannot go below

ground, they may limit for the lowest codes as shown

in Figure 4b. Similarly, limiting can occur near full-scale

Board Layout

when the REF pin is tied to V . If V = V and the DAC

CC

REF

CC

full-scale error (FSE) is positive, the output for the highest

TheexcellentloadregulationandDC-crosstalkperformance

of these devices is achieved in part by keeping “signal”

and“power”groundsseparatedinternallyandbyreducing

shared internal resistance to just 0.005Ω.

codes limits at V as shown in Figure 4c. No full-scale

CC

limiting can occur if V is less than V – FSE.

REF

CC

Offset and linearity are deﬁned and tested over the region

of the DAC transfer function where no output limiting

can occur.

The GND pin functions both as the node to which the refer-

ence and output voltages are referred and as a return path

for power currents in the device. Because of this, careful

thought should be given to the grounding scheme and

board layout in order to ensure rated performance.

The PC board should have separate areas for the analog

anddigitalsectionsofthecircuit.Thiskeepsdigitalsignals

away from sensitive analog signals and facilitates the

use of separate digital and analog ground planes which

have minimal capacitive and resistive interaction with

each other.

2605fa

15

LTC2605/LTC2615/LTC2625

OPERATION

POSITIVE

FSE

V

= V

CC

REF

V

= V

CC

REF

OUTPUT

VOLTAGE

OUTPUT

VOLTAGE

INPUT CODE

2605 F04

(4c)

OUTPUT

VOLTAGE

0

32, 768

65, 535

INPUT CODE

(4a)

0V

NEGATIVE

OFFSET

INPUT CODE

(4b)

Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve. (4a) Overall Transfer Function, (4b) Effect

of Negative Offset for Codes Near Zero-Scale, (4c) Effect of Positive Full-Scale Error for Codes Near Full-Scale

PACKAGE DESCRIPTION

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 p.005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 p.0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 p .004

(0.38 p 0.10)

s 45o

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0o – 8o TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

2605fa

16

LTC2605/LTC2615/LTC2625

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

11/09 Added Text to Serial Digital Interface Section

11

2605fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

17

LTC2605/LTC2615/LTC2625

TYPICAL APPLICATION

Demonstration Circuit—LTC2428 20-Bit ADC Measures Key Performance Parameters

ADDRESS SELECTION

V

CC

V

CC

V

REF

V

CC

C1

0.1μF

C2

0.1μF

6

16

REF

V

CC

11

10

7

2

TP3

CA0

CA1

CA2

V

A

B

C

D

E

OUT

DAC A

3

4

TP4

DAC B

5

V

CC

12

13

14

15

TP5

DAC C

V

OUT

10k

V

F

OUT

9

8

TP6

DAC D

SDA

SCL

V

G

H

2

OUT

I C

BUS

V

DAC OUTPUTS

TP7

DAC E

V

REF

V

CC

V

CC

GND

1

U2

LTC2605CGN

TP8

DAC F

C4

0.1μF

C5

0.1μF

TP9

DAC G

R5

7.5k

JP1

R8

22

ON/OFF

3

TP10

DAC H

C10

100pF

2

DISABLE

ADC

V

IN

7

4

3

2

8

U4

1

LT1236ACS8-5

V

MUXOUT ADCIN FS

CC CC

SET

2

6

V

REF

V

OUT

IN

1

9

CH0

5V

TP11

REF

23

R6

7.5k

10 CH1

11 CH2

12 CH3

13 CH4

14 CH5

15 CH6

17 CH7

GND

4

CSADC

V

2

3

4.096V

20

25

19

21

24

CS

C7

4.7μF

6.3V

C6

0.1μF

CSMUX

SCK

JP2

REF

V

4-/8-CHANNEL

MUX

20-BIT

+

SCK

SPI

BUS

ADC

CLK

U5

D

IN

LT1461ACS8-4

–

2

3

6

SD0

V

CC

V

OUT

IN

1

26

SHDN

GND

5V

TP12

FO

REF

5

ZS

SET

V

CC

2

3

GND GND GND GND GND GND GND

16 18 22 27 28

R7

7.5k

C9

0.1μF

C8 REGULATOR

4

1μF

16V

JP3

1

6

U3

LTC2428CG

TP13

GND

V

CC

2605 TA01

5V

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1458: V = 4.5V to 5.5V, V

LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

= 0V to 4.096V

OUT

CC

LTC1458L: V = 2.7V to 5.5V, V

= 0V to 2.5V

CC

LTC1654

Dual 14-Bit Rail-to-Rail V

DAC

Programmable Speed/Power, 3.5μs/750μA, 8μs/450μA

= 5V(3V), Low Power, Deglitched

OUT

LTC1655/LTC1655L Single 16-Bit V

DAC with Serial Interface in SO-8

V

CC

OUT

LTC1657/LTC1657L Parrallel 5V/3V 16-Bit V

DAC

Low Power, Deglitched, Rail-to-Rail V

OUT

LTC1660/LTC1665 Octal 10-/8-Bit V

DAC in 16-Pin Narrow SSOP

V

CC

= 2.7V to 5.5V, Micropower, Rail-to-Rail Output

OUT

LTC1821

Parallel 16-Bit Voltage Output DAC

Precision 16-Bit Settling in 2μs for 10V Step

LTC2600/LTC2610/ Octal 16-/14-/12-Bit V

LTC2620

DACs in 16-Lead SSOP

250μA per DAC, 2.5V to 5.5V Supply Range,

Rail-to-Rail Output, SPI Interface

OUT

LTC2601/LTC2611/ Single 16-/14-/12-Bit V

LTC2621

DACs in 10-Lead DFN

300μA per DAC, 2.5V to 5.5V Supply Range,

Rail-to-Rail Output, SPI Interface

OUT

LTC2602/LTC2612/ Dual 16-/14-/12-Bit V

LTC2622

DACs in 8-Lead MSOP

300μA per DAC, 2.5V to 5.5V Supply Range,

Rail-to-Rail Output, SPI Interface

OUT

LTC2604/LTC2614/ Quad 16-/14-/12-Bit V

LTC2624

LTC2606/LTC2616/ Single 16-/14-/12-Bit V

LTC2626

DACs in 16-Lead SSOP

250μA per DAC, 2.5V to 5.5V Supply Range,

Rail-to-Rail Output, SPI Interface

OUT

2

DACs with I C Interface in 10-Lead DFN 270μA per DAC, 2.7V to 5.5V Supply Range,

OUT

2

Rail-to-Rail Output, I C Interface

2605fa

LT 1109 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

18

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2615IGNTRPBF
厂家：	Linear
描述：	Octal 16-/14-/12-Bit Rail-to Rail DACs in 16-Lead SSOP 八通道16位/ 14位/ 12位轨至轨数模转换器采用16引脚SSOP 转换器数模转换器
文件：	总18页 (文件大小：270K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2615IGNTRPBF [Linear]

相关型号：

LTC2615_15

LTC2616

LTC2616CDD

LTC2616CDD-1

LTC2616CDD-1#TRPBF

LTC2616IDD

LTC2616IDD#PBF

LTC2616IDD#TR

LTC2616IDD#TRPBF

LTC2616IDD-1

LTC2616IDD-1#TR

LTC2616IDD-1#TRPBF