LTC4300A-3IDD#PBF_技术文档

LTC4300A-3

Level-Shifting

Hot Swappable 2-Wire

Bus Buffer with Enable

FeaTures

DescripTion

The LTC^®4300A-3 hot swappable 2-wire bus buffer allows

I/O card insertion into a live backplane without corruption

ofthedataandclockbusses.Whentheconnectionismade,

the LTC4300A-3 provides bidirectional buffering, keeping

the backplane and card capacitances isolated. Rise time

accelerator circuitry allows the use of weaker DC pull-up

currentswhilestillmeetingrisetimerequirements.During

insertion, the SDA and SCL lines are precharged to 1V to

minimize bus disturbances.

n

Bidirectional Buffer* for SDA and SCL Lines

Increases Fanout

n

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal From Backplane

n

Logic Threshold ENABLE Input

n

Isolates Input SDA and SCL Lines From Output

2

n

Compatible with I C, I C Fast Mode and SMBus

Standards (Up to 400kHz Operation)

1V Precharge on all SDA and SCL Lines

Supports Clock Stretching, Arbitration and

Synchronization

n

The LTC4300A-3 provides level translation between

3.3V and 5V supplies. The backplane and card can both

be powered with supplies ranging from 2.7V to 5.5V.

The LTC4300A-3 also incorporates a CMOS threshold

ENABLE pin which forces the part into a low current mode

and isolates the card from the backplane. When driven to

■

5V to 3.3V Level Translation

High Impedance SDA, SCL Pins for V = 0V,

CC

V

CC2

= 0V

■

Small 8-Lead DFN and MSOP Packages

V , the ENABLE pin sets normal operation.

CC

applicaTions

TheLTC4300A-3isavailableintheMSOPand3mm×3mm

DFN packages.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

Hot Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners. *Patent pending.

n

Hot Board Insertion

n

Servers

n

Capacitance Buffer/Bus Extender

Desktop Computer

n

Typical applicaTion

V

3.3V

CC

Input–Output Connection

V

CC2

0.01µF

10k

3

10k

8

1

INPUT

OUTPUT

SIDE

2

7

SIDE

SCLIN

SDAIN

SCLOUT

150pF

50pF

0.5V/DIV

6

SDAOUT

4300a3 TA01b

200ns/DIV

LTC4300A-3

5

ENABLE

OFF ON

GND

4

4300a3 TA01

4300a3fa

1

LTC4300A-3

absoluTe MaxiMuM raTings ^{(Note 1)}

V

CC2

to GND ..................................................–0.3V to 7V

Storage Temperature Range

CC

V

to GND................................................. –0.3V to 7V

MSOP ................................................ –65°C to 150°C

DFN.................................................... –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

SDAIN, SCLIN, SDAOUT, SCLOUT................ –0.3V to 7V

ENABLE........................................................ –0.3V to 7V

Operating Temperature Range

MSOP Only .......................................................300°C

LTC4300A-3C ......................................... 0°C to 70°C

LTC4300A-3I........................................–40°C to 85°C

pin conFiguraTion

TOP VIEW

V

1

2

3

4

8

7

6

5

V

CC

CC2

V

1

8 V

CC

7 SDAOUT

6 SDAIN

CC2

SCLOUT

SCLIN

GND

SDAOUT

SDAIN

9

SCLOUT 2

SCLIN

GND

3

4

5 ENABLE

ENABLE

MS8 PACKAGE

8-LEAD PLASTIC MSOP

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

T

= 125°C, θ = 200°C/W

JMAX

JA

T

= 125°C, θ = 43°C/W

JA

JMAX

EXPOSED PAD (PIN 9), PCB CONNECTION IS OPTIONAL

orDer inForMaTion

LEAD FREE FINISH

TAPE AND REEL

PART MARKING*

LBHG

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC4300A-3CDD#PBF

LTC4300A-3IDD#PBF

LTC4300A-3CMS8#PBF

LTC4300A-3IMS8#PBF

LTC4300A-3CDD#TRPBF

LTC4300A-3IDD#TRPBF

LTC4300A-3CMS8#TRPBF

LLTC4300A-3IMS8#TRPBF

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

LBHG

–40°C to 85°C

0°C to 70°C

LTBHD

LTBHF

8-Lead Plastic MSOP

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

4300a3fa

2

LTC4300A-3

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 2.7V to 5.5V, V_CC2= 2.7V to 5.5V, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply

l

V

Positive Supply Voltage

2.7

5.5

V

CC

Card Side Supply Voltage

Supply Current in Shutdown Mode

CC2

I

V

= 0V

20

3

µA

mA

SD

ENABLE

V

Supply Current

= V

= 0V, V

= V

= 5.5V

4.1

2.9

VCC1

VCC2

CC

SDAIN

SCLIN

CC1

CC2

Supply Current

= V

= 0V, V

= V = 5.5V

CC2

2.1

CC2

SDAOUT

SCLOUT

CC1

Start-Up Circuitry

l

V

Precharge Voltage

SDA, SCL Floating

0.8

50

1.0

95

1.2

V

µs

V

PRE

t

Bus Idle Time

150

IDLE

V

ENABLE Threshold Voltage

Disable Threshold Voltage

ENABLE Input Current

ENABLE Delay, On-Off

ENABLE Delay, Off-On

0.5 • V

0.1

0.9 • V

CC

EN

CC

ENABLE Pin

0.1 • V

V

DIS

CC

I

t

ENABLE from 0V to V

1

µA

ns

µs

EN

CC

10

PHL

PLH

95

Rise Time Accelerators

Transient Boosted Pull-Up Current

I

Positive Transition on SDA, SCL, V = 2.7V,

CC2

1

2

mA

PULLUPAC

CC

V

= 2.7V, Slew Rate = 1.25V/µs (Note 2)

Input-Output Connection

l

V

Input-Output Offset Voltage

10k to V on SDA, SCL, V = 3.3V (Note 3),

CC2

0

100

175

mV

OS

CC

V

= 3.3V, V = 0.2V

IN

f

Operating Frequency

Guaranteed by Design, Not Subject to Test

400

10

kHz

pF

V

SCL, SDA

C

V

Digital Input Capacitance

Output Low Voltage, Input = 0V

IN

l

SDA, SCL Pins, I

CC2

= 3mA, V = 2.7V,

0

0.4

OL

SINK

CC

V

= 2.7V

I

Input Leakage Current

SDA, SCL Pins = V = 5.5V, V

= 5.5V

5

µA

LEAK

CC

CC2

Timing Characteristics

2

f

t

I C Operating Frequency

(Note 4)

0

400

kHz

µs

I2C

Bus Free Time Between Stop and

Start Condition

1.3

BUF

t

Hold Time After (Repeated) Start

Condition

(Note 4)

0.6

µs

hD,STA

t

Repeated Start Condition Setup Time (Note 4)

0.6

300

100

1.3

0.6

µs

ns

µs

ns

su,STA

su,STO

hD, DAT

su, DAT

LOW

Stop Condition Setup Time

Data Hold Time

(Note 4)

Data Setup Time

(Note 4)

Clock Low Period

(Note 4)

Clock High Period

Clock, Data Fall Time

Clock, Data Rise Time

(Note 4)

HIGH

(Notes 4, 5)

20 + 0.1 • C

300

75

f

B

r

l

High-to-Low Propagation Delay

Skew, SCL-SDA

V

CC

V

CC

= 2.7V, V

= 5.5V, V

= 5.5V;

= 2.7V (Note 6)

0

PHL,SKEW

CC2

4300a3fa

3

LTC4300A-3

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: Guaranteed by design, not subject to test.

Note 5: C = total capacitance of one bus line in pF.

B

Note 6: These tests measure the difference in high-to-low propagation

delay t

between the clock and data channels. The delay on each

PHL

Note 2: I

varies with temperature and V voltage, as shown in

PULLUPAC

CC

channel is measured from the 50% point of the falling driven input signal

to the 50% point of the output driven by the LTC4300A-3.The skew is

the Typical Performance Characteristics section.

defined as (t

-t

). Testing is performed in both directions—

Note 3: The connection circuitry always regulates its output to a higher

PHL(SCL) PHL(SDA)

from input bus to output bus and vice versa. Tests are performed with

approximately 500pF of distributed equivalent capacitance on each SDA

and SCL pin.

voltage than its input. The magnitude of this offset voltage as a function of

the pull-up resistor and V voltage is shown in the Typical Performance

CC

Characteristics section.

Typical perForMance characTerisTics

Input–Output High to Low

Propagation Delay vs Temperature

I_CCvs Temperature

I_PULLUPACvs Temperature

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

4.4

4.3

12

10

8

100

80

60

40

20

0

V

= 2.7V

= 3.3V

CC

V

= 5.5V

CC

V

= 5V

CC

6

V

= 3V

V

= 5.5V

V

= 2.7V

CC

4

2

C

= C

PULLUPIN

= 100pF

= 10k

PULLUPOUT

= 2.7V

25

IN

OUT

R

= R

0

–50

–25

0

50

75

100

–50

–25

0

25

50

75

100

–50

–25

0

25

50

75

100

TEMPERATURE (°C)

4300a3 G03

4300a3 G01

4300a3 G02

Connection Circuitry V_OUT– V_IN

I_SDvs Temperature

35

300

250

200

150

100

50

T

= 25°C

IN

A

V

= 0V

30

25

20

15

10

5

V

= 5.5V

CC

V

= 5V

CC

V

= 3.3V

CC

V

= 2.7V

25

CC

0

50

100

–50 –25

0

75

0

10,000

20,000

(Ω)

30,000

40,000

R

TEMPERATURE (°C)

PULLUP

4300a3 G05

4300a3 G04

4300a3fa

4

LTC4300A-3

pin FuncTions ^(DFN/MSOP)

V

(Pin 1): Card Supply Voltage. This is the supply

isolates SCLIN from SCLOUT. For active operation, drive

CC2

2

voltage for the devices on the card I C busses. Connect

pull-up resistors from SDAOUT and SCLOUT to this pin.

Place a bypass capacitor of at least 0.01µF close to this

pin for best results.

this pin to V . If this feature is unused, tie to V . Since

CC CC

ENABLE is V referenced, do not connect to V

or

CC

CC2

pull up to V

.

CC2

SDAIN (Pin 6): Serial Data Input. Connect this pin to the

SDA bus on the backplane.

SCLOUT (Pin 2): Serial Clock Output. Connect this pin to

the SCL bus on the card.

SDAOUT (Pin 7): Serial Data Output. Connect this pin to

the SDA bus on the card.

SCLIN (Pin 3): Serial Clock Input. Connect this pin to the

SCL bus on the backplane.

V

(Pin 8): Main Input Power Supply from Backplane.

CC

GND (Pin 4): Device Ground. Connect this pin to a ground

plane for best results.

This is the supply voltage for the devices on the backplane

2

I C busses. Connect pull-up resistors from SDAIN and

SCLIN to this pin. Place a bypass capacitor of at least

0.01µF close to this pin for best results.

ENABLE (Pin 5): Digital CMOS Threshold Input. Ground-

ing this pin puts the part in a low current mode. It also

disables the rise time accelerators, disables the bus

discharge circuitry, isolates SDAIN from SDOUT and

Exposed Pad (Pin 9, DFN Package Only): Exposed pad

may by be left open or connected to device ground.

4300a3fa

5

LTC4300A-3

block DiagraM

2-Wire Bus Buffer and Hot Swap™ Controller

V

CC

8

2mA

1

V

CC2

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

BACKPLANE-TO-CARD

SDAIN

6

47 SDAOUT

CONNECTION

CONNECT

100k

1V

PRECHARGE

2mA

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

BACKPLANE-TO-CARD

CONNECTION

SCLIN

3

2

SCLOUT

– 1V

CONNECT

+

–

V

CC2

+

–

+

–

STOP BIT AND BUS IDLE

0.5A

+

–

0.55V

/

CC

20pF

0.45V

95µs

CONNECT CONNECT

UVLO

DELAY,

RISING

ONLY

RD

S

ENABLE

5

QB

4

GND

0.5pF

4300a3 BD

4300a3fa

6

LTC4300A-3

operaTion

Start-Up

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the backplane

and card capacitances isolated. Because of this isolation,

the waveforms on the backplane busses look slightly

different than the corresponding card bus waveforms, as

described here.

When the LTC4300A-3 first receives power on its V pin,

CC

either during power-up or during live insertion, it starts

in an undervoltage lockout (UVLO) state, ignoring any

activity on the SDA and SCL pins until V rises above

CC

2.5V. The part also waits for V

to rise above 2V. This

CC2

ensures that the part does not try to function until it has

enough voltage to do so.

Input to Output Offset Voltage

When a logic low voltage, V

, is driven on any of

LOW1

During this time, the 1V precharge circuitry is also ac-

tive and forces 1V through 100k nominal resistors to the

SDA and SCL pins. Because the I/O card is being plugged

into a live backplane, the voltage on the backplane SDA

the LTC4300A-3’s data or clock pins, the LTC4300A-3

regulates the voltage on the other side of the part (call

it V

) to a slightly higher voltage, as directed by the

LOW2

following equation (typical):

and SCL busses may be anywhere between 0V and V .

CC

Precharging the SCL and SDA pins to 1V minimizes the

worst-case voltage differential these pins will see at the

moment of connection, therefore minimizing the amount

of disturbance caused by the I/O card.

V

LOW2

= V + 75mV + (V /R) • 70 [Ω]

LOW1

CC

where R is the bus pull-up resistance in ohms. For ex-

ample, if a device is forcing SDAOUT to 10mV where

V

= 3.3V and the pull-up resistor R on SDAIN is 10k,

CC

OncetheLTC4300A-3comesoutofUVLO, itassumesthat

SDAIN and SCLIN have been inserted into a live system

andthatSDAOUTandSCLOUTarebeingpoweredupatthe

same time as itself. Therefore, it looks for either a stop bit

or bus idle condition on the backplane side to indicate the

completion of a data transaction. When either one occurs,

the part also verifies that both the SDAOUT and SCLOUT

voltages are high. When all of these conditions are met,

theinput-to-outputconnectioncircuitryisactivated,joining

the SDA and SCL busses on the I/O card with those on

the backplane, and the rise time accelerators are enabled.

then the voltage on SDAIN = 10mV + 75mV + (3.3/10000)

• 70 = 108mV (typical). See the Typical Performance Char-

acteristics section for curves showing the offset voltage

as a function of V and R.

CC

Propagation Delays

Duringarisingedge,therisetimeoneachsideisdetermined

by the combined pull-up current of the LTC4300A-3 boost

currentandthebusresistorandtheequivalentcapacitance

on the line. If the pull-up currents are the same, a differ-

ence in rise time occurs which is directly proportional to

the difference in capacitance between the two sides. This

Connection Circuitry

effect is displayed in Figure 1 for V = V

= 3.3V and

CC

CC2

Oncetheconnectioncircuitryisactivated,thefunctionality

oftheSDAINandSDAOUTpinsisidentical.Alowforcedon

eitherpinatanytimeresultsinbothpinvoltagesbeinglow.

For proper operation, logic low input voltages should be

no higher than 0.4V with respect to the ground pin voltage

of the LTC4300A-3. SDAIN and SDAOUT enter a logic high

state only when all devices on both SDAIN and SDAOUT

release high. The same is true for SCLIN and SCLOUT.

Thisimportantfeatureensuresthatclockstretching, clock

synchronization,arbitrationandtheacknowledgeprotocol

always work, regardless of how the devices in the system

are tied to the LTC4300A-3.

a 10k pull-up resistor on each side (50pF on one side

and 150pF on the other). Since the output side has less

capacitance than the input, it rises faster and the effective

propagation delay is negative.

There is a finite propagation delay through the connection

circuitry for falling waveforms. Figure 2 shows the falling

edge waveforms for the same V , pull-up resistors and

CC

equivalent capacitance conditions as used in Figure 1.

An external NMOS device pulls down the voltage on

the side with 150pF capacitance; the LTC4300A-3 pulls

down the voltage on the opposite side, with a delay of

55ns. This delay is always positive and is a function of

4300a3fa

7

LTC4300A-3

INPUT

SIDE

150pF

OUTPUT

SIDE

50pF

OUTPUT

SIDE

INPUT

SIDE

150pF

50pF

0.5V/DIV

4300a3 F01

4300a3 F02

200ns/DIV

Figure 1. Input–Output Connection Low to High Transition

Figure 2. Input–Output Connection High to Low Transition

supply voltage, temperature and the pull-up resistors and For example, assume an SMBus system with V = 3V,

CC

equivalent bus capacitances on both sides of the bus. The a 10k pull-up resistor and equivalent bus capacitance of

Typical Performance Characteristics section shows t

200pF. The rise time of an SMBus system is calculated

– 0.15V) to (V + 0.15V), or 0.65V

PHL

as a function of temperature and voltage for 10k pull-up from (V

IL(MAX)

IH(MIN)

resistors and 100pF equivalent capacitance on both sides to 2.25V. It takes an RC circuit 0.92 time constants to

of the part. By comparison with Figure 2, the V = V traverse this voltage for a 3V supply; in this case, 0.92

CC

CC2

= 3.3V curve shows that increasing the capacitance from • (10k • 200pF) = 1.84µs. Thus, the system exceeds the

50pF to 100pF results in a propagation delay increase maximum allowed rise time of 1µs by 84%. However,

from 55ns to 75ns. Larger output capacitances translate using the rise time accelerators, which are activated at a

to longer delays (up to 150ns). Users must quantify the DC threshold of below 0.65V, the worst-case rise time is:

difference in propagation times for a rising edge versus (2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the

a falling edge in their systems and adjust setup and hold 1µs rise time requirement.

times accordingly.

ENABLE Low Current Disable

Rise Time Accelerators

GroundingtheENABLEpindisconnectsthebackplaneside

Onceconnectionhasbeenestablished,risetimeaccelerator from the card side, disables the rise time accelerators,

circuits on all four SDA and SCL pins are activated. These disables the bus precharge circuitry and puts the part in a

allow the user to choose weaker DC pull-up currents on near-zero current state. When the pin voltage is driven all

the bus, reducing power consumption while still meet- the way to V , the part waits for data transactions on both

CC

ing system rise time requirements. During positive bus the backplane and card sides to be complete (as described

transitions, the LTC4300A-3 switches in 2mA (typical) of in the Start-Up section) before reconnecting the two sides.

current to quickly slew the SDA and SCL lines once their

DC voltages exceed 0.6V. Using a general rule of 20pF of

capacitanceforeverydeviceonthebus(10pFforthedevice

and10pFforinterconnect),chooseapull-upcurrentsothat

the bus will rise on its own at a rate of at least 1.25V/µs

to guarantee activation of the accelerators.

4300a3fa

8

LTC4300A-3

applicaTions inForMaTion

Resistor Pull-Up Value Selection

Live Insertion and Capacitance Buffering Application

The system pull-up resistors must be strong enough to

provide a positive slew rate of 1.25V/µs on the SDA and

SCL pins, in order to activate the boost pull-up currents

during rising edges. Choose maximum resistor value R

using the formula:

Figures 3 and 4 illustrate the usage of the LTC4300A-3

in applications that take advantage of both its Hot Swap

controlling and capacitance buffering features. In all of

these applications, note that if the I/O cards were plugged

directly into the backplane, all of the backplane and card

capacitances would add directly together, making rise-

and fall time requirements difficult to meet. Placing a

LTC4300A-3 on the edge of each card, however, isolates

the card capacitance from the backplane. For a given I/O

card, the LTC4300A-3 drives the capacitance of every-

thing on the card and the backplane must drive only the

capacitance of the LTC4300A-3, which is less than 10pF.

R ≤ (V

– 0.6)(800,000)/C

CC(MIN)

where R is the pull-up resistor value in ohms, V

CC(MIN)

is the minimum V voltage and C is the equivalent bus

CC

capacitance in picofarads (pF).

In addition, regardless of the bus capacitance, always

choose R ≤ 16k for V = 5.5V maximum, R ≤ 24k for

CC

V

= 3.6V maximum. The start-up circuitry requires

CC

logic high voltages on SDAOUT and SCLOUT to connect

the backplane to the card, and these pull-up values are

needed to overcome the precharge voltage.

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

C1

V

CC2

R1

10k

R2

10k

0.01µF

R7

10k

R8

10k

V

CC2

SDAOUT

SCLOUT

ENABLE

CARD_SDA

CARD_SCL

V

CC

SDAIN

SCLIN

LTC4300A-3

GND

SDA

SCL

C2 0.01µF

R3

10k

ENA1

I/O PERIPHERAL CARD 2

C3

R4

10k

R5

10k

0.01µF

V

CC2

SDAOUT

SCLOUT

ENABLE

CARD2_SDA

CARD2_SCL

V

CC

SDAIN

SCLIN

LTC4300A-3

GND

C4 0.01µF

R6

10k

ENA2

4300a3 F03

Figure 3. The LTC4300A-3 in a PCI Application Where All the Pins Have the Same Length.

ENABLE Should Be Held Low Until All Transients Associated with the Live Insertion Have Settled

4300a3fa

9

LTC4300A-3

applicaTions inForMaTion

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

C1

V

CC2

R1

10k

R2

10k

0.01µF

R7

10k

R8

10k

V

CC2

SDAOUT

SCLOUT

ENABLE

CARD_SDA

CARD_SCL

V

CC

SDAIN

SCLIN

SDA

SCL

LTC4300A-3

GND

C2

0.01µF

R3

10k

ENA1

I/O PERIPHERAL CARD 2

C3

R4

10k

R5

10k

0.01µF

V

CC2

SDAOUT

SCLOUT

ENABLE

CARD2_SDA

CARD2_SCL

V

CC

LTC4300A-3

GND

SDAIN

SCLIN

C4

R6

10k

0.01µF

ENA2

4300A-3 F04

Figure 4. The LTC4300A-3 in a Custom Application. Making ENABLE the Shortest Pin Ensures that

V_CCand V_CC2Connect Before ENABLE Is Allowed to Go High, Connecting the Card to the Backplane

5V to 3.3V Level Translator and Power Supply

Redundancy

This application also provides power supply redundancy.

If the V

voltage falls below its UVLO threshold, the

CC2

LTC4300A-3 disconnects the backplane from the card,

so that the backplane can continue to function. If the

Systems requiring different supply voltages for the back-

plane side and the card side can use the LTC4300A-3, as

shown in Figure 5. The pull-up resistors on the card side

V

voltage falls below its UVLO threshold and the V

CC2

CC

voltage remains active, hold ENABLE at ground to ensure

connect from SDAOUT to SCLOUT to V , and those on

CC2

proper operation.

thebackplanesideconnectfromSDAINandSCLINtoV .

CC

TheLTC4300A-3functionsforvoltagesrangingfrom2.7V

to 5.5V on both V and V . There is no constraint on

CC

CC2

CC

the voltage magnitudes of V and V

with respect to

CC2

each other.

4300a3fa

10

LTC4300A-3

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698 Rev C)

0.70 ±0.05

3.5 ±0.05

2.10 ±0.05 (2 SIDES)

1.65 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50

BSC

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.125

0.40 ±0.10

TYP

5

8

3.00 ±0.10

(4 SIDES)

1.65 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

(DD8) DFN 0509 REV C

4

1

0.25 ±0.05

0.75 ±0.05

0.200 REF

0.50 BSC

2.38 ±0.10

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

4300a3fa

11

LTC4300A-3

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-ꢀꢂꢂ0 Rev F)

0.889 0.ꢀꢁ7

(.035 .005)

5.ꢁ3

3.ꢁ0 – 3.45

(.ꢁ0ꢂ)

(.ꢀꢁꢂ – .ꢀ3ꢂ)

MIN

3.00 0.ꢀ0ꢁ

(.ꢀꢀ8 .004)

(NOTE 3)

0.5ꢁ

(.0ꢁ05)

REF

0.ꢂ5

(.0ꢁ5ꢂ)

BSC

0.4ꢁ 0.038

(.0ꢀꢂ5 .00ꢀ5)

TYP

8

7 ꢂ 5

RECOMMENDED SOLDER PAD LAYOUT

3.00 0.ꢀ0ꢁ

(.ꢀꢀ8 .004)

(NOTE 4)

4.90 0.ꢀ5ꢁ

(.ꢀ93 .00ꢂ)

DETAIL “A”

0.ꢁ54

(.0ꢀ0)

0° – ꢂ° TYP

GAUGE PLANE

ꢀ

ꢁ

3

4

0.53 0.ꢀ5ꢁ

(.0ꢁꢀ .00ꢂ)

ꢀ.ꢀ0

(.043)

MAX

0.8ꢂ

(.034)

REF

DETAIL “A”

0.ꢀ8

(.007)

SEATING

PLANE

0.ꢁꢁ – 0.38

0.ꢀ0ꢀꢂ 0.0508

(.009 – .0ꢀ5)

(.004 .00ꢁ)

0.ꢂ5

(.0ꢁ5ꢂ)

BSC

TYP

MSOP (MS8) 0307 REV F

NOTE:

ꢀ. DIMENSIONS IN MILLIMETER/(INCH)

ꢁ. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.ꢀ0ꢁmm (.004") MAX

4300a3fa

12

LTC4300A-3

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

09/12 Updated format of Pin Configuration and Order Information sections

2

3

Added T

parameter to Electrical Characteristics

PHL,SKEW

4300a3fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

13

LTC4300A-3

Typical applicaTion

V

CC

CARD_V , 3.3V

CC

5V

C2

0.01µF

C1

0.01µF

R3

10k

R2

10k

R1

10k

R4

10k

V

CC2

CC

SDAIN

SCLIN

SDAOUT

SCLOUT

CARD_SDA

CARD_SCL

SDA

SCL

LTC4300A-3

GND

4300A-3 F05

ENABLE

Figure 5. 5V to 3.3V Level Translator

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC1380/LTC1393

Single-Ended 8-Channel/Differential 4-Channel

Analog Mux with SMBus Interface

Low R : 35Ω Single-Ended/70Ω Differential, Expandable to 32 Single or

ON

16 Differential Channels

LTC1427-50

LTC1623

Micropower, 10-Bit Current Output DAC with SMBus Precision 50µA 2.5% Tolerance Over Temperature, 4 Selectable SMBus

Interface

Addresses, DAC Powers Up at Zero or Mid-Scale

Dual High Side Switch Controller with SMBus

Interface

8 Selectable Addresses/16-Channel Capability

LTC1663

SMBus Interface 10-Bit Rail-to-Rail Micropower DAC DNL < 0.75LSB Max, 5-Lead SOT-23 Package

2

LTC1694/LTC1694-1 SMBus Accelerator

Improved SMBus/I C Rise Time, Ensures Data Integrity with Multiple

2

SMBus/I C Devices

LT1786F

LTC1695

LTC1840

SMBus Controlled CCFL Switching Regulator

1.25A, 200kHz, Floating or Grounded Lamp Configurations

0.75Ω PMOS 180mA Regulator, 6-Bit DAC

2

SMBus/I C Fan Speed Controller in ThinSOT™

2

Dual I C Fan Speed Controller

Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0

LTC4300A-1/

LTC4300A-2

Hot Swappable 2-Wire Bus Buffer

Preserves Data Integrity Under Hot Swap Conditions, Provides Capacitive

Buffering, Rise Time Acceleration

LTC4301

Supply Independent 2-Wire Bus Buffer

Provides Capacitive Buffer, 3.3V to 5V Level Translation with Only the Card

Bus V Supply

CC

LTC4301L

Hot-Swappable 2-Wire Bus Buffer with Low Voltage

Level Translation

Level Translators, 1V Signals to Standard 3.3V and 5V Logic Rails

2

LTC4302-1/

LTC4302-2

Addressable I C and SMBus Compatible Bus Buffers Provides Capacitive Buffering, Rise time Acceleration, and Input to Output

Connection Control Using 2-Wire Bus Commands

4300a3fa

LT 0912 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

14

●

 LINEAR TECHNOLOGY CORPORATION 2004

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4300A-3IDD#PBF
厂家：	Linear
描述：	LTC4300A-3 - Level Shifting Hot Swappable 2-Wire Bus Buffer with Enable; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C 光电二极管
文件：	总14页 (文件大小：202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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