LTC6992HDCB6-2-PBF [Linear]
TimerBlox Voltage-Controlled Pulse Width Modulator (PWM); TimerBlox系列电压控制型脉宽调制器（ PWM ）
| 型号： | LTC6992HDCB6-2-PBF |
| 厂家： | 
Linear |
| 描述： | TimerBlox Voltage-Controlled Pulse Width Modulator (PWM) |
| 文件： | 总32页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electrical Specifications Subject to Change
LTC6992-1/-2/-3/-4
TimerBlox
Voltage-Controlled Pulse
Width Modulator (PWM)
FEATURES
DESCRIPTION
n
Pulse Width Modulation (PWM) Controlled by
The LTC®6992 is a silicon oscillator with an easy-to-use
analog voltage-controlled pulse width modulation (PWM)
capability. The LTC6992 is part of the TimerBlox™ family
of versatile silicon timing devices.
Simple 0V to 1V Analog Input
n
Four Available Options Define Duty Cycle Limits
– Minimum Duty Cycle at 0% or 5%
– Maximum Duty Cycle at 95% or 100%
A single resistor, R , programs the LTC6992’s inter-
SET
n
Frequency Range: 3.81Hz to 1MHz
nal master oscillator frequency. The output frequency
is determined by this master oscillator and an internal
n
Single Resistor Programs Frequency with <2.4%
Maximum Error
frequency divider, N , programmable to eight settings
DIV
n
PWM Duty Cycle Error <4.5% Maximum
from 1 to 16384.
n
Frequency Modulation (VCO) Capability
n
1MHz 50kΩ
NDIV RSET
2.25V to 5.5V Single Supply Operation
fOUT
=
•
,NDIV = 1,4,16 …16384
n
115μA Supply Current at 100kHz
n
500μs Start-Up Time
Applyingavoltagebetween0Vand1VontheMODpinsets
the duty cycle, according to the following formula:
n
CMOS Output Driver Sources/Sinks 20mA
n
–40°C to 125°C Operating Temperature Range
n
VMOD
0.8 • VSET
VMOD −100mV
1
8
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
Duty Cycle =
−
≅
and 2mm × 3mm DFN
800mV
The four versions differ in their minimum/maximum duty
cycle. Note that a minimum duty cycle limit of 0% or
maximum duty cycle limit of 100% allows oscillations to
stop at the extreme duty cycle settings.
APPLICATIONS
n
LED Dimming Control
n
PWM Servo Loops
n
High Vibration, High Acceleration Environments
OUTPUT DUTY CYCLE LIMITS
PWM DUTY
n
Portable and Battery-Powered Equipment
DEVICE NAME
LTC6992-1
LTC6992-2
LTC6992-3
LTC6992-4
CYCLE RANGE
0% to 100%
5% to 95%
MIN
GND
MAX
V
+
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
TimerBlox and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
0% to 95%
GND
+
5% to 100%
V
TYPICAL APPLICATION
1MHz Pulse Width Modulator
ANALOG PWM
DUTY CYCLE
MOD
MOD
GND
SET
OUT
CONTROL
(0V TO 1V)
0.5V/DIV
LTC6992
+
V
+
V
C1
0.1ꢀF
OUT
1V/DIV
DIV
6992 TA01a
R
SET
50k
6992 TA01b
2ꢀs/DIV
69921234p
1
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
(Note 1)
ABSOLUTE MAXIMUM RATINGS
+
Supply Voltage (V ) to GND .........…………………….6V
Specified Temperature Range (Note 3)
Maximum Voltage On Any Pin
LTC6992C................................................ 0°C to 70°C
LTC6992I .............................................–40°C to 85°C
LTC6992H.......................................... –40°C to 125°C
Junction Temperature .......................................... 150°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
+
.............................(GND – 0.3V) ≤ V ≤ (V + 0.3V)
PIN
Operating Temperature Range (Note 2)
LTC6992C................................................ 0°C to 70°C
LTC6992I .............................................–40°C to 85°C
LTC6992H..........................................–40°C to 125°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
6
5
4
OUT
GND
MOD
V+
DIV
SET
1
2
3
MOD 1
GND 2
SET 3
6 OUT
7
GND
+
5 V
4 DIV
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
DCB PACKAGE
6-LEAD (2mm s 3mm) PLASTIC DFN
T
= 150°C, θ = 230°C/W, θ = 51°C/W
JMAX
JA
JC
T
= 150°C, θ = 64°C/W, θ = 10.6°C/W
JA JC
EXPOSED PAD (PIN 7) IS GND, PCB CONNECTION IS OPTIONAL
JMAX
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
LTC6992CDCB6-1#PBF
LTC6992IDCB6-1#PBF
LTC6992HDCB6-1#PBF
LTC6992CS6-1#PBF
LTC6992IS6-1#PBF
LTC6992CDCB6-1#TRPBF
LTC6992IDCB6-1#TRPBF
LTC6992HDCB6-1#TRPBF
LTC6992CS6-1#TRPBF
LTC6992IS6-1#TRPBF
LTC6992HS6-1#TRPBF
LTC6992CDCB6-2#TRPBF
LTC6992IDCB6-2#TRPBF
LTC6992HDCB6-2#TRPBF
LTC6992CS6-2#TRPBF
LTC6992IS6-2#TRPBF
LTC6992HS6-2#TRPBF
LTC6992CDCB6-3#TRPBF
LTC6992IDCB6-3#TRPBF
LTC6992HDCB6-3#TRPBF
LTC6992CS6-3#TRPBF
LTC6992IS6-3#TRPBF
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6992HS6-1#PBF
LTC6992CDCB6-2#PBF
LTC6992IDCB6-2#PBF
LTC6992HDCB6-2#PBF
LTC6992CS6-2#PBF
LTC6992IS6-2#PBF
6-Lead Plastic TSOT-23
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6992HS6-2#PBF
LTC6992CDCB6-3#PBF
LTC6992IDCB6-3#PBF
LTC6992HDCB6-3#PBF
LTC6992CS6-3#PBF
LTC6992IS6-3#PBF
6-Lead Plastic TSOT-23
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
6-Lead Plastic TSOT-23
–40°C to 85°C
69921234p
2
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
ORDER INFORMATION
LEAD FREE FINISH
LTC6992HS6-3#PBF
LTC6992CDCB6-4#PBF
LTC6992IDCB6-4#PBF
LTC6992HDCB6-4#PBF
LTC6992CS6-4#PBF
LTC6992IS6-4#PBF
LTC6992HS6-4#PBF
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
–40°C to 125°C
0°C to 70°C
LTC6992HS6-3#TRPBF
LTC6992CDCB6-4#TRPBF
LTC6992IDCB6-4#TRPBF
LTC6992HDCB6-4#TRPBF
LTC6992CS6-4#TRPBF
LTC6992IS6-4#TRPBF
LTC6992HS6-4#TRPBF
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
6-Lead Plastic TSOT-23
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
6-Lead Plastic TSOT-23
–40°C to 85°C
6-Lead Plastic TSOT-23
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET
DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
,
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillation Frequency
f
Output Frequency
3.81
1000000
Hz
OUT
Frequency Accuracy (Note 4)
3.81Hz ≤ f
≤ 1MHz
0.8
1.7
2.4
%
%
Δf
OUT
OUT
l
l
Frequency Drift Over Temperature
Frequency Drift Over Supply
0.005
%/°C
Δf /ΔT
OUT
+
+
l
l
V = 4.5V to 5.5V
0.25
0.08
0.65
0.18
%/V
%/V
Δf /ΔV
OUT
+
V = 2.25V to 4.5V
Period Jitter (Note 11)
N
N
= 1
= 4
1.2
%
DIV
DIV
P-P
0.4
0.07
%
P-P
%
%
RMS
N
DIV
= 16
0.15
0.022
%
RMS
P-P
Long-Term Stability of Output
Frequency (Note 9)
TBD
ppm/√kHz
BW
Frequency Modulation Bandwidth
TBD
TBD
kHz
ꢀs
FM
t
Frequency Change Settling Time
(Note 10)
t
= t /N
MASTER OUT DIV
S,FM
Pulse Width Modulation
PWM Duty Cycle Accuracy
l
l
V
V
= 0.2 • V to 0.8 • V
1.5
2.0
4.5
4.9
%
%
ΔD
MOD
MOD
SET
SET
< 0.2 • V or V
> 0.8 • V
SET
MOD
SET
MOD
MOD
MOD
MOD
l
l
l
l
D
D
Maximum Duty Cycle Limit
Minimum Duty Cycle Limit
LTC6992-1/LTC6992-3, POL = 0, V
LTC6992-2/LTC6992-4, POL = 0, V
LTC6992-1/LTC6992-4, POL = 0, V
LTC6992-2/LTC6992-3, POL = 0, V
= 1V
= 1V
= 0V
= 0V
100
%
%
MAX
90.5
95
99
0
%
MIN
1
5
9.5
%
BW
PWM Duty Cycle Bandwidth
TBD
TBD
kHz
ꢀs
PWM
t
Duty Cycle Setting Time (Note 6)
t = t /N
MASTER OUT DIV
S,PWM
69921234p
3
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET
DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
,
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply
+
l
l
l
l
l
l
l
l
l
l
V
Operating Supply Voltage Range
Power-On Reset Voltage
Supply Current
2.25
5.5
1.95
450
285
420
280
390
265
170
150
V
V
+
I
R = ∞, R = 50k,
DIV
V = 5.5V
365
225
350
225
325
215
120
105
ꢀA
ꢀA
ꢀA
ꢀA
ꢀA
ꢀA
ꢀA
ꢀA
S
L
N
SET
= 1
+
V = 2.25V
+
R = ∞, R = 50k,
V = 5.5V
L
DIV
SET
N
= 4
+
V = 2.25V
+
R = ∞, R = 50k,
V = 5.5V
L
DIV
SET
N
≥ 16
+
V = 2.25V
+
R = ∞, R = 800k,
V = 5.5V
L
DIV
SET
N
= 1 to 16, 384
+
V = 2.25V
Analog Inputs
l
l
l
V
Voltage at SET Pin
0.97
50
1.00
75
1.03
800
V
ꢀV/°C
kΩ
SET
ΔV /ΔT
V
Drift Over Temperature
SET
SET
R
Frequency-Setting Resistor
MOD Pin Input Capacitance
MOD Pin Input Current
SET
2.5
pF
l
l
10
nA
V
V
V
V
Voltage for Maximum Duty
LTC6992-1/LTC6992-4, POL = 0, D = 100%
LTC6992-2/LTC6992-3, POL = 0, D = 95%
0.90•V
0.86•V
0.936•V
SET
V
V
MOD,HI
MOD,LO
DIV
MOD
SET
SET
Cycle
l
V
Voltage for Minimum Duty
LTC6992-1/LTC6992-3, POL = 0, D = 0%
LTC6992-2/LTC6992-4, POL = 0, D = 5%
0.064•V
0
0.10•V
0.14•V
V
V
MOD
SET
SET
SET
Cycle
+
l
l
DIV Pin Voltage
V
V
+
ΔV /ΔV
DIV Pin Valid Code Range (Note 5)
Deviation from Ideal
1.5
%
DIV
+
V
/V = (DIVCODE + 0.5)/16
DIV
l
DIV Pin Input Current
10nA
Digital Output
l
I
Output Output Current
20
mA
OUT(MAX)
+
l
l
V
High Level Output Voltage
V = 5.5V
I
I
= –1mA
5.45
4.84
5.48
5.15
V
V
OH
OL
OUT
OUT
= –16mA
+
l
l
V = 3.3V
I
I
= –1mA
= –10mA
3.24
2.75
3.27
2.99
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= –1mA
= -8mA
2.17
1.58
2.21
1.88
V
V
OUT
OUT
+
l
l
V
Low Level Output Voltage
V = 5.5V
I
I
= 1mA
= 16mA
0.02
0.26
0.04
0.54
V
V
OUT
OUT
+
l
l
V = 3.3V
I
I
= 1mA
= 10mA
0.03
0.22
0.05
0.46
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= 1mA
= 8mA
0.03
0.26
0.07
0.54
V
V
OUT
OUT
69921234p
4
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, VMOD = 0V to VSET
,
DIVCODE = 0 to 15 (NDIV = 1 to 16,384), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
t
t
Output Rise Time (Note 8)
V = 5.5V
1.1
1.7
2.7
ns
ns
ns
r
f
+
V = 3.3V
+
V = 2.25V
+
Output Fall Time (Note 8)
V = 5.5V
1.0
1.6
2.4
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 2: The LTC6992C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 9: Long term drift on silicon oscillators is primarily due to the
movement of ions and impurities within the silicon and is tested at 30°C
under otherwise nominal operating conditions. Long term drift is specified
as ppm/√kHr due to the typically non-linear nature of the drift. To calculate
drift for a set time period, translate that time into thousands of hours, take
the square root and multiply by the typical drift number. For instance, a
year is 8.77kHr and would yield a drift of 888ppm at 300ppm/√kHr. Drift
without power applied to the device may be approximated as 1/10th of the
drift with power, or 30ppm/√kHr for a 300ppm/√kHr device.
Note 3: The LTC6992C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6992C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6992I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6992H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 4: Frequency accuracy is defined as the deviation from the f
OUT
equation, assuming R is used to program the frequency.
SET
Note 10: Frequency change settling time is the amount of time required
for the output to settle within 1% of the final frequency after a 0.5x or 2x
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: Duty cycle setting time is the is the amount of time required for
the output to settle within 1% of the final duty cycle after a 10% change
change in I
.
SET
Note 11: Jitter is the ratio of the peak-to-peak deviation of the period to
the mean of the period. This specification is based on characterization and
is not 100% tested.
in the setting ( 80mV step in V
).
MOD
69921234p
5
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
Frequency Error vs Temperature
Frequency Error vs Temperature
Frequency Error vs Temperature
3
2
3
2
3
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
R = 800k
SET
2
1
R
= 200k
R
= 50k
SET
SET
3 PARTS
3 PARTS
3 PARTS
1
1
0
0
0
–1
–2
–3
–1
–2
–3
–1
–2
–3
GUARANTEED MIN OVER TEMPERATURE
25 50 75 100 125
TEMPERATURE (°C)
GUARANTEED MIN OVER TEMPERATURE
25 50 75 100 125
TEMPERATURE (°C)
GUARANTEED MIN OVER TEMPERATURE
–50
0
–25
100 125
–50
0
–50
0
25
50
75
–25
–25
TEMPERATURE (°C)
6992 G02
6992 G01
6992 G03
Frequency Error vs RSET
Frequency Drift vs Supply Voltage
Typical VSET Distribution
0.5
0.4
3
2
250
200
150
100
50
2 LOTS
DFN AND SOT-23
1274 UNITS
GUARANTEED MAX OVER TEMPERATURE
3 PARTS
0.3
0.2
1
R
= 50k
SET
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
–2
–3
R
= 800k
SET
R
= 200k
SET
+
REFERENCED TO V = 4.5V
GUARANTEED MIN OVER TEMPERATURE
0
2
4
5
6
3
800
0.98
0.996
V
SET
1.004
(V)
1.012
1.02
50
200
(k)
400
0.988
100
SUPPLY VOLTAGE (V)
R
SET
6992 G05
6992 G04
6992 G06
VSET Drift vs ISET
VSET Drift vs Supply
VSET vs Temperature
1.0
0.8
1.0
0.8
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
3 PARTS
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
+
REFERENCED TO I
= 10ꢀA
REFERENCED TO V = 4V
SET
0
10
(ꢀA)
15
20
5
6
2
4
5
100 125
3
–50
0
25
50
75
–25
I
SUPPLY (V)
TEMPERATURE (°C)
SET
6992 G07
6992 G08
6992 G09
69921234p
6
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
NDIV = 1 Duty Cycle Error vs RSET
NDIV = 1 Duty Cycle Error vs RSET
NDIV = 1 Duty Cycle Error vs RSET
5
4
5
4
5
4
V
/V
= 0.5 (50%)
V
/V
= 0.8 (87.5%)
V
/V
= 0.2 (12.5%)
MOD SET
MOD SET
MOD SET
DIVCODE = 0
3 PARTS
DIVCODE = 0
3 PARTS
DIVCODE = 0
3 PARTS
3
3
3
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
400
800
50
100
200
(k)
400
800
50
100
200
(k)
50
100
200
(k)
400
800
R
R
R
SET
SET
SET
6992 G11
6992 G10
6992 G12
NDIV > 1 Duty Cycle Error vs RSET
NDIV > 1 Duty Cycle Error vs RSET
NDIV > 1 Duty Cycle Error vs RSET
5
4
5
4
5
4
V
/V
= 0.2 (12.5%)
V
/V
= 0.8 (87.5%)
V
/V
= 0.5 (50%)
MOD SET
MOD SET
MOD SET
DIVCODE = 4
3 PARTS
DIVCODE = 4
3 PARTS
DIVCODE = 4
3 PARTS
3
3
3
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
50
100
200
(k)
400
800
400
800
50
100
200
(k)
50
100
200
(k)
400
800
R
R
R
SET
SET
SET
6992 G13
6992 G15
6992 G14
NDIV = 1 Duty Cycle Clamps
vs RSET
NDIV > 1 Duty Cycle Error vs RSET
97
96
95
94
93
92
97
DIVCODE = 4
3 PARTS
DIVCODE = 0
3 PARTS
96
95
94
93
92
LTC6992-2/LTC6992-3
= V
V
LTC6992-2/LTC6992-3
MOD
SET
V
= V
MOD
SET
8
7
6
5
4
3
8
7
6
5
4
3
LTC6992-2/LTC6992-4
= V
LTC6992-2/LTC6992-4
V
MOD
SET
V
= V
MOD
SET
50
100
200
(k)
400
800
50
100
200
400
800
R
R
(k)
SET
SET
6992 G17
6992 G16
69921234p
7
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
NDIV = 1 Duty Cycle Error
vs Temperature
NDIV = 1 Duty Cycle Error
vs Temperature
NDIV = 1 Duty Cycle Error
vs Temperature
5
4
5
4
5
GUARANTEED MAX
GUARANTEED MAX
= 0.2 (12.5%)
4
3
GUARANTEED MAX
V
/V
= 0.5 (50%)
V
/V
= 0.8 (87.5%)
V
/V
MOD SET
MOD SET
MOD SET
3
3
DIVCODE = 0
3 PARTS
DIVCODE = 0
3 PARTS
DIVCODE = 0
3 PARTS
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
GUARANTEED MIN
GUARANTEED MIN
GUARANTEED MIN
–50
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
–25
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
6992 G19
6992 G18
6992 G20
NDIV > 1 Duty Cycle Error
vs Temperature
NDIV > 1 Duty Cycle Error
vs Temperature
NDIV > 1 Duty Cycle Error
vs Temperature
5
5
4
5
4
4
3
GUARANTEED MAX
GUARANTEED MAX
GUARANTEED MAX
V
/V
= 0.5 (50%)
V
/V
= 0.2 (12.5%)
V
/V
= 0.8 (87.5%)
MOD SET
MOD SET
MOD SET
3
3
DIVCODE = 4
3 PARTS
DIVCODE = 4
3 PARTS
DIVCODE = 4
3 PARTS
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
GUARANTEED MIN
50 75 100 125
GUARANTEED MIN
GUARANTEED MIN
–50
0
25
75 100 125
–25
–50
0
25
50
–25
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
6992 G22
6992 G21
6992 G23
NDIV = 1 Duty Cycle Clamps
vs Temperature
NDIV > 1 Duty Cycle Clamps
vs Temperature
97
96
95
94
93
92
97
96
95
94
93
92
DIVCODE = 0
3 PARTS
DIVCODE = 4
3 PARTS
LTC6992-2/LTC6992-3
= V
LTC6992-2/LTC6992-3
= V
V
MOD
SET
V
MOD
SET
8
7
6
5
4
3
8
7
6
5
4
3
LTC6992-2/LTC6992-4
MOD
LTC6992-2/LTC6992-4
MOD
V
= GND
V
= GND
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
6992 G24
6992 G25
69921234p
8
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
Duty Cycle Error vs DIVCODE
Duty Cycle Error vs DIVCODE
Duty Cycle Error vs DIVCODE
5
4
5
4
5
V
/V
= 0.2 (12.5%)
V
/V
= 0.5 (50%)
V
/V
= 0.8 (87.5%)
MOD SET
MOD SET
MOD SET
4
3
3 PARTS
3 PARTS
3 PARTS
3
3
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
DIVCODE
DIVCODE
DIVCODE
6992 G26
6992 G27
6992 G28
NDIV = 1 Duty Cycle vs VMOD/ VSET
NDIV > 1 Duty Cycle vs VMOD/ VSET
NDIV > 1 Duty Cycle vs VMOD/ VSET
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
DIVCODE = 4
LTC6992-1/
3 PARTS
DIVCODE = 0
LTC6992-1/
3 PARTS
LTC6992-1/LTC6992-3
LTC6992-4
LTC6992-4
LTC6992-2/
LTC6992-3
LTC6992-2/
LTC6992-3
LTC6992-2/
LTC6992-4
LTC6992-2/
LTC6992-4
LTC6992-2/
LTC6992-3
LTC6992-2/
LTC6992-4
LTC6992-1/
LTC6992-4
DIVCODE = 11
3 PARTS
LTC6992-1/LTC6992-3
LTC6992-1/LTC6992-3
1
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
1
0
0.2
0.4
0.6
0.8
V
/V
(V/V)
V
/V
(V/V)
V
/V
(V/V)
MOD SET
MOD SET
MOD SET
6992 G30
6992 G29
6992 G31
NDIV = 1 Duty Cycle Error vs Ideal
NDIV > 1 Duty Cycle Error vs Ideal
NDIV > 1 Duty Cycle Error vs Ideal
5
4
5
4
5
4
DIVCODE = 11
3 PARTS
DIVCODE = 4
3 PARTS
DIVCODE = 0
3 PARTS
3
3
3
PART A
PART C
2
2
2
PART C
PART B
1
1
1
PART C
PART B
0
0
0
PART B
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
PART A
PART A
0
25
50
75
100
100
0
25
50
75
100
0
25
50
75
IDEAL DUTY CYCLE (%)
IDEAL DUTY CYCLE (%)
IDEAL DUTY CYCLE (%)
6992 G34
6992 G33
6992 G32
69921234p
9
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Linearity Near 67% Duty Cycle
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
Linearity Near 100% Duty Cycle
Linearity Near 95% Duty Cycle
72
100
99
98
97
96
95
94
93
92
91
90
89
88
100
99
98
97
96
95
94
93
92
91
90
89
88
DIVCODE = 4
71 3 PARTS
DIVCODE = 4
LTC6992-2/LTC6992-3
3 PARTS
DIVCODE = 4
LTC6992-1/LTC6992-4
3 PARTS
70
69
68
67
66
65
64
63
62
0.676
0.804
0.836
V
0.868
(V/V)
0.9
0.596
0.612
0.628
/V
0.644
(V/V)
0.66
0.804
0.836
V
0.868
(V/V)
0.9
V
/V
/V
MOD SET
MOD SET
MOD SET
6992 G37
6992 G36
6992 G35
Linearity Near 0% Duty Cycle
Linearity Near 5% Duty Cycle
Linearity Near 31% Duty Cycle
36
12
11
10
9
12
11
10
9
DIVCODE = 4
35 3 PARTS
DIVCODE = 4
LTC6992-1/LTC6992-3
3 PARTS
DIVCODE = 4
LTC6992-2/LTC6992-4
3 PARTS
34
33
32
31
30
29
28
27
26
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
0.388
0.18
0.084
0.116
V
0.148
/V (V/V)
0.18
0.308
0.324
0.34
/V
0.356
(V/V)
0.372
0.084
0.116
V
0.148
(V/V)
V
/V
MOD SET
MOD SET
MOD SET
6992 G40
6992 G38
6992 G39
NDIV > 1 Duty Cycle Drift
vs Supply
Duty Cycle Drift vs Supply
Supply Current vs VMOD
0.5
0.4
0.5
0.4
400
350
300
250
200
150
100
50
DIVCODE = 4
DIVCODE = 0
LTC6992-2
5% CLAMP
0.3
0.3
R
= 50k, ÷1
SET
0.2
0.2
V
/V
= 0.2
MOD SET
95% CLAMP
5% CLAMP
V
0.1
0.1
95% CLAMP
R
R
= 50k, ÷16
SET
SET
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
= 100k, ÷4
= 800k, ÷1
V
/V
= 0.5
MOD SET
/V
= 0.8
MOD SET
V
/V
= 0.2
MOD SET
V
/V
= 0.8
MOD SET
R
SET
V
/V
= 0.5
MOD SET
+
+
REFERENCED TO V = 4V
REFERENCED TO V = 4V
0
2
3
4
5
6
2
3
4
5
6
1
0
0.2
0.4
V
0.6
(V)
0.8
SUPPLY (V)
SUPPLY (V)
MOD
6992 G42
6992 G41
6992 G43
69921234p
10
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
Supply Current vs Supply Voltage
Supply Current vs Temperature
Jitter vs Frequency
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
LTC6992-2
PEAK-TO-PEAK PERIOD
DEVIATION MEASURED
OVER 30s INTERVALS
R
= 50k, ÷1
SET
5.0V, R
= 50k, ÷1
SET
R
SET
= 50k, ÷4
5.0V, R
= 50k, ÷16
SET
V
/V
= 0.5
MOD SET
+
÷1, V = 5V
R
R
= 50k, ÷16
2.5V, R
= 50k, ÷1
SET
SET
SET
+
÷1, V = 2.5V
= 100k, ÷1
= 800k, ÷1
5.0V, R
= 800k, ÷1
= 800k, ÷1
+
SET
SET
÷4, V = 5V
+
R
SET
÷4, V = 2.5V
2.5V, R
÷16
÷64
0
0
–50
0
25
50
75 100 125
2
3
4
5
6
–25
0.01
0.1
1
10
100
1000
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
6992 G45
6992 G44
6992 G46
Supply Current vs Frequency, 5V
Supply Current vs Frequency, 2.5V
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
+
+
V
= 5V
V
= 2.5V
÷4
÷16,384
÷4
÷16,384
÷1
÷1
0
0
0.001 0.01
0.1
1
10
100 1000
100 1000
0.001 0.01
0.1
1
10
FREQUENCY (kHz)
FREQUENCY (kHz)
6992 G47
6992 G48
Output Resistance
vs Supply Voltage
Rise and Fall Time
vs Supply Voltage
Typical ISET Current Limit vs V+
50
45
40
35
30
25
20
15
10
5
3.0
2.5
2.0
1.5
1.0
0.5
0
1000
800
600
400
200
0
C
= 5pF
SET PIN SHORTED TO GND
LOAD
OUTPUT SOURCING CURRENT
t
RISE
t
FALL
OUTPUT SINKING CURRENT
0
2
3
4
5
6
2
3
4
5
6
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6992 G50
6992 G51
6992 G52
69921234p
11
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
V+ = 3.3V, RSET = 200k, and TA = 25°C, unless
Typical Start-Up, POL = 1
TYPICAL PERFORMANCE CHARACTERISTICS
otherwise noted.
Typical Start-Up, POL = 0
+
+
V
V
1V/DIV
1V/DIV
OUT
1V/DIV
OUT
1V/DIV
500ꢀs
500ꢀs
6992 G53
6992 G54
100ꢀs/DIV
100ꢀs/DIV
+
+
V
= 2.5V
V
= 2.5V
DIVCODE = 3 (÷64)
DIVCODE = 12 (÷64, POL = 1)
R
V
= 50k
R
V
= 50k
MOD
SET
MOD
SET
= 0.3V (~25% DUTY CYCLE)
= 0.2V (~87.5% DUTY CYCLE)
PIN FUNCTIONS (DCB/S6)
V (Pin1/Pin5):SupplyVoltage(2.25Vto5.5V).Thissup-
ply must be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1μF capacitor.
+
if I drops below approximately 500nA. A resistor con-
SET
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
50ppm/°C or better temperature coefficient. For lower ac-
curacy applications an inexpensive 1% thick film resistor
may be used.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
+
Input. A V referenced A/D converter monitors the DIV
pin voltage (V ) to determine a 4-bit result (DIVCODE).
DIV
+
V
DIV
may be generated by a resistor divider between V
and GND. Use 1% resistors to ensure an accurate result.
The DIV pin and resistors should be shielded from the
OUT pin or any other traces that have fast edges. Limit the
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
capacitance on the DIV pin to less than 100pF so that V
regulating the V voltage.
DIV
SET
settles quickly. The MSB of DIVCODE (POL) determines
if the PWM signal is inverted before driving the output.
Setting POL = 1 results in a negative transfer function
+
V
MOD
GND
SET
OUT
(duty cycle decreasing as V
increases).
LTC6992
+
MOD
V
+
V
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (V ) is regulated to 1V above GND. The
C1
0.1ꢀF
R1
R2
SET
DIV
amount of current sourced from the SET pin (I ) pro-
SET
6992 PF
R
SET
grams the master oscillator frequency. The I
current
SET
range is 1.25μA to 20μA. The output oscillation will stop
69921234p
12
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
PIN FUNCTIONS (DCB/S6)
MOD (Pin 4/Pin 1): Pulse-Width Modulation Input. The
GND(Pin5/Pin2):Ground.Tietoalowinductanceground
voltageontheMODpincontrolstheoutputdutycycle. The
plane for best performance.
linear control range is between 0.1•V
and 0.9•V
SET
SET
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
(approximately100mVto900mV).Beyondthoselimitsthe
output will either clamp at 5% or 95%, or stop oscillating
(0% or 100% duty cycle), depending on the version.
+
fromGNDtoV withanoutputresistanceofapproximately
30Ω. The duty cycle is determined by the voltage on the
MOD pin. When driving an LED or other low-impedance
load a series output resistor should be used to limit
source/sink current to 20mA.
BLOCK DIAGRAM (S6 Package Pin Numbers Shown)
+
V
5
R1
POL
DIV
4-BIT A/D
CONVERTER
DIGITAL
FILTER
4
R2
OUTPUT
POLARITY
MASTER OSCILLATOR
PULSE WIDTH MODULATOR
I
SET
MCLK
PROGRAMMABLE DIVIDER
÷1, 4, 16, 64, 256, 1024, 4096, 16384
f
= 1MHz • 50kΩ •
OSC
V
V
– 0.1•V
MOD(LIM) SET
t
SET
ON
DUTY CYCLE =
0.8•V
OUT
SET
6
t
OUT
DISABLE OUTPUT
UNTIL SETTLED
HALT OSCILLATOR
IF I < 500nA
SET
t
ON
D =
V
MOD(LIM)
t
OFF
POR
VOLTAGE LIMITER
+
–
V
+
–
REF
V
= 1V
SET
1V
V
MOD
1
3
2
6992 BD
SET
GND
MOD
I
SET
R
SET
69921234p
13
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
The LTC6992 is built around a master oscillator with a
DIVCODE
1MHz maximum frequency. The oscillator is controlled
+
The DIV pin connects to an internal, V referenced 4-bit
by the SET pin current (I ) and voltage (V ), with a
SET
SET
A/D converter that monitors the DIV pin voltage (V ) to
DIV
1MHz • 50k conversion factor that is accurate to 0.8%
determine the DIVCODE value. DIVCODE programs two
under typical conditions.
settings on the LTC6992:
ISET
VSET
1
fMASTER
=
=1MHz • 50k •
1. DIVCODE determines the output frequency divider
tMASTER
setting, N
.
DIV
A feedback loop maintains V at 1V 30mV, leaving I
2. DIVCODE determines the output polarity, via the POL
bit.
SET
SET
as the primary means of controlling the output frequency.
The simplest way to generate I is to connect a resistor
+
SET
V
DIV
may be generated by a resistor divider between V
(R ) between SET and GND, such that I = V /R .
SET
SET
SET SET
and GND as shown in Figure 1.
The master oscillator equation reduces to:
1
1MHz •50k
RSET
fMASTER
=
=
2.25V TO 5.5V
tMASTER
+
V
LTC6992
R1
R2
From this equation it is clear that V drift will not affect
SET
theoutputfrequencywhenusingasingleprogramresistor
(R ). Error sources are limited to R tolerance and the
DIV
SET
SET
inherent frequency accuracy Δf
of the LTC6992.
GND
OUT
6992 F01
R
may range from 50k to 800k (equivalent to I
SET
SET
between 1.25μA and 20μA).
Figure 1. Simple Technique for Setting DIVCODE
The LTC6992 includes a programmable frequency divider
which can further divide the frequency by 1, 4, 16, 64,
256, 1024, 4096 or 16384 before driving the OUT pin.
The divider ratio N is set by a resistor divider attached
DIV
to the DIV pin.
ISET
VSET
1
tOUT
1MHz •50k
NDIV
fOUT
=
=
•
With R in place of V /I the equation reduces to:
SET
SET SET
1
1MHz •50k
fOUT
=
=
tOUT NDIV •RSET
69921234p
14
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
Table 1. DIVCODE Programming
+
DIVCODE
POL
0
N
RECOMMENDED f
R1 (kΩ)
Open
976
R2 (kΩ)
Short
102
V
/V
DIV
DIV
OUT
0
1
1
62.5kHz to 1MHz
15.63kHz to 250kHz
3.906kHz to 62.5kHz
976.6Hz to 15.63kHz
244.1Hz to 3.906kHz
61.04Hz to 976.6Hz
15.26Hz to 244.1Hz
3.815Hz to 61.04Hz
3.815Hz to 61.04Hz
15.26Hz to 244.1Hz
61.04Hz to 976.6Hz
244.1Hz to 3.906kHz
976.6Hz to 15.63kHz
3.906kHz to 62.5kHz
15.63kHz to 250kHz
62.5kHz to 1MHz
≤0.03125 0.015
0.09375 0.015
0.15625 0.015
0.21875 0.015
0.28125 0.015
0.34375 0.015
0.40625 0.015
0.46875 0.015
0.53125 0.015
0.59375 0.015
0.65625 0.015
0.71875 0.015
0.78125 0.015
0.84375 0.015
0.90625 0.015
≥0.96875 0.015
0
4
2
0
16
64
976
182
3
0
1000
1000
1000
1000
1000
887
280
4
0
256
1024
4096
16384
16384
4096
1024
256
64
392
5
0
523
6
0
681
7
0
887
8
1
1000
1000
1000
1000
1000
976
9
1
681
10
11
12
13
14
15
1
523
1
392
1
280
1
16
182
1
4
102
976
1
1
Short
Open
Table 1 offers recommended 1% resistor values that ac-
curatelyproducethecorrectvoltagedivisionaswellasthe
column in Table 1 shows the ideal ratio of V
to the
DIV
supply voltage, which can also be calculated as:
correspondingN andPOLvaluesfortherecommended
DIV
VDIV
V+
DIVCODE + 0.5
=
1.5ꢀ
resistor pairs. Other values may be used as long as:
16
+
1. The V /V ratio is accurate to 1.5% (including resis-
DIV
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
tor tolerances and temperature effects)
is 4, V = 0.281 • 3.3V = 928mV 50mV.
DIV
2. The driving impedance (R1||R2) does not exceed
500kΩ.
Figure2illustratestheinformationinTable1,showingthat
N
DIV
is symmetric around the DIVCODE midpoint.
If the voltage is generated by other means (i.e. the output
+
of a DAC) it must track the V supply voltage. The last
POL BIT = 0
1000
POL BIT = 1
15
0
100
1
14
13
2
10
3
12
11
1
0.1
4
10
5
9
6
7
8
0.01
0.001
+
+
0V
0.5•V
V
INCREASING V
DIV
6992 F02
Figure 2. Frequency Range and POL Bit vs DIVCODE
69921234p
15
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
Pulse Width (Duty Cycle) Modulation
Output Polarity (POL Bit)
The MOD pin is a high impedance analog input providing
direct control of the output duty cycle. The duty cycle
is proportional to the voltage applied to the MOD pin,
The duty cycle equation describes a proportional transfer
function, where duty cycle increases as V
increases.
MOD
The LTC6992 includes a POL bit (determined by the
DIVCODE as described earlier) that inverts the output
signal. This makes the duty cycle gain negative, reducing
V
.
MOD
VMOD
0.8 • VSET
1
8
Duty Cycle = D =
−
duty cycle as V
increases.
MOD
POL = 0
VMOD
1
8
Dꢀ
ꢁ
The PWM duty cycle accuracy ΔD specifies that the above
equation is valid to within 4.5% for V between 0.2 •
0.8 • VSET
D•t
OUT
MOD
V
SET
and 0.8 • V (12.5% to 87.5% duty cycle).
SET
OUT
Since V
= 1V 30mV, the duty cycle equation may be
SET
t
OUT
approximated by the following equation.
POL = 1
OUT
VMOD −100mV
Duty Cycle = D ≅
¥
´
VMOD
1
8
Dꢀ1ꢁ
ꢁ
¦
µ
D•t
0.8 • V
§
¶
OUT
SET
800mV
The V
control range is approximately 0.1V to 0.9V.
MOD
+
Driving V
beyond that range (towards GND or V ) will
MOD
6992 F03
t
OUT
have no further affect on the duty cycle.
Duty Cycle Limits
Figure 3. POL Bit Functionality
The only difference between the four versions of the
LTC6992 is the limits, or clamps, placed on the output
duty cycle. The LTC6992-1 generates output duty cycles
ranging from 0% to 100%, meaning the output can stop
+
oscillating and rest at GND or V .
The LTC6992-2 will never stop oscillating, regardless of
the V
level. Internal clamping circuits limit its duty
MOD
cycle to a 5% to 95% range (1% to 99% guaranteed).
Therefore, its V control range is 0.14 • V to 0.86 •
MOD
SET
V
(approximately 0.14V to 0.86V).
SET
The LTC6992-3 and LTC6992-4 complete the family by
providing one-sided clamping. The LTC6992-3 allows
0% to 95% duty cycle, and the LTC6992-4 allows 5% to
100% duty cycle.
69921234p
16
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
Table 2. Duty Cycle Ranges
DUTY CYCLE RANGE vs V
POL = 1 forces a simple logic inversion, so it changes the
dutycyclerangeoftheLTC6992-3(makingit100%to5%)
and LTC6992-4 (making it 95% to 0%). These transfer
functions are detailed in Figure 4.
= 0V → 1V
MOD
PART NUMBER
LTC6992-1
LTC6992-2
LTC6992-3
LTC6992-4
POL = 0
POL = 1
0% to 100%
5% to 95%
0% to 95%
5% to 100%
100% to 0%
95% to 5%
100% to 5%
95% to 0%
100
100
90
80
70
60
50
40
30
20
10
0
V
/V
= 0.1
MOD SET
90
80
70
60
50
40
30
20
10
0
V
/V
= 0.14
MOD SET
POL = 0
POL = 1
POL = 0
POL = 1
V
/V
= 0.86
MOD SET
V
/V
= 0.9
MOD SET
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
/V (V/V)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
/V (V/V)
1
V
V
MOD SET
MOD SET
6992 F04a
6992 F04b
LTC6992-1
LTC6992-2
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
/V
= 0.14
V
/V
= 0.1
MOD SET
MOD SET
POL = 0
POL = 1
POL = 0
POL = 1
V
/V
= 0.9
V
/V
= 0.86
MOD SET
MOD SET
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
/V (V/V)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
/V (V/V)
1
V
V
MOD SET
MOD SET
6992 F02d
6992 F02c
LTC6992-3
LTC6992-4
Figure 4. PWM Transfer Functions for All LTC6992 Family Parts
69921234p
17
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
OPERATION
Changing DIVCODE After Start-Up
Start-Up Time
Following start-up, the A/D converter will continue
When power is first applied to the LTC6992 the power-on
monitoring V for changes. Changes to DIVCODE will
reset (POR) circuit will initiate the start-up time, t
.
DIV
START
be recognized slowly, as the LTC6992 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
The OUT pin is held low during this time. The typical value
for t ranges from 0.5ms to 8ms depending on the
START
master oscillator frequency (independent of N ):
DIV
t
= 500 • t
MASTER
START(TYP)
The output will begin oscillating after t . If POL = 0
START
t
= 16 • (ΔDIVCODE + 6) • t
MASTER
DIVCODE
the first pulse has the correct width. If POL = 1 (DIVCODE
≥ 8), the first pulse width can be shorter or longer than
expected, depending on the duty cycle setting, and will
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes.
AdigitalfilterisusedtoguaranteetheDIVCODEhassettled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
never be less than 25% of t
.
OUT
Duringstart-up,theDIVpinA/Dconvertermustdetermine
the correct DIVCODE before the output is enabled. The
start-up time may increase if the supply or DIV pin volt-
ages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
+
track V . Less than 100pF will not affect performance.
+
V
DIV
STABLE V
DIV
t
DIVCODE
t
START
OUT
6992 F06
1ST PULSE WIDTH MAY BE INACCURATE
Figure 5. DIVCODE Change from 5 to 2
Figure 6. Start-Up Timing Diagram
69921234p
18
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
Basic Operation
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
The simplest and most accurate method to program the
+
or V /V ratio to apply to the DIV pin.
DIV
LTC6992 is to use a single resistor, R , between the
SET
SET and GND pins. The design procedure is a four step
Step 4: Calculate and Select R
SET
process. After choosing the POL bit setting and proper
The final step is to calculate the correct value for R
using the following equation.
LTC6992 version, select the N value and then calculate
SET
DIV
the value for the R resistor.
SET
1MHz • 50k
NDIV • fOUT
Step 1: Selecting the POL Bit Setting
RSET
=
(1b)
Most applications will use POL = 0, resulting in a positive
transferfunction.However,someapplicationsmayrequirea
negativetransferfunction,whereincreasingV
Select the standard resistor value closest to the calculated
value.
reduces
MOD
the output duty cycle. For example, if the LTC6992 is used
in a feedback loop, POL = 1 may be required to achieve
negative feedback.
Example:DesignaPWMcircuitthatsatisfiesthefollowing
requirements:
• f
= 20kHz
OUT
Step 2: Selecting the LTC6992 Version
• Positive V
to duty cycle response
MOD
The difference between the LTC6992 versions is observed
at the endpoints of the duty cycle control range. Applica-
tions that require the output never stop oscillating should
use the LTC6992-2. If it is better to allow the output to
• Output can reach 100% duty cycle, but not 0%
• Minimum power consumption
Step 1: Selecting the POL Bit Setting
+
rest at GND or V (0% or 100% duty cycle, respectively),
select the LTC6992-1.
For positive transfer function (duty cycle increases with
V
), choose POL = 0.
MOD
The LTC6992-3 and LTC6992-4 clamp the duty cycle at
only one end of the control range, allowing the output to
stop oscillating at the other extreme. If POL = 1 the clamp
will swap from low duty cycle to high, or vice-versa. Refer
to Table 2 and Figure 4 for assistance in selecting the
proper version.
Step 2: Selecting the LTC6992 Version
To limit the minimum duty cycle, but allow the maximum
duty cycle to reach 100%, choose LTC6992-4. (Note that
if POL = 1 the LTC6992-3 would be the correct choice.)
Step 3: Selecting the N Frequency Divider Value
Step 3: Selecting the N Frequency Divider Value
DIV
DIV
Choose an N
value that meets the requirements of
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
DIV
Equation (1a).
N
value. For a given output frequency, N should be
DIV
DIV
3.125 ≤ N ≤ 50
DIV
selected to be within the following range.
Potential settings for N include 4 and 16. N = 4 is
DIV
DIV
62.5kHz
fOUT
1MHz
fOUT
the best choice, as it minimizes supply current by us-
ing a large R resistor. POL = 0 and N = 4 requires
≤ NDIV
≤
(1a)
SET
DIV
DIVCODE = 1. Using Table 1, choose the R1 and R2 values
to program DIVCODE = 1.
To minimize supply current, choose the lowest N value
DIV
(generallyrecommended).Forfasterstart-upordecreased
jitter,chooseahigherN setting.Alternatively,useTable1
DIV
as a guide to select the best N value for the given ap-
DIV
plication.
69921234p
19
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
Some applications can eliminate ΔV
sensitivity by
Step 4: Select R
SET
SET
making V
proportional to V . For example, Figure 9
MOD
SET
Calculate the correct value for R using Equation (1b).
SET
shows a simple circuit for generating an arbitrary duty
1MHz • 50k
4•20kHz
cycle. The equation for duty cycle does not depend on
RSET
=
= 625k
V
SET
at all.
Since 625k is not available as a standard 1% resistor,
substitute 619k if a 0.97% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
100
90
80
70
60
50
40
30
20
10
0
ΔV
= –30mV
SET
ΔV
= 0mV
SET
The completed design is shown in Figure 7.
ΔV
= 30mV
SET
V
MOD
MOD
GND
SET
OUT
LTC6992-4
2.25V TO 5.5V
+
V
R1
976k
0
0.2
0.4
0.6
(V)
0.8
1
V
MOD
6992 F08
DIVCODE = 1
DIV
R2
102k
6992 F07
Figure 8. Duty Cycle Variation Due to ΔVSET
R
SET
625k
Figure 7. 20kHz PWM Oscillator
MOD
GND
SET
OUT
LTC6992-X
2.25V TO 5.5V
R1
+
V
Duty Cycle Sensitivity to ΔV
SET
The output duty cycle is proportional to the ratio of V
/
MOD
DIV
V
. Since V
can vary up to 30mV from 1V it can
SET
SET
6992 F09
R2
R
R
SET1
SET2
effectively gain or attenuate V
, as shown below when
MOD
RSET2
RSET1 ꢂRSET2
5
4
1
8
Dꢀ
•
ꢁ
ΔV is added to the equation.
SET
VMOD
0.8 • VSET + ΔVSET
1
8
D=
−
(
)
Figure 9. Fixed-Frequency, Arbitrary Duty Cycle Oscillator
The simplifying assumption of ΔV = 0V creates the po-
SET
I
Extremes (Master Oscillator Frequency Extremes)
tential for additional duty cycle error, which increases with
SET
V
MOD
, reaching a maximum of 3.4% if ΔV = –30mV.
SET
PushingI outsideoftherecommended1.25μAto20μA
SET
VMOD ΔVSET
•
ΔVSET
VSET
1
8
rangeforcesthemasteroscillatortooperateoutsideofthe
⎛
⎞
ΔD≅
≅ − D
+
•
⎜
⎟
⎠
ideal
62.5kHz to 1MHz range in which it is most accurate.
⎝
800mV VSET
The oscillator will still function with reduced accuracy
Figure8demonstratestheworst-caseimpactofthisvaria-
for I < 1.25ꢀA. At approximately 500nA, the oscillator
SET
tion (if V is at its 0.97V or 1.03V limits).
SET
output will be frozen in its current state. The output could
halt in a high or low state. This avoids introducing short
pulses while frequency modulating a very low frequency
output.
This error is in addition to the inherent PWM duty cycle
accuracy spec ΔD ( 4.5%), so care should be taken if ac-
curacy at high duty cycles (V
near 0.9V) is critical.
MOD
69921234p
20
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
(TBD • t
) to settle to within 1% of the final value.
MASTER
An example is shown in Figure 11.
Frequency Modulation and Settling Time
Pulse Width Modulation Bandwidth and Settling Time
In addition to pulse-width modulation, the LTC6992 can
be frequency modulated by varying I . The LTC6992
will respond to changes in I
of TBD • f
TheLTC6992willrespondtochangesinV
uptoa–3dB
MOD
SET
bandwidth of TBD (see Figure 10). This makes it easy to
stabilize a feedback loop around the LTC6992, since it
does not introduce a low frequency pole.
up to a –3dB bandwidth
SET
(see Figure 12).
OUT
Following a 2x or 0.5x step change in I , the output
SET
Duty cycle settling time depends on the master oscillator
frequency takes approximately TBD master clock cycles
frequency. Following a 100mV step change in V
, the
(TBD • t
) to settle to within 1% of the final value.
MOD
MASTER
duty cycle takes approximately TBD master clock cycles
An example is shown in Figure 13.
PLACEHOLDER
PLACEHOLDER
Figure 10. PWM Frequency Response
Figure 12. Frequency Modulation Bandwidth
PLACEHOLDER
PLACEHOLDER
Figure 11. PWM Settling Time
Figure 13. Frequency Change Settling Time
69921234p
21
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
Power Supply Current
+
1. Connect the bypass capacitor, C1, directly to the V and
GND pins using a low inductance path. The connection
from C1 to the V pin is easily done directly on the top
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under any
condition using the following equation:
+
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that,C1’sGNDconnectioncanbeaccomplishedthrough
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1μF ceramic capacitor.
If NDIV = 1 (DIVCODE = 0 or 15):
IS(TYP) ≈ V+ • fOUT • 39pF +C
(
)
LOAD
V+
V+
L+
+
+ 2.2•ISET + 85µA
320kΩ 2•RLOAD
If NDIV > 1 (DIVCODE = 1 or 14):
fOUT
IS(TYP) ≈ V+ •
•27pF + V+ • fOUT • 27pF +C
(
)
LOAD
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
NDIV
V+
V+
L+
+
+ 2.6 •ISET + 90µA
3. Place R
as close as possible to the SET pin and
SET
320kΩ 2•RLOAD
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
The LTC6992 is a 2.4% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. The most important use issues involve
adequate supply bypassing and proper PCB layout.
4. Connect R directly to the GND pin. Using a long path
SET
or vias to the ground plane will not have a significant
affect on accuracy, but the direct, short connection is
recommended and easy to apply.
Figure14showsexamplePCBlayoutsforboththeTSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6992. These layouts are
a guide and need not be followed exactly.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
69921234p
22
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
APPLICATIONS INFORMATION
MOD
GND
SET
OUT
LTC6992
+
+
V
V
C1
0.1ꢀF
R1
R2
DIV
R
SET
+
+
V
+
V
C1
R1
C1
V
OUT
GND
MOD
MOD
GND
SET
OUT
+
DIV
SET
V
R2
DIV
R1
R
SET
R
SET
R2
DFN PACKAGE
TSOT-23 PACKAGE
6992 F14
Figure 14. Supply Bypassing and PCB Layout
Constant On-Time Modulator
TYPICAL APPLICATIONS
V
MOD
OUT
C1
MOD
GND
SET
OUT
R
R
M2
M1
V
LTC6992-1
R
*
CC
IN
1.05k
9.31k
11.8k
V
CTRL
V
IN
+
V
R1
182k
DIVCODE = 2
(÷16, POL = 1)
0V TO 2V
R
44.2k
SET
0.1ꢀF
V
SET
DIV
R2
6992 TA02
976k
*OPTIONAL RESISTOR ADJUSTS FOR DESIRED V RANGE.
IN
RSET
50k
RM2
RM1+RM2
IF
ꢀ 0.9 THEN tON = NDIV • 1.125μs •
AS V INCREASES, t
INCREASES AND DUTY CYCLE
OUT
IN
DECREASES (BECAUSE POL = 1) TO MAINTAIN A CONSTANT t
.
ON
FOR CONSTANT OFF-TIME, JUST CHANGE DIVCODE SO POL = 0.
69921234p
23
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Digitally Controlled Duty Cycle with Internal VREF Reference Variation Eliminated
MOD
GND
SET
OUT
+
LTC6992-X
V
+
V
+
C1
0.1ꢀF
V
R1
R2
+
–
DIV
1/2
LTC6078
6992 TA03
R
SET
+
V
V
REF
CC
D
IN
LTC1659
V
OUT
ꢀP
CLK
CS/LD
GND
Programming NDIV Using an 8-Bit DAC
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
DIVCODE DAC CODE
MOD
GND
SET
OUT
0
1
0
24
LTC6992-X
2
40
2.25V TO 5.5V
+
V
3
56
C1
0.1ꢀF
C2
0.1ꢀF
4
72
5
88
6
104
120
136
152
168
184
200
216
232
≥255
DIV
7
8
9
R
SET
V
CC
SDI
10
11
12
13
14
15
V
LTC2630-LZ8 SCK
ꢀP
OUT
CS/LD
GND
6992 TA04
69921234p
24
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Changing Between Two Frequencies
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
ANALOG PWM
DUTY CYCLE CONTROL
(0V TO 1V)
MOD
GND
SET
OUT
MOD
GND
SET
OUT
LTC6992-X
LTC6992-X
+
+
+
+
V
V
V
V
+
V
R1
R2
R1
R2
f
MAX
R
VCO
DIV
DIV
f
MIN
+
R
R
R
SET1
V
SET
SET2
f
MIN
‘HC04
f
MAX
2N7002
‘HC04
6992 TA05
NOTES
NOTES
WHILE THIS CIRCUIT IS SIMPLER THAN THE CIRCUIT TO THE RIGHT,
1. WHEN THE NMOSFET IS OFF, THE FREQUENCY IS SET BY R
= R
SET1
= R
SET1
.
SET
SET
ITS FREQUENCY ACCURACY IS WORSE DUE TO THE EFFECT OF
2. WHEN THE NMOSFET IS ON, THE FREQUENCY IS SET BY R
|| R
.
SET2
+
+
V
SUPPLY VARIATION FROM SYSTEM TO SYSTEM AND OVER TEMPERATURE.
3. V SUPPLY VARIATION IS NOT A FACTOR AS THE SWITCHING RESISTOR IS
EITHER FLOATING OR CONNECTED TO GROUND.
Simple Diode Temperature Sensor
R8
84.5k
5V
R6
5V
R7
16.9k
+10mV/C
5V
45.3k
R9
–
+
365ꢁ
MOC207M
D3
MOD
GND
SET
OUT
D1
1N458
LT6003
Q1
LTC6992-2
+
V
5V
R4
1000k
OUTPUT
C1
1ꢀF
R11
422ꢁ
DIV
R5
186k
6992 TA06
R1
130k
R2
N
= 16
50k
DIV
f = 10kHz
ADJUST FOR 50% DUT CYCLE AT 25°C
R3
130k
PWM OUTPUT FOR ISOLATED MEASUREMENT
+1% DUTY CYCLE CHANGE PER DEGREE C
–10°C TO 65°C RANGE WITH OPTO-ISOLATOR (DC: 15% TO 95%)
69921234p
25
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Motor Speed/Direction Control for Full H-Bridge (Locked Anti-Phase Drive)
V
S
12V
A1
A2
2.6kHz, 5% TO 95% PWM
5% DC = CLOCKWISE
50% DC = STOPPED
CW CURRENT
FLOW
95% DC = COUNTER CLOCKWISE
MOTOR
INPUT 0V TO 1V
MOD
GND
SET
OUT
LTC6992-2
+
+
V
V
R1
1000k
POWER H-BRIDGE
HIGH = SWITCH ON
DIV
R3
300k
R2
280k
6992 TA07
Motor Speed/Direction Control for Full H-Bridge (Sign/Magnitude Drive)
V
S
12V
A4
A5
2.6kHz, 5% TO 95% PWM
5% DC = SLOW
95% DC = FAST
CW CURRENT
FLOW
MOTOR
INPUT 0V TO 1V
MOD
GND
SET
OUT
LTC6992-2
+
+
V
V
R4
POWER H-BRIDGE
HIGH = SWITCH ON
1000k
DIV
R3
300k
R5
280k
A3
DIRECTION
H = CCW, L = CW
6992 TA08
69921234p
26
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Ratiometric Sensor to Pulse Width, Non-Inverting Response
R6
9.09k
V
S
C2
0.22ꢀF
C1
0.15ꢀF
R4
90.9k
R5
10M
2.5V TO 5.5V
K = 1
–
+
R3
OUTPUT
DUTY CYCLE = K • 100%
10k
MOD
OUT
R
SENSOR
LT1490
LTC6992-1
K• V
K = 0
S
+
GND
SET
V
V
S
R1
1000k
DIV
R2
186k
6992 TA09
R
SET
316k
N
OUT
= 16
DIV
= 10kHz
f
Ratiometric Sensor to Pulse Width, Inverting Response
R6
9.09k
C2
0.22ꢀF
R6
90.9k
2.5V TO 5.5V
V
S
C1
0.15ꢀF
V
S
R3
100k
K = 1
R
SENSOR
K = 0
K • V
S
–
+
OUTPUT
R4
10k
MOD
GND
SET
OUT
DUTY CYCLE = (1–K) • 100%
LT1490
LTC6992-1
V
S
+
R5
10k
V
V
S
R1
1000k
DIV
R2
186k
6992 TA10
R
SET
316k
N
OUT
= 16
DIV
= 10kHz
f
69921234p
27
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Ratio Control Servo Pulse Generator
R6
9.09k
C2
0.22ꢀF
C1
1ꢀF
R6
90.9k
2.5V TO 5.5V
V
S
V
S
R5
130k
–
+
OUTPUT
MOD
GND
SET
OUT
1ms TO 2ms PULSE EVERY 16ms
LT1490
LTC6992-1
R6
8.66k
+
V
V
S
R1
2ms
SERVO
CONTROL
POT
1000k
DIV
10k
R2
681k
1ms
6992 TA11
R
SET
316k
N
OUT
= 4096
= 62.5kHz, 16ms PERIOD
DIV
f
Direct Voltage Controlled PWM Dimming 0 to 15000 Cd/m2 Intensity
R3
90.9ꢁ
V
MOD
GND
SET
OUT
DIMMING
LTC6992-1
D1
+
5V
V
HIGH INTENSITY LED
SSL-LX5093XUWC
C1
R1
1M
0.1ꢀF
DIV
R2
280k
6992 TA12
R
SET
105k
f = 7.5kHz
= 64
N
DIV
69921234p
28
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATIONS
Wide Range LED Dimming (0 to 85000 Cd/m2 Brightness)
R2
7.5k
5V
V
FAST
FAST PWM
R1
10k
5V
–
+
CONTROLS 6000 TO 85000
–
2
Cd/m BRIGHTNESS
MOD
OUT
+
LT6004
LT6004
LTC6992-4
+
GND
SET
V
R4
7.5k
R3
5V
3.3V
3.3V
5V
PV
10k
C4
R
DIV1
0.1ꢀF
1M
V
REF
DIV
IN
IN
R
DIV2
+
LED
R
280k
SET1
61.9k
5–100%
= 64
A1
D1
D2
N
DIV
LT3518UF
f = 12.6kHz
PWM
V
DIMMING
0V TO 1.65V
SLOW PWM
CONTROLS 0 TO 6000
2
Cd/m BRIGHTNESS
V
SLOW
LUMILEDS LXHL-BW02
MOD
OUT
LTC6992-1
+
GND
SET
V
5V
C1
R
DIV3
0.1ꢀF
1M
DIV
R
DIV4
R
681k
SET2
0–100%
124k
6992 TA13
N
= 4096
DIV
f
= 100kHz
OUT
69921234p
29
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
PACKAGE DESCRIPTION
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 0.05
1.65 0.05
(2 SIDES)
3.55 0.05
2.15 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
1.35 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
2.00 0.10
(2 SIDES)
0.40 0.10
R = 0.05
TYP
4
6
3.00 0.10 1.65 0.10
(2 SIDES)
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
(DCB6) DFN 0405
3
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
1.35 0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
69921234p
30
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636 Rev B)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
69921234p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
TYPICAL APPLICATION
LED Driver with 5000:1 Dimming Range
L1
6.8ꢀH
D1
V
IN
5V TO 16V
C1
0.22ꢀF
R1
3.92M
SHDN
V
IN
SW
FB
R2
124k
LT3517
ANALOG PWM
DUTY CYCLE
CONTROL
300mA
PWM
TGEN
MOD
GND
SET
OUT
ISP
LTC6992-1
5V
C1
2.2ꢀF
(0V TO 1V)
R
SENSE
V
REF
+
330mΩ
C2
4.7ꢀF
V
CTRL
SYNC
ISN
TG
1M
DIV
V
C
R
T
SS GND
102k
681k
C4
0.1pF
C3
0.1pF
R
6.04k
2MHz
T
6992 TA14
C1: KEMET C0806C225K4RAC
C2: KEMET C1206C475K3RAC
C3, C4: MURATA GRM21BR71H104KA01B
C5: MURATA GRM21BR71H224KA01B
D1: DIODE DFL5160
L1: TOKO B992A5-6RBN
LEDS: LUXEON I (WHITE)
M1: ZETEX ZXMP6A13FTA
RELATED PARTS
PART NUMBER
LTC1799
DESCRIPTION
COMMENTS
Wide Frequency Range
Low Power, Wide Frequency Range
Micropower, I = 35ꢀA at 400kHz
1MHz to 33MHz ThinSOT Silicon Oscillator
1MHz to 20MHz ThinSOT Silicon Oscillator
LTC6900
LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator
SUPPLY
LTC6990
TimerBlox, Voltage Controlled Oscillator
TimerBlox, Very Low Frequency Clock with Reset
TimerBlox, Monostable Pulse Generator
Frequency from 488Hz to 1MHz, No Caps, 2% Accurate
LTC6991
Cycle Time from 2ms to 9.5 Hours, No Caps, 2% Accurate
Resistor Set Pulse Width from 1ꢀs to 2ms, No Caps, 2% Accurate
Resistor Set Pulse Width from 1ꢀs to 2ms, No Caps, 2% Accurate
Resistor Set Delay from 1ꢀs to 2ms, No Caps, 2% Accurate
LTC6993-1
LTC6993-2
LTC6994-1
LTC6994-2
TimerBlox, Retriggerable Monostable Pulse Generator
TimerBlox, Delay Block, First Edge Only Delayed
TimerBlox, Delay Block/Debouncer, Both Edges Delayed
Resistor Set Delay from 1ꢀs to 2ms, No Capacitors Required,
2% Accurate
69921234p
LT 0510 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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