LTM4644EY#PBF [Linear]
暂无描述;型号: | LTM4644EY#PBF |
厂家: | Linear |
描述: | 暂无描述 稳压器 |
文件: | 总36页 (文件大小:815K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM4644/LTM4644-1
Quad DC/DC µModule
Regulator with Configurable 4A Output Array
FEATURES
DESCRIPTION
Quad Output Step-Down µModule® Regulator with 4A
per Output
The LTM®4644/LTM4644-1 is a quad DC/DC step-down
µModule (micromodule) regulator with 4A per output.
Outputs can be paralleled in an array for up to 16A capabil-
ity. Included in the package are the switching controllers,
powerFETs,inductorsandsupportcomponents.Operating
over an input voltage range of 4V to 14V or 2.375V to 14V
with an external bias supply, the LTM4644/LTM4644-1
supports an output voltage range of 0.6V to 5.5V. Its
high efficiency design delivers 4A continuous (5A peak)
output current per channel. Only bulk input and output
capacitors are needed.
n
n
Wide Input Voltage Range: 4V to 14V
n
2.375V to 14V with External Bias
n
n
n
0.6V to 5.5V Output Voltage
4A DC, 5A Peak Output Current Each Channel
Up to 5.5W Power Dissipation (T = 60°C, 200 LFM,
A
No Heat Sink)
n
n
n
n
n
n
n
n
1.5ꢀ Total Output Voltage Regulation
Current Mode Control, Fast Transient Response
Parallelable for Higher Output Current
Output Voltage Tracking
Internal Temperature Sensing Diode Output
External Frequency Synchronization
Overvoltage, Current and Temperature Protection
9mm × 15mm × 5.01mm BGA Package
LTM4644
LTM4644-1
Top Feedback Resistor
from V -to-V
Integrated
60.4k 0.5ꢀ
External (to be added on
PCB)
OUT
FB
(one resistor per channel) Resistor
Application
General
Applications
To Interface with
PMBus power system
management supervisory
ICs such as the LTC2975
APPLICATIONS
n
Multirail Point of Load Regulation
FPGAs, DSPs and ASICs Applications
Configurable Output Array*
n
4A
4A
8A
L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule and PolyPhase are registered
trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
12A
16A
4A
4A
4A
4A
4A
* Note 4
Click to view associated TechClip Videos.
TYPICAL APPLICATION
4V to 14V Input, Quad 0.9V, 1V, 1.2V and 1.5V Output DC/DC µModule Regulator*
1.5V Output Efficiency and
Power Loss (Each Channel)
CLKIN
CLKOUT
95
90
85
80
75
70
65
60
55
2
V
V
4V to 14V
1.5V/4A
IN1
OUT1
FB1
22µF
×2
16V
SVIN1
RUN1
47µF
4V
PGOOD1
40.2k
60.4k
LTM4644
1.5
1
V
IN2
V
1.2V/4A
OUT2
SVIN2
RUN2
FB2
47µF
4V
PGOOD2
V
IN3
V
1V/4A
OUT3
SVIN3
RUN3
FB3
47µF
4V
0.5
0
PGOOD3
90.9k
121k
V
V
= 5V
IN
IN
V
IN4
V
0.9V/4A
= 12V
OUT4
SVIN4
RUN4
FB4
47µF
4V
0
1
2
3
4
PGOOD4
LOAD CURRENT (A)
TEMP SGND GND
4644 TA01b
4644 TA01a
*T = 60°C, 200LFM, NO HEAT SINK
A
4644fd
1
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V , SV (Per Channel).............................. –0.3V to 15V
IN
IN
V
IN1
TRACK/SS1
1
2
3
4
5
6
7
V
(Per Channel) (Note 3) ............–0.3V to SV or 6V
OUT
IN
V
GND
FB1
OUT1
RUN (Per Channel)..................................... –0.3V to 15V
A
B
C
D
E
F
SV
IN1
GND
MODE1
INTV (Per Channel) ............................... –0.3V to 3.6V
CC
COMP1
CLKIN
FB2
RUN1
PGOOD, MODE, TRACK/SS,
PGOOD2 PGOOD1 INTV
CC1
V
V
V
FB (Per Channel)...................................–0.3V to INTV
OUT2
TRACK/SS2
CC
SV
IN2
MODE2
CLKOUT (Note 3), CLKIN.......................–0.3V to INTV
GND
CC
COMP2
SGND
Internal Operating Temperature Range
V
RUN2
IN2
(Notes 2, 5)............................................ –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Body Temperature ................. 245°C
PGOOD3 TEMP INTV
CC2
OUT3
GND
TRACK/SS3
G
H
J
FB3
SV
IN3
MODE3
COMP3
FB4
V
IN3
INTV
RUN3
CC3
PGOOD4 CLKOUT
OUT4
GND
TRACK/SS4
RUN4
K
L
INTV
CC4
COMP4
V
IN4
SV
MODE4
IN4
BGA PACKAGE
77-LEAD (9mm × 15mm × 5.01mm)
T
= 125°C, θ = 17°C/W, θ = 2.75°C/W,
JMAX
JCtop
JCbottom
θ
+ θ = 11°C/W, θ = 10°C/W
JB
BA JA
θ VALUES PER JESD 51-12
WEIGHT = 1.9g
http://www.linear.com/product/LTM4644#orderinfo
ORDER INFORMATION
PART MARKING*
PACKAGE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)
PART NUMBER
LTM4644EY#PBF
LTM4644IY#PBF
LTM4644MPY#PBF
LTM4644IY
PAD OR BALL FINISH
SAC305 (RoHS)
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
DEVICE
FINISH CODE
TYPE
BGA
BGA
BGA
BGA
BGA
BGA
BGA
BGA
LTM4644Y
LTM4644Y
LTM4644Y
LTM4644Y
LTM4644Y
LTM4644Y-1
LTM4644Y-1
LTM4644Y-1
e1
e1
e1
e0
e0
e1
e1
e0
3
3
3
3
3
3
3
3
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTM4644MPY
SnPb (63/37)
LTM4644EY-1#PBF
LTM4644IY-1#PBF
LTM4644IY-1
SAC305 (RoHS)
SAC305 (RoHS)
SnPb (63/37)
Note: The LTM4644-1 does not include the internal top feedback resistor.
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• Package and Tray Drawings:
www.linear.com/packaging
• Terminal Finish Part Markings:
www.linear.com/leadfree
4644fd
2
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, per the typical application.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Switching Regulator Section: per Channel
l
l
V , SV
Input DC Voltage
SV = V
IN
4
14
V
V
IN
IN
IN
V
V
Output Voltage Range
0.6
5.5
OUT(RANGE)
OUT(DC)
Output Voltage, Total Variation
with Line and Load
C
= 22µF, C
= 100µF Ceramic,
IN
OUT
l
MODE = INTV ,V = 4V to 14V, I
= 0A to 4A (Note 4)
1.477
1.1
1.50 1.523
V
CC IN
FB(BOT)
OUT
LTM4644: R
LTM4644-1: R
= 40.2k
= 60.4k, R
= 40.2k
FB(TOP)
FB(BOT)
V
RUN
RUN Pin On Threshold
V
Rising
RUN
1.2
1.3
V
I
Input Supply Bias Current
V
V
= 12V, V
= 12V, V
= 1.5V, MODE = INTV
= 1.5V, MODE = GND
6
2
11
mA
mA
µA
Q(SVIN)
IN
IN
OUT
OUT
CC
Shutdown, RUN = 0, V = 12V
IN
I
I
Input Supply Current
V
V
V
V
= 12V, V
= 12V, V
= 1.5V, I = 4A
OUT
0.62
A
A
S(VIN)
IN
OUT
OUT
Output Continuous Current Range
Line Regulation Accuracy
Load Regulation Accuracy
Output Ripple Voltage
= 1.5V (Note 4)
0
4
0.15
1
OUT(DC)
IN
l
l
ΔV
ΔV
(Line)/V
= 1.5V, V = 4V to 14V, I = 0A
OUT
0.04
0.5
5
ꢀ/V
ꢀ
OUT
OUT
OUT
OUT
OUT
IN
(Load)/V
= 1.5V, I
= 0A to 4A
OUT
OUT
OUT
V
I
V
= 0A, C
= 1.5V
= 100µF Ceramic, V = 12V,
mV
OUT(AC)
OUT
IN
OUT
ΔV
Turn-On Overshoot
Turn-On Time
I
= 0A, C
= 1.5V
= 100µF Ceramic, V = 12V,
30
2.5
160
40
7
mV
ms
mV
µs
OUT(START)
OUT
OUT
OUT
IN
V
t
C
V
= 100µF Ceramic, No Load, TRACK/SS = 0.01µF,
= 1.5V
START
OUT
= 12V, V
IN
OUT
ΔV
OUTLS
Peak Deviation for Dynamic Load Load: 0ꢀ to 50ꢀ to 0ꢀ of Full Load, C
= 47µF
OUT
Ceramic, V = 12V, V
= 1.5V
IN
OUT
t
Settling Time for Dynamic Load
Step
Load: 0ꢀ to 50ꢀ to 0ꢀ of Full Load, C
Ceramic, V = 12V, V = 1.5V
= 47µF
SETTLE
OUT
IN
OUT
I
Output Current Limit
Voltage at FB Pin
V
= 12V, V
= 1.5V
5
A
OUTPK
IN
OUT
V
FB
I
I
= 0A, V
= 0A, V
= 1.5V, 0°C to 125°C
= 1.5V, –40°C to 125°C
0.594
0.592
0.60 0.606
0.60 0.608
V
V
OUT
OUT
OUT
OUT
l
I
FB
Current at FB Pin
(Note 3)
30
nA
R
FBHI
Resistor Between V
and FB
OUT
LTM4644 Only
60.05 60.40 60.75
kΩ
Pins
I
Track Pin Soft-Start Pull-Up
Current
TRACK/SS = 0V
2.5
4
µA
TRACK/SS
V
V
Undervoltage Lockout
V
IN
V
IN
Falling
Hysteresis
2.4
2.6
350
2.8
V
mV
IN(UVLO)
IN
t
t
Minimum On-Time
Minimum Off-Time
PGOOD Trip Level
(Note 3)
(Note 3)
40
70
ns
ns
ON(MIN)
OFF(MIN)
V
V
With Respect to Set Output
Ramping Negative
Ramping Positive
PGOOD
FB
V
V
–13
7
–10
10
–7
13
ꢀ
ꢀ
FB
FB
I
PGOOD Leakage
2
µA
V
PGOOD
V
V
V
PGOOD Voltage Low
I
= 1mA
PGOOD
0.02
3.3
0.5
1
0.1
3.4
PGL
Internal V Voltage
SV = 4V to 14V
3.2
V
INTVCC
INTVCC
OSC
CC
IN
Load Reg INTV Load Regulation
I
= 0mA to 20mA
ꢀ
CC
CC
f
Oscillator Frequency
CLKIN Threshold
MHz
V
CLKIN
0.7
4644fd
3
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
and guaranteed over full –55°C to 125°C internal operating temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
Note 2: The LTM4644E/LTM4644E-1 is tested under pulsed load
conditions such that T ≈ T . The LTM4644E/LTM4644-1 is guaranteed to
Note 3: 100ꢀ tested at wafer level.
J
A
meet performance specifications over the 0°C to 125°C internal operating
temperature range. Specifications over the full –40°C to 125°C internal
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LTM4644I/LTM4644I-1
is guaranteed to meet specifications over the full –40°C to 125°C internal
operating temperature range. The LTM4644MP/LTM4644MP-1 is tested
Note 4: See output current derating curves for different V , V
and T .
A
IN OUT
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
TYPICAL PERFORMANCE CHARACTERISTICS
(Per Channel)
Efficiency vs Load Current from
5VIN (One Channel Operating)
Efficiency vs Load Current from
12VIN (One Channel Operating)
DCM Mode Efficiency from
1.5VOUT
100
95
90
85
80
75
70
95
90
85
80
75
70
65
100
90
80
70
60
50
40
30
20
10
0
5V
OUT
3.3V
2.5V
1.8V
1.5V
1.2V
OUT
OUT
OUT
OUT
OUT
3.3V
2.5V
1.8V
1.5V
1.2V
OUT
OUT
OUT
OUT
OUT
5V
IN
IN
12V
0
3
4
0
3
4
0.001
0.01
0.1
1
10
1
2
1
2
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4644 G01
4644 G02
4644 G03
1.0V Output Transient Response
1.5V Output Transient Response
2.5V Output Transient Response
V
V
V
OUT
OUT
OUT
50mV/DIV
50mV/DIV
50mV/DIV
AC-COUPLED
AC-COUPLED
AC-COUPLED
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
4644 G04
4644 G05
4644 G06
20µs/DIV
= 1V, I = 3A TO 4A, 1A/µs
20µs/DIV
= 1.5V, I
20µs/DIV
= 2.5V, I = 3A TO 4A, 1A/µs
OUT
V
C
= 12V, V
= 10pF
V
C
= 12V, V
= 10pF
= 3A TO 4A, 1A/µs
V
C
= 12V, V
= 10pF
IN
FF
OUT
OUT
IN
FF
OUT
OUT
IN
FF
OUT
OUTPUT CAPACITOR = 1 • 47µF CERAMIC
OUTPUT CAPACITOR = 1 • 47µF CERAMIC
OUTPUT CAPACITOR = 1 • 47µF CERAMIC
4644fd
4
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
TYPICAL PERFORMANCE CHARACTERISTICS
3.3V Output Transient Response
5V Output Transient Response
Start-Up with No Load
V
V
OUT
OUT
I
IN
50mV/DIV
50mV/DIV
0.1A/DIV
AC-COUPLED
AC-COUPLED
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
V
OUT
0.5V/DIV
4644 G07
4644 G08
4644 G09
20µs/DIV
= 3.3V, I
20µs/DIV
5ms/DIV
= 1.5V
V
= 12V, V
= 3A TO 4A, 1A/µs
V
= 12V, V
= 5V, I
= 3A TO 4A, 1A/µs
V
= 12V, V
IN OUT
IN
OUT
OUT
IN
OUT
OUT
OUTPUT CAPACITOR = 47µF CERAMIC
OUTPUT CAPACITOR = 47µF CERAMIC
INPUT CAPACITOR = 150µF SANYO ELECTROLYTIC
CAPACITOR (OPTIONAL) + 22µF CERAMIC CAPACITOR
OUTPUT CAPACITOR = 47µF CERAMIC CAPACITOR
SOFT-START CAPACITOR = 0.1µF
Start-Up with 4A Load
Short-Circuit with No Load
Short-Circuit with 4A Load
I
I
I
IN
0.5A/DIV
IN
IN
0.2A/DIV
0.5A/DIV
V
V
V
OUT
0.5V/DIV
OUT
OUT
0.5V/DIV
0.5V/DIV
4644 G10
4644 G11
4644 G12
5ms/DIV
20µs/DIV
20µs/DIV
V
= 12V, V
= 1.5V
V
= 12V, V
= 1.5V
V
= 12V, V
= 1.5V
IN
OUT
IN
OUT
IN
OUT
INPUT CAPACITOR = 150µF SANYO ELECTROLYTIC
CAPACITOR (OPTIONAL) + 22µF CERAMIC CAPACITOR
OUTPUT CAPACITOR = 47µF CERAMIC CAPACITOR
SOFT-START CAPACITOR = 0.1µF
INPUT CAPACITOR = 150µF SANYO ELECTROLYTIC
CAPACITOR (OPTIONAL) + 22µF CERAMIC CAPACITOR
OUTPUT CAPACITOR = 47µF CERAMIC CAPACITOR
INPUT CAPACITOR = 150µF SANYO ELECTROLYTIC
CAPACITOR (OPTIONAL) + 22µF CERAMIC CAPACITOR
OUTPUT CAPACITOR = 47µF CERAMIC CAPACITOR
Recovery to No Load from
Short-Circuit
Output Ripple
Start Into Pre-Biased Output
V
IN
2V/DIV
V
V
OUT
1V/DIV
OUT
200mV/DIV
5mV/DIV
AC-COUPLED
I
OUT
20A/DIV
4644 G14
4644 G15
4644 G13
V
V
= 12V
500µs/DIV
V
V
= 12V
= 5V
1µs/DIV
V
V
= 12V
= 1V
5µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.5V
INPUT CAPACITOR = 22µF SANYO ELECTROLYTIC
CAPACITOR (OPTIONAL) + 2× 22µF CERAMIC CAP.
OUTPUT CAPACITOR = 2× 47µF CERAMIC CAP.
SOFT-START CAPACITOR = 0.1µF
INPUT CAPACITOR = 22µF SANYO ELECTROLYTIC
CAPACITOR (OPTIONAL) + 2× 22µF CERAMIC CAP.
OUTPUT CAPACITOR = 2× 47µF CERAMIC CAP.
SOFT-START CAPACITOR = 0.1µF
INPUT CAPACITOR = 22µF SANYO ELECTROLYTIC
CAPACITOR (OPTIONAL) + 2× 22µF CERAMIC CAP.
OUTPUT CAPACITOR = 2× 47µF CERAMIC CAP.
SOFT-START CAPACITOR = 0.1µF
20MHz MEASUREMENT BANDWIDTH
4644fd
5
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
SV , SV , SV , SV (B5, E5, H5, L5): Signal V .
IN1
IN2
IN
IN4
IN
Filtered input voltage to the internal 3.3V regulator for
the control circuitry of each Switching mode Regulator
Channel. Tie this pin to the V pin respectively in most
V
(A1, A2, A3), V
(C1, D1, D2), V
(F1,
IN
OUT1
G1, G2), V
OUT2
OUT3
applications. Connect SV to an external voltage supply
(J1, K1, K2): Power Output Pins of Each
IN
OUT4
of at least 4V which must also be greater than V
.
Switching Mode Regulator Channel. Apply output load
between these pins and GND pins. Recommend placing
outputdecouplingcapacitancedirectlybetweenthesepins
and GND pins. See the Applications Information section
for paralleling outputs.
OUT
TRACK/SS1, TRACK/SS2, TRACK/SS3, TRACK/SS4 (A6,
D6, G6, K6): Output Tracking and Soft-Start Pin of Each
Switching Mode Regulator Channel. Allows the user to
control the rise time of the output voltage. Putting a volt-
age below 0.6V on this pin bypasses the internal reference
input to the error amplifier, instead it servos the FB pin
to match the TRACK voltage. Above 0.6V, the tracking
function stops and the internal reference resumes control
of the error amplifier. There’s an internal 2.5µA pull-up
GND (A4-A5, B1-B2, C5, D3-D5, E1-E2, F5, G3-G5,
H1-H2, J5, K3-K4, L1-L2): Power Ground Pins for Both
Input and Output Returns. Use large PCB copper areas to
connect all GND together.
V
IN1
(B3, B4), V (E3, E4), V (H3, H4), V (L3, L4):
IN2 IN3 IN4
current from INTV on this pin, so putting a capacitor
CC
Power input pins connect to the drain of the internal top
MOSFET for each switching mode regulator channel.
Apply input voltages between these pins and GND pins.
Recommendplacinginputdecouplingcapacitancedirectly
here provides soft-start function.
MODE1, MODE2, MODE3, MODE4 (B6, E6, H6, L6):
Operation Mode Select for Each Switching Mode Regula-
tor Channel. Tie this pin to INTV to force continuous
between each of V pins and GND pins.
CC
IN
synchronous operation at all output loads. Tying it to
SGND enables discontinuous current mode operation at
light loads. Do not leave floating.
PGOOD1, PGOOD2, PGOOD3, PGOOD4 (C3, C2, F2,
J2): Output Power Good with Open-Drain Logic of Each
Switching Mode Regulator Channel. PGOOD is pulled to
ground when the voltage on the FB pin is not within 10ꢀ
of the internal 0.6V reference.
RUN1, RUN2, RUN3, RUN4(C6, F6, J6, K7):RunControl
Input of Each Switching Mode Regulator Channel. Enable
regulator operation by tying the specific RUN pin above
1.2V. Pulling it below 1.1V shuts down the respective
regulator channel. Do not leave floating.
CLKOUT (J3): Output Clock Signal for PolyPhase® Opera-
tion of the Module. The phase of CLKOUT with respect to
CLKIN is set to 180°. CLKOUT’s peak-to-peak amplitude
FB1, FB2, FB3, FB4 (A7, D7, G7, J7): The Negative Input
of the Error Amplifier for Each Switching Mode Regulator
Channel. Internally, in LTM4644, this pin is connected to
is INTV to GND. See the Application Information section
CC
for details. Strictly output; do not drive this pin.
INTV , INTV , INTV , INTV (C4, F4, J4, K5):
CC4
CC1
CC2
CC3
V
OUT
of each channel with a 60.4kΩ precision resistor.
Internal 3.3V Regulator Output of Each Switching Mode
Regulator Channel. The internal power drivers and con-
trol circuits are powered from this voltage. Each pin is
internally decoupled to GND with 1µF low ESR ceramic
capacitor already.
Different output voltages can be programmed with an
additional resistor between the FB and GND pins for the
LTM4644, and two resistors between the V , FB and
OUT
GNDpinsfortheLTM4644-1.InPolyPhaseoperation,tying
the FB pins together allows for parallel operation. See the
Applications Information section for details.
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LTM4644/LTM4644-1
PIN FUNCTIONS
COMP1, COMP2, COMP3, COMP4 (B7, E7, H7, L7): Cur-
rent Control Threshold and Error Amplifier Compensation
Point of Each Switching Mode Regulator Channel. The
internal current comparator threshold is proportional to
thisvoltage. Tie theCOMPpinstogetherforparallelopera-
tion. The device is internally compensated.
SGND(F7):SignalGroundConnection.SGNDisconnected
to GND internally through single point. Use a separated
SGND ground copper area for the ground of the feedback
resistor and other components connected to signal pins.
A second connection between the PGND plane and SGND
plane is recommended on the backside of the PCB under-
neath the module.
CLKIN (C7): External Synchronization Input to Phase
Detector of the Module. This pin is internally terminated
to SGND with 20kΩ. The phase-locked loop will force
the channel 1 turn-on signal to be synchronized with the
rising edge of the CLKIN signal. Channel 2, channel 3 and
channel 4 will also be synchronized with the rising edge of
the CLKIN signal with a pre-determined phase shift. See
the Applications Information section for details.
TEMP (F3): Onboard Temperature Diode for Monitoring
the VBE Junction Voltage Change with Temperature. See
the Applications Information section.
4644fd
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LTM4644/LTM4644-1
BLOCK DIAGRAM
CLKIN
V
OUT1
100k
100k
100k
100k
PGOOD1
INTV
CC1
60.4k
(*LTM4644 ONLY)
SV
V
IN1
IN1
FB1
V
INTV
CC1
IN
60.4k
4V TO 14V
0.22µF
1µF
10µF
47µF
1µF
1µH
MODE1
V
1.2V
4A
OUT1
V
OUT1
GND
POWER CONTROL
CLKOUT
TRACK/SS1
RUN1
0.1µF
COMP1
INTERNAL
COMP
SGND
GND
INTERNAL
FILTER
FREQ1
162k
V
OUT2
PGOOD2
INTV
CC2
60.4k
SV
V
IN2
IN2
(*LTM4644 ONLY)
1µF
FB2
INTV
CC2
V
IN
40.2k
0.22µF
1µF
10µF
47µF
CLKIN
1µH
MODE2
TRACK/SS2
RUN2
V
1.5V
4A
OUT2
V
OUT2
GND
POWER CONTROL
0.1µF
COMP2
CLKOUT
INTERNAL
COMP
INTERNAL
FILTER
FREQ2
162k
V
OUT3
PGOOD3
INTV
CC3
60.4k
SV
V
IN3
IN3
(*LTM4644 ONLY)
1µF
FB3
INTV
CC3
V
IN
30.1k
0.22µF
1µF
10µF
47µF
CLKIN
1µH
MODE3
TRACK/SS3
RUN3
V
1.8V
4A
OUT3
V
OUT3
GND
POWER CONTROL
0.1µF
COMP3
CLKOUT
INTERNAL
COMP
INTERNAL
FILTER
FREQ3
162k
V
OUT4
PGOOD4
INTV
CC4
60.4k
SV
V
IN4
IN4
(*LTM4644 ONLY)
1µF
FB4
INTV
CC4
V
IN
90.9k
0.22µF
1µF
10µF
47µF
CLKIN
1µH
MODE4
V
1V
4A
OUT4
V
OUT4
GND
POWER CONTROL
TRACK/SS4
RUN4
0.1µF
COMP4
CLKOUT
INTERNAL
COMP
INTERNAL
FILTER
TEMP
FREQ4
162k
CLKOUT
4644 BD
*LTM4644-1 DOES NOT INCLUDE 60.4k RESISTOR
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LTM4644/LTM4644-1
DECOUPLING REQUIREMENTS (per Channel)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
External Input Capacitor Requirement
I
= 4A
= 4A
4.7
10
µF
IN
OUT
(V = 4V to 14V, V
= 1.5V)
IN
OUT
C
External Output Capacitor Requirement
(V = 4V to 14V, V = 1.5V)
I
22
47
µF
OUT
OUT
IN
OUT
OPERATION
The LTM4644 is a quad output standalone non-isolated
switch mode DC/DC power supply. It has four separate
regulatorchannelswitheachofthemcapableofdelivering
upto4Acontinuousoutputcurrentwithfewexternalinput
and output capacitors. Each regulator provides precisely
regulatedoutputvoltageprogrammablefrom0.6Vto5.5V
viaasingleexternalresistor(tworesistorsforLTM4644-1)
over 4V to 14V input voltage range. With an external bias
voltage, this module can operate from an input voltage
as low as 2.375V. The typical application schematic is
shown in Figure 33.
employ a 2+2, 3+1 or 4 channels parallel operation which
is more than flexible in a multirail POL application like
FPGA. Furthermore, the LTM4644 has CLKIN and CLK-
OUT pins for frequency synchronization or polyphasing
multiple devices which allow up to 8 phases cascaded to
run simultaneously.
Current mode control also provides cycle-by-cycle fast
current monitoring. Foldback current limiting is provided
in an overcurrent condition to reduce the inductor valley
current to approximately 40ꢀ of the original value when
V
FB
drops. An internal overvoltage and undervoltage
TheLTM4644integratesfourseparateconstantfrequency
controlled on-time valley current mode regulators, power
MOSFETs, inductors, and other supporting discrete com-
ponents. The typical switching frequency is set to 1MHz.
For switching noise-sensitive applications, the µModule
regulator can be externally synchronized to a clock from
700kHz to 1.3MHz. See the Applications Information
section.
comparators pull the open-drain PGOOD output low if
the output feedback voltage exits a 10ꢀ window around
the regulation point. Continuous conduction mode (CCM)
operation is forced during OV and UV conditions except
duringstart-upwhentheTRACKpinisrampingupto0.6V.
Pulling the RUN pin below 1.1V forces the controller into
its shutdown state, turning off both power MOSFETs and
most of the internal control circuitry. At light load cur-
rents, discontinuous conduction mode (DCM) operation
can be enabled to achieve higher efficiency compared to
continuous conduction mode (CCM) by setting the MODE
pin to SGND. The TRACK/SS pin is used for power supply
trackingandsoft-startprogramming.SeetheApplications
Information section.
With current mode control and internal feedback loop
compensation, the LTM4644 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
Current mode control provides the flexibility of paralleling
any of the separate regulator channels with accurate cur-
rent sharing. With a built-in clock interleaving between
each two regulator channels, the LTM4644 could easily
Atemperaturediodeisincludedinsidethemoduletomoni-
tor the temperature of the module. See the Applications
Information section for details.
4644fd
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LTM4644/LTM4644-1
APPLICATIONS INFORMATION
The typical LTM4644 application circuit is shown in
Figure 33. External component selection is primarily
determined by the input voltage, the output voltage and
the maximum load current. Refer to Table 7 for specific
externalcapacitorrequirementsforaparticularapplication.
For parallel operation of N channels, use the following
equation can be used to solve for R . Tie the V
FB(BOT)
OUT
and the FB and COMP pins together for each paralleled
output with a single resistor to GND as determined by:
⎛
⎜
⎝
⎞
⎟
⎠
60.4k
N
V to V
Step-Down Ratios
IN
OUT
RFB(BOT)
=
⎛
⎜
⎝
⎞
VOUT
0.6
−1
⎟
There are restrictions in the maximum V and V
step-
IN
OUT
⎠
down ratio that can be achieved for a given input voltage
due to the minimum off-time and minimum on-time limits
of each regulator. The minimum off-time limit imposes a
maximum duty cycle which can be calculated as:
OUTPUT VOLTAGE PROGRAMMING (LTM4644-1)
ThePWM controllerhasaninternal0.6Vreferencevoltage.
Adding two resistors R
FB(BOT)
from V
to FB pin and
FB(TOP)
OUT
D
MAX
= 1 – t
• f
R
from FB pin to GND programs the output voltage:
OFF(MIN) SW
where t
is the minimum off-time, 70ns typical for
SW
OFF(MIN)
RFB(TOP)
RFB(BOT)
=
LTM4644, and f is the switching frequency. Conversely
VOUT
0.6
theminimumon-timelimitimposesaminimumdutycycle
of the converter which can be calculated as:
–1
For parallel operation of N Channels, only one set of
and R is needed while tying the V , FB
D
= t
• f
MIN
ON(MIN) SW
R
FB(TOP)
FB(BOT)
OUT
where t
is the minimum on-time, 40ns typical for
and COMP pins from different channels together. See
ON(MIN)
LTM4644. In the rare cases where the minimum duty
cycle is surpassed, the output voltage will still remain
in regulation, but the switching frequency will decrease
from its programmed value. Note that additional thermal
derating may be applied. See the Thermal Considerations
and Output Current Derating section in this data sheet.
Figure 1 for example.
V
OUT1
R
R
FB(TOP)
FB1
LTM4644-1
FB(BOT)
COMP1
V
OUT2
FB2
Output Voltage Programming (LTM4644)
COMP2
V
OUT3
FB3
ThePWM controllerhasaninternal0.6Vreferencevoltage.
As shown in the Block Diagram, a 60.4k internal feedback
COMP3
resistor connects each regulator channel from V
pin
4644 F01
OUT
to FB pin. Adding a resistor R
programs the output voltage:
from FB pin to GND
FB(BOT)
Figure 1. LTM4644-1 Feedback Resistor
for Paralleling Application
60.4k
LTM4644
LTM4644-1
RFB(BOT)
=
VOUT
Top Feedback Resistor
from V -to-V
Integrated
60.4k 0.5ꢀ
(one resistor per channel) Resistor
External (to be added on
PCB)
−1
0.6
OUT
FB
Application
General
Applications
To Interface with
Table 1. VFB Resistor Table vs Various Output Voltages
(V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3
(k) Open 90.9 60.4 40.2 30.1 19.1 13.3 8.25
PMBus power system
management supervisory
ICs such as the LTC2975
V
5.0
OUT
R
FB(BOT)
4644fd
10
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LTM4644/LTM4644-1
APPLICATIONS INFORMATION
Input Decoupling Capacitors
comparator may remain tripped for several cycles and
force the top MOSFET to stay off for several cycles, thus
skipping cycles. The inductor current does not reverse
in this mode.
The LTM4644 module should be connected to a low ac-
impedance DC source. For each regulator channel, a 10µF
input ceramic capacitor is recommended for RMS ripple
current decoupling. A bulk input capacitor is only needed
whentheinputsourceimpedanceiscompromisedbylong
inductive leads, traces or not enough source capacitance.
Thebulkcapacitorcanbeanelectrolyticaluminumcapaci-
tor or polymer capacitor.
Force Continuous Conduction Mode (CCM)
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous conduction
modeoperationshouldbeused.Forcedcontinuousopera-
Without considering the inductor ripple current, the RMS
current of the input capacitor can be estimated as:
tion can be enabled by tying the MODE pin to INTV . In
CC
this mode, inductor current is allowed to reverse during
low output loads, the COMP voltage is in control of the
current comparator threshold throughout, and the top
MOSFETalwaysturnsonwitheachoscillatorpulse.During
start-up, forcedcontinuousmodeisdisabledandinductor
current is prevented from reversing until the LTM4644’s
output voltage is in regulation.
IOUT(MAX)
ICIN(RMS)
=
• D•(1−D)
η%
whereηꢀistheestimatedefficiencyofthepowermodule.
Output Decoupling Capacitors
Withanoptimizedhighfrequency,highbandwidthdesign,
only single piece of low ESR output ceramic capacitor is
required for each regulator channel to achieve low output
voltagerippleandverygoodtransientresponse.Additional
output filtering may be required by the system designer,
if further reduction of output ripples or dynamic transient
spikes is required. Table 7 shows a matrix of different
output voltages and output capacitors to minimize the
voltage droop and overshoot during a 2A load step tran-
sient. Multiphase operation will reduce effective output
ripple as a function of the number of phases. Application
Note77discussesthisnoisereductionversusoutputripple
current cancellation, but the output capacitance will be
more a function of stability and transient response. The
LTpowerCAD™DesignToolisavailabletodownloadonline
for output ripple, stability and transient response analysis
and calculating the output ripple reduction as the number
of phases implemented increases by N times.
Operating Frequency
The operating frequency of the LTM4644 is optimized to
achievethecompactpackagesizeandtheminimumoutput
ripplevoltagewhilestillkeepinghighefficiency.Thedefault
operating frequency is internally set to 1MHz. In most ap-
plications, no additional frequency adjusting is required.
If any operating frequency other than 1MHz is required
by application, the µModule regulator can be externally
synchronized to a clock from 700kHz to 1.3MHz.
Frequency Synchronization and Clock In
The power module has a phase-locked loop comprised
of an internal voltage controlled oscillator and a phase
detector. This allows all internal top MOSFET turn-on to
be locked to the rising edge of the same external clock.
The external clock frequency range must be within 30ꢀ
around the 1MHz set frequency. A pulse detection circuit
is used to detect a clock on the CLKIN pin to turn on the
phase-locked loop. The pulse width of the clock has to
be at least 400ns. The clock high level must be above 2V
and clock low level below 0.3V. During the start-up of
the regulator, the phase-locked loop function is disabled.
Discontinuous Conduction Mode (DCM)
Inapplicationswherelowoutputrippleandhighefficiency
at intermediate current are desired, discontinuous con-
duction mode (DCM) should be used by connecting the
MODE pin to SGND. At light loads the internal current
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LTM4644/LTM4644-1
APPLICATIONS INFORMATION
Multichannel Parallel Operation
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is reduced by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
thanthenumberofphasesusedtimestheoutputvoltage).
Theoutputrippleamplitudeisalsoreducedbythenumber
of phases used when all of the outputs are tied together
to achieve a single high output current design.
For loads that demand more than 4A of output current,
the LTM4644 multiple regulator channels can be easily
paralleled to provide more output current without increas-
ing input and output voltage ripples. The LTM4644 has
preset built-in phase shift between each two of the four
regulator channels which is suitable to employ a 2+2, 3+1
or 4 channels parallel operation. Table 2 gives the phase
difference between regulator channels.
The LTM4644 device is an inherently current mode con-
trolled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. Please tie the RUN, TRACK/SS, FB and COMP
pins of each paralleling channel together. Figure 35 and
Figure 36 shows an example of parallel operation and pin
connection.
Table 2. Phase Difference Between Regulator Channels
CHANNEL
CH1
CH2
CH3
CH4
Phase Difference
180°
90°
180°
Figure 2 shows a 2+2 and a 4-channels parallel concept
schematic for clock phasing.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reductionasafunctionofthenumberofinterleavedphases.
Figure 3 shows this graph.
180°
180°
CH1
(0°)
CH2
(180°)
CH3
(0°)
CH4
(180°)
V
OUT1
V
OUT2
V
OUT3
V
OUT4
Soft-Start and Output Voltage Tracking
LTM4644
The TRACK/SS pin provides a means to either soft-start
of each regulator channel or track it to a different power
supply. A capacitor on the TRACK/SS pin will program the
ramp rate of the output voltage. An internal 2.5µA current
source will charge up the external soft-start capacitor
8A
8A
towards the INTV voltage. When the TRACK/SS voltage
CC
is below 0.6V, it will take over the internal 0.6V reference
voltage to control the output voltage. The total soft-start
time can be calculated as:
180°
90°
180°
CH1
(0°)
CH2
(180°)
CH3
(270°)
CH4
(90°)
CSS
t
SS = 0.6 •
2.5µA
V
OUT1
V
OUT2
V
OUT3
V
OUT4
where C is the capacitance on the TRACK/SS pin. Cur-
rent foldback and forced continuous mode are disabled
during the soft-start process.
SS
LTM4644
16A
4644 F02
Figure 2. 2+2 and 4 Channels Parallel Concept Schematic
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APPLICATIONS INFORMATION
0.60
1-PHASE
2-PHASE
4-PHASE
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
OUT IN
4644 F03
Figure 3. Normalized RMS Ripple Current for Single Phase or Polyphase Applications
Outputvoltagetrackingcanalsobeprogrammedexternally
Where the 60.4k is the integrated top feedback resistor
and the R is the external bottom feedback resistor
TR(TOP) TR(BOT)
divider on the TRACK/SS pin of the slave regulator, as
shown in Figure 5.
using the TRACK/SS pin of each regulator channel. The
output can be tracked up and down with another regula-
tor. Figure 4 and Figure 5 show an example waveform
and schematic of a ratiometric tracking where the slave
FB(SL)
of the LTM4644. The R
/R
is the resistor
regulator’s (V
, V
and V
) output slew rate is
OUT2 OUT3
proportional to the master’s (V
OUT4
Following the upper equation, the master’s output slew
rate (MR) and the slave’s output slew rate (SR) in volts/
time is determined by:
).
OUT1
Since the slave regulator’s TRACK/SS is connected to
the master’s output through a R /R resistor
TR(TOP) TR(BOT)
RFB(SL)
divider and its voltage used to regulate the slave output
voltage when TRACK/SS voltage is below 0.6V, the slave
outputvoltageandthemasteroutputvoltageshouldsatisfy
the following equation during the start-up.
R
FB(SL) +60.4k
RTR(BOT)
MR
SR
=
R
TR(TOP) +RTR(BOT)
RFB(SL)
VOUT(SL)
•
R
FB(SL) +60.4k
RTR(BOT)
= VOUT(MA)
•
R
TR(TOP) +RTR(BOT)
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APPLICATIONS INFORMATION
The TRACK pins will have the 2.5µA current source on
when a resistive divider is used to implement tracking on
that specific channel. This will impose an offset on the
TRACK pin input. Smaller value resistors with the same
ratios as the resistor values calculated from the above
equation can be used. For example, where the 60.4k is
used then a 6.04k can be used to reduce the TRACK pin
offset to a negligible value.
V
V
V
V
= 3.3V
= 2.5V
= 1.8V
= 1.2V
OUT1
OUT2
OUT3
OUT4
The coincident output tracking can be recognized as a
special ratiometric output tracking which the master’s
output slew rate (MR) is the same as the slave’s output
slew rate (SR), as waveform shown in Figure 6.
4644 F04
TIME
Figure 4. Output Ratiometric Tracking Waveform
From the equation we could easily find out that, in the
coincident tracking, the slave regulator’s TRACK/SS pin
resistor divider is always the same as its output voltage
divider.
Forexample,V
=3.3V,MR=3.3V/24msandV
OUT(SL)
OUT(MA)
= 1.2V, SR = 1.2V/24ms as V
and V
shown in
OUT1
OUT4
Figure 5. From the equation, we could solve out that
R
= 60.4k and R
= 13.3k is a good com-
TR4(TOP)
TR4(BOT)
RFB(SL)
RTR(BOT)
bination. Follow the same equation, we can get the same
=
R
/R
resistor divider value for V
and
TR(TOP) TR(BOT)
OUT2
R
FB(SL) +60.4k
R
TR(TOP) +RTR(BOT)
V
.
OUT3
V
IN
4V TO 14V
CH1
CH2
CH3
CH4
60.4k
60.4k
60.4k
60.4k
4644 F05
C
SS
R
R
R
FB(SL)4
60.4k
FB(SL)2
FB(SL)3
0.1µF
19.1k
30.1k
R
FB1
13.3k
R
R
TR(TOP)2
60.4k
TR(BOT)2
13.3k
R
R
R
TR(BOT)3
13.3k
TR(TOP)3
60.4k
R
TR(TOP)4
60.4k
TR(BOT)4
13.3k
Figure 5. Output Ratiometric Tracking Schematic
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APPLICATIONS INFORMATION
For example, R
= 60.4k and R
= 60.4k is
reference only, while still keeping the power MOSFETs
off. Further increasing the RUN pin voltage above 1.2V
will turn on the entire regulator channel.
TR4(TOP)
TR4(BOT)
a good combination for coincident tracking for V
OUT(MA)
= 3.3V and V
= 1.2V application.
OUT(SL)
Pre-Biased Output Start-Up
V
V
V
V
= 3.3V
= 2.5V
= 1.8V
= 1.2V
OUT1
OUT2
OUT3
OUT4
There may be situations that require the power supply to
start up with some charge on the output capacitors. The
LTM4644 can safely power up into a pre-biased output
without discharging it.
TheLTM4644accomplishesthisbyforcingdiscontinuous
mode (DCM) operation until the TRACK/SS pin voltage
reaches 0.6V reference voltage. This will prevent the BG
from turning on during the pre-biased output start-up
which would discharge the output.
4644 F06
TIME
Figure 6. Output Coincident Tracking Waveform
Do not pre-bias LTM4644 with an output voltage higher
than INTV (3.3V).
CC
Power Good
Overtemperature Protection
The PGOOD pins are open drain pins that can be used
to monitor each valid output voltage regulation. This pin
monitors a 10ꢀ window around the regulation point. A
resistor can be pulled up to a particular supply voltage for
monitoring. To prevent unwanted PGOOD glitches dur-
Theinternalovertemperatureprotectionmonitorsthejunc-
tiontemperatureofthemodule.Ifthejunctiontemperature
reachesapproximately160°C,bothpowerswitcheswillbe
turned off until the temperature drops about 15°C cooler.
ing transients or dynamic V
changes, the LTM4644’s
OUT
Low Input Application
PGOOD falling edge includes a blanking delay of approxi-
mately 52 switching cycles.
The LTM4644 module has a separate SV pin for each
IN
regulator channel which makes it compatible with opera-
Stability Compensation
tion from an input voltage as low as 2.375V. The SV pin
IN
The LTM4644 module internal compensation loop of each
regulator channel is designed and optimized for low ESR
ceramic output capacitors only application. Table 6 is
provided for most application requirements. In case of
bulk output capacitors is required for output ripples or
dynamic transient spike reduction, an additional 10pF to
is the signal input of the regulator control circuitry while
the V pin is the power input which directly connected
IN
to the drain of the top MOSFET. In most application with
input voltage ranges from 4V to 14V, connect the SV
IN
pin directly to the V pin of each regulator channel. An
IN
optional filter, consisting of a resistor (1Ω to 10Ω) be-
tween SV and V ground, can be placed for additional
15pF phase boost capacitor is required between the V
OUT
IN
IN
and FB pins. The LTpowerCAD Design Tool is available to
noise immunity. This filter is not necessary in most cases
if good PCB layout practices are followed (see Figure 32).
In a low input voltage (2.375V to 4V) application, or to
reducepowerdissipationbytheinternalbiasLDO,connect
download for control loop optimization.
RUN Enable
SV to an external voltage higher than 4V with a 0.1µF
IN
Pulling the RUN pin of each regulator channel to ground
forcestheregulatorintoitsshutdownstate,turningoffboth
power MOSFETs and most of its internal control circuitry.
Bringing the RUN pin above 0.7V turns on the internal
local bypass capacitor. Figure 34 shows an example of a
low input voltage application. Please note, SV voltage
IN
cannot go below V
voltage.
OUT
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APPLICATIONS INFORMATION
Temperature Monitoring
Solving for T, T = –(V – V )/(dV /dT) provides the
G0 D D
temperature.
A diode connected PNP transistor is used for the TEMP
monitor function by monitoring its voltage over tempera-
ture. The temperature dependence of this diode voltage
can be understood in the equation:
1st Example: Figure 7 for 27°C, or 300K the diode
voltage is 0.598V, thus, 300K = –(1200mV – 598mV)/
–2.0 mV/K)
⎛ ⎞
ID
2nd Example: Figure 7 for 75°C, or 350K the diode
voltage is 0.50V, thus, 350K = –(1200mV – 500mV)/
–2.0mV/K)
V =nV ln
⎜ ⎟
D
T
I
⎝ ⎠
S
where V is the thermal voltage (kT/q), and n, the ideality
Converting the Kelvin scale to Celsius is simply taking the
Kelvin temp and subtracting 273 from it.
T
factor, is 1 for the diode connected PNP transistor be-
ing used in the LTM4644. I is expressed by the typical
S
A typical forward voltage is given in the electrical charac-
teristics section of the data sheet, and Figure 7 is the plot
of this forward voltage. Measure this forward voltage at
27°C to establish a reference point. Then using the above
expression while measuring the forward voltage over
temperature will provide a general temperature monitor.
empirical equation:
⎛
⎜
⎝
⎞
⎟
⎠
–VG0
VT
I =I exp
0
S
where I is a process and geometry dependent current, (I
0
0
Connect a resistor between TEMP and V to set the cur-
IN
is typically around 20k orders of magnitude larger than I
S
rent to 100µA. See Figure 35 for an example.
at room temperature) and V is the band gap voltage of
G0
1.2V extrapolated to absolute zero or –273°C.
0.8
I
= 100µA
D
If we take the I equation and substitute into the V equa-
S
D
0.7
0.6
0.5
0.4
0.3
tion, then we get:
⎛ ⎞
⎛
⎞
kT
q
I0
kT
q
V = V –
ln
, V =
⎜ ⎟
⎜
⎟
D
T
G0
I
⎝
⎠
⎝ ⎠
D
The expression shows that the diode voltage decreases
(linearly if I were constant) with increasing temperature
0
and constant diode current. Figure 6 shows a plot of V
D
–50 –25
0
25
50
75 100 125
vs Temperature over the operating temperature range of
TEMPERATURE (°C)
4637 F07
the LTM4644.
Figure 7. Diode Voltage VD vs Temperature T(°C)
If we take this equation and differentiate it with respect to
temperature T, then:
Thermal Considerations and Output Current Derating
dV
D = –
dT
VG0 – VD
T
The thermal resistances reported in the Pin Configura-
tion section of the data sheet are consistent with those
parameters defined by JESD 51-12 and are intended for
use with finite element analysis (FEA) software modeling
tools that leverage the outcome of thermal modeling,
simulation, and correlation to hardware evaluation per-
formed on a µModule package mounted to a hardware
test board: defined by JESD 51-9 (“Test Boards for Area
This dV /dT term is the temperature coefficient equal to
about –2mV/K or –2mV/°C. The equation is simplified for
the first order derivation.
D
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is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
Array Surface Mount Package Thermal Measurements”).
The motivation for providing these thermal coefficients in
foundinJESD51-12(“GuidelinesforReportingandUsing
Electronic Package Thermal Information”).
As in the case of θ
, this value may be useful
JCbottom
for comparing packages but the test conditions don’t
generally match the user’s application.
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to predict the
µModule regulator’s thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in this data sheet can be used
in a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
4. θ , the thermal resistance from junction to the printed
JB
circuitboard,isthejunction-to-boardthermalresistance
wherealmostalloftheheatflowsthroughthebottomof
the µModule regulator and into the board, and is really
the sum of the θ
and the thermal resistance of
JCbottom
the bottom of the part through the solder joints and
through a portion of the board. The board temperature
is measured a specified distance from the package.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 8; blue resistances are
contained within the μModule regulator, whereas green
resistances are external to the µModule package.
The Pin Configuration section typically gives four thermal
coefficients explicitly defined in JESD 51-12; these coef-
ficients are quoted or paraphrased below:
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operatingconditionsofaμModuleregulator. Forexample,
in normal board-mounted applications, never does 100ꢀ
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
1. θ , the thermal resistance from junction to ambient, is
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move.Thisvalueisdeterminedwiththepartmountedto
a JESD 51-9 defined test board, which does not reflect
an actual application or viable operating condition.
for θ
and θ , respectively. In practice, power
JCbottom
JCtop
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
2. θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the page. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditionsdon’tgenerallymatchtheuser’sapplication.
Within the LTM4644, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
valuessuppliedinthisdatasheet:(1)Initially,FEAsoftware
3. θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetopof
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
4644fd
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is used to accurately build the mechanical geometry of
the LTM4644 and the specified PCB with all of the cor-
rect material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD 51-12
to predict power loss heat flow and temperature readings
at different interfaces that enable the calculation of the
JEDEC-defined thermal resistance values; (3) the model
and FEA software is used to evaluate the LTM4644 with
heat sink and airflow; (4) having solved for and analyzed
these thermal resistance values and simulated various
operating conditions in the software model, a thorough
laboratory evaluation replicates the simulated conditions
with thermocouples within a controlled-environment
chamberwhileoperatingthedeviceatthesamepowerloss
as that which was simulated. An outcome of this process
and due diligence yields the set of derating curves shown
in this data sheet.
for correlating the thermal resistance. Thermal models
are derived from several temperature measurements in a
controlled temperature chamber along with thermal mod-
eling analysis. The junction temperatures are monitored
while ambient temperature is increased with and without
airflow.Thepowerlossincreasewithambienttemperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
currentorpowerwithincreasingambienttemperature.The
decreasedoutputcurrentwilldecreasetheinternalmodule
loss as ambient temperature is increased. The monitored
junction temperature of 120°C minus the ambient operat-
ing temperature specifies how much module temperature
rise can be allowed. As an example in Figure 16 the load
current is derated to 9.6A at ~90°C with 400LFM of airflow
and no heat sink and the power loss for the 12V to 1.0V
at 9.5A output is about 3.2W. The 3.2W loss is calculated
with 4 times the 0.6W room temperature loss from the
12V to 1.0V power loss curve each channel at 2.4A, and
the 1.35 multiplying factor at 120°C junction. If the 90°C
ambient temperature is subtracted from the 120°C junc-
tion temperature, then the difference of 30°C divided by
The 1V to 5V power loss curves in Figures 9 to 15 can
be used in coordination with the load current derating
curves in Figures 16 to 29 for calculating an approximate
θ thermal resistance for the LTM4644 with various heat
JA
3.2W equals ~9.4°C/W θ thermal resistance. Table 3
JA
sinking and airflow conditions. The power loss curves
are taken at room temperature, and are increased with a
multiplicativefactoraccordingtothejunctiontemperature.
This approximate factor is 1.35 for 120°C. The derating
curves are plotted with the output current starting at 16A
and the ambient temperature at 30°C. These are chosen
to include the lower and higher output voltage ranges
specifies a 10°C/W value which is very close. Tables 3 to
6 provide equivalent thermal resistances for the different
outputs with and without airflow and heat sinking. The
derived thermal resistances in Tables 3 to 6 for the various
conditions can be multiplied by the calculated power loss
asafunctionofambienttemperaturetoderivetemperature
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4644 F08
µMODULE DEVICE
Figure 8. Graphical Representation of JESD 51-12 Thermal Coefficients
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rise above ambient, thus maximum junction temperature.
Room temperature power loss can be derived from the ef-
ficiencycurvesintheTypicalPerformanceCharacteristics
section and adjusted with the above junction temperature
multiplicative factor. The printed circuit board is a 1.6mm
thick four layer board with two ounce copper for the two
outerlayersandoneouncecopperforthetwoinnerlayers.
The PCB dimensions are 95mm × 76mm.
For example, to determine the maximum ambient tem-
perature when V
= 2.5V at 0.6A, V
= 3.3V at 3A,
OUT1
OUT2
V
OUT3
= 1.8V at 1A, V
= 1.2V at 3A, without a heat sink
OUT4
and 400LFM airflow, simply add up the total power loss
for each channel read from Figure 9 to Figure 15 which in
this example equals 2.5W, then multiply by the 1.35 coef-
ficient for 120°C junction temperature and compare the
total power loss number, 3.4W with Figure 30. Figure 30
indicates with a 3.4W total power loss, the maximum am-
bient temperature for this particular application is around
86°C. For reference, the actual thermal derating test in the
chamber resulted in a maximum ambient temperature
of 86.3°C, very close to the calculated value. Also from
Figure 30, it is easy to determine with a 3.4W total power
loss, the maximum ambient temperature is around 77°C
with no airflow and 81°C with 200LFM airflow.
The 16A represents all four channels in parallel at 4A each.
The four parallel channels have their currents reduced at
the same rate to develop an equivalent θ circuit evalu-
JA
ation with thermal couples or IR camera used to validate
the thermal resistance values.
Maximum Operating Ambient Temperature
Figures 30 and 31 display the Maximum Power Loss
Allowance Curves vs ambient temperature with various
heatsinkingandairflowconditions. Thisdatawasderived
from the thermal impedance generated by various ther-
mal derating examinations with the junction temperature
measured at 120°C. This maximum power loss limitation
serves as a guideline when designing multiple output
rails with different voltages and currents by calculating
the total power loss.
Safety Considerations
The LTM4644 modules do not provide galvanic isolation
from V to V . There is no internal fuse. If required,
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure. The device does support thermal
shutdown and overcurrent protection.
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1.5
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
12V
IN
12V
IN
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
IN
5V
5V
IN
0
2.5
LOAD CURRENT (A)
3
3.5
4
0
2.5
LOAD CURRENT (A)
3
3.5
4
0.5
1
1.5
2
0.5
1
1.5
2
4641 F09
Figure 9. Power Loss at 1.0V
Output, (Each Channel, 25°C)
Figure 10. Power Loss at 1.2V 4641 F10
Output, (Each Channel, 25°C)
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
12V
IN
12V
IN
5V
IN
5V
IN
0
2.5
LOAD CURRENT (A)
3
3.5
4
0
2.5
LOAD CURRENT (A)
3
3.5
4
0.5
1
1.5
2
0.5
1
1.5
2
4641 F12
4641 F11
Figure 12. Power Loss at 1.8V
Output, (Each Channel, 25°C)
Figure 11. Power Loss at 1.5V
Output, (Each Channel, 25°C)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
12V
IN
12V
IN
IN
5V
5V
IN
0
2.5
LOAD CURRENT (A)
3
3.5
4
0
2.5
LOAD CURRENT (A)
3
3.5
4
0.5
1
1.5
2
0.5
1
1.5
2
4641 F13
4641 F14
Figure 13. Power Loss at 2.5V
Output, (Each Channel, 25°C)
Figure 14.Power Loss at 3.3V
Output, (Each Channel, 25°C)
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1.8
18
16
14
12
10
8
12V
IN
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6
4
0LFM
200LFM
400LFM
2
0
0
2.5
LOAD CURRENT (A)
3
3.5
4
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
0.5
1
1.5
2
4641 F15
4641 F16
Figure 15. Power Loss at 5V
Output, (Each Channel, 25°C)
Figure 16. 5VIN to 1.0VOUT
Derating Curve 4-Channel
Paralleled, No Heat Sink
18
16
14
12
10
8
18
16
14
12
10
8
6
6
4
4
0LFM
200LFM
400LFM
0LFM
200LFM
400LFM
2
2
0
0
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
4641 F17
4641 F18
Figure 17. 12VIN to 1.0VOUT
Derating Curve 4-Channel
Paralleled, No Heat Sink
Figure 18. 5VIN to 1.0VOUT
Derating Curve 4-Channel
Paralleled, BGA Heat Sink
18
16
14
12
10
8
18
16
14
12
10
8
6
6
4
4
0LFM
0LFM
200LFM
400LFM
200LFM
400LFM
2
2
0
0
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
4641 F19
4641 F20
Figure 19. 12VIN to 1.0VOUT
Derating Curve 4-Channel
Paralleled, BGA Heat Sink
Figure 20. 5VIN to 1.5VOUT
Derating Curve 4-Channel
Paralleled, No Heat Sink
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18
16
14
12
10
8
18
16
14
12
10
8
6
6
4
4
0LFM
0LFM
200LFM
400LFM
200LFM
400LFM
2
0
2
0
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
4641 F21
4641 F22
Figure 21. 12VIN to 1.5VOUT
Derating Curve 4-Channel
Paralleled, No Heat Sink
Figure 22. 5VIN to 1.5VOUT
Derating Curve 4-Channel
Paralleled, BGA Heat Sink
18
16
14
12
10
8
18
16
14
12
10
8
6
6
4
4
0LFM
0LFM
200LFM
400LFM
200LFM
400LFM
2
2
0
0
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
4641 F23
4641 F24
Figure 23. 12VIN to 1.5VOUT
Derating Curve 4-Channel
Paralleled, BGA Heat Sink
Figure 24. 5VIN to 3.3VOUT
Derating Curve 4-Channel
Paralleled, No Heat Sink
18
16
14
12
10
8
18
16
14
12
10
8
6
6
4
4
0LFM
0LFM
200LFM
400LFM
200LFM
400LFM
2
2
0
0
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
4641 F25
4641 F26
Figure 25. 12VIN to 3.3VOUT
Derating Curve 4-Channel
Paralleled, No Heat Sink
Figure 26. 5VIN to 3.3VOUT
Derating Curve 4-Channel
Paralleled, BGA Heat Sink
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18
16
14
12
10
8
18
16
14
12
10
8
18
16
14
12
10
8
6
6
6
4
4
4
0LFM
200LFM
400LFM
0LFM
200LFM
400LFM
0LFM
200LFM
2
2
2
400LFM
0
0
0
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
30
60 70 80 90
100 110 120
40 50
AMBIENT TEMPERATURE (°C)
4641 F27
4641 F28
4641 F29
Figure 27. 12VIN to 3.3VOUT
Derating Curve 4-Channel
Paralleled, BGA Heat Sink
10
Figure 28. 12VIN to 5VOUT
Figure 29. 12VIN to 5VOUT
Derating Curve 4-Channel
Paralleled, BGA Heat Sink
Derating Curve 4-Channel
Paralleled, No Heat Sink
12
11
10
9
9
8
7
6
5
4
3
8
7
6
5
4
3
2
0LFM
0LFM
200LFM
400LFM
2
200LFM
1
1
400LFM
0
0
30
60 70 80 90 100 110 120
40 50
AMBIENT TEMPERATURE (°C)
30
60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
40 50
4641 F30
4641 F31
Figure 30. Power Loss Allowance
vs. Ambient Temperature No Heat
Sink
Figure 31. Power Loss Allowance
vs. Ambient Temperature BGA
Heat Sink
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Table 3. 1.0V Output
DERATING CURVE
Figures 16, 17
Figures 16, 17
Figures 16, 17
Figures 18, 19
Figures 18, 19
Figures 18, 19
V
(V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
None
Θ
Θ
Θ
Θ
(°C/W)
IN
JA
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
Figure 9
0
12.5
11
10
11
9
Figure 9
200
400
0
None
Figure 9
None
Figure 9
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 9
200
400
Figure 9
8
Table 4. 1.5V Output
DERATING CURVE
Figures 20, 21
V
IN
(V)
POWER LOSS CURVE
Figure 11
AIR FLOW (LFM)
HEAT SINK
None
(°C/W)
JA
5, 12
0
12.5
11
10
11
9
Figures 20, 21
5, 12
5, 12
5, 12
5, 12
5, 12
Figure 11
200
400
0
None
Figures 20, 21
Figure 11
None
Figures 22, 23
Figure 11
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figures 22, 23
Figure 11
200
400
Figures 22, 23
Figure 11
8
Table 5. 3.3V Output
DERATING CURVE
Figures 24, 25
V
IN
(V)
POWER LOSS CURVE
Figure 14
AIR FLOW (LFM)
HEAT SINK
None
(°C/W)
JA
5, 12
0
12.5
11
10
11
9
Figures 24, 25
5, 12
5, 12
5, 12
5, 12
5, 12
Figure 14
200
400
0
None
Figures 24, 25
Figure 14
None
Figures 26, 27
Figure 14
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figures 26, 27
Figure 14
200
400
Figures 26, 27
Figure 14
8
Table 6. 5V Output
DERATING CURVE
Figures 26, 27
Figures 26, 27
Figures 26, 27
Figures 28, 29
Figures 28, 29
Figures 28, 29
V
IN
(V)
POWER LOSS CURVE
Figure 15
AIR FLOW (LFM)
HEAT SINK
None
(°C/W)
JA
12
0
12.5
11
10
11
9
12
12
12
12
12
Figure 15
200
400
0
None
Figure 15
None
Figure 15
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 15
200
400
Figure 15
8
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Table 7
C
PART NUMBER
VALUE
C
PART NUMBER
VALUE
C
PART NUMBER VALUE
Sanyo 4TPE100MZB 4V 100µF
IN
OUT1
OUT2
Murata
GRM21BR61C106KE15L 10µF, 16V,
0805, X5R
Murata
GRM21BR60J476ME15 47µF, 6.3V,
0805, X5R
Taiyo Yuden EMK212BJ106KG-T
10µF, 16V,
0805, X5R
Taiyo Yuden JMK212BJ476MG-T
47µF, 6.3V,
0805, X5R
Murata
GRM31CR61C226ME15L 22µF, 16V,
1206, X5R
Taiyo Yuden EMK316BJ226ML-T
22µF, 16V,
1206, X5R
C
C
C
OUT2
P-P
DROOP DERIVATION RECOVERY
LOAD
STEP
(A)
LOAD STEP
SLEW RATE
(A/µs)
IN
OUT1
(CERAMIC)
(µF)
C
(CERAMIC) (BULK)
C
FF
V
R
FB
IN
IN
V
(V)
(BULK)
(µF)
(µF)
(pF)
10
10
10
10
10
10
10
10
10
10
10
(V)
(mv)
(mV)
TIME (µs)
(kΩ)
90.9
90.9
90.9
90.9
60.4
60.4
60.4
60.4
40.2
40.2
40.2
40.2
30.1
30.1
30.1
30.1
19.1
19.1
19.1
19.1
13.3
13.3
13.3
13.3
8.25
8.25
OUT
1
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
47
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5,12
5
72
40
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
100µF
5
60
40
47
47
47
47
47
47
47
47
47
47
47
47
5
127
90
40
5
40
1.2
5
76
40
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
5
5
65
40
5
145
103
80
40
5
40
5
40
5
70
40
5
161
115
95
40
5
40
5
40
5
80
40
5
177
128
125
100
225
161
155
122
285
198
220
420
40
5
40
5
40
5
50
5
40
5
50
5
40
5
60
5
40
10
10
10
5
60
5
40
5
5
40
4644fd
25
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
APPLICATIONS INFORMATION
Layout Checklist/Example
• To minimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
The high integration of LTM4644 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
• Do not put via directly on the pad, unless they are
capped or plated over.
• Use large PCB copper areas for high current paths,
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
including V to V , GND, V
to V
. It helps to
IN1
IN4
OUT1
OUT4
minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci-
• For parallel modules, tie the V , V , and COMP pins
OUT FB
tors next to the V , GND and V
pins to minimize
OUT
together. Use an internal layer to closely connect these
pinstogether. TheTRACK/SSpincanbetiedacommon
capacitor for regulator soft-start.
IN
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• Bring out test points on the signal pins for monitoring.
Figure32givesagoodexampleoftherecommendedlayout.
COUT
COUT
COUT
CIN
Figure 32. Recommended PCB Layout
4644fd
26
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
TYPICAL APPLICATIONS
CLKIN
CLKOUT
V
V
4V to 14V
3.3V/4A
IN1
OUT1
FB1
10µF
×4
16V
1206
47µF
6.3V
0805
SVIN1
RUN1
INTV
LTM4644
COMP1
TRACK/SS1
PGOOD1
13.3k
CC1
0.1µF
MODE1
2.5V/4A
V
V
IN2
OUT2
FB2
47µF
4V
0805
SVIN2
RUN2
INTV
COMP2
TRACK/SS2
PGOOD2
19.1k
CC2
60.4k
13.3k
MODE2
1.5V/4A
V
V
IN3
OUT3
47µF
4V
0805
SVIN3
RUN3
INTV
FB3
COMP3
TRACK/SS3
PGOOD3
40.2k
90.9k
CC3
60.4k
MODE3
1V/4A
V
V
13.3k
IN4
OUT4
47µF
4V
0805
SVIN4
RUN4
INTV
FB4
COMP4
TRACK/SS4
PGOOD4
CC4
60.4k
MODE4
TEMP SGND GND
4644 F41
13.3k
Figure 33. 4V to 14V Input, Quad 1.2V, 1.5V, 2.5V and 3.3V Output with Tracking
4644fd
27
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
TYPICAL APPLICATIONS
CLKIN
CLKOUT
V
V
2.375V to 5V
10µF
1.8V/4A
1.5V/4A
IN1
OUT1
FB1
47µF
4V
SVIN1
RUN1
INTV
×4
LTM4644
COMP1
TRACK/SS1
PGOOD1
6.3V
1206
30.1k
40.2k
60.4k
90.9k
0805
CC1
0.1µF
0.1µF
MODE1
V
V
IN2
OUT2
FB2
47µF
4V
0805
SVIN2
RUN2
INTV
CC2
5V BIAS
COMP2
TRACK/SS2
PGOOD2
1µF
6.3V
MODE2
1.2V/4A
1V/4A
V
V
IN3
OUT3
FB3
47µF
4V
0805
SVIN3
RUN3
INTV
COMP3
TRACK/SS3
PGOOD3
CC3
MODE3
0.1µF
0.1µF
V
V
IN4
OUT4
FB4
47µF
4V
0805
SVIN4
RUN4
INTV
COMP4
TRACK/SS4
PGOOD4
CC4
MODE4
TEMP SGND GND
4644 F41
Figure 34. 2.375V to 5V Input, Quad 1V, 1.2V, 1.5V, 1.8V Output
4644fd
28
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
TYPICAL APPLICATIONS
CLKIN
CLKOUT
V
IN
V
V
1.2V/16A
47µF
IN1
OUT1
FB1
4V to 14V
22µF
×2
16V
1206
SVIN1
RUN1
INTV
×3
4V
LTM4644
COMP1
15.1k
0805
TRACK/SS1
PGOOD1
CC1
MODE1
0.1µF
V
V
IN2
OUT2
FB2
SVIN2
RUN2
INTV
COMP2
TRACK/SS2
PGOOD2
CC2
MODE2
V
V
IN3
OUT3
FB3
SVIN3
RUN3
INTV
COMP3
TRACK/SS3
PGOOD3
CC3
MODE3
V
V
IN4
OUT4
FB4
SVIN4
RUN4
INTV
COMP4
TRACK/SS4
PGOOD4
CC4
V
IN
MODE4
V
– 0.6V
100µA
IN
TEMP SGND GND
R
T
=
R
T
4644 F35
A/D
Figure 35. 4V to 14V Input, 4-Phase, 1.2V at 16A Design with Temperature Monitoring
4644fd
29
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
TYPICAL APPLICATIONS
CLKIN
CLKOUT
V
1.2V/16A
OUT1
47µF
×3
V
60.4k
60.4k
IN
V
IN1
4V to 14V
4V
22µF
×2
16V
1206
FB1
SVIN1
RUN1
INTV
0805
LTM4644-1
COMP1
TRACK/SS1
PGOOD1
CC1
MODE1
0.1µF
V
V
OUT2
IN2
FB2
COMP2
SVIN2
RUN2
TRACK/SS2
PGOOD2
INTV
MODE2
CC2
V
V
OUT3
IN3
FB3
COMP3
SVIN3
RUN3
TRACK/SS3
PGOOD3
INTV
MODE3
CC3
V
V
OUT4
IN4
FB4
COMP4
SVIN4
RUN4
TRACK/SS4
PGOOD4
INTV
MODE4
CC4
V
IN
V
– 0.6V
100µA
IN
TEMP SGND GND
R
=
R
T
T
4644 F36
A/D
Figure 36. 4V to 14V Input, 4-Phase, 1.2V at 16A Design with Temperature Monitoring
4644fd
30
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
TYPICAL APPLICATIONS
CLKIN
CLKOUT
V
V
5V
1.2V/8A
47µF
IN1
OUT1
FB1
22µF
×2
16V
1206
SVIN1
RUN1
INTV
×2
4V
LTM4644
COMP1
TRACK/SS1
PGOOD1
30.2k
0805
CC1
MODE1
0.1µF
V
V
IN2
OUT2
FB2
SVIN2
RUN2
INTV
COMP2
TRACK/SS2
PGOOD2
CC2
MODE2
12V
22µF
×2
V
V
3.3V/8A
47µF
IN3
OUT3
FB3
SVIN3
RUN3
INTV
×2
COMP3
TRACK/SS3
PGOOD3
6.3V
16V
1206
6.65k
0805
CC3
MODE3
0.1µF
V
V
IN4
OUT4
FB4
SVIN4
RUN4
INTV
COMP4
TRACK/SS4
PGOOD4
CC4
MODE4
TEMP SGND GND
4644 F36
Figure 37. 12V and 5V Two Separate Input Rails, 1.2V at 8A and 3.3V at 8A Output
4644fd
31
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
TYPICAL APPLICATIONS
W R V P
V I N _ S N S
I I N _ S N S P
I I N _ S N S M
C H A N N E L 0
C H A N N E L 1
C H A N N E L 2
C H A N N E L 3
4644fd
32
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
LTM4644/LTM4644-1 Component BGA Pinout
PIN
A1
A2
A3
A4
A5
A6
A7
NAME
PIN
B1
B2
B3
B4
B5
B6
B7
NAME
GND
PIN
C1
C2
C3
C4
C5
C6
C7
NAME
PIN
D1
D2
D3
D4
D5
D6
D7
NAME
PIN
E1
E2
E3
E4
E5
E6
E7
NAME
GND
PIN
F1
F2
F3
F4
F5
F6
F7
NAME
V
V
V
V
OUT2
V
OUT2
V
OUT2
V
OUT3
OUT1
OUT1
OUT1
GND
PGOOD2
PGOOD1
GND
PGOOD3
TEMP
V
V
GND
GND
V
V
IN1
IN1
IN2
IN2
GND
GND
INTV
INTV
CC2
CC1
SV
GND
GND
SV
GND
IN1
IN2
TRACK/SS1
FB1
MODE1
COMP1
RUN1
CLKIN
TRACK/SS2
FB2
MODE2
COMP2
RUN2
SGND
PIN
G1
G2
G3
G4
G5
G6
G7
NAME
PIN
H1
H2
H3
H4
H5
H6
H7
NAME
GND
PIN
J1
J2
J3
J4
J5
J6
J7
NAME
PIN
K1
K2
K3
K4
K5
K6
K7
NAME
PIN
L1
L2
L3
L4
L5
L6
L7
NAME
GND
V
V
V
OUT4
V
V
OUT3
OUT3
OUT4
OUT4
GND
PGOOD4
CLKOUT
GND
GND
GND
V
IN3
V
IN3
GND
GND
V
IN4
V
IN4
INTV
CC3
GND
SV
IN3
GND
INTV
SV
IN4
CC4
TRACK/SS3
FB3
MODE3
COMP3
RUN3
FB4
TRACK/SS4
RUN4
MODE4
COMP4
4644fd
33
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTM4644#packaging for the most recent package drawings.
BGA Package
77-Lead (9mm × 15mm × 5.01mm)
(Reference LTC DWG # 05-08-1900 Rev D)
Z
/ / b b b
Z
3 . 8 1 0
2 . 5 4 0
1 . 2 7 0
0 . 3 1 7 5
0 . 3 1 7 5
1 . 2 7 0
0 . 0 0 0
2 . 5 4 0
3 . 8 1 0
4644fd
34
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/14 Add SnPb BGA package option
1, 2
B
06/14 Add Tech Clip video link
Update Order Information
1
2
Update Run Threshold
3
Update Figure 5
13
14
2
Update Soft-Start and Output Voltage Tracking Section
05/16 Added MP-grade (–55°C to 125°C)
C
D
12/16 Added LTM4644-1
1 ,2, 4, 9, 10, 33
Added Comparison Table between LTM4644 and LTM4644-1
Added Output Voltage Programing (LTM4644-1)
Added Figure 36
1
10
30
32
Added Figure 38
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
4644fd
35
For more information www.linear.com/LTM4644
LTM4644/LTM4644-1
PACKAGE PHOTO
DESIGN RESOURCES
SUBJECT
DESCRIPTION
Design:
• Selector Guides
µModule Design and Manufacturing Resources
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
• Demo Boards and Gerber Files
• Free Simulation Tools
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4624
LTM4619
LTM4618
LTM4628
14V , 4A Step-Down µModule Regulator in Tiny
4V ≤ V ≤ 14V, 0.6V ≤ V
≤ 5.5V, V
Tracking, PGOOD, Light Load Mode,
IN
IN
OUT
2
OUT
6.25mm × 6.25mm × 5.01mm BGA
Complete Solution in 1cm (Single-Sided PCB)
Dual 26V, 4A Step-Down µModule Regulator
4.5V ≤ V ≤ 26.5V, 0.8V ≤ V
≤ 5V, PLL Input, V
≤ 5V, PLL Input, V
OUT
Tracking, PGOOD,
Tracking,
IN
OUT
OUT
15mm × 15mm × 2.82mm LGA
4.5V ≤ V ≤ 26.5V, 0.8V ≤ V
26V, 6A Step-Down µModule Regulator
IN
OUT
9mm × 15mm × 4.32mm LGA
4.5V ≤ V ≤ 26.5V, 0.6V ≤ V
Dual 26V, 8A Step-Down µModule Regulator
≤ 5.5V, Remote Sense Amplifier, Internal
OUT
IN
Temperature Sensing Output, 15mm × 15mm × 4.32mm LGA
2.375V ≤ V ≤ 5.5V, 0.8V ≤ V ≤ 5V, 15mm × 15mm × 2.82mm LGA
LTM4614
Dual 5V, 4A µModule Regulator
IN
OUT
LTM4608A
5V, 8A Step-Down µModule Regulator with
2.7V ≤ V ≤ 5.5V, 0.6V ≤ V
≤ 5V, PLL input, Clock Output, V
Tracking and
IN
OUT
OUT
Tracking, Margining and Frequency Synchronization Margining, PGOOD, 9mm × 15mm × 2.82mm LGA
LTM4616
LTM8045
LTM8001
Dual 5V, 8A Step-Down µModule Regulator with
2.7V ≤ V ≤ 5.5V, 0.6V ≤ V
≤ 5V, PLL input, Clock Output, V
Tracking and
IN
OUT
OUT
Tracking, Margining and Frequency Synchronization Margining, PGOOD, 15mm × 15mm × 2.82mm LGA
Inverting or SEPIC µModule DC/DC Converter with 2.8V ≤ V ≤ 18V, 2.5V ≤ V
Up to 700mA Output Current
36V, 5A Step-Down µModule Regulator with
Configurable Array of Five 1A LDOs
≤
15V, Synchronizable, No Derating or Logic-
IN
OUT
Level Shift for Control Inputs when Inverting, 6.25mm × 11.25mm × 4.92mm BGA
6V ≤ V ≤ 36V, 0V ≤ V
≤ 24V, Five Parallelable 1.1A 90µV
Output Noise
IN
OUT
RMS
LDOs, Synchronizable, Adjustable Switcher Output Current Limit, 15mm × 15mm
× 4.92mm BGA
2
LTC®2978
LTC2974
Octal Digital Power Supply Manager with EEPROM I C/PMBus Interface, Configuration EEPROM, Fault Logging, 16-Bit ADC with
0.25ꢀ TUE, 3.3V to 15V Operation
Quad Digital Power Supply Manager with EEPROM I C/PMBus Interface, Configuration EEPROM, Fault Logging, Per Channel Voltage,
2
Current and Temperature Measurements
4644fd
LT 1216 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4644
●
●
LINEAR TECHNOLOGY CORPORATION 2013
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