ASDL-7021 [LITEON]
IrDA팜 FIR/VFIR Controller in TFBGA Package; IrDA FIR / VFIR控制器在TFBGA封装
| 型号： | ASDL-7021 |
| 厂家： | 
LITE-ON TECHNOLOGY CORPORATION |
| 描述： | IrDA팜 FIR/VFIR Controller in TFBGA Package |
| 文件： | 总23页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASDL-7021
IrDA FIR/VFIR Controller in TFBGA Package
Data Sheet
Description
Features
General Features
• Interfaces with IrDA Compliant IR Transceiver
up to VFIR
• Miniature 48 pin TFBGA Package
Height : 1.2 mm
The ASDL-7021 is a new generation large scale integra-
tion (LSI) IrDA controller supporting speeds of SIR (up
to 115Kbps), MIR(1.152Mbps), FIR(4Mbps) and VFIR
(16Mbps). It consists of IrDA Control Block, Remote
Control Block, Timer Control Block, Global Control block
including Buffer Memory and Direct Memory Access
Control Block (DMA) integrated into one single chip.
Width : 4.0 mm
Depth : 4.0 mm
It has all the hardware including Buffer Memory and
Direct Memory Access (DMA) that enables convenient
access to its peripheral IO and memories from system bus
which is similar to simple memory devices. ASDL-7021 is
a class of its own as unlike conventional LSI which utilizes
external DMA for implementing fast infrared transfer,
complicated bus timing and required additional logic for
its interface.
• 8-bit Memory Mapped Interface
• Input clock of 48 MHz
• 4 transmission speed in 3 Blocks
-
-
-
SIR Block (2.4 to 115.2Kbps)
FIR Block (1.152Mbps for MIR and 4Mbps for FIR)
VFIR Block (16Mbps)
• Operating temperature from -40° C ~ 85°C
-
Critical parameters are guaranteed over
temperature and supply voltage
ASDL-7021 utilizes two memory banks for external access
and internal DMA access; these 2 banks are interchange-
able to prevent bus contention. These two banks can be
switched using memory select function of the internal
register and separates internal bus from external, which
enables parallel operation of external microcontroller
operation and internal IrDA data transfer operation.
ASDL-7021 has embedded Universal Remote Control (RC)
function for general purpose remote control communica-
tion.
• Core Power Supply = 1.8V
Clock Power Supply = 3.3V
IO Power Supply =1.8V, 2.5V, 3.3V
• RAM Block with On-Chip buffer memory of 8KByte x 2
Bank Configuration
-
-
1 bank for external access x 8 bit width
1 bank for internal access x 8 bit width through
on-chip DMA block
These 2 banks can be switched
Each transmit and receive have their own buffer
memory of 8KByte x 2
Together with Lite-On FIR transceiver and IrSimple
software, ASDL-7021 is designed to provide Industry
a total solution for high speed wireless connectivity
solution in miniature packaging.
-
-
BANK0
Applications
FIR block
• Mobile Data Communication and Universal Remote
CPU
Control
BANK1
-
Mobile Phones
-
-
-
-
-
-
-
PDAs
Digital Still Camera
Printer
Notebooks
Handy Terminal
Dongles
DMA
DMA
FIR block
CPU
BANK1
Industrial and Medical Instrument
ꢀ
• Remote Control Block
Generate Remote Control burst signal
• Timer Block
Features (Cont.)
• Infrared Interface Block
-
-
IrDA send/receive functions (IRTX0, IRRX0)
Remote Control send function (IRTX1)
-
-
2 channels of generic 16 bit timer
1 channel of Mediabusy timer
• DMA Block
• Moisture Level 3
• Lead-Free and ROHS Compliant
-
DMA transfer function between buffer memory and
SIR, FIR, VFIR block
B1 D6 E4 F5
C2
C4 C5 C6
IrRXD0
A[7:0]
D[7:0]
A6
D1,D2,E2,E1,G1,G2,F1,F2
G3,F3,F4,G4,G5,F7,G6,G7
IrTX0 (IrDA)
B6
IrDA
IrTX1 (Remote)
Transceiver
I/F
C7
B7
A7
IrOUT0 (IrMode)
Ir0UT1 (SD)
/CS
F6
E5
Host
I/F
/WE
/OE
/IRQ
ASDL-7021
E6
D7
/XTALIN
A3
A2
B2
C1
INTERNAL
CLOCK
/XTALOUT
CLKIN
/SD
EXTERNAL
CLOCK
E7
D5
/RESET
CLKSEL
A1
B3
C3
D3
E3
Figure 1a. Pin Layout of ASDL-7021
Figure 1b. Pin layout of ASDL-7021 (Top View)
ꢁ
Application Support Information
The Application Engineering Group is available to assist you with the application design associated with ASDL-7021
FIR/VFIR Controller. You can contact them through your local sales representatives for additional details.
Order Information
Part Number
Packaging Type
Quantity
ASDL-70ꢁꢀ
Tape and Reel
4000
I/O Pins Configuration Table
Pins Description
Buffer Type
(Refer to Figure 2)
Symbol
Power
VDDK
VDDC
VIOꢀ
Pin(s)
Type
Description
C4,C5,C6
POWER
POWER
POWER
POWER
POWER
POWER
ꢀ.8V Power
ꢂ.ꢂV Power
ꢀ.8V, ꢁ.5V, ꢂ.ꢂV
ꢀ.8V, ꢁ.5V, ꢂ.ꢂV
ꢀ.8V, ꢁ.5V, ꢂ.ꢂV
GND
Cꢁ
E4,F5
VIOꢁ
D6
VIOꢂ
Bꢀ
GND
Aꢀ,Bꢂ,Cꢂ,Dꢂ,Eꢂ
Bus Interface Signals (VIO1 Voltage)
A0-A7
Dꢀ,Dꢁ,Eꢁ,Eꢀ,
Gꢀ,Gꢁ,Fꢀ,Fꢁ
I
I
An 8-bit address signal line connects itself directly with an external address bus. It selects the
internal buffer memory and the register addresses of each function module. With the assertion
of the CS signal, A0 - A7 turn out to be valid, which decides the internal addresses.
D0-D7
Gꢂ,Fꢂ,F4,G4
G5,F7,G6,G7
I/O
IO4
An 8-bit data signal line connects itself directly with an external data bus. It is a signal that
performs data conversion with the internal buffer memory and each function module.The bus
direction is determined by WE and OE.
/CS
F6
E5
I
I
I
I
CS is a chip select signal for the IC. Asserting CS activates the external bus of this LSI.
/WE
The WE signal turns the direction of a data bus to the input direction, and takes it into the IC for
the internal buffer memory and registers designated by the address bus, at the start-up of the
signal.
/OE
E6
I
I
The OE signal turns the data bus direction to the output direction, and outputs to the data bus
the contents of the internal buffer memory and register designated by the address bus.
/IRQ
D7
O
O4
This is a signal line that notifies to the outside that ASDL-70ꢁꢀ requests an interrupt.
ꢂ
Other Signals (VIO1 Voltage)
/RESET
/SD
D5
E7
I
I
I
This RESET signal resets ASDL-70ꢁꢀ.
I (internal PullDown)
ꢀ. Low: Shutdown
IC is suspending the clock supply to the core.
The output signal retains the condition.
ꢁ. High: IC is keeping the clock supply to the core.
However, when the externally connected quartz crystal is used with
CLKSEL=Low, the oscillation of the quartz crystal is kept performed
under the condition of CLKSEL=Low, and SD: Low.
When you want to stop the quartz crystal oscillation, you must set
CLKSEL=High.
ꢂ. After wake up from SD, the IC must be reset.
CLKSEL
Cꢀ
I
I
This is used for selecting whether the input signal from CLKIN should be used for the
clock input or whether the quartz crystal should be used at XTALIN and XTALOUT.
Using quartz crystal,
CLKSEL = Low, external quartz crystal is kept under oscillation
CLKSEL = High, external quartz crystal is suspending oscillation
Using CLKIN signal, set CLKSEL = High
Infrared Interface Signal (VIO2 voltage)
IrTXD0
IrTXDꢀ
IrRXD0
IrOUT0
IrOUTꢀ
B6
C7
A6
B7
A7
O
O
I
O4
O4
I
This outputs the IrDA infrared signal and remote control send signal.
This outputs the IrDA infrared signal and remote control send signal.
This inputs a signal from the infrared module.
O
O
O4
O4
This is an output signal for controlling the infrared module.
This is an output signal for controlling the infrared module.
Clock Signal (VIO3 voltage)
CLKIN
Bꢁ
I
I
Clock input
Clock Signal (VDDC Voltage)
/XTALIN
Aꢂ
I
You must connect quartz crystal to create a basic clock or input the clock from outside.
Usually you must connect the quartz crystal between XTALIN and
XTALOUT. The oscillation frequency of the crystal must be 48MHz.
/XTALOUT
Aꢁ
O
TEST Signal
TESTꢀ
TESTꢁ
TESTꢂ
TESTSE
B5
A5
A4
B4
I
I
I
I
I (Internal PullDown)
I (Internal PullDown)
I (Internal PullDown)
I (Internal PullDown)
Test signal (Set to N.C).
Test signal (Set to N.C).
Test signal (Set to N.C).
Test signal (Set to N.C).
4
Output BufferType
O4:
I
I(schmitt)
I(pulldown)
IOL=4mA,IOH=4mA(VIO = 3.3V)
IOL=2.2mA,IOH=2.2mA(VIO = 2.5V)
IOL=1.4mA,IOH=1.4mA(VIO = 1.8V)
VIO
VIO
VIO
O4
IO4
VIO
VIO
Figure 2. I/O Description
Block Diagram
Figure 3. Block Diagram of internal blocks of ASDL-7021
5
Registers Descriptions
Block Name
IrDA
Base Address
0x0000
Offset
0000h
000ꢀh
000ꢁh
000ꢂh
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
00ꢀ0h
00ꢀꢀh
00ꢀꢁh
00ꢀꢂh
00ꢀ4h
00ꢀ5h
00ꢀ6h
00ꢀ7h
00ꢀ8h
00ꢀ9h
00ꢀAh
00ꢀBh
00ꢀCh
00ꢀDh
00ꢀEh
00ꢀFh
00ꢁ0h
00ꢁꢀh
00ꢁꢁh
00ꢁꢂh
00ꢁ4h
00ꢁ5h
00ꢁ6h
00ꢁ7h
00ꢁ8h
00ꢁ9h
00ꢁAh
00ꢁBh
00ꢁCh
00ꢁDh
00ꢁEh
00ꢁFh
00ꢂ0h
00ꢂꢀh
00ꢂꢁh
00ꢂꢂh
00ꢂ4h
00ꢂ5h
00ꢂ6h
00ꢂ7h
Register Name
IRBA0R(IR Base Address0 Register)
IRBAꢀR(IR Base Addressꢀ Register)
IRBAꢁR(IR Base Addressꢁ Register)
IRRSR(IR Ring Size Register)
IRPLC0R(IR Physical Layer Config0 Register) (unused)
IRPLCꢀR(IR Physical Layer Configꢀ Register) (unused)
IRPLCꢁR(IR Physical Layer Configꢁ Register)
IRPLCꢂR(IR Physical Layer Configꢂ Register)
IRC0R(IR Config0 Register)
IRCꢀR (IR Configꢀ Register)
IRCꢁR (IR Configꢁ Register)
IRCꢂR (IR Configꢂ Register)(unused)
IRE0R(IR Enable0 REG.)
IREꢀR (IR EnableꢀREG.)
IRMPL0R(IR Max Packet Length0 REG.)
IRMPLꢀR (IR Max Packet LengthꢀREG.)
IRRP0R(IR Ring Prompt0 REG.)
IRRPꢀR (IR Ring Prompt Registerꢀ REG.) (unused)
IRRPꢁR (IR Ring Prompt Registerꢁ REG.) (unused)
IRRPꢂR (IR Ring Prompt Registerꢂ REG.) (unused)
IRRBC0R(IR Receive Byte Count0 REG.)
IRRBCꢀR (IR Receive Byte Countꢀ REG.)
IRRRPR0R(IR Rx Ring Pointer Readback REG.)
IRTRPR0R (IR Tx Ring Pointer Readback REG.)
IRSF0R(IR SIR Flags0 REG.)
IRSFꢀR (IR SIR Flagsꢀ REG.)
IRLPC0R(IR Latched Phy Config0 REG.)
IRLPCꢀR (IR Latched Phy Config ꢀREG.)
IRAC0R(IR Address Compare0 REG.)
IRACꢀR (IR Address Compareꢀ REG.)
IRACꢁR (IR Address Compareꢁ REG.)
IRACꢂR (IR Address Compareꢂ REG.)
IRLT0R(IR Latency Timer0 REG.)
IRLTꢀR (IR Latency Timerꢀ REG.)
IRLTꢁR (IR Latency Timerꢁ REG.)
IRLTꢂR (IR Latency Timerꢂ REG.)
IRLIV0R(IR LED Indicator and Rx value0 REG.)
IRLIVꢀR (IR LED Indicator and Rx valueꢀ REG.) (unused)
IRLIVꢁR (IR LED Indicator and Rx valueꢁ REG.) (unused)
IRLIVꢂR (IR LED Indicator and Rx valueꢂ REG.) (unused)
IRCS0R(IR Clock Speed0 REG.)
IRCSꢀR (IR Clock Speedꢀ REG.)
IRCSꢁR (IR Clock Speedꢁ REG.) (unused)
IRCSꢂR (IR Clock Speedꢂ REG.) (unused)
IRPM0R(IR Power management REG.)
IRPMꢀR (IR Power management REG.) (unused)
IRPMꢁR (IR Power management REG.) (unused)
IRPMꢂR (IR Power management REG.) (unused)
IRIS0R(Interrupt status read back0 REG.)
IRISꢀR (Interrupt status read backꢀ REG.) (unused)
IRISꢁR (Interrupt status read backꢁ REG.) (unused)
IRISꢂR (Interrupt status read backꢂ REG.) (unused)
IRIE0R (Interrupt enable read back0 REG.)
IRIEꢀR (Interrupt enable read backꢀ REG.) (unused)
IRIEꢁR (Interrupt enable read backꢁ REG.) (unused)
IRIEꢂR (Interrupt enable read backꢂ REG.) (unused)
6
Block Name
IrDA
Base Address
0x0080
(TXFL FIFO)
Offset
0000h
000ꢀh
000ꢁh
000ꢂh
0004h
0005h
0006h
0007h
0008h
0009h
0000h
000ꢀh
000ꢁh
000ꢂh
0004h
0005h
0006h
0007h
0008h
0000h
0000h
000ꢀh
000ꢁh
000ꢂh
0004h
0005h
0006h
0007h
0000h
0000h
000ꢀh
000ꢁh
000ꢂh
0004h
0005h
0006h
0000h
000ꢀh
000ꢁh
000ꢂh
0004h
0005h
0006h
0000h
000ꢀh
000ꢁh
000ꢂh
0004h
0005h
0006h
0000h
000ꢀh
000ꢁh
000ꢂh
0004h
0005h
0006h
Register Name
TXFL0R(TX Frame Length0 REG.)
TXFLꢀR(TX Frame Lengthꢀ REG.)
Unused
TXSR(TX Status REG.)
TXFA0R(TX Frame Address0 REG.)
TXFAꢀR(TX Frame Addressꢀ REG.)
TXFAꢁR(TX Frame Addressꢁ REG.)
TXFAꢂR(TX Frame Addressꢂ REG.)
TXSIR(TX Status IncrementREG.)
TXFCR(TX Frame Count REG)
RXFL0R(RX Frame Length0 REG.)
RXFLꢀR(RX Frame Lengthꢀ REG.)
Unused
IrDA
0x0090
(RXFL FIFO)
RXSR(RX Status REG.)
RXFA0R(RX Frame Address0 REG.)
RXFAꢀR(RX Frame Addressꢀ REG.)
RXFAꢁR(RX Frame Addressꢁ REG.)
RXFAꢂR(RX Frame Addressꢂ REG.)
RXSIR(RX Status IncrementREG.)
MTDR (Memory Transmit Data REG) Write Only
MRDR(Memory Receive Data REG) Read Only
MCR(Memory Control REG.)
Global Control
0x00A0
GISR(Global Interrupt Status REG.)
IRSR (IR Select REG.)
IOR(Ir Output REG)
IIR(Ir Input REG)
ISIER(Ir Sir Interupt Enable REG)
ISISR(Ir Sir Interupt Status REG)
DMACR(DMA Control REG)
DMA Control
Remote Control
0x00B0
0x00C0
RCCCLR(Remote Control Carrier Count Low REG)
RCCCHR(Remote Control Carrier Count High REG)
RCLLR(Remote Control Length Low REG.)
RCLHR(Remote Control Length High REG.)
RCCR(Remote Control Control REG)
RCCRCLR(Remote Control Carrier RX Count Low REG)
RCCRCHR (Remote Control Carrier RX Count High REG)
TSSR0(Timer Source Setting REG.0)
TIER0(Timer Interrupt Enable REG.0)
TCSR0(Timer Contorol Status REG.0)
TCMLR0(Timer Compare Mach Low REG.0)
TCMHR0(Timer Compare Mach High REG.0)
TCLR0(Timer Count Low REG.0)
TCHR0(Timer Count High REG.0)
TSSRꢀ(Timer Source Setting REG.ꢀ)
TIERꢀ(Timer Interrupt Enable REG.ꢀ)
TCSRꢀ(Timer Contorol Status REG.ꢀ)
TCMLRꢀ(Timer Compare Mach Low REG.ꢀ)
TCMHRꢀ(Timer Compare Mach High REG.ꢀ)
TCLRꢀ(Timer Count Low REG.ꢀ)
TCHRꢀ(Timer Count High REG.ꢀ)
TSSRꢁ(Timer Source Setting REG.ꢁ)
TIERꢁ(Timer Interrupt Enable REG.ꢁ)
TCSRꢁ(Timer Contorol Status REG.ꢁ)
TCMLRꢁ(Timer Compare Mach Low REG.ꢁ)
TCMHRꢁ(Timer Compare Mach High REG.ꢁ)
TCLRꢁ(Timer Count Low REG.ꢁ)
TCHRꢁ(Timer Count High REG.ꢁ)
Timer Control
0x00D0
0x00E0
0x00F0
7
Absolute Maximum Ratings
For implementations where case to ambient thermal resistance is ≤ 50°C/W.
Parameter
Symbol
VDDK
VDDC
VIO
Min.
-0.ꢂ
-0.ꢂ
-0.ꢂ
-0.ꢂ
-40
Max.
VIO+0.ꢂ
ꢂ.6ꢂ
ꢂ.6ꢂ
ꢂ.6ꢂ
85
Units
Core Power Supply Voltage
Clock Power Supply Voltage
IO Power Supply Voltage
Input Output Voltage
V
V
V
VI/VO
TA
V
Operating Environnent Temperature
Storage Temperature
°C
°C
TS
-40
ꢀ50
Electrical Specifications (DC)
Specifications (Min. & Max. values) hold over the recommended operating conditions unless otherwise noted.
Unspecified test conditions may be anywhere in their operating range and VIO = 3.3+0.33V
VIO= 3.3+/-0.33V, TA=-40 to +85°C
Parameter
Symbol
VDDK
VDDC
VIO
Min.
ꢀ.6ꢁ
ꢁ.97
ꢁ.97
Typ.
ꢀ.8
Max.
ꢀ.98
ꢂ.6ꢂ
ꢂ.6ꢂ
0.8
Units
V
Conditions
Core Power Supply
Clock Power Supply
ꢂ.ꢂ
V
IO Power Supply
ꢂ.ꢂ
V
Input Low Voltage
VIL
V
LVTTL
Input High Voltage
VIH
ꢁ.0
0.8
V
LVTTL
Switch Threshold
Vt
ꢀ.5
ꢀ.ꢀ
ꢀ.6
ꢀ
V
LVTTL
Schmitt-Trigger –ve Threshold Voltage
Schmitt- Trigger +ve Threshold Voltage
Input Leakage Current
Vt-
V
LVTTL
Vt+
ꢁ.0
ꢀ0
V
LVTTL
IIN
-ꢀ0
-ꢀ0
µA
µA
V
VI=VIO or GND
VI=VIO or GND
IOL = ꢁ ~ꢀ6mA
IOH = ꢁ ~ꢀ6mA
VIN =VIO
SD:High
Tri-State Output Leakage Current
Output Low Voltage
IOZ
ꢀ
ꢀ0
VOL
0.4
Output High Voltage
VOH
ꢁ.4
V
Input Pull-Down Resistance
Current (VFIR running state) – VDDK
Current (IDLE state) – VDDK
Current (VFIR running state) – VIOꢀ
Current (IDLE state) – VIOꢀ
Current (VFIR running state) – VIOꢁ
Current (IDLE state) – VIOꢁ
Current (IDLE state) – VIOꢂ
Clock Power Supply Current-VDDC
RPD
40
75
ꢀ90
ꢁꢁ.5
ꢁꢁ.0
940
ꢂ0
kΩ
mA
mA
µA
µA
µA
µA
µA
mA
Iozꢀk
IOZꢁk
IOZꢀIOꢀ
IOZꢁIOꢀ
IOZꢀIOꢁ
IOZꢁIOꢁ
IOZꢁIOꢂ
IOZꢀC
ꢀ8.6
ꢀ8.0
ꢁ0.5
ꢁ0.ꢂ
SD:High
SD:High
ꢀ4
SD:High
5ꢁ
SD:High
0.ꢀ
4.8
ꢀ
SD:High
ꢂ8
SD:High
4.0ꢀ
5.9ꢂ
Capacitor ꢁ0pF
8
VIO= 2.5+/-0.25V, TA=-40 to +85°C
Parameter
Symbol
Min.
ꢀ.6ꢁ
ꢁ.97
ꢁ.ꢁ5
Typ.
ꢀ.8
Max.
ꢀ.98
Units
Conditions
Core Power Supply
Clock Power Supply
IO Power Supply
Input Low Voltage
Input High Voltage
Switch Threshold
VDDK
VDDC
VIO
VIL
V
V
V
V
V
V
V
ꢂ.ꢂ
ꢂ.6ꢂ
ꢁ.5
ꢁ.75
0.ꢁ5*VIO
CMOS
CMOS
CMOS
CMOS
VIH
Vt
0.6ꢁ5*VIO
0.ꢁ5*VIO
ꢀ.ꢀ5
0.94
Schmitt-Trigger –ve Threshold
Voltage
Vt-
Schmitt- Trigger +ve Threshold
Voltage
Vt+
ꢀ.4
0.6ꢁ5*VIO
V
CMOS
Input Leakage Current
IIN
-ꢀ0
-ꢀ0
ꢀ
ꢀ
ꢀ0
ꢀ0
0.4
µA
µA
V
VI=VIO or GND
VI=VIO or GND
IOL = ꢀ.ꢀ ~8.8mA
IOH = ꢀ.ꢀ ~8.8mA
VIN =VIO
Tri-State Output Leakage Current
Output Low Voltage
IOZ
VOL
VOH
RPD
Output High Voltage
ꢀ.85
45
V
Input Pull-Down Resistance
ꢀꢀ5
ꢁ90
kΩ
VIO= 1.8+/-0.18V, TA=-40 to +85°C
Parameter
Symbol
VDDK
VDDC
VIO
Min.
Typ.
ꢀ.8
Max.
Units
V
Conditions
Core Power Supply
ꢀ.6ꢁ
ꢁ.97
ꢀ.6ꢁ
ꢀ.98
Clock Power Supply
ꢂ.ꢂ
ꢂ.6ꢂ
V
IO Power Supply
ꢀ.8
ꢀ.98
V
Input Low Voltage
VIL
0.ꢂ*VIO
V
CMOS
Input High Voltage
VIH
0.7*VIO
0.ꢂ*VIO
V
CMOS
Switch Threshold
Vt
0.85
0.65
ꢀ.08
ꢀ
V
CMOS
Schmitt-Trigger –ve Threshold Voltage
Schmitt- Trigger +ve Threshold Voltage
Input Leakage Current
Tri-State Output Leakage Current
Output Low Voltage
Vt-
V
CMOS
Vt+
IIN
0.7*VIO
ꢀ0
V
CMOS
-ꢀ0
-ꢀ0
µA
µA
V
VI=VIO or GND
VI=VIO or GND
IOL = 0.7 ~5.6mA
IOH = 0.7 ~5.6mA
VIN =VIO
IOZ
ꢀ
ꢀ0
VOL
VOH
RPD
0.4
Output High Voltage
0.75*VIO
80
V
Input Pull-Down Resistance
ꢁꢀ0
5ꢀ0
kΩ
9
[1]
Shutdown Currents (Internal Clock is Used)
Parameter
Min.
Typ.
Max.
Unit
Conditions
Note
Shutdown Current ꢀ (VDDK)
ꢀ7.8
ꢀ8.8
ꢀ9.7
mA
/SD: LOW
CLKSEL: LOW
CLKIN: LOW
External quartz crystal is
kept under oscillation
Shutdown Current ꢁ (VDDK)
Clock Power Supply Current (VDDC)
Shutdown Current (VIOꢀ)
Shutdown Current (VIOꢁ)
Shutdown Current (VIOꢂ)
0.4
0.ꢀ
0.ꢀ
0.ꢀ
0.ꢀ
mA
mA
mA
mA
mA
/SD: LOW
CLKSEL: HIGH
CLKIN: LOW
External quartz crystal is
suspending oscillation
/SD: LOW
CLKSEL: HIGH
CLKIN: LOW
/SD: LOW
CLKSEL: HIGH
CLKIN: LOW
/SD: LOW
CLKSEL: HIGH
CLKIN: LOW
/SD: LOW
CLKSEL: HIGH
CLKIN: LOW
[1]
Shutdown Currents (External Clock is Used)
Parameter
Min.
Typ.
Max.
Unit
Conditions
Note
Shutdown Current ꢂ (VDDK)
ꢀꢂ.ꢁ
ꢁꢀ.9
mA
/SD: LOW
CLKSEL: HIGH
CLKIN: 48MHz
/XTALIN: LOW
Clock Power Supply Current (VDDC)
Shutdown Current (VIOꢀ)
Shutdown Current (VIOꢁ)
Shutdown Current (VIOꢂ)
0.ꢀ
0.ꢀ
0.ꢀ
mA
mA
mA
mA
/SD: LOW
CLKSEL: HIGH
LKIN: 48MHz
/XTALIN: LOW
/SD: LOW
CLKSEL: HIGH
CLKIN: 48MHz
/XTALIN: LOW
/SD: LOW
CLKSEL: HIGH
CLKIN: 48MHz
/XTALIN: LOW
8.5
/SD: LOW
CLKSEL: HIGH
CLKIN: 48MHz
/XTALIN: LOW
(1) Test Conditions:
- /RESET = HIGH (VIO1)
- A[7:0] = Must be driven either HIGH (VIO1) or LOW (0V)
- D[7:0] = Must be driven either HIGH (VIO1) or LOW (0V)
- /CS = HIGH (VIO1)
- /WE = HIGH (VIO1)
- /OE = HIGH (VIO1)
- IrRXD0 = HIGH (VIO2)
ꢀ0
Clock Standards
Standard values of the system clock input
Frequency: 48MHz 100ppm
Input Duty: Must be within 50% 5%.
Power-up Procedures
V
VDDC,VIO(=1.8 to 3.3V)
VDDK(=1.8V)
t
Recommended Power-Up Procedure
Turn on the core power supply VDDK before you turn on the VDDC
and VIO power supply and shut it down later
V
VDDC,VIO(=1.8 to 3.3V)
VDDK(=1.8V)
V
V
t
Allowable Limit of Power-Up Procedure
If you want to turn on the core power supply VDDK after you turn on VDDC
and VIO power supply, you must keep V = VIO-VDDK < 0.5V during
the time before VDDK becomes stable
ꢀꢀ
A.C Timing
1) Reset Input Timing
tRST
/RESET
-on Oscillation
Item
Symbol
Min
Typ
Max
Unit
Reset Pulse Width
tRST
50
ns
2) Stabilization Time of Power-on Oscillation (Internal Clock is Used)
Oscillation Stabilization Term
Internal clock
VCC
tRST
tSOC1
/RESET
/SD
Parameter
Symbol
Typical Value
Power-on Oscillation stabilization time
Reset Pulse Width
t
ꢁ0ms
50ns
SOCꢀ
RST
t
ꢀꢁ
Stabilization Time of Power-on Oscillation (External Clock is Used)
Oscillation Stabilization Term
External clock
VCC
tRST
tSOC1
/RESET
/SD
Parameter
Symbol
Typical Value
50ns
Power-on Oscillation stabilization time
Reset Pulse Width
t
SOCꢀ
RST
t
50ns
3) Return Oscillation Stabilization Time via CLKSEL
Oscillation stabilization term
Internal clock
CLKSEL
tSOC1
tRST
/RESET
Item
Symbol
TSOCꢀ
Min
Typ
Max
Unit
CLKSEL return oscillation stabilization time
ꢁ0
msec
Oscillation stabilization time when the quartz crystal is connected
ꢀꢂ
4) Read Operations
/CS
Valid data
A[7:0]
tASR
tAHR
tRDW
/OE
tDRD
tDHW
Valid data
D[7:0]
tWTH
tOET
/OE
Item
Symbol
tASR
Min
Max
Unit
ns
Address setting time
Address retaining time
Data delay time
0
0
tAHR
ns
tDRD
80
ns
Read pulse amplitude
Output retaining time
Turnaround time
tRDW
tDHW
tOET
80
0
ns
ns
50
ns
ꢀ4
5) Write Operations
/CS
Valid data
tWRW
A[7:0]
/WR
tASW
tAHW
tDSW tDHW
Valid data
D[7:0]
tWET
/WE
Item
Symbol
Min
Max
Unit
ns
Address setting time
Address retaining time
Write pulse amplitude
Data setting time
Data retaining time
Turnaround time
tASW
tAHW
tWRW
tDSW
tDHW
tWET
0
0
ns
50
ꢀ0
0
ns
ns
ns
70
ns
ꢀ5
6) Send Pulse Amplitude
Item
Symbol
Conditions
Min
ꢁ0.7
ꢀ0.ꢂ
5.ꢀ6
ꢂ.4ꢂ
ꢀ.70
ꢀ.665
Typ
ꢁ0.8
ꢀ0.4
5.ꢀ8
ꢂ.40
ꢀ.7ꢁ
ꢀ.7ꢁ
Max
ꢁ0.9
ꢀ0.5
5.ꢀ9
ꢂ.47
ꢀ.74
ꢀ.769
Unit
μs
SIR send pulse amplitude
9,600bps
ꢀ9,ꢁ00bps
ꢂ8,400bps
57,600bps
ꢀꢀ5,ꢁ00bps
ꢀ.6μS
tTSPW
ꢂ/ꢀ6 pulse amplitude
μs
μs
μs
μs
pulse amplitude ꢀ.6μs fixed
Typ register IRPLCꢁR,IRPLCꢂR
PW[4:0] = 0x4E
μs
ꢁ0.8nsec Step changeable
SIR send cycle
9,600bps
tTSRT
ꢀ04.0
5ꢁ.0
ꢁ5.ꢁ
ꢀ7.ꢁ
8.5
ꢀ04.ꢀ
5ꢁ.ꢀ
ꢁ6.0
ꢀ7.ꢂ
8.6
ꢀ04.ꢁ
5ꢁ.ꢁ
ꢁ6.ꢀ
ꢀ7.4
8.7
μs
μs
μs
μs
μs
s
ꢀ9,ꢁ00bps
ꢂ8,400bps
57,600bps
ꢀꢀ5,ꢁ00bps
ꢀ.ꢀ5ꢁMbps
MIR send pulse amplitude
tTMPW
Typ register IRPLCꢁR,IRPLCꢂR
PW[4:0] = 0x4E
ꢁꢁ6
ꢁꢁ7
ꢁꢁ8
ꢁ0.8nsec Step changeable
MIR send cycle
ꢀ.ꢀ5ꢁMbps
4Mbps
tTMRT
tTFPW
tTFRT
854
ꢀꢁ4
868
ꢀꢁ5
500
4ꢀ.7
875
ꢀꢁ6
s
s
s
s
FIR send pulse amplitude
FIR send cycle
4Mbps
VFIR send pulse amplitude
ꢀ6Mbps
tTFPW
4ꢀ.0
4ꢂ.0
ꢀ6
ASDL-7021 Package Dimension:
ꢀ7
ꢀ8
ASDL-7021 Tape and Reel Dimension:
ꢀ9
Orientation
PIN 1
Cover tape
Carrier tape
Orientation
ꢁ0
Moisture Proof Packaging
All ASDL-7021 options are shipped in moisture proof
package. Once opened, moisture absorption begins.
This part is compliant to JEDEC Level 3.
UNITS IN A SEALED
MOISTURE-PROOF
PACKAGE
PACKAGE IS OPENED
(UNSEALED)
ENVIRONMENT
PARTS ARE NOT
RECOMMENDED TO
BE USED
NO
LESS THAN 30C
AND LESS THAN
60%RH
YES
PACKAGE IS
OPENED LESS
THAN 168 HOURS
YES
NO BAKING IS
NECESSARY
NO
PACKAGE IS
OPENED LESS
THAN 15 DAYS
NO
YES
PERFORM
RECOMMENDED
BAKING CONDITIONS
Figure 4. Baking Conditions Chart
Baking Conditions
Recommended Storage Conditions
Package
Temp
Time
Storage Temperature
Relative Humidity
ꢀ0°C to ꢂ0°C
below 60% RH
In bulk
ꢀꢁ5 °C
≥ ꢁ4hours
Time from unsealing to soldering
Baking should only be done once.
After removal from the bag, the parts should be soldered
within 7 days if stored at the recommended storage con-
ditions. If times longer than 7 days are needed, the parts
must be stored in a dry box.
ꢁꢀ
Recommended Reflow Profile
MAX 260C
255
R3
R4
230
217
200
R2
180
60 sec to 180 sec
Above 217 C
150
R5
R1
120
80
25
0
100
150
200
P3
SOLDER
REFLOW
250
P4
COOL DOWN
300
t-TIME
(SECONDS)
50
P1
HEAT
UP
P2
SOLDER PASTE DRY
Maximum DT/Dtime
Process Zone
Heat Up
Symbol
Pꢀ, Rꢀ
DT
or Duration
ꢁ5°C to ꢀ50°C
ꢀ50°C to ꢁ00°C
ꢂ°C/s
Solder Paste Dry
Solder Reflow
Pꢁ, Rꢁ
60s to ꢀ80s
Pꢂ, Rꢂ
Pꢂ, R4
ꢁ00°C to ꢁ55°C
ꢁ55°C to ꢁ00°C
ꢂ°C/s
-6°C/s
Cool Down
P4, R5
ꢁ00°C to ꢁ5°C
> ꢁꢀ7°C
-6°C/s
Time maintained above ꢁꢀ7°C
Peak Temperature
60s to ꢀ50s
ꢁ60°C
Time within 5°C of actual Peak Temperature
Time ꢁ5°C to Peak Temperature
> ꢁ55°C
ꢁ0s to 40s
8mins
ꢁ5°C to ꢁ60°C
Process zone P3 is the solder reflow zone. In zone P3,
the temperature is quickly raised above the liquidus
point of solder to 255°C (491°F) for optimum results. The
dwell time above the liquidus point of solder should be
between 20 and 40 seconds. It usually takes about 20
seconds to assure proper coalescing of the solder balls
into liquid solder and the formation of good solder con-
nections. Beyond a dwell time of 40 seconds, the inter-
metallic growth within the solder connections becomes
excessive, resulting in the formation of weak and un-
reliable connections. The temperature is then rapidly
reduced to a point below the solidus temperature of the
solder, usually 200°C (392°F), to allow the solder within
the connections to freeze solid.
The reflow profile is a straight-line representation of
a nominal temperature profile for a convective reflow
solder process. The temperature profile is divided into
four process zones, each with different DT/Dtime tem-
perature change rates or duration. The DT/Dtime rates
or duration are detailed in the above table. The tempera-
tures are measured at the component to printed circuit
board connections.
In process zone P1, the PC board and ASDL-7021 pins
are heated to a temperature of 150°C to activate the flux
in the solder paste. The temperature ramp up rate, R1,
is limited to 3°C per second to allow for even heating of
both the PC board and ASDL-7021 pins.
Process zone P2 should be of sufficient time duration
(100 to 180 seconds) to dry the solder paste. The temper-
ature is raised to a level just below the liquidus point of
the solder, usually 200°C (392°F).
Process zone P4 is the cool down after solder freeze.
The cool down rate, R5, from the liquidus point of the
solder to 25°C (77°F) should not exceed 6°C per second
maximum. This limitation is necessary to allow the PC
board and ASDL-7021 pins to change dimensions evenly,
putting minimal stresses on the ASDL-7021.
ꢁꢁ
Appendix A: General Application Guide for the ASDL-7021 Integrated FIR/VFIR IrDA Controller
IrTX0(IrDA)
IrTX1(Remote
/CS
/OE
IrRXD0
/WE
/IRQ
IrOUT0(IrMode/S CLK)
IrOUT1 (SD)
Host
Microcontroller
ASDL-7021
FIR/VFIR IrDA
Controller
IrDA Transceiver
/SD
(can be STC or non-STC
with/without RC)
Address
Bus
/RESET
CLKSEL
CLKIN
RECOMMENDED FIR HW:
ASDL-3023, HSDL-3021,
HSDL-3020 and HSDL-3220
Data
Bus
Figure A1. Block Diagram of ASDL-7021 interface with Recommended Transceiver and Host Microcontroller
For company and product information, please go to our web site:
WWW.liteon.com or
http://optodatabook.liteon.com/databook/databook.aspx
Data subject to change. Copyright © ꢁ007 Lite-On Technology Corporation. All rights reserved.
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