SP721ABG [LITTELFUSE]
SP721 Series 3pF 4kV Diode Array; SP721系列3pF的4kV的二极管阵列
| 型号： | SP721ABG |
| 厂家： | 
LITTELFUSE |
| 描述： | SP721 Series 3pF 4kV Diode Array |
| 文件： | 总6页 (文件大小：689K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVS Diode Arrays (SPA® Diodes)
General Purpose ESD Protection - SP721 Series
RoHS
GREEN
Pb
SP721 Series 3pF 4kV Diode Array
Description
The SP721 is an array of SCR/Diode bipolar structures for
ESD and over-voltage protection to sensitive input circuits.
The SP721 has 2 protection SCR/Diode device structures
per input. There are a total of 6 available inputs that can be
used to protect up to 6 external signal or bus lines. Over-
voltage protection is from the IN (Pins 1 - 3 and Pins 5 - 7)
to V+ or V-.
The SCR structures are designed for fast triggering at a
threshold of one +VBE diode threshold above V+ (Pin 8) or
a -VBE diode threshold below V- (Pin 4). From an IN input,
a clamp to V+ is activated if a transient pulse causes the
input to be increased to a voltage level greater than one
VBE above V+. A similar clamp to V- is activated if a negative
Pinout
pulse, one VBE less than V-, is applied to an IN input.
Standard ESD Human Body Model (HBM) Capability is:
IN
IN
IN
V-
1
2
3
4
8
7
6
5
V+
IN
IN
IN
SP721 (PDIP, SOIC)
TOP VIEW
Features
• ESD Interface Capability for HBM Standards
- MIL STD 3015.7.................................................15kV
- IEC 61000-4-2, Direct Discharge,
- Single Input .......................................... 4kV (Level 2)
-Two Inputs in Parallel ............................ 8kV (Level 4)
- IEC 61000-4-2, Air Discharge...............15kV (Level 4)
• High Peak Current Capability
Functional Block Diagram
V+
IN
V-
8
1
4
- IEC 61000-4-5 (8/20µs)....................................... 3A
- Single Pulse, 100µs Pulse Width........................ 2A
- Single Pulse, 4µs Pulse Width............................ 5A
• Designed to Provide Over-Voltage Protection
- Single-Ended Voltage Range to ........................ +30V
- Differential Voltage Range to ............................ 15V
• Fast Switching.............................................2ns RiseTime
• Low Input Leakages............................1nA at 25ºCTypical
• Low Input Capacitance.....................................3pFTypical
• An Array of 6 SCR/Diode Pairs
3, 5-7
IN
2
IN
• OperatingTemperature Range....................-40ºC to 105ºC
Additional Information
Applications
• Microprocessor/Logic
Input Protection
• Analog Device Input
Protection
• Data Bus Protection
• Voltage Clamp
Resources
Datasheet
Samples
© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13
TVS Diode Arrays (SPA® Diodes)
General Purpose ESD Protection - SP721 Series
Absolute Maximum Ratings
Thermal Information
Parameter
Rating
Units
Parameter
Thermal Resistance (Typical, Note 1)
PDIP Package
Rating
θJA
Units
oC/W
oC/W
oC/W
oC
Continuous Supply Voltage, (V+) - (V-)
Forward Peak Current, IIN to VCC, IIN to GND
(Refer to Figure 5)
+35
V
160
2, 100µs
A
SOIC Package
170
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational sections of this
specification is not implied.
Maximum StorageTemperature Range
Maximum JunctionTemperature (Plastic
Package)
Maximum LeadTemperature
(Soldering 20-40s)(SOIC LeadTips Only)
-65 to 150
150
260
oC
oC
Note:
ESD Ratings and Capability (Figure 1, Table 1)
Load Dump and Reverse Battery (Note 2)
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Characteristics TA = -40oC to 105oC, VIN = 0.5VCC , Unless Otherwise Specified
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Operating Voltage Range,
VSUPPLY
-
2 to 30
-
V
VSUPPLY = [(V+) - (V-)]
Forward Voltage Drop
IN to V-
VFWDL
VFWDH
IIN
IIN = 1A (Peak Pulse)
-
2
2
-
V
V
IN to V+
-
-
Input Leakage Current
Quiescent Supply Current
Equivalent SCR ONThreshold
Equivalent SCR ON Resistance
Input Capacitance
-20
5
+20
nA
nA
V
IQUIESCENT
-
-
-
-
-
50
1.1
1
200
Note 3
-
-
-
-
VFWD/IFWD; Note 3
Ω
CIN
tON
3
pF
ns
Input Switching Speed
2
Notes:
2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- Pins are connected to het same
supply voltage source as the device or control line under protection, a current limiti ng resistor should be connected in series between the external supply and the SP721 supply pins to
limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger romf the V+ and V- Pins to ground are recommended.
3. Refer to the Figure 3 graph for definitions of equivalent “SCR ONThreshold” and “SCR ON Resistance”. These characteristics are given here for thumb-rule nformation to determine peak
current and dissipation under EOS conditions.
Typical Application of the SP721
(Application as an Input Clamp for Over-voltage, Greater
than 1VBE Above V+ or less than -1VBE below V-)
+V
+V
CC
CC
INPUT
DRIVERS
OR
SIGNAL
SOURCES
LINEAR OR
DIGITAL IC
INTERFACE
TO +V
V+
IN 1 - 3
IN 5 - 7
CC
SP721
V-
SP721 INPUT PROTECTION CIRCUIT (1 OF 6 SHOWN)
© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13
TVS Diode Arrays (SPA® Diodes)
General Purpose ESD Protection - SP721 Series
ESD Capability
ESD capability is dependent on the application and defined
test standard.The evaluation results for various test
standards and methods based on Figure 1 are shown in
Table 1.
Figure 1: Electrostatic DischargeTest
R
D
R
1
For the “Modified”MIL-STD-3015.7 condition that is defined
as an “in-circuit” method of ESD testing, the V+ and V- pins
have a return path to ground and the SP721 ESD capability
is typically greater than 15kV from 100pF through 1.5kΩ.By
strict definition of MIL-STD-3015.7 using “pin-to-pin”device
testing, the ESD voltage capability is greater than 6kV.The
MIL-STD-3015.7 results were determined from AT&T ESD
Test Lab measurements.
CHARGE
SWITCH
DISCHARGE
SWITCH
C
D
IN
DUT
H.V.
SUPPLY
V
D
IEC 1000-4-2: R 50 to 100M
MIL-STD-3015.7: R 1 to 10M
1
1
The HBM capability to the IEC 61000-4-2 standard is
greater than 15kV for air discharge (Level 4) and greater
than 4kV for direct discharge (Level 2).Dual pin capability (2
adjacent pins in parallel) is well in excess of 8kV (Level 4).
Table 1: ESDTest Conditions
Standard
Type/Mode
Modified HBM
RD
CD
±±D
1.5kΩ 100pF 15kV
1.5kΩ 100pF 6kV
330Ω 150pF 15kV
MIL STD 3015.7
For ESD testing of the SP721 to EIAJ IC121 Machine
Model (MM) standard, the results are typically better than
1kV from 200pF with no series resistance.
Standard HBM
HBM, Air Discharge
HBM, Direct Discharge 330Ω 150pF 4kV
IEC 61000-4-2
EIAJ IC121
HBM, Direct Discharge,
330Ω 150pF 8kV
Two Parallel Input Pins
Machine Model
0kΩ 200pF 1kV
Figure 2: Low Current SCR ForwardVoltage Drop Curve
Figure 3: High Current SCR ForwardVoltage Drop Curve
2.5
100
TA = 25ºC
SINGLE PULSE
TA = 25ºC
SINGLE PULSE
2
80
1.5
1
60
40
20
0
I
FWD
EQUIV. SAT. ON
THRESHOLD ~ 1.1V
V
FWD
0.5
0
0
2
3
1
800
1000
1200
600
FORWARD SCTVOLTAGE DROP (V)
FORWARD SCRVOLTAGE DROP (mV)
© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13
TVS Diode Arrays (SPA® Diodes)
General Purpose ESD Protection - SP721 Series
PeakTransient Current Capability of the SP721
The peak transient current capability rises sharply as the
width of the current pulse narrows. Destructive testing
was done to fully evaluate the SP721’s ability to withstand
a wide range of peak current pulses vs time. The circuit
used to generate current pulses is shown in Figure 4.
Figure 4: Typical SP721 Peak CurrentTest Circuit
with aVariable PulseWidth Input
VARIABLE TIME DURATION
CURRENT PULSE GENERATOR
+
R
1
V
X
CURRENT
SENSE
-
The test circuit of Figure 4 is shown with a positive pulse
input. For a negative pulse input, the (-) current pulse input
goes to an SP721 ‘IN’ input pin and the (+) current pulse
input goes to the SP721 V- pin. The V+ to V- supply of the
SP721 must be allowed to float. (i.e., It is not tied to the
ground reference of the current pulse generator.) Figure
5 shows the point of overstress as defined by increased
leakage in excess of the data sheet published limits.
(-)
(+)
1
IN
IN
IN
V-
V+
IN
IN
IN
8
7
6
5
2
3
4
SP721
+
-
C1
VOLTAGE
PROBE
R
X
~ 10 TYPICAL
1
V
ADJ. 10V/ATYPICAL
The maximum peak input current capability is dependent
on the ambient temperature, improving as the temperature
is reduced. Peak current curves are shown for ambient
temperatures of 25ºC and 105ºC and a 15V power supply
condition. The safe operating range of the transient peak
current should be limited to no more than 75% of the
measured overstress level for any given pulse width as
shown in the curves of Figure 5.
C1 ~ 100 µF
Figure 5: SP721Typical Single Peak Current Pulse
Capability
Showing the Measured Point of Overstress in Amperes vs
pulse width time in milliseconds
7
CAUTION: SAFE OPERATING CONDITIONS LIMIT
6
5
4
3
2
1
0
THE MAXIMUM PEAK CURRENT FOR A GIVEN
PULSEWIDTHTO BE NO GREATERTHAN 75%
OFTHEVALUES SHOWN ON EACH CURVE.
V+TO V-SUPPLY = 15V
Note that adjacent input pins of the SP721 may be
paralleled to improve current (and ESD) capability. The
sustained peak current capability is increased to nearly
twice that of a single pin.
TA = 25°C
TA = 105°C
0.001
0.01
0.1
1
10
100
1000
PULSEWIDTHTIME (ms)
© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13
TVS Diode Arrays (SPA® Diodes)
General Purpose ESD Protection - SP721 Series
Soldering Parameters
Reflow Condition
-Temperature Min (Ts(min)
Pb – Free assembly
tP
TP
Critical Zone
TL to TP
)
150°C
Ramp-up
TL
TS(max)
Pre Heat -Temperature Max (Ts(max)
)
200°C
tL
-Time (min to max) (ts)
60 – 180 secs
Ramp-down
Preheat
Average ramp up rate (Liquidus) Temp
(TL) to peak
5°C/second max
5°C/second max
TS(min)
tS
TS(max) toTL - Ramp-up Rate
25
-Temperature (TL) (Liquidus) 217°C
time to peak temperature
Reflow
Time
-Temperature (tL)
60 – 150 seconds
260+0/-5 °C
PeakTemperature (TP)
Time within 5°C of actual peak
Temperature (tp)
20 – 40 seconds
Ramp-down Rate
5°C/second max
8 minutes Max.
260°C
Time 25°C to peakTemperature (TP)
Do not exceed
Package Dimensions — Dual-In-Line Plastic Packages (PDIP)
N
Package
PDIP
E1
INDEX
AREA
Pins
8 Lead Dual-in-Line
MS-001
1
2
3
N/2
JEDEC
-B-
-A-
Millimeters
Min Max
Inches
D
E
Notes
Min
-
Max
BASE
PLANE
A2
A
A
A1
A2
B
B1
C
D
D1
E
E1
e
eA
eB
L
-
5.33
-
0.210
-
4
4
-
-
8, 10
-
5
5
6
5
-
-C-
SEATING
PLANE
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
L
C
L
4.95
0.558
1.77
0.355
10.16
-
0.195
0.022
0.070
0.014
0.400
-
D1
B1
eA
A
A
1
D1
e
eC
C
B
eB
0.010 (0.25)
M
C
B S
Notes:
1. Controlling Dimensions: INCH. In case of conflict between English and Metric
dimensions, the inch dimensions control.
8.25
7. 11
0.325
0.280
2. Dimensioning and tolerancing per ANSIY14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No.
95.
6.10
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane
gauge GS-3.
6
7
4
9
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.010 inch (0.25mm).
-
10.92
3.81
-
0.430
0.150
2.93
0.115
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
N
8
8
7.
e B and eC are measured at the lead tips with the leads unconstrained. eC must be zero
or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall
not exceed 0.010 inch (0.25mm).
9. N is t he maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1
dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13
TVS Diode Arrays (SPA® Diodes)
General Purpose ESD Protection - SP721 Series
Package Dimensions — Small Outline Plastic Packages (SOIC)
N
Package
Pins
SOIC
8
INDEX
AREA
0.25(0.010)
M
B M
H
E
-B-
JEDEC
MS-012
Millimeters
Min
Inches
1
2
3
L
Notes
Max
1.75
0.25
0.51
0.25
5.00
4.00
Min
Max
SEATING PLANE
A
A
A1
B
C
D
E
1.35
0.10
0.33
0.19
4.80
3.80
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
-A-
o
h x 45
D
-C-
9
-
μ
e
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
A1
C
B
0.10(0.004)
3
4
-
0.25(0.010)
M C A M B S
Notes:
e
1.27 BSC
0.050 BSC
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication
Number 95.
H
h
5.80
0.25
0.40
6.20
0.50
1.27
0.2284
0.0099
0.016
0.2440
0.0196
0.050
-
2. Dimensioning and tolerancing per ANSIY14.5M-1982.
5
6
7
-
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash,
protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
L
4. Dimension “E” does not include interlead flash or protrusions. Inter-lead flash and
protrusions shall not exceed 0.25mm (0.010 inch) per side.
N
µ
8
8
5. The chamfer on the body is optional. If it is not present, a visual index feature must be
located within the crosshatched area.
0º
8º
0º
8º
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating
plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily
exact.
Part Numbering System
Product Characteristics
Lead Plating
MatteTin
Copper Alloy
SP 721
**
**
TVS Diode Arrays
Lead Material
G = Green
(SPA® Diodes)
P = Lead Free
Lead Coplanarity
Substitute Material
Body Material
0.004 inches (0.102mm)
Silicon
TG= Tape and Reel
Package
Series
AB = 8 Ld SOIC
AP = 8 Ld PDIP
Molded Epoxy
UL 94 V-0
Flammability
Ordering Information
Environmental
Part Number
Temp. Range (ºC)
Package
Marking
Min. Order
Informaton
Lead-free
Green
SP721APP
SP721ABG
-40 to 105
-40 to 105
8 Ld PDIP
8 Ld SOIC
SP721AP(P) 1
SP721A(B)G 2
2000
1960
8 Ld SOICTape
and Reel
SP721ABTG
-40 to 105
Green
SP721A(B)G 2
2500
Notes:
1. SP721AP(P) means device marking either SP721AP or SP721APP.
2. SP721A(B)G means device marking either SP721AG or SP721ABG which are good for types SP721ABG and SP721ABTG.
© 2013 Littelfuse, Inc.
Specifications are subject to change without notice.
Revised: 04/24/13
相关型号：
SP723AB
TVS Diode Arrays - Electronic Protection Array for ESD and Overvoltage Protection
LITTELFUSE
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