L21C11CMB25 [LOGIC]
Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24;
| 型号： | L21C11CMB25 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | Pipeline Register, 8-Bit, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24 CD 外围集成电路 |
| 文件： | 总5页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L21C11
8-bit Variable Length Shift Register
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The L21C11 is a high-speed, low
power CMOS variable length shift
register. It consists of a single 8-bit
wide, adjustable length shift regis-
ter. The shift register can be pro-
The Length Code (L3-0) controls the
number of delay stages applied to the
D7-0 inputs as shown in Table 1.
When the Length Code is 0, the input
is delayed by 1 clock period. When
❑ Variable Length 8-bit Wide Shift
Register
❑ Selectable Delay Length from 1 to
16 Stages
❑ Low Power CMOS Technology
❑ Replaces TRW/Raytheon TMC2111
❑ Load, Shift, and Hold Instructions
❑ Separate Data In and Data Out Pins
❑ DECC SMD No. 5962-96793
grammed to any length from 1 to 16 the Length Code is 1, the delay is 2
stages inclusive. The length of the
shift register is determined by the
Length Code (L3-0) as shown in
Table 1.
clock periods, and so forth. The
Length Code inputs are latched on the
rising edge of CLK. The Length Code
value may be changed at any time
without affecting the contents of
registers R1 through R15.
❑ Available 100% Screened to
The data input is applied to a chain
of registers which are clocked on the
rising edge of the CLK input. These
registers are numbered R1 through
R15. A multiplexer serves to route
the contents of any register, R1
through R15, or the data input, D7-0,
to the output register, denoted R16.
Note that the minimum-length path
from data input to output is through
R16, consisting of a single stage of
delay.
MIL-STD-883, Class B
❑ Package Styles Available:
• 24-pin Plastic DIP
• 24-pin Ceramic DIP
• 28-pin Plastic LCC, J-Lead
• 28-pin Ceramic LCC
L21C11 BLOCK DIAGRAM
R15
R14
R13
8
8
D7-0
Y7-0
R3
R2
R1
4
L3-0
CLK
TO ALL REGISTERS
OBSOLETE
Pipeline Registers
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L21C11
DEVICES INCORPORATED
8-bit Variable Length Shift Register
MAXIMUM RATINGS
TABLE 1. CONTROL ENCODING
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Length Code
Delay
L3
L2
L1
L0
Y7-0
Storagetemperature ....................................................... –65°C to +150°C
Operatingambienttemperature ....................................... –55°C to +125°C
VCC supply voltage with respect to ground ...................... –0.5 V to +7.0 V
Input signal with respect to ground................................... –3.0 V to +7.0 V
Signal applied to high impedance output .......................... –3.0 V to +7.0 V
Output current into low outputs ....................................................... 25 mA
Latchupcurrent .......................................................................... > 400 mA
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
9
OPERATING CONDITIONS
To meet specified electrical and switching characteristics
10
11
12
13
14
15
16
Mode
TemperatureRange
0°C to +70°C
Supply Voltage
Active Operation, Com.
Active Operation, Mil.
4.75 V £ VCC £ 5.25 V
4.50 V £ VCC £ 5.50 V
–55°Cto+125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
Min
Typ
Max Unit
VOH
VOL
VIH
Output High Voltage
VCC = Min., IOH = –12 mA
VCC = Min., IOL = 24 mA
2.4
V
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
0.5
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
Ground ≤ VIN ≤ VCC (Note 12)
(Notes 5, 6)
±20
µA
ICC1
ICC2
VCC Current, Dynamic
VCC Current, Quiescent
10
20 mA
1.0 mA
(Note 7)
OBSOLETE
Pipeline Registers
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L21C11
DEVICES INCORPORATED
8-bit Variable Length Shift Register
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
L21C11–
20
25
15
Symbol Parameter
Min
Max
Min
Max
Min
Max
tPD
tPW
tSD
tHD
tSL
tHL
Output Delay
25
20
15
Clock Pulse Width
Data Setup Time
15
20
2
12
10
0
10
8
Data Hold Time
0
Length Code Setup Time
Length Code Hold Time
20
2
10
0
8
0
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
L21C11–
25
30
20
Symbol Parameter
Min
Max
Min
Max
Min
Max
tPD
tPW
tSD
tHD
tSL
tHL
Output Delay
30
25
20
Clock Pulse Width
Data Setup Time
15
25
2
12
10
2
12
10
0
Data Hold Time
Length Code Setup Time
Length Code Hold Time
25
2
10
2
10
0
SWITCHING WAVEFORMS
tSD
tSL
tHD
tHL
D7-0
L3-0
tPW
tPW
CLK
Y7-0
tPD
OBSOLETE
Pipeline Registers
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L21C11
DEVICES INCORPORATED
8-bit Variable Length Shift Register
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
11. For the tENA test, the transition is
ation of these products at values be- output reference levels of 1.5 V (except
yond those indicated in the Operating
with datasheet loads. For the tDIS test,
the transition is measured to the
tDIS test), and input levels of nominally
Conditions table is not implied. Expo- 0 to 3.0 V. Output loading may be a ±200mV level from the measured
sure to maximum rating conditions for resistive divider which provides for steady-state output voltage with
extended periods may affect reliability.
±10mA loads. The balancing volt-
age, VTH, is set at 3.5 V for Z-to-0
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec-
ification include internal circuitry de-
signedto protect the chipfrom damag-
ing substrate injection currents and ac-
cumulations of static charge. Never-
theless, conventional precautions
should be observed during storage,
handling, and use of these circuits in This device has high-speed outputs ca-
order to avoid exposure to excessive pable of large instantaneous current
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
bridge with upper and lower current to-1 and 1-to-Z tests.
sources of IOH and IOL respectively,
12. These parameters are only tested at
and a balancing voltage of 1.5 V may be
the high temperature extreme, which is
used. Parasitic capacitance is 30 pF
the worst case for leakage current.
minimum, and may be distributed.
FIGURE A. OUTPUT LOADING CIRCUIT
electrical stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:
S1
DUT
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or above VCC
I
OL
V
TH
CL
I
OH
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
FIGURE B. THRESHOLD LEVELS
t
ENA
tDIS
tion will not be adversely affected, how-
ever, input current levels will be well in and the tester common, and device
should be installed between device VCC
OE
0
1.5 V
1.5 V
excess of 100 mA.
ground and tester common.
Z
Z
3.5V Vth
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
4. Actual test conditions may vary
b. Ground and VCC supply planes
from those designated but operation is must be brought directly to the DUT
guaranteed as specified. socket or contactor fingers.
V
OH*
1
0V Vth
VOL*
Measured VOL with IOH = –10mA and IOL = 10mA
V
OH* Measured VOH with IOH = –10mA and IOL = 10mA
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated
by:
compensateforinductivegroundand VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
2
NCV F
4
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements of all parts. Responses
from the internal circuitry are specified
from the point of view of the device.
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
OBSOLETE
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
Output delay, for example, is specified
as a maximum since worst-case opera-
tion of any device always provides data
within that time.
8. These parameters are guaranteed
but not 100% tested.
Pipeline Registers
03/04/99–LDS.21C11-E
4
L21C11
DEVICES INCORPORATED
8-bit Variable Length Shift Register
ORDERING INFORMATION
24-pin — 0.3" wide
28-pin
1
24
23
22
21
20
19
18
17
16
15
14
13
Y
Y
Y
Y
0
1
2
3
D
D
D
D
L
0
1
2
3
0
1
2
4
3
2
1
28 27 26
25
3
5
D
L
L
3
0
1
NC
4
6
24
23
22
21
20
19
L
2
3
5
L2
7
L
6
L3
L
Top
View
8
V
CC
GND
GND
GND
NC
7
GND
GND
VCC
9
CLK
8
CLK
10
11
D
4
9
Y
Y
Y
Y
4
5
6
7
D4
D5
D6
D7
NC
10
11
12
12 13 14 15 16 17 18
Plastic DIP
(P2)
Ceramic DIP
(C1)
Plastic J-Lead Chip Carrier
(J4)
Ceramic Leadless
Chip Carrier (K1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
25 ns
20 ns
15 ns
L21C11PC25
L21C11PC20
L21C11PC15
L21C11JC25
L21C11JC20
L21C11JC15
–55°C to +125°C — COMMERCIAL SCREENING
L21C11CM30
30 ns
25 ns
20 ns
L21C11CM25
L21C11CM20
–55°C to +125°C — MIL-STD-883 COMPLIANT
30 ns
25 ns
20 ns
L21C11CMB30
L21C11CMB25
L21C11CMB20
L21C11KMB30
OBSOLETE
L21C11KMB25
L21C11KMB20
Pipeline Registers
03/04/99–LDS.21C11-E
5
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