L2340QC20G_技术文档

L2340

DEVICES INCORPORATED

Digital Synthesizer

L2340

Digital Synthesizer

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The L2340 is a digital synthesizer that selects the numeric format. A valid

❑ Digital Waveform Synthesis at

50 MHz

performs waveform synthesis, modu-

lation, and demodulation.

transformed result is seen at the

output after 22 clock cycles and will

continue upon every clock cycle

thereafter.

❑ 24-Bit Polar Phase Angle Accuracy

❑ User-selectableWaveformSynthesis,

Frequency Modulation, or Phase

Modulation.

The L2340 automatically generates

quadrature matched pairs of 16-bit

sine and cosine waves in DAC-

15-bit amplitude and 32-bit phase data

❑ Amplitude Input for Amplitude

compatible 16-bit offset binary format are input into the L2340 to produce an

with15-bit amplitude and 32-bit phase output of 16-bit rectangular data. The

Modulation and Gain Adjustment.

inputs.

user may select the data format to

either 16-bit offset binary or 15-bit

unsigned magnitude format. High

accuracy phase increment values with

minimal accumulation error is accom-

plished by use of a 32-bit phase

accumulator.

❑ Replaces TRW/Raytheon/Fairchild

TMC2340A

Output waveforms can be phase or

frequency modulated. Digital output

frequencies are restricted to the

Nyquist limit.

❑ 120-pin PQFP (RoHS compliant)

Functional Description

The phase accumulator structure

supports frequency or phase modula-

tion and is selected by ENP1-0 and

accumulator controls FM and PM.

The L2340 converts Polar (Phase and

Magnitude) data into Rectangular

(Cartesian) coordinates. The user

L2340 BLOCK DIAGRAM

ENA

15

AM14-0

OEI

2

ENP1-0

16

32

I

15-0

PH31-0

Digital

Synthesizer

OEQ

FM

PM

Q

15-0

OBIQ

CLK

Special Arithmetic Functions

08/16/2000–LDS.2340-E

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L2340

DEVICES INCORPORATED

Digital Synthesizer

Outputs

L2340 FUNCTIONAL BLOCK DIAGRAM

I15-0 — x-coordinate Data Output

AM14-0

ENA

PH31-0

ENP1-0

2

FM

PM

I15-0 is the 16-bit Cartesian x-coordi-

nate Data output port. When OEI is

HIGH, I15-0 is forced into the high-

impedance state. I15 is forced HIGH if

OBIQ is LOW.

15

32

M

C

AM

Q15-0 — y-coordinate Data Output

Q15-0 is the 16-bit Cartesian y-coordi-

nate Data output port. When OEQ is

HIGH, Q15-0 is forced into the high-

impedance state. Q15 is forced HIGH

if OBIQ is LOW.

32

PM

FM

32

24

Controls

15

ENA — Amplitude Modulation Data

Input Enable

When ENA is HIGH, AM is latched

into the input register on the rising

edge of clock. When ENA is LOW, the

value stored in the register is un-

changed.

*TRANSFORM

PROCESSOR

OBIQ

16

ENP1-0 — Phase Modulation Data Input

Control

OEI

OEQ

ENP1-0 is the 2-bit Phase Modulation

Data Input Control that determines

one of the four modes shown in Table

1. ‘M’ is the Modulation Register and

‘C’ is the Carrier Register as shown in

the Functional Block Diagram.

I

15-0

Q

15-0

*REQUIRES 18 CYCLES TO COMPLETE AND IS FULLY PIPELINED

SIGNAL DEFINITIONS

Power

Inputs

AM14-0 — Amplitude Modulation Data

Input

TABLE 1. REGISTER OPERATION

Vcc and GND

ENP1-0 Configuration

AM14-0 is the 15-bit Amplitude

Modulation Data input port. AM14-0

is latched on the rising edge of CLK.

+5V power supply. All pins must be

connected.

0 0

0 1

1 0

1 1

No registers enabled, current data held

M register input enabled, C data held

C register input enabled, M data held

M register = 0, C register input enabled

Clock

PH31-0 — Phase Angle Data Input

CLK — Master Clock

PH31-0 is the 32-bit Phase Angle Data

input port. Input phase accumulators

are loaded through this port into

registers enabled by ENP1-0. PH31-0 is

latched on the rising edge of CLK.

The rising edge of CLK strobes all

enabled registers.

TABLE 2. ACCUMULATOR CONTROL

FM PM Configuration

0

1

0

1

0

1

No accumulation (normal operation)

PM accumulator path enabled

FM accumulator path enabled

Logical OR of PM and FM (Nonsensical)

Special Arithmetic Functions

08/16/2000–LDS.2340-E

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L2340

DEVICES INCORPORATED

Digital Synthesizer

FM, PM — Frequency Modulation,

Phase Modulation Control

OBIQ — Data Input/Output Format

Select

OEQ — y-coordinate Data Output

Enable

FM and PM is the 2-bit Frequency

Modulation/Phase Modulation

Control that determines one of the

four modes shown in Table 2. When

full-scale is exceeded, the accumulator

will roll over correctly allowing

continuous phase accumulation

through 2π radians.

When OBIQ is HIGH, offset binary

format is selected. When OBIQ is

LOW, unsigned format is selected.

When OEQ is LOW, Q15-0 is enabled

for data output. When OEQ is HIGH,

Q15-0 is placed in a high-impedance

state.

OEI — x-coordinate Data Output

Enable

When OEI is LOW, I15-0 is enabled for

data output. When OEI is HIGH, I15-0

is placed in a high-impedance state.

FIGURE 1A. INPUT FORMATS

AM

PH

(RTP = 0)

Integer Unsigned Magnitude

14 13 12

2¹⁴2¹³2¹²

Fract. Unsigned Mag./Two's Comp.

2

1

0

31 30 29

*±2⁰2^–12^–2

2

1

0

2²2¹2⁰

2^–292^–302^–31

*±2⁰denotes two's complement sign or highest magnitude bit. Since phase angles are modulo 2π

and phase accumulator is modulo 2³², this bit may be regarded as ±π

.

FIGURE 1B. OUTPUT FORMATS

I

Q

Integer Unsigned Magnitude (OBIQ = 0)

14 13 12

2¹⁴2¹³2¹²

2

1

0

14 13 12

2¹⁴2¹³2¹²

2

1

0

2²2¹2⁰

Offset Binary (OBIQ = 1)

15 14 13

NS 2¹⁴2¹³

2

1

0

15 14 13

NS 2¹⁴2¹³

2

1

0

2²2¹2⁰

NS denotes negative sign. (i.e. '1' negates the number)

Special Arithmetic Functions

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L2340

DEVICES INCORPORATED

Digital Synthesizer

Circle Test

error will introduce noise when

performing waveform sythesis,

modulation, and demodulation.

The minimum theoretical angle

resolution that could be produced is

0.00175° when x = 7FFFH and y = 1H.

A 16-bit internal processor can

produce a minimum angle resolu-

tion of only 0.00549° and will not be

able to properly calculate the

theoretical minimum angle resolu-

tion. On the other hand, a 24-bit

internal processor can produce a

minimum angle resolution of

When performing a coordinate

transformation, inaccuracies are

introduced by a combination of

quantization and approximation

Data values for Figure 2 and Figure

3 are shown in Table 3. By looking

errors. The accuracy of a coordinate at these values, we observe the step

transformer is dependent on the

word length used for the input

variables, the word length used for

internal calculations, as well as the

number of iterations or steps per-

formed. Truncation errors are due

to the finite word length and ap-

proximation errors are due to the

finite number of iterations. For

example, in the case of performing a

polar-to-rectangular transformation,

the accuracy of the rotation will be

determined by how closely the input

rotation angle was approximated by

the summation of sub-rotation

angles.

resolution on a 16-bit internal

processor is not 1 unit in the x and

y. In most cases, the minimum step

resolution is 2 units in the x and y.

On the other hand, step resolution

on a 24-bit internal processor is 1

unit in the x and y thus resulting in

greater accuracy.

0.00002° and could therefore prop-

erly calculate the theoretical mini-

mum angle resolution.

FIGURE 2. CIRCLE TEST RESULT NEAR 45°(16-BIT INTERNAL PROCES-

SOR)

23200

23190

23180

23170

23160

23150

23140

In this study, we compare how

accurately a coordinate transformer

with a 16-bit internal processor

versus a 24-bit internal processor

can calculate all the coordinates of a

circle. By setting the radius to

7FFFH, θ is incremented using the

accumulator of the L2340 in steps of

0000 4000H until all the points of a

full circle are calculated into rectan-

gular coordinates.

Y

23140 23150 23160 23170 23180 23190 23200

X

The resulting rectangular coordi-

nates were plotted and graphed. A

graphical representation of the

resulting vectors for both 16-bit and

24-bit internal processors are com-

pared at 45°. Theoretically, a

perfect circle is the desired output

but when the resulting vectors from

a coordinate transformer with 16-bit

internal processor are graphed and

displayed as shown in Figure 2, we

see significant errors due to the

inherent properties of a digital

synthesizer. In comparison, the 24-

bit internal processor proves to be

significantly more accurate than a

16-bit internal processor due to

minimization of truncation errors.

In many applications, this margin of

FIGURE 3. CIRCLE TEST RESULT NEAR 45°(24-BIT INTERNAL PROCES-

SOR)

23200

23190

23180

23170

23160

23150

23140

Y

23140 23150 23160 23170 23180 23190 23200

X

Special Arithmetic Functions

08/16/2000–LDS.2340-E

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L2340

DEVICES INCORPORATED

Digital Synthesizer

TABLE 3. RESULTANT DATA VALUES OF CIRCLE TEST NEAR 45°

16-bit Internal Processor

24-bit Internal Processor

x

x (HEX)

5AA1

5A9F

5A9D

5A9B

5A98

5A96

5A93

5A91

5A8F

y

y (HEX)

5A63

5A65

5A67

5A69

5A6C

5A6E

5A70

5A72

5A74

x

x (HEX)

5A9F

5A9E

5A9D

5A9C

5A9B

5A9A

5A99

5A98

5A97

5A96

5A95

5A94

5A93

5A92

5A91

5A90

5A8F

y

y (HEX)

5A64

5A65

5A66

5A67

5A68

5A69

5A6A

5A6B

5A6C

5A6D

5A6E

5A6F

5A70

5A71

5A72

5A73

5A74

23201

23199

23197

23195

23192

23190

23187

23185

23183

23139

23141

23143

23145

23148

03148

23148

23150

23152

23154

23156

23199

23198

23197

23196

23195

23194

23193

23192

23191

23190

23189

23188

23187

23186

23185

23184

23183

23140

23141

23142

23143

23144

23145

23146

23147

23148

23149

23150

23151

23152

23153

23154

23155

23156

Special Arithmetic Functions

08/16/2000–LDS.2340-E

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L2340

DEVICES INCORPORATED

Digital Synthesizer

MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)

Storage temperature ........................................................................................................... –65°C to +150°C

Operating ambient temperature........................................................................................... –55°C to +125°C

VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V

Input signal with respect to ground ............................................................................... –0.5 V to VCC + 0.5 V

Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V

Output current into low outputs............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

OPERATING CONDITIONS To meet specified electrical and switching characteristics

Mode

Temperature Range (Ambient)

0°C to +70°C

Supply Voltage

4.75 V ≤ VCC ≤ 5.25 V

4.50 V ≤ VCC ≤ 5.50 V

Active Operation, Commercial

Active Operation, Military

–55°C to +125°C

ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

Symbol Parameter

Test Condition

Min

Typ

Max Unit

VOH

VOL

VIH

Output High Voltage

VCC = Min., IOH = –2.0 mA

VCC = Min., IOL = 4.0 mA

2.4

V

Output Low Voltage

Input High Voltage

Input Low Voltage

Input Current

0.4

VCC

0.8

V

2.0

0.0

VIL

(Note 3)

V

IIX

Ground ≤ VIN ≤ VCC (Note 12)

Ground ≤ VOUT ≤ VCC (Note 12)

(Notes 5, 6)

±10

µA

IOZ

Output Leakage Current

VCC Current, Dynamic

VCC Current, Quiescent

Input Capacitance

Output Capacitance

ICC1

ICC2

CIN

COUT

95 mA

(Note 7)

5

10

mA

pF

TA = 25°C, f = 1 MHz

Special Arithmetic Functions

08/16/2000–LDS.2340-E

6

L2340

DEVICES INCORPORATED

Digital Synthesizer

SWITCHING CHARACTERISTICS

COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)

L2340–

*

50

*

25

20

Symbol Parameter

Min

Max

Min

Max

Min

Max

tCYC

tPWL

Cycle Time

50

25

20

Clock Pulse Width Low

10

8

7

0

7

6

1

tPWH Clock Pulse Width High

tS

Input Setup Time

12

1

tH

Input Hold Time

tD

Output Delay

22

13

18

13

16

13

tENA

tDIS

Three-State Output Enable Delay (Note 11)

Three-State Output Disable Delay (Note 11)

MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)

L2340–

*

50

*

25

*

20

Symbol Parameter

Min

Max

Min

Max

Min

Max

tCYC

tPWL

Cycle Time

50

25

20

Clock Pulse Width Low

11

8

9

7

2

7

6

1

tPWH Clock Pulse Width High

tS

Input Setup Time

13

2

tH

Input Hold Time

tD

Output Delay

25

15

20

14

18

13

tENA

tDIS

Three-State Output Enable Delay (Note 11)

Three-State Output Disable Delay (Note 11)

*DISCONTINUED SPEED

GRADE

Special Arithmetic Functions

08/16/2000–LDS.2340-E

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L2340

DEVICES INCORPORATED

Digital Synthesizer

SWITCHING WAVEFORMS:

NO ACCUMULATION

0

1

2

3

22

23

24

CLK

t

H

t

PWL

tS

tPWH

OBIQ

tCYC

00

EN

A

00

EN

B

00

EN

C

FM, PM

ENA

ENP1-0

AM14-0

PH31-0

tD

I15-0

f(A)

f(B)

Q

15-0

SWITCHING WAVEFORMS:

PHASE MODULATION

0

1

2

3

4

22

23

24

25

CLK

OBIQ

00

01

FM, PM

ENA

R

AM14-0

10

01

I

01

J

01

K

01

L

ENP1-0

C

PH31-0

I15-0

C + I

2C + J

3C + K

4C + L

Q

15-0

Special Arithmetic Functions

08/16/2000–LDS.2340-E

8

L2340

DEVICES INCORPORATED

Digital Synthesizer

NOTES

1. Maximum Ratings indicate stress 9. AC specifications are tested with

11. For the tENA test, the transition is

specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point

ation of these products at values be- output reference levels of 1.5 V (except

yond those indicated in the Operating

with datasheet loads. For the tDIS test,

the transition is measured to the

tDIS test), and input levels of nominally

Conditions table is not implied. Expo- 0 to 3.0 V. Output loading may be a ±200mV level from the measured

sure to maximum rating conditions for resistive divider which provides for steady-state output voltage with

extended periods may affect reliability.

±10mA loads. The balancing volt-

age, VTH, is set at 3.5 V for Z-to-0

specified IOH and IOL at an output

voltage of VOH min and VOL max

2. The products described by this spec-

ification include internal circuitry de-

signedto protect the chipfrom damag-

ing substrate injection currents and ac-

cumulations of static charge. Never-

theless, conventional precautions

should be observed during storage,

handling, and use of these circuits in This device has high-speed outputs ca-

order to avoid exposure to excessive pable of large instantaneous current

respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-

bridge with upper and lower current to-1 and 1-to-Z tests.

sources of IOH and IOL respectively,

12. These parameters are only tested at

and a balancing voltage of 1.5 V may be

the high temperature extreme, which is

used. Parasitic capacitance is 30 pF

the worst case for leakage current.

minimum, and may be distributed.

FIGURE A. OUTPUT LOADING CIRCUIT

electrical stress values.

pulses and fast turn-on/turn-off times.

Asaresult, caremustbeexercisedinthe

testing of this device. The following

measures are recommended:

S1

DUT

3. This device provides hard clamping

of transient undershoot and overshoot.

Input levels below ground or above

VCC will be clamped beginning at –

I

OL

V

TH

CL

I

OH

a. A 0.1 µF ceramic capacitor should be

0.6 V and VCC + 0.6 V. The device can installed between VCC and Ground

withstand indefinite operation with in- leads as close to the Device Under Test

puts in the range of –0.5 V to +7.0 V. (DUT) as possible. Similar capacitors

FIGURE B. THRESHOLD LEVELS

t

ENA

tDIS

Device operation will not be adversely

affected, however, input current levels and the tester common, and device

should be installed between device VCC

OE

0

1.5 V

will be well in excess of 100 mA.

ground and tester common.

Z

3.5V Vth

1.5 V

V

OL*

0.2 V

0

1

Z

4. Actual test conditions may vary

b. Ground and VCC supply planes

from those designated but operation is must be brought directly to the DUT

guaranteed as specified. socket or contactor fingers.

V

OH*

1

0V Vth

VOL*

Measured VOL with IOH = –10mA and IOL = 10mA

V

OH* Measured VOH with IOH = –10mA and IOL = 10mA

5. Supplycurrentforagivenapplication c. Input voltages should be adjusted to

can be accurately approximated by:

compensateforinductivegroundand VCC

noise to maintain required DUT input

levels relative to the DUT ground pin.

2

NCV F

4

where

10. Each parameter is shown as a min-

imum or maximum value. Input re-

quirements are specified from the point

of view of the external system driving

the chip. Setup time, for example, is

specified as a minimum since the exter-

nal system must supply at least that

much time to meet the worst-case re-

quirementsofallparts. Responsesfrom

the internal circuitry are specified from

the point of view of the device. Output

delay, for example, is specified as a

maximumsinceworst-caseoperationof

anydevicealwaysprovidesdatawithin

that time.

N = total number of device outputs

C = capacitive load per output

V = supply voltage

F = clock frequency

6. Tested with all outputs changing ev-

ery cycle and no load, at a 20 MHz clock

rate.

7. Tested with all inputs within 0.1 V of

VCC or Ground, no load.

8. These parameters are guaranteed

but not 100% tested.

Special Arithmetic Functions

08/16/2000–LDS.2340-E

9

L2340

DEVICES INCORPORATED

Digital Synthesizer

ORDERING INFORMATION

120-pin

V

Q

GND

Q

CC

1

2

3

4

5

6

7

8

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

I

10

11

4

3

GND

I

V

I

GND

OEI

V

GND

AM14

AM13

GND

AM12

AM11

AM10

AM

12

13

14

2

1

0

CC

VCC

15

OEQ

GND

CLK

GND

OBIQ

ENP

GND

ENP

PM

FM

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

CC

0

Top

View

1

9

8

7

6

V

CC

PH

0

1

2

3

4

5

6

PH

GND

PH

GND

AM

GND

AM

5

4

3

2

7

AM

V

1

8

CC

Plastic Quad Flatpack

(Q1)

Speed

0°C to +70°C — COMMERCIAL SCREENING

20 ns

L2340QC20, L2340QC20G

Special Arithmetic Functions

08/16/2000–LDS.2340-E

10

L2340

DEVICES INCORPORATED

Digital Synthesizer

ORDERING INFORMATION

1

2

3

4

5

6

7

8

9

10

11

12

13

120-pin

A

B

C

D

E

F

Q

5

3

1

Q

7

4

2

0

Q

8

6

Q

10

Q

12

11

Q

14

Q

15

I

0

1

I

2

3

I

4

5

I

6

7

I

8

9

I

10

12

13

15

Q

9

Q

13 GND

VCC GND GND

V

CC GND

V

CC GND GND

VCC

I

11

14

OEQ

GND

KEY

GND GND

V

CC

V

CC GND OEI

CC GND AM14

Top View

OBIQ GND CLK

V

Through Package

G

H

J

ENP

1

ENP

FM

0

GND

GND AM12 AM13

(i.e., Component Side Pinout)

PM

VCC

AM

9

AM10 AM11

PH

0

PH

1

PH

3

GND AM

7

5

3

1

AM

8

6

4

2

0

K

L

2

4

GND

GND AM

5

6

8

7

9

VCC YPI14

V

CC GND

V

CC PH27 PH31

VCC AM

M

N

PH11 PH13 PH16 PH18 PH20 PH23 PH25 PH28 ENA AM

PH10 PH12 PH15 PH17 PH19 PH21 PH22 PH24 PH26 PH29 PH30 AM

Discontinued Package

Ceramic Pin Grid Array

(G4)

Speed

0°C to +70°C — COMMERCIAL SCREENING

–55°C to +125°C — COMMERCIAL SCREENING

–55°C to +125°C — MIL-STD-883 COMPLIANT

Special Arithmetic Functions

08/16/2000–LDS.2340-E

11


型号：	L2340QC20G
厂家：	LOGIC DEVICES INCORPORATED
描述：	Coordinate Transform Processor, CMOS, PQFP120, ROHS COMPLIANT, PLASTIC, QFP-120 外围集成电路
文件：	总11页 (文件大小：212K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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