L29C525 [LOGIC]

Dual Pipeline Register; 双管道注册


型号：	L29C525
厂家：	LOGIC DEVICES INCORPORATED
描述：	Dual Pipeline Register 双管道注册
文件：	总6页 (文件大小：173K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L29C525

DEVICES INCORPORATED

Dual Pipeline Register

L29C525

Dual Pipeline Register

DEVICES INCORPORATED

FEATURES

DESCRIPTION

The L29C525 is a high-speed, low

power CMOS pipeline register. It is

Instruction I1-0 = 01 (Push B) acts

similarly to the Push A and B

pin-for-pin compatible with the AMD instruction, except that only the B side

Am29525. The L29C525 can be registers are shifted. The input data is

configured as two independent 8-level applied to register B0, and the

❑ Dual 8-Deep Pipeline Register

❑ Configurable to Single 16-Deep

❑ Low Power CMOS Technology

❑ Replaces AMD Am29525

❑ Load, Shift, and Hold Instructions

❑ Separate Data In and Data Out Pins

❑ Three-State Outputs

pipelines or as a single 16-level

contents of register B7 are lost. The

contents of the A side registers are

unaffected. Instruction I1-0 = 10 (Push

A) is identical to the Push B

instruction, except that the A side

registers are shifted and the B side

registers are unaffected.

pipeline. The configuration imple-

mented is determined by the instruc-

tion code (I1-0) as shown in Table 2.

❑ Package Styles Available:

• 28-pin Plastic DIP

The I1-0 instruction code controls the

internal routing of data and loading of

each register. For instruction I1-0 = 00

(Push A and B), data applied at the

D7-0 inputs is latched into register A0

on the rising edge of CLK. The

contents of A0 simultaneously move

to register A1, A1 moves to A2, and so

on. The contents of register A7 are

wrapped back to register B0. The

registers on the B side are similarly

shifted, with the contents of register

B7 lost.

• 28-pin Plastic LCC, J-Lead

Instruction I1-0 = 11 (Hold) causes no

internal data movement. It is equiva-

lent to preventing the application of a

clock edge to any internal register.

The contents of any of the registers is

selectable at the output through the

use of the S3-0 control inputs. The

independence of the I and S control

lines allows simultaneous reading and

writing. Encoding for the S3-0 controls

is given in Table 3.

L29C525 BLOCK DIAGRAM

7-0

1-0

CLK

7-0

3-0

Pipeline Registers

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L29C525

DEVICES INCORPORATED

Dual Pipeline Register

TABLE 1. REGISTER LOAD OPERATIONS

Single 16 Level

Dual 8 Level

Push A

Push A and B

Push B

Hold All Registers

HOLD

TABLE 2. INSTRUCTION SET

Inputs

TABLE 3. OUTPUT SELECT

Y7-0

Mnemonics

Shift

Description

Push A and B

Push B

LDB

LDA

Push A

HLD

Hold All Registers

Pipeline Registers

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L29C525

DEVICES INCORPORATED

Dual Pipeline Register

MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)

Storage temperature ........................................................................................................... –65°C to +150°C

Operating ambient temperature........................................................................................... –55°C to +125°C

VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V

Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V

Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V

Output current into low outputs............................................................................................................. 25 mA

Latchup current ............................................................................................................................... > 400 mA

OPERATING CONDITIONS To meet specified electrical and switching characteristics

Mode

Temperature Range (Ambient)

0°C to +70°C

Supply Voltage

4.75 V ≤ VCC ≤ 5.25 V

4.50 V ≤ VCC ≤ 5.50 V

Active Operation, Commercial

Active Operation, Military

–55°C to +125°C

ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

Symbol Parameter

Test Condition

Min

Typ

Max Unit

VOH

VOL

VIH

Output High Voltage

VCC = Min., IOH = –12 mA

VCC = Min., IOL = 24 mA

2.4

Output Low Voltage

Input High Voltage

Input Low Voltage

0.5

VCC

0.8

2.0

0.0

VIL

(Note 3)

IIX

Input Current

Ground ≤ VIN ≤ VCC (Note 12)

Ground ≤ VOUT ≤ VCC (Note 12)

(Notes 5, 6)

±20

µA

IOZ

ICC1

ICC2

Output Leakage Current

VCC Current, Dynamic

VCC Current, Quiescent

35 mA

1.0 mA

(Note 7)

Pipeline Registers

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L29C525

DEVICES INCORPORATED

Dual Pipeline Register

SWITCHING CHARACTERISTICS

COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)

L29C525–

Symbol Parameter

Min

Max

Min

Max

tPD

Clock to Output Delay

tSEL

tPW

tSD

tHD

tSI

Select to Output Delay

Clock Pulse Width

Data Setup Time

Data Hold Time

Instruction Setup Time

tHI

Instruction Hold Time

tENA

tDIS

Three-State Output Enable Delay (Note 11)

Three-State Output Disable Delay (Note 11)

MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)

L29C525–

20*

Symbol Parameter

Min

Max

Min

Max

tPD

Clock to Output Delay

tSEL

tPW

tSD

tHD

tSI

Select to Output Delay

Clock Pulse Width

Data Setup Time

Data Hold Time

Instruction Setup Time

tHI

Instruction Hold Time

tENA

tDIS

Three-State Output Enable Delay (Note 11)

Three-State Output Disable Delay (Note 11)

SWITCHING WAVEFORMS

tHD

7-0

1-0

tHI

tPW

CLK

tPD

S3-0

SEL

DIS

tENA

HIGH IMPEDANCE

Y7-0

*DISCONTINUED SPEED GRADE

Pipeline Registers

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L29C525

DEVICES INCORPORATED

Dual Pipeline Register

NOTES

1. Maximum Ratings indicate stress 9. AC specifications are tested with

11. For the tENA test, the transition is

specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point

ationoftheseproductsatvaluesbeyond output reference levels of 1.5 V (except

those indicated in the Operating Condi-

with datasheet loads. For the tDIS test,

the transition is measured to the

tDIS test), and input levels of nominally

tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200mV level from the measured

maximum rating conditions for ex- resistive divider which provides for steady-state output voltage with

tended periods may affect reliability.

±10mA loads. The balancing volt-

age, VTH, is set at 3.5 V for Z-to-0

specified IOH and IOL at an output

voltage of VOH min and VOL max

2. The products described by this spec-

ification include internal circuitry de-

signedto protect the chipfrom damag-

ing substrate injection currents and ac-

cumulationsofstaticcharge. Neverthe-

less, conventional precautions should

be observed during storage, handling,

and use of these circuits in order to This device has high-speed outputs ca-

avoid exposure to excessive electrical pable of large instantaneous current

respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-

bridge with upper and lower current to-1 and 1-to-Z tests.

sources of IOH and IOL respectively,

12. These parameters are only tested at

and a balancing voltage of 1.5 V may be

the high temperature extreme, which is

used. Parasitic capacitance is 30 pF

the worst case for leakage current.

minimum, and may be distributed.

FIGURE A. OUTPUT LOADING CIRCUIT

stress values.

pulses and fast turn-on/turn-off times.

Asaresult, caremustbeexercisedinthe

testing of this device. The following

measures are recommended:

DUT

3. Thisdeviceprovideshardclampingof

transient undershoot and overshoot. In-

put levels below ground or above VCC

will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be

VCC + 0.6 V. The device can withstand installed between VCC and Ground

indefinite operation with inputs in the leads as close to the Device Under Test

range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors

FIGURE B. THRESHOLD LEVELS

ENA

tDIS

tion will not be adversely affected, how-

ever, input current levels will be well in and the tester common, and device

should be installed between device VCC

1.5 V

excess of 100 mA.

ground and tester common.

3.5V Vth

1.5 V

OL*

0.2 V

4. Actualtestconditionsmayvaryfrom

b. Ground and VCC supply planes

those designated but operation is guar- must be brought directly to the DUT

anteed as specified. socket or contactor fingers.

OH*

0V Vth

VOL

* Measured VOL with IOH = –10mA and IOL = 10mA

VOH*

Measured VOH with IOH = –10mA and IOL = 10mA

5. Supply current for a given applica- c. Input voltages should be adjusted to

tioncanbeaccuratelyapproximatedby:

compensateforinductivegroundand VCC

noise to maintain required DUT input

levels relative to the DUT ground pin.

NCV F

where

10. Each parameter is shown as a min-

imum or maximum value. Input re-

quirements are specified from the point

of view of the external system driving

the chip. Setup time, for example, is

specified as a minimum since the exter-

nal system must supply at least that

much time to meet the worst-case re-

quirementsofallparts. Responsesfrom

the internal circuitry are specified from

the point of view of the device. Output

delay, for example, is specified as a

maximumsinceworst-caseoperationof

anydevicealwaysprovidesdatawithin

that time.

N = total number of device outputs

C = capacitive load per output

V = supply voltage

F = clock frequency

6. Tested with all outputs changing ev-

ery cycle and no load, at a 5 MHz clock

rate.

7. Tested with all inputs within 0.1 V of

VCC or Ground, no load.

8. These parameters are guaranteed

but not 100% tested.

Pipeline Registers

03/32/2000–LDS.29C525-G

L29C525

DEVICES INCORPORATED

Dual Pipeline Register

ORDERING INFORMATION

28-pin — 0.3" wide

28-pin

28 27 26

Top

View

VCC

GND

VCC

GND

12 13 14 15 16 17 18

CLK

Plastic DIP

(P10)

Plastic J-Lead Chip Carrier

(J4)

Speed

0°C to +70°C — COMMERCIAL SCREENING

20 ns

15 ns

L29C525PC20

L29C525JC20

L29C525JC15

L29C525PC15

–55°C to +125°C — COMMERCIAL SCREENING

–55°C to +125°C — MIL-STD-883 COMPLIANT

Pipeline Registers

03/27/2000–LDS.29C525-G

L29C525 [LOGIC]

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