L7710QI12 [LOGIC]
FFT Processor, 16-Bit, CMOS, PQFP144, PLASTIC, QFP-144;
| 型号： | L7710QI12 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | FFT Processor, 16-Bit, CMOS, PQFP144, PLASTIC, QFP-144 时钟 外围集成电路 |
| 文件： | 总13页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
L7710 - DragonFly
High-Speed FFT Processor
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The L7710 is a high-speed Fast Fourier averaging of the output. 20-bit block
❑ 100 MHz Operation
❑ 3.3 Volt Power Supply
❑ 5 Volt Tolerant I/ O
❑ Computes up to a 1024 Point
Complex FFT in 18 µs*, the fastest
single-chip 1K Complex FFT
compute time yet to date!
Transform Processor. The L7710
allows extremely fast FFT computa-
tions to take place within a single
monolithic device. All data buffering
and working storage required for up
to a 1024 point complex FFT operation
are on-chip. This eliminates the need
for expensive, high-speed external
memories, while decreasing internal
computation time.
floating point precision is achieved
with internal scaling logic. Exact
specified scaling is also an option
through the use of a scaling register.
The core transform processor is
comprised of a “Dragonfly” processor
which computes 4-point complex
transforms in approximately 10 nsec
when the pipeline is fully loaded. It
consists of several multipliers and
adders in parallel to achieve this high,
sustained computation throughput
rate. Input data and twiddle factor
coefficients are presented to the
processor core every 10 nsec and
output is clocked out at the same rate
giving the processing performances
indicated.
❑ 4 Programmable Complex FFT
Point Sizes: 16 Point (240 ns), 64
Point (1.2 µs), 256 Point (3.4 µs),
and 1024 Point (18 µs)**
The interface to the device appears to
the user as if it were a synchronous
SRAM with all appropriate signaling.
❑ Standby Modes result in Significant
Power Savings while simultaneously
Retaining Internal Memory Data
❑ Supports Both Forward and Inverse
There are several programmable
options available on the device to
perform complex input data
Fast Fourier Transforms
❑ Configurable as a FIR Filter with
up to 1024 Complex Taps
windowing, forward/ inverse transform,
transform overlap, and exponential
❑ Device Contains Seven Built-In
Windowing Functions in ROM
L7710 BLOCK DIAGRAM
❑ Window Buffer (2K x 16-bit) Enables
Users to Program their own Complex
Window Functions through
Independent Address and Data
Input Lines
CB
FILT
FF
EF
DRD/DWE
❑ 16-bit Fixed Point Data Precision
(96 dB Dynamic Range) on Output
with 20-bit Internal Computation
Precision
WRD/WWE
16
DIN15-0
16
WIN15-0
11
16
DOUT15-0
AIN10-0
2
CACC1-0
❑ 224K-bit Internal RAM
❑ 1.2M-bit Internal Function ROM
❑ Package Styles Available:
• 144-pin Plastic Quad Flatpack
• 144-pin Flatpack
11
CTM
2
OVC1-0
ADOUT10-0
TEN
High-Speed
FFT
Processor
ORD/OWE
OE
XYMODE
3
WD2-0
SZ1-0
INV
2
EOT
DBO
AVG
SCTRL
HOLD
OVF
PRELIMINARY
STDBY
OCLK
*
1024 Complex FFT Computation time based on
CE
RESET
CPINS
PLL1-0
XY Mode with 25% Input Overlap. 1024
Complex FFT with No Overlap and Averaged
Linear or Decibel Power is computed in 24 µs.
ACOP
2
** All Computation times based on XY Mode with
25% Input Overlap.
CLK
Logic Products
06/25/98–LDS.7710-PRE.A
1
L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
Some applications of the L7710 in the
telecommunication field are: Wireless
Base Stations, Satellite Communica-
tions, Software Defined Radios, Cable
Modems and OFDM Applications;
while some sample instrumentation
applications are: Digital Spectrum
Analyzers, Modulation Analyzers,
and Distortion Analyzers.
FIGURE 1. INPUT AND WINDOW DATA FORMATS
Input Data Window Data
15 14 13
2
1
0
15 14 13
–215 214 213
2
1
0
–215 214 213
(Sign)
22 21 20
22 21 20
(Sign)
FIGURE 2. INPUT AND WINDOW ADDRESS FORMATS
SIGNAL DEFINITIONS
Power
Input Data Address
Window Data Address
10 0
10
9
8
2
1
0
9
8
2
1
Vcc and GND
210 29 28
22 21 20
210 29 28
22 21 20
+3.3 V power supply. All pins must
be connected.
Clock
FIGURE 3. DATA OUTPUT FORMATS
CLK — Master Clock
Real/Imaginary Mode
XY Mode (Averaged)
The rising edge of CLK strobes all
enabled registers and input memory
latches.
15 14 13
2
1
0
15 14 13
2
1
0
–215 214 213
22 21 20
–215 214 213
22 21 20
(Sign)
(Sign)
OCLK — Output Clock
The rising edge of OCLK strobes the
output buffer memory and the following
flags: EF, OVF and EOT.
Linear Power Mode
Averaged Linear Power Mode
14 13 12
214 213 212
2
1
0
14 13 12
214 213 212
2
1
0
22 21 20
22 21 20
Inputs
DIN15-0 — Data Input
DIN15-0 is the 16-bit registered data
input port. This input port is actually
bidirectional. Depending on the value
present on CACC1-0 and DRD/ DWE,
this port may act as an output port.
Data is latched on the rising edge of
CLK, provided DRD/ DWE is held
LOW. The data format is two’s
complement.
Decibel Mode
Averaged Decibel Mode
15 14 13
-215 214 213
2
1
0
15 14 13
2
1
0
22 21 20
-215 214 213
22 21 20
(Sign)
(Sign)
WIN15-0 — Window Input
Outputs
WIN15-0 is the 16-bit registered data
input port. This input port is actually
bidirectional. Depending on the value
DOUT15-0 — Data Output
AIN10-0 — Data/Window Input Address
DOUT15-0 is the 16-bit registered data
output port. See Figure 3.
AIN10-0 is the input address bus for
PRELIMINARY
present on CACC1-0 and WRD/ WWE,
DIN15-0 and WIN15-0 and controlled
by CACC1-0. Refer to table 5.
this port may act as an output port.
Data is latched on the rising edge of
CLK, provided WRD/ WWE is held
LOW. The data format is two’s
complement.
ADOUT10-0 — Data Output Address
ADOUT10-0 provides address infor-
mation for DOUT15-0. This bus is
bidirectional. In Continuous Mode
(CTM=1), the LF7710 outputs data
Logic Products
06/25/98–LDS.7710-PRE.A
2
L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
TABLE 1. OVERLAP MODE
TABLE 5. ADDRESS LINE CONTROL (CTM = 0 & CB =0)
OVC1-0
0 0
Configuration
No Overlap
25 %
CACC1-0
Active Loading Location
Active Corresponding Data Bus
0 0
Control Register
WIN15-0
0 1
0 1
Window RAM
WIN15-0
1 0
50%
1 0
Data Input RAM
DIN15-0
1 1
75%
1 1
Data Input & Window RAM
DIN15-0 & WIN15-0
TABLE 2. WINDOW MODE
TABLE 6. ADDRESS LINE CONTROL (CTM = 1 & CB=0)
CACC1-0
Active Loading Location
Control Register
Window RAM
N/A
Active Corresponding Data Bus
WD2-0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Configuration
Rectangular Window
Bartlett
0 0
WIN15-0
WIN15-0
N/A
0 1
1 0
Hamming
1 1
Window RAM
WIN15-0
Hanning
Trapezoidal
Blackman-Harris
Welch
TABLE 7. BUFFER RESET (CB=1)
TABLE 8. STANDBY MODES
CACC1-0
0 0
Location to be Cleared
Control Register
Window RAM
STDBY HOLD
Operation
Normal Operation
Output Buffer Held
Soft Standby
Buffer
0
0
1
1
0
1
0
1
0 1
TABLE 3. PLL MODE
1 0
Input RAM
PLL1-0
Bus Options
1 1
Output RAM
Hard Standby
0 0
x1
x2
x3
x4
pulsed in Non-Continuous Mode or
the window stage of the next transform
is completed in Continuous Mode.
EF — Empty Flag
0 1
EF will go LOW indicating to the user
that the data output buffer is empty.
EF will be asserted at all other times.
EF will automatically become
1 0
1 1
OVF — Overflow Flag
When OVF goes HIGH, this is indicative
of an internal data overflow. Note:
OVF will not go HIGH if SCALE has
been set to the default mode, all zeros.
In this mode, the device performs
block floating point which acts as an
automatic internal scale to prevent
overflow. If SCALE is set to any value
other than 0, the user should be
monitor OVF.
TABLE 4. LENGTH CONTROL
deasserted upon system reset.
SZ1-0
0 0
Complex Transform Length
Controls
16
64
0 1
CTM — Continuous Transform Mode
1 0
256
1024
When CTM is LOW, Non-Continuous
Transform operation is possible.
When TEN is pulsed LOW, the
transform starts (or restarts if the
previous transform was in mid-
computation). When CTM is HIGH,
Continuous Transform Mode is
enabled, which places the device in
synchronous operation. While in
Continuous Transform Mode, the part
acts like a “Data Pump.” Data MUST
be made available on the input buffers
when expected and likewise, output
will be shifted out in a FIFO-like
1 1
output address information automati-
cally. However, should the user desire
to read out data from DOUT15-0 in any
order, they may present addresses to
ADOUT10-0, provided they are in
FF — Full Flag
FF will go LOW indicating to the user
PRELIMINARY
that the data input buffer is full. FF
Non-Continuous Mode (CTM=0).
will be asserted at all other times. FF
will automatically become asserted
upon system reset.
EOT — End of Transform
The EOT signal goes HIGH when the
transform has completed and goes
LOW again when either a new TEN is
Logic Products
06/25/98–LDS.7710-PRE.A
3
L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
TABLE 8. VALID COMBINATIONS OF OVERLAP MODES (OVC1-0) AND PLL MODES (PLL1-0) FOR CTM=1
Full Complex Transform
Real Transform
Imaginary Transform
OVC1-0 PLL1-0 Mode x1 (100 MHz) OVC1-0 PLL1-0 Mode x1 (100 MHz) OVC1-0 PLL1-0 Mode x1 (100 MHz)
00
01
10
11
Valid Operation
Valid Operation
Valid Operation
Valid Operation
00
01
10
11
Valid Operation
Valid Operation
Valid Operation
Valid Operation
00
01
10
11
Valid Operation
Valid Operation
Valid Operation
Valid Operation
OVC1-0 PLL1-0 Mode x2 (50 MHz)
OVC1-0 PLL1-0 Mode x2 (50 MHz)
OVC1-0 PLL1-0 Mode x2 (50 MHz)
00
01
10
11
Data Starvation
Data Starvation
Valid Operation
Valid Operation
00
01
10
11
Valid Operation
Valid Operation
Valid Operation
Valid Operation
00
01
10
11
Valid Operation
Valid Operation
Valid Operation
Valid Operation
OVC1-0 PLL1-0 Mode x3 (33 MHz)
OVC1-0 PLL1-0 Mode x3 (33 MHz)
OVC1-0 PLL1-0 Mode x3 (33 MHz)
00
01
10
11
Data Starvation
Data Starvation
Data Starvation
Valid Operation
00
01
10
11
Data Starvation
Data Starvation
Valid Operation
Valid Operation
00
01
10
11
Data Starvation
Data Starvation
Valid Operation
Valid Operation
OVC1-0 PLL1-0 Mode x4 (25 MHz)
OVC1-0 PLL1-0 Mode x4 (25 MHz)
OVC1-0 PLL1-0 Mode x4 (25 MHz)
00
01
10
11
Data Starvation
Data Starvation
Data Starvation
Valid Operation
00
01
10
11
Data Starvation
Data Starvation
Valid Operation
Valid Operation
00
01
10
11
Data Starvation
Data Starvation
Valid Operation
Valid Operation
autonomous fashion. Note: In either
mode, the user should follow the
recommended combinations of
Overlap Modes (OVC1-0) and PLL
Modes (PLL1-0) in order to avoid
unexpected data on the output. See
Table 8.
HOLD — Hold Output Buffer Data
DBO — Linear Power/dB Output
Holds output buffer contents steady
while HOLD is held HIGH. When
HOLD is held LOW, the output buffer LOW, Linear Power format is selected.
allows data to be changed. When the
device is in Standby Mode, the data in
all the buffers is static, regardless of
the status of HOLD. If HOLD and
STDBY are HIGH, the device is in a
“hard standby mode”. Refer to table 8
for standby modes.
When DBO is HIGH, dB Output
format is selected. When DBO is
See Table 9.
XYMODE — XY Mode
TEN — Transform Enable Control
When XYMODE is HIGH, the device
is in XY Mode. The output mode can
be either Real/ Imaginary or XY Mode
(Averaged), depending on the value
of AVG. If XYMODE is LOW the
device is in Power Mode. The output
can be in one of the following modes:
Linear Power, Decibel, Averaged
Linear Power, and Averaged Decibel
Power.
When the device is in Continous
Transform Mode (CTM=1), TEN
should be held LOW. When the device
is in Non-Continuous Mode (CTM=0),
TEN can be pulsed LOW to start a
PRELIMINARY
transform. Should TEN be pulsed
LOW in the middle of a transform
computation, the transform will restart.
SCTRL — Scale Control
When SCTRL is LOW, scaling is
automatically handled internally
through block floating point. When
SCTRL is HIGH, scaling is achieved
through the scaling registers and is
under user control.
Logic Products
06/25/98–LDS.7710-PRE.A
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L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
INV — Forward/Inverse Transform Control
Register 1, CACC1-0 should be set to
00. The value 001h would then be
loaded through AIN10-0. Data from
Control Register 1 would then be
made available at WIN15-0. Refer to
Tables 5-7 for CACC1-0 mapping. See
Figure 4 for the Control Register Map.
See Figures 5 and 6 for Control
FIGURE 4. CONTROL REGISTER
When INV is LOW, Forward Transform
is selected. When INV is HIGH, Inverse
Transform is selected. This signal is
internally automatically controlled
when the device is in Filter Mode.
MAP (CACC1-0=00)
XX
XX 7FFh
SZ1-0 — Complex Transform Length
XX
XX 004h
003h
Register 0 and 1 Internal Mapping.
ALPHA
SCALE
SZ1-0 is the 2-bit Transform Length
selector and is selected from the four
predefined configurations. See Table 4.
002h
CPINS — Control Pins
CR1
001h
CPINS changes control from the
external control pins to the control
registers. If CPINS is HIGH, control
of the device is determined by the
external control pins. If CPINS is LOW,
control of the device is determined by
the internal control registers.
CR0
000h
OVC1-0 — Overlap Control
15
0
OVC1-0 is the 2-bit Overlap Control
which determines the type of overlap
used and is selected from the four
predefined configurations. See Table 1.
AVG — Average Real and Imaginary
When AVG is enabled, Exponential
Window Averaging on Power is
performed. See Table 9.
PLL1-0 — PLL Mode
OE — Output Enable
PLL1-0 is the 2-bit PLL mode selector
and is selected from the four pre-
defined configurations. See Table 3.
Data is available on the output port
(DOUT15-0) on the falling edge of CLK
while OE is held LOW. When OE is
HIGH, DOUT15-0 is placed in a high-
impedance state. CLKOUT is not
affected by OE.
FILT — FFT/FIR Operation Mode
When FILT is held LOW, the device is
in FFT Mode. When FILT is held
HIGH, the device is in FIR Mode.
CACC1-0 — Control Access
CACC1-0 determines the active buffer
loading location (i.e. Control Register,
Window RAM and/ or Data Input
RAM) depending on the value of
CTM. It also determines the buffer
location to be cleared depending on
the value of CB. For instance, in order
for the user to read the Control
WD2-0 — Window Configuration
DRD/DWE — Data Read/Write Enable
WD2-0 is the 3-bit Window Configuration
mode select which determines the type
of Window used and is selected from
the seven predefined configurations
stored in the Window Configuration
ROM or user-definable Window RAM.
See Table 2.
If DRD/ DWE is held LOW while CE
is held LOW, data on DIN15-0 is written
to the corresponding location associ-
ated with CACC1-0 on the rising edge
of CLK. If DRD/ DWE is HIGH while
FIGURE 5. CONTROL REGISTER 0 MAPPING
0
0
EOT
13
OVF
12
INV
11
WD
2
WD
1
WD
0
FILT
7
AVG XYMODE DBO SCTRL HOLD TEN
CTM
0
15
14
10
9
8
6
5
4
3
2
1
RESERVED BITS: 15, 14
EOT AND OVF ARE ONLY READ-ONLY BITS, THE REST READ-WRITEABLE
FIGURE 6. CONTROL REGISTER 1 MAPPING
PRELIMINARY
0
0
0
0
0
0
PLL
1
PLL
0
0
7
0
6
OVC
1
OVC
0
0
3
0
2
SZ
1
SZ
0
0
15
14
13
12
11
10
9
8
5
4
1
RESERVED BITS: 15 - 10, 7, 6, 3, 2
ALL BITS ARE READ/WRITABLE
Logic Products
06/25/98–LDS.7710-PRE.A
5
L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
FIGURE 7. INPUT BUFFER
MEMORY MAP
FIGURE 8. WINDOW BUFFER
MEMORY MAP
FIGURE 9. OUTPUT BUFFER
MEMORY MAP FOR
XY MODE
I
1023
1023
1022
1022
7FFh
I
1023
1023
1022
1022
7FFh
(XYMODE=1)
R
I
R
I
I
R
I
R
1023
1023
1022
1022
7FFh
R
R
I
1
I
1
R1
R1
I
R
0
I
R
0
I
R
I
1
0
000h
0
000h
1
15
0
15
0
0
R0
000h
CE is LOW, DIN15-0 is placed in an
output mode in order to read data. If
CE is HIGH, DIN15-0 is tri-stated.
fact that FFT engine has been powered
down. The data in all the buffers is
static, regardless of the status of
HOLD. If both STDBY and HOLD are
held HIGH, additional power savings
is achieved by the powering down of
the PLL, or going into a “hard standby
mode”. To return from a the hard
standby state, the user must drop
HOLD to a logic LOW and wait at
least a tPLL time in order to allow the
PLL to restart before dropping
15
0
FIGURE 10. OUTPUT BUFFER
MEMORY MAP FOR
POWER MODE
WRD/WWE — Window Read/Write Enable
If WRD/ WWE is held LOW while CE
is held LOW, data on WIN15-0 is
(XYMODE=0)
written to the corresponding location
associated with CACC1-0 on the rising
edge of CLK. If WRD/ WWE is HIGH
while CE is LOW, DIN15-0 is placed in
an output mode in order to read data.
If CE is HIGH, DIN15-0 is tri-stated.
P1023
3FFh
P
P
P
1022
1021
1020
STDBY. Refer to table 8 for standby
modes.
CE — Chip Enable
P
P
P
P
3
2
1
0
ACOP — Automatic Continuous
Operation
If CE is LOW, DIN15-0 and WIN15-0
are active as either input or output
ports determined by DRD/ DWE and
WRD/ WWE. If CE is HIGH, both
ports are tri-stated. Only WIN15-0 is
affected when CTM=1.
The ACOP signal automatically
controls the FFT engine based on the
user read-rate of the output buffer
when in continous transfer mode.
ACOP allows the device to guarantee
succesive completed transforms
without loss of output data and user
intervention, i.e. HOLD and/ or
STDBY going high. When ACOP = 1
and CTM = 1, the output buffer will
not be written over until the empty
flag, EF, is asserted. However, the
000h
15
0
RESET — System Reset
CB — Clear Buffer
The RESET signal resets all pointers to
all buffers, however it does not reset
any RAM, with the exception of the
control registers. All values inside
Control Registers 0 and 1 are reset to
zero in addition to both the Alpha and
Scale Registers.
Clears the Input Buffer, Output
Buffer, Control Register or Window
Buffer to all zeros when pulsed HIGH
for one clock cycle depending on the
value present at CACC1-0. WC has no
effect. Refer to table 7 for buffer
PRELIMINARY
input buffer may go full, i.e. the FF
selection.
flag is asserted, waiting for the user to USER ACCESSIBLE RESOURCES
STDBY — Standby Mode
read the output buffer. The HOLD
signal is not necessary when ACOP
and CTM are active, except for
standby modes. ACOP is not valid
when CTM = 0.
Data I/O Interface Description
By asserting STDBY to HIGH, the
device is placed in a standby state.
Power consumption drops, due to the
When FILT is held LOW, the device is
in FFT Mode. When FILT is held
HIGH, the device is in FIR Mode.
Logic Products
06/25/98–LDS.7710-PRE.A
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L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
Real and imaginary data enter the
device through an “SRAM-style”
interface, which is synchronous with
the CLK signal. Input data (to both
the input and window buffers) is
clocked in on the rising edge of CLK
when both DRD/ DWE and WRD/
WWE are held LOW. Output is
according to the output mode selected Once data has been clocked into the
(see Figures 10 and 11). Output is
streamed through the use of an
onboard FIFO to the DOUT15-0 pins,
following an address present on
ADOUT10-0 for the given address
setup time and OE asserted LOW.
Illegal combinations of PLL Modes
device, a logic LOW on TEN pin will
start transform operations. Approxi-
mately 18 microseconds later (for a
1024 Point FFT), EOT will go HIGH
indicating results are available on the
output data bus. Addresses of desired
output locations are driven via an
external device (e.g. DSP or DMA
controller). Between EOT and the
next TEN assertion, new input data, as
clocked out on the falling edge of CLK and OVC Modes with CTM=1 are
while OE is held LOW, acting much
like a FIFO to the user.
shown in Table 8. EOT will be gener-
ated after the first output is received
into the internal output buffer. This is well as any new window data, can be
designed to prevent user access prior
to any post transform computations,
such as log or averaging operations.
Addresses of input data are automati-
cally generated in consideration of the
overlap mode.
entered into the device with timing
based on tCYC.
Continuous Transform Mode
In Continuous Transform Mode
(CTM=1), the device I/ O is clocked in
synchronism with the PLL mode
(PLL1-0) and the overlap mode (OVC1-0).
For example, if the PLL mode is x2
(PLL1-0=01), and overlap is in 50%
overlap (OVC1-0=10) and the clock
input is 50 MHz, then synchronous
The user must be aware that if the
overlap control is in any mode other
than (OVC10=00) then aged data
(located at lower addresses) is over-
written by more recent data prior to
EOT assertion. For example, in 25%
overlap mode (OVC10=01) and a 1024
point complex transform (SZ10=11);
real and imaginary points 768 and
higher (600h-7FFh) are copied to the
first 256 real and imaginary locations
of the buffer (000h-1FFh). (See Figure
7 for the Input Buffer Memory Map).
In this example, the user should start
addressing the most recent data
beginning at 200h (point 256 and
higher).
Non-Continuous Transform Mode
In non-continuous mode (CTM=0), the
data should be clocked into the device user has direct control over address-
at a 50 MHz input rate according to ing the input and output data. The
the input memory map and the size of user is free to place data anywhere in
the transform specified.
the 2K input memory map by writing
to its corresponding memory location
directly according the input buffer
memory map (See Figure 7). Data on
the DIN15-0 and WIN15-0 pins are
latched into the buffer memories via
the use of DRD/ DWE and WRD/
WWE along with CE. With CE held
LOW, DRD/ DWE or WRD/ WWE (or
both) are used to latch the data into
the corresponding internal SRAM
buffers at the address specified by the
individual address lines, AIN10-0.
There will be 2N (N is specified by
SZ1-0 in Table 4) locations which are
automatically sequenced for both
input and output, beginning with
zero, and appear at their respective
address lines. This allows the device
to be directly interfaced to a parallel
type A/ D converter at the input or to
a parallel DAC, Digital Signal Proces-
sor or DMA controller at the output.
Output data is memory mapped
Data I/O Interface Description
By setting CACC1-0 to 00 and CB to 0,
the window buffer is disabled and
causes the first four locations to be
treated as “configuration” registers.
Control Registers 0 and 1 are found in
the corresponding first two locations
000h and 001h (See Figure 4). Figures
5 and 6 show the formats of Control
Registers 1 and 2. Control Register 0
consists of 16 bits which are readable
and writable with the exception of
EOT which is read-only. Control
Register 1 also consists of 16-bits,
however the last 9 bits are reserved.
All 7 of the first bits are read/ writ-
able. See the Signal Definitions section
for descriptions of each bit.
TABLE 9. OUTPUT MODES FOR COMBINATIONS OF AVG, XYMODE AND DBO
AVG XYMODE DBO Output Modes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
Linear Power Mode (Refer to Figure 11)
Decibel Mode (Refer to Figure 11)
PRELIMINARY
0
1
0
1
0
1
Real/Imaginary Mode (Refer to Figure 10)
Invalid Mode
Averaged Linear Power Mode (Refer to Figure 11)
Averaged Decibel Power Mode (Refer to Figure 11)
XY Mode (Averaged) (Refer to Figure 10)
Invalid Mode
Logic Products
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L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
FIGURE 12. EIGHT STAGES OF THE 1024 POINT FFT DATA FLOW
STAGE 1. (260 CYCLES)
STAGE 2. (260 CYCLES)
STAGE 3. (260 CYCLES)
Twiddle
ROM
Twiddle
ROM
Window
Memory/
ROM
Input
Memory
A
Window
B
A
DF
B
A
DF
B
STAGE 4. (260 CYCLES)
STAGE 5. (260 CYCLES)
STAGE 6. (260 CYCLES)
Twiddle
ROM
Twiddle
ROM
Twiddle
ROM
A
DF
B
A
DF
B
A
DF
B
The ALPHA control register at
location 003h is the value associated
with exponential averaging of the
output. The equation is:
STAGE 7. (260 CYCLES)
STAGE 8. (260 CYCLES)
α OUTPUT + (1−α ) LAST_OUTPUT
Exponential
A
B
Average
This register is a positive value in the
range of 0000h-7FFFh (representing a
positive fractional magnitude between
0.0 and 1.0). When the ALPHA
A
SQUARE
B
Output
Memory
Bit
Reversal
register is non-zero, it is used to
compute the “moving average”
represented by the equation above.
Operational Modes
The SCALE control register at location overflow if the user is not careful
PRELIMINARY
002h is for input “power-of-two”
scaling. The device scales each stage
of the processing by a fixed value of 20 reset state), the device will not auto-
about input scaling. When SCALE is
set to other than 0 (which is the default
This device has two operating modes,
functioning as an FFT and as an FIR
filter. In FFT mode (FILT=0), an FFT
is executed according to the size
to 2+4, in the event the user does not
wish to use the block-floating point
scaling provided by the hardware.
Warning: Internal computations may
matically scale internally to prevent
an overflow condition. Should an
overflow condition occur, the over-
flow pin (OVF) will go HIGH.
specified by SZ1-0 bits as is shown in
Table 4. Data is loaded into the unit
(according to the status of CTM) and
Logic Products
06/25/98–LDS.7710-PRE.A
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DEVICES INCORPORATED
High-Speed FFT Processor
only to 2N memory locations, N being Data Handling and Formats
the transform size. Data up to the first
There are a variety of output modes
2N input memory locations will be
which affect the presentation of output
pre-multiplied (complex) by any user
data and in some cases, its format. For
window specification and then
example, in Real/ Imaginary mode
transformed. Transform results are
(XYMODE=1), at the completion of a
output according to the output format
transform, data appears at the output
buffer as interleaved real and imaginary
(See Figure 10) and in 16-bit two’s
complement format (See Figure 3). In
Linear Power mode, data is presented
to the first half (N) output buffer
chosen and in like manner to the
input, occupy the first 2N output
buffer locations. In continuous mode
(CTM=1), the memory locations are
automatically sequenced out of the
output buffer. In non-continuous
mode, results remain in the output
buffer for individual interrogation.
locations and is in 15-bit magnitude
format. In Decibel Output mode
(DBO=1), data is presented to the
output buffer in negative magnitude
format (16 bits wide but bit 15 is always
1) indicating a maximum of 0 dB at 0
and descending negatively from there.
In FIR mode (FILT=1), a FIR filter is
implemented. The filter takes a little
more than twice as long to operate
since it must, of necessity, perform
two transforms an FFT and an inverse
FFT. First, the data is input according
the SZ1-0 and the status of CTM up to
2N locations, N being the filter size.
Once the first FFT transform is
complete, the results are multiplied by
the data found in the window buffer.
The window buffer acts as coefficient
storage for the filter. Finally, a
In the continuous mode (CTM=1), the
address lines are driven from the
device and are sequenced from 0 to 2N
memory locations for XYMODE=1 or N
memory locations for power mode
(XYMODE=0).
second inverse transform is ex-
ecuted and the operation is com-
plete. The results on the output buffer
are the filtered data. The data is
output in a similar fashion to that of
the FFT output however, the EOT will
not be asserted until the second
transform is completed. Also, the INV
is toggled by the device automatically
and is not affected by the designated
pin or bit in CR0. Since the window
buffer is used for coefficient storage,
the user is limited to using one of the
built in window functions for the first
FFT pass. Control pins AVG, DBO,
XYMODE and INV are ignored in FIR
mode.
PRELIMINARY
Logic Products
06/25/98–LDS.7710-PRE.A
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L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground .......................................................................................... –0.5 V to 5.5 V
Signal applied to high impedance output ................................................................................. –0.5 V to 5.5 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
ESD (MIL-STD-883E Method 3015.7) ............................................................................................... > 2000 V
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
3.00 V ≤ VCC ≤ 3.60 V
3.00 V ≤ VCC ≤ 3.60 V
Active Operation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
Min
Typ
Max Unit
VOH
VOL
VIH
Output High Voltage
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 4.0 mA
2.4
V
Output Low Voltage
Input High Voltage
Input Low Voltage
0.4
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
Input Current
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±10
±10
µA
µA
IOZ
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
VCC Current, Quiescent
Input Capacitance
ICC1
ICC2
ICC3
CIN
COUT
200 mA
10 mA
Soft Standby, PLL Running (Note 7)
Hard Standby, PLL Disabled (Note 7)
TA = 25°C, f = 1 MHz
2
mA
pF
10
PRELIMINARY
Output Capacitance
TA = 25°C, f = 1 MHz
10
pF
Logic Products
06/25/98–LDS.7710-PRE.A
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L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
L7710
15
12
10
Symbol Parameter
Min
Max
Min
Max
Min
Max
tCYC
tPW
tS
Cycle Time
15
12
10
Clock Pulse Width
6
5
0
5
4
0
4
3
0
Input Setup Time
tH
Input Hold Time
tD
Output Delay
10
15
15
8
12
12
7
10
10
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
L7710
15
20
12
Symbol Parameter
Min
Max
Min
Max
Min
Max
tCYC
tPW
tS
Cycle Time
20
15
6
12
Clock Pulse Width
8
7
2
5
4
0
Input Setup Time
5
tH
Input Hold Time
1
tD
Output Delay
12
17
17
10
15
15
8
12
12
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
PRELIMINARY
Logic Products
06/25/98–LDS.7710-PRE.A
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L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with the point of view of the device. Output
specifications only. Functional oper- input transition times less than 3 ns, delay, for example, is specified as a
ation ofthese products at values beyond output reference levels of 1.5 V (except maximum since worst-case operation of
those indicated in the Operating Condi-
any device always provides data within
tENA/ tDIS test), and input levels of
tions table is not implied. Exposure to nominally 0 to 3.0 V. Output loading that time.
maximum rating conditions for ex- m ay be a resistive d ivid er w hich
11. Transition is measured ±200 mV
from steady-state voltage with speci-
fied loading.
tended periods may affect reliability.
provides for specified IOH and IOL at an
output voltage of VOH min and VOL
max respectively. Alternatively, a
diode bridge with upper and lower
cu rrent sou rces of IOH and IOL
respectively, and a balancing voltage of
1.5Vmay be used. Parasiticcapacitance
is 30 p F m inim u m , and m ay be
distributed. For tENABLE and tDISABLE
measurements, the load current is
increased to 10 mA to reduce the RC
delay component of the measurement.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations ofstaticcharge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to
avoid exposure to excessive electrical
stress values.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. INPUT CIRCUIT
VCC
3. Thisdeviceprovideshard clampingof
transient undershoot and overshoot. In-
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
p
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/ turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
10Ω
300Ω
n
tion will not be adversely affected, how- a. A 0.1 µF ceramic capacitor should be
ever, input current levels will be well in
excess of 100 mA.
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between device VCC
and the tester common, and device
ground and tester common.
FIGURE B. OUTPUT CIRCUIT
4. Actualtest conditions may vary from
those designated but operation is guar-
anteed as specified.
VCC
5. Supply current for a given applica-
tion can be accurately approximated by:
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
n
2
NCV F
OUTPUT
n+
c. Input voltages should be adjusted to
compensate for inductive ground and
VCC noise to maintain required DUT
input levels relative to the DUT ground
pin.
4
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
D1
p–
n
F = clock frequency
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
6. Tested with all outputs changing ev-
ery cycle and no load, at a X MHz clock
FIGURE C. THRESHOLD LEVELS
t
DIS
tENA
PRELIMINARY
rate.
the chip. Setup time, for example, is
OE
7. Tested with all inputs within 0.1 V of
0.2 V
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements ofall parts. Responses from
the internal circuitry are specified from
0.2 V
HIGH IMPEDANCE
VCC or Ground, no load.
TRISTATE
OUTPUTS
8. These parameters are guaranteed
but not 100% tested.
0.2 V
0.2 V
Logic Products
06/25/98–LDS.7710-PRE.A
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L7710 - DragonFlyTM
DEVICES INCORPORATED
High-Speed FFT Processor
ORDERING INFORMATION
144-pin
GND
CTM
SZ1
1
2
3
4
5
6
7
8
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
VCC
INV
FILT
AVG
XYMODE
DBO
DOUT15
DOUT14
DOUT13
DOUT12
GND
SZ0
OVC1
OVC2
DIN15
DIN14
DIN13
DIN12
VCC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
VCC
DIN11
DIN10
DIN9
DIN8
VCC
DOUT11
DOUT10
DOUT9
DOUT8
GND
ORD/OWE
EF
VCC
DOUT7
DOUT6
DOUT5
DOUT4
GND
Top
View
FF
DRD/DWE
GND
DIN7
DIN6
DIN5
DIN4
VCC
GND
DIN3
DIN2
VCC
DOUT3
DOUT2
DOUT1
DOUT0
GND
DIN1
DIN0
CACC1
CACC0
CB
AIN10
AIN9
VCC
STDBY
HOLD
OCLK
GND
74
73
VCC
Plastic Quad Flatpack
(G5)
Flatpack
(F3)
Speed
0°C to +70°C — COMMERCIAL SCREENING
15 ns
12 ns
10 ns
L7710QC15
L7710QC12
L7710QC10
–40°C to +85°C — INDUSTRIAL SCREENING
15 ns
12 ns
10 ns
L7710QI15
L7710QI12
L7710QI10
PRELIMINARY
–55°C to +125°C — MIL-STD-883 COMPLIANT
20 ns
15 ns
12 ns
L7710FMB20
L7710FMB15
L7710FMB12
Logic Products
06/25/98–LDS.7710-PRE.A
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