L7C108WC15L [LOGIC]
Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32;
| 型号： | L7C108WC15L |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, SOJ-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L7C108/109
128K x 8 Static RAM (Low Power)
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The L7C108 and L7C109 are high-
performance, low-power CMOS static
RAMs. The storage circuitry is organ-
ized as 131,072 words by 8 bits per
word. The 8 Data In and Data Out
signals share I/O pins. The L7C108 has
a single active-low Chip Enable. The
L7C109 has two Chip Enables (one
active-low). These devices are available
inthree speeds with maximum access
times from 10 ns to 15 ns.
consume only 1.5 mW (typical), at 3 V,
allowing effective battery backup
operation.
q 128K x 8 Static RAM with Chip
Select Powerdown, Output Enable
q Auto-Powerdown™ Design
q Advanced CMOS Technology
q High Speed — to 10 ns maximum
q Low Power Operation
Active: 570 mW typical at 15 ns
Standby: 5 mW typical
The L7C108 and L7C109 provide
asynchronous (unclocked) operation
with matching access and cycle times.
The Chip Enables and a three-state I/O
bus with a separate Output Enable
control simplify the connection of
several chips for increased storage
capacity.
q Data Retention at 2 V for Battery
Backup Operation
q DSCC SMD No. 5962-89598
Inputs and outputs are TTL compat-
ible. Operation is from a single +5 V
power supply. Power consumption
is 930 mW (typical) at 10 ns. Dissipa-
tion drops to 50 mW (typical) when
the memory is deselected.
q Available 100% Screened to
Memory locations are specified on
address pins A0 through A16. For the
L7C108, reading from a designated
location is accomplished by presenting
an address and driving CE1 and OE
LOW while WE remains HIGH. For
the L7C109, CE1 and OE must be
LOW while CE2 and WE are HIGH.
The data in the addressed memory
location will then appear on the Data
Out pins within one access time. The
output pins stay in a high-impedance
state when CE1 or OE is HIGH, or CE2
(L7C109) or WE is LOW.
MIL-STD-883, Class B
q Plug Compatible with Cypress
CY7C108/109, IDT71024/71B024,
Micron MT5C1008, Motorola
MCM6226A/62L26A, Sony
CXK581020
q Package Styles Available:
• 32-pin Sidebraze, Hermetic DIP
• 32-pin Plastic SOJ
Two standby modes are available.
Proprietary Auto-Powerdown™
circuitry reduces power consumption
automatically during read or write
accesses which are longer than the
minimum access time, or when the
memory is deselected. In addition,
data may be retained in inactive
storage with a supply voltage as low
as 2 V. The L7C108 and L7C109
• 32-pin Ceramic LCC
• 32-pin Ceramic SOJ
Writing to an addressed location is
accomplished when the active-low
CE1 and WE inputs are both LOW,
and CE2 (L7C109) is HIGH. Any of
these signals may be used to terminate
the write operation. Data In and Data
Out signals have the same polarity.
L7C108/109 BLOCK DIAGRAM
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection
current of up to 200 mA on any pin
without damage.
512 x 256 x 8
MEMORY
ARRAY
9
ROW
ADDRESS
CE
1
8
COLUMN SELECT
I/O7-0
WE
OE
CONTROL
& COLUMN SENSE
OBSOLETE
CE
2
(L7C109 only)
8
COLUMN ADDRESS
1M Static RAMs
03/04/99–LDS.108/9-N
1
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 200 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
4.5 V ≤ VCC ≤ 5.5 V
4.5 V ≤ VCC ≤ 5.5 V
4.5 V ≤ VCC ≤ 5.5 V
2.0 V ≤ VCC ≤ 5.5 V
2.0 V ≤ VCC ≤ 5.5 V
2.0 V ≤ VCC ≤ 5.5 V
Active Operation, Commercial
Active Operation, Industrial
Active Operation, Military
Data Retention, Commercial
Data Retention, Industrial
Data Retention, Military
–40°C to +85°C
–55°C to +125°C
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 5)
L7C108/109
L7C108-L/109-L
Symbol Parameter
Test Condition
Min
Typ Max Min
Typ Max Unit
VOH
VOL
VIH
Output High Voltage
VCC = 4.5 V, IOH = –4.0 mA
IOL = 8.0 mA
2.4
2.4
V
Output Low Voltage
Input High Voltage
0.4
0.4
V
V
2.2
VCC
2.2
VCC
+0.5
+0.3
VIL
Input Low Voltage
(Note 3)
–0.5
–5
0.8 –3.0
+5 –10
+5 –10
35
0.8
V
IIX
Input Leakage Current
Output Leakage Current
VCC Current, TTL Inactive
VCC Current, CMOS Standby
VCC Current, Data Retention
Input Capacitance
GND ≤ VIN ≤ VCC
(Note 4)
+10 µA
+10 µA
25 mA
0.9 mA
300 µA
IOZ
–5
ICC2
ICC3
ICC4
CIN
COUT
(Note 7)
10
1
(Note 8)
5.0
VCC = 3.0 V (Notes 9, 10)
Ambient Temp = 25°C, VCC = 5.0 V
Test Frequency = 1 MHz (Note 10)
500 1000
7
5
pF
pF
Output Capacitance
8
7
OBSOLETE
L7C108/109-
Symbol Parameter
Test Condition
15
12
10 Unit
ICC1
VCC Current, Active
(Note 6)
160
170
180 mA
1M Static RAMs
03/04/99–LDS.108/9-N
2
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
SWITCHING CHARACTERISTICS Over Operating Range
READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109–
15
12
10
Symbol Parameter
Min Max Min Max Min Max
tAVAV
tAVQV
tAXQX
tCLQV
tCLQZ
tCHQZ
tOLQV
tOLQZ
tOHQZ
tPU
Read Cycle Time
15
15
3
12
12
3
10
10
3
Address Valid to Output Valid (Notes 13, 14)
Address Change to Output Change
15
15
12
12
10
10
Chip Enable Low to Output Valid (Notes 13, 15)
Chip Enable Low to Output Low Z (Notes 20, 21)
Chip Enable High to Output High Z (Notes 20, 21)
Output Enable Low to Output Valid
4
7
3
6
3
5
Output Enable Low to Output Low Z (Notes 20, 21)
Output Enable High to Output High Z (Notes 20, 21)
Input Transition to Power Up (Notes 10, 19)
Power Up to Power Down (Notes 10, 19)
Chip Enable High to Data Retention (Note 10)
0
0
0
0
0
0
0
0
0
4
3
3
tPD
15
12
10
tCHVL
READ CYCLE — ADDRESS CONTROLLED Notes 13, 14
t
AVAV
ADDRESS
t
AVQV
DATA OUT
PREVIOUS DATA VALID
AXQX
DATA VALID
t
t
PU
tPD
I
CC
READ CYCLE — CE/OE CONTROLLED Notes 13, 15
t
AVAV
CE
t
CLQV
t
CHQZ
t
CLQZ
OE
t
OLQV
t
OHQZ
t
OLQZ
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA OUT
DATA VALID
t
PU
tPD
I
CC
50%
50%
DATA RETENTION Notes 9, 10
DATA RETENTION MODE
OBSOLETE
V
CC
4.5 V
4.5 V
≥ 2 V
t
CHVL
tAVAV
CE
V
IH
VIH
1M Static RAMs
03/04/99–LDS.108/9-N
3
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
SWITCHING CHARACTERISTICS Over Operating Range
WRITE CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109–
15
12
10
Symbol Parameter
Min Max Min Max Min Max
tAVAV
Write Cycle Time
15
13
0
12
10
0
10
9
tCLEW
tAVBW
tAVEW
tEWAX
tWLEW
tDVEW
tEWDX
tWHQZ
tWLQZ
Chip Enable Low to End of Write Cycle
Address Valid to Beginning of Write Cycle
Address Valid to End of Write Cycle
End of Write Cycle to Address Change
Write Enable Low to End of Write Cycle
Data Valid to End of Write Cycle
0
13
0
10
0
9
0
11
8
9
8
6
5
End of Write Cycle to Data Change
Write Enable High to Output Low Z (Notes 20, 21)
Write Enable Low to Output High Z (Notes 20, 21)
0
0
0
3
3
3
5
5
5
WRITE CYCLE — WE CONTROLLED Notes 16, 17, 18, 19
tAVAV
ADDRESS
CE
tCLEW
tAVEW
tEWAX
tWLEW
WE
tAVBW
tDVEW
tEWDX
DATA IN
DATA OUT
DATA-IN VALID
t
WLQZ
tWHQZ
HIGH IMPEDANCE
PD
tPU
t
tPU
ICC
WRITE CYCLE — CE CONTROLLED Notes 16, 17, 18, 19
tAVAV
ADDRESS
CE
tAVBW
tCLEW
tAVEW
tEWAX
tWLEW
WE
tDVEW
tEWDX
DATA IN
DATA OUT
DATA-IN VALID
OBSOLETE
HIGH IMPEDANCE
tPU
tPD
I
CC
1M Static RAMs
03/04/99–LDS.108/9-N
4
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
NOTES
1. MaximumRatingsindicatestressspecifi- 11. Test conditions assume input transition 20. At any given temperature and voltage
cations only. Functional operation of these times of less than 3 ns, reference levels of condition, output disable time is less than
products at values beyond those indicated 1.5 V, output loading for specified IOL and output enable time for any given device.
in the Operating Conditions table is not IOH plus 30 pF (Fig. 1a), and input pulse
21. Transition is measured ±200 mV from
implied. Exposure to maximum rating con- levels of 0 to 3.0 V (Fig. 2).
steady state voltage with specified loading
ditions for extended periods may affect re-
12. Each parameter is shown as a minimum in Fig. 1b. This parameter is sampled and
liability of the tested device.
or maximum value. Input requirements are not 100% tested.
2. The products described by this specifica- specified from the point of view of the exter-
22. All address timings are referenced from
tion include internal circuitry designed to nal system driving the chip. For example,
the last valid address line to the first transi-
protect the chip from damaging substrate tAVEW is specified as a minimum since the
tioning address line.
injection currents and accumulations of external system must supply at least that
static charge. Nevertheless, conventional much time to meet the worst-case require- 23. CE1, CE2, orWEmustbeinactiveduring
precautions should be observed during ments of all parts. Responses from the inter- address transitions.
storage, handling, and use of these circuits nal circuitry are specified from the point of
24. This product is a very high speed device
in order to avoid exposure to excessive elec- view of the device. Access time, for ex-
and care must be taken during testing in
trical stress values.
ample, is specified as a maximum since
worst-case operation of any device always
provides data within that time.
order to realize valid test information. In-
adequate attention to setups and proce-
dures can cause a good part to be rejected as
faulty. Long high inductance leads that
cause supply bounce must be avoided by
bringing the VCC and ground planes di-
rectly up to the contactor fingers. A 0.01 µF
3. This product provides hard clamping of
transient undershoot. Input levels below
ground will be clamped beginning at –0.6 V. 13. WE is high for the read cycle.
A current in excess of 100 mA is required to
14. The chip is continuously selected (CE1
reach –2.0 V. The device can withstand in-
low, CE2 high).
definite operation with inputs as low as –3 V
subject only to power dissipation and bond 15. All address lines are valid prior-to or high frequency capacitor is also required
wire fusing constraints.
coincident-with the CE1 and CE2 transition between VCC and ground. To avoid signal
to active.
reflections, proper terminations must be
used.
4. Tested with GND ≤ VOUT ≤ VCC. The de-
vice is disabled, i.e., CE1 = VCC, CE2 = GND. 16. The internal write cycle of the memory
is defined by the overlap of CE1 and CE2
5. A series of normalized curves is available
activeandWElow. Allthreesignalsmustbe
to supply the designer with typical DC and
active to initiate a write. Any signal can
ACparametricinformationforLogicDevices
terminate a write by going inactive. The
Static RAMs. These curves may be used to
address, data, and control input setup and
determine device characteristics at various
hold times should be referenced to the sig-
temperatures and voltage levels.
FIGURE 1a.
R
1 480Ω
+5 V
nalthatbecomesactivelastorbecomesinac-
OUTPUT
6. Tested with all address and data inputs tive first.
changing at the maximum cycle rate. The
17. If WE goes low before or concurrent
device is continuously enabled for writing,
with the latter of CE1 and CE2 going active,
i.e., CE1 ≤ VIL, CE2 ≥ VIH, WE ≤ VIL. Input
the output remains in a high impedance
pulse levels are 0 to 3.0 V.
R
255Ω
2
30 pF
INCLUDING
JIG AND
SCOPE
state.
7. Tested with outputs open and all address
18. If CE1 and CE2 goes inactive before or
and data inputs changing at the maximum
concurrent with WE going high, the output
read cycle rate. The device is continuously
remains in a high impedance state.
FIGURE 1b.
disabled, i.e., CE1 ≥ VIH, CE2 ≤ VIL.
19. Powerup from ICC2 to ICC1 occurs as a
8. Tested with outputs open and all ad-
R
1
480Ω
result of any of the following conditions:
+5 V
dress and data inputs stable. The device
is continuously disabled, i.e., CE1 = VCC, a. Rising edge of CE2 (CE1 active) or the
OUTPUT
CE2 = GND. Input levels are within 0.2 V
of VCC or GND.
falling edge of CE1 (CE2 active).
b. Falling edge of WE (CE1, CE2 active).
R
255Ω
2
INCLUDING
JIG AND
SCOPE
5 pF
9. Data retention operation requires that
VCC never drop below 2.0 V. CE1 must be
≥ VCC – 0.2 V or CE2 must be ≤ 0.2 V. All
c. Transition on any address line (CE1, CE2
active).
other inputs must meet VIN ≥ VCC – 0.2 V or d. Transition on any data line (CE1, CE2,
VIN ≤ 0.2 V to ensure full powerdown. For
low power version (if applicable), this re-
quirement applies only to CE1, CE2, and
and WE active).
The device automatically powers down
FIGURE 2.
from ICC1 to ICC2 after tPD has elapsed from
OBSOLETE
WE; there are no restrictions on data and
address.
any of the prior conditions. This means that
power dissipation is dependent on only
+3.0 V
90%
10%
<3 ns
90%
10. These parameters are guaranteed but cycle rate, and is not on Chip Select pulse
not 100% tested. width.
10%
GND
<3 ns
1M Static RAMs
03/04/99–LDS.108/9-N
5
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
L7C108 ORDERING INFORMATION
32-pin — 0.4" wide
32-pin — 0.4" wide
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
16
NC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
16
NC
2
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
2
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
3
NC
3
NC
4
WE
4
WE
5
A15
A14
A13
A12
5
A15
A14
A13
A12
6
6
7
7
8
8
9
OE
OE
9
10
11
12
13
14
15
16
A11
A11
10
11
12
13
14
15
16
CE
1
CE
1
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
A10
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
A10
I/O
I/O
I/O
0
1
2
I/O
I/O
I/O
0
1
2
GND
GND
Sidebraze Hermetic DIP
(D12)
Plastic SOJ
(W6)
Speed
0°C to +70°C — COMMERCIAL SCREENING
L7C108DC15*
15 ns
12 ns
10 ns
L7C108WC15*
L7C108WC12*
L7C108WC10*
L7C108DC12*
L7C108DC10*
–40°C to +85°C — COMMERCIAL SCREENING
15 ns
12 ns
10 ns
L7C108WI15*
L7C108WI12*
L7C108WI10*
–55°C to +125°C — COMMERCIAL SCREENING
15 ns
12 ns
L7C108DM15
L7C108DM12
OBSOLETE
–55°C to +125°C — MIL-STD-883 COMPLIANT
15 ns
12 ns
L7C108DMB15
L7C108DMB12
*The Low Power version is specified by adding the "L" suffix after the speed grade (e.g., L7C108WI10L)
1M Static RAMs
03/04/99–LDS.108/9-N
6
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
L7C108 ORDERING INFORMATION
32-pin
32-pin — 0.440" wide
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
16
NC
4
3
2
1
32 31 30
29
2
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
3
NC
5
A
A
A
A
A
A
A
3
4
5
6
7
8
9
WE
4
WE
6
28
27
26
25
24
23
22
21
A
A
A
A
15
14
13
12
5
A15
A14
A13
A12
7
6
8
7
Top
View
9
8
10
11
12
13
OE
OE
9
A
11
A11
10
11
12
13
14
15
16
A
10
CE
I/O
1
CE
1
I/O
0
7
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
A10
I/O
I/O
I/O
0
1
2
14 15 16 17 18 19 20
GND
Ceramic Leadless Chip Carrier
(K10)
Ceramic SOJ
(Y1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
L7C108KC15*
15 ns
12 ns
10 ns
L7C108KC12*
L7C108KC10*
–40°C to +85°C — COMMERCIAL SCREENING
15 ns
12 ns
10 ns
–55°C to +125°C — COMMERCIAL SCREENING
15 ns
12 ns
L7C108KM15
L7C108KM12
L7C108YM15
L7C108YM12
OBSOLETE
–55°C to +125°C — MIL-STD-883 COMPLIANT
15 ns
12 ns
L7C108KMB15
L7C108KMB12
L7C108YMB15
L7C108YMB12
*The Low Power version is specified by adding the "L" suffix after the speed grade (e.g., L7C108KC10L)
1M Static RAMs
03/04/99–LDS.108/9-N
7
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
L7C109 ORDERING INFORMATION
32-pin — 0.4" wide
32-pin — 0.4" wide
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
16
NC
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
A
CC
16
NC
2
A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
2
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
3
CE
2
3
CE
2
4
WE
WE
4
5
A15
A14
A13
A12
A
A
A
A
15
14
13
12
5
6
6
7
7
8
8
9
OE
OE
9
10
11
12
13
14
15
16
A11
A
11
10
11
12
13
14
15
16
CE
1
CE
1
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
A10
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
A
10
I/O
I/O
I/O
0
1
2
I/O
I/O
I/O
0
1
2
GND
GND
Sidebraze Hermetic DIP
(D12)
Plastic SOJ
(W6)
Speed
0°C to +70°C — COMMERCIAL SCREENING
L7C109DC15*
15 ns
12 ns
10 ns
L7C109WC15*
L7C109WC12*
L7C109WC10*
L7C109DC12*
L7C109DC10*
–40°C to +85°C — COMMERCIAL SCREENING
15 ns
12 ns
10 ns
L7C109WI15*
L7C109WI12*
L7C109WI10*
–55°C to +125°C — COMMERCIAL SCREENING
15 ns
12 ns
L7C109DM15
L7C109DM12
OBSOLETE
–55°C to +125°C — MIL-STD-883 COMPLIANT
15 ns
12 ns
L7C109DMB15
L7C109DMB12
*The Low Power version is specified by adding the "L" suffix after the speed grade (e.g., L7C109WI10L)
1M Static RAMs
03/04/99–LDS.108/9-N
8
L7C108/109
DEVICES INCORPORATED
128K x 8 Static RAM (Low Power)
L7C109 ORDERING INFORMATION
32-pin
32-pin — 0.440" wide
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
16
NC
4
3
2
1
32 31 30
29
2
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
3
CE
2
5
A
A
A
A
A
A
A
3
4
5
6
7
8
9
WE
WE
4
6
28
27
26
25
24
23
22
21
A
A
A
A
15
14
13
12
A
A
A
A
15
14
13
12
5
7
6
8
7
Top
View
9
8
10
11
12
13
OE
OE
9
A
11
A
11
10
11
12
13
14
15
16
A
10
CE
I/O
1
CE
1
I/O
0
7
I/O
I/O
I/O
I/O
I/O
7
6
5
4
3
A
10
I/O
I/O
I/O
0
1
2
14 15 16 17 18 19 20
GND
Ceramic Leadless Chip Carrier
(K10)
Ceramic SOJ
(Y1)
Speed
0°C to +70°C — COMMERCIAL SCREENING
L7C109KC15*
15 ns
12 ns
10 ns
L7C109KC12*
L7C109KC10*
–40°C to +85°C — COMMERCIAL SCREENING
15 ns
12 ns
10 ns
–55°C to +125°C — COMMERCIAL SCREENING
15 ns
12 ns
L7C109KM15
L7C109KM12
L7C109YM15
L7C109YM12
OBSOLETE
–55°C to +125°C — MIL-STD-883 COMPLIANT
15 ns
12 ns
L7C109KMB15
L7C109KMB12
L7C109YMB15
L7C109YMB12
*The Low Power version is specified by adding the "L" suffix after the speed grade (e.g., L7C109KC10L)
1M Static RAMs
03/04/99–LDS.108/9-N
9
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