LMU12GC35 [LOGIC]
Multiplier, 12-Bit, CMOS, CPGA68, CERAMIC, PGA-68;
| 型号： | LMU12GC35 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | Multiplier, 12-Bit, CMOS, CPGA68, CERAMIC, PGA-68 时钟 输入元件 外围集成电路 |
| 文件： | 总6页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMU12
12 x 12-bit Parallel Multiplier
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The LMU12 is a high-speed, low
The TCA and TCB controls specify the
power 12-bit parallel multiplier. It is A and B operands as two’s comple-
❑ 20 ns Worst-Case Multiply Time
❑ Low Power CMOS Technology
❑ Replaces Fairchild MPY012H
pin and functionally compatible with
Fairchild MPY012H devices. Full
military ambient temperature range
operation is attained by the use of
advanced CMOS technology.
ment when HIGH, or unsigned
magnitude when LOW.
❑ Two’s Complement, Unsigned, or
Mixed Operands
RND is loaded on the rising edge of
the logical OR of CLK A and CLK B.
RND, when HIGH, adds ‘1’ to the
most significant bit position of the
least significant half of the product.
Subsequent truncation of the 12 least
❑ Three-State Outputs
❑ Package Styles Available:
• 68-pin Ceramic PGA
The LMU12 produces the 24-bit
product of two 12-bit numbers. Data
present at the A inputs, along with
the TCA control bit, is loaded into the significant bits produces a result
A register on the rising edge of
CLK A. B data and the TCB control
bit are similarly loaded by CLK B.
correctly rounded to 12-bit precision.
At the output, the Right Shift control
(RS) selects either of two output
formats. RS LOW produces a 23-bit
product with a copy of the sign bit
inserted in the MSB position of the
least significant half. RS HIGH gives
a full 24-bit product. Two 12-bit
output registers are provided to hold
the most and least significant halves
of the result (MSP and LSP) as
LMU12 BLOCK DIAGRAM
TCA
A
11-0
TCB
B11-0
12
A REGISTER
12
B REGISTER
CLK A
CLK B
defined by RS. These registers are
loaded on the rising edge of CLK M
and CLK L respectively. For asyn-
chronous output, these registers may
be made transparent by setting the
feed through control (FT) HIGH.
RND
24
FORMAT ADJUST
RS
12
12
FT
CLK M
RESULT
REGISTER
CLK L
OEL
OEM
12
12
R
23-12
R
11-0
Multipliers
03/26/1999–LDS.12-O
1
LMU12
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
FIGURE 1A. INPUT FORMATS
AIN
BIN
Fractional Two’s Complement (TCA, TCB = 1)
11 10 9
2
1
0
11 10 9
2
1
0
–20 2–1 2–2
2–9 2–10 2–11
–20 2–1 2–2
2–9 2–10 2–11
(Sign)
(Sign)
Integer Two’s Complement (TCA, TCB = 1)
11 10 9
2
1
0
11 10 9
2
1
0
–211 210 29
22 21 20
–211 210 29
22 21 20
(Sign)
(Sign)
Unsigned Fractional (TCA, TCB = 0)
11 10 9
2–1 2–2 2–3
2
1
0
11 10 9
2–1 2–2 2–3
2
1
0
2–10 2–11 2–12
2–10 2–11 2–12
Unsigned Integer (TCA, TCB = 0)
11 10 9
211 210 29
2
1
0
11 10 9
211 210 29
2
1
0
22 21 20
22 21 20
FIGURE 1B. OUTPUT FORMATS
MSP
LSP
Fractional Two’s Complement (RS = 0)
23 22 21
14 13 12
2–9 2–10 2–11
11 10 9
2
1
0
–20 2–1 2–2
–20 2–12 2–13
2–20 2–21 2–22
(Sign)
(Sign)
Fractional Two’s Complement (RS = 1)
23 22 21
14 13 12
2–8 2–9 2–10
11 10 9
2–11 2–12 2–13
2
1
0
–21 20 2–1
2–20 2–21 2–22
(Sign)
Integer Two’s Complement (RS = 1)
23 22 21
14 13 12
214 213 212
11 10 9
211 210 29
2
1
0
–223 222 221
22 21 20
(Sign)
Unsigned Fractional (RS = 1)
23 22 21
2–1 2–2 2–3
14 13 12
2–10 2–11 2–12
11 10 9
2–13 2–14 2–15
2
1
0
2–22 2–23 2–24
Unsigned Integer (RS = 1)
23 22 21
223 222 221
14 13 12
214 213 212
11 10 9
211 210 29
2
1
0
22 21 20
Multipliers
03/26/1999–LDS.12-O
2
LMU12
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
4.75 V ≤ VCC ≤ 5.25 V
4.50 V ≤ VCC ≤ 5.50 V
Active Operation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
VOH
VOL
VIH
Parameter
Test Condition
Min
Typ
Max Unit
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 8.0 mA
2.4
V
0.5
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±20
±20
µA
µA
IOZ
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
ICC1
ICC2
17
35 mA
1.0 mA
(Note 7)
Multipliers
03/26/1999–LDS.12-O
3
LMU12
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LMU12–
*
65
*
45
35
20
Symbol Parameter
Min Max Min Max Min Max Min Max
tMC
Clocked Multiply Time
65
95
45
65
35
55
20
40
tMUC Unclocked Multiply Time
tPW
tS
Clock Pulse Width
25
18
2
15
15
2
15
12
2
8
10
0
Input Register Setup Time
Input Register Hold Time
tH
tD
Output Delay
26
22
20
25
22
20
25
20
18
18
15
15
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
LMU12–
*
75
*
55
*
45
*
25
Symbol Parameter
Min Max Min Max Min Max Min Max
tMC
Clocked Multiply Time
75
55
75
45
65
25
45
tMUC Unclocked Multiply Time
110
tPW
tS
Clock Pulse Width
25
18
2
20
15
2
15
15
2
10
12
2
Input Register Setup Time
Input Register Hold Time
tH
tD
Output Delay
30
26
24
30
26
24
25
24
22
20
20
20
tENA
tDIS
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
SWITCHING WAVEFORMS
tS
tH
INPUT
tPW
tPW
CLK A
CLK B
tMC
tD
CLK L
CLK M
tMUC
OEL
OEM
tDIS
tENA
HIGH IMPEDANCE
R23-0
*DISCONTINUED SPEED GRADE
Multipliers
03/26/1999–LDS.12-O
4
LMU12
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with
11. For the tENA test, the transition is
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
ation ofthese products at values beyond output reference levels of 1.5 V (except
those indicated in the Operating Condi-
with datasheet loads. For the tDIS test,
the transition is m easu red to the
tDIS test), and input levels of nominally
tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200m V level from the m easured
maximum rating conditions for ex- resistive divider which provides for steady-state ou tp u t v oltage w ith
tended periods may affect reliability.
±10m A load s. The balancing volt-
age, VTH , is set at 3.5 V for Z-to-0
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations ofstaticcharge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
bridge with upper and lower current to-1 and 1-to-Z tests.
sources of IOH and IOL respectively,
12. These parameters are only tested at
and a balancing voltage of 1.5 V may be
the high temperature extreme, which is
used. Parasitic capacitance is 30 pF
the worst case for leakage current.
minimum, and may be distributed.
FIGURE A. OUTPUT LOADING CIRCUIT
stress values.
pulses and fast turn-on/ turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
S1
DUT
3. Thisdeviceprovideshard clamping of
transient undershoot and overshoot. In-
put levels below ground or above VCC
I
OL
V
TH
CL
I
OH
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
FIGURE B. THRESHOLD LEVELS
t
ENA
tDIS
tion will not be adversely affected, how-
ever, input current levels will be well in and the tester common, and device
should be installed between device VCC
OE
0
1.5 V
1.5 V
excess of 100 mA.
ground and tester common.
Z
Z
3.5V Vth
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
4. Actualtest conditions may vary from
b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified. socket or contactor fingers.
V
OH*
1
0V Vth
VOL*
Measured VOL with IOH = –10mA and IOL = 10mA
V
OH* Measured VOH with IOH = –10mA and IOL = 10mA
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by:
compensatefor inductiveground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
2
NCV F
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements ofall parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
Multipliers
03/26/1999–LDS.12-O
5
LMU12
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
ORDERING INFORMATION
64-pin
68-pin
A
A
A
A
A
A
A
A
R
R
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A
A
A
A
8
2
9
1
2
3
4
5
6
7
8
9
10
11
3
10
11
4
5
CLK A
CLK B
RND
A
B
6
NC
A
0
1
RND
A
2
3
A4
A6
A8
A
10 CLK A
TCA NC
11 CLK B
7
8
TCA
9
B
B
B
B
B
B
V
V
V
B
B
B
B
B
B
0
R1
R0
R2
R4
R6
R8
A
A
A5
A7
A9
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
C
D
E
F
G
H
J
2
R3
R5
R7
R9
B1
B3
B5
B0
B2
B4
3
4
5
CC
CC
CC
6
Top View
Through Package
(i.e., Component Side Pinout)
V
CC
V
CC
CC
R
R
10
11
7
8
R11
R10
B6
V
OEL
OEM
GND
GND
FT
RS
CLK L
CLK M
9
10
11
OEM OEL
GND GND
B8
B7
TCB
R
R
R
R
R
R
R
R
23
22
21
20
19
18
17
16
B10
B9
K
L
NC
FT CLK L
RS CLK M
TCB
NC
B11
R
12
13
R
14
15
R
16
17
R
18
19
R
20
21
R
22
23
R12
R13
R14
R15
R
R
R
R
R
R
Discontinued Package
Sidebraze Hermetic DIP
(D6)
Ceramic Pin Grid Array
(G2)
Speed
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
35 ns
20 ns
LMU12GC35
LMU12GC20
Multipliers
03/26/1999–LDS.12-O
6
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