LPR521CMB18 [LOGIC]
Pipeline Register, 16-Bit, CMOS, CDIP40, 0.600 INCH, CERAMIC, DIP-40;
| 型号： | LPR521CMB18 |
| 厂家： | 
LOGIC DEVICES INCORPORATED |
| 描述： | Pipeline Register, 16-Bit, CMOS, CDIP40, 0.600 INCH, CERAMIC, DIP-40 时钟 CD 输出元件 外围集成电路 |
| 文件： | 总6页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LPR520/521
4 x 16-bit Multilevel Pipeline Register
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The LPR520 and LPR521 are functionally The S1-0 select lines control a 4-to-1
❑ Four 16-bit Registers
compatible with the IDT29FCT520/
IDT29FCT521 and AMD Am29520/
Am29521 but have 16-bit inputs and
outputs. They are implemented in low
power CMOS.
multiplexer which routes the contents
of any of the registers to the Y output
pins. The independence of the I and S
controls allows simultaneous write
and read operations on different
registers.
❑ Implements Double 2-Stage Pipe-
line or Single 4-Stage Pipeline
Register
❑ Hold, Shift, and Load Instructions
❑ Separate Data In and Data Out Pins
The LPR520 and LPR521 contain four
registers which can be configured as
two independent, 2-level pipelines or
as one 4-level pipeline.
❑ High-Speed, Low Power CMOS
Technology
TABLE 1.
LPR520 INSTRUCTION TABLE
❑ Three-State Outputs
❑ DESC SMD No. 5962-89716
The Instruction pins, I1-0, control the
loading of the registers. For either
device, the registers may be config-
ured as a four-stage delay line, with
data loaded into R1 and shifted
sequentially through R2, R3, and R4.
Also, for the LPR520, data may be
loaded from the inputs into either R1
or R3 with only R2 or R4 shifting. The
LPR521 differs from the LPR520 in
that R2 and R4 remain unchanged
during this type of data load, as
shown in Tables 1 and 2. Finally, I1-0
may be set to prevent any register
from changing.
❑ Available 100% Screened to
I1 I0 Description
MIL-STD-883, Class B
L
L
L
H
L
D➞R1 R1➞R2 R2➞R3 R3➞R4
❑ Package Styles Available:
• 40-pin Plastic DIP
HOLD HOLD
D➞R3
R3➞R4
• 40-pin Ceramic DIP
• 44-pin Plastic LCC, J-Lead
• 44-pin Ceramic LCC
H
H
D➞R1 R1➞R2 HOLD
HOLD
H
ALL REGISTERS ON HOLD
TABLE 2.
LPR521 INSTRUCTION TABLE
I1 I0 Description
L
L
L
H
L
D➞R1 R1➞R2 R2➞R3 R3➞R4
HOLD HOLD
D➞R3
HOLD
HOLD
H
H
D➞R1 HOLD
HOLD
LPR520/521 BLOCK DIAGRAM
H
ALL REGISTERS ON HOLD
TABLE 3. OUTPUT SELECT
S1 S0 Register Selected
16
L
L
L
H
L
Register 4
Register 3
Register 2
Register 1
D15-0
REG 1
H
H
16
REG 2
Y
15-0
H
REG 3
REG 4
OE
2
S
1-0
2
I
1-0
CLK
Pipeline Registers
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1
LPR520/521
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature .......................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground .......................................................................... –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
0°C to +70°C
Supply Voltage
4.75 V ≤ VCC ≤ 5.25 V
4.50 V ≤ VCC ≤ 5.50 V
Active Operation, Commercial
Active Operation, Military
–55°C to +125°C
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol Parameter
Test Condition
Min
Typ
Max Unit
VOH
VOL
VIH
Output High Voltage
VCC = Min., IOH = –2.0 mA
VCC = Min., IOL = 8.0 mA
2.4
V
Output Low Voltage
Input High Voltage
Input Low Voltage
0.5
VCC
0.8
V
V
2.0
0.0
VIL
(Note 3)
V
IIX
Input Current
Ground ≤ VIN ≤ VCC (Note 12)
Ground ≤ VOUT ≤ VCC (Note 12)
(Notes 5, 6)
±20
±20
µA
µA
IOZ
ICC1
ICC2
Output Leakage Current
VCC Current, Dynamic
VCC Current, Quiescent
10
40 mA
1.0 mA
(Note 7)
Pipeline Registers
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2
LPR520/521
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
LPR520/521–
22
25
15
Symbol Parameter
Min
Max
Min
Max
Min
Max
tPD
tSEL
tPW
tSI
Clock to Output Delay
25
22
15
Select to Output Delay
25
20
15
Clock Pulse Width
10
13
3
10
10
3
8
6
1
6
1
Instruction Setup Time
tHI
Instruction Hold Time
tSD
tHD
tENA
tDIS
Data Setup Time
13
3
10
3
Data Hold Time
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
25
25
21
15
15
12
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
LPR520/521–
24
30
18
Symbol Parameter
Min
Max
Min
Max
Min
Max
tPD
tSEL
tPW
tSI
Clock to Output Delay
30
24
18
Select to Output Delay
30
22
18
Clock Pulse Width
15
15
5
10
10
3
9
8
2
8
2
Instruction Setup Time
tHI
Instruction Hold Time
tSD
tHD
tENA
tDIS
Data Setup Time
15
5
10
3
Data Hold Time
Three-State Output Enable Delay (Note 11)
Three-State Output Disable Delay (Note 11)
25
20
22
16
16
13
SWITCHING WAVEFORMS
I
1-0
tSI
tHI
D15-0
tSD
tHD
tPW
CLK
tPW
S1-0
tPD
tSEL
OE
tDIS
tENA
HIGH IMPEDANCE
Y
15-0
Pipeline Registers
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3
LPR520/521
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with the point of view of the device. Output
specifications only. Functional oper- input transition times less than 3 ns, delay, for example, is specified as a
ation of these products at values be- output reference levels of 1.5 V (except maximumsinceworst-caseoperationof
yond those indicated in the Operating tENA/tDIS test), and input levels of anydevicealwaysprovidesdatawithin
Conditions table is not implied. Expo- nominally 0 to 3.0 V. Output loading that time.
sure to maximum rating conditions for may be a resistive divider which
extended periods may affect reliability. provides for specifiedIOH andIOL at an
11. Transition is measured ±200 mV
from steady-state voltage with speci-
fied loading.
output voltage of VOH min and VOL
2. The products described by this spec-
ification include internal circuitry de-
signedto protect the chipfrom damag-
ing substrate injection currents and ac-
cumulations of static charge. Never-
theless, conventional precautions
should be observed during storage,
handling, and use of these circuits in
order to avoid exposure to excessive
electrical stress values.
max respectively. Alternatively, a
diode bridge with upper and lower
current sources of IOH and IOL
respectively, and a balancing voltage of
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
1.5 V may be used.
Parasitic
capacitance is 30 pF minimum, and
may be distributed. For tENABLE and
tDISABLE measurements, the load
current is increased to 10 mA to reduce
the RC delay component of the
measurement.
FIGURE 1. THRESHOLD LEVELS
t
DIS
tENA
OE
0.2 V
0.2 V
HIGH IMPEDANCE
3. This device provides hard clamping
of transient undershoot and overshoot.
Input levels below ground or aboveVCC
will be clamped beginning at –0.6 V and
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
range of –0.5 V to +7.0 V. Device opera-
tion will not be adversely affected, how-
TRISTATE
OUTPUTS
This device has high-speed outputs ca-
pable of large instantaneous current
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in
the testing of this device. The following
measures are recommended:
0.2 V
0.2 V
ever, input current levels will be well in a. A 0.1 µF ceramic capacitor should be
excess of 100 mA.
installed between VCC and Ground
leads as close to the Device Under Test
(DUT) as possible. Similar capacitors
should be installed between deviceVCC
and the tester common, and device
ground and tester common.
4. Actual test conditions may vary
from those designated but operation is
guaranteed as specified.
5. Supply current for a given applica-
tion can be accurately approximated
by:
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
2
NCV F
4
c. Input voltages should be adjusted to
compensate for inductive ground and
VCC noise to maintain required DUT
input levels relative to the DUT ground
pin.
where
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirementsofallparts. Responsesfrom
the internal circuitry are specified from
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
Pipeline Registers
06/30/95–LDS.P520/1-K
4
LPR520/521
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
LPR520 — ORDERING INFORMATION
40-pin — 0.6" wide
44-pin
I0
I1
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
S0
2
D0
3
S1
D1
4
Y0
6
5
4
3
2
1
44 43 42 41 40
39
D2
5
Y1
7
D3
D4
NC
Y2
D3
6
Y2
8
38
37
36
35
34
33
32
31
30
29
D4
7
Y3
9
D5
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
D5
8
Y4
10
11
12
13
14
15
16
17
D6
D6
9
Y5
D7
D7
10
11
12
13
14
15
16
17
18
19
20
Y6
Top
View
D8
D8
Y7
D9
D9
Y8
D10
D11
D12
NC
D10
D11
D12
D13
D14
D15
CLK
GND
Y9
Y10
Y11
Y12
Y13
Y14
Y15
OE
18 19 20 21 22 23 24 25 26 27 28
Plastic DIP
(P3)
Ceramic DIP
(C11)
Plastic J-Lead Chip Carrier
(J1)
Ceramic Leadless
Chip Carrier (K2)
Speed
0°C to +70°C — COMMERCIAL SCREENING
25 ns
22 ns
15 ns
LPR520PC25
LPR520PC22
LPR520PC15
LPR520JC25
LPR520JC22
LPR520JC15
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
LPR520CMB30
30 ns
24 ns
18 ns
LPR520KMB30
LPR520KMB24
LPR520KMB18
LPR520CMB24
LPR520CMB18
Pipeline Registers
06/30/95–LDS.P520/1-K
5
LPR520/521
DEVICES INCORPORATED
4 x 16-bit Multilevel Pipeline Register
LPR521 — ORDERING INFORMATION
40-pin — 0.6" wide
44-pin
I0
I1
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
S0
2
D0
3
S1
D1
4
Y0
6
5
4
3
2
1
44 43 42 41 40
39
D2
5
Y1
7
D3
D4
NC
Y2
D3
6
Y2
8
38
37
36
35
34
33
32
31
30
29
D4
7
Y3
9
D5
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
D5
8
Y4
10
11
12
13
14
15
16
17
D6
D6
9
Y5
D7
Top
View
D7
10
11
12
13
14
15
16
17
18
19
20
Y6
D8
D8
Y7
D9
D9
Y8
D10
D11
D12
NC
D10
D11
D12
D13
D14
D15
CLK
GND
Y9
Y10
Y11
Y12
Y13
Y14
Y15
OE
18 19 20 21 22 23 24 25 26 27 28
Plastic DIP
(P3)
Ceramic DIP
(C11)
Plastic J-Lead Chip Carrier
(J1)
Ceramic Leadless
Chip Carrier (K2)
Speed
0°C to +70°C — COMMERCIAL SCREENING
25 ns
22 ns
15 ns
LPR521PC25
LPR521PC22
LPR521PC15
LPR521JC25
LPR521JC22
LPR521JC15
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
LPR521CMB30
30 ns
24 ns
18 ns
LPR521KMB30
LPR521KMB24
LPR521KMB18
LPR521CMB24
LPR521CMB18
Pipeline Registers
06/30/95–LDS.P520/1-K
6
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