LR24C256 [LRC]
Bi-directional Data Transfer Protocol;
| 型号： | LR24C256 |
| 厂家： | 
LESHAN RADIO COMPANY |
| 描述： | Bi-directional Data Transfer Protocol |
| 文件： | 总14页 (文件大小：607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LESHAN RADIO COMPANY, LTD.
128K bits (16,384 X 8) / 256K bits (32,768 X 8) Two-wire Serial EEPROM
Two-wire Serial EEPROM
LR 24C128/LR 24C256
ꢀFeatures
ꢁ
ꢁ
ꢁ
ꢁ
Two-wire Serial Interface
VCC = 1.8V to 5.5V
Bi-directional Data Transfer Protocol
Internally Organized
LR24C128, 16,384 X 8 (128K bits)
LR24C256, 32,768 X 8 (256K bits)
400 kHz (1.8V, 2.7V, 5V) Compatibility
64-byte Page (128K/256K) Write Modes
Partial Page Writes Allowed
Self-timed Write Cycle (5 ms max)
High-reliability
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
1 Million Write Cycles guaranteed
Data Retention > 100 Years
Operating Temperature: -40
to +85
8-lead PDIP, 8-lead SOP and 8-lead TSSOP Packages
ꢀPin Configuration
ꢀOrdering Infomation
LR24Cxxx: PDIP8
LR24CxxxD: SOP8
LR24CxxxT: TSSOP8
ꢀDescription
LR24C128/LR24C256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where
low-power and low-voltage operations are essential. The LR24C128/LR24C256 is available in
space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a
two-wire serial interface.
1
LESHAN RADIO COMPANY, LTD.
ꢀPin Descriptions
Block Diagram
2
LESHAN RADIO COMPANY, LTD.
DEVICE/PAGE ADDRESSES ( A1 and A0): The A1 and A0 pins are device address inputs that are hard wired for the
24C128 / 24C256. Four 128k/256k devices may be addressed on a single bus system (device addressing is discussed in detail
under the Device Addressing section).
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed
with any number of other open-drain or open- collector devices.
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock
data out of each device.
WRITE PROTECT (WP): The 24C128/ 24C256 has a Write Protect pin that provides hardware data protection. The Write
Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC,
the write protection feature is enabled and operates as shown in the following Table 2.
Functional Description
1. Memory Organization
24C128, 128K SERIAL EEPROM: The 128K is internally organized as 256 pages of 64 bytes each.
Random word addressing requires a 14-bit data word address.
24C256, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64 bytes each.
Random word addressing requires a 15-bit data word address.
2. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods (see Figure 1). Data changes during SCL high periods will
indicate a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see Figure 2).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (see Figure 2)
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a “0” to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The LR24C128/LR24C256 features a low-power standby mode which is enabled: (a) upon
power-up and (b) after the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by
following these steps:
1.
2.
3.
Clock up to 9 cycles.
Look for SDA high in each cycle while SCL is high.
Create a start condition.
3
LESHAN RADIO COMPANY, LTD.
Figure 1. Data Validity
Figure 2. Start and Stop Definition
Figure 3. Output Acknowledge
4
LESHAN RADIO COMPANY, LTD.
3. Device Addressing
The 128K/256K EEPROM devices all require an 8-bit device address word following a start condition to
enable the chip for a read or write operation (see Figure 4).
The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits
as shown. This is common to all the Serial EEPROM devices.
The 128K/256K uses the three device address bits A1, A0 to allow as many as four devices on the same
bus. These bits must compare to their corresponding hardwired input pins. The A1 and A0 pins use an
internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if
this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip
will return to a standby state.
DATA SECURITY: The LR24C128/LR24C256 has a hardware data protection scheme that allows the
user to write protect the entire memory when the WP pin is at VCC.
4. Write Operations
BYTE WRITE: A write operation requires two 8-bit data word address following the device address word
and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”
and the addressing device, such as a microcontroller, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory.
All inputs are disabled during this write cycle and the EEPROM will not respond until the write is
complete (see Figure 5).
PAGE WRITE: The 128K/256K devices are capable of 64-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition
after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data
word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a “0”
after each data word received. The microcontroller must terminate the page write sequence with a stop
condition (see Figure 6).
The data word address lower six (128K/256K) bits are internally incremented following the receipt of
each data word. The higher data word address bits are not incremented, retaining the memory page row
location. When the word address, internally generated, reaches the page boundary, the following byte is
placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM,
the data word address will “roll over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs
are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by
the device address word. The read/write bit is representative of the operation desired. Only if the internal
write cycle has completed will the EEPROM respond with a “0”, allowing the read or write sequence to
continue.
5. Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write
select bit in the device address word is set to “1”. There are three read operations: current address read,
random address read and sequential read.
5
LESHAN RADIO COMPANY, LTD.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address
accessed during the last read or write operation, incremented by one. This address stays valid between
operations as long as the chip power is maintained. The address “roll over” during read is from the last
byte of the last memory page to the first byte of the first page. The address “roll over” during write is from
the last byte of the current page to the first byte of the same page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond
with an input “0” but does generate a following stop condition (see
Figure 7).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word
address. Once the device address word and data word address are clocked in and acknowledged by the
EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a
current address read by sending a device address with the read/write select bit high. The EEPROM
acknowledges the device address and serially clocks out the data word. The microcontroller does not
respond with a “0” but does generate a following stop condition (see Figure 9).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random
address read. After the microcontroller receives a data word, it responds with an acknowledge. As long
as the EEPROM receives an acknowledge, it will continue to increment the data word address and
serially clock out sequential data words. When the memory address limit is reached, the data word
address will “roll over” and the sequential read will continue. The sequential read operation is
terminated when the microcontroller does not respond with a “0” but does generate a following stop
condition (see
Figure 10)
Figure 4. Device Address
Figure 5. Byte Write
Figure 6. Page Write
6
LESHAN RADIO COMPANY, LTD.
Figure 7. Current Address Read
Figure 8. Random Read
Figure 9. Sequential Read
7
LESHAN RADIO COMPANY, LTD.
ꢀElectrical Characteristics
8
LESHAN RADIO COMPANY, LTD.
9
LESHAN RADIO COMPANY, LTD.
AC Electrical Characteristics
10
LESHAN RADIO COMPANY, LTD.
Bus Timing
Figure 10. SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing
Figure 11. SCL: Serial Clock, SDA: Serial Data I/O
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the
end of the internal clear/write cycle.
Note:
11
LESHAN RADIO COMPANY, LTD.
Package Information
PDIP Outline Dimensions
1. This drawing is for general information only; refer to JEDEC Drawing MS-001,
Variation BA for additional information.
Note:
2. Dimensions A and L are measured with the package seated in JEDEC seating
plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or
protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar
protrusions shall not exceed 0.010 (0.25 mm).
12
LESHAN RADIO COMPANY, LTD.
JEDEC SOIC
Note: 1. These drawings are for general information only. Refer to JEDEC Drawing
MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
13
LESHAN RADIO COMPANY, LTD.
TSSOP
Note: 1. This drawing is for general information only. Refer to JEDEC Drawing
MO-153, Variation AA, for proper dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold
Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead
Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar
protrusion shall be 0.08 mm total in excess of the b dimension at maximum
material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
14
相关型号：
©2020 ICPDF网 联系我们和版权申明