LY24C08SL_技术文档

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

REVISION HISTORY

Revision

Rev. 0.1

Rev. 0.2

Rev. 0.3

Rev. 0.4

Description

Initial Issue

Edit package

Edit A0, A1, A2 address pins

Issue Date

October.06.2005

October.21.2005

December.06.2005

December.12.2005

Integral 2K, 4K, 8K, 16K datasheet

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

1

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

FEATURES

GENERAL DESCRIPTION

2-wire serial interface

Automatic word address increment

Operating voltage:1.8V~5.5V

Operating current

Maximum write current: <3mA at 5.5V

Maximum read current: <0.5mA at 5.5V

Maximum stand-by current: <5uA at 5.5V

16-byte page buffer

Hardware controlled write protection

EEPROM programming voltage generated on

chip

The LY24C02/04/08/16 is a 2,048 / 4,096 / 8192 /

16,384-bit serial read/write non-volatile memory

device, supporting the standard 2 wire serial

interface. It is fabricated using most advanced

CMOS technology. It has been developed for low

power and low voltage application (1.8V to

5.5V).The LY24C02/04/08/16 is guaranteed for

1,000,000 erase/write cycles and 100 years data

retention.

1,000,000 erase/write cycle

100 years data retention

Operating temperature range

℃

to +70 (commercial)

0

，

8-pin DIP SOP TSSOP package

Lead free and green package available

FUNCTIONAL BLOCK DIAGRAM

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

2

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

PIN CONFIGURATION

Note: The LY24C02/04/08/16 is available in 8-pin DIP, SOP, TSSOP package.

PIN DESCRIPTION

TYPE

Input

I/O

SYMBOL

A0 – A2

SDA

DESCRIPTION

Device Address Inputs

Serial Data Inputs/Outputs

Serial clock Input

Write protect Input

Power Supply

Input

---

SCL

WP

V_CC

---

V_SS

Ground

ABSOLUTE MAXIMUN RATINGS

PARAMETER

Supply voltage

SYMBOL

Vcc

RATING

-0.3 to +6.5

0 to 70

UNIT

V

Input voltage

Vin

V

Output voltage

Vo

V

℃

Operating temperature

Storage Temperature

TA

TSTG

-65 to 150

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

3

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

DC ELECTRICAL CHARACTERISTICS

SYMBOL

Vcc

TEST CONDITION

MIN.

1.8

-0.3

MAX.

5.5

0.3 Vcc

UNIT

PARAMETER

Power Supply

V

Input Low Voltage

Input High Voltage

Input Leakage Current

Output Leakage

Current

V_IL

V_IH

I_LI

SCL, SDA, A0, A1, A2

V_IN=0 to V_CC

0.7 Vcc Vcc+0.3

-

10

A

µ

I_LO

V_OUT=0 to V_CC

10

A

µ

Output Low Voltage

V_OL

I_OL= 0.15mA,Vcc=1.8V

I_OL= 2.1mA, Vcc=2.5V

Minimum cycle= 400kHz

0.2

0.4

3

V

Write

Read

Icc_w

Icc_r

Power Supply

Current

mA

Minimum cycle= 400kHz

Vcc=SDA=SCL=5.5V

All other inputs =0V

0.5

Standby Power Supply

Current

5

Isb

-

uA

Notes:

℃

℃ ℃

to +85 (I), V_CC=1.8V to 5.5V

1. T_A=-25

to 70 (C), -40

D.C. Electrical Characteristics (Continued)

PARAMETER

SYMBOL

Conditions

MIN.

MAX

UNIT

℃

25 , 1MHz,

Vcc=5V,V_IN=0V

A0,A1,A2 SCL and WP pin

Input Capacitance

C_IN

10

pF

-

℃

25 , 1MHz,

Input/Output Capacitance

C_I/O

pF

Vcc=5V,V_I/o=0V

SDA pin

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

4

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

AC ELECTRICAL CHARACTERISTICS

PARAMETER

SYM.

UNIT

Conditions Vcc = 1.8 to 5.5V Vcc = 2.5 to 5.5V

(Standard Mode) (Fast Mode)

MIN.

MAX.

MIN.

MAX.

External clock frequency

Clock high time

Clock low time

Rising time

Falling time

Start condition hold time

Start condition setup time

Data input hold time

Data input setup time

Stop condition setup time

f_CLK

t_HIGH

t_LOW

t_R

t_F

t_HD:STA

t_SU:STA

t_HD:DAT

t_SU:DAT

t_SU:STO

-

0

4

4.7

-

4

4.7

0

0.25

4

100

-

1

0.3

-

0

0.6

1.3

-

400

-

0.3

-

kHz

us

SDA, SCL

-

0.6

0

0.1

0.6

-

Before new

transmission

Bus free time

t_BUF

4.7

-

1.3

-

Data output valid from clock low_(note)t_AA

-

0.3

-

3.5

100

5

-

0.9

50

5

us

ns

ms

Noise spike width

Write cycle time

Notes:

t_SP

t_WR

1. Upon customers request up to 400 kHz (Max.)in standard mode and 1 MHz in fast mode are available.

2. When acting as a transmitter, the LY24C02/04/08/16 must provide an internal minimum delay time to bridge the undefined (minimum 300

ns)

Of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition.

FUNCTION DESCRIPTION

I²C-BUS INTERFACE

The LY24C02/04/08/16 supports the I²C-bus serial interface data transmission protocol.

The 2-wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines

must be connected to VCC by a pull-up resistor that is located somewhere on the bus.

Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the

bus is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop

conditions, controlling bus access. The A2, A1 and A0 pins are device address inputs that are hard wired for

the LY24C02/04/08/16. As many as eight for 2K (four for 4K,two for 8K, one for 16K )devices may be

addressed on a single bus system.

A0, A1, A2

The A0, A1 and A2 pins are device address inputs that are hard wired for the LY24C02. As many as eight for

2K devices may be addressed on a single bus system.

The LY24C04 uses A1 and A2 pins for hard wire addressing and a total of four 4K devices may be addressed

on a single bus system. The A0 pin is not connected in the LY24C04.

The LY24C08 only use the A2 input for hard wire addressing and a total of two 8K devices may be addressed

on a single bus system. The A0 and A1 pins are no connects in the LY24C08.

The LY24C16 does not use the A0, A1, A2 device address pins. so the A0, A1, A2 pins have no connection.

I²C-BUS PROTOCOLS

Here are several rules for I²C-bus transfers:

— A new data transfer can be initiated only when the bus is currently not busy.

— MSB is always transferred first in transmitting data.

— During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

5

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

The I2C-bus interface supports the following communication protocols:

• Bus not busy: The SDA and the SCL lines remain High level when the bus is not active.

• Start condition: Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains

High level. All bus commands must be preceded by a start condition.

• Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains

High level. All bus operations must be completed by a stop condition

Note: Data transmission sequence

• Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration

of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock

pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total

number of bytes that can be transferred in one operation is theoretically unlimited.

• ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The

transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which

the master generates, the receiver pulls the SDA line low to acknowledge that it successfully received the

eight bits of data (see Figure 3-8). But the slave does not send an ACK if an internal write cycle is still in

progress.

In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors

the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to

transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition

to be issued by the master before returning to its stand-by mode.

Note: Acknowledge response from receiver

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

6

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

BYTE WRITE OPERATION

In a complete byte write operation, the master transmits the slave address, word address, and one data byte

to the LY24C02/04/08/16 slave device

Note: Byte write operation

Following the Start condition, the master sends the device identifier (4 bits), the device address (3 bits), and

an R/W bit set to “0” onto the bus. Then the addressed LY24C02/04/08/16 generates an ACK and waits for the

next byte. The next byte to be transmitted by the master is the word address. This 8-bit address is written into

the word address pointer of the LY24C02/04/08/16

When the LY24C02/04/08/16 receives the word address, it responds by issuing an ACK and then waits for the

next 8-bit data. When it receives the data byte, the LY24C02/04/08/16 again responds with an ACK. The

master terminates the transfer by generating a Stop condition, at which time the LY24C02/04/08/16 begins

the internal write cycle.

While the internal write cycle is in progress, all LY24C02/04/08/16 inputs are disabled and the

LY24C02/04/08/16 does not respond to additional requests from the master.

PAGE WRITE OPERATION

The LY24C02/04/08/16 can also perform 16-byte page write operation. A page write operation is initiated in

the same way as a byte write operation. However, instead of finishing the write operation after the first data

byte is transferred, the master can transmit up to 15 additional bytes. The LY24C02/04/08/16 responds with

an ACK each time it receives a complete byte of data.

Note: Page write operation

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

7

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

The LY24C02/04/08/16 automatically increments the word address pointer each time it receives a complete

data byte. When one byte has been received, the internal word address pointer increments to the next

address and the next data byte can be received.

If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation,

the LY24C02/04/08/16 word address pointer value “rolls over” and the previously received data is overwritten.

If the master transmits less than 16 bytes and generates a stop condition, the LY24C02/04/08/16 writes the

received data to the corresponding EEPROM address.

During a page write operation, all inputs are disabled and there is no response to additional requests from the

master until the internal write cycle is completed.

POLLING FOR AN ACK SIGNAL

When the master issues a stop condition to initiate a write cycle, the LY24C02/04/08/16 starts an internal

write cycle. The master can then immediately begin polling for an ACK from the slave device.

To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave

address. As long as the LY24C02/04/08/16 remains busy with the write operation, no ACK is returned. When

the LY24C02/04/08/16 completes the write operation, it returns an ACK and the master can then proceed with

the next read or write operation.

Note: Master polling for an ACK signal from a slave device

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

8

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

HARDWARE-BASED WRITE PROTECTION

You can also write-protect the entire memory area of the LY24C02/04/08/16. This method of write protection

is controlled by the state of the Write Protect (WP) pin.

When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored.The

LY24C02/04/08/16 will acknowledge slave and word address, but it will not generate an acknowledge after

receiving the first byte of the data. Thus the write cycle will not be started when the stop condition is generated.

By connecting the WP pin to VSS, the write function is allowed for the entire memory.

These write protection features effectively change the EEPROM to a ROM in order to prevent data from being

overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged

on the bus, but data bytes are not acknowledged.

CURRENT ADDRESS BYTE READ OPERATION

The internal word address pointer maintains the address of the last word accessed, incremented by one.

Therefore, if the last access (either read or write) was to the address “n”, the next read operation would

access data at address “n+1”.

When the LY24C02/04/08/16 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends

the eight bits of data. The master does not acknowledge the transfer but it does generate a Stop condition. In

this way, the LY24C02/04/08/16 effectively stops the transmission.

Note: Current address byte read operation

RANDOM ADDRESS BYTE READ OPERATION

Using random read operations, the master can access any memory location at any time. Before it issues the

slave address with the R/W bit set to “1”, the master must first perform a “dummy” write operation. This

operation is performed in the following steps:

1. The master first issues a Start condition, the slave address, and the word address to be read. (This step

sets the internal word address pointer of the LY24C02/04/08/16 to the desired address.)

2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed

by another slave address, with the R/W bit set to “1”.

3. TheLY24C02/04/08/16 then sends an ACK and the 8-bit data stored at the desired

address.

4. At this point, the master does not acknowledge the transmission, but generates a stop condition instead.

5. In response, the LY24C02/04/08/16 stops transmitting data and reverts to its stand-by mode.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

9

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

Note: Random address byte read operation

SEQUENTIAL READ OPERATION

Sequential read operations can be performed in two ways: as a series of current address reads or as random

address reads. The first data is sent in the same way as the previous read mode used on the bus. The next

time,however, the master responds with an ACK, indicating that it requires additional data.

The LY24C02/04/08/16 continues to output data for each ACK it receives. To stop the sequential read

operation, the master does not respond with an ACK, but instead issues a Stop condition.

Using this method, data is output sequentially with the data from address “n” followed by the data from “n+1”.

The word address pointer for read operations increments all word addresses, allowing the entire EEPROM to

be read sequentially in a single operation. After the entire EEPROM is read, the word address pointer “rolls

over” and the LY24C02/04/08/16 continues to transmit data for each ACK it receives from the master.

Note: Sequential read operation

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

10

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

PACKAGE OUTLINE DIMENSION

8-pin 150mil SOP Package Outline Dimension

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

11

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

8-pin TSSOP Package Outline Dimension

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

12

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

8-pin 300mil PDIP Package Outline Dimension

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

13

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

Ordering information

W

LY24C

Z

XXV

Z : Temperature Range

Blank: (Commercial 0°C~ 70°C

)

W : Lead Information

N : Normal

L : Lead Free

V : Package Type

S : 8 -pin 150 mil SOP

8-pin

R :

TSSOP

XX: Memory Density

02 : 2K

04 : 4K

08 : 8K

16 :16K

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

14

®

LY24C02/04/08/16

2K/4K/8K/16K-bit 2-Wire Serial EEPROM

Preliminary. 0.4

THIS PAGE IS LEFT BLANK INTENTIONALLY.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

40 Hsuch-Fu Rd., Hsinchu, Taiwan.

TEL: 886-3-5165511

FAX: 886-3-5165522

15


型号：	LY24C08SL
厂家：	Lyontek Inc.
描述：	EEPROM, 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总15页 (文件大小：212K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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