概述
数据手册LY61L12816GL-25LLET 概述
128K X 16 BIT HIGH SPEED CMOS SRAM
LY61L12816GL-25LLET 数据手册
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LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Description
Initial Issued
Issue Date
May.26.2008
Aug.26.2009
PACKAGE OUTLINE DIMENSION
Revised
Rev. 1.2
Revised VTERM to VT1 and VT2
Aug.27.2009
Revised Test Condition of ICC/ISB1/IDR
FEATURES ORDERING INFORMATION
Revised
&
Lead free and green package available to Green package
available
ABSOLUTE MAXIMUN RATINGS
Deleted TSOLDER in
ORDERING INFORMATION
Added packing type in
Added I grade Spec.
Rev. 1.3
Rev. 1.4
Rev. 1.5
Apr.13.2010
May.6.2010
Aug.25.2010
Added package type TFBGA
ORDERING INFORMATION
Revised
Added E grade
in page 12
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
FEATURES
GENERAL DESCRIPTION
The LY61L12816 is a 2,087,152-bit low power
CMOS static random access memory organized as
131,072 words by 16 bits. It is fabricated using very
high performance, high reliability CMOS technology.
Its standby current is stable within the range of
operating temperature.
Fast access time : 10/12/15/20/25ns
Very low power consumption:
Operating current(Normal version):
200/180/150/110/90mA(TYP.)
Operating current(15/20/25ns LL version):
45/40/35mA(TYP.)
Standby current(Normal version):
0.5mA(TYP.)
Standby current(15/20/25ns LL version):
The LY61L12816 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
20 A(TYP.)
µ
Single 3.3V power supply
All inputs and outputs TTL compatible
Fully static operation
The LY61L12816 operates from a single power
supply of 3.3V and all inputs and outputs are fully
TTL compatible
Tri-state output
Data byte control : LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
Data retention voltage : 2.0V (MIN.)
Green package available
Package : 44-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Power Dissipation
Speed
Product
Family
LY61L12816
LY61L12816(E)
LY61L12816(I)
LY61L12816
Operating
Temperature
0 ~ 70℃
Vcc Range
Standby(ISB1,TYP.) Operating(Icc,TYP.)
3.15 ~ 3.6V
3.15 ~ 3.6V
3.15 ~ 3.6V
3.0 ~ 3.6V
3.0 ~ 3.6V
10/12ns
10/12ns
0.5mA
0.5mA
200/180mA
200/180mA
-20 ~ 80℃
-40 ~ 85℃
0 ~ 70℃
10/12ns
0.5mA
200/180mA
15/20/25ns
15/20/25ns
0.5mA
150/110/90mA
45/40/35mA(LL)
0 ~ 70℃
LY61L12816(LL)
20µA(LL)
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A16
Address Inputs
Vcc
Vss
DQ0 – DQ15 Data Inputs/Outputs
CE#
WE#
OE#
LB#
UB#
VCC
Chip Enable Input
Write Enable Input
Output Enable Input
Lower Byte Control
Upper Byte Control
Power Supply
128Kx16
MEMORY ARRAY
A0-A16
DECODER
VSS
Ground
DQ0-DQ7
Lower Byte
I/O DATA
CIRCUIT
COLUMN I/O
DQ8-DQ15
Upper Byte
CE#
WE#
OE#
LB#
CONTROL
CIRCUIT
UB#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
PIN CONFIGURATION
A4
A3
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A2
3
A7
A1
4
OE#
UB#
LB#
DQ15
DQ14
DQ13
DQ12
Vss
A0
5
CE#
DQ0
DQ1
DQ2
DQ3
Vcc
Vss
DQ4
DQ5
DQ6
DQ7
WE#
A16
A15
A14
A13
A12
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Vcc
LB# OE# A0
DQ8 UB# A3
DQ9 DQ10 A5
Vss DQ11 NC
A1
A2 NC
A
B
C
D
E
F
DQ11
DQ10
DQ9
DQ8
NC
A4 CE# DQ0
A6 DQ1 DQ2
A7 DQ3 Vcc
Vcc DQ12 NC A16 DQ4 Vss
DQ14 DQ13 A14 A15 DQ5 DQ6
DQ15 NC A12 A13 WE# DQ7
A8
A9
G
H
A10
A11
NC
NC
1
A8
2
A9 A10 A11 NC
3
4
5
6
TSOP II
TFBGA
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
SYMBOL
VT1
RATING
UNIT
V
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
-0.5 to 4.6
VT2
-0.5 to VCC+0.5
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
V
℃
Operating Temperature
TA
℃
W
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
1
IOUT
50
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
TRUTH TABLE
I/O OPERATION
MODE
CE# OE# WE# LB# UB#
SUPPLY CURRENT
DQ0-DQ7
High – Z
High – Z
High – Z
DOUT
High – Z
DOUT
DIN
High – Z
DIN
DQ8-DQ15
High – Z
High – Z
High – Z
High – Z
DOUT
DOUT
High – Z
DIN
Standby
H
L
L
L
L
L
L
L
L
X
H
X
L
L
L
X
X
X
X
H
X
H
H
H
L
X
X
H
L
H
L
L
H
L
X
X
H
H
L
L
H
L
ISB1
ICC
Output Disable
Read
Write
ICC
L
L
ICC
L
DIN
Note: H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
-10/12
MIN.
3.15
3.0
2.2
- 0.3
- 1
TYP. *4 MAX.
UNIT
PARAMETER
Supply Voltage
3.3
3.3
3.6
3.6
V
V
V
V
VCC
-15/20/25
*1
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
VIH
VIL
-
-
-
VCC+0.3
0.6
*2
ILI
V
V
CC ≧ VIN ≧ VSS
CC ≧ VOUT ≧ VSS,
Output Disabled
IOL = 8mA
1
A
µ
ILO
- 1
-
1
A
µ
Output High Voltage
Output Low Voltage
VOH IOH = -4mA
VOL
2.4
-
-
V
V
-
-
-
-
-
-
-
-
-
-
0.4
250
220
200
150
115
60
200
180
150
110
90
10
12
mA
mA
mA
mA
mA
mA
mA
mA
15
20
25
15LL
20LL
25LL
Cycle time = Min.
CE# = VIL , II/O = 0mA
Others at VIL or VIH
Average Operating
Power supply Current
ICC
45
40
50
35
45
5*5
50*6
mA
CE# ≧VCC - 0.2V
Others at 0.2V or
Normal
-
-
0.5
10
Standby Power
Supply Current
ISB1
15/20/25LL
A
µ
VCC - 0.2V
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25
5. 1mA for special request
6. 20 A for special request
µ
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
MIN.
-
-
MAX
8
10
UNIT
pF
pF
CIN
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.2V to VCC - 0.2V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -8mA/16mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
LY61L12816 LY61L12816 LY61L12816 LY61L12816 LY61L12816
-10 -12 -15 -20 -25
PARAMETER
SYM.
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
LB#, UB# Access Time
tRC
tAA
tACE
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
tBA
10
-
-
-
10
10
5
-
12
-
-
-
12
12
6
-
15
-
-
-
15
15
7
-
20
-
-
-
20
20
8
-
25
-
-
-
25
25
9
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
*
*
*
*
2
0
-
-
3
-
3
0
-
-
3
-
4
0
-
-
3
-
4
0
-
-
3
-
4
0
-
-
3
-
-
-
-
-
-
5
5
-
5
5
-
6
6
-
6
6
-
7
7
-
7
7
-
8
8
-
8
8
-
9
9
-
9
9
-
LB#, UB# to High-Z Output
LB#, UB# to Low-Z Output
tBHZ
tBLZ
*
*
-
2
-
3
-
4
-
4
-
4
(2) WRITE CYCLE
PARAMETER
LY61L12816 LY61L12816 LY61L12816 LY61L12816 LY61L12816
-10 -12 -15 -20 -25
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SYM.
UNIT
Write Cycle Time
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
10
8
8
0
8
0
6
0
2
-
-
-
-
-
-
-
-
-
-
6
-
12
10
10
0
9
0
7
0
3
-
-
-
-
-
-
-
-
-
-
7
-
15
12
12
0
10
0
8
0
4
-
-
-
-
-
-
-
-
-
-
8
-
20
16
16
0
11
0
9
0
5
-
-
-
-
-
-
-
-
-
-
9
-
25
20
20
0
12
0
10
0
6
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
LB#, UB# Valid to End of Write
tOW
tWHZ
tBW
*
*
-
20
10
-
8
10
12
16
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
Dout
tAA
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
LB#,UB#
tBA
OE#
tOE
tOH
tOLZ
tBLZ
tCLZ
tOHZ
tBHZ
tCHZ
High-Z
Dout
High-Z
Data Valid
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
tBW
tWP
LB#,UB#
WE#
tAS
tWR
tWHZ
TOW
High-Z
Dout
(4)
(4)
tDW
tDH
Din
Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
tBW
LB#,UB#
tWP
WE#
Dout
Din
tWHZ
High-Z
(4)
tDW
tDH
Data Valid
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
WRITE CYCLE 3 (LB#,UB# Controlled)
(1,2,5,6)
tWC
Address
tAW
tWR
CE#
tAS
tCW
tBW
LB#,UB#
WE#
tWP
tWHZ
High-Z
Dout
Din
(4)
tDW
tDH
Data Valid
Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
SYMBOL
TEST CONDITION
CE# ≧ VCC - 0.2V
CC = 2.0V
MIN.
2.0
TYP. MAX. UNIT
VDR
-
3.6
V
V
Normal
-
-
0.3
1
mA
CE# ≧ VCC - 0.2V
Others at 0.2V or
VCC - 0.2V
Data Retention Current
IDR
15/20/25(LL)
5
30
A
µ
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
VDR ≧ 2.0V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
PACKAGE OUTLINE DIMENSION
Ⅱ
44-pin 400mil TSOP-
Package Outline Dimension
DIMENSIONS IN MILLMETERS
DIMENSIONS IN MILS
SYMBOLS
MIN.
-
NOM.
-
MAX.
1.20
0.15
1.05
0.45
0.21
18.618
12.014
10.363
-
MIN.
NOM.
-
MAX.
A
A1
A2
b
-
47.2
5.9
41.3
17.7
8.3
733
473
408
-
0.05
0.95
0.30
0.12
18.212
11.506
9.957
-
0.10
1.00
-
2.0
37.4
11.8
4.7
717
453
392
-
3.9
39.4
-
c
-
-
D
18.415
11.760
10.160
0.800
0.50
0.805
-
725
463
400
31.5
19.7
31.7
-
E
E1
e
L
0.40
-
0.60
-
15.7
-
23.6
-
ZD
y
-
0o
0.076
6o
-
0o
3
6o
3o
3o
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
48-ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
ORDERING INFORMATION
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
®
LY61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.5
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
13
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