LY61L20498AGL-10T [LYONTEK]
Standard SRAM,;
| 型号： | LY61L20498AGL-10T |
| 厂家： | 
Lyontek Inc. |
| 描述： | Standard SRAM, 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
REVISION HISTORY
Revision
Rev. 1.0
Description
Initial Issue
Issue Date
Oct.21.2014
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
FEATURES
GENERAL DESCRIPTION
The LY61L20498A is a 16M-bit high speed CMOS
static random access memory organized as 2048K
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
Fast access time : 10ns
Low power consumption:
Operating current : 70mA (TYP.)
Standby current : 4mA(TYP.)
Single 3.3V power supply
All inputs and outputs TTL compatible
Fully static operation
The LY61L20498A operates from a single power
supply of 3.3V and all inputs and outputs are fully
TTL compatible
Tri-state output
Data retention voltage : 1.5V (MIN.)
Green package available
Package : 54-pin 400 mil TSOP-II
48-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Power Dissipation
Speed
Product
Family
LY61L20498A
Operating
Temperature
0 ~ 70℃
V
CC Range
Standby(ISB1,TYP.) Operating(ICC,TYP.)
2.7 ~ 3.6V
2.7 ~ 3.6V
10ns
10ns
4mA
4mA
70mA
70mA
-40 ~ 85℃
LY61L20498A(I)
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
Address Inputs
A0 – A20
Vcc
Vss
DQ0 – DQ7 Data Inputs/Outputs
CE#, CE2
WE#
OE#
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
2048Kx8
MEMORY ARRAY
A0-A20
DECODER
VCC
VSS
Ground
NC
No Connection
I/O DATA
CIRCUIT
DQ0-DQ7
COLUMN I/O
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
PIN CONFIGURATION
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
SYMBOL
VT1
RATING
-0.5 to 4.6
-0.5 to VCC+0.5
0 to 70(C grade)
-40 to 85(I grade)
-65 to 150
1
UNIT
V
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
VT2
V
℃
Operating Temperature
TA
℃
W
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
IOUT
50
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
CE#
H
CE2
X
OE#
X
WE#
X
SUPPLY CURRENT
MODE
I/O OPERATION
High-Z
ISB1
ISB1
ICC
ICC
ICC
Standby
High-Z
X
L
X
X
Output Disable
Read
High-Z
L
H
H
H
DOUT
L
H
L
H
Write
DIN
L
H
X
L
Note: H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYM.
TEST CONDITION
MIN.
2.7
2.2
- 0.3
- 1
TYP. *4 MAX.
UNIT
PARAMETER
Supply Voltage
VCC
3.3
3.6
VCC+0.3
0.8
V
V
V
*1
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
VIH
VIL
-
-
-
*2
ILI
V
V
CC ≧ VIN ≧ VSS
CC ≧ VOUT ≧ VSS,
Output Disabled
1
A
µ
ILO
- 1
-
1
A
µ
Output High Voltage
Output Low Voltage
VOH IOH = -4mA
VOL IOL = 8mA
2.4
-
-
-
-
V
V
0.4
Average Operating
Power supply
Current
Standby Power
Supply Current
Notes:
CE# ≤0.2V and CE2≧ VCC-0.2V,
-10
-12
-
-
70
65
120
110
mA
ICC
other pins at 0.2V or VCC-0.2V,
I/O = 0mA; f=max.
mA
mA
I
CE# ≧ VCC - 0.2V;
other pins at 0.2V or VCC-0.2V.
ISB1
-
4
40
1. VIH(MAX) = VCC + 2.0V for pulse width less than 6ns.
2. VIL(MIN) = VSS - 2.0V for pulse width less than 6ns.
3. Over/Undershoot specifications are characterized on engineering evaluation stage, not for mass production test.
4. Typical values are included for reference only and are not guaranteed or tested.
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
MIN.
-
-
MAX
8
10
UNIT
pF
pF
CIN
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
speed
10/12ns
Input Pulse Levels
0.2V to Vcc-0.2V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
3ns
VCC/2
CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
tRC
UNIT
LY61L20498A-10
LY61L20498A-12
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
10
-
-
-
10
10
4.5
-
12
-
-
-
12
12
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACE
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
-
-
*
*
*
*
2
0
-
3
0
-
-
-
5
-
4
-
4
-
5
2
-
2
-
(2) WRITE CYCLE
PARAMETER
SYM.
tWC
tAW
tCW
tAS
UNIT
LY61L20498A-10
LY61L20498A-12
MIN.
10
8
MAX.
MIN.
12
10
10
0
MAX.
Write Cycle Time
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
8
-
0
-
-
tWP
tWR
tDW
tDH
tOW
8
-
10
0
-
-
0
-
6
-
7
-
0
-
0
-
*
2
-
2
-
tWHZ
*
-
4
-
5
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
Dout
tAA
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
CE2
OE#
tOE
tOLZ
tOH
tOHZ
tCHZ
tCLZ
High-Z
High-Z
Dout
Data Valid
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ
.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
CE2
WE#
Dout
Din
tAS
tWP
tWR
tWHZ
TOW
High-Z
(4)
(4)
tDW
tDH
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
CE2
tAS
tWR
tCW
tWP
WE#
Dout
Din
tWHZ
High-Z
(4)
tDW
tDH
Data Valid
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
VCC for Data Retention
VDR
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
1.5
-
3.6
V
VCC = 1.5V
CE# ≧ VCC - 0.2V
or CE2 ≦ 0.2V
Data Retention Current
IDR
-
4
40
mA
Other pins at 0.2V or VCC-0.2V
See Data Retention
Waveforms (below)
Chip Disable to Data
Retention Time
Recovery Time
tCDR
tR
0
-
-
-
-
ns
ns
tRC*
tRC*
= Read Cycle Time
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
CE2 ≦ 0.2V
CE2
VIL
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
PACKAGE OUTLINE DIMENSION
54-pin 400 mil TSOP-II Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
48-ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
ORDERING INFORMATION
Package Type
Access Time
Temperature
Packing
Type
Lyontek Item No.
(Speed/ns)
10
Range(℃)
54-pin(400 mil)
Tray
LY61L20498AML-10
LY61L20498AML-10T
LY61L20498AML-10I
LY61L20498AML-10IT
LY61L20498AGL-10
LY61L20498AGL-10T
LY61L20498AGL-10I
LY61L20498AGL-10IT
0℃~70℃
Tape Reel
Tray
TSOP-II
-40℃~85℃
0℃~70℃
Tape Reel
Tray
48-ball(6mmx8mm)
TFBGA
10
Tape Reel
Tray
-40℃~85℃
Tape Reel
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
®
LY61L20498A
2048K X 8 BIT HIGH SPEED CMOS SRAM
Rev 1.0
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No. 17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
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