LY61L5128RL [LYONTEK]
512K X 8 BIT HIGH SPEED CMOS SRAM; 512K ×8位高速CMOS SRAM
| 型号： | LY61L5128RL |
| 厂家： | 
Lyontek Inc. |
| 描述： | 512K X 8 BIT HIGH SPEED CMOS SRAM |
| 文件： | 总15页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 2.0
Description
Initial Issue
Revised Package Outline Dimension(TSOP-II)
Revised ICC and ISB1
Issue Date
Sep.5.2006
Apr.12.2007
Jun.23.2007
Revised Test Condition of ISB1/IDR
Added E and I grade
Revised ABSOLUTE MAXIMUN RATINGS
Adding PKG type : 36-ball 6mm x 8mm TFBGA
Revised Test Condition of ICC
Rev. 2.1
Rev. 2.2
Mar.31.2008
Apr.17.2009
FEATURES ORDERING INFORMATION
Revised
&
Lead free and green package available to Green package
available
ABSOLUTE MAXIMUN RATINGS
Deleted TSOLDER in
ORDERING INFORMATION
Added packing type in
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
FEATURES
GENERAL DESCRIPTION
The LY61L5128 is a 4,194,304-bit low power CMOS
static random access memory organized as 524,288
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
Fast access time : 10/12/15/20/25ns
Very low power consumption:
Operating current(Normal version):
180/160/140/80/70mA(MAX.)
Standby current:
12mA(MAX. for 10/12/15ns)
5mA(MAX. for 20/25ns)
The LY61L5128 is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
100 A( (MAX. for 20/25ns LL version)
µ
Single 3.3V power supply
All inputs and outputs TTL compatible
Fully static operation
The LY61L5128 operates from a single power
supply of 3.3V and all inputs and outputs are fully
TTL compatible
Tri-state output
Data retention voltage : 2.0V (MIN.)
Green package available
Package : 32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
44-pin 400 mil TSOP-II
36-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Product
Family
Operating
Temperature
Power Dissipation
Speed
Vcc Range
Standby(ISB1,MAX.) Operating(Icc,MAX.)
0 ~ 70℃
-20 ~ 80℃
-40 ~ 85℃
0 ~ 70℃
LY61L5128
3.15/3.0 ~ 3.6V 10/12/15ns
3.15/3.0 ~ 3.6V 10/12/15ns
3.15/3.0 ~ 3.6V 10/12/15ns
12mA
12mA
12mA
5mA
180/160/140mA
180/160/140mA
180/160/140mA
80/70mA
LY61L5128(E)
LY61L5128(I)
LY61L5128
3.0 ~ 3.6V
3.0 ~ 3.6V
3.0 ~ 3.6V
3.0 ~ 3.6V
3.0 ~ 3.6V
3.0 ~ 3.6V
20/25ns
20/25ns
20/25ns
20/25ns
20/25ns
20/25ns
-20 ~ 80℃
-40 ~ 85℃
0 ~ 70℃
LY61L5128(E)
LY61L5128(I)
LY61L5128(LL)
LY61L5128(LLE)
LY61L5128(LLI)
5mA
80/70mA
5mA
80/70mA
100µA
100µA
100µA
80/70mA
-20 ~ 80℃
-40 ~ 85℃
80/70mA
80/70mA
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
DESCRIPTION
A0 - A18
Address Inputs
Vcc
Vss
DQ0 – DQ7 Data Inputs/Outputs
CE#
WE#
OE#
VCC
VSS
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
512Kx8
MEMORY ARRAY
A0-A18
DECODER
Ground
NC
No Connection
I/O DATA
CIRCUIT
DQ0-DQ7
COLUMN I/O
CE#
WE#
OE#
CONTROL
CIRCUIT
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
PIN CONFIGURATION
NC
NC
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A4
3
NC
A3
4
A5
A2
5
A6
A1
6
A7
A0
7
A8
CE#
DQ0
DQ1
Vcc
Vss
DQ2
DQ3
WE#
A18
A17
A16
A15
A14
NC
8
OE#
DQ7
DQ6
Vss
Vcc
DQ5
DQ4
A9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1 NC
A3
A6
A8
A
B
C
D
E
F
DQ4 A2 WE# A4
A7 DQ0
DQ1
DQ5
Vss
NC
A5
A10
A11
A12
A13
NC
Vcc
Vcc
Vss
DQ6
A18 A17
DQ2
DQ7 OE# CE# A16 A15 DQ3
A9 A10 A11 A12 A13 A14
G
H
NC
NC
NC
1
2
3
4
5
6
TSOP-II
TFBGA
A11
A9
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A8
3
A13
WE#
A17
A15
Vcc
A18
A16
A14
A12
A7
4
5
6
7
8
LY61L5128
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
TSOP-I/STSOP
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
SYMBOL
VT1
RATING
-0.5 to 4.6
UNIT
V
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
VT2
-0.5 to VCC+0.5
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
V
℃
Operating Temperature
TA
℃
W
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
1
IOUT
50
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
CE#
H
OE#
X
WE#
X
SUPPLY CURRENT
MODE
I/O OPERATION
High-Z
Standby
ISB1
ICC
ICC
ICC
Output Disable
Read
L
H
H
High-Z
L
L
H
DOUT
Write
L
X
L
DIN
Note: H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
TYP. *4 MAX.
UNIT
PARAMETER
10/12
15/20/25 3.0
3.15
3.3
3.3
-
-
-
3.6
3.6
VCC+0.3
0.6
V
V
V
V
Supply Voltage
VCC
*1
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
VIH
VIL
2.2
- 0.3
- 1
*2
ILI
V
V
CC ≧ VIN ≧ VSS
CC ≧ VOUT ≧ VSS,
1
A
µ
ILO
- 1
-
1
A
µ
Output Disabled
IOH = -4mA
IOL = 8mA
Output High Voltage
Output Low Voltage
VOH
VOL
2.4
-
-
-
-
-
-
-
0.4
180
160
140
80
V
V
10
12
15
20
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
Cycle time = Min.
CE# = VIL , II/O = 0mA
others at VIH or VIL
Average Operating
Power supply Current
ICC
50
45
-
0.5
20
25
70
10/12/15
20/25
20/25LL
12
Standby Power
Supply Current
CE# ≧VCC - 0.2V,
others at 0.2V or VCC - 0.2V
5*5
ISB1
100*6
A
µ
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25
5. 1mA for special request
6. 50 A for special request
µ
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
MIN.
-
-
MAX
8
10
UNIT
pF
pF
CIN
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.2V to VCC - 0.2V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -8mA/16mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
LY61L5128 LY61L5128 LY61L5128 LY61L5128 LY61L5128
PARAMETER
SYM.
UNIT
-10
-12
-15
-20
-25
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
tRC
tAA
tACE
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
10
-
-
-
10
10
5
-
-
5
5
-
12
-
-
-
12
12
6
-
-
6
6
-
15
-
-
-
15
15
7
-
-
7
7
-
20
-
-
-
20
20
8
-
-
8
8
-
25
-
-
-
25
25
9
-
-
9
9
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
*
*
*
*
2
0
-
-
3
3
0
-
-
3
4
0
-
-
3
4
0
-
-
3
4
0
-
-
3
(2) WRITE CYCLE
PARAMETER
LY61L5128 LY61L5128 LY61L5128 LY61L5128 LY61L5128
SYM.
UNIT
-10
-12
-15
-20
-25
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
10
8
8
0
8
0
6
0
2
-
-
-
-
-
-
-
-
-
-
6
12
10
10
0
9
0
7
0
3
-
-
-
-
-
-
-
-
-
-
7
15
12
12
0
10
0
8
0
4
-
-
-
-
-
-
-
-
-
-
8
20
16
16
0
11
0
9
0
5
-
-
-
-
-
-
-
-
-
-
9
25
20
20
0
12
0
10
0
6
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
tOW
tWHZ
*
*
-
10
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
Dout
tAA
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
OE#
tOE
tOLZ
tOH
tOHZ
tCHZ
tCLZ
High-Z
Dout
High-Z
Data Valid
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
tAS
tWP
tWR
WE#
Dout
Din
tWHZ
TOW
High-Z
(4)
(4)
tDW
tDH
Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
tWP
WE#
Dout
Din
tWHZ
High-Z
(4)
tDW
tDH
Data Valid
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
MIN. TYP. MAX. UNIT
VCC for Data Retention
VDR
CE# ≧ VCC - 0.2V
2.0
-
-
3.6
V
mA
mA
10/12/15
20/25
20/25LL
-
-
-
VCC = 2.0V
CE# ≧ VCC - 0.2V
others at 0.2V or VCC - 0.2V
Data Retention Current
IDR
0.5
10
1
50
A
µ
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
VDR ≧ 2.0V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
PACKAGE OUTLINE DIMENSION
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT
INCH(BASE)
MM(REF)
SYM.
A
0.047 (MAX)
1.20 (MAX)
A1
A2
±
±
0.004 0.002 0.10 0.05
±
±
0.039 0.002 1.00 0.05
0.008 + 0.002 0.20 + 0.05
b
- 0.001
0.005 (TYP)
-0.03
0.127 (TYP)
c
D
±
±
0.724 0.004 18.40 0.10
E
±
±
0.315 0.004 8.00 0.10
e
0.020 (TYP) 0.50 (TYP)
HD
L
±
±
0.787 0.008 20.00 0.20
±
±
0.0197 0.004 0.50 0.10
L1
y
Θ
±
±
0.0315 0.004 0.08 0.10
0.003 (MAX) 0.076 (MAX)
o
o
o
o
～
～
5
0
5
0
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
HD
c
L
12° (2x)
12° (2x)
32
1
17
16
"A"
y
Seating Plane
D
12° (2X)
16
17
GAUGE PLANE
0
SEATING PLANE
L
12° (2X)
L1
"A" DATAIL VIEW
1
32
UNIT
INCH(BASE)
0.049 (MAX)
MM(REF)
1.25 (MAX)
SYM.
A
A1
A2
b
±
±
0.005 0.002 0.130 0.05
±
±
0.039 0.002 1.00 0.05
±
±
0.008 0.01
0.20 0.025
c
0.005 (TYP)
0.127 (TYP)
D
±
±
0.465 0.004 11.80 0.10
E
±
±
0.315 0.004 8.00 0.10
e
0.020 (TYP) 0.50 (TYP)
HD
L
±
±
13.40 0.20.
0.528 0.008
±
±
0.0197 0.004 0.50 0.10
L1
y
Θ
±
±
0.0315 0.004 0.8 0.10
0.003 (MAX) 0.076 (MAX)
o
o
o
o
～
～
5
0
5
0
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
Ⅱ
44-pin 400mil TSOP-
Package Outline Dimension
DIMENSIONS IN MILLMETERS
DIMENSIONS IN MILS
SYMBOLS
MIN.
-
NOM.
-
MAX.
1.20
0.15
1.05
0.45
0.21
18.618
12.014
10.363
-
MIN.
NOM.
-
MAX.
A
A1
A2
b
-
47.2
5.9
41.3
17.7
8.3
733
473
408
-
0.05
0.95
0.30
0.12
18.212
11.506
9.957
-
0.10
1.00
-
2.0
37.4
11.8
4.7
717
453
392
-
3.9
39.4
-
c
-
-
D
18.415
11.760
10.160
0.800
0.50
0.805
-
725
463
400
31.5
19.7
31.7
-
E
E1
e
L
0.40
-
0.60
-
15.7
-
23.6
-
ZD
y
-
0o
0.076
6o
-
0o
3
6o
3o
3o
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
36 ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
ORDERING INFORMATION
LY61L5128 U V - WW XX Y Z
Z : Packing Type
Blank : Tube or Tray
T : Tape Reel
Y : Temperature Range
Blank : (Commercial) 0°C ~ 70°C
E : (Extended) -20°C ~ +80°C
I : (Industrial) -40°C ~ +85°C
XX : Power Type
LL : Ultra Low Power
WW : Access Time(Speed)
V : Lead Information
L : Green Package
U : Package Type
L : 32-pin 8 mm x 20 mm TSOP-I
R : 32-pin 8 mm x 13.4 mm STSOP
M : 44-pin 400 mil TSOP-II
G : 36-ball 6 mm x 8 mm TFBGA
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
13
®
LY61L5128
512K X 8 BIT HIGH SPEED CMOS SRAM
Rev. 2.2
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
14
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