LY62L12816GL-70LLET_技术文档

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

REVISION HISTORY

Revision

Rev. 1.0

Rev. 1.1

Rev. 1.2

Description

Initial Issue

Revised Package Outline Dimension(TSOP-II)

Issue Date

Jul.25.2004

Apr.12.2007

Mar.30.2009

℃

Added I_SB1/I_DRvalues when T_A= 25 and T_A= 40

Added SL grade

Deleted L grade

FEATURES ORDERING INFORMATION

Revised

&

Lead free and green package available to Green package

available

ORDERING INFORMATION

Added packing type in

Revised V_TERMto V_T1and V_T2

ABSOLUTE MAXIMUN RATINGS

Deleted T_SOLDERin

Rev. 1.3

Rev. 1.4

May.6.2010

Aug.25.2010

PACKAGE OUTLINE DIMENSION

Revised

in page 10

ORDERING INFORMATION

in page 11

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

0

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

GENERAL DESCRIPTION

FEATURES

The LY62L12816 is a 2,097,152-bit low power

CMOS static random access memory organized

as 131,072 words by 16 bits. It is fabricated

using very high performance, high reliability

CMOS technology. Its standby current is stable

within the range of operating temperature.

Fast access time : 45/55/70ns

Low power consumption:

Operating current : 23/20/18mA (TYP.)

Standby current : 1μA (TYP.) LL/SL -version

Single 2.7V ~ 3.6V power supply

All inputs and outputs TTL compatible

Fully static operation

Tri-state output

Data byte control : LB# (DQ0 ~ DQ7)

UB# (DQ8 ~ DQ15)

The LY62L12816 is well designed for low power

application, and particularly well suited for

battery back-up nonvolatile memory application.

Data retention voltage : 1.5V (MIN.)

Green package available

Package : 44-pin 400 mil TSOP-II

48-ball 6mm x 8mm TFBGA

The LY62L12816 operates from a single

power supply of 2.7V ~ 3.6V and all inputs and

outputs are fully TTL compatible

PRODUCT FAMILY

Power Dissipation

Speed

Product

Family

LY62L12816

Operating

Temperature

0 ~ 70℃

Vcc Range

Standby(ISB1,TYP.) Operating(Icc,TYP.)

2.7 ~ 3.6V

45/55/70ns

1µA

23/20/18mA

-20 ~ 80℃

-40 ~ 85℃

LY62L12816(E)

LY62L12816(I)

FUNCTIONAL BLOCK DIAGRAM

PIN DESCRIPTION

SYMBOL

DESCRIPTION

Address Inputs

Vcc

Vss

A0 - A16

DQ0 – DQ15 Data Inputs/Outputs

128Kx16

A0-A16

DECODER

CE#

WE#

OE#

LB#

UB#

V_CC

Chip Enable Input

Write Enable Input

Output Enable Input

Lower Byte Control

Upper Byte Control

Power Supply

MEMORY ARRAY

DQ0-DQ7

Lower Byte

I/O DATA

CIRCUIT

V_SS

Ground

COLUMN I/O

DQ8-DQ15

Upper Byte

CE#

WE#

OE#

LB#

CONTROL

CIRCUIT

UB#

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

1

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

PIN CONFIGURATION

A4

A3

1

2

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A5

A6

A2

3

A7

A1

4

OE#

UB#

LB#

DQ15

DQ14

DQ13

DQ12

Vss

A0

5

CE#

DQ0

DQ1

DQ2

DQ3

Vcc

Vss

DQ4

DQ5

DQ6

DQ7

WE#

A16

A15

A14

A13

A12

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

Vcc

LB# OE# A0

DQ8 UB# A3

DQ9 DQ10 A5

Vss DQ11 NC

A1

A2 NC

A

B

C

D

E

F

DQ11

DQ10

DQ9

DQ8

NC

A4 CE# DQ0

A6 DQ1 DQ2

A7 DQ3 Vcc

Vcc DQ12 NC A16 DQ4 Vss

DQ14 DQ13 A14 A15 DQ5 DQ6

DQ15 NC A12 A13 WE# DQ7

A8

A9

G

H

A10

A11

NC

1

A8

2

A9 A10 A11 NC

3

4

5

6

TSOP II

TFBGA

ABSOLUTE MAXIMUN RATINGS*

PARAMETER

SYMBOL

VT1

RATING

UNIT

V

Voltage on VCC relative to VSS

Voltage on any other pin relative to VSS

-0.5 to 4.6

VT2

-0.5 to VCC+0.5

0 to 70(C grade)

-20 to 80(E grade)

-40 to 85(I grade)

-65 to 150

V

℃

Operating Temperature

TA

℃

W

Storage Temperature

Power Dissipation

DC Output Current

TSTG

PD

1

IOUT

50

mA

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

2

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

TRUTH TABLE

I/O OPERATION

MODE

CE# OE# WE# LB# UB#

SUPPLY CURRENT

DQ0-DQ7

DQ8-DQ15

H

X

H

L

X

H

L

X

L

H

L

X

H

X

L

H

L

H

L

High – Z

D_OUT

High – Z

D_OUT

D_IN

High – Z

D_IN

High – Z

D_OUT

High – Z

D_IN

Standby

I_SB,I_SB1

I_CC,I_CC1

L

H

L

Output Disable

Read

Write

I_CC,I_CC1

L

H

L

I_CC,I_CC1

D_IN

Note: H = V_IH, L = V_IL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

SYMBOL

TEST CONDITION

MIN.

2.7

2.2

- 0.2

- 1

TYP. ^*4

3.0

MAX.

3.6

V_CC+0.3

0.6

UNIT

PARAMETER

Supply Voltage

V_CC

V

*1

Input High Voltage

Input Low Voltage

Input Leakage Current

Output Leakage

Current

V_IH

V_IL

-

*2

I_LI

V

_CC≧ V_IN≧ V_SS

_CC≧ V_OUT≧ V_SS,

Output Disabled

1

A

µ

I_LO

- 1

-

1

A

µ

Output High Voltage

Output Low Voltage

V_OHI_OH= -1mA

2.2

2.7

-

23

20

18

-

V

mA

V_OL

I_OL= 2mA

-

0.4

40

35

30

- 45

- 55

- 70

Cycle time = Min.

CE# = V_IL, I_I/O= 0mA

Other pins at V_ILor V_IH

I_CC

Average Operating

Power supply Current

Cycle time = 1 s

µ

I_CC1

I_SB

-

4

5

mA

CE# = 0.2V , I_I/O= 0mA

Other pins at 0.2V or V_CC- 0.2V

CE# = V_IH,other pins at V_ILor V_IH

-

0.3

1

0.5

10

20

LL

LLE/LLI

A

µ

A

µ

SL^*5

Standby Power

Supply Current

CE# ≧V_CC- 0.2V

Others at 0.2V or

℃

-

1

3

A

25

µ

I_SB1

SLE^*5

SLI^*5

A

40

V_CC- 0.2V

SL

SLE/SLI

-

1

10

15

A

µ

A

µ

Notes:

1. V_IH(max) = V_CC+ 3.0V for pulse width less than 10ns.

2. V_IL(min) = V_SS- 3.0V for pulse width less than 10ns.

3. Over/Undershoot specifications are characterized, not 100% tested.

4. Typical values are included for reference only and are not guaranteed or tested.

℃

Typical values are measured at V_CC= V_CC(TYP.) and T_A= 25

5. This parameter is measured at VCC = 3.0V

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

3

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

CAPACITANCE (TA = 25℃, f = 1.0MHz)

PARAMETER

Input Capacitance

Input/Output Capacitance

SYMBOL

MIN.

-

MAX

6

8

UNIT

pF

C_IN

C_I/O

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels

0.2V to V_CC- 0.2V

Input Rise and Fall Times

Input and Output Timing Reference Levels

Output Load

3ns

1.5V

C_L= 30pF + 1TTL, I_OH/I_OL= -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER

SYM.

UNIT

LY62L12816-45 LY62L12816-55 LY62L12816-70

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

Address Access Time

Chip Enable Access Time

Output Enable Access Time

Chip Enable to Output in Low-Z

Output Enable to Output in Low-Z

Chip Disable to Output in High-Z

Output Disable to Output in High-Z t_OHZ

Output Hold from Address Change

LB#, UB# Access Time

t_RC

t_AA

45

-

55

-

70

-

ns

45

25

-

55

30

-

70

35

-

t_ACE

t_OE

t_CLZ

t_OLZ

t_CHZ

-

*

10

5

-

10

-

10

5

-

10

-

10

5

-

10

-

15

-

45

20

-

20

-

55

25

-

25

-

70

30

-

t_OH

t_BA

t_BHZ

LB#, UB# to High-Z Output

LB#, UB# to Low-Z Output

*

-

10

-

10

-

10

t_BLZ

(2) WRITE CYCLE

PARAMETER

SYM.

t_WC

t_AW

t_CW

t_AS

UNIT

LY62L12816-45 LY62L12816-55 LY62L12816-70

MIN.

45

40

0

MAX.

MIN.

55

50

0

MAX.

MIN.

70

60

0

MAX.

Write Cycle Time

-

ns

Address Valid to End of Write

Chip Enable to End of Write

Address Set-up Time

Write Pulse Width

Write Recovery Time

Data to Write Time Overlap

Data Hold from End of Write Time

Output Active from End of Write

Write to Output in High-Z

LB#, UB# Valid to End of Write

-

t_WP

t_WR

t_DW

t_DH

t_OW

35

0

-

45

0

-

55

0

-

20

0

-

25

0

-

30

0

-

*

5

-

5

-

5

-

t_WHZ

*

-

35

15

-

45

20

-

60

25

-

t_BW

*These parameters are guaranteed by device characterization, but not production tested.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

4

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled) (1,2)

tRC

Address

Dout

tAA

tOH

Previous Data Valid

Data Valid

READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)

tRC

Address

tAA

CE#

tACE

LB#,UB#

tBA

OE#

tOE

tOH

tOLZ

tBLZ

tCLZ

tOHZ

tBHZ

tCHZ

High-Z

Dout

High-Z

Data Valid

Notes :

1.WE#is high for read cycle.

2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low_.

3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise t_AAis the limiting parameter.

4.t_CLZ, t_BLZ,t_OLZ, t_CHZ,t_BHZand t_OHZare specified with C_L= 5pF. Transition is measured ±500mV from steady state.

5.At any given temperature and voltage condition, t_CHZis less than t_CLZ, t_BHZis less than t_BLZ, t_OHZis less than t_OLZ.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

5

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

tWC

Address

tAW

CE#

tCW

tBW

LB#,UB#

WE#

tAS

tWP

tWR

tWHZ

TOW

High-Z

Dout

(4)

tDW

tDH

Din

Data Valid

WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)

tWC

Address

tAW

CE#

tAS

tWR

tCW

tBW

LB#,UB#

tWP

WE#

Dout

Din

tWHZ

High-Z

(4)

tDW

tDH

Data Valid

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

6

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

WRITE CYCLE 3 (LB#,UB# Controlled)

(1,2,5,6)

tWC

Address

tAW

tWR

CE#

tAS

t^CW

tBW

LB#,UB#

WE#

tWP

tWHZ

High-Z

Dout

Din

(4)

tDW

tDH

Data Valid

Notes :

1.WE#,CE#, LB#, UB# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.

3.During a WE# controlled write cycle with OE# low, t_WPmust be greater than t_WHZ+ t_DWto allow the drivers to turn off and data to be

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance

state.

6.t_OWand t_WHZare specified with C_L= 5pF. Transition is measured ±500mV from steady state.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

7

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

DATA RETENTION CHARACTERISTICS

PARAMETER

V_CCfor Data Retention

SYMBOL

TEST CONDITION

CE# ≧ V_CC- 0.2V

MIN.

1.5

-

TYP. MAX. UNIT

V_DR

-

3.6

5

10

V

LL

0.5

A

µ

LLE/LLI

SL

A

V_CC= 1.5V

℃

-

0.5

3

25

40

A

µ

Data Retention Current

I_DR

CE# ≧ V_CC- 0.2V

Others at 0.2V or V_CC-0.2V

SLE

SLI

SL

℃

A

-

0.5

5

10

A

µ

A

µ

SLE/SLI

Chip Disable to Data

Retention Time

Recovery Time

See Data Retention

Waveforms (below)

t_CDR

t_R

0

-

ns

t_RC

*

t_{RC = Read Cycle Time}

*

DATA RETENTION WAVEFORM

Low Vcc Data Retention Waveform (1) (CE# controlled)

VDR ≧ 1.5V

Vcc(min.)

Vcc

Vcc(min.)

tCDR

tR

V^IH

CE# ≧ Vcc-0.2V

VIH

CE#

Low Vcc Data Retention Waveform (2) (LB#, UB# controlled)

VDR ≧ 1.5V

Vcc(min.)

Vcc

Vcc(min.)

tCDR

tR

V^IH

LB#,UB# ≧ Vcc-0.2V

VIH

LB#,UB#

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

8

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

PACKAGE OUTLINE DIMENSION

Ⅱ

44-pin 400mil TSOP-

Package Outline Dimension

DIMENSIONS IN MILLMETERS

DIMENSIONS IN MILS

SYMBOLS

MIN.

-

NOM.

-

MAX.

1.20

0.15

1.05

0.45

0.21

18.618

12.014

10.363

-

MIN.

NOM.

-

MAX.

A

A1

A2

b

-

47.2

5.9

41.3

17.7

8.3

733

473

408

-

0.05

0.95

0.30

0.12

18.212

11.506

9.957

-

0.10

1.00

-

2.0

37.4

11.8

4.7

717

453

392

-

3.9

39.4

-

c

-

D

18.415

11.760

10.160

0.800

0.50

0.805

-

725

463

400

31.5

19.7

31.7

-

E

E1

e

L

0.40

-

0.60

-

15.7

-

23.6

-

ZD

y

-

0^o

0.076

6^o

-

0^o

3

6^o

3^o

Θ

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

9

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

48-ball 6mm × 8mm TFBGA Package Outline Dimension

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

10

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

ORDERING INFORMATION

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

11

®

LY62L12816

128K X 16 BIT LOW POWER CMOS SRAM

Rev. 1.4

THIS PAGE IS LEFT BLANK INTENTIONALLY.

Lyontek Inc. ^{reserves the rights to change the specifications and products without notice.}

5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.

TEL: 886-3-6668838

FAX: 886-3-6668836

12


型号：	LY62L12816GL-70LLET
厂家：	Lyontek Inc.
描述：	128K X 16 BIT LOW POWER CMOS SRAM 静态存储器
文件：	总13页 (文件大小：275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LY62L12816GL-70LLET [LYONTEK]

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