LY62L25616GL-55SLI [LYONTEK]
Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, TFBGA-48;型号: | LY62L25616GL-55SLI |
厂家: | Lyontek Inc. |
描述: | Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, TFBGA-48 静态存储器 内存集成电路 |
文件: | 总15页 (文件大小:687K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
REVISION HISTORY
Revision
Rev. 1.0
Rev. 2.0
Rev. 2.1
Rev. 2.2
Description
Initial Issue
Revised ISB(max) : 0.5mA => 1.25mA
Revised Package Outline Dimension(TSOP-II)
Deleted L Spec.
Issue Date
Jul.25.2004
May.11.2006
Apr.12.2007
Nov.8.2007
Added SL Spec.
Revised Test Condition of ICC/ISB1/IDR
Revised VTERM to VT1 and VT2
Revised IDR
Rev. 2.3
Rev. 2.4
Mar.21.2008
Mar.30.2009
℃
℃
Added ISB1/IDR values when TA = 25 and TA = 40
FEATURES ORDERING INFORMATION
Revised
&
Lead free and green package available to Green package
available
ORDERING INFORMATION
Added packing type in
ABSOLUTE MAXIMUN RATINGS
Deleted TSOLDER in
Rev. 2.5
Rev. 2.6
Rev. 2.7
May.6.2010
Aug.30.2010
Jan.7.2016
PACKAGE OUTLINE DIMENSION
Revised
Revised
in page 10
ORDERING INFORMATION
in page 11
TIMING WAVEFORMS
Revised Notes of READ CYCLE of
in page 5
Rev. 2.8
Rev. 2.9
May.20.2016
Jun.29.2016
ORDERING INFORMATION
Corrected
Typo.
Deleted WRITE CYCLE Notes :
1.WE#,CE#, LB#, UB# must be high during all address transitions.
in page 7
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
FEATURES
GENERAL DESCRIPTION
The LY62L25616 is a 4,194,304-bit low power CMOS
static random access memory organized as 262,144
words by 16 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of operating
temperature.
Fast access time : 45/55/70ns
Low power consumption:
Operating current : 40/30/20mA (TYP.)
Standby current : 2A (TYP.) LL-version
1A (TYP.) SL-version
Single 2.7V ~ 3.6V power supply
All inputs and outputs TTL compatible
Fully static operation
Tri-state output
Data byte control : LB# (DQ0 ~ DQ7)
UB# (DQ8 ~ DQ15)
Data retention voltage : 1.5V (MIN.)
Green package available
Package : 44-pin 400 mil TSOP II
48-ball 6mm x 8mm TFBGA
The LY62L25616 is well designed for low power
application, and particularly well suited for battery
back-up nonvolatile memory application.
The LY62L25616 operates from a single power
supply of 2.7V ~ 3.6V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Power Dissipation
Speed
Product
Family
Operating
Temperature
Vcc Range
Standby(ISB1,TYP.) Operating(Icc,TYP.)
0 ~ 70℃
-20 ~ 80℃
-40 ~ 85℃
LY62L25616
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
45/55/70ns
45/55/70ns
45/55/70ns
2µA(LL)/1µA(SL)
2µA(LL)/1µA(SL)
2µA(LL)/1µA(SL)
40/30/20mA
40/30/20mA
40/30/20mA
LY62L25616(E)
LY62L25616(I)
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL
A0 - A17
DESCRIPTION
Address Inputs
Vcc
Vss
DQ0 – DQ15 Data Inputs/Outputs
CE#
WE#
OE#
LB#
UB#
VCC
Chip Enable Input
Write Enable Input
Output Enable Input
Lower Byte Control
Upper Byte Control
Power Supply
256Kx16
MEMORY ARRAY
A0-A17
DECODER
VSS
Ground
DQ0-DQ7
Lower Byte
I/O DATA
CIRCUIT
COLUMN I/O
DQ8-DQ15
Upper Byte
CE#
WE#
OE#
LB#
CONTROL
CIRCUIT
UB#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
PIN CONFIGURATION
A4
A3
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A2
3
A7
A1
4
OE#
UB#
LB#
DQ15
DQ14
DQ13
DQ12
Vss
A0
5
CE#
DQ0
DQ1
DQ2
DQ3
Vcc
Vss
DQ4
DQ5
DQ6
DQ7
WE#
A17
A16
A15
A14
A13
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Vcc
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
TSOP II
LB# OE# A0
DQ8 UB# A3
DQ9 DQ10 A5
A1
A2
NC
A
B
C
D
E
F
A4 CE# DQ0
A6 DQ1 DQ2
Vss DQ11 A17 A7 DQ3 Vcc
Vcc DQ12 NC A16 DQ4 Vss
DQ14 DQ13 A14 A15 DQ5 DQ6
DQ15 NC A12 A13 WE# DQ7
G
H
NC
A8
A9 A10 A11 NC
TFBGA(Top View)
1
2
3
4
5
6
TFBGA(See through with Top View)
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
SYMBOL
VT1
RATING
-0.5 to 4.6
UNIT
V
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
VT2
-0.5 to VCC+0.5
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
V
℃
Operating Temperature
TA
℃
W
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
1
IOUT
50
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
I/O OPERATION
MODE
Standby
CE# OE# WE# LB# UB#
SUPPLY CURRENT
DQ0-DQ7
DQ8-DQ15
H
X
X
X
X
X
X
H
X
H
High – Z
High – Z
High – Z
High – Z
ISB,ISB1
ICC,ICC1
ICC,ICC1
L
L
L
L
L
L
L
L
H
H
L
L
L
X
X
X
H
H
H
H
H
L
L
X
L
H
L
L
H
L
X
L
H
L
L
H
L
High – Z
High – Z
DOUT
High – Z
DOUT
High – Z
High – Z
High – Z
DOUT
Output Disable
Read
DOUT
DIN
High – Z
DIN
High – Z
DIN
Write
L
L
ICC,ICC1
L
DIN
Note: H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
2.7
2.2
- 0.2
- 1
TYP. *4
3.0
MAX.
3.6
VCC+0.3
0.6
UNIT
PARAMETER
Supply Voltage
VCC
V
V
V
*1
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage
Current
VIH
VIL
-
-
-
*2
ILI
V
V
CC ≧ VIN ≧ VSS
CC ≧ VOUT ≧ VSS,
Output Disabled
IOL = 2mA
Cycle time = Min.
CE# = VIL , II/O = 0mA
Other pins at VIL or VIH
1
A
µ
ILO
- 1
-
1
A
µ
Output High Voltage
Output Low Voltage
VOH IOH = -1mA
VOL
2.2
2.7
-
40
30
20
-
V
V
mA
mA
mA
-
-
-
-
0.4
50
40
30
- 45
- 55
- 70
ICC
Average Operating
Power supply Current
Cycle time = 1 s
µ
ICC1
ISB
-
4
5
mA
CE# = 0.2V , II/O = 0mA
Other pins at 0.2V or VCC - 0.2V
CE# = VIH, other pins at VIL or VIH
-
-
-
0.3
2
2
1.25
15
20
mA
LL
LLE/LLI
A
A
µ
µ
SL*5
Standby Power
Supply Current
CE# ≧VCC - 0.2V
Others at 0.2V or
VCC - 0.2V
℃
℃
-
-
1
1
3
3
A
A
25
µ
µ
ISB1
SLE*5
SLI*5
40
SL
SLE/SLI
-
-
1
1
10
12
A
A
µ
µ
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
℃
Typical values are measured at VCC = VCC(TYP.) and TA = 25
5. This parameter is measured at VCC = 3.0V
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
MIN.
-
-
MAX
6
8
UNIT
pF
pF
CIN
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0.2V to VCC - 0.2V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
SYM.
tRC
UNIT
LY62L25616-45 LY62L25616-55 LY62L25616-70
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
LB#, UB# Access Time
45
-
-
-
55
-
-
-
70
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
45
45
25
-
55
55
30
-
70
70
35
-
tACE
tOE
tCLZ
tOLZ
tCHZ
-
-
-
*
*
*
10
5
-
-
10
-
10
5
-
-
10
-
10
5
-
-
10
-
-
-
-
15
15
-
45
20
-
20
20
-
55
25
-
25
25
-
70
30
-
tOHZ
tOH
tBA
*
LB#, UB# to High-Z Output
LB#, UB# to Low-Z Output
tBHZ
*
-
10
-
10
-
10
tBLZ
*
(2) WRITE CYCLE
PARAMETER
SYM.
tWC
tAW
tCW
tAS
UNIT
LY62L25616-45 LY62L25616-55 LY62L25616-70
MIN.
45
40
40
0
MAX.
MIN.
55
50
50
0
MAX.
MIN.
70
60
60
0
MAX.
Write Cycle Time
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
LB#, UB# Valid to End of Write
-
-
-
tWP
tWR
tDW
tDH
tOW
35
0
-
-
45
0
-
-
55
0
-
-
20
0
-
-
25
0
-
-
30
0
-
-
*
5
-
5
-
5
-
tWHZ
*
-
35
15
-
-
45
20
-
-
60
25
-
tBW
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
Dout
tAA
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
LB#,UB#
tBA
OE#
*6
tOE
tOH
tOLZ
tBLZ
tCLZ
tOHZ
tBHZ
tCHZ
High-Z
Dout
High-Z
Data Valid
Notes :
1.WE#is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low, LB# or UB# = low.
3.Address must be valid prior to or coincident with CE# = low, LB# or UB# = low transition; otherwise tAA is the limiting parameter.
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tBHZ is less than tBLZ, tOHZ is less than tOLZ.
6.CE# = low, LB# or UB# = low transition must be at least 25ns prior to OE# = low transition; otherwise tBA is the limiting parameter.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
WRITE CYCLE 1 (WE# Controlled) (1,2,4,5)
tWC
Address
tAW
CE#
tCW
tBW
LB#,UB#
WE#
tAS
tWP
tWR
tOW
tWHZ
High-Z
(4)
Dout
(4)
tDW
tDH
Din
Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,4,5)
tWC
Address
tAW
CE#
tAS
tWR
tCW
tBW
LB#,UB#
tWP
WE#
Dout
Din
tWHZ
High-Z
(4)
tDW
tDH
Data Valid
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
WRITE CYCLE 3 (LB#,UB# Controlled)
(1,4,5)
tWC
Address
tAW
tWR
CE#
tAS
tCW
tBW
LB#,UB#
WE#
tWP
tWHZ
High-Z
Dout
Din
(4)
tDW
tDH
Data Valid
Notes :
1.A write occurs during the overlap of a low CE#, low WE#, LB# or UB# = low.
2.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed
on the bus.
3.During this period, I/O pins are in the output state, and input signals must not be applied.
4.If the CE#, LB#, UB# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
5.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITION
CE# ≧ VCC - 0.2V
MIN.
1.5
TYP.
-
MAX.
3.6
UNIT
V
V
for Data Retention VDR
CC
LL
LLE/LLI
-
-
1.0
1.0
12
16
A
A
µ
µ
VCC = 1.5V
CE# ≧ VCC - 0.2V
Others at 0.2V or VCC-0.2V
SL
SLE
SLI
℃
℃
-
-
0.5
0.5
2.5
2.5
25
A
A
µ
µ
Data Retention Current
IDR
40
SL
SLE/SLI
-
-
0.5
0.5
8
10
A
A
µ
µ
Chip Disable to Data
Retention Time
Recovery Time
See Data Retention
Waveforms (below)
tCDR
tR
0
-
-
-
-
ns
ns
tRC
*
tRC = Read Cycle Time
*
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
CE# ≧ Vcc-0.2V
VIH
CE#
Low Vcc Data Retention Waveform (2) (LB#, UB# controlled)
VDR ≧ 1.5V
Vcc(min.)
Vcc
Vcc(min.)
tCDR
tR
VIH
LB#,UB# ≧ Vcc-0.2V
VIH
LB#,UB#
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
PACKAGE OUTLINE DIMENSION
Ⅱ
44-pin 400mil TSOP
Package Outline Dimension
DIMENSIONS IN MILLMETERS
DIMENSIONS IN MILS
SYMBOLS
MIN.
-
NOM.
-
MAX.
1.20
0.15
1.05
0.45
0.21
18.618
12.014
10.363
-
MIN.
NOM.
-
MAX.
A
A1
A2
b
-
47.2
5.9
41.3
17.7
8.3
733
473
408
-
0.05
0.95
0.30
0.12
18.212
11.506
9.957
-
0.10
1.00
-
2.0
37.4
11.8
4.7
717
453
392
-
3.9
39.4
-
c
-
-
D
18.415
11.760
10.160
0.800
0.50
0.805
-
725
463
400
31.5
19.7
31.7
-
E
E1
e
L
0.40
-
0.60
-
15.7
-
23.6
-
ZD
y
Θ
-
0.076
6o
-
3
0o
3o
0o
3o
6o
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
48-ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
ORDERING INFORMATION
Package Type Access Time
(Speed)(ns)
Power Type
Temperature
Range(℃)
0℃~70℃
Packing
Type
Lyontek Item No.
44Pin(400mil)
TSOP II
45
55
70
Tray
LY62L25616ML-45SL
LY62L25616ML-45SLT
LY62L25616ML-45SLE
LY62L25616ML-45SLET
LY62L25616ML-45SLI
LY62L25616ML-45SLIT
LY62L25616ML-45LL
LY62L25616ML-45LLT
LY62L25616ML-45LLE
LY62L25616ML-45LLET
LY62L25616ML-45LLI
LY62L25616ML-45LLIT
LY62L25616ML-55SL
LY62L25616ML-55SLT
LY62L25616ML-55SLE
LY62L25616ML-55SLET
LY62L25616ML-55SLI
LY62L25616ML-55SLIT
LY62L25616ML-55LL
LY62L25616ML-55LLT
LY62L25616ML-55LLE
LY62L25616ML-55LLET
LY62L25616ML-55LLI
LY62L25616ML-55LLIT
LY62L25616ML-70SL
LY62L25616ML-70SLT
LY62L25616ML-70SLE
LY62L25616ML-70SLET
LY62L25616ML-70SLI
LY62L25616ML-70SLIT
LY62L25616ML-70LL
LY62L25616ML-70LLT
LY62L25616ML-70LLE
LY62L25616ML-70LLET
LY62L25616ML-70LLI
LY62L25616ML-70LLIT
Special Ultra
Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Ultra Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Special Ultra
Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Ultra Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Special Ultra
Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Ultra Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
Tape Reel
Tray
Tape Reel
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
ORDERING INFORMATION
Package Type Access Time
(Speed)(ns)
Power Type
Temperature
Packing
Type
Lyontek Item No.
Range(℃)
0℃~70℃
48-ball
45
55
70
Tray
LY62L25616GL-45SL
LY62L25616GL-45SLT
LY62L25616GL-45SLE
LY62L25616GL-45SLET
LY62L25616GL-45SLI
LY62L25616GL-45SLIT
LY62L25616GL-45LL
LY62L25616GL-45LLT
LY62L25616GL-45LLE
LY62L25616GL-45LLET
LY62L25616GL-45LLI
LY62L25616GL-45LLIT
LY62L25616GL-55SL
LY62L25616GL-55SLT
LY62L25616GL-55SLE
LY62L25616GL-55SLET
LY62L25616GL-55SLI
LY62L25616GL-55SLIT
LY62L25616GL-55LL
LY62L25616GL-55LLT
LY62L25616GL-55LLE
LY62L25616GL-55LLET
LY62L25616GL-55LLI
LY62L25616GL-55LLIT
LY62L25616GL-70SL
LY62L25616GL-70SLT
LY62L25616GL-70SLE
LY62L25616GL-70SLET
LY62L25616GL-70SLI
LY62L25616GL-70SLIT
LY62L25616GL-70LL
LY62L25616GL-70LLT
LY62L25616GL-70LLE
LY62L25616GL-70LLET
LY62L25616GL-70LLI
LY62L25616GL-70LLIT
Special Ultra
Low Power
(6mmx8mm)
TFBGA
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Ultra Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Special Ultra
Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Ultra Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Special Ultra
Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
0℃~70℃
Tape Reel
Tray
Tape Reel
Tray
Ultra Low Power
Tape Reel
Tray
-20℃~80℃
-40℃~85℃
Tape Reel
Tray
Tape Reel
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
13
LY62L25616
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 2.9
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
2F, No.17, Industry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
14
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